From fc8c4c059c23347d932ae3fd2ab295d1ccdb7d58 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 29 Nov 2019 15:51:37 +0200 Subject: ARM: at91: Kconfig: add sam9x60 pll config flag Add SAM9X60's pll config flag. It was first used in commit a436c2a447e5 ("clk: at91: add sam9x60 PLL driver"). Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1575035505-6310-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index af41725fcc72..262b550d7329 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -154,6 +154,9 @@ config HAVE_AT91_AUDIO_PLL config HAVE_AT91_I2S_MUX_CLK bool +config HAVE_AT91_SAM9X60_PLL + bool + config SOC_SAM_V4_V5 bool -- cgit v1.2.3-59-g8ed1b From fe7ff55d7918ce264b3edb3965a92291eb1475a4 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 29 Nov 2019 15:51:38 +0200 Subject: ARM: at91: Kconfig: add config flag for SAM9X60 SoC Add config flag for SAM9X60 SoC. Signed-off-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/1575035505-6310-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/Kconfig | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 262b550d7329..7979420bd48b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -105,11 +105,28 @@ config SOC_AT91SAM9 AT91SAM9X35 AT91SAM9XE +config SOC_SAM9X60 + bool "SAM9X60" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select ATMEL_SDRAMC + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X60 SoC + comment "Clocksource driver selection" config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -119,7 +136,7 @@ config ATMEL_CLOCKSOURCE_PIT config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a -- cgit v1.2.3-59-g8ed1b From eb0df9b7fb022af73fb5002f3506a5b1a92df1ae Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 29 Nov 2019 15:51:39 +0200 Subject: ARM: at91: pm: move SAM9X60's PM under its own SoC config flag Move SAM9X60's PM part under SoC config flag. This allows the building of SAM9X60 platform withouth depending on CONFIG_SOC_AT91SAM9 flag, allowing us to select only necessary config flags for SAM9X60. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1575035505-6310-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/at91sam9.c | 18 ------------------ arch/arm/mach-at91/pm.c | 2 +- arch/arm/mach-at91/sam9x60.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 19 deletions(-) create mode 100644 arch/arm/mach-at91/sam9x60.c (limited to 'arch') diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index de64301dcff2..f565490f1b70 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -6,6 +6,7 @@ # CPU-specific support obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o +obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o obj-$(CONFIG_SOC_SAMA5) += sama5.o obj-$(CONFIG_SOC_SAMV7) += samv7.o diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c index bf629c90c758..7e572189a5eb 100644 --- a/arch/arm/mach-at91/at91sam9.c +++ b/arch/arm/mach-at91/at91sam9.c @@ -31,21 +31,3 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9") .init_machine = at91sam9_init, .dt_compat = at91_dt_board_compat, MACHINE_END - -static void __init sam9x60_init(void) -{ - of_platform_default_populate(NULL, NULL, NULL); - - sam9x60_pm_init(); -} - -static const char *const sam9x60_dt_board_compat[] __initconst = { - "microchip,sam9x60", - NULL -}; - -DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60") - /* Maintainer: Microchip */ - .init_machine = sam9x60_init, - .dt_compat = sam9x60_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index d5af6aedc02c..56a6a49b19e2 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -805,7 +805,7 @@ void __init at91rm9200_pm_init(void) void __init sam9x60_pm_init(void) { - if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) + if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) return; at91_pm_modes_init(); diff --git a/arch/arm/mach-at91/sam9x60.c b/arch/arm/mach-at91/sam9x60.c new file mode 100644 index 000000000000..d8c739d25458 --- /dev/null +++ b/arch/arm/mach-at91/sam9x60.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X60. + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + */ + +#include +#include + +#include +#include + +#include "generic.h" + +static void __init sam9x60_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + sam9x60_pm_init(); +} + +static const char *const sam9x60_dt_board_compat[] __initconst = { + "microchip,sam9x60", + NULL +}; + +DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60") + /* Maintainer: Microchip */ + .init_machine = sam9x60_init, + .dt_compat = sam9x60_dt_board_compat, +MACHINE_END -- cgit v1.2.3-59-g8ed1b From 80f58695158eb252889938822b2951c060816aaa Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 29 Nov 2019 15:51:43 +0200 Subject: ARM: debug-ll: select DEBUG_AT91_RM9200_DBGU for sam9x60 Select DEBUG_AT91_RM9200_DBGU for SAM9X60 SoC. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1575035505-6310-8-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/Kconfig.debug | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 8bcbd0cd739b..b70d7debf5ca 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -147,14 +147,14 @@ choice 0x80024000 | 0xf0024000 | UART9 config DEBUG_AT91_RM9200_DBGU - bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU" + bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU" select DEBUG_AT91_UART - depends on SOC_AT91RM9200 || SOC_AT91SAM9 + depends on SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 help Say Y here if you want kernel low-level debugging support on the DBGU port of: at91rm9200, at91sam9260, at91sam9g20, at91sam9261, - at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5 + at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5, sam9x60 config DEBUG_AT91_SAM9263_DBGU bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU" -- cgit v1.2.3-59-g8ed1b From b3082f1bf8a604c9a0f483b5d6060d7255c2a51b Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 4 Nov 2019 15:35:31 +0800 Subject: ARM: imx: Add i.MX7ULP SoC serial number support i.MX7ULP's unique ID layout in OCOTP is different from other i.MX6/7 SoCs as below: OCOTP layout unique ID 0x4b0 bit[15:0] bit[15:0] 0x4c0 bit[15:0] bit[31:16] 0x4d0 bit[15:0] bit[47:32] 0x4e0 bit[15:0] bit[63:48] Add support for reading serial number from OCOTP on i.MX7ULP. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 871f98342d50..06f8d64b65af 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -15,6 +15,11 @@ #define OCOTP_UID_H 0x420 #define OCOTP_UID_L 0x410 +#define OCOTP_ULP_UID_1 0x4b0 +#define OCOTP_ULP_UID_2 0x4c0 +#define OCOTP_ULP_UID_3 0x4d0 +#define OCOTP_ULP_UID_4 0x4e0 + unsigned int __mxc_cpu_type; static unsigned int imx_soc_revision; @@ -164,6 +169,7 @@ struct device * __init imx_soc_device_init(void) soc_id = "i.MX7D"; break; case MXC_CPU_IMX7ULP: + ocotp_compat = "fsl,imx7ulp-ocotp"; soc_id = "i.MX7ULP"; break; default: @@ -178,11 +184,25 @@ struct device * __init imx_soc_device_init(void) } if (!IS_ERR_OR_NULL(ocotp)) { - regmap_read(ocotp, OCOTP_UID_H, &val); - soc_uid = val; - regmap_read(ocotp, OCOTP_UID_L, &val); - soc_uid <<= 32; - soc_uid |= val; + if (__mxc_cpu_type == MXC_CPU_IMX7ULP) { + regmap_read(ocotp, OCOTP_ULP_UID_4, &val); + soc_uid = val & 0xffff; + regmap_read(ocotp, OCOTP_ULP_UID_3, &val); + soc_uid <<= 16; + soc_uid |= val & 0xffff; + regmap_read(ocotp, OCOTP_ULP_UID_2, &val); + soc_uid <<= 16; + soc_uid |= val & 0xffff; + regmap_read(ocotp, OCOTP_ULP_UID_1, &val); + soc_uid <<= 16; + soc_uid |= val & 0xffff; + } else { + regmap_read(ocotp, OCOTP_UID_H, &val); + soc_uid = val; + regmap_read(ocotp, OCOTP_UID_L, &val); + soc_uid <<= 32; + soc_uid |= val; + } } soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", -- cgit v1.2.3-59-g8ed1b From 4562fa4c86c92a2df635fe0697c9e06379738741 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 11 Dec 2019 10:53:36 +0800 Subject: ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D ARM_ERRATA_814220 has below description: The v7 ARM states that all cache and branch predictor maintenance operations that do not specify an address execute, relative to each other, in program order. However, because of this erratum, an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable ARM_ERRATA_814220 for proper workaround. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 593bf1519608..4326c8f53462 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -520,6 +520,7 @@ config SOC_IMX6UL bool "i.MX6 UltraLite support" select PINCTRL_IMX6UL select SOC_IMX6 + select ARM_ERRATA_814220 help This enables support for Freescale i.MX6 UltraLite processor. @@ -556,6 +557,7 @@ config SOC_IMX7D select PINCTRL_IMX7D select SOC_IMX7D_CA7 if ARCH_MULTI_V7 select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M + select ARM_ERRATA_814220 help This enables support for Freescale i.MX7 Dual processor. -- cgit v1.2.3-59-g8ed1b From da4f2b4ccc49ab1f9e7ca7f32c1a3272806f48ce Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 11 Dec 2019 14:25:58 -0600 Subject: ARM: OMAP2+: am43xx: Add lcdc clockdomain As described in AM437x TRM, spruhl7h, Revised January 2018, there is an LCDC clockdomain present in the PER power domain. Although it is entirely unused on AM437x, it should be defined along with the other clockdomains so it can be shut off by Linux as there are no users. Reported-by: Munan Xu Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomains43xx_data.c | 10 ++++++++++ arch/arm/mach-omap2/prcm43xx.h | 1 + 2 files changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c index 751708d727af..c96a2b1efbad 100644 --- a/arch/arm/mach-omap2/clockdomains43xx_data.c +++ b/arch/arm/mach-omap2/clockdomains43xx_data.c @@ -84,6 +84,15 @@ static struct clockdomain l3s_tsc_43xx_clkdm = { .flags = CLKDM_CAN_SWSUP, }; +static struct clockdomain lcdc_43xx_clkdm = { + .name = "lcdc_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .prcm_partition = AM43XX_CM_PARTITION, + .cm_inst = AM43XX_CM_PER_INST, + .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS, + .flags = CLKDM_CAN_SWSUP, +}; + static struct clockdomain dss_43xx_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "per_pwrdm" }, @@ -173,6 +182,7 @@ static struct clockdomain *clockdomains_am43xx[] __initdata = { &pruss_ocp_43xx_clkdm, &ocpwp_l3_43xx_clkdm, &l3s_tsc_43xx_clkdm, + &lcdc_43xx_clkdm, &dss_43xx_clkdm, &l3_aon_43xx_clkdm, &emif_43xx_clkdm, diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index e2ad14e77064..7078a61c1d3f 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -68,6 +68,7 @@ #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 +#define AM43XX_CM_PER_LCDC_CDOFFS 0x0800 #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 -- cgit v1.2.3-59-g8ed1b From 8de44fb70659a5bc0c53a443e6129ea1bf00fd8b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Dec 2019 15:05:37 +0200 Subject: ARM: OMAP2+: pdata-quirks: add PRM data for reset support The parent clockdomain for reset must be in force wakeup mode, otherwise the reset may never complete. Add pdata quirks for this purpose for PRM driver. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index ca52271de5a8..d8260e61ef92 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "clockdomain.h" #include "common.h" @@ -408,6 +409,12 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void)) pcs_pdata.rearm = rearm; } +static struct ti_prm_platform_data ti_prm_pdata = { + .clkdm_deny_idle = clkdm_deny_idle, + .clkdm_allow_idle = clkdm_allow_idle, + .clkdm_lookup = clkdm_lookup, +}; + /* * GPIOs for TWL are initialized by the I2C bus and need custom * handing until DSS has device tree bindings. @@ -510,6 +517,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { /* Common auxdata */ OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), + OF_DEV_AUXDATA("ti,omap-prm-inst", 0, NULL, &ti_prm_pdata), { /* sentinel */ }, }; -- cgit v1.2.3-59-g8ed1b From e4c4b540e1e6c21ff8b987e92b2bd170ee006a94 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Dec 2019 15:05:38 +0200 Subject: ARM: OMAP4+: remove pdata quirks for omap4+ iommus IOMMU driver will be using ti-sysc bus driver for power management control going forward, and the pdata quirks are not needed for anything anymore. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index d8260e61ef92..88ca7f82510a 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -261,16 +261,6 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) -static struct iommu_platform_data omap4_iommu_pdata = { - .reset_name = "mmu_cache", - .assert_reset = omap_device_assert_hardreset, - .deassert_reset = omap_device_deassert_hardreset, - .device_enable = omap_device_enable, - .device_idle = omap_device_idle, -}; -#endif - #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) static struct wkup_m3_platform_data wkup_m3_data = { .reset_name = "wkup_m3", @@ -495,10 +485,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { &wkup_m3_data), #endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) - OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", - &omap4_iommu_pdata), - OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", - &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000, "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]), OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000, -- cgit v1.2.3-59-g8ed1b From 2f14101a1d760db72393910d481fbf7768c44530 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 12 Dec 2019 15:05:39 +0200 Subject: ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879 Errata Title: i879: DSP MStandby requires CD_EMU in SW_WKUP Description: The DSP requires the internal emulation clock to be actively toggling in order to successfully enter a low power mode via execution of the IDLE instruction and PRCM MStandby/Idle handshake. This assumes that other prerequisites and software sequence are followed. Workaround: The emulation clock to the DSP is free-running anytime CCS is connected via JTAG debugger to the DSP subsystem or when the CD_EMU clock domain is set in SW_WKUP mode. The CD_EMU domain can be set in SW_WKUP mode via the CM_EMU_CLKSTCTRL [1:0]CLKTRCTRL field. Implementation: This patch implements this workaround by denying the HW_AUTO mode for the EMU clockdomain during the power-up of any DSP processor and re-enabling the HW_AUTO mode during the shutdown of the last DSP processor (actually done during the enabling and disabling of the respective DSP MDMA MMUs). Reference counting has to be used to manage the independent sequencing between the multiple DSP processors. This switching is done at runtime rather than a static clockdomain flags value to meet the target power domain state for the EMU power domain during suspend. Note that the DSP MStandby behavior is not consistent across all boards prior to this fix. Please see commit 45f871eec6c0 ("ARM: OMAP2+: Extend DRA7 IPU1 MMU pdata quirks to DSP MDMA MMUs") for details. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-iommu.c | 43 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index f1a6ece8108e..78247e6f4a72 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -11,14 +11,43 @@ #include "omap_hwmod.h" #include "omap_device.h" +#include "clockdomain.h" #include "powerdomain.h" +static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, + bool enable) +{ + static struct clockdomain *emu_clkdm; + static DEFINE_SPINLOCK(emu_lock); + static atomic_t count; + struct device_node *np = pdev->dev.of_node; + + if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) + return; + + if (!emu_clkdm) { + emu_clkdm = clkdm_lookup("emu_clkdm"); + if (WARN_ON_ONCE(!emu_clkdm)) + return; + } + + spin_lock(&emu_lock); + + if (enable && (atomic_inc_return(&count) == 1)) + clkdm_deny_idle(emu_clkdm); + else if (!enable && (atomic_dec_return(&count) == 0)) + clkdm_allow_idle(emu_clkdm); + + spin_unlock(&emu_lock); +} + int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, u8 *pwrst) { struct powerdomain *pwrdm; struct omap_device *od; u8 next_pwrst; + int ret = 0; od = to_omap_device(pdev); if (!od) @@ -31,13 +60,21 @@ int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, if (!pwrdm) return -EINVAL; - if (request) + if (request) { *pwrst = pwrdm_read_next_pwrst(pwrdm); + omap_iommu_dra7_emu_swsup_config(pdev, true); + } if (*pwrst > PWRDM_POWER_RET) - return 0; + goto out; next_pwrst = request ? PWRDM_POWER_ON : *pwrst; - return pwrdm_set_next_pwrst(pwrdm, next_pwrst); + ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst); + +out: + if (!request) + omap_iommu_dra7_emu_swsup_config(pdev, false); + + return ret; } -- cgit v1.2.3-59-g8ed1b From 4ea3711aece423a160c5b341ba531ccc81c009d1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Dec 2019 15:05:40 +0200 Subject: ARM: OMAP2+: omap-iommu.c conversion to ti-sysc Convert omap2 iommu platform code to use ti-sysc instead of legacy omap-device / hwmod interfaces. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-iommu.c | 99 ++++++++++++++++++++++++++++++++-------- 1 file changed, 80 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 78247e6f4a72..54aff33e55e6 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -8,19 +8,27 @@ #include #include +#include +#include -#include "omap_hwmod.h" -#include "omap_device.h" #include "clockdomain.h" #include "powerdomain.h" +struct pwrdm_link { + struct device *dev; + struct powerdomain *pwrdm; + struct list_head node; +}; + +static DEFINE_SPINLOCK(iommu_lock); +static struct clockdomain *emu_clkdm; +static atomic_t emu_count; + static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, bool enable) { - static struct clockdomain *emu_clkdm; - static DEFINE_SPINLOCK(emu_lock); - static atomic_t count; struct device_node *np = pdev->dev.of_node; + unsigned long flags; if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) return; @@ -31,34 +39,87 @@ static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, return; } - spin_lock(&emu_lock); + spin_lock_irqsave(&iommu_lock, flags); - if (enable && (atomic_inc_return(&count) == 1)) + if (enable && (atomic_inc_return(&emu_count) == 1)) clkdm_deny_idle(emu_clkdm); - else if (!enable && (atomic_dec_return(&count) == 0)) + else if (!enable && (atomic_dec_return(&emu_count) == 0)) clkdm_allow_idle(emu_clkdm); - spin_unlock(&emu_lock); + spin_unlock_irqrestore(&iommu_lock, flags); +} + +static struct powerdomain *_get_pwrdm(struct device *dev) +{ + struct clk *clk; + struct clk_hw_omap *hwclk; + struct clockdomain *clkdm; + struct powerdomain *pwrdm = NULL; + struct pwrdm_link *entry; + unsigned long flags; + static LIST_HEAD(cache); + + spin_lock_irqsave(&iommu_lock, flags); + + list_for_each_entry(entry, &cache, node) { + if (entry->dev == dev) { + pwrdm = entry->pwrdm; + break; + } + } + + spin_unlock_irqrestore(&iommu_lock, flags); + + if (pwrdm) + return pwrdm; + + clk = of_clk_get(dev->of_node->parent, 0); + if (!clk) { + dev_err(dev, "no fck found\n"); + return NULL; + } + + hwclk = to_clk_hw_omap(__clk_get_hw(clk)); + clk_put(clk); + if (!hwclk || !hwclk->clkdm_name) { + dev_err(dev, "no hwclk data\n"); + return NULL; + } + + clkdm = clkdm_lookup(hwclk->clkdm_name); + if (!clkdm) { + dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name); + return NULL; + } + + pwrdm = clkdm_get_pwrdm(clkdm); + if (!pwrdm) { + dev_err(dev, "pwrdm not found: %s\n", clkdm->name); + return NULL; + } + + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (entry) { + entry->dev = dev; + entry->pwrdm = pwrdm; + spin_lock_irqsave(&iommu_lock, flags); + list_add(&entry->node, &cache); + spin_unlock_irqrestore(&iommu_lock, flags); + } + + return pwrdm; } int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, u8 *pwrst) { struct powerdomain *pwrdm; - struct omap_device *od; u8 next_pwrst; int ret = 0; - od = to_omap_device(pdev); - if (!od) - return -ENODEV; - - if (od->hwmods_cnt != 1) - return -EINVAL; - - pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]); + pwrdm = _get_pwrdm(&pdev->dev); if (!pwrdm) - return -EINVAL; + return -ENODEV; if (request) { *pwrst = pwrdm_read_next_pwrst(pwrdm); -- cgit v1.2.3-59-g8ed1b From 4601832f40501efc3c2fd264a5a69bd1ac17d520 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 12 Dec 2019 15:05:41 +0200 Subject: ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot The IPU1 MMU has been using common IOMMU pdata quirks defined and used by all IPU IOMMU devices on OMAP4 and beyond. Separate out the pdata for IPU1 MMU with the additional .set_pwrdm_constraint ops plugged in, so that the IPU1 power domain can be restricted to ON state during the boot and active period of the IPU1 remote processor. This eliminates the pre-conditions for the IPU1 boot issue as described in commit afe518400bdb ("iommu/omap: fix boot issue on remoteprocs with AMMU/Unicache"). NOTE: 1. RET is not a valid target power domain state on DRA7 platforms, and IPU power domain is normally programmed for OFF. The IPU1 still fails to boot though, and an unclearable l3_noc error is thrown currently on 4.14 kernel without this fix. This behavior is slightly different from previous 4.9 LTS kernel. 2. The fix is currently applied only to IPU1 on DRA7xx SoC, as the other affected processors on OMAP4/OMAP5/DRA7 are in domains that are not entering RET. IPU2 on DRA7 is in CORE power domain which is only programmed for ON power state. The fix can be easily scaled if these domains do hit RET in the future. 3. The issue was not seen on current DRA7 platforms if any of the DSP remote processors were booted and using one of the GPTimers 5, 6, 7 or 8 on previous 4.9 LTS kernel. This was due to the errata fix for i874 implemented in commit 1cbabcb9807e ("ARM: DRA7: clockdomain: Implement timer workaround for errata i874") which keeps the IPU1 power domain from entering RET when the timers are active. But the timer workaround did not make any difference on 4.14 kernel, and an l3_noc error was seen still without this fix. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 88ca7f82510a..7c6e57e4bcb2 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -43,6 +43,17 @@ struct pdata_init { static struct of_dev_auxdata omap_auxdata_lookup[]; static struct twl4030_gpio_platform_data twl_gpio_auxdata; +#if IS_ENABLED(CONFIG_OMAP_IOMMU) +int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, + u8 *pwrst); +#else +static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, + bool request, u8 *pwrst) +{ + return 0; +} +#endif + #ifdef CONFIG_MACH_NOKIA_N8X0 static void __init omap2420_n8x0_legacy_init(void) { @@ -276,6 +287,10 @@ static void __init omap5_uevm_legacy_init(void) #endif #ifdef CONFIG_SOC_DRA7XX +static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = { + .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint, +}; + static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; @@ -499,6 +514,12 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { &dra7_hsmmc_data_mmc2), OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", + &dra7_ipu1_dsp_iommu_pdata), #endif /* Common auxdata */ OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), -- cgit v1.2.3-59-g8ed1b From 064f42b28a6d6cfddc983cb433d52c3d3b006442 Mon Sep 17 00:00:00 2001 From: Justin Chen Date: Tue, 10 Dec 2019 14:48:56 -0800 Subject: ARM: brcmstb: Add debug UART entry for 7216 7216 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly. Signed-off-by: Justin Chen [florian: expand commit message] Signed-off-by: Florian Fainelli --- arch/arm/include/debug/brcmstb.S | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index bf8702ee8f86..132a20c4a676 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -31,6 +31,7 @@ #define UARTA_7268 UARTA_7255 #define UARTA_7271 UARTA_7268 #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) +#define UARTA_7216 UARTA_7278 #define UARTA_7364 REG_PHYS_ADDR(0x40b000) #define UARTA_7366 UARTA_7364 #define UARTA_74371 REG_PHYS_ADDR(0x406b00) @@ -82,17 +83,18 @@ ARM_BE8( rev \rv, \rv ) /* Chip specific detection starts here */ 20: checkuart(\rp, \rv, 0x33900000, 3390) -21: checkuart(\rp, \rv, 0x72500000, 7250) -22: checkuart(\rp, \rv, 0x72550000, 7255) -23: checkuart(\rp, \rv, 0x72600000, 7260) -24: checkuart(\rp, \rv, 0x72680000, 7268) -25: checkuart(\rp, \rv, 0x72710000, 7271) -26: checkuart(\rp, \rv, 0x72780000, 7278) -27: checkuart(\rp, \rv, 0x73640000, 7364) -28: checkuart(\rp, \rv, 0x73660000, 7366) -29: checkuart(\rp, \rv, 0x07437100, 74371) -30: checkuart(\rp, \rv, 0x74390000, 7439) -31: checkuart(\rp, \rv, 0x74450000, 7445) +21: checkuart(\rp, \rv, 0x72160000, 7216) +22: checkuart(\rp, \rv, 0x72500000, 7250) +23: checkuart(\rp, \rv, 0x72550000, 7255) +24: checkuart(\rp, \rv, 0x72600000, 7260) +25: checkuart(\rp, \rv, 0x72680000, 7268) +26: checkuart(\rp, \rv, 0x72710000, 7271) +27: checkuart(\rp, \rv, 0x72780000, 7278) +28: checkuart(\rp, \rv, 0x73640000, 7364) +29: checkuart(\rp, \rv, 0x73660000, 7366) +30: checkuart(\rp, \rv, 0x07437100, 74371) +31: checkuart(\rp, \rv, 0x74390000, 7439) +32: checkuart(\rp, \rv, 0x74450000, 7445) /* No valid UART found */ 90: mov \rp, #0 -- cgit v1.2.3-59-g8ed1b From c586f47f55d8239466824f917582c7d7d9e546ed Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 20 Dec 2019 10:21:15 -0800 Subject: ARM: bcm: Select ARM_AMBA for ARCH_BRCMSTB BCM7211 uses a PL011 UART and is supported using ARCH_BRCMSTB, make sure that we can enable that driver by selecting ARM_AMBA. Signed-off-by: Florian Fainelli --- arch/arm/mach-bcm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index e4e25f287ad7..fcfe2a0e8058 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -211,6 +211,7 @@ config ARCH_BRCMSTB bool "Broadcom BCM7XXX based boards" depends on ARCH_MULTI_V7 select ARCH_HAS_RESET_CONTROLLER + select ARM_AMBA select ARM_GIC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER -- cgit v1.2.3-59-g8ed1b From ad097ab061b00bcf2e0666b74828323c20c87b3a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Jan 2020 17:52:08 +0100 Subject: ARM: exynos: Correct the help text for platform Kconfig option ARCH_EXYNOS option is used for entire ARMv7 Exynos family, including also Exynos3 SoCs. Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4ef56571145b..9fb045ab80e4 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -41,7 +41,7 @@ menuconfig ARCH_EXYNOS select POWER_RESET_SYSCON select POWER_RESET_SYSCON_POWEROFF help - Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) + Support for SAMSUNG EXYNOS SoCs if ARCH_EXYNOS -- cgit v1.2.3-59-g8ed1b From 45984f0c70ccc03e09f97ee5d0749396547b6594 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Jan 2020 16:20:51 +0100 Subject: ARM: samsung: Rename Samsung and Exynos to lowercase Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/Kconfig | 36 +++++++++++------------ arch/arm/mach-exynos/common.h | 2 +- arch/arm/mach-exynos/exynos.c | 4 +-- arch/arm/mach-exynos/include/mach/map.h | 2 +- arch/arm/mach-exynos/pm.c | 2 +- arch/arm/mach-exynos/smc.h | 2 +- arch/arm/mach-exynos/suspend.c | 2 +- arch/arm/mach-s3c24xx/Kconfig | 16 +++++----- arch/arm/plat-samsung/adc.c | 2 +- arch/arm/plat-samsung/devs.c | 2 +- arch/arm/plat-samsung/gpio-samsung.c | 2 +- arch/arm/plat-samsung/include/plat/samsung-time.h | 2 +- 12 files changed, 37 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 9fb045ab80e4..73ce92a0cdb2 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -3,10 +3,10 @@ # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # http://www.samsung.com/ -# Configuration options for the EXYNOS +# Configuration options for the Samsung Exynos menuconfig ARCH_EXYNOS - bool "Samsung EXYNOS" + bool "Samsung Exynos" depends on ARCH_MULTI_V7 select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SUPPORTS_BIG_ENDIAN @@ -41,7 +41,7 @@ menuconfig ARCH_EXYNOS select POWER_RESET_SYSCON select POWER_RESET_SYSCON_POWEROFF help - Support for SAMSUNG EXYNOS SoCs + Support for Samsung Exynos SoCs if ARCH_EXYNOS @@ -51,14 +51,14 @@ config S5P_DEV_MFC Compile in setup memory (init) code for MFC config ARCH_EXYNOS3 - bool "SAMSUNG EXYNOS3" + bool "Samsung Exynos3" default y select ARM_CPU_SUSPEND if PM help - Samsung EXYNOS3 (Cortex-A7) SoC based systems + Samsung Exynos3 (Cortex-A7) SoC based systems config ARCH_EXYNOS4 - bool "SAMSUNG EXYNOS4" + bool "Samsung Exynos4" default y select ARM_CPU_SUSPEND if PM_SLEEP select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 @@ -66,48 +66,48 @@ config ARCH_EXYNOS4 select GIC_NON_BANKED select MIGHT_HAVE_CACHE_L2X0 help - Samsung EXYNOS4 (Cortex-A9) SoC based systems + Samsung Exynos4 (Cortex-A9) SoC based systems config ARCH_EXYNOS5 - bool "SAMSUNG EXYNOS5" + bool "Samsung Exynos5" default y help - Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems + Samsung Exynos5 (Cortex-A15/A7) SoC based systems -comment "EXYNOS SoCs" +comment "Exynos SoCs" config SOC_EXYNOS3250 - bool "SAMSUNG EXYNOS3250" + bool "Samsung Exynos3250" default y depends on ARCH_EXYNOS3 config CPU_EXYNOS4210 - bool "SAMSUNG EXYNOS4210" + bool "Samsung Exynos4210" default y depends on ARCH_EXYNOS4 config SOC_EXYNOS4412 - bool "SAMSUNG EXYNOS4412" + bool "Samsung Exynos4412" default y depends on ARCH_EXYNOS4 config SOC_EXYNOS5250 - bool "SAMSUNG EXYNOS5250" + bool "Samsung Exynos5250" default y depends on ARCH_EXYNOS5 config SOC_EXYNOS5260 - bool "SAMSUNG EXYNOS5260" + bool "Samsung Exynos5260" default y depends on ARCH_EXYNOS5 config SOC_EXYNOS5410 - bool "SAMSUNG EXYNOS5410" + bool "Samsung Exynos5410" default y depends on ARCH_EXYNOS5 config SOC_EXYNOS5420 - bool "SAMSUNG EXYNOS5420" + bool "Samsung Exynos5420" default y depends on ARCH_EXYNOS5 select EXYNOS_MCPM if SMP @@ -115,7 +115,7 @@ config SOC_EXYNOS5420 select ARM_CPU_SUSPEND config SOC_EXYNOS5800 - bool "SAMSUNG EXYNOS5800" + bool "Samsung EXYNOS5800" default y depends on SOC_EXYNOS5420 diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 56411bb63d45..afd988a92836 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -3,7 +3,7 @@ * Copyright (c) 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Common Header for EXYNOS machines + * Common Header for Exynos machines */ #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 9aa483366ebc..7a8d1555db40 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // -// SAMSUNG EXYNOS Flattened Device Tree enabled machine +// Samsung Exynos Flattened Device Tree enabled machine // // Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. // http://www.samsung.com @@ -192,7 +192,7 @@ static void __init exynos_dt_fixup(void) of_fdt_limit_memory(8); } -DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") +DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") .l2c_aux_val = 0x3c400001, .l2c_aux_mask = 0xc20fffff, .smp = smp_ops(exynos_smp_ops), diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 22ebe3654633..8d58faa54ff7 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -3,7 +3,7 @@ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * - * EXYNOS - Memory map definitions + * Exynos - Memory map definitions */ #ifndef __ASM_ARCH_MAP_H diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 48e7fb38613e..78af34cc89cc 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -3,7 +3,7 @@ // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. // http://www.samsung.com // -// EXYNOS - Power Management support +// Exynos - Power Management support // // Based on arch/arm/mach-s3c2410/pm.c // Copyright (c) 2006 Simtec Electronics diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h index 98832e50852d..5c30feb8f07d 100644 --- a/arch/arm/mach-exynos/smc.h +++ b/arch/arm/mach-exynos/smc.h @@ -2,7 +2,7 @@ /* * Copyright (c) 2012 Samsung Electronics. * - * EXYNOS - SMC Call + * Exynos - SMC Call */ #ifndef __ASM_ARCH_EXYNOS_SMC_H diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 6a0d3448ea00..3bf14ca78b62 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -3,7 +3,7 @@ // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. // http://www.samsung.com // -// EXYNOS - Suspend support +// Exynos - Suspend support // // Based on arch/arm/mach-s3c2410/pm.c // Copyright (c) 2006 Simtec Electronics diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 686f0bbde998..c5c06d98b147 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -19,12 +19,12 @@ config PLAT_S3C24XX -menu "SAMSUNG S3C24XX SoCs Support" +menu "Samsung S3C24XX SoCs Support" comment "S3C24XX SoCs" config CPU_S3C2410 - bool "SAMSUNG S3C2410" + bool "Samsung S3C2410" default y select CPU_ARM920T select S3C2410_COMMON_CLK @@ -35,7 +35,7 @@ config CPU_S3C2410 of Samsung Mobile CPUs. config CPU_S3C2412 - bool "SAMSUNG S3C2412" + bool "Samsung S3C2412" select CPU_ARM926T select S3C2412_COMMON_CLK select S3C2412_PM if PM_SLEEP @@ -43,7 +43,7 @@ config CPU_S3C2412 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line config CPU_S3C2416 - bool "SAMSUNG S3C2416/S3C2450" + bool "Samsung S3C2416/S3C2450" select CPU_ARM926T select S3C2416_PM if PM_SLEEP select S3C2443_COMMON_CLK @@ -51,7 +51,7 @@ config CPU_S3C2416 Support for the S3C2416 SoC from the S3C24XX line config CPU_S3C2440 - bool "SAMSUNG S3C2440" + bool "Samsung S3C2440" select CPU_ARM920T select S3C2410_COMMON_CLK select S3C2410_PM if PM_SLEEP @@ -59,7 +59,7 @@ config CPU_S3C2440 Support for S3C2440 Samsung Mobile CPU based systems. config CPU_S3C2442 - bool "SAMSUNG S3C2442" + bool "Samsung S3C2442" select CPU_ARM920T select S3C2410_COMMON_CLK select S3C2410_PM if PM_SLEEP @@ -71,7 +71,7 @@ config CPU_S3C244X depends on CPU_S3C2440 || CPU_S3C2442 config CPU_S3C2443 - bool "SAMSUNG S3C2443" + bool "Samsung S3C2443" select CPU_ARM920T select S3C2443_COMMON_CLK help @@ -591,6 +591,6 @@ config PM_H1940 help Internal node for H1940 and related PM -endmenu # SAMSUNG S3C24XX SoCs Support +endmenu # Samsung S3C24XX SoCs Support endif # ARCH_S3C24XX diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index ee3d5c989a76..4f7b27239bd4 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -40,7 +40,7 @@ enum s3c_cpu_type { TYPE_ADCV11, /* S3C2443 */ TYPE_ADCV12, /* S3C2416, S3C2450 */ TYPE_ADCV2, /* S3C64XX */ - TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ + TYPE_ADCV3, /* S5PV210, S5PC110, Exynos4210 */ }; struct s3c_adc_client { diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 1602f6dc900b..089a17687104 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -3,7 +3,7 @@ // Copyright (c) 2011 Samsung Electronics Co., Ltd. // http://www.samsung.com // -// Base SAMSUNG platform device definitions +// Base Samsung platform device definitions #include #include diff --git a/arch/arm/plat-samsung/gpio-samsung.c b/arch/arm/plat-samsung/gpio-samsung.c index f66c820cd82b..8955fd675265 100644 --- a/arch/arm/plat-samsung/gpio-samsung.c +++ b/arch/arm/plat-samsung/gpio-samsung.c @@ -8,7 +8,7 @@ // Ben Dooks // http://armlinux.simtec.co.uk/ // -// SAMSUNG - GPIOlib support +// Samsung - GPIOlib support #include #include diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h index d16eefe9ae78..32ab0860f631 100644 --- a/arch/arm/plat-samsung/include/plat/samsung-time.h +++ b/arch/arm/plat-samsung/include/plat/samsung-time.h @@ -9,7 +9,7 @@ #ifndef __ASM_PLAT_SAMSUNG_TIME_H #define __ASM_PLAT_SAMSUNG_TIME_H __FILE__ -/* SAMSUNG HR-Timer Clock mode */ +/* Samsung HR-Timer Clock mode */ enum samsung_timer_mode { SAMSUNG_PWM0, SAMSUNG_PWM1, -- cgit v1.2.3-59-g8ed1b From 1a3388d506bf5b45bb283e6a4c4706cfb4897333 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 3 Oct 2019 14:50:31 -0600 Subject: ARM: tegra: Enable PLLP bypass during Tegra124 LP1 For a little over a year, U-Boot has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail[1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. PLLP is one of those clocks. This clock is shut down during LP1 in order to save power. Enable bypass (which I believe routes osc_div_clk, essentially the crystal clock, to the PLL output) so that this clock signal toggles even though the PLL is not active. This is required so that LP1 power mode (system suspend) operates correctly. The bypass configuration must then be undone when resuming from LP1, so that all peripheral clocks run at the expected rate. Without this, many peripherals won't work correctly; for example, the UART baud rate would be incorrect. NVIDIA's downstream kernel code only does this if not compiled for Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's downstream code makes this change conditional upon the active CPU cluster. The upstream kernel currently doesn't support cluster switching, so this patch doesn't test the active CPU cluster ID. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 3341a12bbb9c..c796a97194ac 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -370,6 +370,14 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLC_BASE pll_locked r1, r0, CLK_RESET_PLLX_BASE + tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 + cmp r1, #TEGRA30 + beq 1f + ldr r1, [r0, #CLK_RESET_PLLP_BASE] + bic r1, r1, #(1<<31) @ disable PllP bypass + str r1, [r0, #CLK_RESET_PLLP_BASE] +1: + mov32 r7, TEGRA_TMRUS_BASE ldr r1, [r7] add r1, r1, #LOCK_DELAY @@ -630,7 +638,10 @@ tegra30_switch_cpu_to_clk32k: str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] /* disable PLLP, PLLA, PLLC and PLLX */ + tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 + cmp r1, #TEGRA30 ldr r0, [r5, #CLK_RESET_PLLP_BASE] + orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster bic r0, r0, #(1 << 30) str r0, [r5, #CLK_RESET_PLLP_BASE] ldr r0, [r5, #CLK_RESET_PLLA_BASE] -- cgit v1.2.3-59-g8ed1b From cf94a7a06a7d7d4402d7313cf622ca2823bad43c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 3 Oct 2019 14:50:32 -0600 Subject: ARM: tegra: Modify reshift divider during LP1 The reshift hardware module implements the RAM re-repair process. This module uses PLLP as an input clock during LP1 resume. The input divider for this clock is typically set for PLLP's normal rate. During LP1 resume, PLLP is bypassed and so runs at the crystal rate, which is much slower. Consequently, decrease the divider so that the reshift module runs at a reasonable rate during LP1 resume. NVIDIA's downstream kernel code only does this if not compiled for Tegra30, so the added code is made conditional upon the chip ID. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index c796a97194ac..f01ea3be1405 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -59,6 +59,9 @@ #define CLK_RESET_PLLX_MISC3_IDDQ 3 #define CLK_RESET_PLLM_MISC_IDDQ 5 #define CLK_RESET_PLLC_MISC_IDDQ 26 +#define CLK_RESET_PLLP_RESHIFT 0x528 +#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b +#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 @@ -373,9 +376,13 @@ _pll_m_c_x_done: tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 cmp r1, #TEGRA30 beq 1f + ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass str r1, [r0, #CLK_RESET_PLLP_BASE] + + mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT + str r1, [r0, #CLK_RESET_PLLP_RESHIFT] 1: mov32 r7, TEGRA_TMRUS_BASE @@ -644,6 +651,10 @@ tegra30_switch_cpu_to_clk32k: orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster bic r0, r0, #(1 << 30) str r0, [r5, #CLK_RESET_PLLP_BASE] + beq 1f + mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE + str r0, [r5, #CLK_RESET_PLLP_RESHIFT] +1: ldr r0, [r5, #CLK_RESET_PLLA_BASE] bic r0, r0, #(1 << 30) str r0, [r5, #CLK_RESET_PLLA_BASE] -- cgit v1.2.3-59-g8ed1b From 9c65b8463f41f3a9edef97e3109752159d4c6a4b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 3 Oct 2019 14:50:33 -0600 Subject: ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume Configure the clock controller to set an alternate clock for the CPU when it receives an IRQ during LP1 (system suspend). Specifically, use clk_m (the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will be the LP1 wake event. This reduces the amount of time taken to resume from LP1. NVIDIA's downstream kernel executes this code on both Tegra30 and Tegra124, so it appears OK to make this change unconditionally. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra30.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index f01ea3be1405..02cc6ff96f30 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -670,8 +670,12 @@ tegra30_switch_cpu_to_clk32k: pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ _no_pll_in_iddq: - /* switch to CLKS */ - mov r0, #0 /* brust policy = 32KHz */ + /* + * Switch to clk_s (32KHz); bits 28:31=0 + * Enable burst on CPU IRQ; bit 24=1 + * Set IRQ burst clock source to clk_m; bits 10:8=0 + */ + mov r0, #(1 << 24) str r0, [r5, #CLK_RESET_SCLK_BURST] ret lr -- cgit v1.2.3-59-g8ed1b From 6c6b3f1f260b24dc0ab9cbbf369e4fa36819ab8b Mon Sep 17 00:00:00 2001 From: Quanyang Wang Date: Tue, 22 Oct 2019 11:23:28 +0800 Subject: ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start When kernel booting, it will create a cpuid map between the logical cpus and physical cpus. In a normal boot, the cpuid map is as below: Physical Logical 0 ==> 0 1 ==> 1 But in kdump, there is a condition that the crash happens at the physical cpu1, and the crash kernel will run at the physical cpu1 too, so the cpuid map in crash kernel is as below: Physical Logical 1 ==> 0 0 ==> 1 The functions zynq_slcr_cpu_stop/start is to stop/start the physical cpus, the parameter cpu should be the physical cpuid. So use cpu_logical_map to translate the logical cpuid to physical cpuid. Or else the logical cpu0(physical cpu1) will stop itself and the processor will hang. Signed-off-by: Quanyang Wang Tested-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/mach-zynq/platsmp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index a10085be9073..68ec303fa278 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -30,6 +31,7 @@ int zynq_cpun_start(u32 address, int cpu) { u32 trampoline_code_size = &zynq_secondary_trampoline_end - &zynq_secondary_trampoline; + u32 phy_cpuid = cpu_logical_map(cpu); /* MS: Expectation that SLCR are directly map and accessible */ /* Not possible to jump to non aligned address */ @@ -39,7 +41,7 @@ int zynq_cpun_start(u32 address, int cpu) u32 trampoline_size = &zynq_secondary_trampoline_jump - &zynq_secondary_trampoline; - zynq_slcr_cpu_stop(cpu); + zynq_slcr_cpu_stop(phy_cpuid); if (address) { if (__pa(PAGE_OFFSET)) { zero = ioremap(0, trampoline_code_size); @@ -68,7 +70,7 @@ int zynq_cpun_start(u32 address, int cpu) if (__pa(PAGE_OFFSET)) iounmap(zero); } - zynq_slcr_cpu_start(cpu); + zynq_slcr_cpu_start(phy_cpuid); return 0; } -- cgit v1.2.3-59-g8ed1b From c74067a0f776c1d695a713a4388c3b6a094ee40a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 7 Jan 2020 22:51:39 +0100 Subject: ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A i.MX7D is supported for either the v7-A or the v7-M cores, but the latter causes a warning: WARNING: unmet direct dependencies detected for ARM_ERRATA_814220 Depends on [n]: CPU_V7 [=n] Selected by [y]: - SOC_IMX7D [=y] && ARCH_MXC [=y] && (ARCH_MULTI_V7 [=n] || ARM_SINGLE_ARMV7M [=y]) Make the select statement conditional. Fixes: 4562fa4c86c9 ("ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D") Signed-off-by: Arnd Bergmann Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 4326c8f53462..95584ee02b55 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -557,7 +557,7 @@ config SOC_IMX7D select PINCTRL_IMX7D select SOC_IMX7D_CA7 if ARCH_MULTI_V7 select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M - select ARM_ERRATA_814220 + select ARM_ERRATA_814220 if ARCH_MULTI_V7 help This enables support for Freescale i.MX7 Dual processor. -- cgit v1.2.3-59-g8ed1b From 6b9dfd986a81a999a27b6ed9dbe91203089c62dd Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 11 Dec 2019 13:04:07 +0200 Subject: ARM: at91: pm: use SAM9X60 PMC's compatible SAM9X60 PMC's has a different PMC. It was not integrated at the moment commit 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") was published. Fixes: 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1576062248-18514-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/pm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 56a6a49b19e2..62c170fbd339 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -751,6 +751,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, + { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[1] }, { /* sentinel */ }, }; -- cgit v1.2.3-59-g8ed1b From ec6e618c8c018c1361d77789a100a5f6f6317178 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 11 Dec 2019 13:04:08 +0200 Subject: ARM: at91: pm: use of_device_id array to find the proper shdwc node Use of_device_id array to find the proper shdwc compatibile node. SAM9X60's shdwc changes were not integrated when commit eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") was integrated. Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1576062248-18514-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/pm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 62c170fbd339..374b9d155558 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -691,6 +691,12 @@ static void __init at91_pm_use_default_mode(int pm_mode) soc_pm.data.suspend_mode = AT91_PM_ULP0; } +static const struct of_device_id atmel_shdwc_ids[] = { + { .compatible = "atmel,sama5d2-shdwc" }, + { .compatible = "microchip,sam9x60-shdwc" }, + { /* sentinel. */ } +}; + static void __init at91_pm_modes_init(void) { struct device_node *np; @@ -700,7 +706,7 @@ static void __init at91_pm_modes_init(void) !at91_is_pm_mode_active(AT91_PM_ULP1)) return; - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); + np = of_find_matching_node(NULL, atmel_shdwc_ids); if (!np) { pr_warn("%s: failed to find shdwc!\n", __func__); goto ulp1_default; -- cgit v1.2.3-59-g8ed1b From db711893eac81442fb5cde3801e183d3abfe5693 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 2 Jan 2020 16:19:40 -0500 Subject: ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization This can be used for detecting secure features or making early device init sequence changes based on device security type. Signed-off-by: Andrew F. Davis Reviewed-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 11 +++++++++++ arch/arm/mach-omap2/omap-secure.c | 4 ++++ arch/arm/mach-omap2/omap-secure.h | 2 ++ 3 files changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 349e48042982..f28047233665 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -51,6 +51,7 @@ #include "prm33xx.h" #include "prm44xx.h" #include "opp2xxx.h" +#include "omap-secure.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific @@ -430,6 +431,7 @@ void __init omap2420_init_early(void) omap_hwmod_init_postsetup(); omap_clk_soc_init = omap2420_dt_clk_init; rate_table = omap2420_rate_table; + omap_secure_init(); } void __init omap2420_init_late(void) @@ -454,6 +456,7 @@ void __init omap2430_init_early(void) omap_hwmod_init_postsetup(); omap_clk_soc_init = omap2430_dt_clk_init; rate_table = omap2430_rate_table; + omap_secure_init(); } void __init omap2430_init_late(void) @@ -481,6 +484,7 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_secure_init(); } void __init omap3430_init_early(void) @@ -533,6 +537,7 @@ void __init ti814x_init_early(void) dm814x_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dm814x_dt_clk_init; + omap_secure_init(); } void __init ti816x_init_early(void) @@ -549,6 +554,7 @@ void __init ti816x_init_early(void) dm816x_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dm816x_dt_clk_init; + omap_secure_init(); } #endif @@ -566,6 +572,7 @@ void __init am33xx_init_early(void) am33xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = am33xx_dt_clk_init; + omap_secure_init(); } void __init am33xx_init_late(void) @@ -589,6 +596,7 @@ void __init am43xx_init_early(void) omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = am43xx_dt_clk_init; + omap_secure_init(); } void __init am43xx_init_late(void) @@ -617,6 +625,7 @@ void __init omap4430_init_early(void) omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = omap4xxx_dt_clk_init; + omap_secure_init(); } void __init omap4430_init_late(void) @@ -643,6 +652,7 @@ void __init omap5_init_early(void) omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = omap5xxx_dt_clk_init; + omap_secure_init(); } void __init omap5_init_late(void) @@ -666,6 +676,7 @@ void __init dra7xx_init_early(void) dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dra7xx_dt_clk_init; + omap_secure_init(); } void __init dra7xx_init_late(void) diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 24298e47b9f1..e936732cdc4f 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -163,3 +163,7 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) NO_FLAG, 3, ptr, count, flag, 0); } + +void __init omap_secure_init(void) +{ +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 20046e8f8ecb..9aeeb236a224 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -72,6 +72,8 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); +void omap_secure_init(void); + #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER void set_cntfreq(void); #else -- cgit v1.2.3-59-g8ed1b From dbebc8bfe9dcb760b72ec7e2bb9de30a174ff8dc Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 2 Jan 2020 16:19:41 -0500 Subject: ARM: OMAP2+: Introduce check for OP-TEE in omap_secure_init() This check and associated flag can be used to signal the presence of OP-TEE on the platform. This can be used to determine which SMC calls to make to perform secure operations. Signed-off-by: Andrew F. Davis Reviewed-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-secure.c | 19 +++++++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 3 +++ 2 files changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index e936732cdc4f..568646660081 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -20,6 +21,23 @@ static phys_addr_t omap_secure_memblock_base; +bool optee_available; + +static void __init omap_optee_init_check(void) +{ + struct device_node *np; + + /* + * We only check that the OP-TEE node is present and available. The + * OP-TEE kernel driver is not needed for the type of interaction made + * with OP-TEE here so the driver's status is not checked. + */ + np = of_find_node_by_path("/firmware/optee"); + if (np && of_device_is_available(np)) + optee_available = true; + of_node_put(np); +} + /** * omap_sec_dispatcher: Routine to dispatch low power secure * service routines @@ -166,4 +184,5 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) void __init omap_secure_init(void) { + omap_optee_init_check(); } diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 9aeeb236a224..78a1c4f04bbe 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -10,6 +10,8 @@ #ifndef OMAP_ARCH_OMAP_SECURE_H #define OMAP_ARCH_OMAP_SECURE_H +#include + /* Monitor error code */ #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF @@ -72,6 +74,7 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); +extern bool optee_available; void omap_secure_init(void); #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER -- cgit v1.2.3-59-g8ed1b From 48840e16c299d886a1fc333375f0564c34cab127 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 2 Jan 2020 16:19:42 -0500 Subject: ARM: OMAP2+: Use ARM SMC Calling Convention when OP-TEE is available On High-Security(HS) OMAP2+ class devices a couple actions must be performed from the ARM TrustZone during boot. These traditionally can be performed by calling into the secure ROM code resident in this secure world using legacy SMC calls. Optionally OP-TEE can replace this secure world functionality by replacing the ROM after boot. ARM recommends a standard calling convention is used for this interaction (SMC Calling Convention). We check for the presence of OP-TEE and use this type of call to perform the needed actions, falling back to the legacy OMAP ROM call if OP-TEE is not available. Signed-off-by: Andrew F. Davis Reviewed-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/common.h | 2 +- arch/arm/mach-omap2/omap-secure.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 2 ++ arch/arm/mach-omap2/omap-smc.S | 6 +++--- 4 files changed, 33 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 223b37c48389..3b1fd8e7d705 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -255,7 +255,7 @@ extern void gic_dist_disable(void); extern void gic_dist_enable(void); extern bool gic_dist_disabled(void); extern void gic_timer_retrigger(void); -extern void omap_smc1(u32 fn, u32 arg); +extern void _omap_smc1(u32 fn, u32 arg); extern void omap4_sar_ram_init(void); extern void __iomem *omap4_get_sar_ram_base(void); extern void omap4_mpuss_early_init(void); diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 568646660081..d00e3c72e37d 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -8,6 +8,7 @@ * Copyright (C) 2013 Pali Rohár */ +#include #include #include #include @@ -17,12 +18,17 @@ #include #include +#include "common.h" #include "omap-secure.h" static phys_addr_t omap_secure_memblock_base; bool optee_available; +#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + static void __init omap_optee_init_check(void) { struct device_node *np; @@ -71,6 +77,27 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, return ret; } +void omap_smccc_smc(u32 fn, u32 arg) +{ + struct arm_smccc_res res; + + arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg, + 0, 0, 0, 0, 0, 0, &res); + WARN(res.a0, "Secure function call 0x%08x failed\n", fn); +} + +void omap_smc1(u32 fn, u32 arg) +{ + /* + * If this platform has OP-TEE installed we use ARM SMC calls + * otherwise fall back to the OMAP ROM style calls. + */ + if (optee_available) + omap_smccc_smc(fn, arg); + else + _omap_smc1(fn, arg); +} + /* Allocate the memory to save secure ram */ int __init omap_secure_ram_reserve_memblock(void) { diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 78a1c4f04bbe..736e594365f4 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -62,6 +62,8 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); +extern void omap_smccc_smc(u32 fn, u32 arg); +extern void omap_smc1(u32 fn, u32 arg); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index fd2bcd91f4a1..d4832845a4e8 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -18,18 +18,18 @@ * the monitor API number. It uses few CPU registers * internally and hence they need be backed up including * link register "lr". - * Function signature : void omap_smc1(u32 fn, u32 arg) + * Function signature : void _omap_smc1(u32 fn, u32 arg) */ .arch armv7-a .arch_extension sec -ENTRY(omap_smc1) +ENTRY(_omap_smc1) stmfd sp!, {r2-r12, lr} mov r12, r0 mov r0, r1 dsb smc #0 ldmfd sp!, {r2-r12, pc} -ENDPROC(omap_smc1) +ENDPROC(_omap_smc1) /** * u32 omap_smc2(u32 id, u32 falg, u32 pargs) -- cgit v1.2.3-59-g8ed1b From 8ab871f8bdfcca627802b6992e556fba5722a268 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 2 Jan 2020 16:19:43 -0500 Subject: ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers During suspend CPU context may be lost in both non-secure and secure CPU states. The kernel can handle saving and restoring the non-secure context but must call into the secure side to allow it to save any context it may lose. Add these calls here. Note that on systems with OP-TEE available the suspend call is issued to OP-TEE using the ARM SMCCC, but the resume call is always issued to the ROM. This is because on waking from suspend the ROM is restored as the secure monitor. It is this resume call that instructs the ROM to restore OP-TEE, all subsequent calls will be handled by OP-TEE and should use the ARM SMCCC. Signed-off-by: Andrew F. Davis Acked-by: Dave Gerlach Reviewed-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-secure.h | 3 +++ arch/arm/mach-omap2/pm33xx-core.c | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 736e594365f4..ba8c486c0454 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -53,6 +53,9 @@ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 +#define AM43xx_PPA_SVC_PM_SUSPEND 0x71 +#define AM43xx_PPA_SVC_PM_RESUME 0x72 + /* Secure RX-51 PPA (Primary Protected Application) APIs */ #define RX51_PPA_HWRNG 29 #define RX51_PPA_L2_INVAL 40 diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index f11442ed3eff..7461b0346549 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -28,6 +28,7 @@ #include "prm33xx.h" #include "soc.h" #include "sram.h" +#include "omap-secure.h" static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; static struct clockdomain *gfx_l4ls_clkdm; @@ -166,6 +167,16 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), { int ret = 0; + /* Suspend secure side on HS devices */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) { + if (optee_available) + omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0); + else + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + } + amx3_pre_suspend_common(); scu_power_mode(scu_base, SCU_PM_POWEROFF); ret = cpu_suspend(args, fn); @@ -174,6 +185,19 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), if (!am43xx_check_off_mode_enable()) amx3_post_suspend_common(); + /* + * Resume secure side on HS devices. + * + * Note that even on systems with OP-TEE available this resume call is + * issued to the ROM. This is because upon waking from suspend the ROM + * is restored as the secure monitor. On systems with OP-TEE ROM will + * restore OP-TEE during this call. + */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + return ret; } -- cgit v1.2.3-59-g8ed1b From 5ec6fd39f5f23278c6c2f528b412dcff6a29eb59 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 20 Jan 2020 20:33:28 +0100 Subject: ARM: s3c24xx: Switch to atomic pwm API in rx1950 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop using the legacy PWM API which only still exists because there are some users left. Note this change make use of the fact that the value of struct pwm_state::duty_cycle doesn't matter for a disabled PWM and so its value can stay constant simplifying the code a bit. A side effect of the conversion is that the pwm isn't stopped in rx1950_backlight_init() by the call to pwm_apply_args() just before reenabling it when rx1950_lcd_power(1) is called. Signed-off-by: Uwe Kleine-König Reviewed-by: Vasily Khoruzhick Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c24xx/mach-rx1950.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index 29f9b345a531..03d8f27cdc32 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -377,6 +377,7 @@ static struct pwm_lookup rx1950_pwm_lookup[] = { }; static struct pwm_device *lcd_pwm; +static struct pwm_state lcd_pwm_state; static void rx1950_lcd_power(int enable) { @@ -429,15 +430,16 @@ static void rx1950_lcd_power(int enable) /* GPB1->OUTPUT, GPB1->0 */ gpio_direction_output(S3C2410_GPB(1), 0); - pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD); - pwm_disable(lcd_pwm); + + lcd_pwm_state.enabled = false; + pwm_apply_state(lcd_pwm, &lcd_pwm_state); /* GPC0->0, GPC10->0 */ gpio_direction_output(S3C2410_GPC(0), 0); gpio_direction_output(S3C2410_GPC(10), 0); } else { - pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD); - pwm_enable(lcd_pwm); + lcd_pwm_state.enabled = true; + pwm_apply_state(lcd_pwm, &lcd_pwm_state); gpio_direction_output(S3C2410_GPC(0), 1); gpio_direction_output(S3C2410_GPC(5), 1); @@ -493,10 +495,13 @@ static int rx1950_backlight_init(struct device *dev) } /* - * FIXME: pwm_apply_args() should be removed when switching to - * the atomic PWM API. + * This is only required to initialize .polarity; all other values are + * fixed in this driver. */ - pwm_apply_args(lcd_pwm); + pwm_init_state(lcd_pwm, &lcd_pwm_state); + + lcd_pwm_state.period = LCD_PWM_PERIOD; + lcd_pwm_state.duty_cycle = LCD_PWM_DUTY; rx1950_lcd_power(1); rx1950_bl_power(1); -- cgit v1.2.3-59-g8ed1b From 21829ec37e1b9356e442729fcdd7e189fc28d63b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 21 Jan 2020 11:37:12 +0100 Subject: ARM: exynos: Drop unneeded select of MIGHT_HAVE_CACHE_L2X0 Support for Samsung Exynos SoCs depends on ARCH_MULTI_V7, which selects ARCH_MULTI_V6_V7. As the latter selects MIGHT_HAVE_CACHE_L2X0, there is no need for ARCH_EXYNOS4 to select MIGHT_HAVE_CACHE_L2X0. Signed-off-by: Geert Uytterhoeven Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 73ce92a0cdb2..52a515017fe7 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -64,7 +64,6 @@ config ARCH_EXYNOS4 select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select GIC_NON_BANKED - select MIGHT_HAVE_CACHE_L2X0 help Samsung Exynos4 (Cortex-A9) SoC based systems -- cgit v1.2.3-59-g8ed1b From af15a11b9046722f831588eff8fc423d28a1df44 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 21 Jan 2020 11:37:21 +0100 Subject: ARM: s3c64xx: Drop unneeded select of TIMER_OF Support for Samsung S3C64XX systems depends on ARCH_MULTI_V6, and thus on ARCH_MULTIPLATFORM. As the latter selects TIMER_OF, there is no need for MACH_S3C64XX_DT to select TIMER_OF. Signed-off-by: Geert Uytterhoeven Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c64xx/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 5700822e3c74..ac3e3563487f 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -336,7 +336,6 @@ config MACH_WLF_CRAGG_6410 config MACH_S3C64XX_DT bool "Samsung S3C6400/S3C6410 machine using Device Tree" - select TIMER_OF select CPU_S3C6400 select CPU_S3C6410 select PINCTRL -- cgit v1.2.3-59-g8ed1b From c37baa06f8a970e4a533d41f7d33e5e57de5ad25 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Wed, 22 Jan 2020 12:20:17 -0500 Subject: ARM: OMAP2+: Fix undefined reference to omap_secure_init omap_secure_init() is now called from all OMAP2+ platforms during their init_early() call. This function is in omap-secure.o so include that in the build for these platforms. Fixes: db711893eac8 ("ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization") Reported-by: Dan Murphy Signed-off-by: Andrew F. Davis Tested-by: Dan Murphy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f07cfda85156..e1135b9d67c6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -16,11 +16,11 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ clock-common = clock.o secure-common = omap-smc.o omap-secure.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) -obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) -- cgit v1.2.3-59-g8ed1b