From 96983ffefce46312e9372d357309dda413553009 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Fri, 18 Sep 2009 19:12:45 -0700 Subject: MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines. This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover MIPSxx-style board cache code. Signed-off-by: Kevin Cernekee Signed-off-by: Ralf Baechle --- arch/mips/mm/sc-mips.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index b55c2d1b998f..5ab5fa8c1d82 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size) */ static void mips_sc_inv(unsigned long addr, unsigned long size) { + unsigned long lsize = cpu_scache_line_size(); + unsigned long almask = ~(lsize - 1); + + cache_op(Hit_Writeback_Inv_SD, addr & almask); + cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask); blast_inv_scache_range(addr, addr + size); } -- cgit v1.2.3-59-g8ed1b