From 2f26e6189d3bdfcbf2b3bd0d6ff88eb8e7022246 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 18 Mar 2016 08:21:19 +0100 Subject: ARM: at91: use chipid device for soc detection So far, the CIDR and EXID registers were in the DBGU interface. This device has disappeared with the SAMA5D2 family. These registers are exposed through a new device called chipid. Signed-off-by: Ludovic Desroches [nicolas.ferre@atmel.com: remove useless warnings] Acked-by: Alexandre Belloni Acked-by: Rob Herring [arnd@arndb.de: suggest to use static functions to reduce scope] Acked-by: Arnd Bergmann Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/soc.c | 81 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/soc.c b/arch/arm/mach-at91/soc.c index 54343ffa3e53..c6fda75ddb89 100644 --- a/arch/arm/mach-at91/soc.c +++ b/arch/arm/mach-at91/soc.c @@ -22,48 +22,93 @@ #include "soc.h" #define AT91_DBGU_CIDR 0x40 -#define AT91_DBGU_CIDR_VERSION(x) ((x) & 0x1f) -#define AT91_DBGU_CIDR_EXT BIT(31) -#define AT91_DBGU_CIDR_MATCH_MASK 0x7fffffe0 #define AT91_DBGU_EXID 0x44 +#define AT91_CHIPID_CIDR 0x00 +#define AT91_CHIPID_EXID 0x04 +#define AT91_CIDR_VERSION(x) ((x) & 0x1f) +#define AT91_CIDR_EXT BIT(31) +#define AT91_CIDR_MATCH_MASK 0x7fffffe0 -struct soc_device * __init at91_soc_init(const struct at91_soc *socs) +static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid) { - struct soc_device_attribute *soc_dev_attr; - const struct at91_soc *soc; - struct soc_device *soc_dev; struct device_node *np; void __iomem *regs; - u32 cidr, exid; np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu"); if (!np) np = of_find_compatible_node(NULL, NULL, "atmel,at91sam9260-dbgu"); + if (!np) + return -ENODEV; - if (!np) { - pr_warn("Could not find DBGU node"); - return NULL; + regs = of_iomap(np, 0); + of_node_put(np); + + if (!regs) { + pr_warn("Could not map DBGU iomem range"); + return -ENXIO; } + *cidr = readl(regs + AT91_DBGU_CIDR); + *exid = readl(regs + AT91_DBGU_EXID); + + iounmap(regs); + + return 0; +} + +static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) +{ + struct device_node *np; + void __iomem *regs; + + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid"); + if (!np) + return -ENODEV; + regs = of_iomap(np, 0); of_node_put(np); if (!regs) { pr_warn("Could not map DBGU iomem range"); - return NULL; + return -ENXIO; } - cidr = readl(regs + AT91_DBGU_CIDR); - exid = readl(regs + AT91_DBGU_EXID); + *cidr = readl(regs + AT91_CHIPID_CIDR); + *exid = readl(regs + AT91_CHIPID_EXID); iounmap(regs); + return 0; +} + +struct soc_device * __init at91_soc_init(const struct at91_soc *socs) +{ + struct soc_device_attribute *soc_dev_attr; + const struct at91_soc *soc; + struct soc_device *soc_dev; + u32 cidr, exid; + int ret; + + /* + * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more + * in the dbgu device but in the chipid device whose purpose is only + * to expose these two registers. + */ + ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid); + if (ret) + ret = at91_get_cidr_exid_from_chipid(&cidr, &exid); + if (ret) { + if (ret == -ENODEV) + pr_warn("Could not find identification node"); + return NULL; + } + for (soc = socs; soc->name; soc++) { - if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK)) + if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK)) continue; - if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid) + if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid) break; } @@ -79,7 +124,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) soc_dev_attr->family = soc->family; soc_dev_attr->soc_id = soc->name; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", - AT91_DBGU_CIDR_VERSION(cidr)); + AT91_CIDR_VERSION(cidr)); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { kfree(soc_dev_attr->revision); @@ -91,7 +136,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) if (soc->family) pr_info("Detected SoC family: %s\n", soc->family); pr_info("Detected SoC: %s, revision %X\n", soc->name, - AT91_DBGU_CIDR_VERSION(cidr)); + AT91_CIDR_VERSION(cidr)); return soc_dev; } -- cgit v1.2.3-59-g8ed1b From c07f98a73978964065b57079cae9ab9d060769fe Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 18 Mar 2016 08:21:20 +0100 Subject: ARM: at91/soc: reference the whole sama5d2 family Add EXID of all SoCs of the SAMA5D2 family. Signed-off-by: Ludovic Desroches Acked-by: Alexandre Belloni Acked-by: Arnd Bergmann Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/sama5.c | 20 +++++++++++++++++++- arch/arm/mach-at91/soc.h | 12 +++++++++++- 2 files changed, 30 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index df8fdf1cf66d..922b85f07cd2 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -18,8 +18,26 @@ #include "soc.h" static const struct at91_soc sama5_socs[] = { - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, + "sama5d21", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH, + "sama5d22", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH, + "sama5d23", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH, + "sama5d24", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH, + "sama5d24", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH, + "sama5d26", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH, "sama5d27", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH, + "sama5d27", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH, + "sama5d28", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH, + "sama5d28", "sama5d2"), AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, "sama5d31", "sama5d3"), AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 8ede0ef86172..228efded5085 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -63,7 +63,17 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 #define SAMA5D2_CIDR_MATCH 0x0a5c08c0 -#define SAMA5D27_EXID_MATCH 0x00000021 +#define SAMA5D21CU_EXID_MATCH 0x0000005a +#define SAMA5D22CU_EXID_MATCH 0x00000059 +#define SAMA5D22CN_EXID_MATCH 0x00000069 +#define SAMA5D23CU_EXID_MATCH 0x00000058 +#define SAMA5D24CX_EXID_MATCH 0x00000004 +#define SAMA5D24CU_EXID_MATCH 0x00000014 +#define SAMA5D26CU_EXID_MATCH 0x00000012 +#define SAMA5D27CU_EXID_MATCH 0x00000011 +#define SAMA5D27CN_EXID_MATCH 0x00000021 +#define SAMA5D28CU_EXID_MATCH 0x00000010 +#define SAMA5D28CN_EXID_MATCH 0x00000020 #define SAMA5D3_CIDR_MATCH 0x0a5c07c0 #define SAMA5D31_EXID_MATCH 0x00444300 -- cgit v1.2.3-59-g8ed1b From 33406c805730377ff48741f9ad99e7aada91595b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 5 May 2015 13:13:57 +0100 Subject: ARM: STi: Update platform level menuconfig 'help' Encompass newer STiH4{07,10} and STiH418 SoC based platforms. Acked-by: Peter Griffin Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/mach-sti/Kconfig | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index a196d14f65f5..6f1af29f935d 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -18,11 +18,10 @@ menuconfig ARCH_STI select PL310_ERRATA_769419 if CACHE_L2X0 select RESET_CONTROLLER help - Include support for STiH41x SOCs like STiH415/416 using the device tree - for discovery - More information at Documentation/arm/STiH41x and - at Documentation/devicetree - + Include support for STMicroelectronics' STiH415/416, STiH407/10 and + STiH418 family SoCs using the Device Tree for discovery. More + information can be found in Documentation/arm/sti/ and + Documentation/devicetree. if ARCH_STI -- cgit v1.2.3-59-g8ed1b From 9ad4d9a38a7f62a4891124501cdce4e768dbba16 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 10 Apr 2016 13:20:09 -0600 Subject: ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Add missing data for all McASP ports for the dra7 family Signed-off-by: Peter Ujfalusi Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 237 ++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 9442d89bd229..7610f3ef28b7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1374,6 +1374,52 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { .sysc = &dra7xx_mcasp_sysc, }; +/* mcasp1 */ +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "mcasp1_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks), +}; + +/* mcasp2 */ +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp2_hwmod = { + .name = "mcasp2", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp2_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks), +}; + /* mcasp3 */ static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = { { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" }, @@ -1396,6 +1442,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = { .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks), }; +/* mcasp4 */ +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp4_hwmod = { + .name = "mcasp4", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp4_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks), +}; + +/* mcasp5 */ +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp5_hwmod = { + .name = "mcasp5", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp5_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks), +}; + +/* mcasp6 */ +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp6_hwmod = { + .name = "mcasp6", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp6_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks), +}; + +/* mcasp7 */ +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp7_hwmod = { + .name = "mcasp7", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp7_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks), +}; + +/* mcasp8 */ +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp8_hwmod = { + .name = "mcasp8", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp8_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks), +}; + /* * 'mmc' class * @@ -2726,6 +2882,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> mcasp3 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { .master = &dra7xx_l4_per2_hwmod, @@ -2742,6 +2930,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp7_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp8_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> elm */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { .master = &dra7xx_l4_per1_hwmod, @@ -3484,8 +3712,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, &dra7xx_l4_per2__cpgmac0, + &dra7xx_l4_per2__mcasp1, + &dra7xx_l3_main_1__mcasp1, + &dra7xx_l4_per2__mcasp2, + &dra7xx_l3_main_1__mcasp2, &dra7xx_l4_per2__mcasp3, &dra7xx_l3_main_1__mcasp3, + &dra7xx_l4_per2__mcasp4, + &dra7xx_l4_per2__mcasp5, + &dra7xx_l4_per2__mcasp6, + &dra7xx_l4_per2__mcasp7, + &dra7xx_l4_per2__mcasp8, &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__tpcc, -- cgit v1.2.3-59-g8ed1b From b05ff3c394bc5dbb1bc88073759f01c0ebdf5de1 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Sun, 10 Apr 2016 13:20:09 -0600 Subject: ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS Add hwmod entries for the PWMSS on DRA7. Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock equal to L4PER2_L3_GICLK/2(l3_iclk_div/2). Signed-off-by: Vignesh R [fcooper@ti.com: Do not add eQEP, ePWM and eCAP hwmod entries] Signed-off-by: Franklin S Cooper Jr [paul@pwsan.com: fixed sparse warnings; added missing comments] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 89 +++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 7610f3ef28b7..2f15cf13e0d7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -383,6 +383,68 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = { }, }; +/* pwmss */ +static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +/* + * epwmss class + */ +static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &dra7xx_epwmss_sysc, +}; + +/* epwmss0 */ +static struct omap_hwmod dra7xx_epwmss0_hwmod = { + .name = "epwmss0", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss1 */ +static struct omap_hwmod dra7xx_epwmss1_hwmod = { + .name = "epwmss1", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss2 */ +static struct omap_hwmod dra7xx_epwmss2_hwmod = { + .name = "epwmss2", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET, + }, + }, +}; + /* * 'dma' class * @@ -3693,6 +3755,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> epwmss0 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss0_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +/* l4_per2 -> epwmss1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +/* l4_per2 -> epwmss2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__dmm, &dra7xx_l3_main_2__l3_instr, @@ -3814,6 +3900,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__vcp2, &dra7xx_l4_per2__vcp2, &dra7xx_l4_wkup__wd_timer2, + &dra7xx_l4_per2__epwmss0, + &dra7xx_l4_per2__epwmss1, + &dra7xx_l4_per2__epwmss2, NULL, }; -- cgit v1.2.3-59-g8ed1b From 461932dfb54ebaf7da438fd8b769a01ce97a9360 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sun, 10 Apr 2016 13:20:10 -0600 Subject: ARM: OMAP2+: hwmod: RTC: Add lock and unlock functions RTC IP have kicker feature which prevents spurious writes to its registers. In order to write into any of the RTC registers, KICK values has to be written to KICK registers. Also, RTC busy flag needs to be polled for non-TC registers as well, without which update is not proper and confirmed it by testing on DRA7-evm. Introduce omap_hwmod_rtc_unlock/lock functions, which writes into these KICK registers inorder to lock and unlock RTC registers. Signed-off-by: Lokesh Vutla [paul@pwsan.com: fixed subject line] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.h | 2 ++ arch/arm/mach-omap2/omap_hwmod_reset.c | 65 ++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 7c7a31169475..4041bad79a9a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -754,6 +754,8 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); */ extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh); +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh); +void omap_hwmod_rtc_lock(struct omap_hwmod *oh); /* * Chip variant-specific hwmod init routines - XXX should be converted diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c index 65e186c9df55..b68f9c0aff0b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_reset.c +++ b/arch/arm/mach-omap2/omap_hwmod_reset.c @@ -29,6 +29,16 @@ #include #include "omap_hwmod.h" +#include "common.h" + +#define OMAP_RTC_STATUS_REG 0x44 +#define OMAP_RTC_KICK0_REG 0x6c +#define OMAP_RTC_KICK1_REG 0x70 + +#define OMAP_RTC_KICK0_VALUE 0x83E70B13 +#define OMAP_RTC_KICK1_VALUE 0x95A4F1E0 +#define OMAP_RTC_STATUS_BUSY BIT(0) +#define OMAP_RTC_MAX_READY_TIME 50 /** * omap_hwmod_aess_preprogram - enable AESS internal autogating @@ -51,3 +61,58 @@ int omap_hwmod_aess_preprogram(struct omap_hwmod *oh) return 0; } + +/** + * omap_rtc_wait_not_busy - Wait for the RTC BUSY flag + * @oh: struct omap_hwmod * + * + * For updating certain RTC registers, the MPU must wait + * for the BUSY status in OMAP_RTC_STATUS_REG to become zero. + * Once the BUSY status is zero, there is a 15 microseconds access + * period in which the MPU can program. + */ +static void omap_rtc_wait_not_busy(struct omap_hwmod *oh) +{ + int i; + + /* BUSY may stay active for 1/32768 second (~30 usec) */ + omap_test_timeout(omap_hwmod_read(oh, OMAP_RTC_STATUS_REG) + & OMAP_RTC_STATUS_BUSY, OMAP_RTC_MAX_READY_TIME, i); + /* now we have ~15 microseconds to read/write various registers */ +} + +/** + * omap_hwmod_rtc_unlock - Unlock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * In order to write into any of the RTC registers, KICK values has te be + * written in respective KICK registers. This is needed for hwmod to write into + * sysconfig register. + */ +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} + +/** + * omap_hwmod_rtc_lock - Lock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * Once the RTC registers are written, KICK mechanism needs to be locked, + * in order to prevent any spurious writes. This function locks back the RTC + * registers once hwmod completes its write into sysconfig register. + */ +void omap_hwmod_rtc_lock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} -- cgit v1.2.3-59-g8ed1b From d7d31b897050ce2c60960ebb6517fc228c52e9bb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sun, 10 Apr 2016 13:20:10 -0600 Subject: ARM: DRA7: RTC: Add lock and unlock functions Hook omap_hwmod_rtc_unlock/lock functions into RTC hwmod, so that SYSCONFIG register is updated properly Signed-off-by: Lokesh Vutla Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 2f15cf13e0d7..ace844b84207 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1925,6 +1925,8 @@ static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { .name = "rtcss", .sysc = &dra7xx_rtcss_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; /* rtcss */ -- cgit v1.2.3-59-g8ed1b From b5a553c08bec14a058501df3fa6eb39f63f00a98 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sun, 10 Apr 2016 13:20:10 -0600 Subject: ARM: AMx3xx: RTC: Add lock and unlock functions Hook omap_hwmod_rtc_unlock/lock functions into RTC hwmod, so that SYSCONFIG register is updated properly. Signed-off-by: Lokesh Vutla Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 907a452b78ea..aed33621deeb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -918,6 +918,8 @@ static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { static struct omap_hwmod_class am33xx_rtc_hwmod_class = { .name = "rtc", .sysc = &am33xx_rtc_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; struct omap_hwmod am33xx_rtc_hwmod = { -- cgit v1.2.3-59-g8ed1b From 22d20cb4876eaee0c64960c69469e3631a61786f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sun, 10 Apr 2016 13:20:11 -0600 Subject: ARM: DRA7: hwmod: Add data for GPTimer 12 Add the hwmod data for GPTimer 12. GPTimer 12 is present in WKUPAON power domain and is clocked from a secure 32K clock. GPTimer 12 serves as a secure timer on HS devices, but is available for kernel on regular GP devices. The hwmod link is registered only on GP devices. The hwmod data also reused the existing timer class instead of reintroducing the identical dra7xx_timer_secure_sysc class which was dropped in commit edec17863362 ("ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4"). Cc: Paul Walmsley Signed-off-by: Suman Anna Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 36 +++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index ace844b84207..d0e7e5259ec3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -2285,6 +2285,20 @@ static struct omap_hwmod dra7xx_timer11_hwmod = { }, }; +/* timer12 */ +static struct omap_hwmod dra7xx_timer12_hwmod = { + .name = "timer12", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "secure_32k_clk_src_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, + }, + }, +}; + /* timer13 */ static struct omap_hwmod dra7xx_timer13_hwmod = { .name = "timer13", @@ -3573,6 +3587,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_wkup -> timer12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_timer12_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per3 -> timer13 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { .master = &dra7xx_l4_per3_hwmod, @@ -3908,6 +3930,13 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { NULL, }; +/* GP-only hwmod links */ +static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l4_wkup__timer12, + NULL, +}; + +/* SoC variant specific hwmod links */ static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, NULL, @@ -3925,9 +3954,12 @@ int __init dra7xx_hwmod_init(void) ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); if (!ret && soc_is_dra74x()) - return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); else if (!ret && soc_is_dra72x()) - return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + + if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) + ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); return ret; } -- cgit v1.2.3-59-g8ed1b From c20c8f750d9f8f8617f07ee2352d3ff560e66bc2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sun, 10 Apr 2016 13:20:11 -0600 Subject: ARM: OMAP2+: hwmod: fix _idle() hwmod state sanity check sequence The omap_hwmod _enable() function can return success without setting the hwmod state to _HWMOD_STATE_ENABLED for IPs with reset lines when all of the reset lines are asserted. The omap_hwmod _idle() function also performs a similar check, but after checking for the hwmod state first. This triggers the WARN when pm_runtime_get and pm_runtime_put are invoked on IPs with all reset lines asserted. Reverse the checks for hwmod state and reset lines status to fix this. Issue found during a unbind operation on a device with reset lines still asserted, example backtrace below ------------[ cut here ]------------ WARNING: CPU: 1 PID: 879 at arch/arm/mach-omap2/omap_hwmod.c:2207 _idle+0x1e4/0x240() omap_hwmod: mmu_dsp: idle state can only be entered from enabled state Modules linked in: CPU: 1 PID: 879 Comm: sh Not tainted 4.4.0-00008-ga989d951331a #3 Hardware name: Generic OMAP5 (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x90/0xc0) [] (dump_stack) from [] (warn_slowpath_common+0x78/0xb4) [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) [] (warn_slowpath_fmt) from [] (_idle+0x1e4/0x240) [] (_idle) from [] (omap_hwmod_idle+0x28/0x48) [] (omap_hwmod_idle) from [] (omap_device_idle+0x3c/0x90) [] (omap_device_idle) from [] (__rpm_callback+0x2c/0x60) [] (__rpm_callback) from [] (rpm_callback+0x20/0x80) [] (rpm_callback) from [] (rpm_suspend+0x138/0x74c) [] (rpm_suspend) from [] (__pm_runtime_idle+0x78/0xa8) [] (__pm_runtime_idle) from [] (__device_release_driver+0x64/0x100) [] (__device_release_driver) from [] (device_release_driver+0x20/0x2c) [] (device_release_driver) from [] (unbind_store+0x78/0xf8) [] (unbind_store) from [] (kernfs_fop_write+0xc0/0x1c4) [] (kernfs_fop_write) from [] (__vfs_write+0x20/0xdc) [] (__vfs_write) from [] (vfs_write+0x90/0x164) [] (vfs_write) from [] (SyS_write+0x44/0x9c) [] (SyS_write) from [] (ret_fast_syscall+0x0/0x1c) ---[ end trace a4182013c75a9f50 ]--- While at this, fix the sequence in _shutdown() as well, though there is no easy reproducible scenario. Fixes: 747834ab8347 ("ARM: OMAP2+: hwmod: revise hardreset behavior") Signed-off-by: Suman Anna Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2af6ff63e3b4..83cb527755a9 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2207,15 +2207,15 @@ static int _idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", oh->name); return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -2262,6 +2262,9 @@ static int _shutdown(struct omap_hwmod *oh) int ret, i; u8 prev_state; + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", @@ -2269,9 +2272,6 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { -- cgit v1.2.3-59-g8ed1b From acc98009b87a811f9f815650274a1044474cd167 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Wed, 6 Apr 2016 17:39:07 +0200 Subject: ARM: imx: always use TWD on IMX6Q There is no reason to limit the TWD to be used on SMP kernels only if the hardware has it available. On Wandboard i.MX6SOLO, running PREEMPT-RT and cyclictest I see as max immediately after start in idle: UP : ~90us SMP: ~50us UP + TWD: ~20us. Based on this numbers I prefer the TWD over the slightly slower MXC timer. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8973fae25436..dd905b9602a0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -526,7 +526,7 @@ config SOC_IMX6Q bool "i.MX6 Quad/DualLite support" select ARM_ERRATA_764369 if SMP select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP + select HAVE_ARM_TWD select PCI_DOMAINS if PCI select PINCTRL_IMX6Q select SOC_IMX6 -- cgit v1.2.3-59-g8ed1b From d86786474babdf1a2b0dfe245e38f18afc203cc2 Mon Sep 17 00:00:00 2001 From: Erin Lo Date: Wed, 13 Apr 2016 15:07:43 +0800 Subject: ARM: mediatek: Add MT2701 config options for mediatek SoCs. The upcoming MTK pinctrl driver have a big pin table for each SoC and we don't want to bloat the kernel binary if we don't need it. Add config options so we can build for one SoC only. Add MT2701. Signed-off-by: Erin Lo Acked-by: Linus Walleij Signed-off-by: Matthias Brugger --- arch/arm/mach-mediatek/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 8ced4ad94af0..70e49d54434e 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -10,6 +10,10 @@ menuconfig ARCH_MEDIATEK if ARCH_MEDIATEK +config MACH_MT2701 + bool "MediaTek MT2701 SoCs support" + default ARCH_MEDIATEK + config MACH_MT6589 bool "MediaTek MT6589 SoCs support" default ARCH_MEDIATEK -- cgit v1.2.3-59-g8ed1b From e60ba933bc94b778425612c039a16b3acd4bf756 Mon Sep 17 00:00:00 2001 From: Jonas Rabenstein Date: Wed, 6 Apr 2016 10:14:08 +0200 Subject: ARM: OMAP2+: remove redundant multiplatform checks The directory arch/arm/mach-omap2 is only selected for compilation if CONFIG_ARCH_OMAP2PLUS is selected. CONFIG_ARCH_OMAP2PLUS itself is a silent option and all machines selecting this option are multiplatform devices. As a consequence checks for CONFIG_ARCH_MULTIPLATFORM as well as CONFIG_ARCH_OMAP2PLUS within that directory are superfluous and can be removed. Signed-off-by: Jonas Rabenstein Reviewed-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/soc.h | 140 +++++++------------------------------------ 2 files changed, 22 insertions(+), 120 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 0ba6a0e6fa19..04e276ce8413 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ +ccflags-y := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-omap/include # Common support diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 70df8f6cddcc..8862c095095f 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -39,82 +39,10 @@ #include /* - * Test if multicore OMAP support is needed + * OMAP2+ is always defined as ARCH_MULTIPLATFORM in Kconfig */ #undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_MULTIPLATFORM #define MULTI_OMAP2 -#endif -#ifdef CONFIG_SOC_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_SOC_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP4 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap4 -# endif -#endif - -#ifdef CONFIG_SOC_OMAP5 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap5 -# endif -#endif - -#ifdef CONFIG_SOC_AM33XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am33xx -# endif -#endif - -#ifdef CONFIG_SOC_AM43XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am43xx -# endif -#endif - -#ifdef CONFIG_SOC_DRA7XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME DRA7XX -# endif -#endif /* * Omap device type i.e. EMU/HS/TST/GP/BAD @@ -242,11 +170,6 @@ IS_AM_SUBCLASS(437x, 0x437) IS_DRA_SUBCLASS(75x, 0x75) IS_DRA_SUBCLASS(72x, 0x72) -#define soc_is_omap24xx() 0 -#define soc_is_omap242x() 0 -#define soc_is_omap243x() 0 -#define soc_is_omap34xx() 0 -#define soc_is_omap343x() 0 #define soc_is_ti81xx() 0 #define soc_is_ti816x() 0 #define soc_is_ti814x() 0 @@ -265,46 +188,27 @@ IS_DRA_SUBCLASS(72x, 0x72) #define soc_is_dra74x() 0 #define soc_is_dra72x() 0 -#if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP2) -# undef soc_is_omap24xx -# define soc_is_omap24xx() is_omap24xx() -# endif -# if defined (CONFIG_SOC_OMAP2420) -# undef soc_is_omap242x -# define soc_is_omap242x() is_omap242x() -# endif -# if defined (CONFIG_SOC_OMAP2430) -# undef soc_is_omap243x -# define soc_is_omap243x() is_omap243x() -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef soc_is_omap34xx -# undef soc_is_omap343x -# define soc_is_omap34xx() is_omap34xx() -# define soc_is_omap343x() is_omap343x() -# endif +#if defined(CONFIG_ARCH_OMAP2) +# define soc_is_omap24xx() is_omap24xx() #else -# if defined(CONFIG_ARCH_OMAP2) -# undef soc_is_omap24xx -# define soc_is_omap24xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP2420) -# undef soc_is_omap242x -# define soc_is_omap242x() 1 -# endif -# if defined(CONFIG_SOC_OMAP2430) -# undef soc_is_omap243x -# define soc_is_omap243x() 1 -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef soc_is_omap34xx -# define soc_is_omap34xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP3430) -# undef soc_is_omap343x -# define soc_is_omap343x() 1 -# endif +# define soc_is_omap24xx() 0 +#endif +#if defined(CONFIG_SOC_OMAP2420) +# define soc_is_omap242x() is_omap242x() +#else +# define soc_is_omap242x() 0 +#endif +#if defined(CONFIG_SOC_OMAP2430) +# define soc_is_omap243x() is_omap243x() +#else +# define soc_is_omap243x() 0 +#endif +#if defined(CONFIG_ARCH_OMAP3) +# define soc_is_omap34xx() is_omap34xx() +# define soc_is_omap343x() is_omap343x() +#else +# define soc_is_omap34xx() 0 +# define soc_is_omap343x() 0 #endif /* @@ -339,7 +243,6 @@ IS_OMAP_TYPE(3430, 0x3430) #define soc_is_omap5430() 0 /* These are needed for the common code */ -#ifdef CONFIG_ARCH_OMAP2PLUS #define soc_is_omap7xx() 0 #define soc_is_omap15xx() 0 #define soc_is_omap16xx() 0 @@ -350,7 +253,6 @@ IS_OMAP_TYPE(3430, 0x3430) #define soc_is_omap1710() 0 #define cpu_class_is_omap1() 0 #define cpu_class_is_omap2() 1 -#endif #if defined(CONFIG_ARCH_OMAP2) # undef soc_is_omap2420 -- cgit v1.2.3-59-g8ed1b From f971512c78ee675c0308f1cda483a57e5de6769f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 31 Mar 2016 16:58:33 -0500 Subject: ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA Erratum i892 as will be documented in the upcoming G or later revision of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock needs to be kept active all the time to ensure that asymmetric aging degradation is minimal and within the design allowed margin. By allowing core domain to transition to INA and allowing L3 clock to be turned off for extended periods of time, there is a risk of functional issues and device failure as a result. Ref: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/powerdomains7xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 287a2037aa16..f2b4557124f3 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -160,7 +160,7 @@ static struct powerdomain core_7xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_INA_ON, + .pwrsts = PWRSTS_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { -- cgit v1.2.3-59-g8ed1b From 41feb8efd636c99ff73a2e6b8b4a57e2dd569b4b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 31 Mar 2016 16:58:34 -0500 Subject: ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories When the power domain is in "ON" state, the memories should be always in "ON", even though the hardware register allows other states to be written, wrong states may confuse certain hardware blocks. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/powerdomains7xx_data.c | 66 +++++++++++++++--------------- 1 file changed, 33 insertions(+), 33 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index f2b4557124f3..81e883d972b9 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -45,10 +45,10 @@ static struct powerdomain iva_7xx_pwrdm = { [3] = PWRSTS_OFF_RET, /* tcm2_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* hwa_mem */ - [1] = PWRSTS_OFF_RET, /* sl2_mem */ - [2] = PWRSTS_OFF_RET, /* tcm1_mem */ - [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + [0] = PWRSTS_ON, /* hwa_mem */ + [1] = PWRSTS_ON, /* sl2_mem */ + [2] = PWRSTS_ON, /* tcm1_mem */ + [3] = PWRSTS_ON, /* tcm2_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -83,8 +83,8 @@ static struct powerdomain ipu_7xx_pwrdm = { [1] = PWRSTS_OFF_RET, /* periphmem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* aessmem */ - [1] = PWRSTS_OFF_RET, /* periphmem */ + [0] = PWRSTS_ON, /* aessmem */ + [1] = PWRSTS_ON, /* periphmem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -101,7 +101,7 @@ static struct powerdomain dss_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* dss_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dss_mem */ + [0] = PWRSTS_ON, /* dss_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -119,8 +119,8 @@ static struct powerdomain l4per_7xx_pwrdm = { [1] = PWRSTS_OFF_RET, /* retained_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* nonretained_bank */ - [1] = PWRSTS_OFF_RET, /* retained_bank */ + [0] = PWRSTS_ON, /* nonretained_bank */ + [1] = PWRSTS_ON, /* retained_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -136,7 +136,7 @@ static struct powerdomain gpu_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* gpu_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gpu_mem */ + [0] = PWRSTS_ON, /* gpu_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -171,11 +171,11 @@ static struct powerdomain core_7xx_pwrdm = { [4] = PWRSTS_OFF_RET, /* ipu_unicache */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* core_nret_bank */ - [1] = PWRSTS_OFF_RET, /* core_ocmram */ - [2] = PWRSTS_OFF_RET, /* core_other_bank */ - [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ - [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + [0] = PWRSTS_ON, /* core_nret_bank */ + [1] = PWRSTS_ON, /* core_ocmram */ + [2] = PWRSTS_ON, /* core_other_bank */ + [3] = PWRSTS_ON, /* ipu_l2ram */ + [4] = PWRSTS_ON, /* ipu_unicache */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -232,7 +232,7 @@ static struct powerdomain vpe_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* vpe_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vpe_bank */ + [0] = PWRSTS_ON, /* vpe_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -250,8 +250,8 @@ static struct powerdomain mpu_7xx_pwrdm = { [1] = PWRSTS_RET, /* mpu_ram */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* mpu_l2 */ - [1] = PWRSTS_OFF_RET, /* mpu_ram */ + [0] = PWRSTS_ON, /* mpu_l2 */ + [1] = PWRSTS_ON, /* mpu_ram */ }, }; @@ -269,9 +269,9 @@ static struct powerdomain l3init_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gmac_bank */ - [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ - [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ + [0] = PWRSTS_ON, /* gmac_bank */ + [1] = PWRSTS_ON, /* l3init_bank1 */ + [2] = PWRSTS_ON, /* l3init_bank2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -287,7 +287,7 @@ static struct powerdomain eve3_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve3_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve3_bank */ + [0] = PWRSTS_ON, /* eve3_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -303,7 +303,7 @@ static struct powerdomain emu_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* emu_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* emu_bank */ + [0] = PWRSTS_ON, /* emu_bank */ }, }; @@ -320,9 +320,9 @@ static struct powerdomain dsp2_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp2_edma */ - [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ + [0] = PWRSTS_ON, /* dsp2_edma */ + [1] = PWRSTS_ON, /* dsp2_l1 */ + [2] = PWRSTS_ON, /* dsp2_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -340,9 +340,9 @@ static struct powerdomain dsp1_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp1_edma */ - [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ + [0] = PWRSTS_ON, /* dsp1_edma */ + [1] = PWRSTS_ON, /* dsp1_l1 */ + [2] = PWRSTS_ON, /* dsp1_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -358,7 +358,7 @@ static struct powerdomain cam_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* vip_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vip_bank */ + [0] = PWRSTS_ON, /* vip_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -374,7 +374,7 @@ static struct powerdomain eve4_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve4_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve4_bank */ + [0] = PWRSTS_ON, /* eve4_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -390,7 +390,7 @@ static struct powerdomain eve2_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve2_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve2_bank */ + [0] = PWRSTS_ON, /* eve2_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -406,7 +406,7 @@ static struct powerdomain eve1_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve1_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve1_bank */ + [0] = PWRSTS_ON, /* eve1_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; -- cgit v1.2.3-59-g8ed1b From dac4fba2cd8b34e175e54e4740816a1a4de3dcc9 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 31 Mar 2016 16:58:35 -0500 Subject: ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability Open Switch Retention(OSWR) is a retention state which is unsupported in DRA7 SoC. This state is achieved when power state is set to retention and logic power state is set to OFF. Even though DRA7 architecture is a OMAP derivative, none of the powerdomains are actually implemented to achieve OSWR in the SoC. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/powerdomains7xx_data.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 81e883d972b9..0ec2d00f4237 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -35,7 +35,7 @@ static struct powerdomain iva_7xx_pwrdm = { .name = "iva_pwrdm", .prcm_offs = DRA7XX_PRM_IVA_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 4, .pwrsts_mem_ret = { @@ -75,7 +75,7 @@ static struct powerdomain ipu_7xx_pwrdm = { .name = "ipu_pwrdm", .prcm_offs = DRA7XX_PRM_IPU_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 2, .pwrsts_mem_ret = { @@ -94,7 +94,7 @@ static struct powerdomain dss_7xx_pwrdm = { .name = "dss_pwrdm", .prcm_offs = DRA7XX_PRM_DSS_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { @@ -112,7 +112,7 @@ static struct powerdomain l4per_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_L4PER_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* nonretained_bank */ @@ -225,8 +225,8 @@ static struct powerdomain vpe_7xx_pwrdm = { .name = "vpe_pwrdm", .prcm_offs = DRA7XX_PRM_VPE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_OFF_ON, + .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* vpe_bank */ @@ -261,7 +261,7 @@ static struct powerdomain l3init_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_L3INIT_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 3, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* gmac_bank */ -- cgit v1.2.3-59-g8ed1b From 814a9586fdeb8cce4f6661288fada4a6ae94a94f Mon Sep 17 00:00:00 2001 From: Anna-Maria Gleixner Date: Mon, 4 Apr 2016 14:55:17 +0200 Subject: ARM: OMAP2+: wakeupgen: Add comment for unhandled FROZEN transitions FROZEN hotplug notifiers are not handled and do not have to be. Insert a comment to remember that the lack of the FROZEN transitions is no accident. Cc: Tony Lindgren Cc: Santosh Shilimkar Cc: linux-omap@vger.kernel.org Signed-off-by: Anna-Maria Gleixner Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-wakeupgen.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index f397bd6bd6e3..f436ccb6137b 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -320,6 +320,11 @@ static int irq_cpu_hotplug_notify(struct notifier_block *self, { unsigned int cpu = (unsigned int)hcpu; + /* + * Corresponding FROZEN transitions do not have to be handled, + * they are handled by at a higher level + * (drivers/cpuidle/coupled.c). + */ switch (action) { case CPU_ONLINE: wakeupgen_irqmask_all(cpu, 0); -- cgit v1.2.3-59-g8ed1b From 86cad16087a8cdad88c1ac124afde4de01500c21 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 24 Mar 2016 18:51:28 -0500 Subject: ARM: davinci: da8xx: move usb code to new file We will be adding more da8xx-specific code for phy and clocks, so it will be better to have this in a separate file. This way we don't have a bunch of #ifdefs for all of the da8xx stuff. While at it, fix some checkpatch warnings coming from existing code. Signed-off-by: David Lechner [nsekhar@ti.com: typo and checkpatch fixes] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/Makefile | 4 +- arch/arm/mach-davinci/usb-da8xx.c | 107 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-davinci/usb.c | 73 -------------------------- 3 files changed, 109 insertions(+), 75 deletions(-) create mode 100644 arch/arm/mach-davinci/usb-da8xx.c (limited to 'arch') diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 2e3464b8bab4..da4c336b4637 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -14,8 +14,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c new file mode 100644 index 000000000000..f141f5171906 --- /dev/null +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -0,0 +1,107 @@ +/* + * DA8xx USB + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DA8XX_USB0_BASE 0x01e00000 +#define DA8XX_USB1_BASE 0x01e25000 + +#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) + +static struct musb_hdrc_config musb_config = { + .multipoint = true, + .num_eps = 5, + .ram_bits = 10, +}; + +static struct musb_hdrc_platform_data usb_data = { + /* OTG requires a Mini-AB connector */ + .mode = MUSB_OTG, + .clock = "usb20", + .config = &musb_config, +}; + +static struct resource da8xx_usb20_resources[] = { + { + .start = DA8XX_USB0_BASE, + .end = DA8XX_USB0_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_USB_INT, + .flags = IORESOURCE_IRQ, + .name = "mc", + }, +}; + +static u64 usb_dmamask = DMA_BIT_MASK(32); + +static struct platform_device usb_dev = { + .name = "musb-da8xx", + .id = -1, + .dev = { + .platform_data = &usb_data, + .dma_mask = &usb_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da8xx_usb20_resources, + .num_resources = ARRAY_SIZE(da8xx_usb20_resources), +}; + +int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) +{ + usb_data.power = mA > 510 ? 255 : mA / 2; + usb_data.potpgt = (potpgt + 1) / 2; + + return platform_device_register(&usb_dev); +} + +#else + +int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) +{ + return 0; +} + +#endif /* CONFIG_USB_MUSB_HDRC */ + +static struct resource da8xx_usb11_resources[] = { + [0] = { + .start = DA8XX_USB1_BASE, + .end = DA8XX_USB1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_IRQN, + .end = IRQ_DA8XX_IRQN, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device da8xx_usb11_device = { + .name = "ohci", + .id = 0, + .dev = { + .dma_mask = &da8xx_usb11_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(da8xx_usb11_resources), + .resource = da8xx_usb11_resources, +}; + +int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) +{ + da8xx_usb11_device.dev.platform_data = pdata; + return platform_device_register(&da8xx_usb11_device); +} diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index 6ed5a54ae74d..0e7e89c1f331 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -10,14 +10,10 @@ #include #include #include -#include #include #define DAVINCI_USB_OTG_BASE 0x01c64000 -#define DA8XX_USB0_BASE 0x01e00000 -#define DA8XX_USB1_BASE 0x01e25000 - #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) static struct musb_hdrc_config musb_config = { .multipoint = true, @@ -81,79 +77,10 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) platform_device_register(&usb_dev); } -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -static struct resource da8xx_usb20_resources[] = { - { - .start = DA8XX_USB0_BASE, - .end = DA8XX_USB0_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DA8XX_USB_INT, - .flags = IORESOURCE_IRQ, - .name = "mc", - }, -}; - -int __init da8xx_register_usb20(unsigned mA, unsigned potpgt) -{ - usb_data.clock = "usb20"; - usb_data.power = mA > 510 ? 255 : mA / 2; - usb_data.potpgt = (potpgt + 1) / 2; - - usb_dev.resource = da8xx_usb20_resources; - usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources); - usb_dev.name = "musb-da8xx"; - - return platform_device_register(&usb_dev); -} -#endif /* CONFIG_DAVINCI_DA8XX */ - #else void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) { } -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -int __init da8xx_register_usb20(unsigned mA, unsigned potpgt) -{ - return 0; -} -#endif - #endif /* CONFIG_USB_MUSB_HDRC */ - -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -static struct resource da8xx_usb11_resources[] = { - [0] = { - .start = DA8XX_USB1_BASE, - .end = DA8XX_USB1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DA8XX_IRQN, - .end = IRQ_DA8XX_IRQN, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device da8xx_usb11_device = { - .name = "ohci", - .id = 0, - .dev = { - .dma_mask = &da8xx_usb11_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(da8xx_usb11_resources), - .resource = da8xx_usb11_resources, -}; - -int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) -{ - da8xx_usb11_device.dev.platform_data = pdata; - return platform_device_register(&da8xx_usb11_device); -} -#endif /* CONFIG_DAVINCI_DA8XX */ -- cgit v1.2.3-59-g8ed1b From 8a9d088f66f84d7317b4adc64d3d3114f1ee8583 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 24 Mar 2016 18:51:30 -0500 Subject: ARM: davinci: clk: add set_parent callback for mux clocks Introduce a set_parent callback that will be used for mux clocks, such as the USB PHY muxes and the async3 clock domain mux. Signed-off-by: David Lechner [nsekhar@ti.com: checkpatch fixes] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/clock.c | 19 ++++++++++++++++++- arch/arm/mach-davinci/clock.h | 1 + 2 files changed, 19 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 3424eac6b588..34b4f9fda35d 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -195,6 +195,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent) return -EINVAL; mutex_lock(&clocks_mutex); + if (clk->set_parent) { + int ret = clk->set_parent(clk, parent); + + if (ret) { + mutex_unlock(&clocks_mutex); + return ret; + } + } clk->parent = parent; list_del_init(&clk->childnode); list_add(&clk->childnode, &clk->parent->children); @@ -224,8 +232,17 @@ int clk_register(struct clk *clk) mutex_lock(&clocks_mutex); list_add_tail(&clk->node, &clocks); - if (clk->parent) + if (clk->parent) { + if (clk->set_parent) { + int ret = clk->set_parent(clk, clk->parent); + + if (ret) { + mutex_unlock(&clocks_mutex); + return ret; + } + } list_add_tail(&clk->childnode, &clk->parent->children); + } mutex_unlock(&clocks_mutex); /* If rate is already set, use it */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 1e4e836173a1..e2a5437a1aee 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -106,6 +106,7 @@ struct clk { int (*reset) (struct clk *clk, bool reset); void (*clk_enable) (struct clk *clk); void (*clk_disable) (struct clk *clk); + int (*set_parent) (struct clk *clk, struct clk *parent); }; /* Clock flags: SoC-specific flags start at BIT(16) */ -- cgit v1.2.3-59-g8ed1b From a4b8c18c40704c28be62af4606cc6758c9ff3dba Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Apr 2016 10:33:16 +0200 Subject: ARM: shmobile: timer: Drop support for Cortex A8 Commit edf4100906044225 ("ARM: shmobile: sh7372 dtsi: Remove Legacy file") removed the DTS for the last shmobile SoC with a Cortex A8 CPU core (sh7372 aka SH-Mobile AP4), hence drop support for it in the loops-per-jiffy preset code. As "div" is always 1 for supported contemporary ARM processors, we can simplify the code: - Absorb shmobile_setup_delay_hz(), which was always called with mult = div = 1, - Return earlier if the Cortex A7/A15 arch timer exists and support is enabled. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/timer.c | 52 ++++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 67d79f9c6bad..6196a6380385 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -20,28 +20,9 @@ #include "common.h" -static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz, - unsigned int mult, unsigned int div) -{ - /* calculate a worst-case loops-per-jiffy value - * based on maximum cpu core hz setting and the - * __delay() implementation in arch/arm/lib/delay.S - * - * this will result in a longer delay than expected - * when the cpu core runs on lower frequencies. - */ - - unsigned int value = HZ * div / mult; - - if (!preset_lpj) - preset_lpj = max_cpu_core_hz / value; -} - void __init shmobile_init_delay(void) { struct device_node *np, *cpus; - unsigned int div = 0; - bool has_arch_timer = false; u32 max_freq = 0; cpus = of_find_node_by_path("/cpus"); @@ -51,25 +32,32 @@ void __init shmobile_init_delay(void) for_each_child_of_node(cpus, np) { u32 freq; + if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER) && + (of_device_is_compatible(np, "arm,cortex-a7") || + of_device_is_compatible(np, "arm,cortex-a15"))) { + of_node_put(np); + of_node_put(cpus); + return; + } + if (!of_property_read_u32(np, "clock-frequency", &freq)) max_freq = max(max_freq, freq); - - if (of_device_is_compatible(np, "arm,cortex-a8")) { - div = 2; - } else if (of_device_is_compatible(np, "arm,cortex-a9")) { - div = 1; - } else if (of_device_is_compatible(np, "arm,cortex-a7") || - of_device_is_compatible(np, "arm,cortex-a15")) { - div = 1; - has_arch_timer = true; - } } of_node_put(cpus); - if (!max_freq || !div) + if (!max_freq) return; - if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) - shmobile_setup_delay_hz(max_freq, 1, div); + /* + * Calculate a worst-case loops-per-jiffy value + * based on maximum cpu core hz setting and the + * __delay() implementation in arch/arm/lib/delay.S. + * + * This will result in a longer delay than expected + * when the cpu core runs on lower frequencies. + */ + + if (!preset_lpj) + preset_lpj = max_freq / HZ; } -- cgit v1.2.3-59-g8ed1b From 01bbcdffa90d13f61d8034ef82a68484edbc2f5c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 15 Apr 2016 19:48:29 +0900 Subject: ARM: uniphier: correct the call order of of_node_put() Put nodes after of_address_to_resource() in case the nodes might be released while parsing in them. Signed-off-by: Masahiro Yamada Signed-off-by: Arnd Bergmann --- arch/arm/mach-uniphier/platsmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-uniphier/platsmp.c b/arch/arm/mach-uniphier/platsmp.c index 69141357afe8..8693b7c15d59 100644 --- a/arch/arm/mach-uniphier/platsmp.c +++ b/arch/arm/mach-uniphier/platsmp.c @@ -99,16 +99,16 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus) int ret; np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-smpctrl"); - of_node_put(np); ret = of_address_to_resource(np, 0, &res); + of_node_put(np); if (!ret) { rom_rsv2_phys = res.start + UNIPHIER_SMPCTRL_ROM_RSV2; } else { /* try old binding too */ np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-system-bus-controller"); - of_node_put(np); ret = of_address_to_resource(np, 1, &res); + of_node_put(np); if (ret) { pr_err("failed to get resource of SMP control\n"); return ret; -- cgit v1.2.3-59-g8ed1b From 8c9184b7d95859b24bba1201780886aabdab8ce1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 3 Mar 2016 10:42:15 +0100 Subject: ARM: Add new mach-oxnas Add mach-oxnas directory containing Kconfig. Signed-off-by: Neil Armstrong --- arch/arm/Kconfig | 2 ++ arch/arm/mach-oxnas/Kconfig | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/mach-oxnas/Kconfig (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdfa6c2b7626..4d48e23ece0a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -804,6 +804,8 @@ source "arch/arm/plat-pxa/Kconfig" source "arch/arm/mach-mmp/Kconfig" +source "arch/arm/mach-oxnas/Kconfig" + source "arch/arm/mach-qcom/Kconfig" source "arch/arm/mach-realview/Kconfig" diff --git a/arch/arm/mach-oxnas/Kconfig b/arch/arm/mach-oxnas/Kconfig new file mode 100644 index 000000000000..4fff3c7666df --- /dev/null +++ b/arch/arm/mach-oxnas/Kconfig @@ -0,0 +1,24 @@ +menuconfig ARCH_OXNAS + bool "Oxford Semiconductor OXNAS Family SoCs" + select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_RESET_CONTROLLER + select PINCTRL + depends on ARCH_MULTI_V5 + help + Support for OxNas SoC family developed by Oxford Semiconductor. + +if ARCH_OXNAS + +config MACH_OX810SE + bool "Support OX810SE Based Products" + select ARM_TIMER_SP804 + select COMMON_CLK_OXNAS + select CPU_ARM926T + select MFD_SYSCON + select PINCTRL_OXNAS + select RESET_OXNAS + select VERSATILE_FPGA_IRQ + help + Include Support for the Oxford Semiconductor OX810SE SoC Based Products. + +endif -- cgit v1.2.3-59-g8ed1b From 1847119dcc9841120dbdc45c0d049f37beed7a71 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 25 Apr 2016 09:49:13 +0100 Subject: ARM: vexpress/mps2: introduce MPS2 platform The Cortex-M Prototyping System (or V2M-MPS2) is designed for prototyping and evaluation Cortex-M family of processors including the latest Cortex-M7 It comes with a range of useful peripherals including 8MB single cycle SRAM, 16MB PSRAM, Ethernet, QSVGA touch screen panel, 4bit RGB VGA connector, Audio, SPI and GPIO. Signed-off-by: Vladimir Murzin Signed-off-by: Sudeep Holla --- arch/arm/Kconfig | 12 ++++++++++++ arch/arm/Makefile | 1 + arch/arm/mach-vexpress/Makefile | 4 +++- arch/arm/mach-vexpress/Makefile.boot | 3 +++ arch/arm/mach-vexpress/v2m-mps2.c | 21 +++++++++++++++++++++ 5 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-vexpress/Makefile.boot create mode 100644 arch/arm/mach-vexpress/v2m-mps2.c (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdfa6c2b7626..6cda5dc5575b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -892,6 +892,18 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config ARCH_MPS2 + bool "ARM MPS2 paltform" + depends on ARM_SINGLE_ARMV7M + select ARM_AMBA + select CLKSRC_MPS2 + help + Support for Cortex-M Prototyping System (or V2M-MPS2) which comes + with a range of available cores like Cortex-M3/M4/M7. + + Please, note that depends which Application Note is used memory map + for the platform may vary, so adjustment of RAM base might be needed. + # Definitions to make life easier config ARCH_ACORN bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8c3ce2ac44c4..274e8a6582f1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp +machine-$(CONFIG_ARCH_MPS2) += vexpress machine-$(CONFIG_ARCH_MOXART) += moxart machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index f5c1006dd6a1..73caae71f307 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -4,7 +4,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \ -I$(srctree)/arch/arm/plat-versatile/include -obj-y := v2m.o +obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o CFLAGS_dcscb.o += -march=armv7-a CFLAGS_REMOVE_dcscb.o = -pg @@ -15,3 +15,5 @@ CFLAGS_tc2_pm.o += -march=armv7-a CFLAGS_REMOVE_tc2_pm.o = -pg obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot new file mode 100644 index 000000000000..eacfc3f5c33e --- /dev/null +++ b/arch/arm/mach-vexpress/Makefile.boot @@ -0,0 +1,3 @@ +# Empty file waiting for deletion once Makefile.boot isn't needed any more. +# Patch waits for application at +# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-vexpress/v2m-mps2.c b/arch/arm/mach-vexpress/v2m-mps2.c new file mode 100644 index 000000000000..e7ad9c27231c --- /dev/null +++ b/arch/arm/mach-vexpress/v2m-mps2.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +static const char *const mps2_compat[] __initconst = { + "arm,mps2", + NULL +}; + +DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)") + .dt_compat = mps2_compat, +MACHINE_END -- cgit v1.2.3-59-g8ed1b From 6fc9ebbdeb75197df780c52f5ebcc3eeffb9cd91 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 14 Apr 2016 14:13:35 -0500 Subject: ARM: davinci: Move clock init after ioremap. Some clocks (such as the USB PHY clocks in DA8xx) will need to use iomem. The davinci_common_init() function must be called before the ioremap, so the clock init is now split out as separate function. Signed-off-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/clock.c | 2 +- arch/arm/mach-davinci/common.c | 6 ------ arch/arm/mach-davinci/da830.c | 2 ++ arch/arm/mach-davinci/da850.c | 2 ++ arch/arm/mach-davinci/dm355.c | 1 + arch/arm/mach-davinci/dm365.c | 1 + arch/arm/mach-davinci/dm644x.c | 1 + arch/arm/mach-davinci/dm646x.c | 1 + 8 files changed, 9 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 34b4f9fda35d..df42c93a93d6 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -577,7 +577,7 @@ EXPORT_SYMBOL(davinci_set_pllrate); * than that used by default in .c file. The reference clock rate * should be updated early in the boot process; ideally soon after the * clock tree has been initialized once with the default reference clock - * rate (davinci_common_init()). + * rate (davinci_clk_init()). * * Returns 0 on success, error otherwise. */ diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index f55ef2ef2f92..6bc8c22b8ace 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -103,12 +103,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info) if (ret < 0) goto err; - if (davinci_soc_info.cpu_clks) { - ret = davinci_clk_init(davinci_soc_info.cpu_clks); - - if (ret != 0) - goto err; - } return; diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 7187e7fc2822..426fd7477357 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -1214,4 +1214,6 @@ void __init da830_init(void) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); + + davinci_clk_init(davinci_soc_info_da830.cpu_clks); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 97d8779a9a65..1f85bbca2e55 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1346,4 +1346,6 @@ void __init da850_init(void) v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); v &= ~CFGCHIP3_PLL1_MASTER_LOCK; __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + davinci_clk_init(davinci_soc_info_da850.cpu_clks); } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index a0ecf499c2f2..5a19cca7ed6a 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -1052,6 +1052,7 @@ void __init dm355_init(void) { davinci_common_init(&davinci_soc_info_dm355); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm355.cpu_clks); } int __init dm355_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 384d3674dd9b..8aa004b02fe9 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -1176,6 +1176,7 @@ void __init dm365_init(void) { davinci_common_init(&davinci_soc_info_dm365); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm365.cpu_clks); } static struct resource dm365_vpss_resources[] = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index b4b3a8b9ca20..0afa279ec460 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -932,6 +932,7 @@ void __init dm644x_init(void) { davinci_common_init(&davinci_soc_info_dm644x); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm644x.cpu_clks); } int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index a43db0f5fbaa..da21353cac45 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -956,6 +956,7 @@ void __init dm646x_init(void) { davinci_common_init(&davinci_soc_info_dm646x); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm646x.cpu_clks); } static int __init dm646x_init_devices(void) -- cgit v1.2.3-59-g8ed1b From 3f2a09d57bb12ca55f92209b3ef0c0684cdb20b0 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 14 Apr 2016 14:13:36 -0500 Subject: ARM: davinci: da850: use clk->set_parent for async3 The da850 family of processors has an async3 clock domain that can be muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks have a set_parent callback, we can use this to control the async3 mux instead of a stand-alone function. This adds a new async3_clk and sets the appropriate child clocks. The default is use to pll1_sysclk2 since it is not affected by processor frequency scaling. Signed-off-by: David Lechner [nsekhar@ti.com: drop unnecessary comment] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/da850.c | 81 ++++++++++++++++++------------------------- 1 file changed, 33 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 1f85bbca2e55..239886299968 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -34,9 +34,6 @@ #include "clock.h" #include "mux.h" -/* SoC specific clock flags */ -#define DA850_CLK_ASYNC3 BIT(16) - #define DA850_PLL1_BASE 0x01e1a000 #define DA850_TIMER64P2_BASE 0x01f0c000 #define DA850_TIMER64P3_BASE 0x01f0d000 @@ -161,6 +158,32 @@ static struct clk pll1_sysclk3 = { .div_reg = PLLDIV3, }; +static int da850_async3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + if (parent == &pll0_sysclk2) { + val &= ~CFGCHIP3_ASYNC3_CLKSRC; + } else if (parent == &pll1_sysclk2) { + val |= CFGCHIP3_ASYNC3_CLKSRC; + } else { + pr_err("Bad parent on async3 clock mux\n"); + return -EINVAL; + } + + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + return 0; +} + +static struct clk async3_clk = { + .name = "async3", + .parent = &pll1_sysclk2, + .set_parent = da850_async3_set_parent, +}; + static struct clk i2c0_clk = { .name = "i2c0", .parent = &pll0_aux_clk, @@ -234,18 +257,16 @@ static struct clk uart0_clk = { static struct clk uart1_clk = { .name = "uart1", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_UART1, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk uart2_clk = { .name = "uart2", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_UART2, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk aintc_clk = { @@ -300,10 +321,9 @@ static struct clk emac_clk = { static struct clk mcasp_clk = { .name = "mcasp", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_McASP0, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk lcdc_clk = { @@ -355,10 +375,9 @@ static struct clk spi0_clk = { static struct clk spi1_clk = { .name = "spi1", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_SPI1, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk vpif_clk = { @@ -386,10 +405,9 @@ static struct clk dsp_clk = { static struct clk ehrpwm_clk = { .name = "ehrpwm", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_PWM, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) @@ -421,10 +439,9 @@ static struct clk ehrpwm_tbclk = { static struct clk ecap_clk = { .name = "ecap", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_ECAP, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk_lookup da850_clks[] = { @@ -442,6 +459,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "pll1_aux", &pll1_aux_clk), CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "async3", &async3_clk), CLK("i2c_davinci.1", NULL, &i2c0_clk), CLK(NULL, "timer0", &timerp64_0_clk), CLK("davinci-wdt", NULL, &timerp64_1_clk), @@ -909,30 +927,6 @@ static struct davinci_timer_info da850_timer_info = { .clocksource_id = T0_TOP, }; -static void da850_set_async3_src(int pllnum) -{ - struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; - struct clk_lookup *c; - unsigned int v; - int ret; - - for (c = da850_clks; c->clk; c++) { - clk = c->clk; - if (clk->flags & DA850_CLK_ASYNC3) { - ret = clk_set_parent(clk, newparent); - WARN(ret, "DA850: unable to re-parent clock %s", - clk->name); - } - } - - v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); - if (pllnum) - v |= CFGCHIP3_ASYNC3_CLKSRC; - else - v &= ~CFGCHIP3_ASYNC3_CLKSRC; - __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); -} - #ifdef CONFIG_CPU_FREQ /* * Notes: @@ -1328,15 +1322,6 @@ void __init da850_init(void) if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) return; - /* - * Move the clock source of Async3 domain to PLL1 SYSCLK2. - * This helps keeping the peripherals on this domain insulated - * from CPU frequency changes caused by DVFS. The firmware sets - * both PLL0 and PLL1 to the same frequency so, there should not - * be any noticeable change even in non-DVFS use cases. - */ - da850_set_async3_src(1); - /* Unlock writing to PLL0 registers */ v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); v &= ~CFGCHIP0_PLL_MASTER_LOCK; -- cgit v1.2.3-59-g8ed1b From 313a98faf1e33945c59872da5a0425260ffb39b5 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 19 Apr 2016 18:40:04 -0700 Subject: ARM: mv78xx0: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Andrew Lunn Cc: Jason Cooper Signed-off-by: Stephen Boyd Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mv78xx0/common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 99cc93900a24..45a05207b418 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -168,8 +168,7 @@ static struct clk *tclk; static void __init clk_init(void) { - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - get_tclk()); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk()); orion_clkdev_init(tclk); } -- cgit v1.2.3-59-g8ed1b From cc1e18967c540c9a3ffc30ea63e500ecaa61812a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 19 Apr 2016 18:38:50 -0700 Subject: ARM: orion5x: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Andrew Lunn Signed-off-by: Stephen Boyd Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 70c3366c8d03..058994e99570 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -66,8 +66,7 @@ static struct clk *tclk; void __init clk_init(void) { - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - orion5x_tclk); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); orion_clkdev_init(tclk); } -- cgit v1.2.3-59-g8ed1b From 3a1a4559624a51e1f4ed8954d546ccc7367bb8d4 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 19 Apr 2016 18:45:48 -0700 Subject: ARM: dove: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Andrew Lunn Signed-off-by: Stephen Boyd Signed-off-by: Gregory CLEMENT --- arch/arm/mach-dove/common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0cdaa3851d2e..0d420a2bfe3e 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -88,8 +88,7 @@ static void __init dove_clk_init(void) struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; struct clk *xor0, *xor1, *ge, *gephy; - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - dove_tclk); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); -- cgit v1.2.3-59-g8ed1b From 715552aa30ffe3bd776bb7635056f6622a29133d Mon Sep 17 00:00:00 2001 From: Sylvain Lemieux Date: Mon, 4 Apr 2016 15:48:34 -0400 Subject: ARM: lpc32xx: remove reboot header file The header file "reboot.h" is no longer needed, following the migration of the restart code into the pnx4008 watchdog. Signed-off-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/mach-lpc32xx/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 2d90801ed1e1..9b5ae42d3a6f 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -21,7 +21,6 @@ #include #include -#include /* * Other arch specific structures and functions -- cgit v1.2.3-59-g8ed1b From d82b4b0a5ebeb55c3b88e49b38135a847736e6b5 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 18 Apr 2016 04:05:25 +0300 Subject: ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers After switching the platform to common clock framework there is no more need to keep dead code in arch/arm/mach-lpc32xx, which glued legacy clock source and clock provider drivers, remove the leftovers. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/mach-lpc32xx/common.c | 95 ------------------------------------------ arch/arm/mach-lpc32xx/common.h | 23 +--------- 2 files changed, 1 insertion(+), 117 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5b7a1e78c3a5..2f6067bce7c3 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -17,13 +17,6 @@ */ #include -#include -#include -#include -#include -#include -#include -#include #include #include @@ -43,19 +36,6 @@ void lpc32xx_get_uid(u32 devid[4]) devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); } -/* - * Returns SYSCLK source - * 0 = PLL397, 1 = main oscillator - */ -int clk_is_sysclk_mainosc(void) -{ - if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) & - LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0) - return 1; - - return 0; -} - /* * Detects and returns IRAM size for the device variation */ @@ -87,81 +67,6 @@ u32 lpc32xx_return_iram_size(void) } EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size); -/* - * Computes PLL rate from PLL register and input clock - */ -u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup) -{ - u32 ilfreq, p, m, n, fcco, fref, cfreq; - int mode; - - /* - * PLL requirements - * ifreq must be >= 1MHz and <= 20MHz - * FCCO must be >= 156MHz and <= 320MHz - * FREF must be >= 1MHz and <= 27MHz - * Assume the passed input data is not valid - */ - - ilfreq = ifreq; - m = pllsetup->pll_m; - n = pllsetup->pll_n; - p = pllsetup->pll_p; - - mode = (pllsetup->cco_bypass_b15 << 2) | - (pllsetup->direct_output_b14 << 1) | - pllsetup->fdbk_div_ctrl_b13; - - switch (mode) { - case 0x0: /* Non-integer mode */ - cfreq = (m * ilfreq) / (2 * p * n); - fcco = (m * ilfreq) / n; - fref = ilfreq / n; - break; - - case 0x1: /* integer mode */ - cfreq = (m * ilfreq) / n; - fcco = (m * ilfreq) / (n * 2 * p); - fref = ilfreq / n; - break; - - case 0x2: - case 0x3: /* Direct mode */ - cfreq = (m * ilfreq) / n; - fcco = cfreq; - fref = ilfreq / n; - break; - - case 0x4: - case 0x5: /* Bypass mode */ - cfreq = ilfreq / (2 * p); - fcco = 156000000; - fref = 1000000; - break; - - case 0x6: - case 0x7: /* Direct bypass mode */ - default: - cfreq = ilfreq; - fcco = 156000000; - fref = 1000000; - break; - } - - if (fcco < 156000000 || fcco > 320000000) - cfreq = 0; - - if (fref < 1000000 || fref > 27000000) - cfreq = 0; - - return (u32) cfreq; -} - -u32 clk_get_pclk_div(void) -{ - return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F); -} - static struct map_desc lpc32xx_io_desc[] __initdata = { { .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START), diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 9b5ae42d3a6f..30c9e64fc65b 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -19,36 +19,15 @@ #ifndef __LPC32XX_COMMON_H #define __LPC32XX_COMMON_H -#include -#include +#include /* * Other arch specific structures and functions */ -extern void lpc32xx_timer_init(void); extern void __init lpc32xx_init_irq(void); extern void __init lpc32xx_map_io(void); extern void __init lpc32xx_serial_init(void); - -/* - * Structure used for setting up and querying the PLLS - */ -struct clk_pll_setup { - int analog_on; - int cco_bypass_b15; - int direct_output_b14; - int fdbk_div_ctrl_b13; - int pll_p; - int pll_n; - u32 pll_m; -}; - -extern int clk_is_sysclk_mainosc(void); -extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup); -extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval); -extern u32 clk_get_pclk_div(void); - /* * Returns the LPC32xx unique 128-bit chip ID */ -- cgit v1.2.3-59-g8ed1b From 71d42e9c71d7fca2eca98eac315cb485b5d2314d Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 18 Apr 2016 04:37:38 +0300 Subject: ARM: lpc32xx: remove duplicate const on lpc32xx_auxdata_lookup Remove redundant duplicate const, which is found by smatch: arch/arm/mach-lpc32xx/phy3250.c:162:42: warning: duplicate const Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/mach-lpc32xx/phy3250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index b2f9e226febe..1ae723072521 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -159,7 +159,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { .dma_filter = pl08x_filter_id, }; -static const struct of_dev_auxdata const lpc32xx_auxdata_lookup[] __initconst = { +static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL), OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), -- cgit v1.2.3-59-g8ed1b From 8c2ed9bcfbeb7f313b567b25e87effd75e7dc3d6 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 21 Mar 2016 17:22:31 +1030 Subject: arm: Add Aspeed machine Aspeed devices are a common Baseboard Management Controller (BMC) system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and support for a large number of peripherals. This patch adds basic support for the ast2400 and ast2500 machines, capable of booting to a prompt in QEMU (-M palmetto-bmc), on an Palmetto OpenPower development machine, and on the ast2500 EVB. Signed-off-by: Joel Stanley --- MAINTAINERS | 7 +++++++ arch/arm/Kconfig | 2 ++ arch/arm/mach-aspeed/Kconfig | 30 ++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 arch/arm/mach-aspeed/Kconfig (limited to 'arch') diff --git a/MAINTAINERS b/MAINTAINERS index 61a323a6b2cf..e727935fdf04 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -975,6 +975,13 @@ F: arch/arm/mach-artpec F: arch/arm/boot/dts/artpec6* F: drivers/clk/clk-artpec6.c +ARM/ASPEED MACHINE SUPPORT +M: Joel Stanley +S: Maintained +F: arch/arm/mach-aspeed/ +F: arch/arm/boot/dts/aspeed-* +F: drivers/*/*aspeed* + ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT M: Nicolas Ferre M: Alexandre Belloni diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdfa6c2b7626..c4512f6b77f6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -775,6 +775,8 @@ source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-aspeed/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-imx/Kconfig" diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig new file mode 100644 index 000000000000..5225fbcb250d --- /dev/null +++ b/arch/arm/mach-aspeed/Kconfig @@ -0,0 +1,30 @@ +menuconfig ARCH_ASPEED + bool "Aspeed BMC architectures" + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + select SRAM + select WATCHDOG + select ASPEED_WATCHDOG + select MOXART_TIMER + help + Say Y here if you want to run your kernel on an ASpeed BMC SoC. + +if ARCH_ASPEED + +config MACH_ASPEED_G4 + bool "Aspeed SoC 4th Generation" + depends on ARCH_MULTI_V5 + select CPU_ARM926T + help + Say yes if you intend to run on an Aspeed ast2400 or similar + fourth generation BMCs, such as those used by OpenPower Power8 + systems. + +config MACH_ASPEED_G5 + bool "Aspeed SoC 5th Generation" + depends on ARCH_MULTI_V6 + select CPU_V6 + help + Say yes if you intend to run on an Aspeed ast2500 or similar + fifth generation Aspeed BMCs. + +endif -- cgit v1.2.3-59-g8ed1b