From 323d23aeac4918c7a540b597a26fa7a67645593a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 23 Apr 2009 08:51:22 -0500 Subject: Revert "powerpc: Add support for early tlbilx opcode" This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6. Our HW guys were able to fix this so it never sees the light of day. Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/mmu.h | 6 ------ arch/powerpc/include/asm/ppc-opcode.h | 11 +---------- arch/powerpc/kernel/cputable.c | 2 +- arch/powerpc/mm/tlb_nohash_low.S | 14 +------------- 4 files changed, 3 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 86d2366ab6a1..cbf154387091 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -52,12 +52,6 @@ */ #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) -/* This indicates that the processor uses the wrong opcode for tlbilx - * instructions. During the ISA 2.06 development the opcode for tlbilx - * changed and some early implementations used to old opcode - */ -#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000) - #ifndef __ASSEMBLY__ #include diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ef4da37f3c10..640ccbbc0977 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -44,7 +44,6 @@ #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a #define PPC_INST_TLBILX 0x7c000024 -#define PPC_INST_TLBILX_EARLY 0x7c000626 #define PPC_INST_WAIT 0x7c00007c /* macros to insert fields into opcodes */ @@ -64,18 +63,10 @@ #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ - __PPC_T_TLB(t) | \ - __PPC_RA(a) | __PPC_RB(b)) + __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) - -#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \ - __PPC_T_TLB(t) | \ - __PPC_RA(a) | __PPC_RB(b)) -#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b) -#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b) -#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b) #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ __PPC_WC(w)) diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 57db50f40289..cd1b687544f3 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_features = CPU_FTRS_E500MC, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | - MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, + MMU_FTR_USE_TLBILX, .icache_bsize = 64, .dcache_bsize = 64, .num_pmcs = 4, diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 45fed3698349..788b87c36f77 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION andi. r3,r3,MMUCSR0_TLBFI@l bne 1b MMU_FTR_SECTION_ELSE - BEGIN_MMU_FTR_SECTION_NESTED(96) - PPC_TLBILX_ALL(0,r3) - MMU_FTR_SECTION_ELSE_NESTED(96) - PPC_TLBILX_ALL_EARLY(0,r3) - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) + PPC_TLBILX_ALL(0,0) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION wrteei 0 mfspr r4,SPRN_MAS6 /* save MAS6 */ mtspr SPRN_MAS6,r3 - BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_PID(0,0) - MMU_FTR_SECTION_ELSE_NESTED(96) - PPC_TLBILX_PID_EARLY(0,0) - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) mtspr SPRN_MAS6,r4 /* restore MAS6 */ wrtee r10 MMU_FTR_SECTION_ELSE @@ -193,11 +185,7 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE - BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_VA(0,r3) - MMU_FTR_SECTION_ELSE_NESTED(96) - PPC_TLBILX_VA_EARLY(0,r3) - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync -- cgit v1.2.3-59-g8ed1b From b62c31ae401c6df25c61b206681a6e904ef97169 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Thu, 23 Apr 2009 22:56:11 +1000 Subject: powerpc: fix for long standing bug noticed by gcc 4.4.0 Previous gcc versions didn't notice this because one of the preceding #ifs always evaluated to true. gcc 4.4.0 produced this error: arch/powerpc/mm/tlb_nohash_low.S:206:6: error: #elif with no expression Signed-off-by: Stephen Rothwell Acked-by: Josh Boyer Signed-off-by: Kumar Gala --- arch/powerpc/mm/tlb_nohash_low.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 788b87c36f77..3037911279b1 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -191,6 +191,6 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) isync 1: wrtee r10 blr -#elif +#else #error Unsupported processor type ! #endif -- cgit v1.2.3-59-g8ed1b From 644e28f3426810710b176080cc906995ebc24b63 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Thu, 23 Apr 2009 10:55:06 +0000 Subject: powerpc/44x: Correct memory size calculation for denali-based boards Some U-Boot versions incorrectly set the number of chipselects to two for Sequoia/Rainier boards while they only have one chipselect hardwired. This patch adds a workaround for this, hardcoding the number of chipselects to one for sequioa/rainer board models and reading the actual value from the memory controller register DDR0_10 otherwise. It also fixes another error in the way ibm4xx_denali_fixup_memsize calculates memory size. When testing the DDR_REDUC bit, the polarity is backwards. A "1" implies 32-bit wide memory while a "0" implies 64-bit wide memory. Signed-off-by: Mikhail Zolotaryov Signed-off-by: Valentine Barshak Signed-off-by: Steven A. Falco Acked-by: Stefan Roese Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 56 +++++++++++++++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 5c878436f348..325b310573b9 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -158,21 +158,33 @@ void ibm440spe_fixup_memsize(void) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) -void ibm4xx_denali_fixup_memsize(void) +/* + * Some U-Boot versions set the number of chipselects to two + * for Sequoia/Rainier boards while they only have one chipselect + * hardwired. Hardcode the number of chipselects to one + * for sequioa/rainer board models or read the actual value + * from the memory controller register DDR0_10 otherwise. + */ +static inline u32 ibm4xx_denali_get_cs(void) { - u32 val, max_cs, max_col, max_row; - u32 cs, col, row, bank, dpath; - unsigned long memsize; + void *devp; + char model[64]; + u32 val, cs; - val = SDRAM0_READ(DDR0_02); - if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) - fatal("DDR controller is not initialized\n"); + devp = finddevice("/"); + if (!devp) + goto read_cs; - /* get maximum cs col and row values */ - max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); - max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); - max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); + if (getprop(devp, "model", model, sizeof(model)) <= 0) + goto read_cs; + model[sizeof(model)-1] = 0; + + if (!strcmp(model, "amcc,sequoia") || + !strcmp(model, "amcc,rainier")) + return 1; + +read_cs: /* get CS value */ val = SDRAM0_READ(DDR0_10); @@ -183,7 +195,25 @@ void ibm4xx_denali_fixup_memsize(void) cs++; val = val >> 1; } + return cs; +} + +void ibm4xx_denali_fixup_memsize(void) +{ + u32 val, max_cs, max_col, max_row; + u32 cs, col, row, bank, dpath; + unsigned long memsize; + + val = SDRAM0_READ(DDR0_02); + if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) + fatal("DDR controller is not initialized\n"); + /* get maximum cs col and row values */ + max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); + max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); + max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); + + cs = ibm4xx_denali_get_cs(); if (!cs) fatal("No memory installed\n"); if (cs > max_cs) @@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void) val = SDRAM0_READ(DDR0_14); if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) - dpath = 8; /* 64 bits */ - else dpath = 4; /* 32 bits */ + else + dpath = 8; /* 64 bits */ /* get address pins (rows) */ val = SDRAM0_READ(DDR0_42); -- cgit v1.2.3-59-g8ed1b From 28853da20c840f0d147674ac850c539d3306109f Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 27 Apr 2009 17:24:28 +0100 Subject: powerpc/86xx: Add device_type entry to soc for ppc9a The 'device_type = "soc";' line *is* needed in the DTS for get_immrbase() to return the correct address. Signed-off-by: Martyn Welch Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/gef_ppc9a.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index d47ad0718759..53a7a6255909 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -161,6 +161,7 @@ #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; + device_type = "soc"; compatible = "fsl,mpc8641-soc", "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M -- cgit v1.2.3-59-g8ed1b From 2e8aead1b57ede7979bd4e24797c77e181775d9c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Apr 2009 08:03:01 +0000 Subject: powerpc: ppc32 needs elf_read_implies_exec() On ppc64 we implemented elf_read_implies_exec() for 32-bit binaries because old toolchains had bugs where they didn't mark program segments executable that needed to be. For some reason we didn't do this on ppc32 builds. This hadn't been an issue until commit 8d30c14c ("powerpc/mm: Rework I$/D$ coherency (v3)"), which had as a side effect that we are now enforcing execute permissions to some extent on 32-bit 4xx and Book E processors. This fixes it by defining elf_read_implies_exec on 32-bit to turn on the read-implies-exec behaviour on programs that are sufficiently old that they don't have a PT_GNU_STACK program header. Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/elf.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h index 087c22f1d368..d6b4a12cdeff 100644 --- a/arch/powerpc/include/asm/elf.h +++ b/arch/powerpc/include/asm/elf.h @@ -260,6 +260,7 @@ do { \ #else # define SET_PERSONALITY(ex) \ set_personality(PER_LINUX | (current->personality & (~PER_MASK))) +# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) #endif /* __powerpc64__ */ extern int dcache_bsize; -- cgit v1.2.3-59-g8ed1b From ff61e5ccc35b7159a50741fc4b992817785acd5c Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Wed, 22 Apr 2009 22:43:03 +0000 Subject: powerpc/cell: Select PCI for IBM_CELL_BLADE AND CELLEB Currently PPC_CELL_NATIVE selects PPC_OF_PLATFORM_PCI, but does not select PCI. This can lead to a config with the former and the latter disabled, which does not build. To fix this PPC_CELL_NATIVE should select PCI. However, that would force PCI on for QPACE, which also selects PPC_CELL_NATIVE. So instead move the select of PPC_OF_PLATFORM_PCI and PCI under both IBM_CELL_BLADE and CELLEB. Signed-off-by: Michael Ellerman Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras --- arch/powerpc/platforms/cell/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig index 40e24c39ad06..50f17bdd3c16 100644 --- a/arch/powerpc/platforms/cell/Kconfig +++ b/arch/powerpc/platforms/cell/Kconfig @@ -13,7 +13,6 @@ config PPC_CELL_COMMON config PPC_CELL_NATIVE bool select PPC_CELL_COMMON - select PPC_OF_PLATFORM_PCI select MPIC select IBM_NEW_EMAC_EMAC4 select IBM_NEW_EMAC_RGMII @@ -25,6 +24,8 @@ config PPC_IBM_CELL_BLADE bool "IBM Cell Blade" depends on PPC64 && PPC_BOOK3S select PPC_CELL_NATIVE + select PPC_OF_PLATFORM_PCI + select PCI select MMIO_NVRAM select PPC_UDBG_16550 select UDBG_RTAS_CONSOLE @@ -33,6 +34,8 @@ config PPC_CELLEB bool "Toshiba's Cell Reference Set 'Celleb' Architecture" depends on PPC64 && PPC_BOOK3S select PPC_CELL_NATIVE + select PPC_OF_PLATFORM_PCI + select PCI select HAS_TXX9_SERIAL select PPC_UDBG_BEAT select USB_OHCI_BIG_ENDIAN_MMIO -- cgit v1.2.3-59-g8ed1b From d8f48457d5af6601abdecaad7a95c45bfeef90d5 Mon Sep 17 00:00:00 2001 From: Geoff Levand Date: Thu, 16 Apr 2009 09:05:37 +0000 Subject: powerpc/ps3: Fix build error on UP A non-SMP version of smp_send_stop() is now included in smp.h. Remove the unneeded definition in the PS3 smp.c. Fixes build errors like these when CONFIG_SMP=n: arch/powerpc/platforms/ps3/setup.c:49: error: redefinition of 'smp_send_stop' include/linux/smp.h:125: error: previous definition of 'smp_send_stop' was here Reported-by: Subrata Modak Signed-off-by: Geoff Levand Signed-off-by: Paul Mackerras --- arch/powerpc/platforms/ps3/setup.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c index 66181821322a..1a7b5ae0c83e 100644 --- a/arch/powerpc/platforms/ps3/setup.c +++ b/arch/powerpc/platforms/ps3/setup.c @@ -45,10 +45,6 @@ DEFINE_MUTEX(ps3_gpu_mutex); EXPORT_SYMBOL_GPL(ps3_gpu_mutex); -#if !defined(CONFIG_SMP) -static void smp_send_stop(void) {} -#endif - static union ps3_firmware_version ps3_firmware_version; void ps3_get_firmware_version(union ps3_firmware_version *v) -- cgit v1.2.3-59-g8ed1b