From 2fc6f3773733f2a6322ede65abbbe76c9f1908fa Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:23 +0100 Subject: ARM: dts: meson6: add the APB2 bus The Mali GPU and the DVB demulator are located in the APB2 bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index ca978ab952cd..65585255910a 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -70,6 +70,14 @@ }; }; + apb2: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x40000>; + }; + xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; -- cgit v1.2.3-59-g8ed1b From 7e22d72834870af1396f90d31cbff38f36bbfa3d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:24 +0100 Subject: ARM: dts: meson8: add the APB bus Various peripherals (Mali GPU, NAND controller, VPU, etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index e5cd325d7ea8..3fd8260eba92 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -201,6 +201,14 @@ no-map; }; }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; }; /* end of / */ &aobus { -- cgit v1.2.3-59-g8ed1b From e402d24d884130ed308ff1d04fdababffcf0fa86 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:25 +0100 Subject: ARM: dts: meson8b: add the APB bus Various peripherals (Mali GPU, NAND controller, VPU; etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 22d775460767..5d036842c355 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -178,6 +178,14 @@ no-map; }; }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; }; /* end of / */ &aobus { -- cgit v1.2.3-59-g8ed1b From 7d3f6b536e72c94bd19585a3283e8d141614fee0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:46 +0100 Subject: ARM: dts: meson8: add the Mali-450 MP6 GPU Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the latter inherits meson8.dtsi). These SoCs have a Mali-450 GPU with six pixel processors. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV7 | 1, /* 182.1 Mhz */ FCLK_DEV4 | 1, /* 318.7 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 3fd8260eba92..1ea5a36c5040 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -166,6 +166,32 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-182150000 { + opp-hz = /bits/ 64 <182150000>; + opp-microvolt = <1150000>; + }; + opp-318750000 { + opp-hz = /bits/ 64 <318750000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = , @@ -208,6 +234,38 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2", "pp4", "ppmmu4", + "pp5", "ppmmu5", "pp6", "ppmmu6"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + switch-delay = <0xffff>; + }; }; }; /* end of / */ -- cgit v1.2.3-59-g8ed1b From c3ea80b6138caea8a6010fe37c6c3e57cb805b7d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:47 +0100 Subject: ARM: dts: meson8b: add the Mali-450 MP2 GPU Add the Mali-450 GPU and it's OPP table for Meson8. The GPU uses two pixel processors in this configuration. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV5 | 1, /* 255 Mhz */ FCLK_DEV7 | 0, /* 364 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 5d036842c355..dd498e681939 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -158,6 +158,32 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-255000000 { + opp-hz = /bits/ 64 <255000000>; + opp-microvolt = <1150000>; + }; + opp-364300000 { + opp-hz = /bits/ 64 <364300000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + pmu { compatible = "arm,cortex-a5-pmu"; interrupts = , @@ -185,6 +211,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8b-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + switch-delay = <0xffff>; + }; }; }; /* end of / */ -- cgit v1.2.3-59-g8ed1b From 29f0023d01f063feacfc404f0446905aee4f82ee Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 29 Dec 2018 15:35:56 +0100 Subject: ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the Odroid-C1+ schematics the Ethernet TXD1 signal is routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and TXD1 can be routed to DIF_2_N instead. The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured as TXD0 and TXD1 data lines as well. This results in a bad Ethernet receive performance. Presumably this is due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. As a result of that data can only be transmitted on eth_txd2 and eth_txd3. However, I have no scope to fully confirm this assumption. The vendor u-boot sources for Odroid-C1 use the following Ethernet pinmux configuration: SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); This translates to the following pin groups in the mainline kernel: - register 6 bit 0: eth_rxd1 (DIF_0_P) - register 6 bit 1: eth_rxd0 (DIF_0_N) - register 6 bit 2: eth_rx_dv (DIF_1_P) - register 6 bit 3: eth_rx_clk (DIF_1_N) - register 6 bit 6: eth_tx_en (DIF_3_P) - register 6 bit 8: eth_ref_clk (DIF_3_N) - register 6 bit 9: eth_mdc (DIF_4_P) - register 6 bit 10: eth_mdio_en (DIF_4_N) - register 6 bit 11: eth_tx_clk (GPIOH_9) - register 6 bit 12: eth_txd2 (GPIOH_8) - register 6 bit 13: eth_txd3 (GPIOH_7) - register 7 bit 20: eth_txd0_0 (GPIOH_6) - register 7 bit 21: eth_txd1_0 (GPIOH_5) - register 7 bit 22: eth_rxd3 (DIF_2_P) - register 7 bit 23: eth_rxd2 (DIF_2_N) Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and eth_rxd3 groups so we don't rely on the bootloader to set them up. iperf3 statistics before this change: - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) iperf3 statistics after this change: - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) - receiving on Odroid-C1: 750 Mbits/sec (0 retries) Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") Signed-off-by: Martin Blumenstingl Cc: Emiliano Ingrassia Cc: Linus Lüssing Tested-by: Emiliano Ingrassia Reviewed-by: Emiliano Ingrassia Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index dd498e681939..9fca77478fec 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -324,9 +324,7 @@ groups = "eth_tx_clk", "eth_tx_en", "eth_txd1_0", - "eth_txd1_1", "eth_txd0_0", - "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", "eth_rxd1", @@ -335,7 +333,9 @@ "eth_mdc", "eth_ref_clk", "eth_txd2", - "eth_txd3"; + "eth_txd3", + "eth_rxd3", + "eth_rxd2"; function = "ethernet"; bias-disable; }; -- cgit v1.2.3-59-g8ed1b From b6db3936f2833c9f27aa9d868bb7bb6e87401b40 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:21 +0100 Subject: ARM: dts: meson: switch the clock controller to the HHI register area The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 15 ++++++++------- arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++------- 3 files changed, 23 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e4645f612712..536d6314d97e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -72,6 +72,13 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hhi: system-controller@4000 { + compatible = "amlogic,meson-hhi-sysctrl", + "simple-mfd", + "syscon"; + reg = <0x4000 0x400>; + }; + assist: assist@7c00 { compatible = "amlogic,meson-mx-assist", "syscon"; reg = <0x7c00 0x200>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1ea5a36c5040..66b167537aaa 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -327,13 +327,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -468,6 +461,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9fca77478fec..9faf70a6ed9a 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -276,13 +276,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8b-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -437,6 +430,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; -- cgit v1.2.3-59-g8ed1b From c0ad99a2deacc7eab5f9bd9dd176bd4cbeea91e2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:22 +0100 Subject: ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible The SAR ADC on Meson8m2 is slightly different compared to Meson8. The ADC functionality is identical but the calibration of the internal thermal sensor is different. Use the Meson8m2 specific compatible so the temperature sensor is calibrated correctly on boards using the Meson8m2 SoC. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8m2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index d1a28c2adac5..bb87b251e16d 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -50,6 +50,10 @@ }; }; +&saradc { + compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; -- cgit v1.2.3-59-g8ed1b From f4c6e8e223c2c77cd3bdde4c9da280fb2338aa5b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:23 +0100 Subject: ARM: dts: meson8: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 66b167537aaa..a9781243453e 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -449,6 +449,11 @@ compatible = "amlogic,meson8-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -536,6 +541,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { -- cgit v1.2.3-59-g8ed1b From bbbcf64360bb32c8eab46020b78a0c0e0de4c40c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:24 +0100 Subject: ARM: dts: meson8b: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9faf70a6ed9a..fe84a8c3ce81 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -407,6 +407,11 @@ compatible = "amlogic,meson8b-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -505,6 +510,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { -- cgit v1.2.3-59-g8ed1b From 1a4f28ab2556deacd34b925bf419432a59670af6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:25 +0100 Subject: ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0872f6e3abf5..0cebe849a920 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -64,6 +64,11 @@ timeout-ms = <20000>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + leds { compatible = "gpio-leds"; -- cgit v1.2.3-59-g8ed1b From a6c94928261a307002c4f8f3c0875c4a655a3a50 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:26 +0100 Subject: ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 58669abda259..9251dc102fcc 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -118,6 +118,11 @@ 1800000 1>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_1v8: regulator-vcc-1v8 { /* * RICHTEK RT9179 configured for a fixed output voltage of -- cgit v1.2.3-59-g8ed1b From e7e871b50f80145d37d13e8fbdc73a7dd52c4d88 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:27 +0100 Subject: ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index f5853610b20b..d1d3c828c039 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -44,6 +44,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_3v3: regulator-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "VCC3V3"; -- cgit v1.2.3-59-g8ed1b From b7d10841e5d7003bb8bc57c122494b4fb47836c0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:37 +0100 Subject: ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad on the SoC. Enable the interrupt function of the PHY's INTR32 pin to switch it from it's default "receive error" mode to "interrupt pin" mode. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0cebe849a920..74b726fc0d30 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -169,6 +169,10 @@ eth_phy0: ethernet-phy@0 { /* IC Plus IP101A/G (0x02430c54) */ reg = <0>; + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; }; -- cgit v1.2.3-59-g8ed1b From 3e7db1c1b7a32dfbf1f9fc33d444c83e64dd3513 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:38 +0100 Subject: ARM: dts: meson8b: ec100: improve the description of the regulators USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN. VCC5V is supplied by the main power input called PWR_5V_STB. The name of it's enable GPIO signal is 3V3_5V_EN. VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the voltage of VCCK can be changed by changing it's feedback voltage via PWM_C. VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is supplied by VCC3V3. VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It is supplied by either VCC3V3 (when the board is powered) or the RTC coin cell battery. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 68 +++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 74b726fc0d30..34cd72911d63 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -88,6 +88,9 @@ }; usb_vbus: regulator-usb-vbus { + /* + * Silergy SY6288CCAC-GP 2A Power Distribution Switch. + */ compatible = "regulator-fixed"; regulator-name = "USB_VBUS"; @@ -95,11 +98,20 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* + * signal name from the schematics: USB_PWR_EN + */ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; enable-active-high; }; vcc_5v: regulator-vcc5v { + /* + * supplied by the main power input which called PWR_5V_STB + * in the schematics + */ compatible = "regulator-fixed"; regulator-name = "VCC5V"; @@ -107,6 +119,9 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + /* + * signal name from the schematics: 3V3_5V_EN + */ gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; regulator-boot-on; @@ -114,12 +129,18 @@ }; vcck: regulator-vcck { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. + */ compatible = "pwm-regulator"; regulator-name = "VCCK"; regulator-min-microvolt = <860000>; regulator-max-microvolt = <1140000>; + vin-supply = <&vcc_5v>; + pwms = <&pwm_cd 0 1148 0>; pwm-dutycycle-range = <100 0>; @@ -128,19 +149,66 @@ }; vcc_1v8: regulator-vcc1v8 { + /* + * ABLIC S-1339D18-M5001-GP + */ compatible = "regulator-fixed"; regulator-name = "VCC1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + vin-supply = <&vcc_3v3>; }; vcc_3v3: regulator-vcc3v3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * VDDIO_AO3.3V in the schematics. + */ compatible = "regulator-fixed"; regulator-name = "VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v>; + }; + + vcc_ddr3: regulator-vcc-ddr3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * DDR3_1.5V in the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_DDR3_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&vcc_5v>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_rtc: regulator-vcc-rtc { + /* + * Global Mixed-mode Technology Inc. G918T12U-GP + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_RTC"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + /* + * When the board is powered then the input is VCC3V3, + * otherwise power is taken from the coin cell battery. + */ + vin-supply = <&vcc_3v3>; }; }; -- cgit v1.2.3-59-g8ed1b From 99f0619b0d0d87f921b05f0b7e43ff2e080a4fcc Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:39 +0100 Subject: ARM: dts: meson8b: ec100: add the GPIO line names This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 50 +++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 34cd72911d63..889fdc31fb78 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -289,6 +289,56 @@ }; }; +&gpio_ao { + gpio-line-names = "Linux_TX", "Linux_RX", + "SLP_S5_N", "USB2_OC_FLAG#", + "HUB_RST", "USB_PWR_EN", + "I2S_IN", "SLP_S1_N", + "TCK", "TMS", "TDI", "TDO", + "HDMI_CEC", "5640_IRQ", + "MUTE", "S805_TEST#"; +}; + +&gpio { + gpio-line-names = /* Bank GPIOX */ + "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", + "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", + "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", + "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", + "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", + "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", + /* Bank GPIOY */ + "", "", "", "", "", "", "", "", "", "", + "", "", + /* Bank GPIODV */ + "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", + "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", + "VDDEE_PWM 3V3_5V_EN", + /* Bank GPIOH */ + "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", + "RMII_IRQ", "RMII_RST#", "RMII_TXD1", + "RMII_TXD0", "AV_select_1", "AV_select_2", + "MCU_Control_S", + /* Bank CARD */ + "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", + "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", + "CARD_EN_DET (CARD_DET)", + /* Bank BOOT */ + "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", + "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", + "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", + "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", + "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", + "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", + "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", + "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", + /* Bank DIF */ + "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", + "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", + "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", + "RMII_MDIO"; +}; + &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_c1_pins>; -- cgit v1.2.3-59-g8ed1b