From 0865805d82d4c822647ee35ab2629c48cc40706b Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 10 Aug 2017 08:34:03 +0200 Subject: clk: at91: add audio pll clock drivers This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz. Signed-off-by: Nicolas Ferre Signed-off-by: Quentin Schulz Acked-by: Boris Brezillon Signed-off-by: Stephen Boyd --- drivers/clk/at91/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/at91/Makefile') diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 13e67bd35cff..c68947b65a4c 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -6,6 +6,7 @@ obj-y += pmc.o sckc.o obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o obj-y += clk-system.o clk-peripheral.o clk-programmable.o +obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o -- cgit v1.2.3-59-g8ed1b