From c1e846b8ee5eee78765242fe204f566596c52ad1 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 4 Dec 2019 22:35:55 -0800 Subject: clk: zynqmp: Extend driver for versal Add Versal compatible string to support Versal binding. Signed-off-by: Jolly Shah Signed-off-by: Michal Simek Signed-off-by: Rajan Vaja Link: https://lkml.kernel.org/r/1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd --- drivers/clk/zynqmp/clkc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk/zynqmp/clkc.c') diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index a11f93ecbf34..10e89f23880b 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -2,7 +2,7 @@ /* * Zynq UltraScale+ MPSoC clock controller * - * Copyright (C) 2016-2018 Xilinx + * Copyright (C) 2016-2019 Xilinx * * Based on drivers/clk/zynq/clkc.c */ @@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev) static const struct of_device_id zynqmp_clock_of_match[] = { {.compatible = "xlnx,zynqmp-clk"}, + {.compatible = "xlnx,versal-clk"}, {}, }; MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match); -- cgit v1.2.3-59-g8ed1b