From b4f91664307d5bf4f0d93da12a6146f9cf3559fb Mon Sep 17 00:00:00 2001 From: Atul Gupta Date: Thu, 2 May 2019 03:46:55 -0700 Subject: crypto: chelsio - Fix NULL pointer dereference Do not request FW to generate cidx update if there is less space in tx queue to post new request. SGE DBP 1 pidx increment too large BUG: unable to handle kernel NULL pointer dereference at 0000000000000124 SGE error for queue 101 Signed-off-by: Atul Gupta Signed-off-by: Herbert Xu --- drivers/crypto/chelsio/chcr_ipsec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/crypto') diff --git a/drivers/crypto/chelsio/chcr_ipsec.c b/drivers/crypto/chelsio/chcr_ipsec.c index 2f60049361ef..f429aae72542 100644 --- a/drivers/crypto/chelsio/chcr_ipsec.c +++ b/drivers/crypto/chelsio/chcr_ipsec.c @@ -575,7 +575,8 @@ inline void *chcr_crypto_wreq(struct sk_buff *skb, if (unlikely(credits < ETHTXQ_STOP_THRES)) { netif_tx_stop_queue(q->txq); q->q.stops++; - wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; + if (!q->dbqt) + wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; } wr_mid |= FW_ULPTX_WR_DATA_F; wr->wreq.flowid_len16 = htonl(wr_mid); -- cgit v1.2.3-59-g8ed1b From 33ddc108c5a1cfba72a08a92f35a0ba5bbd1cfd8 Mon Sep 17 00:00:00 2001 From: Atul Gupta Date: Thu, 2 May 2019 03:47:27 -0700 Subject: crypto: chelsio - Fix softlockup with heavy I/O removed un-necessary lock_chcr_dev to protect device state DETACH. lock is not required to protect I/O count Signed-off-by: Atul Gupta Signed-off-by: Herbert Xu --- drivers/crypto/chelsio/chcr_algo.c | 13 +++---------- drivers/crypto/chelsio/chcr_core.c | 4 ---- 2 files changed, 3 insertions(+), 14 deletions(-) (limited to 'drivers/crypto') diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c index 8a76fce22943..73bbd499b6ff 100644 --- a/drivers/crypto/chelsio/chcr_algo.c +++ b/drivers/crypto/chelsio/chcr_algo.c @@ -200,17 +200,10 @@ void chcr_verify_tag(struct aead_request *req, u8 *input, int *err) static int chcr_inc_wrcount(struct chcr_dev *dev) { - int err = 0; - - spin_lock_bh(&dev->lock_chcr_dev); if (dev->state == CHCR_DETACH) - err = 1; - else - atomic_inc(&dev->inflight); - - spin_unlock_bh(&dev->lock_chcr_dev); - - return err; + return 1; + atomic_inc(&dev->inflight); + return 0; } static inline void chcr_dec_wrcount(struct chcr_dev *dev) diff --git a/drivers/crypto/chelsio/chcr_core.c b/drivers/crypto/chelsio/chcr_core.c index 239b933d6df6..029a7354f541 100644 --- a/drivers/crypto/chelsio/chcr_core.c +++ b/drivers/crypto/chelsio/chcr_core.c @@ -243,15 +243,11 @@ static void chcr_detach_device(struct uld_ctx *u_ctx) { struct chcr_dev *dev = &u_ctx->dev; - spin_lock_bh(&dev->lock_chcr_dev); if (dev->state == CHCR_DETACH) { - spin_unlock_bh(&dev->lock_chcr_dev); pr_debug("Detached Event received for already detach device\n"); return; } dev->state = CHCR_DETACH; - spin_unlock_bh(&dev->lock_chcr_dev); - if (atomic_read(&dev->inflight) != 0) { schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM); wait_for_completion(&dev->detach_comp); -- cgit v1.2.3-59-g8ed1b From 0a4491d3febe0b8c328870d1909fc91756970237 Mon Sep 17 00:00:00 2001 From: Atul Gupta Date: Thu, 2 May 2019 03:47:57 -0700 Subject: crypto: chelsio - count incomplete block in IV The partial block should count as one and appropriately appended to IV. eg 499B for AES CTR should count 32 block than 31 and correct count value is updated in iv out. Signed-off-by: Atul Gupta Signed-off-by: Herbert Xu --- drivers/crypto/chelsio/chcr_algo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/crypto') diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c index 73bbd499b6ff..177f572b9589 100644 --- a/drivers/crypto/chelsio/chcr_algo.c +++ b/drivers/crypto/chelsio/chcr_algo.c @@ -1094,8 +1094,8 @@ static int chcr_final_cipher_iv(struct ablkcipher_request *req, int ret = 0; if (subtype == CRYPTO_ALG_SUB_TYPE_CTR) - ctr_add_iv(iv, req->info, (reqctx->processed / - AES_BLOCK_SIZE)); + ctr_add_iv(iv, req->info, DIV_ROUND_UP(reqctx->processed, + AES_BLOCK_SIZE)); else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS) ret = chcr_update_tweak(req, iv, 1); else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) { -- cgit v1.2.3-59-g8ed1b From 24586b5feaf17ecf85ae6259fe3ea7815dee432d Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Mon, 6 May 2019 14:39:44 +0800 Subject: crypto: caam - fix DKP detection logic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The detection for DKP (Derived Key Protocol) relied on the value of the setkey function. This was broken by the recent change which added des3_aead_setkey. This patch fixes this by introducing a new flag for DKP and setting that where needed. Fixes: 1b52c40919e6 ("crypto: caam - Forbid 2-key 3DES in FIPS mode") Reported-by: Horia Geantă Signed-off-by: Herbert Xu Tested-by: Horia Geantă Signed-off-by: Herbert Xu --- drivers/crypto/caam/caamalg.c | 9 +++++++-- drivers/crypto/caam/caamalg_qi.c | 7 +++++-- drivers/crypto/caam/caamalg_qi2.c | 8 +++++++- 3 files changed, 19 insertions(+), 5 deletions(-) (limited to 'drivers/crypto') diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index 3e23d4b2cce2..c0ece44f303b 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -89,6 +89,7 @@ struct caam_alg_entry { int class2_alg_type; bool rfc3686; bool geniv; + bool nodkp; }; struct caam_aead_alg { @@ -2052,6 +2053,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, { @@ -2070,6 +2072,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, /* Galois Counter Mode */ @@ -2089,6 +2092,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, /* single-pass ipsec_esp descriptor */ @@ -3334,6 +3338,7 @@ static struct caam_aead_alg driver_aeads[] = { OP_ALG_AAI_AEAD, .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | OP_ALG_AAI_AEAD, + .nodkp = true, }, }, { @@ -3356,6 +3361,7 @@ static struct caam_aead_alg driver_aeads[] = { OP_ALG_AAI_AEAD, .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | OP_ALG_AAI_AEAD, + .nodkp = true, }, }, }; @@ -3417,8 +3423,7 @@ static int caam_aead_init(struct crypto_aead *tfm) container_of(alg, struct caam_aead_alg, aead); struct caam_ctx *ctx = crypto_aead_ctx(tfm); - return caam_init_common(ctx, &caam_alg->caam, - alg->setkey == aead_setkey); + return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp); } static void caam_exit_common(struct caam_ctx *ctx) diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c index 70af211d2d01..d290d6b41825 100644 --- a/drivers/crypto/caam/caamalg_qi.c +++ b/drivers/crypto/caam/caamalg_qi.c @@ -36,6 +36,7 @@ struct caam_alg_entry { int class2_alg_type; bool rfc3686; bool geniv; + bool nodkp; }; struct caam_aead_alg { @@ -1523,6 +1524,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, { @@ -1541,6 +1543,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, /* Galois Counter Mode */ @@ -1560,6 +1563,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, } }, /* single-pass ipsec_esp descriptor */ @@ -2433,8 +2437,7 @@ static int caam_aead_init(struct crypto_aead *tfm) aead); struct caam_ctx *ctx = crypto_aead_ctx(tfm); - return caam_init_common(ctx, &caam_alg->caam, - alg->setkey == aead_setkey); + return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp); } static void caam_exit_common(struct caam_ctx *ctx) diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c index 33a4df6b81de..2b2980a8a9b9 100644 --- a/drivers/crypto/caam/caamalg_qi2.c +++ b/drivers/crypto/caam/caamalg_qi2.c @@ -42,6 +42,7 @@ struct caam_alg_entry { int class2_alg_type; bool rfc3686; bool geniv; + bool nodkp; }; struct caam_aead_alg { @@ -1480,7 +1481,7 @@ static int caam_cra_init_aead(struct crypto_aead *tfm) crypto_aead_set_reqsize(tfm, sizeof(struct caam_request)); return caam_cra_init(crypto_aead_ctx(tfm), &caam_alg->caam, - alg->setkey == aead_setkey); + !caam_alg->caam.nodkp); } static void caam_exit_common(struct caam_ctx *ctx) @@ -1641,6 +1642,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, { @@ -1659,6 +1661,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, }, }, /* Galois Counter Mode */ @@ -1678,6 +1681,7 @@ static struct caam_aead_alg driver_aeads[] = { }, .caam = { .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, + .nodkp = true, } }, /* single-pass ipsec_esp descriptor */ @@ -2755,6 +2759,7 @@ static struct caam_aead_alg driver_aeads[] = { OP_ALG_AAI_AEAD, .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | OP_ALG_AAI_AEAD, + .nodkp = true, }, }, { @@ -2777,6 +2782,7 @@ static struct caam_aead_alg driver_aeads[] = { OP_ALG_AAI_AEAD, .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | OP_ALG_AAI_AEAD, + .nodkp = true, }, }, { -- cgit v1.2.3-59-g8ed1b From 8c65d35435e8cbfdf953cafe5ebe3648ee9276a2 Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Tue, 7 May 2019 16:37:03 +0300 Subject: crypto: caam - fix caam_dump_sg that iterates through scatterlist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix caam_dump_sg by correctly determining the next scatterlist entry in the list. Fixes: 5ecf8ef9103c ("crypto: caam - fix sg dump") Signed-off-by: Iuliana Prodan Reviewed-by: Horia Geantă Signed-off-by: Herbert Xu --- drivers/crypto/caam/error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/crypto') diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c index a4129a35a330..4da844e4b61d 100644 --- a/drivers/crypto/caam/error.c +++ b/drivers/crypto/caam/error.c @@ -22,7 +22,7 @@ void caam_dump_sg(const char *level, const char *prefix_str, int prefix_type, size_t len; void *buf; - for (it = sg; it && tlen > 0 ; it = sg_next(sg)) { + for (it = sg; it && tlen > 0 ; it = sg_next(it)) { /* * make sure the scatterlist's page * has a valid virtual memory mapping -- cgit v1.2.3-59-g8ed1b From cbc22b062106993980df43a7ffa93351d3218844 Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Thu, 9 May 2019 13:20:48 +0800 Subject: Revert "crypto: caam/jr - Remove extra memory barrier during job ring dequeue" This reverts commit bbfcac5ff5f26aafa51935a62eb86b6eacfe8a49. It caused a crash regression on powerpc: https://lore.kernel.org/linux-crypto/87pnp2aflz.fsf@concordia.ellerman.id.au/ Signed-off-by: Herbert Xu --- drivers/crypto/caam/jr.c | 2 +- drivers/crypto/caam/regs.h | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) (limited to 'drivers/crypto') diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index 044a69b526f7..1de2562d0982 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -213,7 +213,7 @@ static void caam_jr_dequeue(unsigned long devarg) mb(); /* set done */ - wr_reg32_relaxed(&jrp->rregs->outring_rmvd, 1); + wr_reg32(&jrp->rregs->outring_rmvd, 1); jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) & (JOBR_DEPTH - 1); diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index c1fa1ec701d9..8591914d5c51 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -96,14 +96,6 @@ cpu_to_caam(16) cpu_to_caam(32) cpu_to_caam(64) -static inline void wr_reg32_relaxed(void __iomem *reg, u32 data) -{ - if (caam_little_end) - writel_relaxed(data, reg); - else - writel_relaxed(cpu_to_be32(data), reg); -} - static inline void wr_reg32(void __iomem *reg, u32 data) { if (caam_little_end) -- cgit v1.2.3-59-g8ed1b