From 97a4e5c95bf762ac254209dc4808ee5138ee574e Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 8 May 2018 11:06:39 +1000 Subject: fsi/fsi-master-gpio: Reduce turnaround clocks FSI_GPIO_PRIME_SLAVE_CLOCKS is the number of clocks if the "idle" phase between the end of a response and the beginning of the next one. It corresponds to tSendDelay in the FSI specification. The default value in the slave is 16 clocks. 100 is way overkill and significantly reduces the driver performance. This changes it to 20 (which gives the HW a bit of margin still just in case). Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Christopher Bostic Tested-by: Joel Stanley --- drivers/fsi/fsi-master-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/fsi') diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c index c82bbd35276e..029b0a5b6d89 100644 --- a/drivers/fsi/fsi-master-gpio.c +++ b/drivers/fsi/fsi-master-gpio.c @@ -49,7 +49,7 @@ #define FSI_GPIO_CRC_SIZE 4 #define FSI_GPIO_MSG_ID_SIZE 2 #define FSI_GPIO_MSG_RESPID_SIZE 2 -#define FSI_GPIO_PRIME_SLAVE_CLOCKS 100 +#define FSI_GPIO_PRIME_SLAVE_CLOCKS 20 struct fsi_master_gpio { struct fsi_master master; -- cgit v1.2.3-59-g8ed1b