From 1c2928e3e3212252b505b746ec10951027a95813 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 18 Dec 2018 13:59:31 +0200 Subject: regmap: regmap-irq/gpio-max77620: add level-irq support Add level active IRQ support to regmap-irq irqchip. Change breaks existing regmap-irq type setting. Convert the existing drivers which use regmap-irq with trigger type setting (gpio-max77620) to work with this new approach. So we do not magically support level-active IRQs on gpio-max77620 - but add support to the regmap-irq for chips which support them =) We do not support distinguishing situation where HW supports rising and falling edge detection but not both. Separating this would require inventing yet another flags for IRQ types. Signed-off-by: Matti Vaittinen Signed-off-by: Mark Brown --- drivers/gpio/gpio-max77620.c | 96 +++++++++++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 32 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c index 538bce4b5b42..65fa3a198ebd 100644 --- a/drivers/gpio/gpio-max77620.c +++ b/drivers/gpio/gpio-max77620.c @@ -25,60 +25,92 @@ struct max77620_gpio { static const struct regmap_irq max77620_gpio_irqs[] = { [0] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 0, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 0, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [1] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 1, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 1, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [2] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 2, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 2, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [3] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 3, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 3, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [4] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 4, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 4, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [5] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 5, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 5, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [6] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 6, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 6, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, [7] = { - .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7, - .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING, - .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING, .reg_offset = 0, - .type_reg_offset = 7, + .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7, + .type = { + .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING, + .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING, + .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK, + .type_reg_offset = 7, + .types_supported = IRQ_TYPE_EDGE_BOTH, + }, }, }; -- cgit v1.2.3-59-g8ed1b