From 36d26912e8d854853e3cdb300664db274a6636cf Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 29 Sep 2020 14:52:09 -0400 Subject: drm/amd/display: Add support for DCN302 (v2) - add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by: Joshua Aberback Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c') diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 270a8182682d..0b0b840a006c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -186,6 +186,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); break; } +#if defined(CONFIG_DRM_AMD_DC_DCN3_02) + if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) { + dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + break; + } +#endif #endif dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); break; -- cgit v1.2.3-59-g8ed1b