From 5fdb7c4c7f2691efd760b0b0dc00da4a3699f1a6 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 28 Jun 2019 13:39:41 -0400 Subject: drm/amd/display: Expose audio inst from DC to DM [Why] In order to give pin notifications to the sound driver from DM we need to know whether audio is enabled on a stream and what pin it's using from DC. [How] Expose the instance via stream status if it's a mapped resource for the stream. It will be -1 if there's no audio mapped. Cc: Leo Li Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/core') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 173fcfb5abe6..48dfb305a0b0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2011,6 +2011,9 @@ enum dc_status resource_map_pool_resources( if (context->streams[i] == stream) { context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id; + context->stream_status[i].audio_inst = + pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; + return DC_OK; } -- cgit v1.2.3-59-g8ed1b From 41a5a2a8531f95d18bb4efddea581ccb469e8ee5 Mon Sep 17 00:00:00 2001 From: hersen wu Date: Wed, 26 Jun 2019 13:06:07 -0400 Subject: drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq [WHY] dc sw clock implementation of navi10 and raven are not exact the same. dcccg, dchub reference clock initialization is done after dc calls vbios dispcontroller_init table. for raven family, before dispcontroller_init is called by dc, the ref clk values are referred by sw clock implementation and program asic register using wrong values. this causes dchub pstate error. This need provide valid ref clk values. for navi10, since dispcontroller_init is not called, dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will hit aeert. this need remove hubbub2_get_dchub_ref_freq from this location and move to dcn20_init_hw. [HOW] for all asic, initialize dccg, dchub ref clk with data from vbios firmware table by default. for raven asic family, use these data from vbios, for asic which support sw dccg component, like navi10, read ref clk by sw dccg functions and update the ref clk. Signed-off-by: hersen wu Reviewed-by: Jun Lei Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 42 +++++++++------------- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 25 +++++++++++++ 2 files changed, 41 insertions(+), 26 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/core') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 48dfb305a0b0..51a78283a86d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -175,32 +175,22 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, if (res_pool != NULL) { struct dc_firmware_info fw_info = { { 0 } }; - if (dc->ctx->dc_bios->funcs->get_firmware_info( - dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { - res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; - - if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { - // On FPGA these dividers are currently not configured by GDB - res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - } else if (res_pool->dccg && res_pool->hubbub) { - // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error - // as this value must be known for DCHUB programming - (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, - fw_info.pll_info.crystal_frequency, - &res_pool->ref_clocks.dccg_ref_clock_inKhz); - - // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error - (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, - res_pool->ref_clocks.dccg_ref_clock_inKhz, - &res_pool->ref_clocks.dchub_ref_clock_inKhz); - } else { - // Not all ASICs have DCCG sw component - res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - } - } else - ASSERT_CRITICAL(false); + if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios, + &fw_info) == BP_RESULT_OK) { + res_pool->ref_clocks.xtalin_clock_inKhz = + fw_info.pll_info.crystal_frequency; + /* initialize with firmware data first, no all + * ASIC have DCCG SW component. FPGA or + * simulation need initialization of + * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz + * with xtalin_clock_inKhz + */ + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } else + ASSERT_CRITICAL(false); } return res_pool; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 6925d25d2457..0b84a322b8a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -523,6 +523,7 @@ static void dcn20_init_hw(struct dc *dc) struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; struct dc_state *context = dc->current_state; + struct dc_firmware_info fw_info = { { 0 } }; if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); @@ -546,6 +547,30 @@ static void dcn20_init_hw(struct dc *dc) } else { if (!dcb->funcs->is_accelerated_mode(dcb)) { bios_golden_init(dc); + if (dc->ctx->dc_bios->funcs->get_firmware_info( + dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { + res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + if (res_pool->dccg && res_pool->hubbub) { + + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } + } + } else + ASSERT_CRITICAL(false); disable_vga(dc->hwseq); } -- cgit v1.2.3-59-g8ed1b