From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 144 +++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/dc_helper.c (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c new file mode 100644 index 000000000000..3a80b0c08ae4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -0,0 +1,144 @@ +/* + * dc_helper.c + * + * Created on: Aug 30, 2016 + * Author: agrodzov + */ +#include "dm_services.h" +#include + +uint32_t generic_reg_update_ex(const struct dc_context *ctx, + uint32_t addr, uint32_t reg_val, int n, + uint8_t shift1, uint32_t mask1, uint32_t field_value1, + ...) +{ + uint32_t shift, mask, field_value; + int i = 1; + + va_list ap; + va_start(ap, field_value1); + + reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); + + while (i < n) { + shift = va_arg(ap, uint32_t); + mask = va_arg(ap, uint32_t); + field_value = va_arg(ap, uint32_t); + + reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); + i++; + } + + dm_write_reg(ctx, addr, reg_val); + va_end(ap); + + return reg_val; +} + +uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, + uint8_t shift, uint32_t mask, uint32_t *field_value) +{ + uint32_t reg_val = dm_read_reg(ctx, addr); + *field_value = get_reg_field_value_ex(reg_val, mask, shift); + return reg_val; +} + +uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2) +{ + uint32_t reg_val = dm_read_reg(ctx, addr); + *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); + *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); + return reg_val; +} + +uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3) +{ + uint32_t reg_val = dm_read_reg(ctx, addr); + *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); + *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); + *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); + return reg_val; +} + +uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3, + uint8_t shift4, uint32_t mask4, uint32_t *field_value4, + uint8_t shift5, uint32_t mask5, uint32_t *field_value5) +{ + uint32_t reg_val = dm_read_reg(ctx, addr); + *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); + *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); + *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); + *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); + *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); + return reg_val; +} + +/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer + * compiler won't be able to check for size match and is prone to stack corruption type of bugs + +uint32_t generic_reg_get(const struct dc_context *ctx, + uint32_t addr, int n, ...) +{ + uint32_t shift, mask; + uint32_t *field_value; + uint32_t reg_val; + int i = 0; + + reg_val = dm_read_reg(ctx, addr); + + va_list ap; + va_start(ap, n); + + while (i < n) { + shift = va_arg(ap, uint32_t); + mask = va_arg(ap, uint32_t); + field_value = va_arg(ap, uint32_t *); + + *field_value = get_reg_field_value_ex(reg_val, mask, shift); + i++; + } + + va_end(ap); + + return reg_val; +} +*/ + +uint32_t generic_reg_wait(const struct dc_context *ctx, + uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, + unsigned int delay_between_poll_us, unsigned int time_out_num_tries, + const char *func_name) +{ + uint32_t field_value; + uint32_t reg_val; + int i; + + for (i = 0; i <= time_out_num_tries; i++) { + if (i) { + if (0 < delay_between_poll_us && delay_between_poll_us < 1000) + udelay(delay_between_poll_us); + + if (delay_between_poll_us > 1000) + msleep(delay_between_poll_us/1000); + } + + reg_val = dm_read_reg(ctx, addr); + + field_value = get_reg_field_value_ex(reg_val, mask, shift); + + if (field_value == condition_value) + return reg_val; + } + + DC_ERR("REG_WAIT timeout %dus * %d tries - %s", + delay_between_poll_us, time_out_num_tries, func_name); + return reg_val; +} -- cgit v1.2.3-59-g8ed1b From 8318a7eb988c62fa231c71538628ba85d4fbe7ef Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 2 Dec 2016 10:55:32 -0500 Subject: drm/amd/display: add newline to generic_reg_wait timeout message Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 3a80b0c08ae4..c5ff7b6d733d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -138,7 +138,7 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, return reg_val; } - DC_ERR("REG_WAIT timeout %dus * %d tries - %s", + DC_ERR("REG_WAIT timeout %dus * %d tries - %s\n", delay_between_poll_us, time_out_num_tries, func_name); return reg_val; } -- cgit v1.2.3-59-g8ed1b From 98d2cc2b03d937af36ce5ef227ae57232bbe8471 Mon Sep 17 00:00:00 2001 From: Andrew Wong Date: Mon, 12 Dec 2016 11:17:06 -0500 Subject: drm/amd/display: Change locking of registers when flipping frames. - Introduce GRPH_UPDATE_LOCK around programming surface flip. - Remove the now unused graphic surface lock. - Add macros to get and set four registers - both immediate and H Retrace should not be enabled at the same time Signed-off-by: Andrew Wong Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-------- drivers/gpu/drm/amd/display/dc/dc_helper.c | 14 ++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 11 +++-------- .../gpu/drm/amd/display/dc/dce110/dce110_mem_input.c | 17 +++++++++++++++-- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +-- drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 13 +++++++++++++ 6 files changed, 47 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 41df500817ad..75b6e404d016 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1468,11 +1468,6 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda continue; if (updates[i].flip_addr) { - core_dc->hwss.pipe_control_lock( - core_dc->hwseq, - pipe_ctx->pipe_idx, - PIPE_LOCK_CONTROL_SURFACE, - true); core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); } @@ -1485,7 +1480,6 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda core_dc->hwss.pipe_control_lock( core_dc->hwseq, pipe_ctx->pipe_idx, - PIPE_LOCK_CONTROL_SURFACE | PIPE_LOCK_CONTROL_GRAPHICS | PIPE_LOCK_CONTROL_SCL | PIPE_LOCK_CONTROL_BLENDER | @@ -1515,8 +1509,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda pipe_ctx->pipe_idx, PIPE_LOCK_CONTROL_GRAPHICS | PIPE_LOCK_CONTROL_SCL | - PIPE_LOCK_CONTROL_BLENDER | - PIPE_LOCK_CONTROL_SURFACE, + PIPE_LOCK_CONTROL_BLENDER, false); } break; diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index c5ff7b6d733d..a950dd53bca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -65,6 +65,20 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, return reg_val; } +uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3, + uint8_t shift4, uint32_t mask4, uint32_t *field_value4) +{ + uint32_t reg_val = dm_read_reg(ctx, addr); + *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); + *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); + *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); + *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); + return reg_val; +} + uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index dd1cf5e6e949..cd9a371ae237 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -49,12 +49,11 @@ void dce_pipe_control_lock(struct dce_hwseq *hws, bool lock) { uint32_t lock_val = lock ? 1 : 0; - uint32_t dcp_grph, scl, dcp_grph_surf, blnd, update_lock_mode; + uint32_t dcp_grph, scl, blnd, update_lock_mode; - uint32_t val = REG_GET_5(BLND_V_UPDATE_LOCK[blnd_inst], + uint32_t val = REG_GET_4(BLND_V_UPDATE_LOCK[blnd_inst], BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph, BLND_SCL_V_UPDATE_LOCK, &scl, - BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf, BLND_BLND_V_UPDATE_LOCK, &blnd, BLND_V_UPDATE_LOCK_MODE, &update_lock_mode); @@ -64,19 +63,15 @@ void dce_pipe_control_lock(struct dce_hwseq *hws, if (control_mask & PIPE_LOCK_CONTROL_SCL) scl = lock_val; - if (control_mask & PIPE_LOCK_CONTROL_SURFACE) - dcp_grph_surf = lock_val; - if (control_mask & PIPE_LOCK_CONTROL_BLENDER) blnd = lock_val; if (control_mask & PIPE_LOCK_CONTROL_MODE) update_lock_mode = lock_val; - REG_SET_5(BLND_V_UPDATE_LOCK[blnd_inst], val, + REG_SET_4(BLND_V_UPDATE_LOCK[blnd_inst], val, BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph, BLND_SCL_V_UPDATE_LOCK, scl, - BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, dcp_grph_surf, BLND_BLND_V_UPDATE_LOCK, blnd, BLND_V_UPDATE_LOCK_MODE, update_lock_mode); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index af9d682f8943..a20feaedfca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -113,16 +113,25 @@ bool dce110_mem_input_program_surface_flip_and_addr( struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); uint32_t value = 0; + uint32_t value_old = 0; + uint32_t lock_value = 0; + + lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); + set_reg_field_value(lock_value, 1, GRPH_UPDATE, GRPH_UPDATE_LOCK); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value); value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL)); + value_old = value; if (flip_immediate) { - set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); + set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); } else { set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); } - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value); + if (value != value_old) { + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value); + } switch (address->type) { case PLN_ADDR_TYPE_GRAPHICS: @@ -147,6 +156,10 @@ bool dce110_mem_input_program_surface_flip_and_addr( if (flip_immediate) mem_input->current_address = *address; + lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); + set_reg_field_value(lock_value, 0, GRPH_UPDATE, GRPH_UPDATE_LOCK); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value); + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 50d499cc01a4..fcaf2c71e4eb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -40,8 +40,7 @@ enum pipe_lock_control { PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0, PIPE_LOCK_CONTROL_BLENDER = 1 << 1, PIPE_LOCK_CONTROL_SCL = 1 << 2, - PIPE_LOCK_CONTROL_SURFACE = 1 << 3, - PIPE_LOCK_CONTROL_MODE = 1 << 4 + PIPE_LOCK_CONTROL_MODE = 1 << 3 }; struct dce_hwseq; diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h index dbc8424f7b69..a07817472089 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -143,6 +143,13 @@ FN(reg_name, f2), v2, \ FN(reg_name, f3), v3) +#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ + generic_reg_get4(CTX, REG(reg_name), \ + FN(reg_name, f1), v1, \ + FN(reg_name, f2), v2, \ + FN(reg_name, f3), v3, \ + FN(reg_name, f4), v4) + #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ generic_reg_get5(CTX, REG(reg_name), \ FN(reg_name, f1), v1, \ @@ -280,6 +287,12 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3); +uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3, + uint8_t shift4, uint32_t mask4, uint32_t *field_value4); + uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, -- cgit v1.2.3-59-g8ed1b From 11589813e6dfd72093d0e7f53114d6478f689d91 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 7 Jun 2017 15:02:34 -0400 Subject: drm/amd/display: fix enable_optc_clock reg_wait timeouts Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 8 +++++++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 8 ++++---- 2 files changed, 11 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index a950dd53bca4..87fd5b9c8a16 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -135,6 +135,9 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, uint32_t reg_val; int i; + if (ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) + time_out_num_tries *= 20; + for (i = 0; i <= time_out_num_tries; i++) { if (i) { if (0 < delay_between_poll_us && delay_between_poll_us < 1000) @@ -152,7 +155,10 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, return reg_val; } - DC_ERR("REG_WAIT timeout %dus * %d tries - %s\n", + dm_error("REG_WAIT timeout %dus * %d tries - %s\n", delay_between_poll_us, time_out_num_tries, func_name); + if (ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + BREAK_TO_DEBUGGER(); + return reg_val; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index d7072132d456..c5a636c750fa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -449,7 +449,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable) REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, 1, - 20000, 200000); + 2000, 500); /* Enable clock */ REG_UPDATE(OTG_CLOCK_CONTROL, @@ -457,7 +457,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable) REG_WAIT(OTG_CLOCK_CONTROL, OTG_CLOCK_ON, 1, - 20000, 200000); + 2000, 500); } else { REG_UPDATE_2(OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, 0, @@ -465,7 +465,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable) REG_WAIT(OTG_CLOCK_CONTROL, OTG_CLOCK_ON, 0, - 20000, 200000); + 2000, 500); REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, 0, @@ -473,7 +473,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable) REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, 0, - 20000, 200000); + 2000, 500); } } -- cgit v1.2.3-59-g8ed1b From f0558542a72e72919dae2ac2187847ec312c2bcb Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 1 Jun 2017 18:35:54 -0400 Subject: drm/amd/display: redesign mpc Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 10 +- drivers/gpu/drm/amd/display/dc/dc_helper.c | 10 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 105 +++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 336 +++++---------------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 102 +++---- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 73 +++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 12 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 81 ++--- 9 files changed, 228 insertions(+), 502 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index f0f688b99d37..66f0595a4c20 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -517,6 +517,7 @@ static void split_stream_across_pipes( secondary_pipe->stream = primary_pipe->stream; secondary_pipe->tg = primary_pipe->tg; + secondary_pipe->mpcc = pool->mpcc[secondary_pipe->pipe_idx]; secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx]; secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx]; secondary_pipe->xfm = pool->transforms[secondary_pipe->pipe_idx]; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b7f31b985b4f..c51ec617eff7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1008,8 +1008,6 @@ static int acquire_first_split_pipe( if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { - int mpc_idx = pipe_ctx->mpc_idx; - pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; if (pipe_ctx->bottom_pipe) pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; @@ -1021,8 +1019,8 @@ static int acquire_first_split_pipe( pipe_ctx->xfm = pool->transforms[i]; pipe_ctx->opp = pool->opps[i]; pipe_ctx->dis_clk = pool->display_clock; + pipe_ctx->mpcc = pool->mpcc[i]; pipe_ctx->pipe_idx = i; - pipe_ctx->mpc_idx = mpc_idx; pipe_ctx->stream = stream; return i; @@ -1243,6 +1241,9 @@ static int acquire_first_free_pipe( if (!res_ctx->pipe_ctx[i].stream) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + pipe_ctx->mpcc = pool->mpcc[i]; +#endif pipe_ctx->tg = pool->timing_generators[i]; pipe_ctx->mi = pool->mis[i]; pipe_ctx->ipp = pool->ipps[i]; @@ -1251,9 +1252,6 @@ static int acquire_first_free_pipe( pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - pipe_ctx->mpc_idx = -1; -#endif pipe_ctx->stream = stream; return i; diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 87fd5b9c8a16..8ed1440d2b01 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -135,8 +135,11 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, uint32_t reg_val; int i; - if (ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) - time_out_num_tries *= 20; + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { + /* 35 seconds */ + delay_between_poll_us = 35000; + time_out_num_tries = 1000; + } for (i = 0; i <= time_out_num_tries; i++) { if (i) { @@ -157,7 +160,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, dm_error("REG_WAIT timeout %dus * %d tries - %s\n", delay_between_poll_us, time_out_num_tries, func_name); - if (ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + + if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) BREAK_TO_DEBUGGER(); return reg_val; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index f2b581faa9b7..f509dfd97f23 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -592,9 +592,19 @@ static void init_hw(struct core_dc *dc) for (i = 0; i < dc->res_pool->pipe_count; i++) { struct timing_generator *tg = dc->res_pool->timing_generators[i]; + struct mpcc *mpcc = + dc->res_pool->mpcc[i]; + struct mpcc_cfg mpcc_cfg; + + lock_otg_master_update(dc->ctx, tg->inst); + mpcc_cfg.opp_id = 0xf; + mpcc_cfg.top_dpp_id = 0xf; + mpcc_cfg.bot_mpcc_id = 0xf; + mpcc_cfg.top_of_tree = true; + mpcc->funcs->set(mpcc, &mpcc_cfg); + unlock_otg_master(dc->ctx, tg->inst); tg->funcs->disable_vga(tg); - /* Blank controller using driver code instead of * command table. */ @@ -819,8 +829,7 @@ static void reset_front_end_for_pipe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc); - struct mpc_tree_cfg *tree_cfg = NULL; + struct mpcc_cfg mpcc_cfg; if (!pipe_ctx->surface) return; @@ -829,20 +838,14 @@ static void reset_front_end_for_pipe( lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst); - /* TODO: build stream pipes group id. For now, use stream otg - * id as pipe group id - */ - tree_cfg = &dc->current_context->res_ctx.mpc_tree[pipe_ctx->mpc_idx]; - - if (!dcn10_remove_dpp(mpc, tree_cfg, pipe_ctx->pipe_idx)) { - dm_logger_write(dc->ctx->logger, LOG_RESOURCE, - "%s: failed to find dpp to be removed!\n", - __func__); - } + mpcc_cfg.opp_id = 0xf; + mpcc_cfg.top_dpp_id = 0xf; + mpcc_cfg.bot_mpcc_id = 0xf; + mpcc_cfg.top_of_tree = !pipe_ctx->top_pipe; + pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); pipe_ctx->top_pipe = NULL; pipe_ctx->bottom_pipe = NULL; - pipe_ctx->mpc_idx = -1; unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst); @@ -850,8 +853,6 @@ static void reset_front_end_for_pipe( wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx); - wait_mpcc_idle(mpc, pipe_ctx->pipe_idx); - disable_clocks(dc->ctx, pipe_ctx->pipe_idx); pipe_ctx->xfm->funcs->transform_reset(pipe_ctx->xfm); @@ -893,14 +894,10 @@ static void reset_hw_ctx_wrap( reset_hw_ctx(dc, context, reset_front_end_for_pipe); /* Reset Back End*/ reset_hw_ctx(dc, context, reset_back_end_for_pipe); - - memcpy(context->res_ctx.mpc_tree, - dc->current_context->res_ctx.mpc_tree, - sizeof(struct mpc_tree_cfg) * dc->res_pool->pipe_count); } -static bool patch_address_for_sbs_tb_stereo(struct pipe_ctx *pipe_ctx, - PHYSICAL_ADDRESS_LOC *addr) +static bool patch_address_for_sbs_tb_stereo( + struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { struct core_surface *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && @@ -1670,14 +1667,10 @@ static void update_dchubp_dpp( struct input_pixel_processor *ipp = pipe_ctx->ipp; struct core_surface *surface = pipe_ctx->surface; union plane_size size = surface->public.plane_size; - struct mpc_tree_cfg *tree_cfg = NULL; struct default_adjustment ocsc = {0}; - enum dc_color_space color_space; struct tg_color black_color = {0}; - struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc); - struct pipe_ctx *temp_pipe; - int i; - int tree_pos = 0; + struct mpcc_cfg mpcc_cfg; + struct pipe_ctx *top_pipe; bool per_pixel_alpha = surface->public.per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ @@ -1716,39 +1709,23 @@ static void update_dchubp_dpp( 1, IPP_OUTPUT_FORMAT_12_BIT_FIX); - /* mpc TODO un-hardcode object ids - * for pseudo code pipe_move.c : - * add_plane_mpcc(added_plane_inst, mpcc_inst, ...); - * Do we want to cache the tree_cfg? - */ - - /* TODO: build stream pipes group id. For now, use stream otg - * id as pipe group id - */ pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha; - pipe_ctx->mpc_idx = pipe_ctx->tg->inst; - tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx]; - if (tree_cfg->num_pipes == 0) { - tree_cfg->opp_id = pipe_ctx->tg->inst; - for (i = 0; i < MAX_PIPES; i++) { - tree_cfg->dpp[i] = 0xf; - tree_cfg->mpcc[i] = 0xf; - } - } - - for (temp_pipe = pipe_ctx->top_pipe; - temp_pipe != NULL; temp_pipe = temp_pipe->top_pipe) - tree_pos++; - - tree_cfg->dpp[tree_pos] = pipe_ctx->pipe_idx; - tree_cfg->mpcc[tree_pos] = pipe_ctx->pipe_idx; - tree_cfg->per_pixel_alpha[tree_pos] = per_pixel_alpha; - tree_cfg->num_pipes = tree_pos + 1; - dcn10_set_mpc_tree(mpc, tree_cfg); + for (top_pipe = pipe_ctx; top_pipe != NULL; top_pipe = top_pipe->top_pipe) + mpcc_cfg.opp_id = top_pipe->opp->inst; + mpcc_cfg.top_dpp_id = pipe_ctx->pipe_idx; + if (pipe_ctx->bottom_pipe) + mpcc_cfg.bot_mpcc_id = pipe_ctx->bottom_pipe->mpcc->inst; + else + mpcc_cfg.bot_mpcc_id = 0xf; + mpcc_cfg.top_of_tree = !pipe_ctx->top_pipe; + mpcc_cfg.per_pixel_alpha = per_pixel_alpha; + if (!dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].surface) + pipe_ctx->mpcc->funcs->wait_for_idle(pipe_ctx->mpcc); + pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); - color_space = pipe_ctx->stream->public.output_color_space; - color_space_to_black_color(dc, color_space, &black_color); - dcn10_set_mpc_background_color(mpc, pipe_ctx->pipe_idx, &black_color); + color_space_to_black_color( + dc, pipe_ctx->stream->public.output_color_space, &black_color); + pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color); pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; /* scaler configuration */ @@ -1853,13 +1830,8 @@ static void dcn10_apply_ctx_for_surface( /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) { - memcpy(context->res_ctx.mpc_tree, - dc->current_context->res_ctx.mpc_tree, - sizeof(struct mpc_tree_cfg) * dc->res_pool->pipe_count); - + if (!pipe_ctx->top_pipe) program_all_pipe_in_tree(dc, pipe_ctx, context); - } } dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, @@ -1927,8 +1899,7 @@ static void dcn10_apply_ctx_for_surface( if ((!pipe_ctx->surface && old_pipe_ctx->surface) || (!pipe_ctx->stream && old_pipe_ctx->stream)) - reset_front_end_for_pipe(dc, - old_pipe_ctx, dc->current_context); + reset_front_end_for_pipe(dc, old_pipe_ctx, dc->current_context); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 58f80114e36b..19af0ee86191 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -27,34 +27,26 @@ #include "dcn10_mpc.h" #define REG(reg)\ - mpc->mpc_regs->reg + mpcc10->mpcc_regs->reg #define CTX \ - mpc->base.ctx + mpcc10->base.ctx #undef FN #define FN(reg_name, field_name) \ - mpc->mpc_shift->field_name, mpc->mpc_mask->field_name + mpcc10->mpcc_shift->field_name, mpcc10->mpcc_mask->field_name #define MODE_TOP_ONLY 1 #define MODE_BLEND 3 +#define BLND_PP_ALPHA 0 +#define BLND_GLOBAL_ALPHA 2 -/* Internal function to set mpc output mux */ -static void set_output_mux(struct dcn10_mpc *mpc, - uint8_t opp_id, - uint8_t mpcc_id) -{ - if (mpcc_id != 0xf) - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 1); - - REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id); -} -void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc, - unsigned int mpcc_inst, - struct tg_color *bg_color) +void dcn10_mpcc_set_bg_color( + struct mpcc *mpcc, + struct tg_color *bg_color) { + struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc); /* mpc color is 12 bit. tg_color is 10 bit */ /* todo: might want to use 16 bit to represent color and have each * hw block translate to correct color depth. @@ -63,277 +55,89 @@ void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc, uint32_t bg_g_y = bg_color->color_g_y << 2; uint32_t bg_b_cb = bg_color->color_b_cb << 2; - REG_SET(MPCC_BG_R_CR[mpcc_inst], 0, + REG_SET(MPCC_BG_R_CR, 0, MPCC_BG_R_CR, bg_r_cr); - REG_SET(MPCC_BG_G_Y[mpcc_inst], 0, + REG_SET(MPCC_BG_G_Y, 0, MPCC_BG_G_Y, bg_g_y); - REG_SET(MPCC_BG_B_CB[mpcc_inst], 0, + REG_SET(MPCC_BG_B_CB, 0, MPCC_BG_B_CB, bg_b_cb); } -/* This function programs MPC tree configuration - * Assume it is the initial time to setup MPC tree_configure, means - * the instance of dpp/mpcc/opp specified in structure tree_cfg are - * in idle status. - * Before invoke this function, ensure that master lock of OPTC specified - * by opp_id is set. - * - * tree_cfg[in] - new MPC_TREE_CFG - */ - -void dcn10_set_mpc_tree(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg) +static void set_output_mux(struct dcn10_mpcc *mpcc10, int opp_id, int mpcc_id) { - int i; - - for (i = 0; i < tree_cfg->num_pipes; i++) { - uint8_t mpcc_inst = tree_cfg->mpcc[i]; - - REG_SET(MPCC_OPP_ID[mpcc_inst], 0, - MPCC_OPP_ID, tree_cfg->opp_id); - - REG_SET(MPCC_TOP_SEL[mpcc_inst], 0, - MPCC_TOP_SEL, tree_cfg->dpp[i]); - - if (i == tree_cfg->num_pipes-1) { - REG_SET(MPCC_BOT_SEL[mpcc_inst], 0, - MPCC_BOT_SEL, 0xF); - - REG_UPDATE(MPCC_CONTROL[mpcc_inst], - MPCC_MODE, MODE_TOP_ONLY); - } else { - REG_SET(MPCC_BOT_SEL[mpcc_inst], 0, - MPCC_BOT_SEL, tree_cfg->dpp[i+1]); - - REG_UPDATE(MPCC_CONTROL[mpcc_inst], - MPCC_MODE, MODE_BLEND); - } - - if (i == 0) - set_output_mux( - mpc, tree_cfg->opp_id, mpcc_inst); - - REG_UPDATE_2(MPCC_CONTROL[mpcc_inst], - MPCC_ALPHA_BLND_MODE, - tree_cfg->per_pixel_alpha[i] ? 0 : 2, - MPCC_ALPHA_MULTIPLIED_MODE, 0); - } + ASSERT(mpcc10->opp_id == 0xf || opp_id == mpcc10->opp_id); + mpcc10->opp_id = opp_id; + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1); + REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id); } -/* - * This is the function to remove current MPC tree specified by tree_cfg - * Before invoke this function, ensure that master lock of OPTC specified - * by opp_id is set. - * - *tree_cfg[in/out] - current MPC_TREE_CFG - */ -void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg) +static void reset_output_mux(struct dcn10_mpcc *mpcc10) { - int i; - - for (i = 0; i < tree_cfg->num_pipes; i++) { - uint8_t mpcc_inst = tree_cfg->mpcc[i]; - - REG_SET(MPCC_OPP_ID[mpcc_inst], 0, - MPCC_OPP_ID, 0xf); - - REG_SET(MPCC_TOP_SEL[mpcc_inst], 0, - MPCC_TOP_SEL, 0xf); - - REG_SET(MPCC_BOT_SEL[mpcc_inst], 0, - MPCC_BOT_SEL, 0xF); - - /* add remove dpp/mpcc pair into pending list - * TODO FPGA AddToPendingList if empty from pseudo code - */ - tree_cfg->dpp[i] = 0xf; - tree_cfg->mpcc[i] = 0xf; - tree_cfg->per_pixel_alpha[i] = false; - } - set_output_mux(mpc, tree_cfg->opp_id, 0xf); - tree_cfg->opp_id = 0xf; - tree_cfg->num_pipes = 0; + REG_SET(MUX[mpcc10->opp_id], 0, MPC_OUT_MUX, 0xf); + REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->opp_id], OPP_PIPE_CLOCK_EN, 0); + mpcc10->opp_id = 0xf; } -/* TODO FPGA: how to handle DPP? - * Function to remove one of pipe from MPC configure tree by dpp idx - * Before invoke this function, ensure that master lock of OPTC specified - * by opp_id is set - * This function can be invoke multiple times to remove more than 1 dpps. - * - * tree_cfg[in/out] - current MPC_TREE_CFG - * idx[in] - index of dpp from tree_cfg to be removed. - */ -bool dcn10_remove_dpp(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - uint8_t idx) +static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) { - int i; - uint8_t mpcc_inst; - bool found = false; - - /* find dpp_idx from dpp array of tree_cfg */ - for (i = 0; i < tree_cfg->num_pipes; i++) { - if (tree_cfg->dpp[i] == idx) { - found = true; - break; - } - } - - if (!found) { - BREAK_TO_DEBUGGER(); - return false; - } - mpcc_inst = tree_cfg->mpcc[i]; - - REG_SET(MPCC_OPP_ID[mpcc_inst], 0, - MPCC_OPP_ID, 0xf); - - REG_SET(MPCC_TOP_SEL[mpcc_inst], 0, - MPCC_TOP_SEL, 0xf); - - REG_SET(MPCC_BOT_SEL[mpcc_inst], 0, - MPCC_BOT_SEL, 0xf); - - if (i == 0) { - if (tree_cfg->num_pipes > 1) - set_output_mux(mpc, - tree_cfg->opp_id, tree_cfg->mpcc[i+1]); + struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc); + int alpha_blnd_mode = cfg->per_pixel_alpha ? + BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; + int mpcc_mode = cfg->bot_mpcc_id != 0xf ? + MODE_BLEND : MODE_TOP_ONLY; + + REG_SET(MPCC_OPP_ID, 0, + MPCC_OPP_ID, cfg->opp_id); + + REG_SET(MPCC_TOP_SEL, 0, + MPCC_TOP_SEL, cfg->top_dpp_id); + + REG_SET(MPCC_BOT_SEL, 0, + MPCC_BOT_SEL, cfg->bot_mpcc_id); + + REG_SET_4(MPCC_CONTROL, 0xffffffff, + MPCC_MODE, mpcc_mode, + MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, + MPCC_ALPHA_MULTIPLIED_MODE, 0/*TODO: cfg->per_pixel_alpha*/, + MPCC_BLND_ACTIVE_OVERLAP_ONLY, cfg->top_of_tree); + + if (cfg->top_of_tree) { + if (cfg->opp_id != 0xf) + set_output_mux(mpcc10, cfg->opp_id, mpcc->inst); else - set_output_mux(mpc, tree_cfg->opp_id, 0xf); - } else if (i == tree_cfg->num_pipes-1) { - mpcc_inst = tree_cfg->mpcc[i - 1]; - - REG_SET(MPCC_BOT_SEL[mpcc_inst], 0, - MPCC_BOT_SEL, 0xF); - - /* prev mpc is now last, set to top only*/ - REG_UPDATE(MPCC_CONTROL[mpcc_inst], - MPCC_MODE, MODE_TOP_ONLY); - } else { - mpcc_inst = tree_cfg->mpcc[i - 1]; - - REG_SET(MPCC_BOT_SEL[mpcc_inst], 0, - MPCC_BOT_SEL, tree_cfg->mpcc[i+1]); + reset_output_mux(mpcc10); } - - /* update tree_cfg structure */ - while (i < tree_cfg->num_pipes - 1) { - tree_cfg->dpp[i] = tree_cfg->dpp[i+1]; - tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1]; - tree_cfg->per_pixel_alpha[i] = tree_cfg->per_pixel_alpha[i+1]; - i++; - } - tree_cfg->num_pipes--; - - return true; } -/* TODO FPGA: how to handle DPP? - * Function to add DPP/MPCC pair into MPC configure tree by position. - * Before invoke this function, ensure that master lock of OPTC specified - * by opp_id is set - * This function can be invoke multiple times to add more than 1 pipes. - * - * tree_cfg[in/out] - current MPC_TREE_CFG - * dpp_idx[in] - index of an idle dpp insatnce to be added. - * mpcc_idx[in] - index of an idle mpcc instance to be added. - * poistion[in] - position of dpp/mpcc pair to be added into current tree_cfg - * 0 means insert to the most top layer of MPC tree - */ -void dcn10_add_dpp(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - uint8_t dpp_idx, - uint8_t mpcc_idx, - uint8_t per_pixel_alpha, - uint8_t position) +static void dcn10_mpcc_wait_idle(struct mpcc *mpcc) { - uint8_t prev; - uint8_t next; - - REG_SET(MPCC_OPP_ID[mpcc_idx], 0, - MPCC_OPP_ID, tree_cfg->opp_id); - REG_SET(MPCC_TOP_SEL[mpcc_idx], 0, - MPCC_TOP_SEL, dpp_idx); - - if (position == 0) { - /* idle dpp/mpcc is added to the top layer of tree */ - REG_SET(MPCC_BOT_SEL[mpcc_idx], 0, - MPCC_BOT_SEL, tree_cfg->mpcc[0]); + struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc); - /* bottom mpc is always top only */ - REG_UPDATE(MPCC_CONTROL[mpcc_idx], - MPCC_MODE, MODE_TOP_ONLY); - /* opp will get new output. from new added mpcc */ - set_output_mux(mpc, tree_cfg->opp_id, mpcc_idx); - - } else if (position == tree_cfg->num_pipes) { - /* idle dpp/mpcc is added to the bottom layer of tree */ - - /* get instance of previous bottom mpcc, set to middle layer */ - prev = tree_cfg->mpcc[position - 1]; - - REG_SET(MPCC_BOT_SEL[prev], 0, - MPCC_BOT_SEL, mpcc_idx); - - /* all mpcs other than bottom need to blend */ - REG_UPDATE(MPCC_CONTROL[prev], - MPCC_MODE, MODE_BLEND); - - /* mpcc_idx become new bottom mpcc*/ - REG_SET(MPCC_BOT_SEL[mpcc_idx], 0, - MPCC_BOT_SEL, 0xf); - - /* bottom mpc is always top only */ - REG_UPDATE(MPCC_CONTROL[mpcc_idx], - MPCC_MODE, MODE_TOP_ONLY); - } else { - /* idle dpp/mpcc is added to middle of tree */ - prev = tree_cfg->mpcc[position - 1]; /* mpc a */ - next = tree_cfg->mpcc[position]; /* mpc b */ - - /* connect mpc inserted below mpc a*/ - REG_SET(MPCC_BOT_SEL[prev], 0, - MPCC_BOT_SEL, mpcc_idx); + REG_WAIT(MPCC_STATUS, MPCC_IDLE, 1, 1000, 1000); +} - /* blend on mpc being inserted */ - REG_UPDATE(MPCC_CONTROL[mpcc_idx], - MPCC_MODE, MODE_BLEND); - /* Connect mpc b below one inserted */ - REG_SET(MPCC_BOT_SEL[mpcc_idx], 0, - MPCC_BOT_SEL, next); +const struct mpcc_funcs dcn10_mpcc_funcs = { + .set = dcn10_mpcc_set, + .wait_for_idle = dcn10_mpcc_wait_idle, + .set_bg_color = dcn10_mpcc_set_bg_color, +}; - } - /* premultiplied mode only if alpha is on for the layer*/ - REG_UPDATE_2(MPCC_CONTROL[mpcc_idx], - MPCC_ALPHA_BLND_MODE, - tree_cfg->per_pixel_alpha[position] ? 0 : 2, - MPCC_ALPHA_MULTIPLIED_MODE, 0); +void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10, + struct dc_context *ctx, + const struct dcn_mpcc_registers *mpcc_regs, + const struct dcn_mpcc_shift *mpcc_shift, + const struct dcn_mpcc_mask *mpcc_mask, + int inst) +{ + mpcc10->base.ctx = ctx; - /* - * iterating from the last mpc/dpp pair to the one being added, shift - * them down one position - */ - for (next = tree_cfg->num_pipes; next > position; next--) { - tree_cfg->dpp[next] = tree_cfg->dpp[next - 1]; - tree_cfg->mpcc[next] = tree_cfg->mpcc[next - 1]; - tree_cfg->per_pixel_alpha[next] = tree_cfg->per_pixel_alpha[next - 1]; - } + mpcc10->base.inst = inst; + mpcc10->base.funcs = &dcn10_mpcc_funcs; - /* insert the new mpc/dpp pair into the tree_cfg*/ - tree_cfg->dpp[position] = dpp_idx; - tree_cfg->mpcc[position] = mpcc_idx; - tree_cfg->per_pixel_alpha[position] = per_pixel_alpha; - tree_cfg->num_pipes++; -} + mpcc10->mpcc_regs = mpcc_regs; + mpcc10->mpcc_shift = mpcc_shift; + mpcc10->mpcc_mask = mpcc_mask; -void wait_mpcc_idle(struct dcn10_mpc *mpc, - uint8_t mpcc_id) -{ - REG_WAIT(MPCC_STATUS[mpcc_id], - MPCC_IDLE, 1, - 1000, 1000); + mpcc10->opp_id = inst; } - diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index 3e4eb655e913..0f9f1b97d238 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -22,45 +22,45 @@ * */ -#ifndef __DC_MPC_DCN10_H__ -#define __DC_MPC_DCN10_H__ +#ifndef __DC_MPCC_DCN10_H__ +#define __DC_MPCC_DCN10_H__ #include "mpc.h" -#define TO_DCN10_MPC(mpc_base)\ - container_of(mpc_base, struct dcn10_mpc, base) +#define TO_DCN10_MPCC(mpcc_base) \ + container_of(mpcc_base, struct dcn10_mpcc, base) -#define MAX_MPCC 4 -#define MAX_MPC_OUT 4 #define MAX_OPP 4 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ - SRII(MPCC_TOP_SEL, MPCC, inst),\ - SRII(MPCC_BOT_SEL, MPCC, inst),\ - SRII(MPCC_CONTROL, MPCC, inst),\ - SRII(MPCC_STATUS, MPCC, inst),\ - SRII(MPCC_OPP_ID, MPCC, inst),\ - SRII(MPCC_BG_G_Y, MPCC, inst),\ - SRII(MPCC_BG_R_CR, MPCC, inst),\ - SRII(MPCC_BG_B_CB, MPCC, inst),\ - SRII(MPCC_BG_B_CB, MPCC, inst),\ SRII(MUX, MPC_OUT, inst),\ SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst) -struct dcn_mpc_registers { - uint32_t MPCC_TOP_SEL[MAX_MPCC]; - uint32_t MPCC_BOT_SEL[MAX_MPCC]; - uint32_t MPCC_CONTROL[MAX_MPCC]; - uint32_t MPCC_STATUS[MAX_MPCC]; - uint32_t MPCC_OPP_ID[MAX_MPCC]; - uint32_t MPCC_BG_G_Y[MAX_MPCC]; - uint32_t MPCC_BG_R_CR[MAX_MPCC]; - uint32_t MPCC_BG_B_CB[MAX_MPCC]; - uint32_t MUX[MAX_MPC_OUT]; +#define MPCC_COMMON_REG_LIST_DCN1_0(inst) \ + SRI(MPCC_TOP_SEL, MPCC, inst),\ + SRI(MPCC_BOT_SEL, MPCC, inst),\ + SRI(MPCC_CONTROL, MPCC, inst),\ + SRI(MPCC_STATUS, MPCC, inst),\ + SRI(MPCC_OPP_ID, MPCC, inst),\ + SRI(MPCC_BG_G_Y, MPCC, inst),\ + SRI(MPCC_BG_R_CR, MPCC, inst),\ + SRI(MPCC_BG_B_CB, MPCC, inst),\ + SRI(MPCC_BG_B_CB, MPCC, inst) + +struct dcn_mpcc_registers { + uint32_t MPCC_TOP_SEL; + uint32_t MPCC_BOT_SEL; + uint32_t MPCC_CONTROL; + uint32_t MPCC_STATUS; + uint32_t MPCC_OPP_ID; + uint32_t MPCC_BG_G_Y; + uint32_t MPCC_BG_R_CR; + uint32_t MPCC_BG_B_CB; uint32_t OPP_PIPE_CONTROL[MAX_OPP]; + uint32_t MUX[MAX_OPP]; }; -#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ +#define MPCC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ @@ -75,7 +75,7 @@ struct dcn_mpc_registers { SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\ SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) -#define MPC_REG_FIELD_LIST(type) \ +#define MPCC_REG_FIELD_LIST(type) \ type MPCC_TOP_SEL;\ type MPCC_BOT_SEL;\ type MPCC_MODE;\ @@ -90,42 +90,28 @@ struct dcn_mpc_registers { type MPC_OUT_MUX;\ type OPP_PIPE_CLOCK_EN;\ -struct dcn_mpc_shift { - MPC_REG_FIELD_LIST(uint8_t) +struct dcn_mpcc_shift { + MPCC_REG_FIELD_LIST(uint8_t) }; -struct dcn_mpc_mask { - MPC_REG_FIELD_LIST(uint32_t) +struct dcn_mpcc_mask { + MPCC_REG_FIELD_LIST(uint32_t) }; -struct dcn10_mpc { - struct mpc base; - const struct dcn_mpc_registers *mpc_regs; - const struct dcn_mpc_shift *mpc_shift; - const struct dcn_mpc_mask *mpc_mask; -}; - -void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg); - -bool dcn10_remove_dpp(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - uint8_t idx); +struct dcn10_mpcc { + struct mpcc base; + const struct dcn_mpcc_registers *mpcc_regs; + const struct dcn_mpcc_shift *mpcc_shift; + const struct dcn_mpcc_mask *mpcc_mask; -void dcn10_add_dpp(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg, - uint8_t dpp_idx, - uint8_t mpcc_idx, - uint8_t per_pixel_alpha, - uint8_t position); - -void wait_mpcc_idle(struct dcn10_mpc *mpc, - uint8_t mpcc_id); + int opp_id; +}; -void dcn10_set_mpc_tree(struct dcn10_mpc *mpc, - struct mpc_tree_cfg *tree_cfg); +void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10, + struct dc_context *ctx, + const struct dcn_mpcc_registers *mpcc_regs, + const struct dcn_mpcc_shift *mpcc_shift, + const struct dcn_mpcc_mask *mpcc_mask, + int inst); -void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc, - unsigned int mpcc_inst, - struct tg_color *bg_color); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 6ada9a262721..142ac0613d5b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -336,19 +336,28 @@ static const struct dcn_transform_mask tf_mask = { }; -static const struct dcn_mpc_registers mpc_regs = { - MPC_COMMON_REG_LIST_DCN1_0(0), - MPC_COMMON_REG_LIST_DCN1_0(1), - MPC_COMMON_REG_LIST_DCN1_0(2), - MPC_COMMON_REG_LIST_DCN1_0(3), +#define mpcc_regs(id)\ +[id] = {\ + MPCC_COMMON_REG_LIST_DCN1_0(id),\ + MPC_COMMON_REG_LIST_DCN1_0(0),\ + MPC_COMMON_REG_LIST_DCN1_0(1),\ + MPC_COMMON_REG_LIST_DCN1_0(2),\ + MPC_COMMON_REG_LIST_DCN1_0(3),\ +} + +static const struct dcn_mpcc_registers mpcc_regs[] = { + mpcc_regs(0), + mpcc_regs(1), + mpcc_regs(2), + mpcc_regs(3), }; -static const struct dcn_mpc_shift mpc_shift = { - MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) +static const struct dcn_mpcc_shift mpcc_shift = { + MPCC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) }; -static const struct dcn_mpc_mask mpc_mask = { - MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), +static const struct dcn_mpcc_mask mpcc_mask = { + MPCC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), }; #define tg_regs(id)\ @@ -509,28 +518,22 @@ static struct output_pixel_processor *dcn10_opp_create( return &opp->base; } -static struct mpc *dcn10_mpc_create( - struct dc_context *ctx) +static struct mpcc *dcn10_mpcc_create( + struct dc_context *ctx, + int inst) { - struct dcn10_mpc *mpc = dm_alloc(sizeof(struct dcn10_mpc)); + struct dcn10_mpcc *mpcc10 = dm_alloc(sizeof(struct dcn10_mpcc)); - if (!mpc) + if (!mpcc10) return NULL; - mpc->base.ctx = ctx; - mpc->mpc_regs = &mpc_regs; - mpc->mpc_shift = &mpc_shift; - mpc->mpc_mask = &mpc_mask; + dcn10_mpcc_construct(mpcc10, ctx, + &mpcc_regs[inst], + &mpcc_shift, + &mpcc_mask, + inst); - return &mpc->base; -} - -static void dcn10_mpc_destroy(struct mpc **mpc_base) -{ - if (*mpc_base) - dm_free(TO_DCN10_MPC(*mpc_base)); - - *mpc_base = NULL; + return &mpcc10->base; } static struct timing_generator *dcn10_timing_generator_create( @@ -736,6 +739,11 @@ static void destruct(struct dcn10_resource_pool *pool) dm_free(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } + + if (pool->base.mpcc[i] != NULL) { + dm_free(TO_DCN10_MPCC(pool->base.mpcc[i])); + pool->base.mpcc[i] = NULL; + } } for (i = 0; i < pool->base.stream_enc_count; i++) { @@ -760,9 +768,6 @@ static void destruct(struct dcn10_resource_pool *pool) pool->base.dp_clock_source = NULL; } - if (pool->base.mpc != NULL) - dcn10_mpc_destroy(&pool->base.mpc); - if (pool->base.abm != NULL) dce_abm_destroy(&pool->base.abm); @@ -1007,6 +1012,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( idle_pipe->stream = head_pipe->stream; idle_pipe->tg = head_pipe->tg; + idle_pipe->mpcc = pool->mpcc[idle_pipe->pipe_idx]; idle_pipe->mi = pool->mis[idle_pipe->pipe_idx]; idle_pipe->ipp = pool->ipps[idle_pipe->pipe_idx]; idle_pipe->xfm = pool->transforms[idle_pipe->pipe_idx]; @@ -1427,10 +1433,14 @@ static bool construct( dm_error("DC: failed to create tg!\n"); goto otg_create_fail; } + pool->base.mpcc[i] = dcn10_mpcc_create(ctx, i); + if (pool->base.mpcc[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpcc!\n"); + goto mpcc_create_fail; + } } - pool->base.mpc = dcn10_mpc_create(ctx); - if (!resource_construct(num_virtual_links, dc, &pool->base, (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? &res_create_funcs : &res_create_maximus_funcs))) @@ -1444,6 +1454,7 @@ static bool construct( return true; disp_clk_create_fail: +mpcc_create_fail: otg_create_fail: opp_create_fail: transform_create_fail: diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d8a378dabb43..030841889803 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -236,6 +236,9 @@ struct resource_pool { struct output_pixel_processor *opps[MAX_PIPES]; struct timing_generator *timing_generators[MAX_PIPES]; struct stream_encoder *stream_enc[MAX_PIPES * 2]; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct mpcc *mpcc[MAX_PIPES]; +#endif unsigned int pipe_count; unsigned int underlay_pipe_index; @@ -259,9 +262,6 @@ struct resource_pool { struct abm *abm; struct dmcu *dmcu; -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct mpc *mpc; -#endif const struct resource_funcs *funcs; const struct resource_caps *res_cap; @@ -295,8 +295,9 @@ struct pipe_ctx { struct pipe_ctx *top_pipe; struct pipe_ctx *bottom_pipe; + #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - uint8_t mpc_idx; + struct mpcc *mpcc; struct _vcs_dpi_display_dlg_regs_st dlg_regs; struct _vcs_dpi_display_ttu_regs_st ttu_regs; struct _vcs_dpi_display_rq_regs_st rq_regs; @@ -306,9 +307,6 @@ struct pipe_ctx { struct resource_context { struct pipe_ctx pipe_ctx[MAX_PIPES]; -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct mpc_tree_cfg mpc_tree[MAX_PIPES]; -#endif bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index ec1a201747f2..38d158746cc5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -22,76 +22,29 @@ * */ -#ifndef __DC_MPC_H__ -#define __DC_MPC_H__ +#ifndef __DC_MPCC_H__ +#define __DC_MPCC_H__ -/* This structure define the mpc tree configuration - * num_pipes - number of pipes of the tree - * opp_id - instance id of OPP to drive MPC - * dpp- array of DPP index - * mpcc - array of MPCC index - * mode - the most bottom layer MPCC mode control. - * All other layers need to be program to 3 - * - * The connection will be: - * mpcc[num_pipes-1]->mpcc[num_pipes-2]->...->mpcc[1]->mpcc[0]->OPP[opp_id] - * dpp[0]->mpcc[0] - * dpp[1]->mpcc[1] - * ... - * dpp[num_pipes-1]->mpcc[num_pipes-1] - * mpcc[0] is the most top layer of MPC tree, - * mpcc[num_pipes-1] is the most bottom layer. - */ - -struct mpc_tree_cfg { - uint8_t num_pipes; - uint8_t opp_id; - /* dpp pipes for blend */ - uint8_t dpp[6]; - /* mpcc insatnces for blend */ - uint8_t mpcc[6]; - bool per_pixel_alpha[6]; -}; +#include "dc_hw_types.h" -struct mpcc_blnd_cfg { - /* 0- perpixel alpha, 1- perpixel alpha combined with global gain, - * 2- global alpha - */ - uint8_t alpha_mode; - uint8_t global_gain; - uint8_t global_alpha; - bool overlap_only; - bool pre_multiplied_alpha; +struct mpcc_cfg { + int top_dpp_id; + int bot_mpcc_id; + int opp_id; + bool per_pixel_alpha; + bool top_of_tree; }; -struct mpcc_sm_cfg { - bool enable; - /* 0-single plane, 2-row subsampling, 4-column subsampling, - * 6-checkboard subsampling - */ - uint8_t sm_mode; - bool frame_alt; /* 0- disable, 1- enable */ - bool field_alt; /* 0- disable, 1- enable */ - /* 0-no force, 2-force frame polarity from top, - * 3-force frame polarity from bottom - */ - uint8_t force_next_frame_porlarity; - /* 0-no force, 2-force field polarity from top, - * 3-force field polarity from bottom - */ - uint8_t force_next_field_polarity; -}; - -struct mpcc_vupdate_lock_cfg { - bool cfg_lock; - bool adr_lock; - bool adr_cfg_lock; - bool cur0_lock; - bool cur1_lock; +struct mpcc { + const struct mpcc_funcs *funcs; + struct dc_context *ctx; + int inst; }; -struct mpc { - struct dc_context *ctx; +struct mpcc_funcs { + void (*set)(struct mpcc *mpcc, struct mpcc_cfg *cfg); + void (*wait_for_idle)(struct mpcc *mpcc); + void (*set_bg_color)( struct mpcc *mpcc, struct tg_color *bg_color); }; #endif -- cgit v1.2.3-59-g8ed1b From daf6b57dd736ec93b2e1769b90514b015feed3c1 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 11 Jul 2017 13:48:17 -0400 Subject: drm/amd/display: add line number to reg_wait timeout print Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 8ed1440d2b01..87b7f6f8870e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -129,7 +129,7 @@ uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t generic_reg_wait(const struct dc_context *ctx, uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, - const char *func_name) + const char *func_name, int line) { uint32_t field_value; uint32_t reg_val; @@ -158,8 +158,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, return reg_val; } - dm_error("REG_WAIT timeout %dus * %d tries - %s\n", - delay_between_poll_us, time_out_num_tries, func_name); + dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", + delay_between_poll_us, time_out_num_tries, func_name, line); if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index fb61e333aefd..ea494a71a80b 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -194,7 +194,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx, unsigned int generic_reg_wait(const struct dc_context *ctx, uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, - const char *func_name); + const char *func_name, int line); /* These macros need to be used with soc15 registers in order to retrieve diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h index 1828d288c6bc..77eb72874e90 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -188,7 +188,7 @@ #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \ generic_reg_wait(CTX, \ REG(reg_name), FN(reg_name, field), val,\ - delay_between_poll_us, max_try, __func__) + delay_between_poll_us, max_try, __func__, __LINE__) /* macro to update (read, modify, write) register fields */ -- cgit v1.2.3-59-g8ed1b From 755d3bcfd44c16d344c7c6305ac6e7da19c27f5e Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Sun, 23 Jul 2017 14:17:09 -0400 Subject: drm/amd/display: Fix generic_reg_wait 1000ms case Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 87b7f6f8870e..f219bd2068e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -143,11 +143,10 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, for (i = 0; i <= time_out_num_tries; i++) { if (i) { - if (0 < delay_between_poll_us && delay_between_poll_us < 1000) - udelay(delay_between_poll_us); - - if (delay_between_poll_us > 1000) + if (delay_between_poll_us >= 1000) msleep(delay_between_poll_us/1000); + else if (delay_between_poll_us > 0) + udelay(delay_between_poll_us); } reg_val = dm_read_reg(ctx, addr); -- cgit v1.2.3-59-g8ed1b From 8a5d82451e297fc3864bb9ab0247b53c7ab8a022 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 3 Aug 2017 21:23:04 -0400 Subject: drm/amd/display: use some sensible time out 40s time out is not sensible. also make all udelay poll happen more frequently since CPU is busy anyways Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 6 ++++- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 11 +++++---- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 4 ++-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 27 ++++++++++++++-------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 +- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 18 +++++++-------- 6 files changed, 41 insertions(+), 27 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index f219bd2068e5..0d84b2a1ccfd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -135,6 +135,9 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, uint32_t reg_val; int i; + /* something is terribly wrong if time out is > 200ms. (5Hz) */ + ASSERT(delay_between_poll_us * time_out_num_tries <= 200000); + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { /* 35 seconds */ delay_between_poll_us = 35000; @@ -158,7 +161,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, } dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", - delay_between_poll_us, time_out_num_tries, func_name, line); + delay_between_poll_us, time_out_num_tries, + func_name, line); if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index b4fa78292ad2..0e9d914e1a8f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -195,8 +195,9 @@ static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level) BL_PWM_GRP1_REG_LOCK, 0); /* 5.4.4 Wait for pending bit to be cleared */ - REG_WAIT(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, - 0, 10, 1000); + REG_WAIT(BL_PWM_GRP1_REG_LOCK, + BL_PWM_GRP1_REG_UPDATE_PENDING, 0, + 1, 10000); } static void dmcu_set_backlight_level( @@ -224,7 +225,7 @@ static void dmcu_set_backlight_level( /* waitDMCUReadyForCmd */ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, - 0, 100, 800); + 0, 1, 80000); /* setDMCUParam_BL */ REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit); @@ -304,7 +305,7 @@ static bool dce_abm_set_level(struct abm *abm, uint32_t level) struct dce_abm *abm_dce = TO_DCE_ABM(abm); REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, - 100, 800); + 1, 80000); /* setDMCUParam_ABMLevel */ REG_UPDATE_2(MASTER_COMM_CMD_REG, @@ -322,7 +323,7 @@ static bool dce_abm_immediate_disable(struct abm *abm) struct dce_abm *abm_dce = TO_DCE_ABM(abm); REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, - 100, 800); + 1, 80000); /* setDMCUParam_ABMLevel */ REG_UPDATE_2(MASTER_COMM_CMD_REG, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index aaff946a6d0a..92902f011418 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -262,7 +262,7 @@ static void dce_psr_wait_loop( union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; /* waitDMCUReadyForCmd */ - REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; @@ -502,7 +502,7 @@ static void dcn10_psr_wait_loop( union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; /* waitDMCUReadyForCmd */ - REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9165dc80cd22..292dfef91c9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -264,28 +264,32 @@ static void dpp_pg_control( DOMAIN1_POWER_GATE, power_gate); REG_WAIT(DOMAIN1_PG_STATUS, - DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN1_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; case 1: /* DPP1 */ REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, power_gate); REG_WAIT(DOMAIN3_PG_STATUS, - DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN3_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; case 2: /* DPP2 */ REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, power_gate); REG_WAIT(DOMAIN5_PG_STATUS, - DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN5_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; case 3: /* DPP3 */ REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, power_gate); REG_WAIT(DOMAIN7_PG_STATUS, - DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN7_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; default: BREAK_TO_DEBUGGER(); @@ -612,28 +616,32 @@ static void hubp_pg_control( DOMAIN0_POWER_GATE, power_gate); REG_WAIT(DOMAIN0_PG_STATUS, - DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN0_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; case 1: /* DCHUBP1 */ REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, power_gate); REG_WAIT(DOMAIN2_PG_STATUS, - DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN2_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; case 2: /* DCHUBP2 */ REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, power_gate); REG_WAIT(DOMAIN4_PG_STATUS, - DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN4_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; case 3: /* DCHUBP3 */ REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, power_gate); REG_WAIT(DOMAIN6_PG_STATUS, - DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); + DOMAIN6_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; default: BREAK_TO_DEBUGGER(); @@ -1011,7 +1019,8 @@ static void reset_front_end( if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], - VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000); + VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, + 1, 100000); plane_atomic_disable(dc, fe_idx); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 036f161ab1c1..52f2f2dd9a43 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -72,7 +72,7 @@ static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); REG_WAIT(MPCC_STATUS[id], MPCC_IDLE, 1, - 1000, 1000); + 1, 100000); } static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index f4dce2806ae1..941e0125ff06 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -312,7 +312,7 @@ static void tgn10_blank_crtc(struct timing_generator *tg) */ REG_WAIT(OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, 1, - 20000, 200000); + 1, 100000); REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0); @@ -351,7 +351,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, 1, - 2000, 500); + 1, 1000); /* Enable clock */ REG_UPDATE_2(OTG_CLOCK_CONTROL, @@ -359,7 +359,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) OTG_CLOCK_GATE_DIS, 1); REG_WAIT(OTG_CLOCK_CONTROL, OTG_CLOCK_ON, 1, - 2000, 500); + 1, 1000); } else { REG_UPDATE_2(OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, 0, @@ -368,7 +368,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_CLOCK_CONTROL, OTG_CLOCK_ON, 0, - 2000, 500); + 1, 1000); REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, 0, @@ -377,7 +377,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, 0, - 2000, 500); + 1, 1000); } } @@ -429,7 +429,7 @@ static bool tgn10_disable_crtc(struct timing_generator *tg) /* CRTC disabled, so disable clock. */ REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, - 2000, 500); + 1, 100000); return true; } @@ -556,7 +556,7 @@ static void tgn10_unlock(struct timing_generator *tg) /* why are we waiting here? */ REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, 0, - 20000, 200000); + 1, 100000); } static void tgn10_get_position(struct timing_generator *tg, @@ -651,13 +651,13 @@ static void tgn10_wait_for_state(struct timing_generator *tg, case CRTC_STATE_VBLANK: REG_WAIT(OTG_STATUS, OTG_V_BLANK, 1, - 100, 100000); /* 1 vupdate at 10hz */ + 1, 100000); /* 1 vupdate at 10hz */ break; case CRTC_STATE_VACTIVE: REG_WAIT(OTG_STATUS, OTG_V_ACTIVE_DISP, 1, - 100, 100000); /* 1 vupdate at 10hz */ + 1, 100000); /* 1 vupdate at 10hz */ break; default: -- cgit v1.2.3-59-g8ed1b From bf93b448b80bf71c2003659b06487879153b8b9b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:29:47 -0500 Subject: drm/amdgpu: add license to files where it was missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These files were missing it before. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 22 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_helper.c | 22 ++++++++++++++++++++ .../drm/amd/display/dc/dce100/dce100_resource.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.h | 23 +++++++++++++++++++++ .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../display/dc/dce110/dce110_timing_generator_v.c | 23 +++++++++++++++++++++ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 22 ++++++++++++++++++++ .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 22 ++++++++++++++++++++ .../gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/powerplay/inc/smu72.h | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h | 24 +++++++++++++++++++++- 15 files changed, 254 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6c570d4e4516..f8edf5483f11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1,4 +1,6 @@ /* + * Copyright 2017 Advanced Micro Devices, Inc. + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index f337c316ec2c..06525f2c36c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _AMDGPU_TRACE_H_ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 6acee5426e4b..43c7a7fddb83 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_debug.c * diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b7422d3b71ef..928895809867 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 0d84b2a1ccfd..90e81f7ba919 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_helper.c * diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 90911258bdb3..3ea43e2a9450 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index de8fdf438f9b..2f366d66635d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ /* * dce100_resource.h * diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 61adb8174ce0..42df17f9aa8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 07d9303d5477..59b4cd329715 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "dm_services.h" /* include DCE11 register header files */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 3d33bcda7059..498b7f05c5ca 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * link_encoder.h * diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 3050afe8e8a9..b5db1692393c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * stream_encoder.h * diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c index 67fae834bc67..8de384bf9a8f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c @@ -1,4 +1,26 @@ -// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "pp_overdriver.h" #include diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h index 08cd70c75d8b..9ad1cefff79f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_H #define SMU72_H diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h index b2edbc0c3c4d..2aefbb85f620 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_DISCRETE_H #define SMU72_DISCRETE_H diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index 283a0dc25e84..07129e6c31a9 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_GPU_SCHED_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _GPU_SCHED_TRACE_H_ -- cgit v1.2.3-59-g8ed1b From 42cf181b59b8e3cc75485fa493bd0e812f44a74b Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 2 Nov 2017 14:55:14 -0400 Subject: drm/amd/display: add warning on long reg_wait Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc_helper.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 0d84b2a1ccfd..c584252669fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -156,8 +156,13 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, field_value = get_reg_field_value_ex(reg_val, mask, shift); - if (field_value == condition_value) + if (field_value == condition_value) { + if (i * delay_between_poll_us > 1000) + dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n", + delay_between_poll_us * i / 1000, + func_name, line); return reg_val; + } } dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", -- cgit v1.2.3-59-g8ed1b