From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/Makefile | 15 + .../drm/amd/display/dc/dce110/dce110_compressor.c | 859 +++++++++ .../drm/amd/display/dc/dce110/dce110_compressor.h | 78 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1978 ++++++++++++++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.h | 62 + drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c | 62 + drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 76 + .../drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 253 +++ .../drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 303 +++ .../drm/amd/display/dc/dce110/dce110_mem_input.c | 535 ++++++ .../drm/amd/display/dc/dce110/dce110_mem_input.h | 131 ++ .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 1081 +++++++++++ .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 94 + drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c | 77 + drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h | 149 ++ .../gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c | 363 ++++ .../drm/amd/display/dc/dce110/dce110_opp_csc_v.c | 738 ++++++++ .../amd/display/dc/dce110/dce110_opp_formatter.c | 627 +++++++ .../drm/amd/display/dc/dce110/dce110_opp_regamma.c | 537 ++++++ .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 551 ++++++ .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 63 + .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 56 + .../drm/amd/display/dc/dce110/dce110_resource.c | 1413 ++++++++++++++ .../drm/amd/display/dc/dce110/dce110_resource.h | 56 + .../display/dc/dce110/dce110_timing_generator.c | 1953 +++++++++++++++++++ .../display/dc/dce110/dce110_timing_generator.h | 273 +++ .../display/dc/dce110/dce110_timing_generator_v.c | 743 ++++++++ .../display/dc/dce110/dce110_timing_generator_v.h | 33 + .../drm/amd/display/dc/dce110/dce110_transform_v.c | 704 +++++++ .../drm/amd/display/dc/dce110/dce110_transform_v.h | 37 + .../gpu/drm/amd/display/dc/dce110/dce110_types.h | 30 + 31 files changed, 13930 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/Makefile create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile new file mode 100644 index 000000000000..cd7a9095fa06 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the 'controller' sub-component of DAL. +# It provides the control and status of HW CRTC block. + +DCE110 = dce110_ipp.o dce110_ipp_cursor.o \ +dce110_ipp_gamma.o dce110_opp.o dce110_opp_csc.o \ +dce110_timing_generator.o dce110_opp_formatter.o dce110_opp_regamma.o \ +dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \ +dce110_resource.o \ +dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \ +dce110_mem_input_v.o dce110_opp_v.o dce110_transform_v.o + +AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCE110) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c new file mode 100644 index 000000000000..518150a414e2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -0,0 +1,859 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" +#include "gmc/gmc_8_2_sh_mask.h" +#include "gmc/gmc_8_2_d.h" + +#include "include/logger_interface.h" + +#include "dce110_compressor.h" + +#define DCP_REG(reg)\ + (reg + cp110->offsets.dcp_offset) +#define DMIF_REG(reg)\ + (reg + cp110->offsets.dmif_offset) + +static const struct dce110_compressor_reg_offsets reg_offsets[] = { +{ + .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), + .dmif_offset = + (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL + - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), +}, +{ + .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), + .dmif_offset = + (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL + - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), +}, +{ + .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), + .dmif_offset = + (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL + - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), +} +}; + +static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600; + +enum fbc_idle_force { + /* Bit 0 - Display registers updated */ + FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001, + + /* Bit 2 - FBC_GRPH_COMP_EN register updated */ + FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002, + /* Bit 3 - FBC_SRC_SEL register updated */ + FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004, + /* Bit 4 - FBC_MIN_COMPRESSION register updated */ + FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008, + /* Bit 5 - FBC_ALPHA_COMP_EN register updated */ + FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010, + /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */ + FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020, + /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */ + FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040, + + /* Bit 24 - Memory write to region 0 defined by MC registers. */ + FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000, + /* Bit 25 - Memory write to region 1 defined by MC registers */ + FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000, + /* Bit 26 - Memory write to region 2 defined by MC registers */ + FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000, + /* Bit 27 - Memory write to region 3 defined by MC registers. */ + FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000, + + /* Bit 28 - Memory write from any client other than MCIF */ + FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000, + /* Bit 29 - CG statics screen signal is inactive */ + FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000, +}; + +static uint32_t lpt_size_alignment(struct dce110_compressor *cp110) +{ + /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */ + return cp110->base.raw_size * cp110->base.banks_num * + cp110->base.dram_channels_num; +} + +static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110, + uint32_t lpt_control) +{ + /*LPT MC Config */ + if (cp110->base.options.bits.LPT_MC_CONFIG == 1) { + /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS): + * 00 - 1 CHANNEL + * 01 - 2 CHANNELS + * 02 - 4 OR 6 CHANNELS + * (Only for discrete GPU, N/A for CZ) + * 03 - 8 OR 12 CHANNELS + * (Only for discrete GPU, N/A for CZ) */ + switch (cp110->base.dram_channels_num) { + case 2: + set_reg_field_value( + lpt_control, + 1, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_NUM_PIPES); + break; + case 1: + set_reg_field_value( + lpt_control, + 0, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_NUM_PIPES); + break; + default: + dm_logger_write( + cp110->base.ctx->logger, LOG_WARNING, + "%s: Invalid LPT NUM_PIPES!!!", + __func__); + break; + } + + /* The mapping for LPT NUM_BANKS is in + * GRPH_CONTROL.GRPH_NUM_BANKS register field + * Specifies the number of memory banks for tiling + * purposes. Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: + * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK + * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK + * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK + * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */ + switch (cp110->base.banks_num) { + case 16: + set_reg_field_value( + lpt_control, + 3, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_NUM_BANKS); + break; + case 8: + set_reg_field_value( + lpt_control, + 2, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_NUM_BANKS); + break; + case 4: + set_reg_field_value( + lpt_control, + 1, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_NUM_BANKS); + break; + case 2: + set_reg_field_value( + lpt_control, + 0, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_NUM_BANKS); + break; + default: + dm_logger_write( + cp110->base.ctx->logger, LOG_WARNING, + "%s: Invalid LPT NUM_BANKS!!!", + __func__); + break; + } + + /* The mapping is in DMIF_ADDR_CALC. + * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for + * Carrizo specifies the memory interleave per pipe. + * It effectively specifies the location of pipe bits in + * the memory address. + * POSSIBLE VALUES: + * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte + * interleave + * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte + * interleave + */ + switch (cp110->base.channel_interleave_size) { + case 256: /*256B */ + set_reg_field_value( + lpt_control, + 0, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); + break; + case 512: /*512B */ + set_reg_field_value( + lpt_control, + 1, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); + break; + default: + dm_logger_write( + cp110->base.ctx->logger, LOG_WARNING, + "%s: Invalid LPT INTERLEAVE_SIZE!!!", + __func__); + break; + } + + /* The mapping for LOW_POWER_TILING_ROW_SIZE is in + * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field + * for Carrizo. Specifies the size of dram row in bytes. + * This should match up with NOOFCOLS field in + * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns). + * This register DMIF_ADDR_CALC is not used by the + * hardware as it is only used for addrlib assertions. + * POSSIBLE VALUES: + * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row + * boundary + * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row + * boundary + * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row + * boundary */ + switch (cp110->base.raw_size) { + case 4096: /*4 KB */ + set_reg_field_value( + lpt_control, + 2, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ROW_SIZE); + break; + case 2048: + set_reg_field_value( + lpt_control, + 1, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ROW_SIZE); + break; + case 1024: + set_reg_field_value( + lpt_control, + 0, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ROW_SIZE); + break; + default: + dm_logger_write( + cp110->base.ctx->logger, LOG_WARNING, + "%s: Invalid LPT ROW_SIZE!!!", + __func__); + break; + } + } else { + dm_logger_write( + cp110->base.ctx->logger, LOG_WARNING, + "%s: LPT MC Configuration is not provided", + __func__); + } + + return lpt_control; +} + +static bool is_source_bigger_than_epanel_size( + struct dce110_compressor *cp110, + uint32_t source_view_width, + uint32_t source_view_height) +{ + if (cp110->base.embedded_panel_h_size != 0 && + cp110->base.embedded_panel_v_size != 0 && + ((source_view_width * source_view_height) > + (cp110->base.embedded_panel_h_size * + cp110->base.embedded_panel_v_size))) + return true; + + return false; +} + +static uint32_t align_to_chunks_number_per_line( + struct dce110_compressor *cp110, + uint32_t pixels) +{ + return 256 * ((pixels + 255) / 256); +} + +static void wait_for_fbc_state_changed( + struct dce110_compressor *cp110, + bool enabled) +{ + uint8_t counter = 0; + uint32_t addr = mmFBC_STATUS; + uint32_t value; + + while (counter < 10) { + value = dm_read_reg(cp110->base.ctx, addr); + if (get_reg_field_value( + value, + FBC_STATUS, + FBC_ENABLE_STATUS) == enabled) + break; + udelay(10); + counter++; + } + + if (counter == 10) { + dm_logger_write( + cp110->base.ctx->logger, LOG_WARNING, + "%s: wait counter exceeded, changes to HW not applied", + __func__); + } +} + +void dce110_compressor_power_up_fbc(struct compressor *compressor) +{ + uint32_t value; + uint32_t addr; + + addr = mmFBC_CNTL; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); + set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); + set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE); + if (compressor->options.bits.CLK_GATING_DISABLED == 1) { + /* HW needs to do power measurement comparison. */ + set_reg_field_value( + value, + 0, + FBC_CNTL, + FBC_COMP_CLK_GATE_EN); + } + dm_write_reg(compressor->ctx, addr, value); + + addr = mmFBC_COMP_MODE; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); + set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN); + set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN); + dm_write_reg(compressor->ctx, addr, value); + + addr = mmFBC_COMP_CNTL; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN); + dm_write_reg(compressor->ctx, addr, value); + /*FBC_MIN_COMPRESSION 0 ==> 2:1 */ + /* 1 ==> 4:1 */ + /* 2 ==> 8:1 */ + /* 0xF ==> 1:1 */ + set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION); + dm_write_reg(compressor->ctx, addr, value); + compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1; + + value = 0; + dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); + + value = 0xFFFFFF; + dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); +} + +void dce110_compressor_enable_fbc( + struct compressor *compressor, + uint32_t paths_num, + struct compr_addr_and_pitch_params *params) +{ + struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); + + if (compressor->options.bits.FBC_SUPPORT && + (compressor->options.bits.DUMMY_BACKEND == 0) && + (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) && + (!is_source_bigger_than_epanel_size( + cp110, + params->source_view_width, + params->source_view_height))) { + + uint32_t addr; + uint32_t value; + + /* Before enabling FBC first need to enable LPT if applicable + * LPT state should always be changed (enable/disable) while FBC + * is disabled */ + if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) && + (params->source_view_width * + params->source_view_height <= + dce11_one_lpt_channel_max_resolution)) { + dce110_compressor_enable_lpt(compressor); + } + + addr = mmFBC_CNTL; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); + set_reg_field_value( + value, + params->inst, + FBC_CNTL, FBC_SRC_SEL); + dm_write_reg(compressor->ctx, addr, value); + + /* Keep track of enum controller_id FBC is attached to */ + compressor->is_enabled = true; + compressor->attached_inst = params->inst; + cp110->offsets = reg_offsets[params->inst - 1]; + + /*Toggle it as there is bug in HW */ + set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); + dm_write_reg(compressor->ctx, addr, value); + set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); + dm_write_reg(compressor->ctx, addr, value); + + wait_for_fbc_state_changed(cp110, true); + } +} + +void dce110_compressor_disable_fbc(struct compressor *compressor) +{ + struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); + + if (compressor->options.bits.FBC_SUPPORT && + dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) { + uint32_t reg_data; + /* Turn off compression */ + reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); + set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); + dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); + + /* Reset enum controller_id to undefined */ + compressor->attached_inst = 0; + compressor->is_enabled = false; + + /* Whenever disabling FBC make sure LPT is disabled if LPT + * supported */ + if (compressor->options.bits.LPT_SUPPORT) + dce110_compressor_disable_lpt(compressor); + + wait_for_fbc_state_changed(cp110, false); + } +} + +bool dce110_compressor_is_fbc_enabled_in_hw( + struct compressor *compressor, + uint32_t *inst) +{ + /* Check the hardware register */ + uint32_t value; + + value = dm_read_reg(compressor->ctx, mmFBC_STATUS); + if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) { + if (inst != NULL) + *inst = compressor->attached_inst; + return true; + } + + value = dm_read_reg(compressor->ctx, mmFBC_MISC); + if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) { + value = dm_read_reg(compressor->ctx, mmFBC_CNTL); + + if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) { + if (inst != NULL) + *inst = + compressor->attached_inst; + return true; + } + } + return false; +} + +bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *compressor) +{ + /* Check the hardware register */ + uint32_t value = dm_read_reg(compressor->ctx, + mmLOW_POWER_TILING_CONTROL); + + return get_reg_field_value( + value, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ENABLE); +} + +void dce110_compressor_program_compressed_surface_address_and_pitch( + struct compressor *compressor, + struct compr_addr_and_pitch_params *params) +{ + struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); + uint32_t value = 0; + uint32_t fbc_pitch = 0; + uint32_t compressed_surf_address_low_part = + compressor->compr_surface_address.addr.low_part; + + /* Clear content first. */ + dm_write_reg( + compressor->ctx, + DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), + 0); + dm_write_reg(compressor->ctx, + DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0); + + if (compressor->options.bits.LPT_SUPPORT) { + uint32_t lpt_alignment = lpt_size_alignment(cp110); + + if (lpt_alignment != 0) { + compressed_surf_address_low_part = + ((compressed_surf_address_low_part + + (lpt_alignment - 1)) / lpt_alignment) + * lpt_alignment; + } + } + + /* Write address, HIGH has to be first. */ + dm_write_reg(compressor->ctx, + DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), + compressor->compr_surface_address.addr.high_part); + dm_write_reg(compressor->ctx, + DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), + compressed_surf_address_low_part); + + fbc_pitch = align_to_chunks_number_per_line( + cp110, + params->source_view_width); + + if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) + fbc_pitch = fbc_pitch / 8; + else + dm_logger_write( + compressor->ctx->logger, LOG_WARNING, + "%s: Unexpected DCE11 compression ratio", + __func__); + + /* Clear content first. */ + dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0); + + /* Write FBC Pitch. */ + set_reg_field_value( + value, + fbc_pitch, + GRPH_COMPRESS_PITCH, + GRPH_COMPRESS_PITCH); + dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value); + +} + +void dce110_compressor_disable_lpt(struct compressor *compressor) +{ + struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); + uint32_t value; + uint32_t addr; + uint32_t inx; + + /* Disable all pipes LPT Stutter */ + for (inx = 0; inx < 3; inx++) { + value = + dm_read_reg( + compressor->ctx, + DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); + set_reg_field_value( + value, + 0, + DPG_PIPE_STUTTER_CONTROL_NONLPTCH, + STUTTER_ENABLE_NONLPTCH); + dm_write_reg( + compressor->ctx, + DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), + value); + } + /* Disable Underlay pipe LPT Stutter */ + addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + 0, + DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, + STUTTER_ENABLE_NONLPTCH); + dm_write_reg(compressor->ctx, addr, value); + + /* Disable LPT */ + addr = mmLOW_POWER_TILING_CONTROL; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + 0, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ENABLE); + dm_write_reg(compressor->ctx, addr, value); + + /* Clear selection of Channel(s) containing Compressed Surface */ + addr = mmGMCON_LPT_TARGET; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + 0xFFFFFFFF, + GMCON_LPT_TARGET, + STCTRL_LPT_TARGET); + dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value); +} + +void dce110_compressor_enable_lpt(struct compressor *compressor) +{ + struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); + uint32_t value; + uint32_t addr; + uint32_t value_control; + uint32_t channels; + + /* Enable LPT Stutter from Display pipe */ + value = dm_read_reg(compressor->ctx, + DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); + set_reg_field_value( + value, + 1, + DPG_PIPE_STUTTER_CONTROL_NONLPTCH, + STUTTER_ENABLE_NONLPTCH); + dm_write_reg(compressor->ctx, + DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value); + + /* Enable Underlay pipe LPT Stutter */ + addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + 1, + DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, + STUTTER_ENABLE_NONLPTCH); + dm_write_reg(compressor->ctx, addr, value); + + /* Selection of Channel(s) containing Compressed Surface: 0xfffffff + * will disable LPT. + * STCTRL_LPT_TARGETn corresponds to channel n. */ + addr = mmLOW_POWER_TILING_CONTROL; + value_control = dm_read_reg(compressor->ctx, addr); + channels = get_reg_field_value(value_control, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_MODE); + + addr = mmGMCON_LPT_TARGET; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + channels + 1, /* not mentioned in programming guide, + but follow DCE8.1 */ + GMCON_LPT_TARGET, + STCTRL_LPT_TARGET); + dm_write_reg(compressor->ctx, addr, value); + + /* Enable LPT */ + addr = mmLOW_POWER_TILING_CONTROL; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + 1, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ENABLE); + dm_write_reg(compressor->ctx, addr, value); +} + +void dce110_compressor_program_lpt_control( + struct compressor *compressor, + struct compr_addr_and_pitch_params *params) +{ + struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); + uint32_t rows_per_channel; + uint32_t lpt_alignment; + uint32_t source_view_width; + uint32_t source_view_height; + uint32_t lpt_control = 0; + + if (!compressor->options.bits.LPT_SUPPORT) + return; + + lpt_control = dm_read_reg(compressor->ctx, + mmLOW_POWER_TILING_CONTROL); + + /* POSSIBLE VALUES for Low Power Tiling Mode: + * 00 - Use channel 0 + * 01 - Use Channel 0 and 1 + * 02 - Use Channel 0,1,2,3 + * 03 - reserved */ + switch (compressor->lpt_channels_num) { + /* case 2: + * Use Channel 0 & 1 / Not used for DCE 11 */ + case 1: + /*Use Channel 0 for LPT for DCE 11 */ + set_reg_field_value( + lpt_control, + 0, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_MODE); + break; + default: + dm_logger_write( + compressor->ctx->logger, LOG_WARNING, + "%s: Invalid selected DRAM channels for LPT!!!", + __func__); + break; + } + + lpt_control = lpt_memory_control_config(cp110, lpt_control); + + /* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on + * FBC compressed surface pitch. + * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height * + * Surface Pitch) / (Row Size * Number of Channels * + * Number of Banks)). */ + rows_per_channel = 0; + lpt_alignment = lpt_size_alignment(cp110); + source_view_width = + align_to_chunks_number_per_line( + cp110, + params->source_view_width); + source_view_height = (params->source_view_height + 1) & (~0x1); + + if (lpt_alignment != 0) { + rows_per_channel = source_view_width * source_view_height * 4; + rows_per_channel = + (rows_per_channel % lpt_alignment) ? + (rows_per_channel / lpt_alignment + 1) : + rows_per_channel / lpt_alignment; + } + + set_reg_field_value( + lpt_control, + rows_per_channel, + LOW_POWER_TILING_CONTROL, + LOW_POWER_TILING_ROWS_PER_CHAN); + + dm_write_reg(compressor->ctx, + mmLOW_POWER_TILING_CONTROL, lpt_control); +} + +/* + * DCE 11 Frame Buffer Compression Implementation + */ + +void dce110_compressor_set_fbc_invalidation_triggers( + struct compressor *compressor, + uint32_t fbc_trigger) +{ + /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19) + * for DCE 11 regions cannot be used - does not work with S/G + */ + uint32_t addr = mmFBC_CLIENT_REGION_MASK; + uint32_t value = dm_read_reg(compressor->ctx, addr); + + set_reg_field_value( + value, + 0, + FBC_CLIENT_REGION_MASK, + FBC_MEMORY_REGION_MASK); + dm_write_reg(compressor->ctx, addr, value); + + /* Setup events when to clear all CSM entries (effectively marking + * current compressed data invalid) + * For DCE 11 CSM metadata 11111 means - "Not Compressed" + * Used as the initial value of the metadata sent to the compressor + * after invalidation, to indicate that the compressor should attempt + * to compress all chunks on the current pass. Also used when the chunk + * is not successfully written to memory. + * When this CSM value is detected, FBC reads from the uncompressed + * buffer. Set events according to passed in value, these events are + * valid for DCE11: + * - bit 0 - display register updated + * - bit 28 - memory write from any client except from MCIF + * - bit 29 - CG static screen signal is inactive + * In addition, DCE11.1 also needs to set new DCE11.1 specific events + * that are used to trigger invalidation on certain register changes, + * for example enabling of Alpha Compression may trigger invalidation of + * FBC once bit is set. These events are as follows: + * - Bit 2 - FBC_GRPH_COMP_EN register updated + * - Bit 3 - FBC_SRC_SEL register updated + * - Bit 4 - FBC_MIN_COMPRESSION register updated + * - Bit 5 - FBC_ALPHA_COMP_EN register updated + * - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated + * - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated + */ + addr = mmFBC_IDLE_FORCE_CLEAR_MASK; + value = dm_read_reg(compressor->ctx, addr); + set_reg_field_value( + value, + fbc_trigger | + FBC_IDLE_FORCE_GRPH_COMP_EN | + FBC_IDLE_FORCE_SRC_SEL_CHANGE | + FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE | + FBC_IDLE_FORCE_ALPHA_COMP_EN | + FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN | + FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF, + FBC_IDLE_FORCE_CLEAR_MASK, + FBC_IDLE_FORCE_CLEAR_MASK); + dm_write_reg(compressor->ctx, addr, value); +} + +bool dce110_compressor_construct(struct dce110_compressor *compressor, + struct dc_context *ctx) +{ + struct dc_bios *bp = ctx->dc_bios; + struct embedded_panel_info panel_info; + + compressor->base.options.bits.FBC_SUPPORT = true; + compressor->base.options.bits.LPT_SUPPORT = true; + /* For DCE 11 always use one DRAM channel for LPT */ + compressor->base.lpt_channels_num = 1; + compressor->base.options.bits.DUMMY_BACKEND = false; + + /* Check if this system has more than 1 DRAM channel; if only 1 then LPT + * should not be supported */ + if (compressor->base.memory_bus_width == 64) + compressor->base.options.bits.LPT_SUPPORT = false; + + compressor->base.options.bits.CLK_GATING_DISABLED = false; + + compressor->base.ctx = ctx; + compressor->base.embedded_panel_h_size = 0; + compressor->base.embedded_panel_v_size = 0; + compressor->base.memory_bus_width = ctx->asic_id.vram_width; + compressor->base.allocated_size = 0; + compressor->base.preferred_requested_size = 0; + compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; + compressor->base.options.raw = 0; + compressor->base.banks_num = 0; + compressor->base.raw_size = 0; + compressor->base.channel_interleave_size = 0; + compressor->base.dram_channels_num = 0; + compressor->base.lpt_channels_num = 0; + compressor->base.attached_inst = 0; + compressor->base.is_enabled = false; + + if (BP_RESULT_OK == + bp->funcs->get_embedded_panel_info(bp, &panel_info)) { + compressor->base.embedded_panel_h_size = + panel_info.lcd_timing.horizontal_addressable; + compressor->base.embedded_panel_v_size = + panel_info.lcd_timing.vertical_addressable; + } + return true; +} + +struct compressor *dce110_compressor_create(struct dc_context *ctx) +{ + struct dce110_compressor *cp110 = + dm_alloc(sizeof(struct dce110_compressor)); + + if (!cp110) + return NULL; + + if (dce110_compressor_construct(cp110, ctx)) + return &cp110->base; + + BREAK_TO_DEBUGGER(); + dm_free(cp110); + return NULL; +} + +void dce110_compressor_destroy(struct compressor **compressor) +{ + dm_free(TO_DCE110_COMPRESSOR(*compressor)); + *compressor = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h new file mode 100644 index 000000000000..22af5be51581 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h @@ -0,0 +1,78 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_COMPRESSOR_DCE110_H__ +#define __DC_COMPRESSOR_DCE110_H__ + +#include "../inc/compressor.h" + +#define TO_DCE110_COMPRESSOR(compressor)\ + container_of(compressor, struct dce110_compressor, base) + +struct dce110_compressor_reg_offsets { + uint32_t dcp_offset; + uint32_t dmif_offset; +}; + +struct dce110_compressor { + struct compressor base; + struct dce110_compressor_reg_offsets offsets; +}; + +struct compressor *dce110_compressor_create(struct dc_context *ctx); + +bool dce110_compressor_construct(struct dce110_compressor *cp110, + struct dc_context *ctx); + +void dce110_compressor_destroy(struct compressor **cp); + +/* FBC RELATED */ +void dce110_compressor_power_up_fbc(struct compressor *cp); + +void dce110_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num, + struct compr_addr_and_pitch_params *params); + +void dce110_compressor_disable_fbc(struct compressor *cp); + +void dce110_compressor_set_fbc_invalidation_triggers(struct compressor *cp, + uint32_t fbc_trigger); + +void dce110_compressor_program_compressed_surface_address_and_pitch( + struct compressor *cp, + struct compr_addr_and_pitch_params *params); + +bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp, + uint32_t *fbc_mapped_crtc_id); + +/* LPT RELATED */ +void dce110_compressor_enable_lpt(struct compressor *cp); + +void dce110_compressor_disable_lpt(struct compressor *cp); + +void dce110_compressor_program_lpt_control(struct compressor *cp, + struct compr_addr_and_pitch_params *params); + +bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c new file mode 100644 index 000000000000..1a682996b531 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -0,0 +1,1978 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "dm_services.h" +#include "dc.h" +#include "dc_bios_types.h" +#include "core_types.h" +#include "core_status.h" +#include "resource.h" +#include "hw_sequencer.h" +#include "dm_helpers.h" +#include "dce110_hw_sequencer.h" +#include "dce110_timing_generator.h" + +#include "bios/bios_parser_helper.h" +#include "timing_generator.h" +#include "mem_input.h" +#include "opp.h" +#include "ipp.h" +#include "transform.h" +#include "stream_encoder.h" +#include "link_encoder.h" +#include "clock_source.h" +#include "gamma_calcs.h" +#include "audio.h" +#include "dce/dce_hwseq.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +struct dce110_hw_seq_reg_offsets { + uint32_t crtc; +}; + +static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { +{ + .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), +}, +{ + .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), +}, +{ + .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), +}, +{ + .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), +} +}; + +#define HW_REG_BLND(reg, id)\ + (reg + reg_offsets[id].blnd) + +#define HW_REG_CRTC(reg, id)\ + (reg + reg_offsets[id].crtc) + +#define MAX_WATERMARK 0xFFFF +#define SAFE_NBP_MARK 0x7FFF + +/******************************************************************************* + * Private definitions + ******************************************************************************/ +/***************************PIPE_CONTROL***********************************/ +static void dce110_init_pte(struct dc_context *ctx) +{ + uint32_t addr; + uint32_t value = 0; + uint32_t chunk_int = 0; + uint32_t chunk_mul = 0; + + addr = mmUNP_DVMM_PTE_CONTROL; + value = dm_read_reg(ctx, addr); + + set_reg_field_value( + value, + 0, + DVMM_PTE_CONTROL, + DVMM_USE_SINGLE_PTE); + + set_reg_field_value( + value, + 1, + DVMM_PTE_CONTROL, + DVMM_PTE_BUFFER_MODE0); + + set_reg_field_value( + value, + 1, + DVMM_PTE_CONTROL, + DVMM_PTE_BUFFER_MODE1); + + dm_write_reg(ctx, addr, value); + + addr = mmDVMM_PTE_REQ; + value = dm_read_reg(ctx, addr); + + chunk_int = get_reg_field_value( + value, + DVMM_PTE_REQ, + HFLIP_PTEREQ_PER_CHUNK_INT); + + chunk_mul = get_reg_field_value( + value, + DVMM_PTE_REQ, + HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); + + if (chunk_int != 0x4 || chunk_mul != 0x4) { + + set_reg_field_value( + value, + 255, + DVMM_PTE_REQ, + MAX_PTEREQ_TO_ISSUE); + + set_reg_field_value( + value, + 4, + DVMM_PTE_REQ, + HFLIP_PTEREQ_PER_CHUNK_INT); + + set_reg_field_value( + value, + 4, + DVMM_PTE_REQ, + HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); + + dm_write_reg(ctx, addr, value); + } +} +/**************************************************************************/ + +static void enable_display_pipe_clock_gating( + struct dc_context *ctx, + bool clock_gating) +{ + /*TODO*/ +} + +static bool dce110_enable_display_power_gating( + struct core_dc *dc, + uint8_t controller_id, + struct dc_bios *dcb, + enum pipe_gating_control power_gating) +{ + enum bp_result bp_result = BP_RESULT_OK; + enum bp_pipe_control_action cntl; + struct dc_context *ctx = dc->ctx; + unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; + + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) + return true; + + if (power_gating == PIPE_GATING_CONTROL_INIT) + cntl = ASIC_PIPE_INIT; + else if (power_gating == PIPE_GATING_CONTROL_ENABLE) + cntl = ASIC_PIPE_ENABLE; + else + cntl = ASIC_PIPE_DISABLE; + + if (controller_id == underlay_idx) + controller_id = CONTROLLER_ID_UNDERLAY0 - 1; + + if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ + + bp_result = dcb->funcs->enable_disp_power_gating( + dcb, controller_id + 1, cntl); + + /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 + * by default when command table is called + * + * Bios parser accepts controller_id = 6 as indicative of + * underlay pipe in dce110. But we do not support more + * than 3. + */ + if (controller_id < CONTROLLER_ID_MAX - 1) + dm_write_reg(ctx, + HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), + 0); + } + + if (power_gating != PIPE_GATING_CONTROL_ENABLE) + dce110_init_pte(ctx); + + if (bp_result == BP_RESULT_OK) + return true; + else + return false; +} + +static void build_prescale_params(struct ipp_prescale_params *prescale_params, + const struct core_surface *surface) +{ + prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; + + switch (surface->public.format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + prescale_params->scale = 0x2020; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + prescale_params->scale = 0x2008; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + prescale_params->scale = 0x2000; + break; + default: + ASSERT(false); + } +} + +static bool set_gamma_ramp( + struct input_pixel_processor *ipp, + struct output_pixel_processor *opp, + const struct core_gamma *ramp, + const struct core_surface *surface) +{ + struct ipp_prescale_params prescale_params = { 0 }; + struct pwl_params *regamma_params; + bool result = false; + + regamma_params = dm_alloc(sizeof(struct pwl_params)); + if (regamma_params == NULL) + goto regamma_alloc_fail; + + regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; + + opp->funcs->opp_power_on_regamma_lut(opp, true); + + if (ipp) { + build_prescale_params(&prescale_params, surface); + ipp->funcs->ipp_program_prescale(ipp, &prescale_params); + } + + if (ramp && calculate_regamma_params(regamma_params, ramp, surface)) { + + opp->funcs->opp_program_regamma_pwl(opp, regamma_params); + if (ipp) + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); + opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); + } else { + if (ipp) + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); + opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); + } + + opp->funcs->opp_power_on_regamma_lut(opp, false); + + result = true; + + dm_free(regamma_params); + +regamma_alloc_fail: + return result; +} + +static enum dc_status bios_parser_crtc_source_select( + struct pipe_ctx *pipe_ctx) +{ + struct dc_bios *dcb; + /* call VBIOS table to set CRTC source for the HW + * encoder block + * note: video bios clears all FMT setting here. */ + struct bp_crtc_source_select crtc_source_select = {0}; + const struct core_sink *sink = pipe_ctx->stream->sink; + + crtc_source_select.engine_id = pipe_ctx->stream_enc->id; + crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; + /*TODO: Need to un-hardcode color depth, dp_audio and account for + * the case where signal and sink signal is different (translator + * encoder)*/ + crtc_source_select.signal = pipe_ctx->stream->signal; + crtc_source_select.enable_dp_audio = false; + crtc_source_select.sink_signal = pipe_ctx->stream->signal; + crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; + + dcb = sink->ctx->dc_bios; + + if (BP_RESULT_OK != dcb->funcs->crtc_source_select( + dcb, + &crtc_source_select)) { + return DC_ERROR_UNEXPECTED; + } + + return DC_OK; +} + +void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) +{ + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( + pipe_ctx->stream_enc, + &pipe_ctx->encoder_info_frame); + else if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->update_dp_info_packets( + pipe_ctx->stream_enc, + &pipe_ctx->encoder_info_frame); +} + +void dce110_enable_stream(struct pipe_ctx *pipe_ctx) +{ + enum dc_lane_count lane_count = + pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; + + struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct core_link *link = pipe_ctx->stream->sink->link; + + /* 1. update AVI info frame (HDMI, DP) + * we always need to update info frame + */ + uint32_t active_total_with_borders; + uint32_t early_control = 0; + struct timing_generator *tg = pipe_ctx->tg; + + /* TODOFPGA may change to hwss.update_info_frame */ + dce110_update_info_frame(pipe_ctx); + /* enable early control to avoid corruption on DP monitor*/ + active_total_with_borders = + timing->h_addressable + + timing->h_border_left + + timing->h_border_right; + + if (lane_count != 0) + early_control = active_total_with_borders % lane_count; + + if (early_control == 0) + early_control = lane_count; + + tg->funcs->set_early_control(tg, early_control); + + /* enable audio only within mode set */ + if (pipe_ctx->audio != NULL) { + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); + } + + /* For MST, there are multiply stream go to only one link. + * connect DIG back_end to front_end while enable_stream and + * disconnect them during disable_stream + * BY this, it is logic clean to separate stream and link */ + link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, + pipe_ctx->stream_enc->id, true); + +} + +void dce110_disable_stream(struct pipe_ctx *pipe_ctx) +{ + struct core_stream *stream = pipe_ctx->stream; + struct core_link *link = stream->sink->link; + + if (pipe_ctx->audio) { + pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->dp_audio_disable( + pipe_ctx->stream_enc); + else + pipe_ctx->stream_enc->funcs->hdmi_audio_disable( + pipe_ctx->stream_enc); + + pipe_ctx->audio = NULL; + + /* TODO: notify audio driver for if audio modes list changed + * add audio mode list change flag */ + /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, + * stream->stream_engine_id); + */ + } + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( + pipe_ctx->stream_enc); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->stop_dp_info_packets( + pipe_ctx->stream_enc); + + pipe_ctx->stream_enc->funcs->audio_mute_control( + pipe_ctx->stream_enc, true); + + + /* blank at encoder level */ + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); + + link->link_enc->funcs->connect_dig_be_to_fe( + link->link_enc, + pipe_ctx->stream_enc->id, + false); + +} + +void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + struct dc_link_settings *link_settings) +{ + struct encoder_unblank_param params = { { 0 } }; + + /* only 3 items below are used by unblank */ + params.crtc_timing.pixel_clock = + pipe_ctx->stream->public.timing.pix_clk_khz; + params.link_settings.link_rate = link_settings->link_rate; + pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); +} + +static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) +{ + switch (crtc_id) { + case CONTROLLER_ID_D0: + return DTO_SOURCE_ID0; + case CONTROLLER_ID_D1: + return DTO_SOURCE_ID1; + case CONTROLLER_ID_D2: + return DTO_SOURCE_ID2; + case CONTROLLER_ID_D3: + return DTO_SOURCE_ID3; + case CONTROLLER_ID_D4: + return DTO_SOURCE_ID4; + case CONTROLLER_ID_D5: + return DTO_SOURCE_ID5; + default: + return DTO_SOURCE_UNKNOWN; + } +} + +static void build_audio_output( + const struct pipe_ctx *pipe_ctx, + struct audio_output *audio_output) +{ + const struct core_stream *stream = pipe_ctx->stream; + audio_output->engine_id = pipe_ctx->stream_enc->id; + + audio_output->signal = pipe_ctx->stream->signal; + + /* audio_crtc_info */ + + audio_output->crtc_info.h_total = + stream->public.timing.h_total; + + /* + * Audio packets are sent during actual CRTC blank physical signal, we + * need to specify actual active signal portion + */ + audio_output->crtc_info.h_active = + stream->public.timing.h_addressable + + stream->public.timing.h_border_left + + stream->public.timing.h_border_right; + + audio_output->crtc_info.v_active = + stream->public.timing.v_addressable + + stream->public.timing.v_border_top + + stream->public.timing.v_border_bottom; + + audio_output->crtc_info.pixel_repetition = 1; + + audio_output->crtc_info.interlaced = + stream->public.timing.flags.INTERLACE; + + audio_output->crtc_info.refresh_rate = + (stream->public.timing.pix_clk_khz*1000)/ + (stream->public.timing.h_total*stream->public.timing.v_total); + + audio_output->crtc_info.color_depth = + stream->public.timing.display_color_depth; + + audio_output->crtc_info.requested_pixel_clock = + pipe_ctx->pix_clk_params.requested_pix_clk; + + /* + * TODO - Investigate why calculated pixel clk has to be + * requested pixel clk + */ + audio_output->crtc_info.calculated_pixel_clock = + pipe_ctx->pix_clk_params.requested_pix_clk; + + if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || + pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { + audio_output->pll_info.dp_dto_source_clock_in_khz = + dal_display_clock_get_dp_ref_clk_frequency( + pipe_ctx->dis_clk); + } + + audio_output->pll_info.feed_back_divider = + pipe_ctx->pll_settings.feedback_divider; + + audio_output->pll_info.dto_source = + translate_to_dto_source( + pipe_ctx->pipe_idx + 1); + + /* TODO hard code to enable for now. Need get from stream */ + audio_output->pll_info.ss_enabled = true; + + audio_output->pll_info.ss_percentage = + pipe_ctx->pll_settings.ss_percentage; +} + +static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; + + switch (pipe_ctx->scl_data.format) { + case PIXEL_FORMAT_ARGB8888: + /* set boarder color to red */ + color->color_r_cr = color_value; + break; + + case PIXEL_FORMAT_ARGB2101010: + /* set boarder color to blue */ + color->color_b_cb = color_value; + break; + case PIXEL_FORMAT_420BPP12: + /* set boarder color to green */ + color->color_g_y = color_value; + break; + case PIXEL_FORMAT_FP16: + /* set boarder color to white */ + color->color_r_cr = color_value; + color->color_b_cb = color_value; + color->color_g_y = color_value; + break; + default: + break; + } +} + +static void program_scaler(const struct core_dc *dc, + const struct pipe_ctx *pipe_ctx) +{ + struct tg_color color = {0}; + + if (dc->public.debug.surface_visual_confirm) + get_surface_visual_confirm_color(pipe_ctx, &color); + else + color_space_to_black_color(dc, + pipe_ctx->stream->public.output_color_space, + &color); + + pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( + pipe_ctx->xfm, + pipe_ctx->scl_data.lb_params.depth, + &pipe_ctx->stream->bit_depth_params); + + if (pipe_ctx->tg->funcs->set_overscan_blank_color) + pipe_ctx->tg->funcs->set_overscan_blank_color( + pipe_ctx->tg, + &color); + + pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, + &pipe_ctx->scl_data); +} + +static enum dc_status prog_pixclk_crtc_otg( + struct pipe_ctx *pipe_ctx, + struct validate_context *context, + struct core_dc *dc) +{ + struct core_stream *stream = pipe_ctx->stream; + struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + pipe_ctx[pipe_ctx->pipe_idx]; + struct tg_color black_color = {0}; + + if (!pipe_ctx_old->stream) { + + /* program blank color */ + color_space_to_black_color(dc, + stream->public.output_color_space, &black_color); + pipe_ctx->tg->funcs->set_blank_color( + pipe_ctx->tg, + &black_color); + /* + * Must blank CRTC after disabling power gating and before any + * programming, otherwise CRTC will be hung in bad state + */ + pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); + + if (false == pipe_ctx->clock_source->funcs->program_pix_clk( + pipe_ctx->clock_source, + &pipe_ctx->pix_clk_params, + &pipe_ctx->pll_settings)) { + BREAK_TO_DEBUGGER(); + return DC_ERROR_UNEXPECTED; + } + + pipe_ctx->tg->funcs->program_timing( + pipe_ctx->tg, + &stream->public.timing, + true); + } + + if (!pipe_ctx_old->stream) { + if (false == pipe_ctx->tg->funcs->enable_crtc( + pipe_ctx->tg)) { + BREAK_TO_DEBUGGER(); + return DC_ERROR_UNEXPECTED; + } + } + + return DC_OK; +} + +static enum dc_status apply_single_controller_ctx_to_hw( + struct pipe_ctx *pipe_ctx, + struct validate_context *context, + struct core_dc *dc) +{ + struct core_stream *stream = pipe_ctx->stream; + struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + pipe_ctx[pipe_ctx->pipe_idx]; + + /* */ + dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); + + pipe_ctx->opp->funcs->opp_set_dyn_expansion( + pipe_ctx->opp, + COLOR_SPACE_YCBCR601, + stream->public.timing.display_color_depth, + pipe_ctx->stream->signal); + + pipe_ctx->opp->funcs->opp_program_fmt( + pipe_ctx->opp, + &stream->bit_depth_params, + &stream->clamping); + + /* FPGA does not program backend */ + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) + return DC_OK; + + /* TODO: move to stream encoder */ + if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) + if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { + BREAK_TO_DEBUGGER(); + return DC_ERROR_UNEXPECTED; + } + + if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) + stream->sink->link->link_enc->funcs->setup( + stream->sink->link->link_enc, + pipe_ctx->stream->signal); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( + pipe_ctx->stream_enc, + &stream->public.timing, + stream->public.output_color_space); + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( + pipe_ctx->stream_enc, + &stream->public.timing, + stream->phy_pix_clk, + pipe_ctx->audio != NULL); + + if (dc_is_dvi_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( + pipe_ctx->stream_enc, + &stream->public.timing, + (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? + true : false); + + if (!pipe_ctx_old->stream) { + core_link_enable_stream(pipe_ctx); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + dce110_unblank_stream(pipe_ctx, + &stream->sink->link->public.cur_link_settings); + } + + pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + /* program_scaler and allocate_mem_input are not new asic */ + if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, + &pipe_ctx->scl_data, + sizeof(struct scaler_data)) != 0) + program_scaler(dc, pipe_ctx); + + /* mst support - use total stream count */ + pipe_ctx->mi->funcs->allocate_mem_input( + pipe_ctx->mi, + stream->public.timing.h_total, + stream->public.timing.v_total, + stream->public.timing.pix_clk_khz, + context->target_count); + + return DC_OK; +} + +/******************************************************************************/ + +static void power_down_encoders(struct core_dc *dc) +{ + int i; + + for (i = 0; i < dc->link_count; i++) { + dc->links[i]->link_enc->funcs->disable_output( + dc->links[i]->link_enc, SIGNAL_TYPE_NONE); + } +} + +static void power_down_controllers(struct core_dc *dc) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + dc->res_pool->timing_generators[i]->funcs->disable_crtc( + dc->res_pool->timing_generators[i]); + } +} + +static void power_down_clock_sources(struct core_dc *dc) +{ + int i; + + if (dc->res_pool->dp_clock_source->funcs->cs_power_down( + dc->res_pool->dp_clock_source) == false) + dm_error("Failed to power down pll! (dp clk src)\n"); + + for (i = 0; i < dc->res_pool->clk_src_count; i++) { + if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( + dc->res_pool->clock_sources[i]) == false) + dm_error("Failed to power down pll! (clk src index=%d)\n", i); + } +} + +static void power_down_all_hw_blocks(struct core_dc *dc) +{ + power_down_encoders(dc); + + power_down_controllers(dc); + + power_down_clock_sources(dc); +} + +static void disable_vga_and_power_gate_all_controllers( + struct core_dc *dc) +{ + int i; + struct timing_generator *tg; + struct dc_context *ctx = dc->ctx; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + tg = dc->res_pool->timing_generators[i]; + + tg->funcs->disable_vga(tg); + + /* Enable CLOCK gating for each pipe BEFORE controller + * powergating. */ + enable_display_pipe_clock_gating(ctx, + true); + + dc->hwss.power_down_front_end( + dc, &dc->current_context->res_ctx.pipe_ctx[i]); + } +} + +/** + * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: + * 1. Power down all DC HW blocks + * 2. Disable VGA engine on all controllers + * 3. Enable power gating for controller + * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) + */ +void dce110_enable_accelerated_mode(struct core_dc *dc) +{ + power_down_all_hw_blocks(dc); + + disable_vga_and_power_gate_all_controllers(dc); + bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); +} + +/** + * Call display_engine_clock_dce80 to perform the Dclk programming. + */ +void dce110_set_display_clock(struct validate_context *context) +{ + /* Program the display engine clock. + * Check DFS bypass mode support or not. DFSbypass feature is only when + * BIOS GPU info table reports support. */ + + if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) { + /*TODO: set_display_clock_dfs_bypass( + hws, + path_set, + context->res_ctx.pool->display_clock, + context->res_ctx.min_clocks.min_dclk_khz);*/ + } else { + /* + * TODO: need to either port work around from DAL2 function + * getActualRequiredDisplayClock or program displayclock without + * calling vbios. Currently temporily work + * around by increasing the displclk by 15 percent + */ + dal_display_clock_set_clock( + context->res_ctx.pool->display_clock, + context->bw_results.dispclk_khz * 115 / 100); + } + + + /* TODO: When changing display engine clock, DMCU WaitLoop must be + * reconfigured in order to maintain the same delays within DMCU + * programming sequences. */ +} + +static uint32_t compute_pstate_blackout_duration( + struct bw_fixed blackout_duration, + const struct core_stream *stream) +{ + uint32_t total_dest_line_time_ns; + uint32_t pstate_blackout_duration_ns; + + pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; + + total_dest_line_time_ns = 1000000UL * + stream->public.timing.h_total / + stream->public.timing.pix_clk_khz + + pstate_blackout_duration_ns; + + return total_dest_line_time_ns; +} + +/* get the index of the pipe_ctx if there were no gaps in the pipe_ctx array*/ +int get_bw_result_idx( + struct resource_context *res_ctx, + int pipe_idx) +{ + int i, collapsed_idx; + + if (res_ctx->pipe_ctx[pipe_idx].top_pipe) + return 3; + + collapsed_idx = 0; + for (i = 0; i < pipe_idx; i++) { + if (res_ctx->pipe_ctx[i].stream) + collapsed_idx++; + } + + return collapsed_idx; +} + +static bool is_watermark_set_a_greater( + const struct bw_watermarks *set_a, + const struct bw_watermarks *set_b) +{ + if (set_a->a_mark > set_b->a_mark + || set_a->b_mark > set_b->b_mark + || set_a->c_mark > set_b->c_mark + || set_a->d_mark > set_b->d_mark) + return true; + return false; +} + +static bool did_watermarks_increase( + struct pipe_ctx *pipe_ctx, + struct validate_context *context, + struct validate_context *old_context) +{ + int collapsed_pipe_idx = get_bw_result_idx(&context->res_ctx, + pipe_ctx->pipe_idx); + int old_collapsed_pipe_idx = get_bw_result_idx(&old_context->res_ctx, + pipe_ctx->pipe_idx); + struct pipe_ctx *old_pipe_ctx = &old_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + + if (!old_pipe_ctx->stream) + return true; + + if (is_watermark_set_a_greater( + &context->bw_results.nbp_state_change_wm_ns[collapsed_pipe_idx], + &old_context->bw_results.nbp_state_change_wm_ns[old_collapsed_pipe_idx])) + return true; + if (is_watermark_set_a_greater( + &context->bw_results.stutter_exit_wm_ns[collapsed_pipe_idx], + &old_context->bw_results.stutter_exit_wm_ns[old_collapsed_pipe_idx])) + return true; + if (is_watermark_set_a_greater( + &context->bw_results.urgent_wm_ns[collapsed_pipe_idx], + &old_context->bw_results.urgent_wm_ns[old_collapsed_pipe_idx])) + return true; + + return false; +} + +static void program_wm_for_pipe(struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context) +{ + int total_dest_line_time_ns = compute_pstate_blackout_duration( + dc->bw_vbios.blackout_duration, + pipe_ctx->stream); + int bw_result_idx = get_bw_result_idx(&context->res_ctx, + pipe_ctx->pipe_idx); + + pipe_ctx->mi->funcs->mem_input_program_display_marks( + pipe_ctx->mi, + context->bw_results.nbp_state_change_wm_ns[bw_result_idx], + context->bw_results.stutter_exit_wm_ns[bw_result_idx], + context->bw_results.urgent_wm_ns[bw_result_idx], + total_dest_line_time_ns); + + if (pipe_ctx->top_pipe) + pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( + pipe_ctx->mi, + context->bw_results.nbp_state_change_wm_ns[bw_result_idx + 1], + context->bw_results.stutter_exit_wm_ns[bw_result_idx + 1], + context->bw_results.urgent_wm_ns[bw_result_idx + 1], + total_dest_line_time_ns); +} + +void dce110_set_displaymarks( + const struct core_dc *dc, + struct validate_context *context) +{ + uint8_t i, num_pipes; + unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; + + for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + uint32_t total_dest_line_time_ns; + + if (pipe_ctx->stream == NULL) + continue; + + total_dest_line_time_ns = compute_pstate_blackout_duration( + dc->bw_vbios.blackout_duration, pipe_ctx->stream); + pipe_ctx->mi->funcs->mem_input_program_display_marks( + pipe_ctx->mi, + context->bw_results.nbp_state_change_wm_ns[num_pipes], + context->bw_results.stutter_exit_wm_ns[num_pipes], + context->bw_results.urgent_wm_ns[num_pipes], + total_dest_line_time_ns); + if (i == underlay_idx) { + num_pipes++; + pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( + pipe_ctx->mi, + context->bw_results.nbp_state_change_wm_ns[num_pipes], + context->bw_results.stutter_exit_wm_ns[num_pipes], + context->bw_results.urgent_wm_ns[num_pipes], + total_dest_line_time_ns); + } + num_pipes++; + } +} + +static void set_safe_displaymarks(struct resource_context *res_ctx) +{ + int i; + int underlay_idx = res_ctx->pool->underlay_pipe_index; + struct bw_watermarks max_marks = { + MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; + struct bw_watermarks nbp_marks = { + SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; + + for (i = 0; i < MAX_PIPES; i++) { + if (res_ctx->pipe_ctx[i].stream == NULL) + continue; + + res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( + res_ctx->pipe_ctx[i].mi, + nbp_marks, + max_marks, + max_marks, + MAX_WATERMARK); + if (i == underlay_idx) + res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( + res_ctx->pipe_ctx[i].mi, + nbp_marks, + max_marks, + max_marks, + MAX_WATERMARK); + } +} + +static void switch_dp_clock_sources( + const struct core_dc *dc, + struct resource_context *res_ctx) +{ + uint8_t i; + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) + continue; + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) { + struct clock_source *clk_src = + resource_find_used_clk_src_for_sharing( + res_ctx, pipe_ctx); + + if (clk_src && + clk_src != pipe_ctx->clock_source) { + resource_unreference_clock_source( + res_ctx, pipe_ctx->clock_source); + pipe_ctx->clock_source = clk_src; + resource_reference_clock_source(res_ctx, clk_src); + + dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); + } + } + } +} + +/******************************************************************************* + * Public functions + ******************************************************************************/ + +static void reset_single_pipe_hw_ctx( + const struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context) +{ + core_link_disable_stream(pipe_ctx); + if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) { + dm_error("DC: failed to blank crtc!\n"); + BREAK_TO_DEBUGGER(); + } + pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); + pipe_ctx->mi->funcs->free_mem_input( + pipe_ctx->mi, context->target_count); + resource_unreference_clock_source( + &context->res_ctx, pipe_ctx->clock_source); + + dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); + + pipe_ctx->stream = NULL; +} + +static void set_drr(struct pipe_ctx **pipe_ctx, + int num_pipes, int vmin, int vmax) +{ + int i = 0; + struct drr_params params = {0}; + + params.vertical_total_max = vmax; + params.vertical_total_min = vmin; + + /* TODO: If multiple pipes are to be supported, you need + * some GSL stuff + */ + + for (i = 0; i < num_pipes; i++) { + pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); + } +} + +static void set_static_screen_control(struct pipe_ctx **pipe_ctx, + int num_pipes, int value) +{ + unsigned int i; + + for (i = 0; i < num_pipes; i++) + pipe_ctx[i]->tg->funcs-> + set_static_screen_control(pipe_ctx[i]->tg, value); +} + +/* unit: in_khz before mode set, get pixel clock from context. ASIC register + * may not be programmed yet. + * TODO: after mode set, pre_mode_set = false, + * may read PLL register to get pixel clock + */ +static uint32_t get_max_pixel_clock_for_all_paths( + struct core_dc *dc, + struct validate_context *context, + bool pre_mode_set) +{ + uint32_t max_pix_clk = 0; + int i; + + if (!pre_mode_set) { + /* TODO: read ASIC register to get pixel clock */ + ASSERT(0); + } + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) + continue; + + /* do not check under lay */ + if (pipe_ctx->top_pipe) + continue; + + if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) + max_pix_clk = + pipe_ctx->pix_clk_params.requested_pix_clk; + } + + if (max_pix_clk == 0) + ASSERT(0); + + return max_pix_clk; +} + +/* + * Find clock state based on clock requested. if clock value is 0, simply + * set clock state as requested without finding clock state by clock value + */ +static void apply_min_clocks( + struct core_dc *dc, + struct validate_context *context, + enum clocks_state *clocks_state, + bool pre_mode_set) +{ + struct state_dependent_clocks req_clocks = {0}; + struct pipe_ctx *pipe_ctx; + int i; + + for (i = 0; i < MAX_PIPES; i++) { + pipe_ctx = &context->res_ctx.pipe_ctx[i]; + if (pipe_ctx->dis_clk != NULL) + break; + } + + if (!pre_mode_set) { + /* set clock_state without verification */ + if (dal_display_clock_set_min_clocks_state( + pipe_ctx->dis_clk, *clocks_state)) + return; + + /* TODOFPGA */ + } + + /* get the required state based on state dependent clocks: + * display clock and pixel clock + */ + req_clocks.display_clk_khz = context->bw_results.dispclk_khz; + + req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( + dc, context, true); + + if (dal_display_clock_get_required_clocks_state( + pipe_ctx->dis_clk, &req_clocks, clocks_state)) { + dal_display_clock_set_min_clocks_state( + pipe_ctx->dis_clk, *clocks_state); + } else { + } +} + +static enum dc_status apply_ctx_to_hw_fpga( + struct core_dc *dc, + struct validate_context *context) +{ + enum dc_status status = DC_ERROR_UNEXPECTED; + int i; + + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) + continue; + + if (pipe_ctx->stream == pipe_ctx_old->stream) + continue; + + status = apply_single_controller_ctx_to_hw( + pipe_ctx, + context, + dc); + + if (status != DC_OK) + return status; + } + + return DC_OK; +} + +static void reset_hw_ctx_wrap( + struct core_dc *dc, + struct validate_context *context) +{ + int i; + + /* Reset old context */ + /* look up the targets that have been removed since last commit */ + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + /* Note: We need to disable output if clock sources change, + * since bios does optimization and doesn't apply if changing + * PHY when not already disabled. + */ + + /* Skip underlay pipe since it will be handled in commit surface*/ + if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) + continue; + + if (!pipe_ctx->stream || + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + reset_single_pipe_hw_ctx( + dc, pipe_ctx_old, dc->current_context); + } +} + +/*TODO: const validate_context*/ +enum dc_status dce110_apply_ctx_to_hw( + struct core_dc *dc, + struct validate_context *context) +{ + struct dc_bios *dcb = dc->ctx->dc_bios; + enum dc_status status; + int i; + bool programmed_audio_dto = false; + enum clocks_state clocks_state = CLOCKS_STATE_INVALID; + + /* Reset old context */ + /* look up the targets that have been removed since last commit */ + dc->hwss.reset_hw_ctx_wrap(dc, context); + + /* Skip applying if no targets */ + if (context->target_count <= 0) + return DC_OK; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + apply_ctx_to_hw_fpga(dc, context); + return DC_OK; + } + + /* Apply new context */ + dcb->funcs->set_scratch_critical_state(dcb, true); + + /* below is for real asic only */ + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) + continue; + + if (pipe_ctx->stream == pipe_ctx_old->stream) { + if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) + dce_crtc_switch_to_clk_src(dc->hwseq, + pipe_ctx->clock_source, i); + continue; + } + + dc->hwss.enable_display_power_gating( + dc, i, dc->ctx->dc_bios, + PIPE_GATING_CONTROL_DISABLE); + } + + set_safe_displaymarks(&context->res_ctx); + /*TODO: when pplib works*/ + apply_min_clocks(dc, context, &clocks_state, true); + + if (context->bw_results.dispclk_khz + > dc->current_context->bw_results.dispclk_khz) + dc->hwss.set_display_clock(context); + + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) + continue; + + if (pipe_ctx->stream == pipe_ctx_old->stream) + continue; + + if (pipe_ctx->top_pipe) + continue; + + if (context->res_ctx.pipe_ctx[i].audio != NULL) { + /* Setup audio rate clock source */ + /* Issue: + * Audio lag happened on DP monitor when unplug a HDMI monitor + * + * Cause: + * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL + * is set to either dto0 or dto1, audio should work fine. + * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, + * set to dto0 will cause audio lag. + * + * Solution: + * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, + * find first available pipe with audio, setup audio wall DTO per topology + * instead of per pipe. + */ + struct audio_output audio_output; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + build_audio_output(pipe_ctx, &audio_output); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_enc->funcs->dp_audio_setup( + pipe_ctx->stream_enc, + pipe_ctx->audio->inst, + &pipe_ctx->stream->public.audio_info); + else + pipe_ctx->stream_enc->funcs->hdmi_audio_setup( + pipe_ctx->stream_enc, + pipe_ctx->audio->inst, + &pipe_ctx->stream->public.audio_info, + &audio_output.crtc_info); + + pipe_ctx->audio->funcs->az_configure( + pipe_ctx->audio, + pipe_ctx->stream->signal, + &audio_output.crtc_info, + &pipe_ctx->stream->public.audio_info); + + if (!programmed_audio_dto) { + pipe_ctx->audio->funcs->wall_dto_setup( + pipe_ctx->audio, + pipe_ctx->stream->signal, + &audio_output.crtc_info, + &audio_output.pll_info); + programmed_audio_dto = true; + } + } + + status = apply_single_controller_ctx_to_hw( + pipe_ctx, + context, + dc); + + if (DC_OK != status) + return status; + } + + dc->hwss.set_displaymarks(dc, context); + + /* to save power */ + apply_min_clocks(dc, context, &clocks_state, false); + + dcb->funcs->set_scratch_critical_state(dcb, false); + + switch_dp_clock_sources(dc, &context->res_ctx); + + return DC_OK; +} + +/******************************************************************************* + * Front End programming + ******************************************************************************/ +static void set_default_colors(struct pipe_ctx *pipe_ctx) +{ + struct default_adjustment default_adjust = { 0 }; + + default_adjust.force_hw_default = false; + if (pipe_ctx->surface == NULL) + default_adjust.in_color_space = COLOR_SPACE_SRGB; + else + default_adjust.in_color_space = + pipe_ctx->surface->public.color_space; + if (pipe_ctx->stream == NULL) + default_adjust.out_color_space = COLOR_SPACE_SRGB; + else + default_adjust.out_color_space = + pipe_ctx->stream->public.output_color_space; + default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; + default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; + + /* display color depth */ + default_adjust.color_depth = + pipe_ctx->stream->public.timing.display_color_depth; + + /* Lb color depth */ + default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; + + pipe_ctx->opp->funcs->opp_set_csc_default( + pipe_ctx->opp, &default_adjust); +} + +static void program_blender(const struct core_dc *dc, + struct pipe_ctx *pipe_ctx) +{ + enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; + + if (pipe_ctx->bottom_pipe) { + if (pipe_ctx->bottom_pipe->surface->public.visible) { + if (pipe_ctx->surface->public.visible) + blender_mode = BLND_MODE_BLENDING; + else + blender_mode = BLND_MODE_OTHER_PIPE; + } + } + dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); +} + +/** + * TODO REMOVE, USE UPDATE INSTEAD + */ +static void set_plane_config( + const struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct resource_context *res_ctx) +{ + struct mem_input *mi = pipe_ctx->mi; + struct core_surface *surface = pipe_ctx->surface; + struct xfm_grph_csc_adjustment adjust; + struct out_csc_color_matrix tbl_entry; + unsigned int i; + + memset(&adjust, 0, sizeof(adjust)); + memset(&tbl_entry, 0, sizeof(tbl_entry)); + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; + + dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); + + set_default_colors(pipe_ctx); + if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + == true) { + tbl_entry.color_space = + pipe_ctx->stream->public.output_color_space; + + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = + pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + + pipe_ctx->opp->funcs->opp_set_csc_adjustment + (pipe_ctx->opp, &tbl_entry); + } + + if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; + adjust.temperature_matrix[0] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[0]; + adjust.temperature_matrix[1] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[1]; + adjust.temperature_matrix[2] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[2]; + adjust.temperature_matrix[3] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[4]; + adjust.temperature_matrix[4] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[5]; + adjust.temperature_matrix[5] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[6]; + adjust.temperature_matrix[6] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[8]; + adjust.temperature_matrix[7] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[9]; + adjust.temperature_matrix[8] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[10]; + } + + pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); + + pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + program_scaler(dc, pipe_ctx); + + program_blender(dc, pipe_ctx); + + mi->funcs->mem_input_program_surface_config( + mi, + surface->public.format, + &surface->public.tiling_info, + &surface->public.plane_size, + surface->public.rotation, + NULL, + false); + + if (dc->public.config.gpu_vm_support) + mi->funcs->mem_input_program_pte_vm( + pipe_ctx->mi, + surface->public.format, + &surface->public.tiling_info, + surface->public.rotation); +} + +static void update_plane_addr(const struct core_dc *dc, + struct pipe_ctx *pipe_ctx) +{ + struct core_surface *surface = pipe_ctx->surface; + + if (surface == NULL) + return; + + pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( + pipe_ctx->mi, + &surface->public.address, + surface->public.flip_immediate); + + surface->status.requested_address = surface->public.address; + + if (surface->public.visible) + pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false); +} + +void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) +{ + struct core_surface *surface = pipe_ctx->surface; + + if (surface == NULL) + return; + + surface->status.is_flip_pending = + pipe_ctx->mi->funcs->mem_input_is_flip_pending( + pipe_ctx->mi); + + if (surface->status.is_flip_pending && !surface->public.visible) + pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; + + surface->status.current_address = pipe_ctx->mi->current_address; +} + +void dce110_power_down(struct core_dc *dc) +{ + power_down_all_hw_blocks(dc); + disable_vga_and_power_gate_all_controllers(dc); +} + +static bool wait_for_reset_trigger_to_occur( + struct dc_context *dc_ctx, + struct timing_generator *tg) +{ + bool rc = false; + + /* To avoid endless loop we wait at most + * frames_to_wait_on_triggered_reset frames for the reset to occur. */ + const uint32_t frames_to_wait_on_triggered_reset = 10; + uint32_t i; + + for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { + + if (!tg->funcs->is_counter_moving(tg)) { + DC_ERROR("TG counter is not moving!\n"); + break; + } + + if (tg->funcs->did_triggered_reset_occur(tg)) { + rc = true; + /* usually occurs at i=1 */ + DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", + i); + break; + } + + /* Wait for one frame. */ + tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); + tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); + } + + if (false == rc) + DC_ERROR("GSL: Timeout on reset trigger!\n"); + + return rc; +} + +/* Enable timing synchronization for a group of Timing Generators. */ +static void dce110_enable_timing_synchronization( + struct core_dc *dc, + int group_index, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + struct dcp_gsl_params gsl_params = { 0 }; + int i; + + DC_SYNC_INFO("GSL: Setting-up...\n"); + + /* Designate a single TG in the group as a master. + * Since HW doesn't care which one, we always assign + * the 1st one in the group. */ + gsl_params.gsl_group = 0; + gsl_params.gsl_master = grouped_pipes[0]->tg->inst; + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->tg->funcs->setup_global_swap_lock( + grouped_pipes[i]->tg, &gsl_params); + + /* Reset slave controllers on master VSync */ + DC_SYNC_INFO("GSL: enabling trigger-reset\n"); + + for (i = 1 /* skip the master */; i < group_size; i++) + grouped_pipes[i]->tg->funcs->enable_reset_trigger( + grouped_pipes[i]->tg, gsl_params.gsl_group); + + + + for (i = 1 /* skip the master */; i < group_size; i++) { + DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); + /* Regardless of success of the wait above, remove the reset or + * the driver will start timing out on Display requests. */ + DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); + grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); + } + + + /* GSL Vblank synchronization is a one time sync mechanism, assumption + * is that the sync'ed displays will not drift out of sync over time*/ + DC_SYNC_INFO("GSL: Restoring register states.\n"); + for (i = 0; i < group_size; i++) + grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); + + DC_SYNC_INFO("GSL: Set-up complete.\n"); +} + +static void init_hw(struct core_dc *dc) +{ + int i; + struct dc_bios *bp; + struct transform *xfm; + + bp = dc->ctx->dc_bios; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + xfm = dc->res_pool->transforms[i]; + xfm->funcs->transform_reset(xfm); + + dc->hwss.enable_display_power_gating( + dc, i, bp, + PIPE_GATING_CONTROL_INIT); + dc->hwss.enable_display_power_gating( + dc, i, bp, + PIPE_GATING_CONTROL_DISABLE); + dc->hwss.enable_display_pipe_clock_gating( + dc->ctx, + true); + } + + dce_clock_gating_power_up(dc->hwseq, false);; + /***************************************/ + + for (i = 0; i < dc->link_count; i++) { + /****************************************/ + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). */ + struct core_link *link = dc->links[i]; + link->link_enc->funcs->hw_init(link->link_enc); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + + tg->funcs->disable_vga(tg); + + /* Blank controller using driver code instead of + * command table. */ + tg->funcs->set_blank(tg, true); + } + + for (i = 0; i < dc->res_pool->audio_count; i++) { + struct audio *audio = dc->res_pool->audios[i]; + audio->funcs->hw_init(audio); + } +} + +/* TODO: move this to apply_ctx_tohw some how?*/ +static void dce110_power_on_pipe_if_needed( + struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context) +{ + struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct tg_color black_color = {0}; + + if (!old_pipe_ctx->stream && pipe_ctx->stream) { + dc->hwss.enable_display_power_gating( + dc, + pipe_ctx->pipe_idx, + dcb, PIPE_GATING_CONTROL_DISABLE); + + /* + * This is for powering on underlay, so crtc does not + * need to be enabled + */ + + pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, + &pipe_ctx->stream->public.timing, + false); + + pipe_ctx->tg->funcs->enable_advanced_request( + pipe_ctx->tg, + true, + &pipe_ctx->stream->public.timing); + + pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, + pipe_ctx->stream->public.timing.h_total, + pipe_ctx->stream->public.timing.v_total, + pipe_ctx->stream->public.timing.pix_clk_khz, + context->target_count); + + /* TODO unhardcode*/ + color_space_to_black_color(dc, + COLOR_SPACE_YCBCR601, &black_color); + pipe_ctx->tg->funcs->set_blank_color( + pipe_ctx->tg, + &black_color); + } +} + +static void dce110_increase_watermarks_for_pipe( + struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context) +{ + if (did_watermarks_increase(pipe_ctx, context, dc->current_context)) + program_wm_for_pipe(dc, pipe_ctx, context); +} + +static void dce110_set_bandwidth(struct core_dc *dc) +{ + int i; + + for (i = 0; i < dc->current_context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->stream) + continue; + + program_wm_for_pipe(dc, pipe_ctx, dc->current_context); + } + + dc->hwss.set_display_clock(dc->current_context); +} + +static void dce110_program_front_end_for_pipe( + struct core_dc *dc, struct pipe_ctx *pipe_ctx) +{ + struct mem_input *mi = pipe_ctx->mi; + struct pipe_ctx *old_pipe = NULL; + struct core_surface *surface = pipe_ctx->surface; + struct xfm_grph_csc_adjustment adjust; + struct out_csc_color_matrix tbl_entry; + unsigned int i; + + memset(&tbl_entry, 0, sizeof(tbl_entry)); + + if (dc->current_context) + old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + + memset(&adjust, 0, sizeof(adjust)); + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; + + dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); + + set_default_colors(pipe_ctx); + if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + == true) { + tbl_entry.color_space = + pipe_ctx->stream->public.output_color_space; + + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = + pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + + pipe_ctx->opp->funcs->opp_set_csc_adjustment + (pipe_ctx->opp, &tbl_entry); + } + + if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; + adjust.temperature_matrix[0] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[0]; + adjust.temperature_matrix[1] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[1]; + adjust.temperature_matrix[2] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[2]; + adjust.temperature_matrix[3] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[4]; + adjust.temperature_matrix[4] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[5]; + adjust.temperature_matrix[5] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[6]; + adjust.temperature_matrix[6] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[8]; + adjust.temperature_matrix[7] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[9]; + adjust.temperature_matrix[8] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[10]; + } + + pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); + + pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + if (old_pipe && memcmp(&old_pipe->scl_data, + &pipe_ctx->scl_data, + sizeof(struct scaler_data)) != 0) + program_scaler(dc, pipe_ctx); + + mi->funcs->mem_input_program_surface_config( + mi, + surface->public.format, + &surface->public.tiling_info, + &surface->public.plane_size, + surface->public.rotation, + false, + false); + + if (dc->public.config.gpu_vm_support) + mi->funcs->mem_input_program_pte_vm( + pipe_ctx->mi, + surface->public.format, + &surface->public.tiling_info, + surface->public.rotation); + + dm_logger_write(dc->ctx->logger, LOG_SURFACE, + "Pipe:%d 0x%x: addr hi:0x%x, " + "addr low:0x%x, " + "src: %d, %d, %d," + " %d; dst: %d, %d, %d, %d;" + "clip: %d, %d, %d, %d\n", + pipe_ctx->pipe_idx, + pipe_ctx->surface, + pipe_ctx->surface->public.address.grph.addr.high_part, + pipe_ctx->surface->public.address.grph.addr.low_part, + pipe_ctx->surface->public.src_rect.x, + pipe_ctx->surface->public.src_rect.y, + pipe_ctx->surface->public.src_rect.width, + pipe_ctx->surface->public.src_rect.height, + pipe_ctx->surface->public.dst_rect.x, + pipe_ctx->surface->public.dst_rect.y, + pipe_ctx->surface->public.dst_rect.width, + pipe_ctx->surface->public.dst_rect.height, + pipe_ctx->surface->public.clip_rect.x, + pipe_ctx->surface->public.clip_rect.y, + pipe_ctx->surface->public.clip_rect.width, + pipe_ctx->surface->public.clip_rect.height); + + dm_logger_write(dc->ctx->logger, LOG_SURFACE, + "Pipe %d: width, height, x, y\n" + "viewport:%d, %d, %d, %d\n" + "recout: %d, %d, %d, %d\n", + pipe_ctx->pipe_idx, + pipe_ctx->scl_data.viewport.width, + pipe_ctx->scl_data.viewport.height, + pipe_ctx->scl_data.viewport.x, + pipe_ctx->scl_data.viewport.y, + pipe_ctx->scl_data.recout.width, + pipe_ctx->scl_data.recout.height, + pipe_ctx->scl_data.recout.x, + pipe_ctx->scl_data.recout.y); +} + + + +static void dce110_prepare_pipe_for_surface_commit( + struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context) { + struct core_gamma *gamma = NULL; + + dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context); + + if (pipe_ctx->surface->public.gamma_correction) + gamma = DC_GAMMA_TO_CORE( + pipe_ctx->surface->public.gamma_correction); + + dc->hwss.set_gamma_correction( + pipe_ctx->ipp, + pipe_ctx->opp, + gamma, pipe_ctx->surface); +} + +static void dce110_prepare_pipe_for_context( + struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context) +{ + dce110_power_on_pipe_if_needed(dc, pipe_ctx, context); + dce110_prepare_pipe_for_surface_commit(dc, pipe_ctx, context); +} + +static void dce110_apply_ctx_for_surface( + struct core_dc *dc, + struct core_surface *surface, + struct validate_context *context) +{ + int i; + + /* TODO remove when removing the surface reset workaroud*/ + if (!surface) + return; + + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->surface != surface) + continue; + + dce110_program_front_end_for_pipe(dc, pipe_ctx); + program_blender(dc, pipe_ctx); + + } + +} + +static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe) + break; + + if (i == dc->res_pool->pipe_count) + return; + + dc->hwss.enable_display_power_gating( + dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); + if (pipe->xfm) + pipe->xfm->funcs->transform_reset(pipe->xfm); + memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); +} + +static const struct hw_sequencer_funcs dce110_funcs = { + .init_hw = init_hw, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .prepare_pipe_for_context = dce110_prepare_pipe_for_context, + .apply_ctx_for_surface = dce110_apply_ctx_for_surface, + .set_plane_config = set_plane_config, + .update_plane_addr = update_plane_addr, + .update_pending_status = dce110_update_pending_status, + .set_gamma_correction = set_gamma_ramp, + .power_down = dce110_power_down, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dce110_enable_timing_synchronization, + .update_info_frame = dce110_update_info_frame, + .enable_stream = dce110_enable_stream, + .disable_stream = dce110_disable_stream, + .unblank_stream = dce110_unblank_stream, + .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, + .enable_display_power_gating = dce110_enable_display_power_gating, + .power_down_front_end = dce110_power_down_fe, + .pipe_control_lock = dce_pipe_control_lock, + .set_display_clock = dce110_set_display_clock, + .set_displaymarks = dce110_set_displaymarks, + .increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe, + .set_bandwidth = dce110_set_bandwidth, + .set_drr = set_drr, + .set_static_screen_control = set_static_screen_control, + .reset_hw_ctx_wrap = reset_hw_ctx_wrap, + .prog_pixclk_crtc_otg = prog_pixclk_crtc_otg, +}; + +bool dce110_hw_sequencer_construct(struct core_dc *dc) +{ + dc->hwss = dce110_funcs; + + return true; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h new file mode 100644 index 000000000000..a6b4d0d2429f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -0,0 +1,62 @@ +/* +* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HWSS_DCE110_H__ +#define __DC_HWSS_DCE110_H__ + +#include "core_types.h" + +#define GAMMA_HW_POINTS_NUM 256 +struct core_dc; + +bool dce110_hw_sequencer_construct(struct core_dc *dc); + +enum dc_status dce110_apply_ctx_to_hw( + struct core_dc *dc, + struct validate_context *context); + +void dce110_set_display_clock(struct validate_context *context); + +void dce110_set_displaymarks( + const struct core_dc *dc, + struct validate_context *context); + +void dce110_enable_stream(struct pipe_ctx *pipe_ctx); + +void dce110_disable_stream(struct pipe_ctx *pipe_ctx); + +void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + struct dc_link_settings *link_settings); + +void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); + +void dce110_enable_accelerated_mode(struct core_dc *dc); + +void dce110_power_down(struct core_dc *dc); + +void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); + +#endif /* __DC_HWSS_DCE110_H__ */ + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c new file mode 100644 index 000000000000..dd69f6060bb9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c @@ -0,0 +1,62 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "include/logger_interface.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_ipp.h" + +static const struct ipp_funcs funcs = { + .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, + .ipp_cursor_set_position = dce110_ipp_cursor_set_position, + .ipp_program_prescale = dce110_ipp_program_prescale, + .ipp_set_degamma = dce110_ipp_set_degamma, +}; + +bool dce110_ipp_construct( + struct dce110_ipp* ipp, + struct dc_context *ctx, + uint32_t inst, + const struct dce110_ipp_reg_offsets *offset) +{ + ipp->base.ctx = ctx; + + ipp->base.inst = inst; + + ipp->offsets = *offset; + + ipp->base.funcs = &funcs; + + return true; +} + +void dce110_ipp_destroy(struct input_pixel_processor **ipp) +{ + dm_free(TO_DCE110_IPP(*ipp)); + *ipp = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h new file mode 100644 index 000000000000..60eebdecfa10 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h @@ -0,0 +1,76 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_IPP_DCE110_H__ +#define __DC_IPP_DCE110_H__ + +#include "ipp.h" + +struct gamma_parameters; +struct dev_c_lut; + +#define TO_DCE110_IPP(input_pixel_processor)\ + container_of(input_pixel_processor, struct dce110_ipp, base) + +struct dce110_ipp_reg_offsets { + uint32_t dcp_offset; +}; + +struct dce110_ipp { + struct input_pixel_processor base; + struct dce110_ipp_reg_offsets offsets; +}; + +bool dce110_ipp_construct( + struct dce110_ipp* ipp, + struct dc_context *ctx, + enum controller_id id, + const struct dce110_ipp_reg_offsets *offset); + +void dce110_ipp_destroy(struct input_pixel_processor **ipp); + +/* CURSOR RELATED */ +void dce110_ipp_cursor_set_position( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position); + +bool dce110_ipp_cursor_set_attributes( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes); + +/* DEGAMMA RELATED */ +bool dce110_ipp_set_degamma( + struct input_pixel_processor *ipp, + enum ipp_degamma_mode mode); + +void dce110_ipp_program_prescale( + struct input_pixel_processor *ipp, + struct ipp_prescale_params *params); +/* + * Helper functions to be resused in other ASICs + */ +void dce110_helper_select_lut(struct dce110_ipp *ipp110); + +#endif /*__DC_IPP_DCE110_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c new file mode 100644 index 000000000000..95f6ca3ba5df --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c @@ -0,0 +1,253 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "include/logger_interface.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_ipp.h" + +#define CURSOR_COLOR_BLACK 0x00000000 +#define CURSOR_COLOR_WHITE 0xFFFFFFFF + +#define DCP_REG(reg)\ + (reg + ipp110->offsets.dcp_offset) + +static void enable( + struct dce110_ipp *ipp110, + bool enable); + +static void lock( + struct dce110_ipp *ipp110, + bool enable); + +static void program_position( + struct dce110_ipp *ipp110, + uint32_t x, + uint32_t y); + +static bool program_control( + struct dce110_ipp *ipp110, + enum dc_cursor_color_format color_format, + bool enable_magnification, + bool inverse_transparent_clamping); + +static void program_hotspot( + struct dce110_ipp *ipp110, + uint32_t x, + uint32_t y); + +static void program_size( + struct dce110_ipp *ipp110, + uint32_t width, + uint32_t height); + +static void program_address( + struct dce110_ipp *ipp110, + PHYSICAL_ADDRESS_LOC address); + +void dce110_ipp_cursor_set_position( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position) +{ + struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); + + /* lock cursor registers */ + lock(ipp110, true); + + /* Flag passed in structure differentiates cursor enable/disable. */ + /* Update if it differs from cached state. */ + enable(ipp110, position->enable); + + program_position(ipp110, position->x, position->y); + + if (position->hot_spot_enable) + program_hotspot( + ipp110, + position->x_hotspot, + position->y_hotspot); + + /* unlock cursor registers */ + lock(ipp110, false); +} + +bool dce110_ipp_cursor_set_attributes( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes) +{ + struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); + /* Lock cursor registers */ + lock(ipp110, true); + + /* Program cursor control */ + program_control( + ipp110, + attributes->color_format, + attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, + attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); + + /* Program hot spot coordinates */ + program_hotspot(ipp110, attributes->x_hot, attributes->y_hot); + + /* + * Program cursor size -- NOTE: HW spec specifies that HW register + * stores size as (height - 1, width - 1) + */ + program_size(ipp110, attributes->width-1, attributes->height-1); + + /* Program cursor surface address */ + program_address(ipp110, attributes->address); + + /* Unlock Cursor registers. */ + lock(ipp110, false); + + return true; +} + +static void enable( + struct dce110_ipp *ipp110, bool enable) +{ + uint32_t value = 0; + uint32_t addr = DCP_REG(mmCUR_CONTROL); + + value = dm_read_reg(ipp110->base.ctx, addr); + set_reg_field_value(value, enable, CUR_CONTROL, CURSOR_EN); + dm_write_reg(ipp110->base.ctx, addr, value); +} + +static void lock( + struct dce110_ipp *ipp110, bool lock) +{ + uint32_t value = 0; + uint32_t addr = DCP_REG(mmCUR_UPDATE); + + value = dm_read_reg(ipp110->base.ctx, addr); + set_reg_field_value(value, lock, CUR_UPDATE, CURSOR_UPDATE_LOCK); + dm_write_reg(ipp110->base.ctx, addr, value); +} + +static void program_position( + struct dce110_ipp *ipp110, + uint32_t x, + uint32_t y) +{ + uint32_t value = 0; + uint32_t addr = DCP_REG(mmCUR_POSITION); + + value = dm_read_reg(ipp110->base.ctx, addr); + set_reg_field_value(value, x, CUR_POSITION, CURSOR_X_POSITION); + set_reg_field_value(value, y, CUR_POSITION, CURSOR_Y_POSITION); + dm_write_reg(ipp110->base.ctx, addr, value); +} + +static bool program_control( + struct dce110_ipp *ipp110, + enum dc_cursor_color_format color_format, + bool enable_magnification, + bool inverse_transparent_clamping) +{ + uint32_t value = 0; + uint32_t addr = DCP_REG(mmCUR_CONTROL); + uint32_t mode = 0; + + switch (color_format) { + case CURSOR_MODE_MONO: + mode = 0; + break; + case CURSOR_MODE_COLOR_1BIT_AND: + mode = 1; + break; + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: + mode = 2; + break; + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: + mode = 3; + break; + default: + return false; + } + + set_reg_field_value(value, mode, CUR_CONTROL, CURSOR_MODE); + set_reg_field_value(value, enable_magnification, + CUR_CONTROL, CURSOR_2X_MAGNIFY); + set_reg_field_value(value, inverse_transparent_clamping, + CUR_CONTROL, CUR_INV_TRANS_CLAMP); + dm_write_reg(ipp110->base.ctx, addr, value); + + if (color_format == CURSOR_MODE_MONO) { + addr = DCP_REG(mmCUR_COLOR1); + dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_BLACK); + addr = DCP_REG(mmCUR_COLOR2); + dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_WHITE); + } + return true; +} + +static void program_hotspot( + struct dce110_ipp *ipp110, + uint32_t x, + uint32_t y) +{ + uint32_t value = 0; + uint32_t addr = DCP_REG(mmCUR_HOT_SPOT); + + value = dm_read_reg(ipp110->base.ctx, addr); + set_reg_field_value(value, x, CUR_HOT_SPOT, CURSOR_HOT_SPOT_X); + set_reg_field_value(value, y, CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y); + dm_write_reg(ipp110->base.ctx, addr, value); +} + +static void program_size( + struct dce110_ipp *ipp110, + uint32_t width, + uint32_t height) +{ + uint32_t value = 0; + uint32_t addr = DCP_REG(mmCUR_SIZE); + + value = dm_read_reg(ipp110->base.ctx, addr); + set_reg_field_value(value, width, CUR_SIZE, CURSOR_WIDTH); + set_reg_field_value(value, height, CUR_SIZE, CURSOR_HEIGHT); + dm_write_reg(ipp110->base.ctx, addr, value); +} + +static void program_address( + struct dce110_ipp *ipp110, + PHYSICAL_ADDRESS_LOC address) +{ + uint32_t addr = DCP_REG(mmCUR_SURFACE_ADDRESS_HIGH); + /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor + * surface base address in byte. It is 4K byte aligned. + * The correct way to program cursor surface address is to first write + * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS */ + + dm_write_reg(ipp110->base.ctx, addr, address.high_part); + + addr = DCP_REG(mmCUR_SURFACE_ADDRESS); + dm_write_reg(ipp110->base.ctx, addr, address.low_part); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c new file mode 100644 index 000000000000..79a6a6dd72fc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c @@ -0,0 +1,303 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "include/logger_interface.h" +#include "include/fixed31_32.h" +#include "basics/conversion.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_ipp.h" +#include "gamma_types.h" + +#define DCP_REG(reg)\ + (reg + ipp110->offsets.dcp_offset) + +enum { + MAX_INPUT_LUT_ENTRY = 256 +}; + +/*PROTOTYPE DECLARATIONS*/ +static void set_lut_inc( + struct dce110_ipp *ipp110, + uint8_t inc, + bool is_float, + bool is_signed); + +bool dce110_ipp_set_degamma( + struct input_pixel_processor *ipp, + enum ipp_degamma_mode mode) +{ + struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); + + uint32_t value = 0; + + uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; + + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || + mode == IPP_DEGAMMA_MODE_HW_sRGB); + + set_reg_field_value( + value, + degamma_type, + DEGAMMA_CONTROL, + GRPH_DEGAMMA_MODE); + + set_reg_field_value( + value, + degamma_type, + DEGAMMA_CONTROL, + CURSOR_DEGAMMA_MODE); + + set_reg_field_value( + value, + degamma_type, + DEGAMMA_CONTROL, + CURSOR2_DEGAMMA_MODE); + + dm_write_reg(ipp110->base.ctx, DCP_REG(mmDEGAMMA_CONTROL), value); + + return true; +} + +void dce110_ipp_program_prescale( + struct input_pixel_processor *ipp, + struct ipp_prescale_params *params) +{ + struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); + + uint32_t prescale_control = 0; + uint32_t prescale_value = 0; + uint32_t legacy_lut_control = 0; + + prescale_control = dm_read_reg(ipp110->base.ctx, + DCP_REG(mmPRESCALE_GRPH_CONTROL)); + + if (params->mode != IPP_PRESCALE_MODE_BYPASS) { + + set_reg_field_value( + prescale_control, + 0, + PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS); + + /* + * If prescale is in use, then legacy lut should + * be bypassed + */ + legacy_lut_control = dm_read_reg(ipp110->base.ctx, + DCP_REG(mmINPUT_GAMMA_CONTROL)); + + set_reg_field_value( + legacy_lut_control, + 1, + INPUT_GAMMA_CONTROL, + GRPH_INPUT_GAMMA_MODE); + + dm_write_reg(ipp110->base.ctx, + DCP_REG(mmINPUT_GAMMA_CONTROL), + legacy_lut_control); + } else { + set_reg_field_value( + prescale_control, + 1, + PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS); + } + + set_reg_field_value( + prescale_value, + params->scale, + PRESCALE_VALUES_GRPH_R, + GRPH_PRESCALE_SCALE_R); + + set_reg_field_value( + prescale_value, + params->bias, + PRESCALE_VALUES_GRPH_R, + GRPH_PRESCALE_BIAS_R); + + dm_write_reg(ipp110->base.ctx, + DCP_REG(mmPRESCALE_GRPH_CONTROL), + prescale_control); + + dm_write_reg(ipp110->base.ctx, + DCP_REG(mmPRESCALE_VALUES_GRPH_R), + prescale_value); + + dm_write_reg(ipp110->base.ctx, + DCP_REG(mmPRESCALE_VALUES_GRPH_G), + prescale_value); + + dm_write_reg(ipp110->base.ctx, + DCP_REG(mmPRESCALE_VALUES_GRPH_B), + prescale_value); +} + +static void set_lut_inc( + struct dce110_ipp *ipp110, + uint8_t inc, + bool is_float, + bool is_signed) +{ + const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL); + + uint32_t value = dm_read_reg(ipp110->base.ctx, addr); + + set_reg_field_value( + value, + inc, + DC_LUT_CONTROL, + DC_LUT_INC_R); + + set_reg_field_value( + value, + inc, + DC_LUT_CONTROL, + DC_LUT_INC_G); + + set_reg_field_value( + value, + inc, + DC_LUT_CONTROL, + DC_LUT_INC_B); + + set_reg_field_value( + value, + is_float, + DC_LUT_CONTROL, + DC_LUT_DATA_R_FLOAT_POINT_EN); + + set_reg_field_value( + value, + is_float, + DC_LUT_CONTROL, + DC_LUT_DATA_G_FLOAT_POINT_EN); + + set_reg_field_value( + value, + is_float, + DC_LUT_CONTROL, + DC_LUT_DATA_B_FLOAT_POINT_EN); + + set_reg_field_value( + value, + is_signed, + DC_LUT_CONTROL, + DC_LUT_DATA_R_SIGNED_EN); + + set_reg_field_value( + value, + is_signed, + DC_LUT_CONTROL, + DC_LUT_DATA_G_SIGNED_EN); + + set_reg_field_value( + value, + is_signed, + DC_LUT_CONTROL, + DC_LUT_DATA_B_SIGNED_EN); + + dm_write_reg(ipp110->base.ctx, addr, value); +} + +void dce110_helper_select_lut(struct dce110_ipp *ipp110) +{ + uint32_t value = 0; + + set_lut_inc(ipp110, 0, false, false); + + { + const uint32_t addr = DCP_REG(mmDC_LUT_WRITE_EN_MASK); + + value = dm_read_reg(ipp110->base.ctx, addr); + + /* enable all */ + set_reg_field_value( + value, + 0x7, + DC_LUT_WRITE_EN_MASK, + DC_LUT_WRITE_EN_MASK); + + dm_write_reg(ipp110->base.ctx, addr, value); + } + + { + const uint32_t addr = DCP_REG(mmDC_LUT_RW_MODE); + + value = dm_read_reg(ipp110->base.ctx, addr); + + set_reg_field_value( + value, + 0, + DC_LUT_RW_MODE, + DC_LUT_RW_MODE); + + dm_write_reg(ipp110->base.ctx, addr, value); + } + + { + const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL); + + value = dm_read_reg(ipp110->base.ctx, addr); + + /* 00 - new u0.12 */ + set_reg_field_value( + value, + 3, + DC_LUT_CONTROL, + DC_LUT_DATA_R_FORMAT); + + set_reg_field_value( + value, + 3, + DC_LUT_CONTROL, + DC_LUT_DATA_G_FORMAT); + + set_reg_field_value( + value, + 3, + DC_LUT_CONTROL, + DC_LUT_DATA_B_FORMAT); + + dm_write_reg(ipp110->base.ctx, addr, value); + } + + { + const uint32_t addr = DCP_REG(mmDC_LUT_RW_INDEX); + + value = dm_read_reg(ipp110->base.ctx, addr); + + set_reg_field_value( + value, + 0, + DC_LUT_RW_INDEX, + DC_LUT_RW_INDEX); + + dm_write_reg(ipp110->base.ctx, addr, value); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c new file mode 100644 index 000000000000..c0a68c6f585e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -0,0 +1,535 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "dm_services.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" +/* TODO: this needs to be looked at, used by Stella's workaround*/ +#include "gmc/gmc_8_2_d.h" +#include "gmc/gmc_8_2_sh_mask.h" + +#include "include/logger_interface.h" + +#include "dce110_mem_input.h" + +#define DCP_REG(reg) (reg + mem_input110->offsets.dcp) +#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif) +#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe) + +static void program_sec_addr( + struct dce110_mem_input *mem_input110, + PHYSICAL_ADDRESS_LOC address) +{ + uint32_t value = 0; + uint32_t temp; + + /*high register MUST be programmed first*/ + temp = address.high_part & + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK; + set_reg_field_value(value, temp, + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH); + dm_write_reg(mem_input110->base.ctx, + DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH), value); + + value = 0; + temp = address.low_part >> + GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT; + set_reg_field_value(value, temp, + GRPH_SECONDARY_SURFACE_ADDRESS, + GRPH_SECONDARY_SURFACE_ADDRESS); + dm_write_reg(mem_input110->base.ctx, + DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS), value); +} + +static void program_pri_addr( + struct dce110_mem_input *mem_input110, + PHYSICAL_ADDRESS_LOC address) +{ + uint32_t value = 0; + uint32_t temp; + + /*high register MUST be programmed first*/ + temp = address.high_part & + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK; + set_reg_field_value(value, temp, + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH); + dm_write_reg(mem_input110->base.ctx, + DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH), value); + + value = 0; + temp = address.low_part >> + GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT; + set_reg_field_value(value, temp, + GRPH_PRIMARY_SURFACE_ADDRESS, + GRPH_PRIMARY_SURFACE_ADDRESS); + dm_write_reg(mem_input110->base.ctx, + DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS), value); +} + +bool dce110_mem_input_is_flip_pending(struct mem_input *mem_input) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + uint32_t value; + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); + + if (get_reg_field_value(value, GRPH_UPDATE, + GRPH_SURFACE_UPDATE_PENDING)) + return true; + + mem_input->current_address = mem_input->request_address; + return false; +} + +bool dce110_mem_input_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + + uint32_t value = 0; + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL)); + if (flip_immediate) { + set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); + set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); + } else { + set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); + set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); + } + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value); + + switch (address->type) { + case PLN_ADDR_TYPE_GRAPHICS: + if (address->grph.addr.quad_part == 0) + break; + program_pri_addr(mem_input110, address->grph.addr); + break; + case PLN_ADDR_TYPE_GRPH_STEREO: + if (address->grph_stereo.left_addr.quad_part == 0 + || address->grph_stereo.right_addr.quad_part == 0) + break; + program_pri_addr(mem_input110, address->grph_stereo.left_addr); + program_sec_addr(mem_input110, address->grph_stereo.right_addr); + break; + default: + /* not supported */ + BREAK_TO_DEBUGGER(); + break; + } + + mem_input->request_address = *address; + if (flip_immediate) + mem_input->current_address = *address; + + return true; +} + +/* Scatter Gather param tables */ +static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = { + { 8, 64, 64, 8, 8, 1, 4, 0, 0}, + { 16, 64, 32, 8, 16, 1, 8, 0, 0}, + { 32, 32, 32, 16, 16, 1, 8, 0, 0}, + { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */ +}; + +static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = { + { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */ + { 16, 256, 8, 2, 0, 1, 0, 0, 0}, + { 32, 128, 8, 4, 0, 1, 0, 0, 0}, + { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */ +}; + +static const unsigned int dvmm_Hw_Setting_Linear[4][9] = { + { 8, 4096, 1, 8, 0, 1, 0, 0, 0}, + { 16, 2048, 1, 8, 0, 1, 0, 0, 0}, + { 32, 1024, 1, 8, 0, 1, 0, 0, 0}, + { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */ +}; + +/* Helper to get table entry from surface info */ +static const unsigned int *get_dvmm_hw_setting( + union dc_tiling_info *tiling_info, + enum surface_pixel_format format) +{ + enum bits_per_pixel { + bpp_8 = 0, + bpp_16, + bpp_32, + bpp_64 + } bpp; + + if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) + bpp = bpp_64; + else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) + bpp = bpp_32; + else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB1555) + bpp = bpp_16; + else + bpp = bpp_8; + + switch (tiling_info->gfx8.array_mode) { + case DC_ARRAY_1D_TILED_THIN1: + case DC_ARRAY_1D_TILED_THICK: + case DC_ARRAY_PRT_TILED_THIN1: + return dvmm_Hw_Setting_1DTiling[bpp]; + case DC_ARRAY_2D_TILED_THIN1: + case DC_ARRAY_2D_TILED_THICK: + case DC_ARRAY_2D_TILED_X_THICK: + case DC_ARRAY_PRT_2D_TILED_THIN1: + case DC_ARRAY_PRT_2D_TILED_THICK: + return dvmm_Hw_Setting_2DTiling[bpp]; + case DC_ARRAY_LINEAR_GENERAL: + case DC_ARRAY_LINEAR_ALLIGNED: + return dvmm_Hw_Setting_Linear[bpp]; + default: + return dvmm_Hw_Setting_2DTiling[bpp]; + } +} + +bool dce110_mem_input_program_pte_vm( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format); + + unsigned int page_width = 0; + unsigned int page_height = 0; + unsigned int temp_page_width = pte[1]; + unsigned int temp_page_height = pte[2]; + unsigned int min_pte_before_flip = 0; + uint32_t value = 0; + + while ((temp_page_width >>= 1) != 0) + page_width++; + while ((temp_page_height >>= 1) != 0) + page_height++; + + switch (rotation) { + case ROTATION_ANGLE_90: + case ROTATION_ANGLE_270: + min_pte_before_flip = pte[4]; + break; + default: + min_pte_before_flip = pte[3]; + break; + } + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT)); + set_reg_field_value(value, 0xff, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT), value); + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_CONTROL)); + set_reg_field_value(value, page_width, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH); + set_reg_field_value(value, page_height, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT); + set_reg_field_value(value, min_pte_before_flip, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_CONTROL), value); + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_ARB_CONTROL)); + set_reg_field_value(value, pte[5], DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK); + set_reg_field_value(value, 0xff, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_ARB_CONTROL), value); + + return true; +} + +static void program_urgency_watermark( + const struct dc_context *ctx, + const uint32_t offset, + struct bw_watermarks marks_low, + uint32_t total_dest_line_time_ns) +{ + /* register value */ + uint32_t urgency_cntl = 0; + uint32_t wm_mask_cntl = 0; + + uint32_t urgency_addr = offset + mmDPG_PIPE_URGENCY_CONTROL; + uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL; + + /*Write mask to enable reading/writing of watermark set A*/ + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 1, + DPG_WATERMARK_MASK_CONTROL, + URGENCY_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + urgency_cntl = dm_read_reg(ctx, urgency_addr); + + set_reg_field_value( + urgency_cntl, + marks_low.d_mark, + DPG_PIPE_URGENCY_CONTROL, + URGENCY_LOW_WATERMARK); + + set_reg_field_value( + urgency_cntl, + total_dest_line_time_ns, + DPG_PIPE_URGENCY_CONTROL, + URGENCY_HIGH_WATERMARK); + dm_write_reg(ctx, urgency_addr, urgency_cntl); + + /*Write mask to enable reading/writing of watermark set B*/ + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 2, + DPG_WATERMARK_MASK_CONTROL, + URGENCY_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + urgency_cntl = dm_read_reg(ctx, urgency_addr); + + set_reg_field_value(urgency_cntl, + marks_low.a_mark, + DPG_PIPE_URGENCY_CONTROL, + URGENCY_LOW_WATERMARK); + + set_reg_field_value(urgency_cntl, + total_dest_line_time_ns, + DPG_PIPE_URGENCY_CONTROL, + URGENCY_HIGH_WATERMARK); + dm_write_reg(ctx, urgency_addr, urgency_cntl); +} + +static void program_stutter_watermark( + const struct dc_context *ctx, + const uint32_t offset, + struct bw_watermarks marks) +{ + /* register value */ + uint32_t stutter_cntl = 0; + uint32_t wm_mask_cntl = 0; + + uint32_t stutter_addr = offset + mmDPG_PIPE_STUTTER_CONTROL; + uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL; + + /*Write mask to enable reading/writing of watermark set A*/ + + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 1, + DPG_WATERMARK_MASK_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + stutter_cntl = dm_read_reg(ctx, stutter_addr); + + if (ctx->dc->debug.disable_stutter) { + set_reg_field_value(stutter_cntl, + 0, + DPG_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE); + } else { + set_reg_field_value(stutter_cntl, + 1, + DPG_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE); + } + + set_reg_field_value(stutter_cntl, + 1, + DPG_PIPE_STUTTER_CONTROL, + STUTTER_IGNORE_FBC); + + /*Write watermark set A*/ + set_reg_field_value(stutter_cntl, + marks.d_mark, + DPG_PIPE_STUTTER_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK); + dm_write_reg(ctx, stutter_addr, stutter_cntl); + + /*Write mask to enable reading/writing of watermark set B*/ + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 2, + DPG_WATERMARK_MASK_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + stutter_cntl = dm_read_reg(ctx, stutter_addr); + + /*Write watermark set B*/ + set_reg_field_value(stutter_cntl, + marks.a_mark, + DPG_PIPE_STUTTER_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK); + dm_write_reg(ctx, stutter_addr, stutter_cntl); +} + +static void program_nbp_watermark( + const struct dc_context *ctx, + const uint32_t offset, + struct bw_watermarks marks) +{ + uint32_t value; + uint32_t addr; + /* Write mask to enable reading/writing of watermark set A */ + addr = offset + mmDPG_WATERMARK_MASK_CONTROL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + 1, + DPG_WATERMARK_MASK_CONTROL, + NB_PSTATE_CHANGE_WATERMARK_MASK); + dm_write_reg(ctx, addr, value); + + addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + 1, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_ENABLE); + set_reg_field_value( + value, + 1, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_URGENT_DURING_REQUEST); + set_reg_field_value( + value, + 1, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST); + dm_write_reg(ctx, addr, value); + + /* Write watermark set A */ + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + marks.d_mark, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_WATERMARK); + dm_write_reg(ctx, addr, value); + + /* Write mask to enable reading/writing of watermark set B */ + addr = offset + mmDPG_WATERMARK_MASK_CONTROL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + 2, + DPG_WATERMARK_MASK_CONTROL, + NB_PSTATE_CHANGE_WATERMARK_MASK); + dm_write_reg(ctx, addr, value); + + addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + 1, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_ENABLE); + set_reg_field_value( + value, + 1, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_URGENT_DURING_REQUEST); + set_reg_field_value( + value, + 1, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST); + dm_write_reg(ctx, addr, value); + + /* Write watermark set B */ + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + marks.a_mark, + DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_WATERMARK); + dm_write_reg(ctx, addr, value); +} + +void dce110_mem_input_program_display_marks( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns) +{ + struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input); + + program_urgency_watermark( + mem_input->ctx, + bm_dce110->offsets.dmif, + urgent, + total_dest_line_time_ns); + + program_nbp_watermark( + mem_input->ctx, + bm_dce110->offsets.dmif, + nbp); + + program_stutter_watermark( + mem_input->ctx, + bm_dce110->offsets.dmif, + stutter); +} + +static struct mem_input_funcs dce110_mem_input_funcs = { + .mem_input_program_display_marks = + dce110_mem_input_program_display_marks, + .allocate_mem_input = dce_mem_input_allocate_dmif, + .free_mem_input = dce_mem_input_free_dmif, + .mem_input_program_surface_flip_and_addr = + dce110_mem_input_program_surface_flip_and_addr, + .mem_input_program_pte_vm = + dce110_mem_input_program_pte_vm, + .mem_input_program_surface_config = + dce_mem_input_program_surface_config, + .mem_input_is_flip_pending = + dce110_mem_input_is_flip_pending, + .mem_input_update_dchub = NULL +}; +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +bool dce110_mem_input_construct( + struct dce110_mem_input *mem_input110, + struct dc_context *ctx, + uint32_t inst, + const struct dce110_mem_input_reg_offsets *offsets) +{ + /* supported stutter method + * STUTTER_MODE_ENHANCED + * STUTTER_MODE_QUAD_DMIF_BUFFER + * STUTTER_MODE_WATERMARK_NBP_STATE + */ + mem_input110->base.funcs = &dce110_mem_input_funcs; + mem_input110->base.ctx = ctx; + + mem_input110->base.inst = inst; + + mem_input110->offsets = *offsets; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h new file mode 100644 index 000000000000..83b2df93ce49 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h @@ -0,0 +1,131 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MEM_INPUT_DCE110_H__ +#define __DC_MEM_INPUT_DCE110_H__ + +#include "mem_input.h" + +#define TO_DCE110_MEM_INPUT(mi)\ + container_of(mi, struct dce110_mem_input, base) + +struct dce110_mem_input_reg_offsets { + uint32_t dcp; + uint32_t dmif; + uint32_t pipe; +}; + +struct dce110_mem_input { + struct mem_input base; + struct dce110_mem_input_reg_offsets offsets; +}; + +bool dce110_mem_input_construct( + struct dce110_mem_input *mem_input110, + struct dc_context *ctx, + uint32_t inst, + const struct dce110_mem_input_reg_offsets *offsets); + +/* + * dce110_mem_input_program_display_marks + * + * This function will program nbp stutter and urgency watermarks to minimum + * allowable values + */ +void dce110_mem_input_program_display_marks( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns); + +/* + * dce110_allocate_mem_input + * + * This function will allocate a dmif buffer and program required + * pixel duration for pipe + */ +void dce110_allocate_mem_input( + struct mem_input *mem_input, + uint32_t h_total,/* for current stream */ + uint32_t v_total,/* for current stream */ + uint32_t pix_clk_khz,/* for current stream */ + uint32_t total_stream_num); + +/* + * dce110_free_mem_input + * + * This function will deallocate a dmif buffer from pipe + */ +void dce110_free_mem_input( + struct mem_input *mem_input, + uint32_t total_stream_num); + +/* + * dce110_mem_input_program_surface_flip_and_addr + * + * This function programs hsync/vsync mode and surface address + */ +bool dce110_mem_input_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate); + +/* + * dce110_mem_input_program_surface_config + * + * This function will program surface tiling, size, rotation and pixel format + * to corresponding dcp registers. + */ +bool dce110_mem_input_program_surface_config( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + union plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror); + +/* + * dce110_mem_input_program_pte_vm + * + * This function will program pte vm registers. + */ +bool dce110_mem_input_program_pte_vm( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + +/* + * dce110_mem_input_is_flip_pending + * + * This function will wait until the surface update-pending bit is cleared. + * This is necessary when a flip immediate call is requested as we shouldn't + * return until the flip has actually occurred. + */ +bool dce110_mem_input_is_flip_pending( + struct mem_input *mem_input); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c new file mode 100644 index 000000000000..f0310bab4030 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -0,0 +1,1081 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "dm_services.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" +/* TODO: this needs to be looked at, used by Stella's workaround*/ +#include "gmc/gmc_8_2_d.h" +#include "gmc/gmc_8_2_sh_mask.h" + +#include "include/logger_interface.h" +#include "inc/bandwidth_calcs.h" + +#include "dce110_mem_input.h" + +#define DCP_REG(reg) (reg + mem_input110->offsets.dcp) +/*#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)*/ +/*#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)*/ + +static const struct dce110_mem_input_reg_offsets dce110_mi_v_reg_offsets[] = { + { + .dcp = 0, + .dmif = 0, + .pipe = 0, + } +}; + +static void set_flip_control( + struct dce110_mem_input *mem_input110, + bool immediate) +{ + uint32_t value = 0; + + value = dm_read_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_FLIP_CONTROL)); + + set_reg_field_value(value, 1, + UNP_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_PENDING_MODE); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_FLIP_CONTROL), + value); +} + +/* chroma part */ +static void program_pri_addr_c( + struct dce110_mem_input *mem_input110, + PHYSICAL_ADDRESS_LOC address) +{ + uint32_t value = 0; + uint32_t temp = 0; + /*high register MUST be programmed first*/ + temp = address.high_part & +UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK; + + set_reg_field_value(value, temp, + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C, + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C), + value); + + temp = 0; + value = 0; + temp = address.low_part >> + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT; + + set_reg_field_value(value, temp, + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C, + GRPH_PRIMARY_SURFACE_ADDRESS_C); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C), + value); +} + +/* luma part */ +static void program_pri_addr_l( + struct dce110_mem_input *mem_input110, + PHYSICAL_ADDRESS_LOC address) +{ + uint32_t value = 0; + uint32_t temp = 0; + + /*high register MUST be programmed first*/ + temp = address.high_part & +UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK; + + set_reg_field_value(value, temp, + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L, + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L), + value); + + temp = 0; + value = 0; + temp = address.low_part >> + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT; + + set_reg_field_value(value, temp, + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L, + GRPH_PRIMARY_SURFACE_ADDRESS_L); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L), + value); +} + +static void program_addr( + struct dce110_mem_input *mem_input110, + const struct dc_plane_address *addr) +{ + switch (addr->type) { + case PLN_ADDR_TYPE_GRAPHICS: + program_pri_addr_l( + mem_input110, + addr->grph.addr); + break; + case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: + program_pri_addr_l( + mem_input110, + addr->video_progressive.luma_addr); + program_pri_addr_c( + mem_input110, + addr->video_progressive.chroma_addr); + break; + default: + /* not supported */ + BREAK_TO_DEBUGGER(); + } +} + +static void enable(struct dce110_mem_input *mem_input110) +{ + uint32_t value = 0; + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_ENABLE)); + set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE); + dm_write_reg(mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_ENABLE), + value); +} + +static void program_tiling( + struct dce110_mem_input *mem_input110, + const union dc_tiling_info *info, + const enum surface_pixel_format pixel_format) +{ + uint32_t value = 0; + + set_reg_field_value(value, info->gfx8.num_banks, + UNP_GRPH_CONTROL, GRPH_NUM_BANKS); + + set_reg_field_value(value, info->gfx8.bank_width, + UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L); + + set_reg_field_value(value, info->gfx8.bank_height, + UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L); + + set_reg_field_value(value, info->gfx8.tile_aspect, + UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L); + + set_reg_field_value(value, info->gfx8.tile_split, + UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L); + + set_reg_field_value(value, info->gfx8.tile_mode, + UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L); + + set_reg_field_value(value, info->gfx8.pipe_config, + UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG); + + set_reg_field_value(value, info->gfx8.array_mode, + UNP_GRPH_CONTROL, GRPH_ARRAY_MODE); + + set_reg_field_value(value, 1, + UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE); + + set_reg_field_value(value, 0, + UNP_GRPH_CONTROL, GRPH_Z); + + dm_write_reg( + mem_input110->base.ctx, + mmUNP_GRPH_CONTROL, + value); + + value = 0; + + set_reg_field_value(value, info->gfx8.bank_width_c, + UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C); + + set_reg_field_value(value, info->gfx8.bank_height_c, + UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C); + + set_reg_field_value(value, info->gfx8.tile_aspect_c, + UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C); + + set_reg_field_value(value, info->gfx8.tile_split_c, + UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C); + + set_reg_field_value(value, info->gfx8.tile_mode_c, + UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C); + + dm_write_reg( + mem_input110->base.ctx, + mmUNP_GRPH_CONTROL_C, + value); +} + +static void program_size_and_rotation( + struct dce110_mem_input *mem_input110, + enum dc_rotation_angle rotation, + const union plane_size *plane_size) +{ + uint32_t value = 0; + union plane_size local_size = *plane_size; + + if (rotation == ROTATION_ANGLE_90 || + rotation == ROTATION_ANGLE_270) { + + uint32_t swap; + swap = local_size.video.luma_size.x; + local_size.video.luma_size.x = + local_size.video.luma_size.y; + local_size.video.luma_size.y = swap; + + swap = local_size.video.luma_size.width; + local_size.video.luma_size.width = + local_size.video.luma_size.height; + local_size.video.luma_size.height = swap; + + swap = local_size.video.chroma_size.x; + local_size.video.chroma_size.x = + local_size.video.chroma_size.y; + local_size.video.chroma_size.y = swap; + + swap = local_size.video.chroma_size.width; + local_size.video.chroma_size.width = + local_size.video.chroma_size.height; + local_size.video.chroma_size.height = swap; + } + + value = 0; + set_reg_field_value(value, local_size.video.luma_pitch, + UNP_GRPH_PITCH_L, GRPH_PITCH_L); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_PITCH_L), + value); + + value = 0; + set_reg_field_value(value, local_size.video.chroma_pitch, + UNP_GRPH_PITCH_C, GRPH_PITCH_C); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_PITCH_C), + value); + + value = 0; + set_reg_field_value(value, 0, + UNP_GRPH_X_START_L, GRPH_X_START_L); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_X_START_L), + value); + + value = 0; + set_reg_field_value(value, 0, + UNP_GRPH_X_START_C, GRPH_X_START_C); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_X_START_C), + value); + + value = 0; + set_reg_field_value(value, 0, + UNP_GRPH_Y_START_L, GRPH_Y_START_L); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_Y_START_L), + value); + + value = 0; + set_reg_field_value(value, 0, + UNP_GRPH_Y_START_C, GRPH_Y_START_C); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_Y_START_C), + value); + + value = 0; + set_reg_field_value(value, local_size.video.luma_size.x + + local_size.video.luma_size.width, + UNP_GRPH_X_END_L, GRPH_X_END_L); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_X_END_L), + value); + + value = 0; + set_reg_field_value(value, local_size.video.chroma_size.x + + local_size.video.chroma_size.width, + UNP_GRPH_X_END_C, GRPH_X_END_C); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_X_END_C), + value); + + value = 0; + set_reg_field_value(value, local_size.video.luma_size.y + + local_size.video.luma_size.height, + UNP_GRPH_Y_END_L, GRPH_Y_END_L); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_Y_END_L), + value); + + value = 0; + set_reg_field_value(value, local_size.video.chroma_size.y + + local_size.video.chroma_size.height, + UNP_GRPH_Y_END_C, GRPH_Y_END_C); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_Y_END_C), + value); + + value = 0; + switch (rotation) { + case ROTATION_ANGLE_90: + set_reg_field_value(value, 3, + UNP_HW_ROTATION, ROTATION_ANGLE); + break; + case ROTATION_ANGLE_180: + set_reg_field_value(value, 2, + UNP_HW_ROTATION, ROTATION_ANGLE); + break; + case ROTATION_ANGLE_270: + set_reg_field_value(value, 1, + UNP_HW_ROTATION, ROTATION_ANGLE); + break; + default: + set_reg_field_value(value, 0, + UNP_HW_ROTATION, ROTATION_ANGLE); + break; + } + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_HW_ROTATION), + value); +} + +static void program_pixel_format( + struct dce110_mem_input *mem_input110, + enum surface_pixel_format format) +{ + if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + uint32_t value; + uint8_t grph_depth; + uint8_t grph_format; + + value = dm_read_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_CONTROL)); + + switch (format) { + case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: + grph_depth = 0; + grph_format = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + grph_depth = 1; + grph_format = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + grph_depth = 2; + grph_format = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: + grph_depth = 2; + grph_format = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + grph_depth = 3; + grph_format = 0; + break; + default: + grph_depth = 2; + grph_format = 0; + break; + } + + set_reg_field_value( + value, + grph_depth, + UNP_GRPH_CONTROL, + GRPH_DEPTH); + set_reg_field_value( + value, + grph_format, + UNP_GRPH_CONTROL, + GRPH_FORMAT); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_CONTROL), + value); + + value = dm_read_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_CONTROL_EXP)); + + /* VIDEO FORMAT 0 */ + set_reg_field_value( + value, + 0, + UNP_GRPH_CONTROL_EXP, + VIDEO_FORMAT); + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_CONTROL_EXP), + value); + + } else { + /* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */ + uint32_t value; + uint8_t video_format; + + value = dm_read_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_CONTROL_EXP)); + + switch (format) { + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + video_format = 2; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + video_format = 3; + break; + default: + video_format = 0; + break; + } + + set_reg_field_value( + value, + video_format, + UNP_GRPH_CONTROL_EXP, + VIDEO_FORMAT); + + dm_write_reg( + mem_input110->base.ctx, + DCP_REG(mmUNP_GRPH_CONTROL_EXP), + value); + } +} + +bool dce110_mem_input_v_is_surface_pending(struct mem_input *mem_input) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + uint32_t value; + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_UPDATE)); + + if (get_reg_field_value(value, UNP_GRPH_UPDATE, + GRPH_SURFACE_UPDATE_PENDING)) + return true; + + mem_input->current_address = mem_input->request_address; + return false; +} + +bool dce110_mem_input_v_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + + set_flip_control(mem_input110, flip_immediate); + program_addr(mem_input110, + address); + + mem_input->request_address = *address; + + return true; +} + +/* Scatter Gather param tables */ +static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = { + { 8, 64, 64, 8, 8, 1, 4, 0, 0}, + { 16, 64, 32, 8, 16, 1, 8, 0, 0}, + { 32, 32, 32, 16, 16, 1, 8, 0, 0}, + { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */ +}; + +static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = { + { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */ + { 16, 256, 8, 2, 0, 1, 0, 0, 0}, + { 32, 128, 8, 4, 0, 1, 0, 0, 0}, + { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */ +}; + +static const unsigned int dvmm_Hw_Setting_Linear[4][9] = { + { 8, 4096, 1, 8, 0, 1, 0, 0, 0}, + { 16, 2048, 1, 8, 0, 1, 0, 0, 0}, + { 32, 1024, 1, 8, 0, 1, 0, 0, 0}, + { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */ +}; + +/* Helper to get table entry from surface info */ +static const unsigned int *get_dvmm_hw_setting( + union dc_tiling_info *tiling_info, + enum surface_pixel_format format, + bool chroma) +{ + enum bits_per_pixel { + bpp_8 = 0, + bpp_16, + bpp_32, + bpp_64 + } bpp; + + if (format >= SURFACE_PIXEL_FORMAT_INVALID) + bpp = bpp_32; + else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + bpp = chroma ? bpp_16 : bpp_8; + else + bpp = bpp_8; + + switch (tiling_info->gfx8.array_mode) { + case DC_ARRAY_1D_TILED_THIN1: + case DC_ARRAY_1D_TILED_THICK: + case DC_ARRAY_PRT_TILED_THIN1: + return dvmm_Hw_Setting_1DTiling[bpp]; + case DC_ARRAY_2D_TILED_THIN1: + case DC_ARRAY_2D_TILED_THICK: + case DC_ARRAY_2D_TILED_X_THICK: + case DC_ARRAY_PRT_2D_TILED_THIN1: + case DC_ARRAY_PRT_2D_TILED_THICK: + return dvmm_Hw_Setting_2DTiling[bpp]; + case DC_ARRAY_LINEAR_GENERAL: + case DC_ARRAY_LINEAR_ALLIGNED: + return dvmm_Hw_Setting_Linear[bpp]; + default: + return dvmm_Hw_Setting_2DTiling[bpp]; + } +} + +bool dce110_mem_input_v_program_pte_vm( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); + const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); + + unsigned int page_width = 0; + unsigned int page_height = 0; + unsigned int page_width_chroma = 0; + unsigned int page_height_chroma = 0; + unsigned int temp_page_width = pte[1]; + unsigned int temp_page_height = pte[2]; + unsigned int min_pte_before_flip = 0; + unsigned int min_pte_before_flip_chroma = 0; + uint32_t value = 0; + + while ((temp_page_width >>= 1) != 0) + page_width++; + while ((temp_page_height >>= 1) != 0) + page_height++; + + temp_page_width = pte_chroma[1]; + temp_page_height = pte_chroma[2]; + while ((temp_page_width >>= 1) != 0) + page_width_chroma++; + while ((temp_page_height >>= 1) != 0) + page_height_chroma++; + + switch (rotation) { + case ROTATION_ANGLE_90: + case ROTATION_ANGLE_270: + min_pte_before_flip = pte[4]; + min_pte_before_flip_chroma = pte_chroma[4]; + break; + default: + min_pte_before_flip = pte[3]; + min_pte_before_flip_chroma = pte_chroma[3]; + break; + } + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT)); + /* TODO: un-hardcode requestlimit */ + set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L); + set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT), value); + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL)); + set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH); + set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT); + set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL), value); + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL)); + set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK); + set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL), value); + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL_C)); + set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C); + set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C); + set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL_C), value); + + value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C)); + set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C); + set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C), value); + + return true; +} + +bool dce110_mem_input_v_program_surface_config( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + union plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizotal_mirror) +{ + struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + + enable(mem_input110); + program_tiling(mem_input110, tiling_info, format); + program_size_and_rotation(mem_input110, rotation, plane_size); + program_pixel_format(mem_input110, format); + + return true; +} + +static void program_urgency_watermark( + const struct dc_context *ctx, + const uint32_t urgency_addr, + const uint32_t wm_addr, + struct bw_watermarks marks_low, + uint32_t total_dest_line_time_ns) +{ + /* register value */ + uint32_t urgency_cntl = 0; + uint32_t wm_mask_cntl = 0; + + /*Write mask to enable reading/writing of watermark set A*/ + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 1, + DPGV0_WATERMARK_MASK_CONTROL, + URGENCY_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + urgency_cntl = dm_read_reg(ctx, urgency_addr); + + set_reg_field_value( + urgency_cntl, + marks_low.a_mark, + DPGV0_PIPE_URGENCY_CONTROL, + URGENCY_LOW_WATERMARK); + + set_reg_field_value( + urgency_cntl, + total_dest_line_time_ns, + DPGV0_PIPE_URGENCY_CONTROL, + URGENCY_HIGH_WATERMARK); + dm_write_reg(ctx, urgency_addr, urgency_cntl); + + /*Write mask to enable reading/writing of watermark set B*/ + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 2, + DPGV0_WATERMARK_MASK_CONTROL, + URGENCY_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + urgency_cntl = dm_read_reg(ctx, urgency_addr); + + set_reg_field_value(urgency_cntl, + marks_low.b_mark, + DPGV0_PIPE_URGENCY_CONTROL, + URGENCY_LOW_WATERMARK); + + set_reg_field_value(urgency_cntl, + total_dest_line_time_ns, + DPGV0_PIPE_URGENCY_CONTROL, + URGENCY_HIGH_WATERMARK); + + dm_write_reg(ctx, urgency_addr, urgency_cntl); +} + +static void program_urgency_watermark_l( + const struct dc_context *ctx, + struct bw_watermarks marks_low, + uint32_t total_dest_line_time_ns) +{ + program_urgency_watermark( + ctx, + mmDPGV0_PIPE_URGENCY_CONTROL, + mmDPGV0_WATERMARK_MASK_CONTROL, + marks_low, + total_dest_line_time_ns); +} + +static void program_urgency_watermark_c( + const struct dc_context *ctx, + struct bw_watermarks marks_low, + uint32_t total_dest_line_time_ns) +{ + program_urgency_watermark( + ctx, + mmDPGV1_PIPE_URGENCY_CONTROL, + mmDPGV1_WATERMARK_MASK_CONTROL, + marks_low, + total_dest_line_time_ns); +} + +static void program_stutter_watermark( + const struct dc_context *ctx, + const uint32_t stutter_addr, + const uint32_t wm_addr, + struct bw_watermarks marks) +{ + /* register value */ + uint32_t stutter_cntl = 0; + uint32_t wm_mask_cntl = 0; + + /*Write mask to enable reading/writing of watermark set A*/ + + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 1, + DPGV0_WATERMARK_MASK_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + stutter_cntl = dm_read_reg(ctx, stutter_addr); + + if (ctx->dc->debug.disable_stutter) { + set_reg_field_value(stutter_cntl, + 0, + DPGV0_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE); + } else { + set_reg_field_value(stutter_cntl, + 1, + DPGV0_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE); + } + + set_reg_field_value(stutter_cntl, + 1, + DPGV0_PIPE_STUTTER_CONTROL, + STUTTER_IGNORE_FBC); + + /*Write watermark set A*/ + set_reg_field_value(stutter_cntl, + marks.a_mark, + DPGV0_PIPE_STUTTER_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK); + dm_write_reg(ctx, stutter_addr, stutter_cntl); + + /*Write mask to enable reading/writing of watermark set B*/ + wm_mask_cntl = dm_read_reg(ctx, wm_addr); + set_reg_field_value(wm_mask_cntl, + 2, + DPGV0_WATERMARK_MASK_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK); + dm_write_reg(ctx, wm_addr, wm_mask_cntl); + + stutter_cntl = dm_read_reg(ctx, stutter_addr); + /*Write watermark set B*/ + set_reg_field_value(stutter_cntl, + marks.b_mark, + DPGV0_PIPE_STUTTER_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK); + dm_write_reg(ctx, stutter_addr, stutter_cntl); +} + +static void program_stutter_watermark_l( + const struct dc_context *ctx, + struct bw_watermarks marks) +{ + program_stutter_watermark(ctx, + mmDPGV0_PIPE_STUTTER_CONTROL, + mmDPGV0_WATERMARK_MASK_CONTROL, + marks); +} + +static void program_stutter_watermark_c( + const struct dc_context *ctx, + struct bw_watermarks marks) +{ + program_stutter_watermark(ctx, + mmDPGV1_PIPE_STUTTER_CONTROL, + mmDPGV1_WATERMARK_MASK_CONTROL, + marks); +} + +static void program_nbp_watermark( + const struct dc_context *ctx, + const uint32_t wm_mask_ctrl_addr, + const uint32_t nbp_pstate_ctrl_addr, + struct bw_watermarks marks) +{ + uint32_t value; + + /* Write mask to enable reading/writing of watermark set A */ + + value = dm_read_reg(ctx, wm_mask_ctrl_addr); + + set_reg_field_value( + value, + 1, + DPGV0_WATERMARK_MASK_CONTROL, + NB_PSTATE_CHANGE_WATERMARK_MASK); + dm_write_reg(ctx, wm_mask_ctrl_addr, value); + + value = dm_read_reg(ctx, nbp_pstate_ctrl_addr); + + set_reg_field_value( + value, + 1, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_ENABLE); + set_reg_field_value( + value, + 1, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_URGENT_DURING_REQUEST); + set_reg_field_value( + value, + 1, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST); + dm_write_reg(ctx, nbp_pstate_ctrl_addr, value); + + /* Write watermark set A */ + value = dm_read_reg(ctx, nbp_pstate_ctrl_addr); + set_reg_field_value( + value, + marks.a_mark, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_WATERMARK); + dm_write_reg(ctx, nbp_pstate_ctrl_addr, value); + + /* Write mask to enable reading/writing of watermark set B */ + value = dm_read_reg(ctx, wm_mask_ctrl_addr); + set_reg_field_value( + value, + 2, + DPGV0_WATERMARK_MASK_CONTROL, + NB_PSTATE_CHANGE_WATERMARK_MASK); + dm_write_reg(ctx, wm_mask_ctrl_addr, value); + + value = dm_read_reg(ctx, nbp_pstate_ctrl_addr); + set_reg_field_value( + value, + 1, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_ENABLE); + set_reg_field_value( + value, + 1, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_URGENT_DURING_REQUEST); + set_reg_field_value( + value, + 1, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST); + dm_write_reg(ctx, nbp_pstate_ctrl_addr, value); + + /* Write watermark set B */ + value = dm_read_reg(ctx, nbp_pstate_ctrl_addr); + set_reg_field_value( + value, + marks.b_mark, + DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + NB_PSTATE_CHANGE_WATERMARK); + dm_write_reg(ctx, nbp_pstate_ctrl_addr, value); +} + +static void program_nbp_watermark_l( + const struct dc_context *ctx, + struct bw_watermarks marks) +{ + program_nbp_watermark(ctx, + mmDPGV0_WATERMARK_MASK_CONTROL, + mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL, + marks); +} + +static void program_nbp_watermark_c( + const struct dc_context *ctx, + struct bw_watermarks marks) +{ + program_nbp_watermark(ctx, + mmDPGV1_WATERMARK_MASK_CONTROL, + mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL, + marks); +} + +void dce110_mem_input_v_program_display_marks( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns) +{ + program_urgency_watermark_l( + mem_input->ctx, + urgent, + total_dest_line_time_ns); + + program_nbp_watermark_l( + mem_input->ctx, + nbp); + + program_stutter_watermark_l( + mem_input->ctx, + stutter); + +} + +void dce110_mem_input_program_chroma_display_marks( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns) +{ + program_urgency_watermark_c( + mem_input->ctx, + urgent, + total_dest_line_time_ns); + + program_nbp_watermark_c( + mem_input->ctx, + nbp); + + program_stutter_watermark_c( + mem_input->ctx, + stutter); +} + +void dce110_allocate_mem_input_v( + struct mem_input *mi, + uint32_t h_total,/* for current stream */ + uint32_t v_total,/* for current stream */ + uint32_t pix_clk_khz,/* for current stream */ + uint32_t total_stream_num) +{ + uint32_t addr; + uint32_t value; + uint32_t pix_dur; + if (pix_clk_khz != 0) { + addr = mmDPGV0_PIPE_ARBITRATION_CONTROL1; + value = dm_read_reg(mi->ctx, addr); + pix_dur = 1000000000ULL / pix_clk_khz; + set_reg_field_value( + value, + pix_dur, + DPGV0_PIPE_ARBITRATION_CONTROL1, + PIXEL_DURATION); + dm_write_reg(mi->ctx, addr, value); + + addr = mmDPGV1_PIPE_ARBITRATION_CONTROL1; + value = dm_read_reg(mi->ctx, addr); + pix_dur = 1000000000ULL / pix_clk_khz; + set_reg_field_value( + value, + pix_dur, + DPGV1_PIPE_ARBITRATION_CONTROL1, + PIXEL_DURATION); + dm_write_reg(mi->ctx, addr, value); + + addr = mmDPGV0_PIPE_ARBITRATION_CONTROL2; + value = 0x4000800; + dm_write_reg(mi->ctx, addr, value); + + addr = mmDPGV1_PIPE_ARBITRATION_CONTROL2; + value = 0x4000800; + dm_write_reg(mi->ctx, addr, value); + } + +} + +void dce110_free_mem_input_v( + struct mem_input *mi, + uint32_t total_stream_num) +{ +} + +static struct mem_input_funcs dce110_mem_input_v_funcs = { + .mem_input_program_display_marks = + dce110_mem_input_v_program_display_marks, + .mem_input_program_chroma_display_marks = + dce110_mem_input_program_chroma_display_marks, + .allocate_mem_input = dce110_allocate_mem_input_v, + .free_mem_input = dce110_free_mem_input_v, + .mem_input_program_surface_flip_and_addr = + dce110_mem_input_v_program_surface_flip_and_addr, + .mem_input_program_pte_vm = + dce110_mem_input_v_program_pte_vm, + .mem_input_program_surface_config = + dce110_mem_input_v_program_surface_config, + .mem_input_is_flip_pending = + dce110_mem_input_v_is_surface_pending +}; +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +bool dce110_mem_input_v_construct( + struct dce110_mem_input *mem_input110, + struct dc_context *ctx) +{ + mem_input110->base.funcs = &dce110_mem_input_v_funcs; + mem_input110->base.ctx = ctx; + + mem_input110->base.inst = 0; + + mem_input110->offsets = dce110_mi_v_reg_offsets[0]; + + return true; +} + +#if 0 +void dce110_mem_input_v_destroy(struct mem_input **mem_input) +{ + dm_free(TO_DCE110_MEM_INPUT(*mem_input)); + *mem_input = NULL; +} +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h new file mode 100644 index 000000000000..5b1796ccefc0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h @@ -0,0 +1,94 @@ +/* Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MEM_INPUT_V_DCE110_H__ +#define __DC_MEM_INPUT_V_DCE110_H__ + +#include "mem_input.h" +#include "dce110_mem_input.h" + +bool dce110_mem_input_v_construct( + struct dce110_mem_input *mem_input110, + struct dc_context *ctx); + +/* + * This function will program nbp stutter and urgency watermarks to minimum + * allowable values + */ +void dce110_mem_input_v_program_display_marks( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns); + +/* + * This function will allocate a dmif buffer and program required + * pixel duration for pipe + */ +void dce110_allocate_mem_v_input( + struct mem_input *mem_input, + uint32_t h_total,/* for current stream */ + uint32_t v_total,/* for current stream */ + uint32_t pix_clk_khz,/* for current stream */ + uint32_t total_stream_num); + +/* + * This function will deallocate a dmif buffer from pipe + */ +void dce110_free_mem_v_input( + struct mem_input *mem_input, + uint32_t total_stream_num); + +/* + * This function programs hsync/vsync mode and surface address + */ +bool dce110_mem_input_v_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate); + +/* + * dce110_mem_input_v_program_scatter_gather + * + * This function will program scatter gather registers. + */ +bool dce110_mem_input_v_program_pte_vm( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + +/* + * This function will program surface tiling, size, rotation and pixel format + * to corresponding dcp registers. + */ +bool dce110_mem_input_v_program_surface_config( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + union plane_size *plane_size, + enum dc_rotation_angle rotation); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c new file mode 100644 index 000000000000..698ec2f55d0f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c @@ -0,0 +1,77 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_opp.h" + +#include "gamma_types.h" + +enum { + MAX_LUT_ENTRY = 256, + MAX_NUMBER_OF_ENTRIES = 256 +}; + +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +static const struct opp_funcs funcs = { + .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, + .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, + .opp_set_csc_default = dce110_opp_set_csc_default, + .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, + .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode, + .opp_destroy = dce110_opp_destroy, + .opp_program_fmt = dce110_opp_program_fmt, +}; + +bool dce110_opp_construct(struct dce110_opp *opp110, + struct dc_context *ctx, + uint32_t inst, + const struct dce110_opp_reg_offsets *offsets) +{ + opp110->base.funcs = &funcs; + + opp110->base.ctx = ctx; + + opp110->base.inst = inst; + + opp110->offsets = *offsets; + + return true; +} + +void dce110_opp_destroy(struct output_pixel_processor **opp) +{ + dm_free(FROM_DCE11_OPP(*opp)); + *opp = NULL; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h new file mode 100644 index 000000000000..2fbb2415cc97 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h @@ -0,0 +1,149 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPP_DCE110_H__ +#define __DC_OPP_DCE110_H__ + +#include "dc_types.h" +#include "opp.h" +#include "core_types.h" + +#include "gamma_types.h" /* decprecated */ + +struct gamma_parameters; + +#define FROM_DCE11_OPP(opp)\ + container_of(opp, struct dce110_opp, base) + +enum dce110_opp_reg_type { + DCE110_OPP_REG_DCP = 0, + DCE110_OPP_REG_DCFE, + DCE110_OPP_REG_FMT, + + DCE110_OPP_REG_MAX +}; + +struct dce110_regamma { + struct gamma_curve arr_curve_points[16]; + struct curve_points arr_points[3]; + uint32_t hw_points_num; + struct hw_x_point *coordinates_x; + struct pwl_result_data *rgb_resulted; + + /* re-gamma curve */ + struct pwl_float_data_ex *rgb_regamma; + /* coeff used to map user evenly distributed points + * to our hardware points (predefined) for gamma 256 */ + struct pixel_gamma_point *coeff128; + struct pixel_gamma_point *coeff128_oem; + /* coeff used to map user evenly distributed points + * to our hardware points (predefined) for gamma 1025 */ + struct pixel_gamma_point *coeff128_dx; + /* evenly distributed points, gamma 256 software points 0-255 */ + struct gamma_pixel *axis_x_256; + /* evenly distributed points, gamma 1025 software points 0-1025 */ + struct gamma_pixel *axis_x_1025; + /* OEM supplied gamma for regamma LUT */ + struct pwl_float_data *rgb_oem; + /* user supplied gamma */ + struct pwl_float_data *rgb_user; + uint32_t extra_points; + bool use_half_points; + struct fixed31_32 x_max1; + struct fixed31_32 x_max2; + struct fixed31_32 x_min; + struct fixed31_32 divider1; + struct fixed31_32 divider2; + struct fixed31_32 divider3; +}; + +/* OPP RELATED */ +#define TO_DCE110_OPP(opp)\ + container_of(opp, struct dce110_opp, base) + +struct dce110_opp_reg_offsets { + uint32_t fmt_offset; + uint32_t fmt_mem_offset; + uint32_t dcp_offset; + uint32_t dcfe_offset; +}; + +struct dce110_opp { + struct output_pixel_processor base; + struct dce110_opp_reg_offsets offsets; + struct dce110_regamma regamma; +}; + +bool dce110_opp_construct(struct dce110_opp *opp110, + struct dc_context *ctx, + uint32_t inst, + const struct dce110_opp_reg_offsets *offsets); + +void dce110_opp_destroy(struct output_pixel_processor **opp); + +/* REGAMMA RELATED */ +void dce110_opp_power_on_regamma_lut( + struct output_pixel_processor *opp, + bool power_on); + +bool dce110_opp_program_regamma_pwl( + struct output_pixel_processor *opp, + const struct pwl_params *params); + +void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, + enum opp_regamma mode); + +void dce110_opp_set_csc_adjustment( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry); + +void dce110_opp_set_csc_default( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust); + +/* FORMATTER RELATED */ +void dce110_opp_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + +void dce110_opp_program_clamping_and_pixel_encoding( + struct output_pixel_processor *opp, + const struct clamping_and_pixel_encoding_params *params); + +void dce110_opp_set_dyn_expansion( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); + +void dce110_opp_program_fmt( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + +void dce110_opp_set_clamping( + struct dce110_opp *opp110, + const struct clamping_and_pixel_encoding_params *params); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c new file mode 100644 index 000000000000..b46db202ddbb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c @@ -0,0 +1,363 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dce110_opp.h" +#include "basics/conversion.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#define DCP_REG(reg)\ + (reg + opp110->offsets.dcp_offset) + +enum { + OUTPUT_CSC_MATRIX_SIZE = 12 +}; + +static const struct out_csc_color_matrix global_color_matrix[] = { +{ COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, +{ COLOR_SPACE_SRGB_LIMITED, + { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, +{ COLOR_SPACE_YCBCR601, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, + 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, + 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, +/* TODO: correct values below */ +{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } +}; + +enum csc_color_mode { + /* 00 - BITS2:0 Bypass */ + CSC_COLOR_MODE_GRAPHICS_BYPASS, + /* 01 - hard coded coefficient TV RGB */ + CSC_COLOR_MODE_GRAPHICS_PREDEFINED, + /* 04 - programmable OUTPUT CSC coefficient */ + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, +}; + +static void program_color_matrix( + struct dce110_opp *opp110, + const struct out_csc_color_matrix *tbl_entry, + enum grph_color_adjust_option options) +{ + struct dc_context *ctx = opp110->base.ctx; + { + uint32_t value = 0; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[0], + OUTPUT_CSC_C11_C12, + OUTPUT_CSC_C11); + + set_reg_field_value( + value, + tbl_entry->regval[1], + OUTPUT_CSC_C11_C12, + OUTPUT_CSC_C12); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[2], + OUTPUT_CSC_C13_C14, + OUTPUT_CSC_C13); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[3], + OUTPUT_CSC_C13_C14, + OUTPUT_CSC_C14); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[4], + OUTPUT_CSC_C21_C22, + OUTPUT_CSC_C21); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[5], + OUTPUT_CSC_C21_C22, + OUTPUT_CSC_C22); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[6], + OUTPUT_CSC_C23_C24, + OUTPUT_CSC_C23); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[7], + OUTPUT_CSC_C23_C24, + OUTPUT_CSC_C24); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[8], + OUTPUT_CSC_C31_C32, + OUTPUT_CSC_C31); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[9], + OUTPUT_CSC_C31_C32, + OUTPUT_CSC_C32); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[10], + OUTPUT_CSC_C33_C34, + OUTPUT_CSC_C33); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[11], + OUTPUT_CSC_C33_C34, + OUTPUT_CSC_C34); + + dm_write_reg(ctx, addr, value); + } +} + +static bool configure_graphics_mode( + struct dce110_opp *opp110, + enum csc_color_mode config, + enum graphics_csc_adjust_type csc_adjust_type, + enum dc_color_space color_space) +{ + struct dc_context *ctx = opp110->base.ctx; + uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL); + uint32_t value = dm_read_reg(ctx, addr); + + set_reg_field_value( + value, + 0, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + + if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { + if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { + set_reg_field_value( + value, + 4, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + } else { + + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + set_reg_field_value( + value, + 0, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + case COLOR_SPACE_SRGB_LIMITED: + /* TV RGB */ + set_reg_field_value( + value, + 1, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YPBPR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + set_reg_field_value( + value, + 2, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YPBPR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + set_reg_field_value( + value, + 3, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + default: + return false; + } + } + } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + set_reg_field_value( + value, + 0, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + case COLOR_SPACE_SRGB_LIMITED: + /* TV RGB */ + set_reg_field_value( + value, + 1, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YPBPR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + set_reg_field_value( + value, + 2, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YPBPR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + set_reg_field_value( + value, + 3, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + break; + default: + return false; + } + + } else + /* by pass */ + set_reg_field_value( + value, + 0, + OUTPUT_CSC_CONTROL, + OUTPUT_CSC_GRPH_MODE); + + addr = DCP_REG(mmOUTPUT_CSC_CONTROL); + dm_write_reg(ctx, addr, value); + + return true; +} + +void dce110_opp_set_csc_adjustment( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + + program_color_matrix( + opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); + + /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ + configure_graphics_mode(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW, + tbl_entry->color_space); +} + +void dce110_opp_set_csc_default( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_PREDEFINED; + + if (default_adjust->force_hw_default == false) { + const struct out_csc_color_matrix *elm; + /* currently parameter not in use */ + enum grph_color_adjust_option option = + GRPH_COLOR_MATRIX_HW_DEFAULT; + uint32_t i; + /* + * HW default false we program locally defined matrix + * HW default true we use predefined hw matrix and we + * do not need to program matrix + * OEM wants the HW default via runtime parameter. + */ + option = GRPH_COLOR_MATRIX_SW; + + for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { + elm = &global_color_matrix[i]; + if (elm->color_space != default_adjust->out_color_space) + continue; + /* program the matrix with default values from this + * file */ + program_color_matrix(opp110, elm, option); + config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + break; + } + } + + /* configure the what we programmed : + * 1. Default values from this file + * 2. Use hardware default from ROM_A and we do not need to program + * matrix */ + + configure_graphics_mode(opp110, config, + default_adjust->csc_adjust_type, + default_adjust->out_color_space); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c new file mode 100644 index 000000000000..975466f6e424 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c @@ -0,0 +1,738 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dce110_opp.h" +#include "basics/conversion.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" +#include "dce/dce_11_0_enum.h" + +enum { + OUTPUT_CSC_MATRIX_SIZE = 12 +}; + +/* constrast:0 - 2.0, default 1.0 */ +#define UNDERLAY_CONTRAST_DEFAULT 100 +#define UNDERLAY_CONTRAST_MAX 200 +#define UNDERLAY_CONTRAST_MIN 0 +#define UNDERLAY_CONTRAST_STEP 1 +#define UNDERLAY_CONTRAST_DIVIDER 100 + +/* Saturation: 0 - 2.0; default 1.0 */ +#define UNDERLAY_SATURATION_DEFAULT 100 /*1.00*/ +#define UNDERLAY_SATURATION_MIN 0 +#define UNDERLAY_SATURATION_MAX 200 /* 2.00 */ +#define UNDERLAY_SATURATION_STEP 1 /* 0.01 */ +/*actual max overlay saturation + * value = UNDERLAY_SATURATION_MAX /UNDERLAY_SATURATION_DIVIDER + */ + +/* Hue */ +#define UNDERLAY_HUE_DEFAULT 0 +#define UNDERLAY_HUE_MIN -300 +#define UNDERLAY_HUE_MAX 300 +#define UNDERLAY_HUE_STEP 5 +#define UNDERLAY_HUE_DIVIDER 10 /* HW range: -30 ~ +30 */ +#define UNDERLAY_SATURATION_DIVIDER 100 + +/* Brightness: in DAL usually -.25 ~ .25. + * In MMD is -100 to +100 in 16-235 range; which when scaled to full range is + * ~-116 to +116. When normalized this is about 0.4566. + * With 100 divider this becomes 46, but we may use another for better precision + * The ideal one is 100/219 ((100/255)*(255/219)), + * i.e. min/max = +-100, divider = 219 + * default 0.0 + */ +#define UNDERLAY_BRIGHTNESS_DEFAULT 0 +#define UNDERLAY_BRIGHTNESS_MIN -46 /* ~116/255 */ +#define UNDERLAY_BRIGHTNESS_MAX 46 +#define UNDERLAY_BRIGHTNESS_STEP 1 /* .01 */ +#define UNDERLAY_BRIGHTNESS_DIVIDER 100 + +static const struct out_csc_color_matrix global_color_matrix[] = { +{ COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, +{ COLOR_SPACE_SRGB_LIMITED, + { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, +{ COLOR_SPACE_YCBCR601, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, + 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, + 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, +/* TODO: correct values below */ +{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } +}; + +enum csc_color_mode { + /* 00 - BITS2:0 Bypass */ + CSC_COLOR_MODE_GRAPHICS_BYPASS, + /* 01 - hard coded coefficient TV RGB */ + CSC_COLOR_MODE_GRAPHICS_PREDEFINED, + /* 04 - programmable OUTPUT CSC coefficient */ + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, +}; + +static void program_color_matrix_v( + struct dce110_opp *opp110, + const struct out_csc_color_matrix *tbl_entry, + enum grph_color_adjust_option options) +{ + struct dc_context *ctx = opp110->base.ctx; + uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); + bool use_set_a = (get_reg_field_value(cntl_value, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE) != 4); + + set_reg_field_value( + cntl_value, + 0, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + + if (use_set_a) { + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C11_C12_A; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[0], + OUTPUT_CSC_C11_C12_A, + OUTPUT_CSC_C11_A); + + set_reg_field_value( + value, + tbl_entry->regval[1], + OUTPUT_CSC_C11_C12_A, + OUTPUT_CSC_C12_A); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C13_C14_A; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[2], + OUTPUT_CSC_C13_C14_A, + OUTPUT_CSC_C13_A); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[3], + OUTPUT_CSC_C13_C14_A, + OUTPUT_CSC_C14_A); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C21_C22_A; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[4], + OUTPUT_CSC_C21_C22_A, + OUTPUT_CSC_C21_A); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[5], + OUTPUT_CSC_C21_C22_A, + OUTPUT_CSC_C22_A); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C23_C24_A; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[6], + OUTPUT_CSC_C23_C24_A, + OUTPUT_CSC_C23_A); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[7], + OUTPUT_CSC_C23_C24_A, + OUTPUT_CSC_C24_A); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C31_C32_A; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[8], + OUTPUT_CSC_C31_C32_A, + OUTPUT_CSC_C31_A); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[9], + OUTPUT_CSC_C31_C32_A, + OUTPUT_CSC_C32_A); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C33_C34_A; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[10], + OUTPUT_CSC_C33_C34_A, + OUTPUT_CSC_C33_A); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[11], + OUTPUT_CSC_C33_C34_A, + OUTPUT_CSC_C34_A); + + dm_write_reg(ctx, addr, value); + } + set_reg_field_value( + cntl_value, + 4, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + } else { + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C11_C12_B; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[0], + OUTPUT_CSC_C11_C12_B, + OUTPUT_CSC_C11_B); + + set_reg_field_value( + value, + tbl_entry->regval[1], + OUTPUT_CSC_C11_C12_B, + OUTPUT_CSC_C12_B); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C13_C14_B; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[2], + OUTPUT_CSC_C13_C14_B, + OUTPUT_CSC_C13_B); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[3], + OUTPUT_CSC_C13_C14_B, + OUTPUT_CSC_C14_B); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C21_C22_B; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[4], + OUTPUT_CSC_C21_C22_B, + OUTPUT_CSC_C21_B); + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[5], + OUTPUT_CSC_C21_C22_B, + OUTPUT_CSC_C22_B); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C23_C24_B; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[6], + OUTPUT_CSC_C23_C24_B, + OUTPUT_CSC_C23_B); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[7], + OUTPUT_CSC_C23_C24_B, + OUTPUT_CSC_C24_B); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C31_C32_B; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[8], + OUTPUT_CSC_C31_C32_B, + OUTPUT_CSC_C31_B); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[9], + OUTPUT_CSC_C31_C32_B, + OUTPUT_CSC_C32_B); + + dm_write_reg(ctx, addr, value); + } + { + uint32_t value = 0; + uint32_t addr = mmOUTPUT_CSC_C33_C34_B; + /* fixed S2.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[10], + OUTPUT_CSC_C33_C34_B, + OUTPUT_CSC_C33_B); + /* fixed S0.13 format */ + set_reg_field_value( + value, + tbl_entry->regval[11], + OUTPUT_CSC_C33_C34_B, + OUTPUT_CSC_C34_B); + + dm_write_reg(ctx, addr, value); + } + set_reg_field_value( + cntl_value, + 5, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + } + + dm_write_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL, cntl_value); +} + +static bool configure_graphics_mode_v( + struct dce110_opp *opp110, + enum csc_color_mode config, + enum graphics_csc_adjust_type csc_adjust_type, + enum dc_color_space color_space) +{ + struct dc_context *ctx = opp110->base.ctx; + uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL; + uint32_t value = dm_read_reg(ctx, addr); + + set_reg_field_value( + value, + 0, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + + if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { + if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) + return true; + + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + set_reg_field_value( + value, + 0, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + break; + case COLOR_SPACE_SRGB_LIMITED: + /* not supported for underlay on CZ */ + return false; + + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YPBPR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + set_reg_field_value( + value, + 2, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YPBPR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + set_reg_field_value( + value, + 3, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + break; + default: + return false; + } + + } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + set_reg_field_value( + value, + 0, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + break; + case COLOR_SPACE_SRGB_LIMITED: + /* not supported for underlay on CZ */ + return false; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YPBPR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + set_reg_field_value( + value, + 2, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YPBPR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + set_reg_field_value( + value, + 3, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + break; + default: + return false; + } + + } else + /* by pass */ + set_reg_field_value( + value, + 0, + COL_MAN_OUTPUT_CSC_CONTROL, + OUTPUT_CSC_MODE); + + addr = mmCOL_MAN_OUTPUT_CSC_CONTROL; + dm_write_reg(ctx, addr, value); + + return true; +} + +/*TODO: color depth is not correct when this is called*/ +static void set_Denormalization(struct output_pixel_processor *opp, + enum dc_color_depth color_depth) +{ + uint32_t value = dm_read_reg(opp->ctx, mmDENORM_CLAMP_CONTROL); + + switch (color_depth) { + case COLOR_DEPTH_888: + /* 255/256 for 8 bit output color depth */ + set_reg_field_value( + value, + 1, + DENORM_CLAMP_CONTROL, + DENORM_MODE); + break; + case COLOR_DEPTH_101010: + /* 1023/1024 for 10 bit output color depth */ + set_reg_field_value( + value, + 2, + DENORM_CLAMP_CONTROL, + DENORM_MODE); + break; + case COLOR_DEPTH_121212: + /* 4095/4096 for 12 bit output color depth */ + set_reg_field_value( + value, + 3, + DENORM_CLAMP_CONTROL, + DENORM_MODE); + break; + default: + /* not valid case */ + break; + } + + set_reg_field_value( + value, + 1, + DENORM_CLAMP_CONTROL, + DENORM_10BIT_OUT); + + dm_write_reg(opp->ctx, mmDENORM_CLAMP_CONTROL, value); +} + +struct input_csc_matrix { + enum dc_color_space color_space; + uint32_t regval[12]; +}; + +static const struct input_csc_matrix input_csc_matrix[] = { + {COLOR_SPACE_SRGB, +/*1_1 1_2 1_3 1_4 2_1 2_2 2_3 2_4 3_1 3_2 3_3 3_4 */ + {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + {COLOR_SPACE_SRGB_LIMITED, + {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + {COLOR_SPACE_YCBCR601, + {0x2cdd, 0x2000, 0x0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef, + 0x0, 0x2000, 0x38b4, 0xe3a6} }, + {COLOR_SPACE_YCBCR601_LIMITED, + {0x3353, 0x2568, 0x0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108, + 0x0, 0x2568, 0x40de, 0xdd3a} }, + {COLOR_SPACE_YCBCR709, + {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0, + 0x2000, 0x3b61, 0xe24f} }, + {COLOR_SPACE_YCBCR709_LIMITED, + {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0, + 0x2568, 0x43ee, 0xdbb2} } +}; + +static void program_input_csc( + struct output_pixel_processor *opp, enum dc_color_space color_space) +{ + int arr_size = sizeof(input_csc_matrix)/sizeof(struct input_csc_matrix); + struct dc_context *ctx = opp->ctx; + const uint32_t *regval = NULL; + bool use_set_a; + uint32_t value; + int i; + + for (i = 0; i < arr_size; i++) + if (input_csc_matrix[i].color_space == color_space) { + regval = input_csc_matrix[i].regval; + break; + } + if (regval == NULL) { + BREAK_TO_DEBUGGER(); + return; + } + + /* + * 1 == set A, the logic is 'if currently we're not using set A, + * then use set A, otherwise use set B' + */ + value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL); + use_set_a = get_reg_field_value( + value, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_MODE) != 1; + + if (use_set_a) { + /* fixed S2.13 format */ + value = 0; + set_reg_field_value( + value, regval[0], INPUT_CSC_C11_C12_A, INPUT_CSC_C11_A); + set_reg_field_value( + value, regval[1], INPUT_CSC_C11_C12_A, INPUT_CSC_C12_A); + dm_write_reg(ctx, mmINPUT_CSC_C11_C12_A, value); + + value = 0; + set_reg_field_value( + value, regval[2], INPUT_CSC_C13_C14_A, INPUT_CSC_C13_A); + set_reg_field_value( + value, regval[3], INPUT_CSC_C13_C14_A, INPUT_CSC_C14_A); + dm_write_reg(ctx, mmINPUT_CSC_C13_C14_A, value); + + value = 0; + set_reg_field_value( + value, regval[4], INPUT_CSC_C21_C22_A, INPUT_CSC_C21_A); + set_reg_field_value( + value, regval[5], INPUT_CSC_C21_C22_A, INPUT_CSC_C22_A); + dm_write_reg(ctx, mmINPUT_CSC_C21_C22_A, value); + + value = 0; + set_reg_field_value( + value, regval[6], INPUT_CSC_C23_C24_A, INPUT_CSC_C23_A); + set_reg_field_value( + value, regval[7], INPUT_CSC_C23_C24_A, INPUT_CSC_C24_A); + dm_write_reg(ctx, mmINPUT_CSC_C23_C24_A, value); + + value = 0; + set_reg_field_value( + value, regval[8], INPUT_CSC_C31_C32_A, INPUT_CSC_C31_A); + set_reg_field_value( + value, regval[9], INPUT_CSC_C31_C32_A, INPUT_CSC_C32_A); + dm_write_reg(ctx, mmINPUT_CSC_C31_C32_A, value); + + value = 0; + set_reg_field_value( + value, regval[10], INPUT_CSC_C33_C34_A, INPUT_CSC_C33_A); + set_reg_field_value( + value, regval[11], INPUT_CSC_C33_C34_A, INPUT_CSC_C34_A); + dm_write_reg(ctx, mmINPUT_CSC_C33_C34_A, value); + } else { + /* fixed S2.13 format */ + value = 0; + set_reg_field_value( + value, regval[0], INPUT_CSC_C11_C12_B, INPUT_CSC_C11_B); + set_reg_field_value( + value, regval[1], INPUT_CSC_C11_C12_B, INPUT_CSC_C12_B); + dm_write_reg(ctx, mmINPUT_CSC_C11_C12_B, value); + + value = 0; + set_reg_field_value( + value, regval[2], INPUT_CSC_C13_C14_B, INPUT_CSC_C13_B); + set_reg_field_value( + value, regval[3], INPUT_CSC_C13_C14_B, INPUT_CSC_C14_B); + dm_write_reg(ctx, mmINPUT_CSC_C13_C14_B, value); + + value = 0; + set_reg_field_value( + value, regval[4], INPUT_CSC_C21_C22_B, INPUT_CSC_C21_B); + set_reg_field_value( + value, regval[5], INPUT_CSC_C21_C22_B, INPUT_CSC_C22_B); + dm_write_reg(ctx, mmINPUT_CSC_C21_C22_B, value); + + value = 0; + set_reg_field_value( + value, regval[6], INPUT_CSC_C23_C24_B, INPUT_CSC_C23_B); + set_reg_field_value( + value, regval[7], INPUT_CSC_C23_C24_B, INPUT_CSC_C24_B); + dm_write_reg(ctx, mmINPUT_CSC_C23_C24_B, value); + + value = 0; + set_reg_field_value( + value, regval[8], INPUT_CSC_C31_C32_B, INPUT_CSC_C31_B); + set_reg_field_value( + value, regval[9], INPUT_CSC_C31_C32_B, INPUT_CSC_C32_B); + dm_write_reg(ctx, mmINPUT_CSC_C31_C32_B, value); + + value = 0; + set_reg_field_value( + value, regval[10], INPUT_CSC_C33_C34_B, INPUT_CSC_C33_B); + set_reg_field_value( + value, regval[11], INPUT_CSC_C33_C34_B, INPUT_CSC_C34_B); + dm_write_reg(ctx, mmINPUT_CSC_C33_C34_B, value); + } + + /* KK: leave INPUT_CSC_CONVERSION_MODE at default */ + value = 0; + /* + * select 8.4 input type instead of default 12.0. From the discussion + * with HW team, this format depends on the UNP surface format, so for + * 8-bit we should select 8.4 (4 bits truncated). For 10 it should be + * 10.2. For Carrizo we only support 8-bit surfaces on underlay pipe + * so we can always keep this at 8.4 (input_type=2). If the later asics + * start supporting 10+ bits, we will have a problem: surface + * programming including UNP_GRPH* is being done in DalISR after this, + * so either we pass surface format to here, or move this logic to ISR + */ + + set_reg_field_value( + value, 2, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_INPUT_TYPE); + set_reg_field_value( + value, + use_set_a ? 1 : 2, + COL_MAN_INPUT_CSC_CONTROL, + INPUT_CSC_MODE); + + dm_write_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL, value); +} + +void dce110_opp_v_set_csc_default( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_PREDEFINED; + + if (default_adjust->force_hw_default == false) { + const struct out_csc_color_matrix *elm; + /* currently parameter not in use */ + enum grph_color_adjust_option option = + GRPH_COLOR_MATRIX_HW_DEFAULT; + uint32_t i; + /* + * HW default false we program locally defined matrix + * HW default true we use predefined hw matrix and we + * do not need to program matrix + * OEM wants the HW default via runtime parameter. + */ + option = GRPH_COLOR_MATRIX_SW; + + for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { + elm = &global_color_matrix[i]; + if (elm->color_space != default_adjust->out_color_space) + continue; + /* program the matrix with default values from this + * file + */ + program_color_matrix_v(opp110, elm, option); + config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + break; + } + } + + program_input_csc(opp, default_adjust->in_color_space); + + /* configure the what we programmed : + * 1. Default values from this file + * 2. Use hardware default from ROM_A and we do not need to program + * matrix + */ + + configure_graphics_mode_v(opp110, config, + default_adjust->csc_adjust_type, + default_adjust->out_color_space); + + set_Denormalization(opp, default_adjust->color_depth); +} + +void dce110_opp_v_set_csc_adjustment( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + + program_color_matrix_v( + opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); + + /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ + configure_graphics_mode_v(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW, + tbl_entry->color_space); + + /*TODO: Check if denormalization is needed*/ + /*set_Denormalization(opp, adjust->color_depth);*/ +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c new file mode 100644 index 000000000000..eac20775c23f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c @@ -0,0 +1,627 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_opp.h" + +#define FMT_REG(reg)\ + (reg + opp110->offsets.fmt_offset) +/** + * set_truncation + * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp + * 2) enable truncation + * 3) HW remove 12bit FMT support for DCE11 power saving reason. + */ +static void set_truncation( + struct dce110_opp *opp110, + const struct bit_depth_reduction_params *params) +{ + uint32_t value = 0; + uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); + + /*Disable truncation*/ + value = dm_read_reg(opp110->base.ctx, addr); + set_reg_field_value(value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN); + set_reg_field_value(value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH); + set_reg_field_value(value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE); + + dm_write_reg(opp110->base.ctx, addr, value); + + /* no 10bpc trunc on DCE11*/ + if (params->flags.TRUNCATE_ENABLED == 0 || + params->flags.TRUNCATE_DEPTH == 2) + return; + + /*Set truncation depth and Enable truncation*/ + set_reg_field_value(value, 1, + FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN); + set_reg_field_value(value, params->flags.TRUNCATE_MODE, + FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE); + set_reg_field_value(value, params->flags.TRUNCATE_DEPTH, + FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH); + + dm_write_reg(opp110->base.ctx, addr, value); + +} + +/** + * set_spatial_dither + * 1) set spatial dithering mode: pattern of seed + * 2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp + * 3) set random seed + * 4) set random mode + * lfsr is reset every frame or not reset + * RGB dithering method + * 0: RGB data are all dithered with x^28+x^3+1 + * 1: R data is dithered with x^28+x^3+1 + * G data is dithered with x^28+X^9+1 + * B data is dithered with x^28+x^13+1 + * enable high pass filter or not + * 5) enable spatical dithering + */ +static void set_spatial_dither( + struct dce110_opp *opp110, + const struct bit_depth_reduction_params *params) +{ + uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); + uint32_t depth_cntl_value = 0; + uint32_t fmt_cntl_value = 0; + uint32_t dither_r_value = 0; + uint32_t dither_g_value = 0; + uint32_t dither_b_value = 0; + + /*Disable spatial (random) dithering*/ + depth_cntl_value = dm_read_reg(opp110->base.ctx, addr); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE); + set_reg_field_value(depth_cntl_value, 0, + FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE); + + dm_write_reg(opp110->base.ctx, addr, depth_cntl_value); + + /* no 10bpc on DCE11*/ + if (params->flags.SPATIAL_DITHER_ENABLED == 0 || + params->flags.SPATIAL_DITHER_DEPTH == 2) + return; + + addr = FMT_REG(mmFMT_CONTROL); + fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr); + /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ + if (params->flags.FRAME_RANDOM == 1) { + if (params->flags.SPATIAL_DITHER_DEPTH == 0 || + params->flags.SPATIAL_DITHER_DEPTH == 1) { + set_reg_field_value(fmt_cntl_value, 15, + FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX); + set_reg_field_value(fmt_cntl_value, 2, + FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP); + } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { + set_reg_field_value(fmt_cntl_value, 3, + FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX); + set_reg_field_value(fmt_cntl_value, 1, + FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP); + } else + return; + } else { + set_reg_field_value(fmt_cntl_value, 0, + FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX); + set_reg_field_value(fmt_cntl_value, 0, + FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP); + } + + dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value); + + /*Set seed for random values for + * spatial dithering for R,G,B channels*/ + addr = FMT_REG(mmFMT_DITHER_RAND_R_SEED); + set_reg_field_value(dither_r_value, params->r_seed_value, + FMT_DITHER_RAND_R_SEED, + FMT_RAND_R_SEED); + dm_write_reg(opp110->base.ctx, addr, dither_r_value); + + addr = FMT_REG(mmFMT_DITHER_RAND_G_SEED); + set_reg_field_value(dither_g_value, + params->g_seed_value, + FMT_DITHER_RAND_G_SEED, + FMT_RAND_G_SEED); + dm_write_reg(opp110->base.ctx, addr, dither_g_value); + + addr = FMT_REG(mmFMT_DITHER_RAND_B_SEED); + set_reg_field_value(dither_b_value, params->b_seed_value, + FMT_DITHER_RAND_B_SEED, + FMT_RAND_B_SEED); + dm_write_reg(opp110->base.ctx, addr, dither_b_value); + + /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero + * offset for the R/Cr channel, lower 4LSB + * is forced to zeros. Typically set to 0 + * RGB and 0x80000 YCbCr. + */ + /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero + * offset for the G/Y channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB + * and 0x80000 YCbCr. + */ + /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero + * offset for the B/Cb channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB and + * 0x80000 YCbCr. + */ + + /*Set spatial dithering bit depth*/ + set_reg_field_value(depth_cntl_value, + params->flags.SPATIAL_DITHER_DEPTH, + FMT_BIT_DEPTH_CONTROL, + FMT_SPATIAL_DITHER_DEPTH); + + /* Set spatial dithering mode + * (default is Seed patterrn AAAA...) + */ + set_reg_field_value(depth_cntl_value, + params->flags.SPATIAL_DITHER_MODE, + FMT_BIT_DEPTH_CONTROL, + FMT_SPATIAL_DITHER_MODE); + + /*Reset only at startup*/ + set_reg_field_value(depth_cntl_value, + params->flags.FRAME_RANDOM, + FMT_BIT_DEPTH_CONTROL, + FMT_FRAME_RANDOM_ENABLE); + + /*Set RGB data dithered with x^28+x^3+1*/ + set_reg_field_value(depth_cntl_value, + params->flags.RGB_RANDOM, + FMT_BIT_DEPTH_CONTROL, + FMT_RGB_RANDOM_ENABLE); + + /*Disable High pass filter*/ + set_reg_field_value(depth_cntl_value, + params->flags.HIGHPASS_RANDOM, + FMT_BIT_DEPTH_CONTROL, + FMT_HIGHPASS_RANDOM_ENABLE); + + /*Enable spatial dithering*/ + set_reg_field_value(depth_cntl_value, + 1, + FMT_BIT_DEPTH_CONTROL, + FMT_SPATIAL_DITHER_EN); + + addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); + dm_write_reg(opp110->base.ctx, addr, depth_cntl_value); + +} + +/** + * SetTemporalDither (Frame Modulation) + * 1) set temporal dither depth + * 2) select pattern: from hard-coded pattern or programmable pattern + * 3) select optimized strips for BGR or RGB LCD sub-pixel + * 4) set s matrix + * 5) set t matrix + * 6) set grey level for 0.25, 0.5, 0.75 + * 7) enable temporal dithering + */ +static void set_temporal_dither( + struct dce110_opp *opp110, + const struct bit_depth_reduction_params *params) +{ + uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); + uint32_t value; + + /*Disable temporal (frame modulation) dithering first*/ + value = dm_read_reg(opp110->base.ctx, addr); + + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_EN); + + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_RESET); + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_OFFSET); + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_DEPTH); + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_LEVEL); + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_25FRC_SEL); + + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_50FRC_SEL); + + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_75FRC_SEL); + + dm_write_reg(opp110->base.ctx, addr, value); + + /* no 10bpc dither on DCE11*/ + if (params->flags.FRAME_MODULATION_ENABLED == 0 || + params->flags.FRAME_MODULATION_DEPTH == 2) + return; + + /* Set temporal dithering depth*/ + set_reg_field_value(value, + params->flags.FRAME_MODULATION_DEPTH, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_DEPTH); + + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_RESET); + + set_reg_field_value(value, + 0, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_OFFSET); + + /*Select legacy pattern based on FRC and Temporal level*/ + addr = FMT_REG(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL); + dm_write_reg(opp110->base.ctx, addr, 0); + /*Set s matrix*/ + addr = FMT_REG( + mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX); + dm_write_reg(opp110->base.ctx, addr, 0); + /*Set t matrix*/ + addr = FMT_REG( + mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX); + dm_write_reg(opp110->base.ctx, addr, 0); + + /*Select patterns for 0.25, 0.5 and 0.75 grey level*/ + set_reg_field_value(value, + params->flags.TEMPORAL_LEVEL, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_LEVEL); + + set_reg_field_value(value, + params->flags.FRC25, + FMT_BIT_DEPTH_CONTROL, + FMT_25FRC_SEL); + + set_reg_field_value(value, + params->flags.FRC50, + FMT_BIT_DEPTH_CONTROL, + FMT_50FRC_SEL); + + set_reg_field_value(value, + params->flags.FRC75, + FMT_BIT_DEPTH_CONTROL, + FMT_75FRC_SEL); + + /*Enable bit reduction by temporal (frame modulation) dithering*/ + set_reg_field_value(value, + 1, + FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_EN); + + addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); + dm_write_reg(opp110->base.ctx, addr, value); + +} + +/** + * Set Clamping + * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) + * 1 for 8 bpc + * 2 for 10 bpc + * 3 for 12 bpc + * 7 for programable + * 2) Enable clamp if Limited range requested + */ +void dce110_opp_set_clamping( + struct dce110_opp *opp110, + const struct clamping_and_pixel_encoding_params *params) +{ + uint32_t clamp_cntl_value = 0; + uint32_t red_clamp_value = 0; + uint32_t green_clamp_value = 0; + uint32_t blue_clamp_value = 0; + uint32_t addr = FMT_REG(mmFMT_CLAMP_CNTL); + + clamp_cntl_value = dm_read_reg(opp110->base.ctx, addr); + + set_reg_field_value(clamp_cntl_value, + 0, + FMT_CLAMP_CNTL, + FMT_CLAMP_DATA_EN); + + set_reg_field_value(clamp_cntl_value, + 0, + FMT_CLAMP_CNTL, + FMT_CLAMP_COLOR_FORMAT); + + switch (params->clamping_level) { + case CLAMPING_FULL_RANGE: + break; + + case CLAMPING_LIMITED_RANGE_8BPC: + set_reg_field_value(clamp_cntl_value, + 1, + FMT_CLAMP_CNTL, + FMT_CLAMP_DATA_EN); + + set_reg_field_value(clamp_cntl_value, + 1, + FMT_CLAMP_CNTL, + FMT_CLAMP_COLOR_FORMAT); + + break; + + case CLAMPING_LIMITED_RANGE_10BPC: + set_reg_field_value(clamp_cntl_value, + 1, + FMT_CLAMP_CNTL, + FMT_CLAMP_DATA_EN); + + set_reg_field_value(clamp_cntl_value, + 2, + FMT_CLAMP_CNTL, + FMT_CLAMP_COLOR_FORMAT); + + break; + case CLAMPING_LIMITED_RANGE_12BPC: + set_reg_field_value(clamp_cntl_value, + 1, + FMT_CLAMP_CNTL, + FMT_CLAMP_DATA_EN); + + set_reg_field_value(clamp_cntl_value, + 3, + FMT_CLAMP_CNTL, + FMT_CLAMP_COLOR_FORMAT); + + break; + case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: + set_reg_field_value(clamp_cntl_value, + 1, + FMT_CLAMP_CNTL, + FMT_CLAMP_DATA_EN); + + set_reg_field_value(clamp_cntl_value, + 7, + FMT_CLAMP_CNTL, + FMT_CLAMP_COLOR_FORMAT); + + /*set the defaults*/ + set_reg_field_value(red_clamp_value, + 0x10, + FMT_CLAMP_COMPONENT_R, + FMT_CLAMP_LOWER_R); + + set_reg_field_value(red_clamp_value, + 0xFEF, + FMT_CLAMP_COMPONENT_R, + FMT_CLAMP_UPPER_R); + + addr = FMT_REG(mmFMT_CLAMP_COMPONENT_R); + dm_write_reg(opp110->base.ctx, addr, red_clamp_value); + + set_reg_field_value(green_clamp_value, + 0x10, + FMT_CLAMP_COMPONENT_G, + FMT_CLAMP_LOWER_G); + + set_reg_field_value(green_clamp_value, + 0xFEF, + FMT_CLAMP_COMPONENT_G, + FMT_CLAMP_UPPER_G); + + addr = FMT_REG(mmFMT_CLAMP_COMPONENT_G); + dm_write_reg(opp110->base.ctx, addr, green_clamp_value); + + set_reg_field_value(blue_clamp_value, + 0x10, + FMT_CLAMP_COMPONENT_B, + FMT_CLAMP_LOWER_B); + + set_reg_field_value(blue_clamp_value, + 0xFEF, + FMT_CLAMP_COMPONENT_B, + FMT_CLAMP_UPPER_B); + + addr = FMT_REG(mmFMT_CLAMP_COMPONENT_B); + dm_write_reg(opp110->base.ctx, addr, blue_clamp_value); + + break; + + default: + break; + } + + addr = FMT_REG(mmFMT_CLAMP_CNTL); + /*Set clamp control*/ + dm_write_reg(opp110->base.ctx, addr, clamp_cntl_value); + +} + +/** + * set_pixel_encoding + * + * Set Pixel Encoding + * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly + * 1: YCbCr 4:2:2 + */ +static void set_pixel_encoding( + struct dce110_opp *opp110, + const struct clamping_and_pixel_encoding_params *params) +{ + uint32_t fmt_cntl_value; + uint32_t addr = FMT_REG(mmFMT_CONTROL); + + /*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/ + fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr); + + set_reg_field_value(fmt_cntl_value, + 0, + FMT_CONTROL, + FMT_PIXEL_ENCODING); + + if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + set_reg_field_value(fmt_cntl_value, + 1, + FMT_CONTROL, + FMT_PIXEL_ENCODING); + + /*00 - Pixels drop mode ,01 - Pixels average mode*/ + set_reg_field_value(fmt_cntl_value, + 0, + FMT_CONTROL, + FMT_SUBSAMPLING_MODE); + + /*00 - Cb before Cr ,01 - Cr before Cb*/ + set_reg_field_value(fmt_cntl_value, + 0, + FMT_CONTROL, + FMT_SUBSAMPLING_ORDER); + } + dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value); + +} + +void dce110_opp_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + set_truncation(opp110, params); + set_spatial_dither(opp110, params); + set_temporal_dither(opp110, params); +} + +void dce110_opp_program_clamping_and_pixel_encoding( + struct output_pixel_processor *opp, + const struct clamping_and_pixel_encoding_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + dce110_opp_set_clamping(opp110, params); + set_pixel_encoding(opp110, params); +} + +void dce110_opp_set_dyn_expansion( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + uint32_t value; + bool enable_dyn_exp = false; + uint32_t addr = FMT_REG(mmFMT_DYNAMIC_EXP_CNTL); + + value = dm_read_reg(opp->ctx, addr); + + set_reg_field_value(value, 0, + FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); + set_reg_field_value(value, 0, + FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); + + /* From HW programming guide: + FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output + FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/ + if (color_sp == COLOR_SPACE_SRGB) + enable_dyn_exp = true; + + /*00 - 10-bit -> 12-bit dynamic expansion*/ + /*01 - 8-bit -> 12-bit dynamic expansion*/ + if (signal == SIGNAL_TYPE_HDMI_TYPE_A) { + switch (color_dpth) { + case COLOR_DEPTH_888: + set_reg_field_value(value, enable_dyn_exp ? 1:0, + FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); + set_reg_field_value(value, 1, + FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); + break; + case COLOR_DEPTH_101010: + set_reg_field_value(value, enable_dyn_exp ? 1:0, + FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); + set_reg_field_value(value, 0, + FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); + break; + case COLOR_DEPTH_121212: + break; + default: + break; + } + } + + dm_write_reg(opp->ctx, addr, value); +} + +void dce110_opp_program_fmt( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping) +{ + /* dithering is affected by , hence should be + * programmed afterwards */ + dce110_opp_program_bit_depth_reduction( + opp, + fmt_bit_depth); + + dce110_opp_program_clamping_and_pixel_encoding( + opp, + clamping); + + return; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c new file mode 100644 index 000000000000..62051abcfe2f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c @@ -0,0 +1,537 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_opp.h" +#include "gamma_types.h" + +#define DCP_REG(reg)\ + (reg + opp110->offsets.dcp_offset) + +#define DCFE_REG(reg)\ + (reg + opp110->offsets.dcfe_offset) + +enum { + MAX_PWL_ENTRY = 128, + MAX_REGIONS_NUMBER = 16 + +}; + +/* + ***************************************************************************** + * Function: regamma_config_regions_and_segments + * + * build regamma curve by using predefined hw points + * uses interface parameters ,like EDID coeff. + * + * @param : parameters interface parameters + * @return void + * + * @note + * + * @see + * + ***************************************************************************** + */ +static void regamma_config_regions_and_segments( + struct dce110_opp *opp110, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + uint32_t value = 0; + + { + set_reg_field_value( + value, + params->arr_points[0].custom_float_x, + REGAMMA_CNTLA_START_CNTL, + REGAMMA_CNTLA_EXP_REGION_START); + + set_reg_field_value( + value, + 0, + REGAMMA_CNTLA_START_CNTL, + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_START_CNTL), + value); + } + { + value = 0; + set_reg_field_value( + value, + params->arr_points[0].custom_float_slope, + REGAMMA_CNTLA_SLOPE_CNTL, + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_SLOPE_CNTL), value); + } + { + value = 0; + set_reg_field_value( + value, + params->arr_points[1].custom_float_x, + REGAMMA_CNTLA_END_CNTL1, + REGAMMA_CNTLA_EXP_REGION_END); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_END_CNTL1), value); + } + { + value = 0; + set_reg_field_value( + value, + params->arr_points[2].custom_float_slope, + REGAMMA_CNTLA_END_CNTL2, + REGAMMA_CNTLA_EXP_REGION_END_BASE); + + set_reg_field_value( + value, + params->arr_points[1].custom_float_y, + REGAMMA_CNTLA_END_CNTL2, + REGAMMA_CNTLA_EXP_REGION_END_SLOPE); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value); + } + + curve = params->arr_curve_points; + + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_0_1, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_0_1, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_0_1, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_0_1, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS); + + dm_write_reg( + opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_0_1), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_2_3, + REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_2_3, + REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_2_3, + REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_2_3, + REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_2_3), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_4_5, + REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_4_5, + REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_4_5, + REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_4_5, + REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_4_5), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_6_7, + REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_6_7, + REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_6_7, + REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_6_7, + REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_6_7), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_8_9, + REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_8_9, + REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_8_9, + REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_8_9, + REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_8_9), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_10_11, + REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_10_11, + REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_10_11, + REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_10_11, + REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_10_11), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_12_13, + REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_12_13, + REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_12_13, + REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_12_13, + REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_12_13), + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + REGAMMA_CNTLA_REGION_14_15, + REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + REGAMMA_CNTLA_REGION_14_15, + REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + REGAMMA_CNTLA_REGION_14_15, + REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + REGAMMA_CNTLA_REGION_14_15, + REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CNTLA_REGION_14_15), + value); + } +} + +static void program_pwl( + struct dce110_opp *opp110, + const struct pwl_params *params) +{ + uint32_t value; + + { + uint8_t max_tries = 10; + uint8_t counter = 0; + + /* Power on LUT memory */ + value = dm_read_reg(opp110->base.ctx, + DCFE_REG(mmDCFE_MEM_PWR_CTRL)); + + set_reg_field_value( + value, + 1, + DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS); + + dm_write_reg(opp110->base.ctx, + DCFE_REG(mmDCFE_MEM_PWR_CTRL), value); + + while (counter < max_tries) { + value = + dm_read_reg( + opp110->base.ctx, + DCFE_REG(mmDCFE_MEM_PWR_STATUS)); + + if (get_reg_field_value( + value, + DCFE_MEM_PWR_STATUS, + DCP_REGAMMA_MEM_PWR_STATE) == 0) + break; + + ++counter; + } + + if (counter == max_tries) { + dm_logger_write(opp110->base.ctx->logger, LOG_WARNING, + "%s: regamma lut was not powered on " + "in a timely manner," + " programming still proceeds\n", + __func__); + } + } + + value = 0; + + set_reg_field_value( + value, + 7, + REGAMMA_LUT_WRITE_EN_MASK, + REGAMMA_LUT_WRITE_EN_MASK); + + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_LUT_WRITE_EN_MASK), value); + dm_write_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_LUT_INDEX), 0); + + /* Program REGAMMA_LUT_DATA */ + { + const uint32_t addr = DCP_REG(mmREGAMMA_LUT_DATA); + + uint32_t i = 0; + + const struct pwl_result_data *rgb = params->rgb_resulted; + + while (i != params->hw_points_num) { + dm_write_reg(opp110->base.ctx, addr, rgb->red_reg); + dm_write_reg(opp110->base.ctx, addr, rgb->green_reg); + dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg); + + dm_write_reg(opp110->base.ctx, addr, + rgb->delta_red_reg); + dm_write_reg(opp110->base.ctx, addr, + rgb->delta_green_reg); + dm_write_reg(opp110->base.ctx, addr, + rgb->delta_blue_reg); + + ++rgb; + ++i; + } + } + + /* we are done with DCP LUT memory; re-enable low power mode */ + value = dm_read_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL)); + + set_reg_field_value( + value, + 0, + DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS); + + dm_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value); +} + +bool dce110_opp_program_regamma_pwl( + struct output_pixel_processor *opp, + const struct pwl_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + /* Setup regions */ + regamma_config_regions_and_segments(opp110, params); + + /* Program PWL */ + program_pwl(opp110, params); + + return true; +} + +void dce110_opp_power_on_regamma_lut( + struct output_pixel_processor *opp, + bool power_on) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + uint32_t value = + dm_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL)); + + set_reg_field_value( + value, + power_on, + DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS); + + set_reg_field_value( + value, + power_on, + DCFE_MEM_PWR_CTRL, + DCP_LUT_MEM_PWR_DIS); + + dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value); +} + +void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, + enum opp_regamma mode) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + uint32_t value = dm_read_reg(opp110->base.ctx, + DCP_REG(mmREGAMMA_CONTROL)); + + set_reg_field_value( + value, + mode, + REGAMMA_CONTROL, + GRPH_REGAMMA_MODE); + + dm_write_reg(opp110->base.ctx, DCP_REG(mmREGAMMA_CONTROL), + value); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c new file mode 100644 index 000000000000..3b3a9175b2c3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -0,0 +1,551 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_opp.h" +#include "gamma_types.h" + +static void power_on_lut(struct output_pixel_processor *opp, + bool power_on, bool inputgamma, bool regamma) +{ + uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL); + int i; + + if (power_on) { + if (inputgamma) + set_reg_field_value( + value, + 1, + DCFEV_MEM_PWR_CTRL, + COL_MAN_INPUT_GAMMA_MEM_PWR_DIS); + if (regamma) + set_reg_field_value( + value, + 1, + DCFEV_MEM_PWR_CTRL, + COL_MAN_GAMMA_CORR_MEM_PWR_DIS); + } else { + if (inputgamma) + set_reg_field_value( + value, + 0, + DCFEV_MEM_PWR_CTRL, + COL_MAN_INPUT_GAMMA_MEM_PWR_DIS); + if (regamma) + set_reg_field_value( + value, + 0, + DCFEV_MEM_PWR_CTRL, + COL_MAN_GAMMA_CORR_MEM_PWR_DIS); + } + + dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value); + + for (i = 0; i < 3; i++) { + value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL); + if (get_reg_field_value(value, + DCFEV_MEM_PWR_CTRL, + COL_MAN_INPUT_GAMMA_MEM_PWR_DIS) && + get_reg_field_value(value, + DCFEV_MEM_PWR_CTRL, + COL_MAN_GAMMA_CORR_MEM_PWR_DIS)) + break; + + udelay(2); + } +} + +static void set_bypass_input_gamma(struct dce110_opp *opp110) +{ + uint32_t value; + + value = dm_read_reg(opp110->base.ctx, + mmCOL_MAN_INPUT_GAMMA_CONTROL1); + + set_reg_field_value( + value, + 0, + COL_MAN_INPUT_GAMMA_CONTROL1, + INPUT_GAMMA_MODE); + + dm_write_reg(opp110->base.ctx, + mmCOL_MAN_INPUT_GAMMA_CONTROL1, value); +} + +static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode) +{ + uint32_t value = 0; + + set_reg_field_value( + value, + mode, + GAMMA_CORR_CONTROL, + GAMMA_CORR_MODE); + + dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CONTROL, 0); +} + +/* + ***************************************************************************** + * Function: regamma_config_regions_and_segments + * + * build regamma curve by using predefined hw points + * uses interface parameters ,like EDID coeff. + * + * @param : parameters interface parameters + * @return void + * + * @note + * + * @see + * + ***************************************************************************** + */ +static void regamma_config_regions_and_segments( + struct dce110_opp *opp110, const struct pwl_params *params) +{ + const struct gamma_curve *curve; + uint32_t value = 0; + + { + set_reg_field_value( + value, + params->arr_points[0].custom_float_x, + GAMMA_CORR_CNTLA_START_CNTL, + GAMMA_CORR_CNTLA_EXP_REGION_START); + + set_reg_field_value( + value, + 0, + GAMMA_CORR_CNTLA_START_CNTL, + GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT); + + dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, + value); + } + { + value = 0; + set_reg_field_value( + value, + params->arr_points[0].custom_float_slope, + GAMMA_CORR_CNTLA_SLOPE_CNTL, + GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_SLOPE_CNTL, value); + } + { + value = 0; + set_reg_field_value( + value, + params->arr_points[1].custom_float_x, + GAMMA_CORR_CNTLA_END_CNTL1, + GAMMA_CORR_CNTLA_EXP_REGION_END); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_END_CNTL1, value); + } + { + value = 0; + set_reg_field_value( + value, + params->arr_points[2].custom_float_slope, + GAMMA_CORR_CNTLA_END_CNTL2, + GAMMA_CORR_CNTLA_EXP_REGION_END_BASE); + + set_reg_field_value( + value, + params->arr_points[1].custom_float_y, + GAMMA_CORR_CNTLA_END_CNTL2, + GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_END_CNTL2, value); + } + + curve = params->arr_curve_points; + + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_0_1, + GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_0_1, + GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_0_1, + GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_0_1, + GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS); + + dm_write_reg( + opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_0_1, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_2_3, + GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_2_3, + GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_2_3, + GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_2_3, + GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_2_3, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_4_5, + GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_4_5, + GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_4_5, + GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_4_5, + GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_4_5, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_6_7, + GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_6_7, + GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_6_7, + GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_6_7, + GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_6_7, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_8_9, + GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_8_9, + GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_8_9, + GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_8_9, + GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_8_9, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_10_11, + GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_10_11, + GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_10_11, + GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_10_11, + GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_10_11, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_12_13, + GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_12_13, + GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_12_13, + GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_12_13, + GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_12_13, + value); + } + + curve += 2; + { + value = 0; + set_reg_field_value( + value, + curve[0].offset, + GAMMA_CORR_CNTLA_REGION_14_15, + GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET); + + set_reg_field_value( + value, + curve[0].segments_num, + GAMMA_CORR_CNTLA_REGION_14_15, + GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS); + + set_reg_field_value( + value, + curve[1].offset, + GAMMA_CORR_CNTLA_REGION_14_15, + GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET); + + set_reg_field_value( + value, + curve[1].segments_num, + GAMMA_CORR_CNTLA_REGION_14_15, + GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_CNTLA_REGION_14_15, + value); + } +} + +static void program_pwl(struct dce110_opp *opp110, + const struct pwl_params *params) +{ + uint32_t value = 0; + + set_reg_field_value( + value, + 7, + GAMMA_CORR_LUT_WRITE_EN_MASK, + GAMMA_CORR_LUT_WRITE_EN_MASK); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_LUT_WRITE_EN_MASK, value); + + dm_write_reg(opp110->base.ctx, + mmGAMMA_CORR_LUT_INDEX, 0); + + /* Program REGAMMA_LUT_DATA */ + { + const uint32_t addr = mmGAMMA_CORR_LUT_DATA; + uint32_t i = 0; + const struct pwl_result_data *rgb = + params->rgb_resulted; + + while (i != params->hw_points_num) { + dm_write_reg(opp110->base.ctx, addr, rgb->red_reg); + dm_write_reg(opp110->base.ctx, addr, rgb->green_reg); + dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg); + + dm_write_reg(opp110->base.ctx, addr, + rgb->delta_red_reg); + dm_write_reg(opp110->base.ctx, addr, + rgb->delta_green_reg); + dm_write_reg(opp110->base.ctx, addr, + rgb->delta_blue_reg); + + ++rgb; + ++i; + } + } +} + +bool dce110_opp_program_regamma_pwl_v( + struct output_pixel_processor *opp, + const struct pwl_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + /* Setup regions */ + regamma_config_regions_and_segments(opp110, params); + + set_bypass_input_gamma(opp110); + + /* Power on gamma LUT memory */ + power_on_lut(opp, true, false, true); + + /* Program PWL */ + program_pwl(opp110, params); + + /* program regamma config */ + configure_regamma_mode(opp110, 1); + + /* Power return to auto back */ + power_on_lut(opp, false, false, true); + + return true; +} + +void dce110_opp_power_on_regamma_lut_v( + struct output_pixel_processor *opp, + bool power_on) +{ + uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL); + + set_reg_field_value( + value, + 0, + DCFEV_MEM_PWR_CTRL, + COL_MAN_GAMMA_CORR_MEM_PWR_FORCE); + + set_reg_field_value( + value, + power_on, + DCFEV_MEM_PWR_CTRL, + COL_MAN_GAMMA_CORR_MEM_PWR_DIS); + + set_reg_field_value( + value, + 0, + DCFEV_MEM_PWR_CTRL, + COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE); + + set_reg_field_value( + value, + power_on, + DCFEV_MEM_PWR_CTRL, + COL_MAN_INPUT_GAMMA_MEM_PWR_DIS); + + dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c new file mode 100644 index 000000000000..4b32397529ec --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -0,0 +1,63 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dce110_opp.h" +#include "dce110_opp_v.h" + +#include "gamma_types.h" + +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +static const struct opp_funcs funcs = { + .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v, + .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v, + .opp_set_csc_default = dce110_opp_v_set_csc_default, + .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment, + .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode, + .opp_destroy = dce110_opp_destroy, + .opp_program_fmt = dce110_opp_program_fmt, + .opp_program_bit_depth_reduction = + dce110_opp_program_bit_depth_reduction +}; + +bool dce110_opp_v_construct(struct dce110_opp *opp110, + struct dc_context *ctx) +{ + opp110->base.funcs = &funcs; + + opp110->base.ctx = ctx; + + return true; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h new file mode 100644 index 000000000000..dcdbf86fccc1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -0,0 +1,56 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPP_DCE110_V_H__ +#define __DC_OPP_DCE110_V_H__ + +#include "dc_types.h" +#include "opp.h" +#include "core_types.h" + +#include "gamma_types.h" /* decprecated */ + +struct gamma_parameters; + +bool dce110_opp_v_construct(struct dce110_opp *opp110, + struct dc_context *ctx); + +/* underlay callbacks */ +void dce110_opp_v_set_csc_default( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust); + +void dce110_opp_v_set_csc_adjustment( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry); + +bool dce110_opp_program_regamma_pwl_v( + struct output_pixel_processor *opp, + const struct pwl_params *params); + +void dce110_opp_power_on_regamma_lut_v( + struct output_pixel_processor *opp, + bool power_on); + +#endif /* __DC_OPP_DCE110_V_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c new file mode 100644 index 000000000000..959467fa421e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -0,0 +1,1413 @@ +/* +* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "link_encoder.h" +#include "stream_encoder.h" + +#include "resource.h" +#include "dce110/dce110_resource.h" + +#include "include/irq_service_interface.h" +#include "dce/dce_audio.h" +#include "dce110/dce110_timing_generator.h" +#include "irq/dce110/irq_service_dce110.h" +#include "dce110/dce110_timing_generator_v.h" +#include "dce/dce_link_encoder.h" +#include "dce/dce_stream_encoder.h" +#include "dce110/dce110_mem_input.h" +#include "dce110/dce110_mem_input_v.h" +#include "dce110/dce110_ipp.h" +#include "dce/dce_transform.h" +#include "dce110/dce110_transform_v.h" +#include "dce110/dce110_opp.h" +#include "dce110/dce110_opp_v.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_hwseq.h" +#include "dce110/dce110_hw_sequencer.h" + +#include "reg_helper.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT +#include "gmc/gmc_8_2_d.h" +#include "gmc/gmc_8_2_sh_mask.h" +#endif + +#ifndef mmDP_DPHY_INTERNAL_CTRL + #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 + #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 + #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 + #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 + #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 + #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 + #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 + #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 + #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 + #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 +#endif + +#ifndef mmBIOS_SCRATCH_2 + #define mmBIOS_SCRATCH_2 0x05CB + #define mmBIOS_SCRATCH_6 0x05CF +#endif + +#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL + #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC + #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC + #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC + #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC + #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC + #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC + #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC + #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC +#endif + +#ifndef mmDP_DPHY_FAST_TRAINING + #define mmDP_DPHY_FAST_TRAINING 0x4ABC + #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC + #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC + #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC + #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC + #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC + #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC + #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC +#endif + +#ifndef DPHY_RX_FAST_TRAINING_CAPABLE + #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 +#endif + +static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { + { + .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), + .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), + }, + { + .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), + .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), + }, + { + .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), + .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), + }, + { + .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), + .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), + }, + { + .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), + .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), + }, + { + .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), + .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), + } +}; + +static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = { + { + .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), + .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL + - mmDPG_WATERMARK_MASK_CONTROL), + .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL + - mmPIPE0_DMIF_BUFFER_CONTROL), + }, + { + .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), + .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL + - mmDPG_WATERMARK_MASK_CONTROL), + .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL + - mmPIPE0_DMIF_BUFFER_CONTROL), + }, + { + .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), + .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL + - mmDPG_WATERMARK_MASK_CONTROL), + .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL + - mmPIPE0_DMIF_BUFFER_CONTROL), + } +}; + + +static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = { +{ + .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), +}, +{ + .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), +}, +{ + .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), +}, +{ + .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), +}, +{ + .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), +}, +{ + .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), +} +}; + + + + +/* set register offset */ +#define SR(reg_name)\ + .reg_name = mm ## reg_name + +/* set register offset with instance */ +#define SRI(reg_name, block, id)\ + .reg_name = mm ## block ## id ## _ ## reg_name + + +#define transform_regs(id)\ +[id] = {\ + XFM_COMMON_REG_LIST_DCE110(id)\ +} + +static const struct dce_transform_registers xfm_regs[] = { + transform_regs(0), + transform_regs(1), + transform_regs(2) +}; + +static const struct dce_transform_shift xfm_shift = { + XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) +}; + +static const struct dce_transform_mask xfm_mask = { + XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) +}; + +#define aux_regs(id)\ +[id] = {\ + AUX_REG_LIST(id)\ +} + +static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { + aux_regs(0), + aux_regs(1), + aux_regs(2), + aux_regs(3), + aux_regs(4), + aux_regs(5) +}; + +#define hpd_regs(id)\ +[id] = {\ + HPD_REG_LIST(id)\ +} + +static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4), + hpd_regs(5) +}; + + +#define link_regs(id)\ +[id] = {\ + LE_DCE110_REG_LIST(id)\ +} + +static const struct dce110_link_enc_registers link_enc_regs[] = { + link_regs(0), + link_regs(1), + link_regs(2), + link_regs(3), + link_regs(4), + link_regs(5), + link_regs(6), +}; + +#define stream_enc_regs(id)\ +[id] = {\ + SE_COMMON_REG_LIST(id),\ + .TMDS_CNTL = 0,\ +} + +static const struct dce110_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(0), + stream_enc_regs(1), + stream_enc_regs(2) +}; + +static const struct dce_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) +}; + +static const struct dce_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCE110(_MASK) +}; + +#define audio_regs(id)\ +[id] = {\ + AUD_COMMON_REG_LIST(id)\ +} + +static const struct dce_audio_registers audio_regs[] = { + audio_regs(0), + audio_regs(1), + audio_regs(2), + audio_regs(3), + audio_regs(4), + audio_regs(5), + audio_regs(6), +}; + +static const struct dce_audio_shift audio_shift = { + AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_aduio_mask audio_mask = { + AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +/* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ +static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = { +{ + .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ + .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +} +}; + +#define clk_src_regs(id)\ +[id] = {\ + CS_COMMON_REG_LIST_DCE_100_110(id),\ +} + +static const struct dce110_clk_src_regs clk_src_regs[] = { + clk_src_regs(0), + clk_src_regs(1), + clk_src_regs(2) +}; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + +static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 +}; + +static const struct resource_caps carrizo_resource_cap = { + .num_timing_generator = 3, + .num_video_plane = 1, + .num_audio = 3, + .num_stream_encoder = 3, + .num_pll = 2, +}; + +static const struct resource_caps stoney_resource_cap = { + .num_timing_generator = 2, + .num_video_plane = 1, + .num_audio = 3, + .num_stream_encoder = 3, + .num_pll = 2, +}; + +#define CTX ctx +#define REG(reg) mm ## reg + +#ifndef mmCC_DC_HDMI_STRAPS +#define mmCC_DC_HDMI_STRAPS 0x4819 +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 +#endif + +static void read_dce_straps( + struct dc_context *ctx, + struct resource_straps *straps) +{ + REG_GET_2(CC_DC_HDMI_STRAPS, + HDMI_DISABLE, &straps->hdmi_disable, + AUDIO_STREAM_NUMBER, &straps->audio_stream_number); + + REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); +} + +static struct audio *create_audio( + struct dc_context *ctx, unsigned int inst) +{ + return dce_audio_create(ctx, inst, + &audio_regs[inst], &audio_shift, &audio_mask); +} + +static struct timing_generator *dce110_timing_generator_create( + struct dc_context *ctx, + uint32_t instance, + const struct dce110_timing_generator_offsets *offsets) +{ + struct dce110_timing_generator *tg110 = + dm_alloc(sizeof(struct dce110_timing_generator)); + + if (!tg110) + return NULL; + + if (dce110_timing_generator_construct(tg110, ctx, instance, offsets)) + return &tg110->base; + + BREAK_TO_DEBUGGER(); + dm_free(tg110); + return NULL; +} + +static struct stream_encoder *dce110_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dce110_stream_encoder *enc110 = + dm_alloc(sizeof(struct dce110_stream_encoder)); + + if (!enc110) + return NULL; + + if (dce110_stream_encoder_construct( + enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask)) + return &enc110->base; + + BREAK_TO_DEBUGGER(); + dm_free(enc110); + return NULL; +} + +#define SRII(reg_name, block, id)\ + .reg_name[id] = mm ## block ## id ## _ ## reg_name + +static const struct dce_hwseq_registers hwseq_stoney_reg = { + HWSEQ_ST_REG_LIST() +}; + +static const struct dce_hwseq_registers hwseq_cz_reg = { + HWSEQ_CZ_REG_LIST() +}; + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), +}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCE11_MASK_SH_LIST(_MASK), +}; + +static struct dce_hwseq *dce110_hwseq_create( + struct dc_context *ctx) +{ + struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + + if (hws) { + hws->ctx = ctx; + hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? + &hwseq_stoney_reg : &hwseq_cz_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + hws->wa.blnd_crtc_trigger = true; + } + return hws; +} + +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = create_audio, + .create_stream_encoder = dce110_stream_encoder_create, + .create_hwseq = dce110_hwseq_create, +}; + +#define mi_inst_regs(id) { \ + MI_REG_LIST(id), \ + .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ +} +static const struct dce_mem_input_registers mi_regs[] = { + mi_inst_regs(0), + mi_inst_regs(1), + mi_inst_regs(2), +}; + +static const struct dce_mem_input_shift mi_shifts = { + MI_DCE_MASK_SH_LIST(__SHIFT), + .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT +}; + +static const struct dce_mem_input_mask mi_masks = { + MI_DCE_MASK_SH_LIST(_MASK), + .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK +}; + +static struct mem_input *dce110_mem_input_create( + struct dc_context *ctx, + uint32_t inst, + const struct dce110_mem_input_reg_offsets *offset) +{ + struct dce110_mem_input *mem_input110 = + dm_alloc(sizeof(struct dce110_mem_input)); + + if (!mem_input110) + return NULL; + + if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) { + struct mem_input *mi = &mem_input110->base; + + mi->regs = &mi_regs[inst]; + mi->shifts = &mi_shifts; + mi->masks = &mi_masks; + mi->wa.single_head_rdreq_dmif_limit = 3; + return mi; + } + + BREAK_TO_DEBUGGER(); + dm_free(mem_input110); + return NULL; +} + +static void dce110_transform_destroy(struct transform **xfm) +{ + dm_free(TO_DCE_TRANSFORM(*xfm)); + *xfm = NULL; +} + +static struct transform *dce110_transform_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce_transform *transform = + dm_alloc(sizeof(struct dce_transform)); + + if (!transform) + return NULL; + + if (dce_transform_construct(transform, ctx, inst, + &xfm_regs[inst], &xfm_shift, &xfm_mask)) + return &transform->base; + + BREAK_TO_DEBUGGER(); + dm_free(transform); + return NULL; +} + +static struct input_pixel_processor *dce110_ipp_create( + struct dc_context *ctx, + uint32_t inst, + const struct dce110_ipp_reg_offsets *offsets) +{ + struct dce110_ipp *ipp = + dm_alloc(sizeof(struct dce110_ipp)); + + if (!ipp) + return NULL; + + if (dce110_ipp_construct(ipp, ctx, inst, offsets)) + return &ipp->base; + + BREAK_TO_DEBUGGER(); + dm_free(ipp); + return NULL; +} + +struct link_encoder *dce110_link_encoder_create( + const struct encoder_init_data *enc_init_data) +{ + struct dce110_link_encoder *enc110 = + dm_alloc(sizeof(struct dce110_link_encoder)); + + if (!enc110) + return NULL; + + if (dce110_link_encoder_construct( + enc110, + enc_init_data, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source])) { + + enc110->base.features.ycbcr420_supported = false; + enc110->base.features.max_hdmi_pixel_clock = 594000; + return &enc110->base; + } + + BREAK_TO_DEBUGGER(); + dm_free(enc110); + return NULL; +} + +static struct output_pixel_processor *dce110_opp_create( + struct dc_context *ctx, + uint32_t inst, + const struct dce110_opp_reg_offsets *offsets) +{ + struct dce110_opp *opp = + dm_alloc(sizeof(struct dce110_opp)); + + if (!opp) + return NULL; + + if (dce110_opp_construct(opp, + ctx, inst, offsets)) + return &opp->base; + + BREAK_TO_DEBUGGER(); + dm_free(opp); + return NULL; +} + +struct clock_source *dce110_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + dm_alloc(sizeof(struct dce110_clk_src)); + + if (!clk_src) + return NULL; + + if (dce110_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + BREAK_TO_DEBUGGER(); + return NULL; +} + +void dce110_clock_source_destroy(struct clock_source **clk_src) +{ + struct dce110_clk_src *dce110_clk_src; + + if (!clk_src) + return; + + dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); + + if (dce110_clk_src->dp_ss_params) + dm_free(dce110_clk_src->dp_ss_params); + + if (dce110_clk_src->hdmi_ss_params) + dm_free(dce110_clk_src->hdmi_ss_params); + + if (dce110_clk_src->dvi_ss_params) + dm_free(dce110_clk_src->dvi_ss_params); + + dm_free(dce110_clk_src); + *clk_src = NULL; +} + +static void destruct(struct dce110_resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->base.pipe_count; i++) { + if (pool->base.opps[i] != NULL) + dce110_opp_destroy(&pool->base.opps[i]); + + if (pool->base.transforms[i] != NULL) + dce110_transform_destroy(&pool->base.transforms[i]); + + if (pool->base.ipps[i] != NULL) + dce110_ipp_destroy(&pool->base.ipps[i]); + + if (pool->base.mis[i] != NULL) { + dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + pool->base.mis[i] = NULL; + } + + if (pool->base.timing_generators[i] != NULL) { + dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + pool->base.timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->base.stream_enc_count; i++) { + if (pool->base.stream_enc[i] != NULL) + dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] != NULL) { + dce110_clock_source_destroy(&pool->base.clock_sources[i]); + } + } + + if (pool->base.dp_clock_source != NULL) + dce110_clock_source_destroy(&pool->base.dp_clock_source); + + for (i = 0; i < pool->base.audio_count; i++) { + if (pool->base.audios[i] != NULL) { + dce_aud_destroy(&pool->base.audios[i]); + } + } + + if (pool->base.display_clock != NULL) { + dal_display_clock_destroy(&pool->base.display_clock); + } + + if (pool->base.irqs != NULL) { + dal_irq_service_destroy(&pool->base.irqs); + } +} + + +static void get_pixel_clock_parameters( + const struct pipe_ctx *pipe_ctx, + struct pixel_clk_params *pixel_clk_params) +{ + const struct core_stream *stream = pipe_ctx->stream; + + /*TODO: is this halved for YCbCr 420? in that case we might want to move + * the pixel clock normalization for hdmi up to here instead of doing it + * in pll_adjust_pix_clk + */ + pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; + pixel_clk_params->signal_type = pipe_ctx->stream->signal; + pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; + /* TODO: un-hardcode*/ + pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * + LINK_RATE_REF_FREQ_IN_KHZ; + pixel_clk_params->flags.ENABLE_SS = 0; + pixel_clk_params->color_depth = + stream->public.timing.display_color_depth; + pixel_clk_params->flags.DISPLAY_BLANKED = 1; + pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding == + PIXEL_ENCODING_YCBCR420); +} + +void dce110_resource_build_bit_depth_reduction_params( + const struct core_stream *stream, + struct bit_depth_reduction_params *fmt_bit_depth) +{ + memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); + + /*TODO: Need to un-hardcode, refer to function with same name + * in dal2 hw_sequencer*/ + + fmt_bit_depth->flags.TRUNCATE_ENABLED = 0; + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 0; + fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 0; + + /* Diagnostics need consistent CRC of the image, that means + * dithering should not be enabled for Diagnostics. */ + if (IS_DIAG_DC(stream->ctx->dce_environment) == false) { + switch (stream->public.timing.display_color_depth) { + case COLOR_DEPTH_666: + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; + break; + case COLOR_DEPTH_888: + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; + break; + case COLOR_DEPTH_101010: + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; + break; + default: + break; + } + fmt_bit_depth->flags.RGB_RANDOM = 1; + fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; + fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; + fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; + } + + return; +} + +enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) +{ + get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); + pipe_ctx->clock_source->funcs->get_pix_clk_dividers( + pipe_ctx->clock_source, + &pipe_ctx->pix_clk_params, + &pipe_ctx->pll_settings); + dce110_resource_build_bit_depth_reduction_params(pipe_ctx->stream, + &pipe_ctx->stream->bit_depth_params); + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + + return DC_OK; +} + +static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) +{ + if (pipe_ctx->pipe_idx != underlay_idx) + return true; + if (!pipe_ctx->surface) + return false; + if (pipe_ctx->surface->public.format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + return false; + return true; +} + +static enum dc_status validate_mapped_resource( + const struct core_dc *dc, + struct validate_context *context) +{ + enum dc_status status = DC_OK; + uint8_t i, j, k; + + for (i = 0; i < context->target_count; i++) { + struct core_target *target = context->targets[i]; + + for (j = 0; j < target->public.stream_count; j++) { + struct core_stream *stream = + DC_STREAM_TO_CORE(target->public.streams[j]); + struct core_link *link = stream->sink->link; + + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; + + for (k = 0; k < MAX_PIPES; k++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[k]; + + if (context->res_ctx.pipe_ctx[k].stream != stream) + continue; + + if (!is_surface_pixel_format_supported(pipe_ctx, + context->res_ctx.pool->underlay_pipe_index)) + return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; + + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; + + status = dce110_resource_build_pipe_hw_param(pipe_ctx); + + if (status != DC_OK) + return status; + + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; + + /* TODO: validate audio ASIC caps, encoder */ + + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); + + if (status != DC_OK) + return status; + + resource_build_info_frame(pipe_ctx); + + /* do not need to validate non root pipes */ + break; + } + } + } + + return DC_OK; +} + +enum dc_status dce110_validate_bandwidth( + const struct core_dc *dc, + struct validate_context *context) +{ + enum dc_status result = DC_ERROR_UNEXPECTED; + + dm_logger_write( + dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "%s: start", + __func__); + + if (!bw_calcs( + dc->ctx, + &dc->bw_dceip, + &dc->bw_vbios, + context->res_ctx.pipe_ctx, + context->res_ctx.pool->pipe_count, + &context->bw_results)) + result = DC_FAIL_BANDWIDTH_VALIDATE; + else + result = DC_OK; + + if (result == DC_FAIL_BANDWIDTH_VALIDATE) + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, + "%s: %dx%d@%d Bandwidth validation failed!\n", + __func__, + context->targets[0]->public.streams[0]->timing.h_addressable, + context->targets[0]->public.streams[0]->timing.v_addressable, + context->targets[0]->public.streams[0]->timing.pix_clk_khz); + + if (memcmp(&dc->current_context->bw_results, + &context->bw_results, sizeof(context->bw_results))) { + struct log_entry log_entry; + dm_logger_open( + dc->ctx->logger, + &log_entry, + LOG_BANDWIDTH_CALCS); + dm_logger_append(&log_entry, "%s: finish,\n" + "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" + "stutMark_b: %d stutMark_a: %d\n", + __func__, + context->bw_results.nbp_state_change_wm_ns[0].b_mark, + context->bw_results.nbp_state_change_wm_ns[0].a_mark, + context->bw_results.urgent_wm_ns[0].b_mark, + context->bw_results.urgent_wm_ns[0].a_mark, + context->bw_results.stutter_exit_wm_ns[0].b_mark, + context->bw_results.stutter_exit_wm_ns[0].a_mark); + dm_logger_append(&log_entry, + "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" + "stutMark_b: %d stutMark_a: %d\n", + context->bw_results.nbp_state_change_wm_ns[1].b_mark, + context->bw_results.nbp_state_change_wm_ns[1].a_mark, + context->bw_results.urgent_wm_ns[1].b_mark, + context->bw_results.urgent_wm_ns[1].a_mark, + context->bw_results.stutter_exit_wm_ns[1].b_mark, + context->bw_results.stutter_exit_wm_ns[1].a_mark); + dm_logger_append(&log_entry, + "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" + "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", + context->bw_results.nbp_state_change_wm_ns[2].b_mark, + context->bw_results.nbp_state_change_wm_ns[2].a_mark, + context->bw_results.urgent_wm_ns[2].b_mark, + context->bw_results.urgent_wm_ns[2].a_mark, + context->bw_results.stutter_exit_wm_ns[2].b_mark, + context->bw_results.stutter_exit_wm_ns[2].a_mark, + context->bw_results.stutter_mode_enable); + dm_logger_append(&log_entry, + "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" + "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", + context->bw_results.cpuc_state_change_enable, + context->bw_results.cpup_state_change_enable, + context->bw_results.nbp_state_change_enable, + context->bw_results.all_displays_in_sync, + context->bw_results.dispclk_khz, + context->bw_results.required_sclk, + context->bw_results.required_sclk_deep_sleep, + context->bw_results.required_yclk, + context->bw_results.blackout_recovery_time_us); + dm_logger_close(&log_entry); + } + return result; +} + +static bool dce110_validate_surface_sets( + const struct dc_validation_set set[], + int set_count) +{ + int i; + + for (i = 0; i < set_count; i++) { + if (set[i].surface_count == 0) + continue; + + if (set[i].surface_count > 2) + return false; + + if (set[i].surfaces[0]->src_rect.width + != set[i].target->streams[0]->src.width + || set[i].surfaces[0]->src_rect.height + != set[i].target->streams[0]->src.height) + return false; + if (set[i].surfaces[0]->format + >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + return false; + + if (set[i].surface_count == 2) { + if (set[i].surfaces[1]->format + < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + return false; + if (set[i].surfaces[1]->src_rect.width > 1920 + || set[i].surfaces[1]->src_rect.height > 1080) + return false; + + if (set[i].target->streams[0]->timing.pixel_encoding != PIXEL_ENCODING_RGB) + return false; + } + } + + return true; +} + +enum dc_status dce110_validate_with_context( + const struct core_dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *context) +{ + struct dc_context *dc_ctx = dc->ctx; + enum dc_status result = DC_ERROR_UNEXPECTED; + int i; + + if (!dce110_validate_surface_sets(set, set_count)) + return DC_FAIL_SURFACE_VALIDATE; + + context->res_ctx.pool = dc->res_pool; + + for (i = 0; i < set_count; i++) { + context->targets[i] = DC_TARGET_TO_CORE(set[i].target); + dc_target_retain(&context->targets[i]->public); + context->target_count++; + } + + result = resource_map_pool_resources(dc, context); + + if (result == DC_OK) + result = resource_map_clock_resources(dc, context); + + if (!resource_validate_attach_surfaces( + set, set_count, dc->current_context, context)) { + DC_ERROR("Failed to attach surface to target!\n"); + return DC_FAIL_ATTACH_SURFACES; + } + + if (result == DC_OK) + result = validate_mapped_resource(dc, context); + + if (result == DC_OK) + result = resource_build_scaling_params_for_context(dc, context); + + if (result == DC_OK) + result = dce110_validate_bandwidth(dc, context); + + return result; +} + +enum dc_status dce110_validate_guaranteed( + const struct core_dc *dc, + const struct dc_target *dc_target, + struct validate_context *context) +{ + enum dc_status result = DC_ERROR_UNEXPECTED; + + context->res_ctx.pool = dc->res_pool; + + context->targets[0] = DC_TARGET_TO_CORE(dc_target); + dc_target_retain(&context->targets[0]->public); + context->target_count++; + + result = resource_map_pool_resources(dc, context); + + if (result == DC_OK) + result = resource_map_clock_resources(dc, context); + + if (result == DC_OK) + result = validate_mapped_resource(dc, context); + + if (result == DC_OK) { + validate_guaranteed_copy_target( + context, dc->public.caps.max_targets); + result = resource_build_scaling_params_for_context(dc, context); + } + + if (result == DC_OK) + result = dce110_validate_bandwidth(dc, context); + + return result; +} + +static struct pipe_ctx *dce110_acquire_idle_pipe_for_layer( + struct resource_context *res_ctx, + struct core_stream *stream) +{ + unsigned int underlay_idx = res_ctx->pool->underlay_pipe_index; + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; + + if (res_ctx->pipe_ctx[underlay_idx].stream) { + return NULL; + } + + pipe_ctx->tg = res_ctx->pool->timing_generators[underlay_idx]; + pipe_ctx->mi = res_ctx->pool->mis[underlay_idx]; + /*pipe_ctx->ipp = res_ctx->pool->ipps[underlay_idx];*/ + pipe_ctx->xfm = res_ctx->pool->transforms[underlay_idx]; + pipe_ctx->opp = res_ctx->pool->opps[underlay_idx]; + pipe_ctx->dis_clk = res_ctx->pool->display_clock; + pipe_ctx->pipe_idx = underlay_idx; + + pipe_ctx->stream = stream; + + return pipe_ctx; + +} + +static void dce110_destroy_resource_pool(struct resource_pool **pool) +{ + struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); + + destruct(dce110_pool); + dm_free(dce110_pool); + *pool = NULL; +} + + +static const struct resource_funcs dce110_res_pool_funcs = { + .destroy = dce110_destroy_resource_pool, + .link_enc_create = dce110_link_encoder_create, + .validate_with_context = dce110_validate_with_context, + .validate_guaranteed = dce110_validate_guaranteed, + .validate_bandwidth = dce110_validate_bandwidth, + .acquire_idle_pipe_for_layer = dce110_acquire_idle_pipe_for_layer, + .build_bit_depth_reduction_params = + dce110_resource_build_bit_depth_reduction_params +}; + +static void underlay_create(struct dc_context *ctx, struct resource_pool *pool) +{ + struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); + struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); + struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); + struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); + + dce110_opp_v_construct(dce110_oppv, ctx); + dce110_timing_generator_v_construct(dce110_tgv, ctx); + dce110_mem_input_v_construct(dce110_miv, ctx); + dce110_transform_v_construct(dce110_xfmv, ctx); + + pool->opps[pool->pipe_count] = &dce110_oppv->base; + pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; + pool->mis[pool->pipe_count] = &dce110_miv->base; + pool->transforms[pool->pipe_count] = &dce110_xfmv->base; + pool->pipe_count++; + + /* update the public caps to indicate an underlay is available */ + ctx->dc->caps.max_slave_planes = 1; + ctx->dc->caps.max_slave_planes = 1; +} + +static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +{ + struct dm_pp_clock_levels clks = {0}; + + /*do system clock*/ + dm_pp_get_clock_levels_by_type( + dc->ctx, + DM_PP_CLOCK_TYPE_ENGINE_CLK, + &clks); + /* convert all the clock fro kHz to fix point mHz */ + dc->bw_vbios.high_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1], 1000); + dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels/8], 1000); + dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*2/8], 1000); + dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*3/8], 1000); + dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*4/8], 1000); + dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*5/8], 1000); + dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*6/8], 1000); + dc->bw_vbios.low_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[0], 1000); + dc->sclk_lvls = clks; + + /*do display clock*/ + dm_pp_get_clock_levels_by_type( + dc->ctx, + DM_PP_CLOCK_TYPE_DISPLAY_CLK, + &clks); + dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1], 1000); + dc->bw_vbios.mid_voltage_max_dispclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels>>1], 1000); + dc->bw_vbios.low_voltage_max_dispclk = bw_frc_to_fixed( + clks.clocks_in_khz[0], 1000); + + /*do memory clock*/ + dm_pp_get_clock_levels_by_type( + dc->ctx, + DM_PP_CLOCK_TYPE_MEMORY_CLK, + &clks); + + dc->bw_vbios.low_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); + dc->bw_vbios.mid_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, + 1000); + dc->bw_vbios.high_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, + 1000); +} + +enum clocks_state dce110_resource_convert_clock_state_pp_to_dc( + enum dm_pp_clocks_state pp_clock_state) +{ + enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID; + + switch (pp_clock_state) { + case DM_PP_CLOCKS_STATE_INVALID: + dc_clocks_state = CLOCKS_STATE_INVALID; + break; + case DM_PP_CLOCKS_STATE_ULTRA_LOW: + dc_clocks_state = CLOCKS_STATE_ULTRA_LOW; + break; + case DM_PP_CLOCKS_STATE_LOW: + dc_clocks_state = CLOCKS_STATE_LOW; + break; + case DM_PP_CLOCKS_STATE_NOMINAL: + dc_clocks_state = CLOCKS_STATE_NOMINAL; + break; + case DM_PP_CLOCKS_STATE_PERFORMANCE: + dc_clocks_state = CLOCKS_STATE_PERFORMANCE; + break; + case DM_PP_CLOCKS_DPM_STATE_LEVEL_4: + dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4; + break; + case DM_PP_CLOCKS_DPM_STATE_LEVEL_5: + dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5; + break; + case DM_PP_CLOCKS_DPM_STATE_LEVEL_6: + dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6; + break; + case DM_PP_CLOCKS_DPM_STATE_LEVEL_7: + dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7; + break; + default: + dc_clocks_state = CLOCKS_STATE_INVALID; + break; + } + + return dc_clocks_state; +} + +const struct resource_caps *dce110_resource_cap( + struct hw_asic_id *asic_id) +{ + if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) + return &stoney_resource_cap; + else + return &carrizo_resource_cap; +} + +static bool construct( + uint8_t num_virtual_links, + struct core_dc *dc, + struct dce110_resource_pool *pool, + struct hw_asic_id asic_id) +{ + unsigned int i; + struct dc_context *ctx = dc->ctx; + struct firmware_info info; + struct dc_bios *bp; + struct dm_pp_static_clock_info static_clk_info = {0}; + + ctx->dc_bios->regs = &bios_regs; + + pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); + pool->base.funcs = &dce110_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + + pool->base.pipe_count = pool->base.res_cap->num_timing_generator; + pool->base.underlay_pipe_index = pool->base.pipe_count; + + dc->public.caps.max_downscale_ratio = 150; + dc->public.caps.i2c_speed_in_khz = 100; + + /************************************************* + * Create resources * + *************************************************/ + + bp = ctx->dc_bios; + + if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && + info.external_clock_source_frequency_for_dp != 0) { + pool->base.dp_clock_source = + dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); + + pool->base.clock_sources[0] = + dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, + &clk_src_regs[0], false); + pool->base.clock_sources[1] = + dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, + &clk_src_regs[1], false); + + pool->base.clk_src_count = 2; + + /* TODO: find out if CZ support 3 PLLs */ + } + + if (pool->base.dp_clock_source == NULL) { + dm_error("DC: failed to create dp clock source!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } + } + + pool->base.display_clock = dal_display_clock_dce110_create(ctx); + if (pool->base.display_clock == NULL) { + dm_error("DC: failed to create display clock!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } + + /* get static clock information for PPLIB or firmware, save + * max_clock_state + */ + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) { + enum clocks_state max_clocks_state = + dce110_resource_convert_clock_state_pp_to_dc( + static_clk_info.max_clocks_state); + + dal_display_clock_store_max_clocks_state( + pool->base.display_clock, max_clocks_state); + } + + { + struct irq_service_init_data init_data; + init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dce110_create(&init_data); + if (!pool->base.irqs) + goto res_create_fail; + } + + for (i = 0; i < pool->base.pipe_count; i++) { + pool->base.timing_generators[i] = dce110_timing_generator_create( + ctx, i, &dce110_tg_offsets[i]); + if (pool->base.timing_generators[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto res_create_fail; + } + + pool->base.mis[i] = dce110_mem_input_create(ctx, i, + &dce110_mi_reg_offsets[i]); + if (pool->base.mis[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create memory input!\n"); + goto res_create_fail; + } + + pool->base.ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]); + if (pool->base.ipps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create input pixel processor!\n"); + goto res_create_fail; + } + + pool->base.transforms[i] = dce110_transform_create(ctx, i); + if (pool->base.transforms[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create transform!\n"); + goto res_create_fail; + } + + pool->base.opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]); + if (pool->base.opps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create output pixel processor!\n"); + goto res_create_fail; + } + } + + underlay_create(ctx, &pool->base); + + if (!resource_construct(num_virtual_links, dc, &pool->base, + &res_create_funcs)) + goto res_create_fail; + + /* Create hardware sequencer */ + if (!dce110_hw_sequencer_construct(dc)) + goto res_create_fail; + + if (ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev)) + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_STONEY); + else + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO); + + bw_calcs_data_update_from_pplib(dc); + + return true; + +res_create_fail: + destruct(pool); + return false; +} + +struct resource_pool *dce110_create_resource_pool( + uint8_t num_virtual_links, + struct core_dc *dc, + struct hw_asic_id asic_id) +{ + struct dce110_resource_pool *pool = + dm_alloc(sizeof(struct dce110_resource_pool)); + + if (!pool) + return NULL; + + if (construct(num_virtual_links, dc, pool, asic_id)) + return &pool->base; + + BREAK_TO_DEBUGGER(); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h new file mode 100644 index 000000000000..535623aa0052 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -0,0 +1,56 @@ +/* +* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_RESOURCE_DCE110_H__ +#define __DC_RESOURCE_DCE110_H__ + +#include "core_types.h" + +struct core_dc; +struct resource_pool; + +#define TO_DCE110_RES_POOL(pool)\ + container_of(pool, struct dce110_resource_pool, base) + +struct dce110_resource_pool { + struct resource_pool base; +}; + +enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); + +enum clocks_state dce110_resource_convert_clock_state_pp_to_dc( + enum dm_pp_clocks_state pp_clock_state); + +void dce110_resource_build_bit_depth_reduction_params( + const struct core_stream *stream, + struct bit_depth_reduction_params *fmt_bit_depth); + +struct resource_pool *dce110_create_resource_pool( + uint8_t num_virtual_links, + struct core_dc *dc, + struct hw_asic_id asic_id); + +#endif /* __DC_RESOURCE_DCE110_H__ */ + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c new file mode 100644 index 000000000000..b1c97125f6fb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -0,0 +1,1953 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dc_types.h" +#include "dc_bios_types.h" +#include "dc.h" + +#include "include/grph_object_id.h" +#include "include/logger_interface.h" +#include "dce110_timing_generator.h" + +#include "timing_generator.h" + + +#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10 + +#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1) +#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1) + +#define CRTC_REG(reg) (reg + tg110->offsets.crtc) +#define DCP_REG(reg) (reg + tg110->offsets.dcp) + +/* Flowing register offsets are same in files of + * dce/dce_11_0_d.h + * dce/vi_polaris10_p/vi_polaris10_d.h + * + * So we can create dce110 timing generator to use it. + */ + + +/* +* apply_front_porch_workaround +* +* This is a workaround for a bug that has existed since R5xx and has not been +* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. +*/ +static void dce110_timing_generator_apply_front_porch_workaround( + struct timing_generator *tg, + struct dc_crtc_timing *timing) +{ + if (timing->flags.INTERLACE == 1) { + if (timing->v_front_porch < 2) + timing->v_front_porch = 2; + } else { + if (timing->v_front_porch < 1) + timing->v_front_porch = 1; + } +} + +/** + ***************************************************************************** + * Function: is_in_vertical_blank + * + * @brief + * check the current status of CRTC to check if we are in Vertical Blank + * regioneased" state + * + * @return + * true if currently in blank region, false otherwise + * + ***************************************************************************** + */ +static bool dce110_timing_generator_is_in_vertical_blank( + struct timing_generator *tg) +{ + uint32_t addr = 0; + uint32_t value = 0; + uint32_t field = 0; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + addr = CRTC_REG(mmCRTC_STATUS); + value = dm_read_reg(tg->ctx, addr); + field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); + return field == 1; +} + +void dce110_timing_generator_set_early_control( + struct timing_generator *tg, + uint32_t early_cntl) +{ + uint32_t regval; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t address = CRTC_REG(mmCRTC_CONTROL); + + regval = dm_read_reg(tg->ctx, address); + set_reg_field_value(regval, early_cntl, + CRTC_CONTROL, CRTC_HBLANK_EARLY_CONTROL); + dm_write_reg(tg->ctx, address, regval); +} + +/** + * Enable CRTC + * Enable CRTC - call ASIC Control Object to enable Timing generator. + */ +bool dce110_timing_generator_enable_crtc(struct timing_generator *tg) +{ + enum bp_result result; + + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t value = 0; + + /* + * 3 is used to make sure V_UPDATE occurs at the beginning of the first + * line of vertical front porch + */ + set_reg_field_value( + value, + 0, + CRTC_MASTER_UPDATE_MODE, + MASTER_UPDATE_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); + + /* TODO: may want this on to catch underflow */ + value = 0; + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); + + result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true); + + return result == BP_RESULT_OK; +} + +void dce110_timing_generator_program_blank_color( + struct timing_generator *tg, + const struct tg_color *black_color) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR); + uint32_t value = dm_read_reg(tg->ctx, addr); + + set_reg_field_value( + value, + black_color->color_b_cb, + CRTC_BLACK_COLOR, + CRTC_BLACK_COLOR_B_CB); + set_reg_field_value( + value, + black_color->color_g_y, + CRTC_BLACK_COLOR, + CRTC_BLACK_COLOR_G_Y); + set_reg_field_value( + value, + black_color->color_r_cr, + CRTC_BLACK_COLOR, + CRTC_BLACK_COLOR_R_CR); + + dm_write_reg(tg->ctx, addr, value); +} + +/** + ***************************************************************************** + * Function: disable_stereo + * + * @brief + * Disables active stereo on controller + * Frame Packing need to be disabled in vBlank or when CRTC not running + ***************************************************************************** + */ +#if 0 +@TODOSTEREO +static void disable_stereo(struct timing_generator *tg) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL); + uint32_t value = 0; + uint32_t test = 0; + uint32_t field = 0; + uint32_t struc_en = 0; + uint32_t struc_stereo_sel_ovr = 0; + + value = dm_read_reg(tg->ctx, addr); + struc_en = get_reg_field_value( + value, + CRTC_3D_STRUCTURE_CONTROL, + CRTC_3D_STRUCTURE_EN); + + struc_stereo_sel_ovr = get_reg_field_value( + value, + CRTC_3D_STRUCTURE_CONTROL, + CRTC_3D_STRUCTURE_STEREO_SEL_OVR); + + /* + * When disabling Frame Packing in 2 step mode, we need to program both + * registers at the same frame + * Programming it in the beginning of VActive makes sure we are ok + */ + + if (struc_en != 0 && struc_stereo_sel_ovr == 0) { + tg->funcs->wait_for_vblank(tg); + tg->funcs->wait_for_vactive(tg); + } + + value = 0; + dm_write_reg(tg->ctx, addr, value); + + addr = tg->regs[IDX_CRTC_STEREO_CONTROL]; + dm_write_reg(tg->ctx, addr, value); +} +#endif + +/** + * disable_crtc - call ASIC Control Object to disable Timing generator. + */ +bool dce110_timing_generator_disable_crtc(struct timing_generator *tg) +{ + enum bp_result result; + + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false); + + /* Need to make sure stereo is disabled according to the DCE5.0 spec */ + + /* + * @TODOSTEREO call this when adding stereo support + * tg->funcs->disable_stereo(tg); + */ + + return result == BP_RESULT_OK; +} + +/** +* program_horz_count_by_2 +* Programs DxCRTC_HORZ_COUNT_BY2_EN - 1 for DVI 30bpp mode, 0 otherwise +* +*/ +static void program_horz_count_by_2( + struct timing_generator *tg, + const struct dc_crtc_timing *timing) +{ + uint32_t regval; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + regval = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_COUNT_CONTROL)); + + set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL, + CRTC_HORZ_COUNT_BY2_EN); + + if (timing->flags.HORZ_COUNT_BY_TWO) + set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL, + CRTC_HORZ_COUNT_BY2_EN); + + dm_write_reg(tg->ctx, + CRTC_REG(mmCRTC_COUNT_CONTROL), regval); +} + +/** + * program_timing_generator + * Program CRTC Timing Registers - DxCRTC_H_*, DxCRTC_V_*, Pixel repetition. + * Call ASIC Control Object to program Timings. + */ +bool dce110_timing_generator_program_timing_generator( + struct timing_generator *tg, + const struct dc_crtc_timing *dc_crtc_timing) +{ + enum bp_result result; + struct bp_hw_crtc_timing_parameters bp_params; + struct dc_crtc_timing patched_crtc_timing; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + uint32_t vsync_offset = dc_crtc_timing->v_border_bottom + + dc_crtc_timing->v_front_porch; + uint32_t v_sync_start =dc_crtc_timing->v_addressable + vsync_offset; + + uint32_t hsync_offset = dc_crtc_timing->h_border_right + + dc_crtc_timing->h_front_porch; + uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset; + + memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters)); + + /* Due to an asic bug we need to apply the Front Porch workaround prior + * to programming the timing. + */ + + patched_crtc_timing = *dc_crtc_timing; + + dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing); + + bp_params.controller_id = tg110->controller_id; + + bp_params.h_total = patched_crtc_timing.h_total; + bp_params.h_addressable = + patched_crtc_timing.h_addressable; + bp_params.v_total = patched_crtc_timing.v_total; + bp_params.v_addressable = patched_crtc_timing.v_addressable; + + bp_params.h_sync_start = h_sync_start; + bp_params.h_sync_width = patched_crtc_timing.h_sync_width; + bp_params.v_sync_start = v_sync_start; + bp_params.v_sync_width = patched_crtc_timing.v_sync_width; + + /* Set overscan */ + bp_params.h_overscan_left = + patched_crtc_timing.h_border_left; + bp_params.h_overscan_right = + patched_crtc_timing.h_border_right; + bp_params.v_overscan_top = patched_crtc_timing.v_border_top; + bp_params.v_overscan_bottom = + patched_crtc_timing.v_border_bottom; + + /* Set flags */ + if (patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY == 1) + bp_params.flags.HSYNC_POSITIVE_POLARITY = 1; + + if (patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY == 1) + bp_params.flags.VSYNC_POSITIVE_POLARITY = 1; + + if (patched_crtc_timing.flags.INTERLACE == 1) + bp_params.flags.INTERLACE = 1; + + if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1) + bp_params.flags.HORZ_COUNT_BY_TWO = 1; + + result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params); + + program_horz_count_by_2(tg, &patched_crtc_timing); + + tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing); + + /* Enable stereo - only when we need to pack 3D frame. Other types + * of stereo handled in explicit call */ + + return result == BP_RESULT_OK; +} + +/** + ***************************************************************************** + * Function: set_drr + * + * @brief + * Program dynamic refresh rate registers m_DxCRTC_V_TOTAL_*. + * + * @param [in] pHwCrtcTiming: point to H + * wCrtcTiming struct + ***************************************************************************** + */ +void dce110_timing_generator_set_drr( + struct timing_generator *tg, + const struct drr_params *params) +{ + /* register values */ + uint32_t v_total_min = 0; + uint32_t v_total_max = 0; + uint32_t v_total_cntl = 0; + uint32_t static_screen_cntl = 0; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + uint32_t addr = 0; + + addr = CRTC_REG(mmCRTC_V_TOTAL_MIN); + v_total_min = dm_read_reg(tg->ctx, addr); + + addr = CRTC_REG(mmCRTC_V_TOTAL_MAX); + v_total_max = dm_read_reg(tg->ctx, addr); + + addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL); + v_total_cntl = dm_read_reg(tg->ctx, addr); + + addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); + static_screen_cntl = dm_read_reg(tg->ctx, addr); + + if (params != NULL && + params->vertical_total_max > 0 && + params->vertical_total_min > 0) { + + set_reg_field_value(v_total_max, + params->vertical_total_max - 1, + CRTC_V_TOTAL_MAX, + CRTC_V_TOTAL_MAX); + + set_reg_field_value(v_total_min, + params->vertical_total_min - 1, + CRTC_V_TOTAL_MIN, + CRTC_V_TOTAL_MIN); + + set_reg_field_value(v_total_cntl, + 1, + CRTC_V_TOTAL_CONTROL, + CRTC_V_TOTAL_MIN_SEL); + + set_reg_field_value(v_total_cntl, + 1, + CRTC_V_TOTAL_CONTROL, + CRTC_V_TOTAL_MAX_SEL); + + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_FORCE_LOCK_ON_EVENT); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_FORCE_LOCK_TO_MASTER_VSYNC); + + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_SET_V_TOTAL_MIN_MASK_EN); + + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_SET_V_TOTAL_MIN_MASK); + + set_reg_field_value(static_screen_cntl, + 0x180, + CRTC_STATIC_SCREEN_CONTROL, + CRTC_STATIC_SCREEN_EVENT_MASK); + } else { + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_SET_V_TOTAL_MIN_MASK); + set_reg_field_value(static_screen_cntl, + 0, + CRTC_STATIC_SCREEN_CONTROL, + CRTC_STATIC_SCREEN_EVENT_MASK); + set_reg_field_value(v_total_min, + 0, + CRTC_V_TOTAL_MIN, + CRTC_V_TOTAL_MIN); + set_reg_field_value(v_total_max, + 0, + CRTC_V_TOTAL_MAX, + CRTC_V_TOTAL_MAX); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_V_TOTAL_MIN_SEL); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_V_TOTAL_MAX_SEL); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_FORCE_LOCK_ON_EVENT); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_FORCE_LOCK_TO_MASTER_VSYNC); + } + + addr = CRTC_REG(mmCRTC_V_TOTAL_MIN); + dm_write_reg(tg->ctx, addr, v_total_min); + + addr = CRTC_REG(mmCRTC_V_TOTAL_MAX); + dm_write_reg(tg->ctx, addr, v_total_max); + + addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL); + dm_write_reg(tg->ctx, addr, v_total_cntl); + + addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); + dm_write_reg(tg->ctx, addr, static_screen_cntl); +} + +void dce110_timing_generator_set_static_screen_control( + struct timing_generator *tg, + uint32_t value) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t static_screen_cntl = 0; + uint32_t addr = 0; + + addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); + static_screen_cntl = dm_read_reg(tg->ctx, addr); + + set_reg_field_value(static_screen_cntl, + value, + CRTC_STATIC_SCREEN_CONTROL, + CRTC_STATIC_SCREEN_EVENT_MASK); + + set_reg_field_value(static_screen_cntl, + 2, + CRTC_STATIC_SCREEN_CONTROL, + CRTC_STATIC_SCREEN_FRAME_COUNT); + + dm_write_reg(tg->ctx, addr, static_screen_cntl); +} + +/* + * get_vblank_counter + * + * @brief + * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which + * holds the counter of frames. + * + * @param + * struct timing_generator *tg - [in] timing generator which controls the + * desired CRTC + * + * @return + * Counter of frames, which should equal to number of vblanks. + */ +uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT); + uint32_t value = dm_read_reg(tg->ctx, addr); + uint32_t field = get_reg_field_value( + value, CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT); + + return field; +} + +/** + ***************************************************************************** + * Function: dce110_get_crtc_positions + * + * @brief + * Returns CRTC vertical/horizontal counters + * + * @param [out] v_position, h_position + ***************************************************************************** + */ + +void dce110_timing_generator_get_crtc_positions( + struct timing_generator *tg, + int32_t *h_position, + int32_t *v_position) +{ + uint32_t value; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION)); + + *h_position = get_reg_field_value( + value, + CRTC_STATUS_POSITION, + CRTC_HORZ_COUNT); + + *v_position = get_reg_field_value( + value, + CRTC_STATUS_POSITION, + CRTC_VERT_COUNT); +} + +/** + ***************************************************************************** + * Function: get_crtc_scanoutpos + * + * @brief + * Returns CRTC vertical/horizontal counters + * + * @param [out] vpos, hpos + ***************************************************************************** + */ +uint32_t dce110_timing_generator_get_crtc_scanoutpos( + struct timing_generator *tg, + uint32_t *vbl, + uint32_t *position) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + /* TODO 1: Update the implementation once caller is updated + * WARNING!! This function is returning the whole register value + * because the caller is expecting it instead of proper vertical and + * horizontal position. This should be a temporary implementation + * until the caller is updated. */ + + /* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */ + + *vbl = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_V_BLANK_START_END)); + + *position = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_STATUS_POSITION)); + + /* @TODO: return value should indicate if current + * crtc is inside vblank*/ + return 0; +} + +/* TODO: is it safe to assume that mask/shift of Primary and Underlay + * are the same? + * For example: today CRTC_H_TOTAL == CRTCV_H_TOTAL but is it always + * guaranteed? */ +void dce110_timing_generator_program_blanking( + struct timing_generator *tg, + const struct dc_crtc_timing *timing) +{ + uint32_t vsync_offset = timing->v_border_bottom + + timing->v_front_porch; + uint32_t v_sync_start =timing->v_addressable + vsync_offset; + + uint32_t hsync_offset = timing->h_border_right + + timing->h_front_porch; + uint32_t h_sync_start = timing->h_addressable + hsync_offset; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + struct dc_context *ctx = tg->ctx; + uint32_t value = 0; + uint32_t addr = 0; + uint32_t tmp = 0; + + addr = CRTC_REG(mmCRTC_H_TOTAL); + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->h_total - 1, + CRTC_H_TOTAL, + CRTC_H_TOTAL); + dm_write_reg(ctx, addr, value); + + addr = CRTC_REG(mmCRTC_V_TOTAL); + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->v_total - 1, + CRTC_V_TOTAL, + CRTC_V_TOTAL); + dm_write_reg(ctx, addr, value); + + addr = CRTC_REG(mmCRTC_H_BLANK_START_END); + value = dm_read_reg(ctx, addr); + + tmp = timing->h_total - + (h_sync_start + timing->h_border_left); + + set_reg_field_value( + value, + tmp, + CRTC_H_BLANK_START_END, + CRTC_H_BLANK_END); + + tmp = tmp + timing->h_addressable + + timing->h_border_left + timing->h_border_right; + + set_reg_field_value( + value, + tmp, + CRTC_H_BLANK_START_END, + CRTC_H_BLANK_START); + + dm_write_reg(ctx, addr, value); + + addr = CRTC_REG(mmCRTC_V_BLANK_START_END); + value = dm_read_reg(ctx, addr); + + tmp = timing->v_total - (v_sync_start + timing->v_border_top); + + set_reg_field_value( + value, + tmp, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_END); + + tmp = tmp + timing->v_addressable + timing->v_border_top + + timing->v_border_bottom; + + set_reg_field_value( + value, + tmp, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + + dm_write_reg(ctx, addr, value); +} + +void dce110_timing_generator_set_test_pattern( + struct timing_generator *tg, + /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' + * because this is not DP-specific (which is probably somewhere in DP + * encoder) */ + enum controller_dp_test_pattern test_pattern, + enum dc_color_depth color_depth) +{ + struct dc_context *ctx = tg->ctx; + uint32_t value; + uint32_t addr; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + enum test_pattern_color_format bit_depth; + enum test_pattern_dyn_range dyn_range; + enum test_pattern_mode mode; + /* color ramp generator mixes 16-bits color */ + uint32_t src_bpc = 16; + /* requested bpc */ + uint32_t dst_bpc; + uint32_t index; + /* RGB values of the color bars. + * Produce two RGB colors: RGB0 - white (all Fs) + * and RGB1 - black (all 0s) + * (three RGB components for two colors) + */ + uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, + 0x0000, 0x0000}; + /* dest color (converted to the specified color format) */ + uint16_t dst_color[6]; + uint32_t inc_base; + + /* translate to bit depth */ + switch (color_depth) { + case COLOR_DEPTH_666: + bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; + break; + case COLOR_DEPTH_888: + bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; + break; + case COLOR_DEPTH_101010: + bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; + break; + case COLOR_DEPTH_121212: + bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; + break; + default: + bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; + break; + } + + switch (test_pattern) { + case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: + case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: + { + dyn_range = (test_pattern == + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? + TEST_PATTERN_DYN_RANGE_CEA : + TEST_PATTERN_DYN_RANGE_VESA); + mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; + value = 0; + addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS); + + set_reg_field_value( + value, + 6, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_VRES); + set_reg_field_value( + value, + 6, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_HRES); + + dm_write_reg(ctx, addr, value); + + addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL); + value = 0; + + set_reg_field_value( + value, + 1, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_EN); + + set_reg_field_value( + value, + mode, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_MODE); + + set_reg_field_value( + value, + dyn_range, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_DYNAMIC_RANGE); + set_reg_field_value( + value, + bit_depth, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_COLOR_FORMAT); + dm_write_reg(ctx, addr, value); + } + break; + + case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: + case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: + { + mode = (test_pattern == + CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? + TEST_PATTERN_MODE_VERTICALBARS : + TEST_PATTERN_MODE_HORIZONTALBARS); + + switch (bit_depth) { + case TEST_PATTERN_COLOR_FORMAT_BPC_6: + dst_bpc = 6; + break; + case TEST_PATTERN_COLOR_FORMAT_BPC_8: + dst_bpc = 8; + break; + case TEST_PATTERN_COLOR_FORMAT_BPC_10: + dst_bpc = 10; + break; + default: + dst_bpc = 8; + break; + } + + /* adjust color to the required colorFormat */ + for (index = 0; index < 6; index++) { + /* dst = 2^dstBpc * src / 2^srcBpc = src >> + * (srcBpc - dstBpc); + */ + dst_color[index] = + src_color[index] >> (src_bpc - dst_bpc); + /* CRTC_TEST_PATTERN_DATA has 16 bits, + * lowest 6 are hardwired to ZERO + * color bits should be left aligned aligned to MSB + * XXXXXXXXXX000000 for 10 bit, + * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 + */ + dst_color[index] <<= (16 - dst_bpc); + } + + value = 0; + addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS); + dm_write_reg(ctx, addr, value); + + /* We have to write the mask before data, similar to pipeline. + * For example, for 8 bpc, if we want RGB0 to be magenta, + * and RGB1 to be cyan, + * we need to make 7 writes: + * MASK DATA + * 000001 00000000 00000000 set mask to R0 + * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 + * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 + * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 + * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 + * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 + * 100000 11111111 00000000 B1 255, 0xFF00 + * + * we will make a loop of 6 in which we prepare the mask, + * then write, then prepare the color for next write. + * first iteration will write mask only, + * but each next iteration color prepared in + * previous iteration will be written within new mask, + * the last component will written separately, + * mask is not changing between 6th and 7th write + * and color will be prepared by last iteration + */ + + /* write color, color values mask in CRTC_TEST_PATTERN_MASK + * is B1, G1, R1, B0, G0, R0 + */ + value = 0; + addr = CRTC_REG(mmCRTC_TEST_PATTERN_COLOR); + for (index = 0; index < 6; index++) { + /* prepare color mask, first write PATTERN_DATA + * will have all zeros + */ + set_reg_field_value( + value, + (1 << index), + CRTC_TEST_PATTERN_COLOR, + CRTC_TEST_PATTERN_MASK); + /* write color component */ + dm_write_reg(ctx, addr, value); + /* prepare next color component, + * will be written in the next iteration + */ + set_reg_field_value( + value, + dst_color[index], + CRTC_TEST_PATTERN_COLOR, + CRTC_TEST_PATTERN_DATA); + } + /* write last color component, + * it's been already prepared in the loop + */ + dm_write_reg(ctx, addr, value); + + /* enable test pattern */ + addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL); + value = 0; + + set_reg_field_value( + value, + 1, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_EN); + + set_reg_field_value( + value, + mode, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_MODE); + + set_reg_field_value( + value, + 0, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_DYNAMIC_RANGE); + + set_reg_field_value( + value, + bit_depth, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_COLOR_FORMAT); + + dm_write_reg(ctx, addr, value); + } + break; + + case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: + { + mode = (bit_depth == + TEST_PATTERN_COLOR_FORMAT_BPC_10 ? + TEST_PATTERN_MODE_DUALRAMP_RGB : + TEST_PATTERN_MODE_SINGLERAMP_RGB); + + switch (bit_depth) { + case TEST_PATTERN_COLOR_FORMAT_BPC_6: + dst_bpc = 6; + break; + case TEST_PATTERN_COLOR_FORMAT_BPC_8: + dst_bpc = 8; + break; + case TEST_PATTERN_COLOR_FORMAT_BPC_10: + dst_bpc = 10; + break; + default: + dst_bpc = 8; + break; + } + + /* increment for the first ramp for one color gradation + * 1 gradation for 6-bit color is 2^10 + * gradations in 16-bit color + */ + inc_base = (src_bpc - dst_bpc); + + value = 0; + addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS); + + switch (bit_depth) { + case TEST_PATTERN_COLOR_FORMAT_BPC_6: + { + set_reg_field_value( + value, + inc_base, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_INC0); + set_reg_field_value( + value, + 0, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_INC1); + set_reg_field_value( + value, + 6, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_HRES); + set_reg_field_value( + value, + 6, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_VRES); + set_reg_field_value( + value, + 0, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_RAMP0_OFFSET); + } + break; + case TEST_PATTERN_COLOR_FORMAT_BPC_8: + { + set_reg_field_value( + value, + inc_base, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_INC0); + set_reg_field_value( + value, + 0, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_INC1); + set_reg_field_value( + value, + 8, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_HRES); + set_reg_field_value( + value, + 6, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_VRES); + set_reg_field_value( + value, + 0, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_RAMP0_OFFSET); + } + break; + case TEST_PATTERN_COLOR_FORMAT_BPC_10: + { + set_reg_field_value( + value, + inc_base, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_INC0); + set_reg_field_value( + value, + inc_base + 2, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_INC1); + set_reg_field_value( + value, + 8, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_HRES); + set_reg_field_value( + value, + 5, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_VRES); + set_reg_field_value( + value, + 384 << 6, + CRTC_TEST_PATTERN_PARAMETERS, + CRTC_TEST_PATTERN_RAMP0_OFFSET); + } + break; + default: + break; + } + dm_write_reg(ctx, addr, value); + + value = 0; + addr = CRTC_REG(mmCRTC_TEST_PATTERN_COLOR); + dm_write_reg(ctx, addr, value); + + /* enable test pattern */ + addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL); + value = 0; + + set_reg_field_value( + value, + 1, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_EN); + + set_reg_field_value( + value, + mode, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_MODE); + + set_reg_field_value( + value, + 0, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_DYNAMIC_RANGE); + /* add color depth translation here */ + set_reg_field_value( + value, + bit_depth, + CRTC_TEST_PATTERN_CONTROL, + CRTC_TEST_PATTERN_COLOR_FORMAT); + + dm_write_reg(ctx, addr, value); + } + break; + case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: + { + value = 0; + dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL), value); + dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_COLOR), value); + dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS), + value); + } + break; + default: + break; + } +} + +/** +* dce110_timing_generator_validate_timing +* The timing generators support a maximum display size of is 8192 x 8192 pixels, +* including both active display and blanking periods. Check H Total and V Total. +*/ +bool dce110_timing_generator_validate_timing( + struct timing_generator *tg, + const struct dc_crtc_timing *timing, + enum signal_type signal) +{ + uint32_t h_blank; + uint32_t h_back_porch; + uint32_t hsync_offset = timing->h_border_right + + timing->h_front_porch; + uint32_t h_sync_start = timing->h_addressable + hsync_offset; + + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + ASSERT(timing != NULL); + + if (!timing) + return false; + + /* Check maximum number of pixels supported by Timing Generator + * (Currently will never fail, in order to fail needs display which + * needs more than 8192 horizontal and + * more than 8192 vertical total pixels) + */ + if (timing->h_total > tg110->max_h_total || + timing->v_total > tg110->max_v_total) + return false; + + h_blank = (timing->h_total - timing->h_addressable - + timing->h_border_right - + timing->h_border_left); + + if (h_blank < tg110->min_h_blank) + return false; + + if (timing->h_front_porch < tg110->min_h_front_porch) + return false; + + h_back_porch = h_blank - (h_sync_start - + timing->h_addressable - + timing->h_border_right - + timing->h_sync_width); + + if (h_back_porch < tg110->min_h_back_porch) + return false; + + return true; +} + +/** +* Wait till we are at the beginning of VBlank. +*/ +void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg) +{ + /* We want to catch beginning of VBlank here, so if the first try are + * in VBlank, we might be very close to Active, in this case wait for + * another frame + */ + while (dce110_timing_generator_is_in_vertical_blank(tg)) { + if (!dce110_timing_generator_is_counter_moving(tg)) { + /* error - no point to wait if counter is not moving */ + break; + } + } + + while (!dce110_timing_generator_is_in_vertical_blank(tg)) { + if (!dce110_timing_generator_is_counter_moving(tg)) { + /* error - no point to wait if counter is not moving */ + break; + } + } +} + +/** +* Wait till we are in VActive (anywhere in VActive) +*/ +void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg) +{ + while (dce110_timing_generator_is_in_vertical_blank(tg)) { + if (!dce110_timing_generator_is_counter_moving(tg)) { + /* error - no point to wait if counter is not moving */ + break; + } + } +} + +/** + ***************************************************************************** + * Function: dce110_timing_generator_setup_global_swap_lock + * + * @brief + * Setups Global Swap Lock group for current pipe + * Pipe can join or leave GSL group, become a TimingServer or TimingClient + * + * @param [in] gsl_params: setup data + ***************************************************************************** + */ + +void dce110_timing_generator_setup_global_swap_lock( + struct timing_generator *tg, + const struct dcp_gsl_params *gsl_params) +{ + uint32_t value; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t address = DCP_REG(mmDCP_GSL_CONTROL); + uint32_t check_point = FLIP_READY_BACK_LOOKUP; + + value = dm_read_reg(tg->ctx, address); + + /* This pipe will belong to GSL Group zero. */ + set_reg_field_value(value, + 1, + DCP_GSL_CONTROL, + DCP_GSL0_EN); + + set_reg_field_value(value, + gsl_params->gsl_master == tg->inst, + DCP_GSL_CONTROL, + DCP_GSL_MASTER_EN); + + set_reg_field_value(value, + HFLIP_READY_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_FORCE_DELAY); + + /* Keep signal low (pending high) during 6 lines. + * Also defines minimum interval before re-checking signal. */ + set_reg_field_value(value, + HFLIP_CHECK_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + + + { + uint32_t value_crtc_vtotal; + + value_crtc_vtotal = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_V_TOTAL)); + + set_reg_field_value(value, + 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ + DCP_GSL_CONTROL, + DCP_GSL_SYNC_SOURCE); + + /* Checkpoint relative to end of frame */ + check_point = get_reg_field_value(value_crtc_vtotal, + CRTC_V_TOTAL, + CRTC_V_TOTAL); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0); + } + + set_reg_field_value(value, + 1, + DCP_GSL_CONTROL, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); + + dm_write_reg(tg->ctx, address, value); + + /********************************************************************/ + address = CRTC_REG(mmCRTC_GSL_CONTROL); + + value = 0; + set_reg_field_value(value, + check_point - FLIP_READY_BACK_LOOKUP, + CRTC_GSL_CONTROL, + CRTC_GSL_CHECK_LINE_NUM); + + set_reg_field_value(value, + VFLIP_READY_DELAY, + CRTC_GSL_CONTROL, + CRTC_GSL_FORCE_DELAY); + + dm_write_reg(tg->ctx, address, value); +} + +void dce110_timing_generator_tear_down_global_swap_lock( + struct timing_generator *tg) +{ + /* Clear all the register writes done by + * dce110_timing_generator_setup_global_swap_lock + */ + + uint32_t value; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t address = DCP_REG(mmDCP_GSL_CONTROL); + + value = 0; + + /* This pipe will belong to GSL Group zero. */ + /* Settig HW default values from reg specs */ + set_reg_field_value(value, + 0, + DCP_GSL_CONTROL, + DCP_GSL0_EN); + + set_reg_field_value(value, + 0, + DCP_GSL_CONTROL, + DCP_GSL_MASTER_EN); + + set_reg_field_value(value, + 0x2, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_FORCE_DELAY); + + set_reg_field_value(value, + 0x6, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + + /* Restore DCP_GSL_PURPOSE_SURFACE_FLIP */ + { + uint32_t value_crtc_vtotal; + + value_crtc_vtotal = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_V_TOTAL)); + + set_reg_field_value(value, + 0, + DCP_GSL_CONTROL, + DCP_GSL_SYNC_SOURCE); + } + + set_reg_field_value(value, + 0, + DCP_GSL_CONTROL, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); + + dm_write_reg(tg->ctx, address, value); + + /********************************************************************/ + address = CRTC_REG(mmCRTC_GSL_CONTROL); + + value = 0; + set_reg_field_value(value, + 0, + CRTC_GSL_CONTROL, + CRTC_GSL_CHECK_LINE_NUM); + + set_reg_field_value(value, + 0x2, + CRTC_GSL_CONTROL, + CRTC_GSL_FORCE_DELAY); + + dm_write_reg(tg->ctx, address, value); +} +/** + ***************************************************************************** + * Function: is_counter_moving + * + * @brief + * check if the timing generator is currently going + * + * @return + * true if currently going, false if currently paused or stopped. + * + ***************************************************************************** + */ +bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg) +{ + uint32_t h1 = 0; + uint32_t h2 = 0; + uint32_t v1 = 0; + uint32_t v2 = 0; + + tg->funcs->get_position(tg, &h1, &v1); + tg->funcs->get_position(tg, &h2, &v2); + + if (h1 == h2 && v1 == v2) + return false; + else + return true; +} + +void dce110_timing_generator_enable_advanced_request( + struct timing_generator *tg, + bool enable, + const struct dc_crtc_timing *timing) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); + uint32_t value = dm_read_reg(tg->ctx, addr); + + if (enable) { + set_reg_field_value( + value, + 0, + CRTC_START_LINE_CONTROL, + CRTC_LEGACY_REQUESTOR_EN); + } else { + set_reg_field_value( + value, + 1, + CRTC_START_LINE_CONTROL, + CRTC_LEGACY_REQUESTOR_EN); + } + + if ((timing->v_sync_width + timing->v_front_porch) <= 3) { + set_reg_field_value( + value, + 3, + CRTC_START_LINE_CONTROL, + CRTC_ADVANCED_START_LINE_POSITION); + set_reg_field_value( + value, + 0, + CRTC_START_LINE_CONTROL, + CRTC_PREFETCH_EN); + } else { + set_reg_field_value( + value, + 4, + CRTC_START_LINE_CONTROL, + CRTC_ADVANCED_START_LINE_POSITION); + set_reg_field_value( + value, + 1, + CRTC_START_LINE_CONTROL, + CRTC_PREFETCH_EN); + } + + set_reg_field_value( + value, + 1, + CRTC_START_LINE_CONTROL, + CRTC_PROGRESSIVE_START_LINE_EARLY); + + set_reg_field_value( + value, + 1, + CRTC_START_LINE_CONTROL, + CRTC_INTERLACE_START_LINE_EARLY); + + dm_write_reg(tg->ctx, addr, value); +} + +/*TODO: Figure out if we need this function. */ +void dce110_timing_generator_set_lock_master(struct timing_generator *tg, + bool lock) +{ + struct dc_context *ctx = tg->ctx; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK); + uint32_t value = dm_read_reg(ctx, addr); + + set_reg_field_value( + value, + lock ? 1 : 0, + CRTC_MASTER_UPDATE_LOCK, + MASTER_UPDATE_LOCK); + + dm_write_reg(ctx, addr, value); +} + +void dce110_timing_generator_enable_reset_trigger( + struct timing_generator *tg, + int source_tg_inst) +{ + uint32_t value; + uint32_t rising_edge = 0; + uint32_t falling_edge = 0; + enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + /* Setup trigger edge */ + { + uint32_t pol_value = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_V_SYNC_A_CNTL)); + + /* Register spec has reversed definition: + * 0 for positive, 1 for negative */ + if (get_reg_field_value(pol_value, + CRTC_V_SYNC_A_CNTL, + CRTC_V_SYNC_A_POL) == 0) { + rising_edge = 1; + } else { + falling_edge = 1; + } + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); + + trig_src_select = TRIGGER_SOURCE_SELECT_GSL_GROUP0; + + set_reg_field_value(value, + trig_src_select, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); + + set_reg_field_value(value, + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); + + set_reg_field_value(value, + rising_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_RISING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + falling_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + 0, /* send every signal */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_FREQUENCY_SELECT); + + set_reg_field_value(value, + 0, /* no delay */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_DELAY); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); + + /**************************************************************/ + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 2, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 1, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); +} + +void dce110_timing_generator_disable_reset_trigger( + struct timing_generator *tg) +{ + uint32_t value; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 0, /* force counter now mode is disabled */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + + /********************************************************************/ + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); + + set_reg_field_value(value, + TRIGGER_SOURCE_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); + + set_reg_field_value(value, + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); +} + +/** + ***************************************************************************** + * @brief + * Checks whether CRTC triggered reset occurred + * + * @return + * true if triggered reset occurred, false otherwise + ***************************************************************************** + */ +bool dce110_timing_generator_did_triggered_reset_occur( + struct timing_generator *tg) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t value = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + return get_reg_field_value(value, + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; +} + +/** + * dce110_timing_generator_disable_vga + * Turn OFF VGA Mode and Timing - DxVGA_CONTROL + * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors; + */ +void dce110_timing_generator_disable_vga( + struct timing_generator *tg) +{ + uint32_t addr = 0; + uint32_t value = 0; + + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + switch (tg110->controller_id) { + case CONTROLLER_ID_D0: + addr = mmD1VGA_CONTROL; + break; + case CONTROLLER_ID_D1: + addr = mmD2VGA_CONTROL; + break; + case CONTROLLER_ID_D2: + addr = mmD3VGA_CONTROL; + break; + case CONTROLLER_ID_D3: + addr = mmD4VGA_CONTROL; + break; + case CONTROLLER_ID_D4: + addr = mmD5VGA_CONTROL; + break; + case CONTROLLER_ID_D5: + addr = mmD6VGA_CONTROL; + break; + default: + break; + } + value = dm_read_reg(tg->ctx, addr); + + set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); + set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); + set_reg_field_value( + value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT); + set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); + + dm_write_reg(tg->ctx, addr, value); +} + +/** +* set_overscan_color_black +* +* @param :black_color is one of the color space +* :this routine will set overscan black color according to the color space. +* @return none +*/ + +void dce110_timing_generator_set_overscan_color_black( + struct timing_generator *tg, + const struct tg_color *color) +{ + struct dc_context *ctx = tg->ctx; + uint32_t addr; + uint32_t value = 0; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + set_reg_field_value( + value, + color->color_b_cb, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_BLUE); + + set_reg_field_value( + value, + color->color_r_cr, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_RED); + + set_reg_field_value( + value, + color->color_g_y, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_GREEN); + + addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR); + dm_write_reg(ctx, addr, value); + addr = CRTC_REG(mmCRTC_BLACK_COLOR); + dm_write_reg(ctx, addr, value); + /* This is desirable to have a constant DAC output voltage during the + * blank time that is higher than the 0 volt reference level that the + * DAC outputs when the NBLANK signal + * is asserted low, such as for output to an analog TV. */ + addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR); + dm_write_reg(ctx, addr, value); + + /* TO DO we have to program EXT registers and we need to know LB DATA + * format because it is used when more 10 , i.e. 12 bits per color + * + * m_mmDxCRTC_OVERSCAN_COLOR_EXT + * m_mmDxCRTC_BLACK_COLOR_EXT + * m_mmDxCRTC_BLANK_DATA_COLOR_EXT + */ + +} + +void dce110_tg_program_blank_color(struct timing_generator *tg, + const struct tg_color *black_color) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR); + uint32_t value = dm_read_reg(tg->ctx, addr); + + set_reg_field_value( + value, + black_color->color_b_cb, + CRTC_BLACK_COLOR, + CRTC_BLACK_COLOR_B_CB); + set_reg_field_value( + value, + black_color->color_g_y, + CRTC_BLACK_COLOR, + CRTC_BLACK_COLOR_G_Y); + set_reg_field_value( + value, + black_color->color_r_cr, + CRTC_BLACK_COLOR, + CRTC_BLACK_COLOR_R_CR); + + dm_write_reg(tg->ctx, addr, value); + + addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR); + dm_write_reg(tg->ctx, addr, value); +} + +void dce110_tg_set_overscan_color(struct timing_generator *tg, + const struct tg_color *overscan_color) +{ + struct dc_context *ctx = tg->ctx; + uint32_t value = 0; + uint32_t addr; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + set_reg_field_value( + value, + overscan_color->color_b_cb, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_BLUE); + + set_reg_field_value( + value, + overscan_color->color_g_y, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_GREEN); + + set_reg_field_value( + value, + overscan_color->color_r_cr, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_RED); + + addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR); + dm_write_reg(ctx, addr, value); +} + +void dce110_tg_get_position(struct timing_generator *tg, + struct crtc_position *position) +{ + int32_t h_position; + int32_t v_position; + + dce110_timing_generator_get_crtc_positions(tg, &h_position, &v_position); + + position->horizontal_count = (uint32_t)h_position; + position->vertical_count = (uint32_t)v_position; +} + +void dce110_tg_program_timing(struct timing_generator *tg, + const struct dc_crtc_timing *timing, + bool use_vbios) +{ + if (use_vbios) + dce110_timing_generator_program_timing_generator(tg, timing); + else + dce110_timing_generator_program_blanking(tg, timing); +} + +bool dce110_tg_is_blanked(struct timing_generator *tg) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL)); + + if (get_reg_field_value( + value, + CRTC_BLANK_CONTROL, + CRTC_BLANK_DATA_EN) == 1 && + get_reg_field_value( + value, + CRTC_BLANK_CONTROL, + CRTC_CURRENT_BLANK_STATE) == 1) + return true; + return false; +} + +bool dce110_tg_set_blank(struct timing_generator *tg, + bool enable_blanking) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t value = 0; + + set_reg_field_value( + value, + 1, + CRTC_DOUBLE_BUFFER_CONTROL, + CRTC_BLANK_DATA_DOUBLE_BUFFER_EN); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_DOUBLE_BUFFER_CONTROL), value); + value = 0; + + if (enable_blanking) { + int counter; + + set_reg_field_value( + value, + 1, + CRTC_BLANK_CONTROL, + CRTC_BLANK_DATA_EN); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), value); + + for (counter = 0; counter < 100; counter++) { + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL)); + + if (get_reg_field_value( + value, + CRTC_BLANK_CONTROL, + CRTC_BLANK_DATA_EN) == 1 && + get_reg_field_value( + value, + CRTC_BLANK_CONTROL, + CRTC_CURRENT_BLANK_STATE) == 1) + break; + + msleep(1); + } + + if (counter == 100) { + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "timing generator %d blank timing out.\n", + tg110->controller_id); + return false; + } + } else + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), 0); + + return true; +} + +bool dce110_tg_validate_timing(struct timing_generator *tg, + const struct dc_crtc_timing *timing) +{ + return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); +} + +void dce110_tg_wait_for_state(struct timing_generator *tg, + enum crtc_state state) +{ + switch (state) { + case CRTC_STATE_VBLANK: + dce110_timing_generator_wait_for_vblank(tg); + break; + + case CRTC_STATE_VACTIVE: + dce110_timing_generator_wait_for_vactive(tg); + break; + + default: + break; + } +} + +void dce110_tg_set_colors(struct timing_generator *tg, + const struct tg_color *blank_color, + const struct tg_color *overscan_color) +{ + if (blank_color != NULL) + dce110_tg_program_blank_color(tg, blank_color); + if (overscan_color != NULL) + dce110_tg_set_overscan_color(tg, overscan_color); +} + +static const struct timing_generator_funcs dce110_tg_funcs = { + .validate_timing = dce110_tg_validate_timing, + .program_timing = dce110_tg_program_timing, + .enable_crtc = dce110_timing_generator_enable_crtc, + .disable_crtc = dce110_timing_generator_disable_crtc, + .is_counter_moving = dce110_timing_generator_is_counter_moving, + .get_position = dce110_timing_generator_get_crtc_positions, + .get_frame_count = dce110_timing_generator_get_vblank_counter, + .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, + .set_early_control = dce110_timing_generator_set_early_control, + .wait_for_state = dce110_tg_wait_for_state, + .set_blank = dce110_tg_set_blank, + .is_blanked = dce110_tg_is_blanked, + .set_colors = dce110_tg_set_colors, + .set_overscan_blank_color = + dce110_timing_generator_set_overscan_color_black, + .set_blank_color = dce110_timing_generator_program_blank_color, + .disable_vga = dce110_timing_generator_disable_vga, + .did_triggered_reset_occur = + dce110_timing_generator_did_triggered_reset_occur, + .setup_global_swap_lock = + dce110_timing_generator_setup_global_swap_lock, + .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, + .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, + .tear_down_global_swap_lock = + dce110_timing_generator_tear_down_global_swap_lock, + .enable_advanced_request = + dce110_timing_generator_enable_advanced_request, + .set_drr = + dce110_timing_generator_set_drr, + .set_static_screen_control = + dce110_timing_generator_set_static_screen_control, + .set_test_pattern = dce110_timing_generator_set_test_pattern + +}; + +bool dce110_timing_generator_construct( + struct dce110_timing_generator *tg110, + struct dc_context *ctx, + uint32_t instance, + const struct dce110_timing_generator_offsets *offsets) +{ + if (!tg110) + return false; + + tg110->controller_id = CONTROLLER_ID_D0 + instance; + tg110->base.inst = instance; + + tg110->offsets = *offsets; + + tg110->base.funcs = &dce110_tg_funcs; + + tg110->base.ctx = ctx; + tg110->base.bp = ctx->dc_bios; + + tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; + tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; + + tg110->min_h_blank = 56; + tg110->min_h_front_porch = 4; + tg110->min_h_back_porch = 4; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h new file mode 100644 index 000000000000..39906502ad5c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -0,0 +1,273 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_TIMING_GENERATOR_DCE110_H__ +#define __DC_TIMING_GENERATOR_DCE110_H__ + +#include "timing_generator.h" +#include "../include/grph_object_id.h" +#include "../include/hw_sequencer_types.h" + +/* GSL Sync related values */ + +/* In VSync mode, after 4 units of time, master pipe will generate + * flip_ready signal */ +#define VFLIP_READY_DELAY 4 +/* In HSync mode, after 2 units of time, master pipe will generate + * flip_ready signal */ +#define HFLIP_READY_DELAY 2 +/* 6 lines delay between forcing flip and checking all pipes ready */ +#define HFLIP_CHECK_DELAY 6 +/* 3 lines before end of frame */ +#define FLIP_READY_BACK_LOOKUP 3 + +/* Trigger Source Select - ASIC-defendant, actual values for the + * register programming */ +enum trigger_source_select { + TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0, + TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1, + TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2, + TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3, + TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4, + TRIGGER_SOURCE_SELECT_GENERICF = 5, + TRIGGER_SOURCE_SELECT_GENERICE = 6, + TRIGGER_SOURCE_SELECT_VSYNCA = 7, + TRIGGER_SOURCE_SELECT_HSYNCA = 8, + TRIGGER_SOURCE_SELECT_VSYNCB = 9, + TRIGGER_SOURCE_SELECT_HSYNCB = 10, + TRIGGER_SOURCE_SELECT_HPD1 = 11, + TRIGGER_SOURCE_SELECT_HPD2 = 12, + TRIGGER_SOURCE_SELECT_GENERICD = 13, + TRIGGER_SOURCE_SELECT_GENERICC = 14, + TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15, + TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16, + TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17, + TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18, + TRIGGER_SOURCE_SELECT_BLONY = 19, + TRIGGER_SOURCE_SELECT_GENERICA = 20, + TRIGGER_SOURCE_SELECT_GENERICB = 21, + TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22, + TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23 +}; + +/* Trigger Source Select - ASIC-dependant, actual values for the + * register programming */ +enum trigger_polarity_select { + TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0, + TRIGGER_POLARITY_SELECT_CRTC = 1, + TRIGGER_POLARITY_SELECT_GENERICA = 2, + TRIGGER_POLARITY_SELECT_GENERICB = 3, + TRIGGER_POLARITY_SELECT_HSYNCA = 4, + TRIGGER_POLARITY_SELECT_HSYNCB = 5, + TRIGGER_POLARITY_SELECT_VIDEO_CAPTURE = 6, + TRIGGER_POLARITY_SELECT_GENERICC = 7 +}; + + +struct dce110_timing_generator_offsets { + int32_t crtc; + int32_t dcp; + + /* DCE80 use only */ + int32_t dmif; +}; + +struct dce110_timing_generator { + struct timing_generator base; + struct dce110_timing_generator_offsets offsets; + struct dce110_timing_generator_offsets derived_offsets; + + enum controller_id controller_id; + + uint32_t max_h_total; + uint32_t max_v_total; + + uint32_t min_h_blank; + uint32_t min_h_front_porch; + uint32_t min_h_back_porch; + + uint32_t min_h_sync_width; + uint32_t min_v_sync_width; + uint32_t min_v_blank; + +}; + +#define DCE110TG_FROM_TG(tg)\ + container_of(tg, struct dce110_timing_generator, base) + +bool dce110_timing_generator_construct( + struct dce110_timing_generator *tg, + struct dc_context *ctx, + uint32_t instance, + const struct dce110_timing_generator_offsets *offsets); + +/* determine if given timing can be supported by TG */ +bool dce110_timing_generator_validate_timing( + struct timing_generator *tg, + const struct dc_crtc_timing *timing, + enum signal_type signal); + +/******** HW programming ************/ + +/* Program timing generator with given timing */ +bool dce110_timing_generator_program_timing_generator( + struct timing_generator *tg, + const struct dc_crtc_timing *dc_crtc_timing); + +/* Disable/Enable Timing Generator */ +bool dce110_timing_generator_enable_crtc(struct timing_generator *tg); +bool dce110_timing_generator_disable_crtc(struct timing_generator *tg); + +void dce110_timing_generator_set_early_control( + struct timing_generator *tg, + uint32_t early_cntl); + +/**************** TG current status ******************/ + +/* return the current frame counter. Used by Linux kernel DRM */ +uint32_t dce110_timing_generator_get_vblank_counter( + struct timing_generator *tg); + +/* Get current H and V position */ +void dce110_timing_generator_get_crtc_positions( + struct timing_generator *tg, + int32_t *h_position, + int32_t *v_position); + +/* return true if TG counter is moving. false if TG is stopped */ +bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg); + +/* wait until TG is in beginning of vertical blank region */ +void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg); + +/* wait until TG is in beginning of active region */ +void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg); + +/*********** Timing Generator Synchronization routines ****/ + +/* Setups Global Swap Lock group, TimingServer or TimingClient*/ +void dce110_timing_generator_setup_global_swap_lock( + struct timing_generator *tg, + const struct dcp_gsl_params *gsl_params); + +/* Clear all the register writes done by setup_global_swap_lock */ +void dce110_timing_generator_tear_down_global_swap_lock( + struct timing_generator *tg); + +/* Reset slave controllers on master VSync */ +void dce110_timing_generator_enable_reset_trigger( + struct timing_generator *tg, + int source); + +/* disabling trigger-reset */ +void dce110_timing_generator_disable_reset_trigger( + struct timing_generator *tg); + +/* Checks whether CRTC triggered reset occurred */ +bool dce110_timing_generator_did_triggered_reset_occur( + struct timing_generator *tg); + +/******** Stuff to move to other virtual HW objects *****************/ +/* Move to enable accelerated mode */ +void dce110_timing_generator_disable_vga(struct timing_generator *tg); +/* TODO: Should we move it to transform */ +/* Fully program CRTC timing in timing generator */ +void dce110_timing_generator_program_blanking( + struct timing_generator *tg, + const struct dc_crtc_timing *timing); + +/* TODO: Should we move it to opp? */ +/* Combine with below and move YUV/RGB color conversion to SW layer */ +void dce110_timing_generator_program_blank_color( + struct timing_generator *tg, + const struct tg_color *black_color); +/* Combine with above and move YUV/RGB color conversion to SW layer */ +void dce110_timing_generator_set_overscan_color_black( + struct timing_generator *tg, + const struct tg_color *color); +void dce110_timing_generator_color_space_to_black_color( + enum dc_color_space colorspace, + struct tg_color *black_color); +/*************** End-of-move ********************/ + +/* Not called yet */ +void dce110_timing_generator_set_test_pattern( + struct timing_generator *tg, + /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' + * because this is not DP-specific (which is probably somewhere in DP + * encoder) */ + enum controller_dp_test_pattern test_pattern, + enum dc_color_depth color_depth); + +void dce110_timing_generator_set_drr( + struct timing_generator *tg, + const struct drr_params *params); + +void dce110_timing_generator_set_static_screen_control( + struct timing_generator *tg, + uint32_t value); + +uint32_t dce110_timing_generator_get_crtc_scanoutpos( + struct timing_generator *tg, + uint32_t *vbl, + uint32_t *position); + +void dce110_timing_generator_enable_advanced_request( + struct timing_generator *tg, + bool enable, + const struct dc_crtc_timing *timing); + +void dce110_timing_generator_set_lock_master(struct timing_generator *tg, + bool lock); + +void dce110_tg_program_blank_color(struct timing_generator *tg, + const struct tg_color *black_color); + +void dce110_tg_set_overscan_color(struct timing_generator *tg, + const struct tg_color *overscan_color); + +void dce110_tg_get_position(struct timing_generator *tg, + struct crtc_position *position); + +void dce110_tg_program_timing(struct timing_generator *tg, + const struct dc_crtc_timing *timing, + bool use_vbios); + +bool dce110_tg_is_blanked(struct timing_generator *tg); + +bool dce110_tg_set_blank(struct timing_generator *tg, + bool enable_blanking); + +bool dce110_tg_validate_timing(struct timing_generator *tg, + const struct dc_crtc_timing *timing); + +void dce110_tg_wait_for_state(struct timing_generator *tg, + enum crtc_state state); + +void dce110_tg_set_colors(struct timing_generator *tg, + const struct tg_color *blank_color, + const struct tg_color *overscan_color); + +#endif /* __DC_TIMING_GENERATOR_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c new file mode 100644 index 000000000000..3bf3179e07c5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -0,0 +1,743 @@ +#include "dm_services.h" + +/* include DCE11 register header files */ +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#include "dc_types.h" +#include "dc_bios_types.h" +#include "dc.h" + +#include "include/grph_object_id.h" +#include "include/logger_interface.h" +#include "dce110_timing_generator.h" +#include "dce110_timing_generator_v.h" + +#include "timing_generator.h" + +/** ******************************************************************************** + * + * DCE11 Timing Generator Implementation + * + **********************************************************************************/ + +/** +* Enable CRTCV +*/ + +static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg) +{ +/* +* Set MASTER_UPDATE_MODE to 0 +* This is needed for DRR, and also suggested to be default value by Syed. +*/ + + uint32_t value; + + value = 0; + set_reg_field_value(value, 0, + CRTCV_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE); + dm_write_reg(tg->ctx, + mmCRTCV_MASTER_UPDATE_MODE, value); + + /* TODO: may want this on for looking for underflow */ + value = 0; + dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); + + value = 0; + set_reg_field_value(value, 1, + CRTCV_MASTER_EN, CRTC_MASTER_EN); + dm_write_reg(tg->ctx, + mmCRTCV_MASTER_EN, value); + + return true; +} + +static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) +{ + uint32_t value; + + value = dm_read_reg(tg->ctx, + mmCRTCV_CONTROL); + set_reg_field_value(value, 0, + CRTCV_CONTROL, CRTC_DISABLE_POINT_CNTL); + set_reg_field_value(value, 0, + CRTCV_CONTROL, CRTC_MASTER_EN); + dm_write_reg(tg->ctx, + mmCRTCV_CONTROL, value); + /* + * TODO: call this when adding stereo support + * tg->funcs->disable_stereo(tg); + */ + return true; +} + +static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t addr = mmCRTCV_BLANK_CONTROL; + uint32_t value = dm_read_reg(tg->ctx, addr); + uint8_t counter = 100; + + set_reg_field_value( + value, + 1, + CRTCV_BLANK_CONTROL, + CRTC_BLANK_DATA_EN); + + set_reg_field_value( + value, + 0, + CRTCV_BLANK_CONTROL, + CRTC_BLANK_DE_MODE); + + dm_write_reg(tg->ctx, addr, value); + + while (counter > 0) { + value = dm_read_reg(tg->ctx, addr); + + if (get_reg_field_value( + value, + CRTCV_BLANK_CONTROL, + CRTC_BLANK_DATA_EN) == 1 && + get_reg_field_value( + value, + CRTCV_BLANK_CONTROL, + CRTC_CURRENT_BLANK_STATE) == 1) + break; + + msleep(1); + counter--; + } + + if (!counter) { + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "timing generator %d blank timing out.\n", + tg110->controller_id); + return false; + } + + return true; +} + +static bool dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg) +{ + uint32_t addr = mmCRTCV_BLANK_CONTROL; + uint32_t value = dm_read_reg(tg->ctx, addr); + + set_reg_field_value( + value, + 0, + CRTCV_BLANK_CONTROL, + CRTC_BLANK_DATA_EN); + + set_reg_field_value( + value, + 0, + CRTCV_BLANK_CONTROL, + CRTC_BLANK_DE_MODE); + + dm_write_reg(tg->ctx, addr, value); + + return true; +} + +static bool dce110_timing_generator_v_is_in_vertical_blank( + struct timing_generator *tg) +{ + uint32_t addr = 0; + uint32_t value = 0; + uint32_t field = 0; + + addr = mmCRTCV_STATUS; + value = dm_read_reg(tg->ctx, addr); + field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK); + return field == 1; +} + +static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg) +{ + uint32_t value; + uint32_t h1 = 0; + uint32_t h2 = 0; + uint32_t v1 = 0; + uint32_t v2 = 0; + + value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); + + h1 = get_reg_field_value( + value, + CRTCV_STATUS_POSITION, + CRTC_HORZ_COUNT); + + v1 = get_reg_field_value( + value, + CRTCV_STATUS_POSITION, + CRTC_VERT_COUNT); + + value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); + + h2 = get_reg_field_value( + value, + CRTCV_STATUS_POSITION, + CRTC_HORZ_COUNT); + + v2 = get_reg_field_value( + value, + CRTCV_STATUS_POSITION, + CRTC_VERT_COUNT); + + if (h1 == h2 && v1 == v2) + return false; + else + return true; +} + +static void dce110_timing_generator_v_wait_for_vblank(struct timing_generator *tg) +{ + /* We want to catch beginning of VBlank here, so if the first try are + * in VBlank, we might be very close to Active, in this case wait for + * another frame + */ + while (dce110_timing_generator_v_is_in_vertical_blank(tg)) { + if (!dce110_timing_generator_v_is_counter_moving(tg)) { + /* error - no point to wait if counter is not moving */ + break; + } + } + + while (!dce110_timing_generator_v_is_in_vertical_blank(tg)) { + if (!dce110_timing_generator_v_is_counter_moving(tg)) { + /* error - no point to wait if counter is not moving */ + break; + } + } +} + +/** +* Wait till we are in VActive (anywhere in VActive) +*/ +static void dce110_timing_generator_v_wait_for_vactive(struct timing_generator *tg) +{ + while (dce110_timing_generator_v_is_in_vertical_blank(tg)) { + if (!dce110_timing_generator_v_is_counter_moving(tg)) { + /* error - no point to wait if counter is not moving */ + break; + } + } +} + +static void dce110_timing_generator_v_wait_for_state(struct timing_generator *tg, + enum crtc_state state) +{ + switch (state) { + case CRTC_STATE_VBLANK: + dce110_timing_generator_v_wait_for_vblank(tg); + break; + + case CRTC_STATE_VACTIVE: + dce110_timing_generator_v_wait_for_vactive(tg); + break; + + default: + break; + } +} + +static void dce110_timing_generator_v_program_blanking( + struct timing_generator *tg, + const struct dc_crtc_timing *timing) +{ + uint32_t vsync_offset = timing->v_border_bottom + + timing->v_front_porch; + uint32_t v_sync_start = timing->v_addressable + vsync_offset; + + uint32_t hsync_offset = timing->h_border_right + + timing->h_front_porch; + uint32_t h_sync_start = timing->h_addressable + hsync_offset; + + struct dc_context *ctx = tg->ctx; + uint32_t value = 0; + uint32_t addr = 0; + uint32_t tmp = 0; + + addr = mmCRTCV_H_TOTAL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->h_total - 1, + CRTCV_H_TOTAL, + CRTC_H_TOTAL); + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_V_TOTAL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->v_total - 1, + CRTCV_V_TOTAL, + CRTC_V_TOTAL); + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_H_BLANK_START_END; + value = dm_read_reg(ctx, addr); + + tmp = timing->h_total - + (h_sync_start + timing->h_border_left); + + set_reg_field_value( + value, + tmp, + CRTCV_H_BLANK_START_END, + CRTC_H_BLANK_END); + + tmp = tmp + timing->h_addressable + + timing->h_border_left + timing->h_border_right; + + set_reg_field_value( + value, + tmp, + CRTCV_H_BLANK_START_END, + CRTC_H_BLANK_START); + + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_V_BLANK_START_END; + value = dm_read_reg(ctx, addr); + + tmp = timing->v_total - (v_sync_start + timing->v_border_top); + + set_reg_field_value( + value, + tmp, + CRTCV_V_BLANK_START_END, + CRTC_V_BLANK_END); + + tmp = tmp + timing->v_addressable + timing->v_border_top + + timing->v_border_bottom; + + set_reg_field_value( + value, + tmp, + CRTCV_V_BLANK_START_END, + CRTC_V_BLANK_START); + + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_H_SYNC_A; + value = 0; + set_reg_field_value( + value, + timing->h_sync_width, + CRTCV_H_SYNC_A, + CRTC_H_SYNC_A_END); + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_H_SYNC_A_CNTL; + value = dm_read_reg(ctx, addr); + if (timing->flags.HSYNC_POSITIVE_POLARITY) { + set_reg_field_value( + value, + 0, + CRTCV_H_SYNC_A_CNTL, + CRTC_H_SYNC_A_POL); + } else { + set_reg_field_value( + value, + 1, + CRTCV_H_SYNC_A_CNTL, + CRTC_H_SYNC_A_POL); + } + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_V_SYNC_A; + value = 0; + set_reg_field_value( + value, + timing->v_sync_width, + CRTCV_V_SYNC_A, + CRTC_V_SYNC_A_END); + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_V_SYNC_A_CNTL; + value = dm_read_reg(ctx, addr); + if (timing->flags.VSYNC_POSITIVE_POLARITY) { + set_reg_field_value( + value, + 0, + CRTCV_V_SYNC_A_CNTL, + CRTC_V_SYNC_A_POL); + } else { + set_reg_field_value( + value, + 1, + CRTCV_V_SYNC_A_CNTL, + CRTC_V_SYNC_A_POL); + } + dm_write_reg(ctx, addr, value); + + addr = mmCRTCV_INTERLACE_CONTROL; + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->flags.INTERLACE, + CRTCV_INTERLACE_CONTROL, + CRTC_INTERLACE_ENABLE); + dm_write_reg(ctx, addr, value); +} + +static void dce110_timing_generator_v_enable_advanced_request( + struct timing_generator *tg, + bool enable, + const struct dc_crtc_timing *timing) +{ + uint32_t addr = mmCRTCV_START_LINE_CONTROL; + uint32_t value = dm_read_reg(tg->ctx, addr); + + if (enable) { + if ((timing->v_sync_width + timing->v_front_porch) <= 3) { + set_reg_field_value( + value, + 3, + CRTCV_START_LINE_CONTROL, + CRTC_ADVANCED_START_LINE_POSITION); + } else { + set_reg_field_value( + value, + 4, + CRTCV_START_LINE_CONTROL, + CRTC_ADVANCED_START_LINE_POSITION); + } + set_reg_field_value( + value, + 0, + CRTCV_START_LINE_CONTROL, + CRTC_LEGACY_REQUESTOR_EN); + } else { + set_reg_field_value( + value, + 2, + CRTCV_START_LINE_CONTROL, + CRTC_ADVANCED_START_LINE_POSITION); + set_reg_field_value( + value, + 1, + CRTCV_START_LINE_CONTROL, + CRTC_LEGACY_REQUESTOR_EN); + } + + dm_write_reg(tg->ctx, addr, value); +} + +static bool dce110_timing_generator_v_set_blank(struct timing_generator *tg, + bool enable_blanking) +{ + if (enable_blanking) + return dce110_timing_generator_v_blank_crtc(tg); + else + return dce110_timing_generator_v_unblank_crtc(tg); +} + +static void dce110_timing_generator_v_program_timing(struct timing_generator *tg, + const struct dc_crtc_timing *timing, + bool use_vbios) +{ + if (use_vbios) + dce110_timing_generator_program_timing_generator(tg, timing); + else + dce110_timing_generator_v_program_blanking(tg, timing); +} + +static void dce110_timing_generator_v_program_blank_color( + struct timing_generator *tg, + const struct tg_color *black_color) +{ + uint32_t addr = mmCRTCV_BLACK_COLOR; + uint32_t value = dm_read_reg(tg->ctx, addr); + + set_reg_field_value( + value, + black_color->color_b_cb, + CRTCV_BLACK_COLOR, + CRTC_BLACK_COLOR_B_CB); + set_reg_field_value( + value, + black_color->color_g_y, + CRTCV_BLACK_COLOR, + CRTC_BLACK_COLOR_G_Y); + set_reg_field_value( + value, + black_color->color_r_cr, + CRTCV_BLACK_COLOR, + CRTC_BLACK_COLOR_R_CR); + + dm_write_reg(tg->ctx, addr, value); +} + +static void dce110_timing_generator_v_set_overscan_color_black( + struct timing_generator *tg, + const struct tg_color *color) +{ + struct dc_context *ctx = tg->ctx; + uint32_t addr; + uint32_t value = 0; + + set_reg_field_value( + value, + color->color_b_cb, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_BLUE); + + set_reg_field_value( + value, + color->color_r_cr, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_RED); + + set_reg_field_value( + value, + color->color_g_y, + CRTC_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_GREEN); + + addr = mmCRTCV_OVERSCAN_COLOR; + dm_write_reg(ctx, addr, value); + addr = mmCRTCV_BLACK_COLOR; + dm_write_reg(ctx, addr, value); + /* This is desirable to have a constant DAC output voltage during the + * blank time that is higher than the 0 volt reference level that the + * DAC outputs when the NBLANK signal + * is asserted low, such as for output to an analog TV. */ + addr = mmCRTCV_BLANK_DATA_COLOR; + dm_write_reg(ctx, addr, value); + + /* TO DO we have to program EXT registers and we need to know LB DATA + * format because it is used when more 10 , i.e. 12 bits per color + * + * m_mmDxCRTC_OVERSCAN_COLOR_EXT + * m_mmDxCRTC_BLACK_COLOR_EXT + * m_mmDxCRTC_BLANK_DATA_COLOR_EXT + */ +} + +static void dce110_tg_v_program_blank_color(struct timing_generator *tg, + const struct tg_color *black_color) +{ + uint32_t addr = mmCRTCV_BLACK_COLOR; + uint32_t value = dm_read_reg(tg->ctx, addr); + + set_reg_field_value( + value, + black_color->color_b_cb, + CRTCV_BLACK_COLOR, + CRTC_BLACK_COLOR_B_CB); + set_reg_field_value( + value, + black_color->color_g_y, + CRTCV_BLACK_COLOR, + CRTC_BLACK_COLOR_G_Y); + set_reg_field_value( + value, + black_color->color_r_cr, + CRTCV_BLACK_COLOR, + CRTC_BLACK_COLOR_R_CR); + + dm_write_reg(tg->ctx, addr, value); + + addr = mmCRTCV_BLANK_DATA_COLOR; + dm_write_reg(tg->ctx, addr, value); +} + +static void dce110_timing_generator_v_set_overscan_color(struct timing_generator *tg, + const struct tg_color *overscan_color) +{ + struct dc_context *ctx = tg->ctx; + uint32_t value = 0; + uint32_t addr; + + set_reg_field_value( + value, + overscan_color->color_b_cb, + CRTCV_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_BLUE); + + set_reg_field_value( + value, + overscan_color->color_g_y, + CRTCV_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_GREEN); + + set_reg_field_value( + value, + overscan_color->color_r_cr, + CRTCV_OVERSCAN_COLOR, + CRTC_OVERSCAN_COLOR_RED); + + addr = mmCRTCV_OVERSCAN_COLOR; + dm_write_reg(ctx, addr, value); +} + +static void dce110_timing_generator_v_set_colors(struct timing_generator *tg, + const struct tg_color *blank_color, + const struct tg_color *overscan_color) +{ + if (blank_color != NULL) + dce110_tg_v_program_blank_color(tg, blank_color); + if (overscan_color != NULL) + dce110_timing_generator_v_set_overscan_color(tg, overscan_color); +} + +static void dce110_timing_generator_v_set_early_control( + struct timing_generator *tg, + uint32_t early_cntl) +{ + uint32_t regval; + uint32_t address = mmCRTC_CONTROL; + + regval = dm_read_reg(tg->ctx, address); + set_reg_field_value(regval, early_cntl, + CRTCV_CONTROL, CRTC_HBLANK_EARLY_CONTROL); + dm_write_reg(tg->ctx, address, regval); +} + +static void dce110_timing_generator_v_get_crtc_positions( + struct timing_generator *tg, + int32_t *h_position, + int32_t *v_position) +{ + uint32_t value; + + value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); + + *h_position = get_reg_field_value( + value, + CRTCV_STATUS_POSITION, + CRTC_HORZ_COUNT); + + *v_position = get_reg_field_value( + value, + CRTCV_STATUS_POSITION, + CRTC_VERT_COUNT); +} + +static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg) +{ + uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT; + uint32_t value = dm_read_reg(tg->ctx, addr); + uint32_t field = get_reg_field_value( + value, CRTCV_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT); + + return field; +} + +static bool dce110_timing_generator_v_did_triggered_reset_occur( + struct timing_generator *tg) +{ + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "Timing Sync not supported on underlay pipe\n"); + return false; +} + +static void dce110_timing_generator_v_setup_global_swap_lock( + struct timing_generator *tg, + const struct dcp_gsl_params *gsl_params) +{ + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "Timing Sync not supported on underlay pipe\n"); + return; +} + +static void dce110_timing_generator_v_enable_reset_trigger( + struct timing_generator *tg, + int source_tg_inst) +{ + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "Timing Sync not supported on underlay pipe\n"); + return; +} + +static void dce110_timing_generator_v_disable_reset_trigger( + struct timing_generator *tg) +{ + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "Timing Sync not supported on underlay pipe\n"); + return; +} + +static void dce110_timing_generator_v_tear_down_global_swap_lock( + struct timing_generator *tg) +{ + dm_logger_write(tg->ctx->logger, LOG_ERROR, + "Timing Sync not supported on underlay pipe\n"); + return; +} + +static void dce110_timing_generator_v_disable_vga( + struct timing_generator *tg) +{ + return; +} + +static bool dce110_tg_v_is_blanked(struct timing_generator *tg) +{ + /* Signal comes from the primary pipe, underlay is never blanked. */ + return false; +} + +/** ******************************************************************************************** + * + * DCE11 Timing Generator Constructor / Destructor + * + *********************************************************************************************/ +static const struct timing_generator_funcs dce110_tg_v_funcs = { + .validate_timing = dce110_tg_validate_timing, + .program_timing = dce110_timing_generator_v_program_timing, + .enable_crtc = dce110_timing_generator_v_enable_crtc, + .disable_crtc = dce110_timing_generator_v_disable_crtc, + .is_counter_moving = dce110_timing_generator_v_is_counter_moving, + .get_position = dce110_timing_generator_v_get_crtc_positions, + .get_frame_count = dce110_timing_generator_v_get_vblank_counter, + .set_early_control = dce110_timing_generator_v_set_early_control, + .wait_for_state = dce110_timing_generator_v_wait_for_state, + .set_blank = dce110_timing_generator_v_set_blank, + .is_blanked = dce110_tg_v_is_blanked, + .set_colors = dce110_timing_generator_v_set_colors, + .set_overscan_blank_color = + dce110_timing_generator_v_set_overscan_color_black, + .set_blank_color = dce110_timing_generator_v_program_blank_color, + .disable_vga = dce110_timing_generator_v_disable_vga, + .did_triggered_reset_occur = + dce110_timing_generator_v_did_triggered_reset_occur, + .setup_global_swap_lock = + dce110_timing_generator_v_setup_global_swap_lock, + .enable_reset_trigger = dce110_timing_generator_v_enable_reset_trigger, + .disable_reset_trigger = dce110_timing_generator_v_disable_reset_trigger, + .tear_down_global_swap_lock = + dce110_timing_generator_v_tear_down_global_swap_lock, + .enable_advanced_request = + dce110_timing_generator_v_enable_advanced_request +}; + +bool dce110_timing_generator_v_construct( + struct dce110_timing_generator *tg110, + struct dc_context *ctx) +{ + if (!tg110) + return false; + + tg110->controller_id = CONTROLLER_ID_UNDERLAY0; + + tg110->base.funcs = &dce110_tg_v_funcs; + + tg110->base.ctx = ctx; + tg110->base.bp = ctx->dc_bios; + + tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; + tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; + + tg110->min_h_blank = 56; + tg110->min_h_front_porch = 4; + tg110->min_h_back_porch = 4; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h new file mode 100644 index 000000000000..7e49ca8e26ad --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h @@ -0,0 +1,33 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_TIMING_GENERATOR_V_DCE110_H__ +#define __DC_TIMING_GENERATOR_V_DCE110_H__ + +bool dce110_timing_generator_v_construct( + struct dce110_timing_generator *tg110, + struct dc_context *ctx); + +#endif /* __DC_TIMING_GENERATOR_V_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c new file mode 100644 index 000000000000..7d8cf7a58f46 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -0,0 +1,704 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce110_transform_v.h" +#include "dm_services.h" +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" + +#define SCLV_PHASES 64 + +struct sclv_ratios_inits { + uint32_t h_int_scale_ratio_luma; + uint32_t h_int_scale_ratio_chroma; + uint32_t v_int_scale_ratio_luma; + uint32_t v_int_scale_ratio_chroma; + struct init_int_and_frac h_init_luma; + struct init_int_and_frac h_init_chroma; + struct init_int_and_frac v_init_luma; + struct init_int_and_frac v_init_chroma; +}; + +static void calculate_viewport( + const struct scaler_data *scl_data, + struct rect *luma_viewport, + struct rect *chroma_viewport) +{ + /*Do not set chroma vp for rgb444 pixel format*/ + luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; + luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; + luma_viewport->width = + scl_data->viewport.width - scl_data->viewport.width % 2; + luma_viewport->height = + scl_data->viewport.height - scl_data->viewport.height % 2; + chroma_viewport->x = luma_viewport->x; + chroma_viewport->y = luma_viewport->y; + chroma_viewport->height = luma_viewport->height; + chroma_viewport->width = luma_viewport->width; + + if (scl_data->format == PIXEL_FORMAT_420BPP12) { + luma_viewport->height += luma_viewport->height % 2; + luma_viewport->width += luma_viewport->width % 2; + /*for 420 video chroma is 1/4 the area of luma, scaled + *vertically and horizontally + */ + chroma_viewport->x = luma_viewport->x / 2; + chroma_viewport->y = luma_viewport->y / 2; + chroma_viewport->height = luma_viewport->height / 2; + chroma_viewport->width = luma_viewport->width / 2; + } +} + +static void program_viewport( + struct dce_transform *xfm_dce, + struct rect *luma_view_port, + struct rect *chroma_view_port) +{ + struct dc_context *ctx = xfm_dce->base.ctx; + uint32_t value = 0; + uint32_t addr = 0; + + if (luma_view_port->width != 0 && luma_view_port->height != 0) { + addr = mmSCLV_VIEWPORT_START; + value = 0; + set_reg_field_value( + value, + luma_view_port->x, + SCLV_VIEWPORT_START, + VIEWPORT_X_START); + set_reg_field_value( + value, + luma_view_port->y, + SCLV_VIEWPORT_START, + VIEWPORT_Y_START); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_VIEWPORT_SIZE; + value = 0; + set_reg_field_value( + value, + luma_view_port->height, + SCLV_VIEWPORT_SIZE, + VIEWPORT_HEIGHT); + set_reg_field_value( + value, + luma_view_port->width, + SCLV_VIEWPORT_SIZE, + VIEWPORT_WIDTH); + dm_write_reg(ctx, addr, value); + } + + if (chroma_view_port->width != 0 && chroma_view_port->height != 0) { + addr = mmSCLV_VIEWPORT_START_C; + value = 0; + set_reg_field_value( + value, + chroma_view_port->x, + SCLV_VIEWPORT_START_C, + VIEWPORT_X_START_C); + set_reg_field_value( + value, + chroma_view_port->y, + SCLV_VIEWPORT_START_C, + VIEWPORT_Y_START_C); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_VIEWPORT_SIZE_C; + value = 0; + set_reg_field_value( + value, + chroma_view_port->height, + SCLV_VIEWPORT_SIZE_C, + VIEWPORT_HEIGHT_C); + set_reg_field_value( + value, + chroma_view_port->width, + SCLV_VIEWPORT_SIZE_C, + VIEWPORT_WIDTH_C); + dm_write_reg(ctx, addr, value); + } +} + +/* + * Function: + * void setup_scaling_configuration + * + * Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps + * Input: data + * + * Output: + * void + */ +static bool setup_scaling_configuration( + struct dce_transform *xfm_dce, + const struct scaler_data *data) +{ + bool is_scaling_needed = false; + struct dc_context *ctx = xfm_dce->base.ctx; + uint32_t value = 0; + + set_reg_field_value(value, data->taps.h_taps - 1, + SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS); + set_reg_field_value(value, data->taps.v_taps - 1, + SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS); + set_reg_field_value(value, data->taps.h_taps_c - 1, + SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C); + set_reg_field_value(value, data->taps.v_taps_c - 1, + SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C); + dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value); + + value = 0; + if (data->taps.h_taps + data->taps.v_taps > 2) { + set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE); + set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN); + is_scaling_needed = true; + } else { + set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE); + set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN); + } + + if (data->taps.h_taps_c + data->taps.v_taps_c > 2) { + set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C); + set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C); + is_scaling_needed = true; + } else if (data->format != PIXEL_FORMAT_420BPP12) { + set_reg_field_value( + value, + get_reg_field_value(value, SCLV_MODE, SCL_MODE), + SCLV_MODE, + SCL_MODE_C); + set_reg_field_value( + value, + get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN), + SCLV_MODE, + SCL_PSCL_EN_C); + } else { + set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C); + set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C); + } + dm_write_reg(ctx, mmSCLV_MODE, value); + + value = 0; + /* + * 0 - Replaced out of bound pixels with black pixel + * (or any other required color) + * 1 - Replaced out of bound pixels with the edge pixel + */ + set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE); + dm_write_reg(ctx, mmSCLV_CONTROL, value); + + return is_scaling_needed; +} + +/** +* Function: +* void program_overscan +* +* Purpose: Programs overscan border +* Input: overscan +* +* Output: + void +*/ +static void program_overscan( + struct dce_transform *xfm_dce, + const struct scaler_data *data) +{ + uint32_t overscan_left_right = 0; + uint32_t overscan_top_bottom = 0; + + int overscan_right = data->h_active - data->recout.x - data->recout.width; + int overscan_bottom = data->v_active - data->recout.y - data->recout.height; + + if (overscan_right < 0) { + BREAK_TO_DEBUGGER(); + overscan_right = 0; + } + if (overscan_bottom < 0) { + BREAK_TO_DEBUGGER(); + overscan_bottom = 0; + } + + set_reg_field_value(overscan_left_right, data->recout.x, + EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT); + + set_reg_field_value(overscan_left_right, overscan_right, + EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT); + + set_reg_field_value(overscan_top_bottom, data->recout.y, + EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP); + + set_reg_field_value(overscan_top_bottom, overscan_bottom, + EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM); + + dm_write_reg(xfm_dce->base.ctx, + mmSCLV_EXT_OVERSCAN_LEFT_RIGHT, + overscan_left_right); + + dm_write_reg(xfm_dce->base.ctx, + mmSCLV_EXT_OVERSCAN_TOP_BOTTOM, + overscan_top_bottom); +} + +static void set_coeff_update_complete( + struct dce_transform *xfm_dce) +{ + uint32_t value; + + value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE); + set_reg_field_value(value, 1, SCLV_UPDATE, SCL_COEF_UPDATE_COMPLETE); + dm_write_reg(xfm_dce->base.ctx, mmSCLV_UPDATE, value); +} + +static void program_multi_taps_filter( + struct dce_transform *xfm_dce, + int taps, + const uint16_t *coeffs, + enum ram_filter_type filter_type) +{ + struct dc_context *ctx = xfm_dce->base.ctx; + int i, phase, pair; + int array_idx = 0; + int taps_pairs = (taps + 1) / 2; + int phases_to_program = SCLV_PHASES / 2 + 1; + + uint32_t select = 0; + uint32_t power_ctl, power_ctl_off; + + if (!coeffs) + return; + + /*We need to disable power gating on coeff memory to do programming*/ + power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL); + power_ctl_off = power_ctl; + set_reg_field_value(power_ctl_off, 1, DCFEV_MEM_PWR_CTRL, SCLV_COEFF_MEM_PWR_DIS); + dm_write_reg(ctx, mmDCFEV_MEM_PWR_CTRL, power_ctl_off); + + /*Wait to disable gating:*/ + for (i = 0; i < 10; i++) { + if (get_reg_field_value( + dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS), + DCFEV_MEM_PWR_STATUS, + SCLV_COEFF_MEM_PWR_STATE) == 0) + break; + + udelay(1); + } + + set_reg_field_value(select, filter_type, SCLV_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE); + + for (phase = 0; phase < phases_to_program; phase++) { + /*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror + phase 0 is unique and phase N/2 is unique if N is even*/ + set_reg_field_value(select, phase, SCLV_COEF_RAM_SELECT, SCL_C_RAM_PHASE); + for (pair = 0; pair < taps_pairs; pair++) { + uint32_t data = 0; + + set_reg_field_value(select, pair, + SCLV_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX); + + dm_write_reg(ctx, mmSCLV_COEF_RAM_SELECT, select); + + set_reg_field_value( + data, 1, + SCLV_COEF_RAM_TAP_DATA, + SCL_C_RAM_EVEN_TAP_COEF_EN); + set_reg_field_value( + data, coeffs[array_idx], + SCLV_COEF_RAM_TAP_DATA, + SCL_C_RAM_EVEN_TAP_COEF); + + if (taps % 2 && pair == taps_pairs - 1) { + set_reg_field_value( + data, 0, + SCLV_COEF_RAM_TAP_DATA, + SCL_C_RAM_ODD_TAP_COEF_EN); + array_idx++; + } else { + set_reg_field_value( + data, 1, + SCLV_COEF_RAM_TAP_DATA, + SCL_C_RAM_ODD_TAP_COEF_EN); + set_reg_field_value( + data, coeffs[array_idx + 1], + SCLV_COEF_RAM_TAP_DATA, + SCL_C_RAM_ODD_TAP_COEF); + + array_idx += 2; + } + + dm_write_reg(ctx, mmSCLV_COEF_RAM_TAP_DATA, data); + } + } + + /*We need to restore power gating on coeff memory to initial state*/ + dm_write_reg(ctx, mmDCFEV_MEM_PWR_CTRL, power_ctl); +} + +static void calculate_inits( + struct dce_transform *xfm_dce, + const struct scaler_data *data, + struct sclv_ratios_inits *inits, + struct rect *luma_viewport, + struct rect *chroma_viewport) +{ + inits->h_int_scale_ratio_luma = + dal_fixed31_32_u2d19(data->ratios.horz) << 5; + inits->v_int_scale_ratio_luma = + dal_fixed31_32_u2d19(data->ratios.vert) << 5; + inits->h_int_scale_ratio_chroma = + dal_fixed31_32_u2d19(data->ratios.horz_c) << 5; + inits->v_int_scale_ratio_chroma = + dal_fixed31_32_u2d19(data->ratios.vert_c) << 5; + + inits->h_init_luma.integer = 1; + inits->v_init_luma.integer = 1; + inits->h_init_chroma.integer = 1; + inits->v_init_chroma.integer = 1; +} + +static void program_scl_ratios_inits( + struct dce_transform *xfm_dce, + struct sclv_ratios_inits *inits) +{ + struct dc_context *ctx = xfm_dce->base.ctx; + uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO; + uint32_t value = 0; + + set_reg_field_value( + value, + inits->h_int_scale_ratio_luma, + SCLV_HORZ_FILTER_SCALE_RATIO, + SCL_H_SCALE_RATIO); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_VERT_FILTER_SCALE_RATIO; + value = 0; + set_reg_field_value( + value, + inits->v_int_scale_ratio_luma, + SCLV_VERT_FILTER_SCALE_RATIO, + SCL_V_SCALE_RATIO); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C; + value = 0; + set_reg_field_value( + value, + inits->h_int_scale_ratio_chroma, + SCLV_HORZ_FILTER_SCALE_RATIO_C, + SCL_H_SCALE_RATIO_C); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C; + value = 0; + set_reg_field_value( + value, + inits->v_int_scale_ratio_chroma, + SCLV_VERT_FILTER_SCALE_RATIO_C, + SCL_V_SCALE_RATIO_C); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_HORZ_FILTER_INIT; + value = 0; + set_reg_field_value( + value, + inits->h_init_luma.fraction, + SCLV_HORZ_FILTER_INIT, + SCL_H_INIT_FRAC); + set_reg_field_value( + value, + inits->h_init_luma.integer, + SCLV_HORZ_FILTER_INIT, + SCL_H_INIT_INT); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_VERT_FILTER_INIT; + value = 0; + set_reg_field_value( + value, + inits->v_init_luma.fraction, + SCLV_VERT_FILTER_INIT, + SCL_V_INIT_FRAC); + set_reg_field_value( + value, + inits->v_init_luma.integer, + SCLV_VERT_FILTER_INIT, + SCL_V_INIT_INT); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_HORZ_FILTER_INIT_C; + value = 0; + set_reg_field_value( + value, + inits->h_init_chroma.fraction, + SCLV_HORZ_FILTER_INIT_C, + SCL_H_INIT_FRAC_C); + set_reg_field_value( + value, + inits->h_init_chroma.integer, + SCLV_HORZ_FILTER_INIT_C, + SCL_H_INIT_INT_C); + dm_write_reg(ctx, addr, value); + + addr = mmSCLV_VERT_FILTER_INIT_C; + value = 0; + set_reg_field_value( + value, + inits->v_init_chroma.fraction, + SCLV_VERT_FILTER_INIT_C, + SCL_V_INIT_FRAC_C); + set_reg_field_value( + value, + inits->v_init_chroma.integer, + SCLV_VERT_FILTER_INIT_C, + SCL_V_INIT_INT_C); + dm_write_reg(ctx, addr, value); +} + +static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) +{ + if (taps == 4) + return get_filter_4tap_64p(ratio); + else if (taps == 2) + return filter_2tap_64p; + else if (taps == 1) + return NULL; + else { + /* should never happen, bug */ + BREAK_TO_DEBUGGER(); + return NULL; + } +} + +static bool dce110_xfmv_power_up_line_buffer(struct transform *xfm) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + uint32_t value; + + value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL); + + /*Use all three pieces of memory always*/ + set_reg_field_value(value, 0, LBV_MEMORY_CTRL, LB_MEMORY_CONFIG); + /*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/ + set_reg_field_value(value, xfm_dce->lb_memory_size, LBV_MEMORY_CTRL, + LB_MEMORY_SIZE); + + dm_write_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL, value); + + return true; +} + +static void dce110_xfmv_set_scaler( + struct transform *xfm, + const struct scaler_data *data) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + bool is_scaling_required = false; + bool filter_updated = false; + const uint16_t *coeffs_v, *coeffs_h, *coeffs_h_c, *coeffs_v_c; + struct rect luma_viewport = {0}; + struct rect chroma_viewport = {0}; + + dce110_xfmv_power_up_line_buffer(xfm); + /* 1. Calculate viewport, viewport programming should happen after init + * calculations as they may require an adjustment in the viewport. + */ + + calculate_viewport(data, &luma_viewport, &chroma_viewport); + + /* 2. Program overscan */ + program_overscan(xfm_dce, data); + + /* 3. Program taps and configuration */ + is_scaling_required = setup_scaling_configuration(xfm_dce, data); + + if (is_scaling_required) { + /* 4. Calculate and program ratio, filter initialization */ + + struct sclv_ratios_inits inits = { 0 }; + + calculate_inits( + xfm_dce, + data, + &inits, + &luma_viewport, + &chroma_viewport); + + program_scl_ratios_inits(xfm_dce, &inits); + + coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); + coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); + coeffs_v_c = get_filter_coeffs_64p(data->taps.v_taps_c, data->ratios.vert_c); + coeffs_h_c = get_filter_coeffs_64p(data->taps.h_taps_c, data->ratios.horz_c); + + if (coeffs_v != xfm_dce->filter_v + || coeffs_v_c != xfm_dce->filter_v_c + || coeffs_h != xfm_dce->filter_h + || coeffs_h_c != xfm_dce->filter_h_c) { + /* 5. Program vertical filters */ + program_multi_taps_filter( + xfm_dce, + data->taps.v_taps, + coeffs_v, + FILTER_TYPE_RGB_Y_VERTICAL); + program_multi_taps_filter( + xfm_dce, + data->taps.v_taps_c, + coeffs_v_c, + FILTER_TYPE_CBCR_VERTICAL); + + /* 6. Program horizontal filters */ + program_multi_taps_filter( + xfm_dce, + data->taps.h_taps, + coeffs_h, + FILTER_TYPE_RGB_Y_HORIZONTAL); + program_multi_taps_filter( + xfm_dce, + data->taps.h_taps_c, + coeffs_h_c, + FILTER_TYPE_CBCR_HORIZONTAL); + + xfm_dce->filter_v = coeffs_v; + xfm_dce->filter_v_c = coeffs_v_c; + xfm_dce->filter_h = coeffs_h; + xfm_dce->filter_h_c = coeffs_h_c; + filter_updated = true; + } + } + + /* 7. Program the viewport */ + program_viewport(xfm_dce, &luma_viewport, &chroma_viewport); + + /* 8. Set bit to flip to new coefficient memory */ + if (filter_updated) + set_coeff_update_complete(xfm_dce); +} + +static void dce110_xfmv_reset(struct transform *xfm) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + + xfm_dce->filter_h = NULL; + xfm_dce->filter_v = NULL; + xfm_dce->filter_h_c = NULL; + xfm_dce->filter_v_c = NULL; +} + +static void dce110_xfmv_set_gamut_remap( + struct transform *xfm, + const struct xfm_grph_csc_adjustment *adjust) +{ + /* DO NOTHING*/ +} + +static void dce110_xfmv_set_pixel_storage_depth( + struct transform *xfm, + enum lb_pixel_depth depth, + const struct bit_depth_reduction_params *bit_depth_params) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + int pixel_depth, expan_mode; + uint32_t reg_data = 0; + + switch (depth) { + case LB_PIXEL_DEPTH_18BPP: + pixel_depth = 2; + expan_mode = 1; + break; + case LB_PIXEL_DEPTH_24BPP: + pixel_depth = 1; + expan_mode = 1; + break; + case LB_PIXEL_DEPTH_30BPP: + pixel_depth = 0; + expan_mode = 1; + break; + case LB_PIXEL_DEPTH_36BPP: + pixel_depth = 3; + expan_mode = 0; + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + set_reg_field_value( + reg_data, + expan_mode, + LBV_DATA_FORMAT, + PIXEL_EXPAN_MODE); + + set_reg_field_value( + reg_data, + pixel_depth, + LBV_DATA_FORMAT, + PIXEL_DEPTH); + + dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data); + + if (!(xfm_dce->lb_pixel_depth_supported & depth)) { + /*we should use unsupported capabilities + * unless it is required by w/a*/ + dm_logger_write(xfm->ctx->logger, LOG_WARNING, + "%s: Capability not supported", + __func__); + } +} + +static const struct transform_funcs dce110_xfmv_funcs = { + .transform_reset = dce110_xfmv_reset, + .transform_set_scaler = dce110_xfmv_set_scaler, + .transform_set_gamut_remap = + dce110_xfmv_set_gamut_remap, + .transform_set_pixel_storage_depth = + dce110_xfmv_set_pixel_storage_depth, + .transform_get_optimal_number_of_taps = + dce_transform_get_optimal_number_of_taps +}; +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +bool dce110_transform_v_construct( + struct dce_transform *xfm_dce, + struct dc_context *ctx) +{ + xfm_dce->base.ctx = ctx; + + xfm_dce->base.funcs = &dce110_xfmv_funcs; + + xfm_dce->lb_pixel_depth_supported = + LB_PIXEL_DEPTH_18BPP | + LB_PIXEL_DEPTH_24BPP | + LB_PIXEL_DEPTH_30BPP; + + xfm_dce->prescaler_on = true; + xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; + xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/ + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h new file mode 100644 index 000000000000..267af34db3e5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h @@ -0,0 +1,37 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TRANSFORM_V_DCE110_H__ +#define __DAL_TRANSFORM_V_DCE110_H__ + +#include "../dce/dce_transform.h" + +#define LB_TOTAL_NUMBER_OF_ENTRIES 1712 +#define LB_BITS_PER_ENTRY 144 + +bool dce110_transform_v_construct( + struct dce_transform *xfm110, + struct dc_context *ctx); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h new file mode 100644 index 000000000000..55f52382ddfb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h @@ -0,0 +1,30 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCE110_TYPES_H_ +#define __DCE110_TYPES_H_ + +#define GAMMA_SEGMENTS_NUM 16 + +#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_DCE110_DCE110_TYPES_H_ */ -- cgit v1.2.3-59-g8ed1b From 1293b4339fb09693bdfc938495b671f0ac9bfae5 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Tue, 29 Nov 2016 17:56:05 -0500 Subject: drm/amd/display: Block 3D Timings - we don't yet support 3D timings in DAL3 - somehow a code path was being executed that resulted in HW programming for a 3D timing, which caused 3D displays to show half the desktop in one frame, and the other half of the desktop in the next frame - blocking all 3D timings in timing generator validation until we implement proper 3D timing support Signed-off-by: Joshua Aberback Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index b1c97125f6fb..12a258763ef1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1113,6 +1113,10 @@ bool dce110_timing_generator_validate_timing( if (!timing) return false; + /* Currently we don't support 3D, so block all 3D timings */ + if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) + return false; + /* Check maximum number of pixels supported by Timing Generator * (Currently will never fail, in order to fail needs display which * needs more than 8192 horizontal and -- cgit v1.2.3-59-g8ed1b From 197062bf12d7a516ea96e24859fe5981e30ea9ff Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 30 Nov 2016 16:15:47 -0500 Subject: drm/amd/display: refactor DCE11 DVVM - move to new programming style - clean up table to make it obvious what we are programming Signed-off-by: Tony Cheng Reviewed-by: Zeyu Fan Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 135 ++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 59 +++++++-- .../drm/amd/display/dc/dce100/dce100_resource.c | 6 +- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 113 +---------------- .../drm/amd/display/dc/dce110/dce110_mem_input.h | 11 -- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 8 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 6 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 6 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 6 +- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +- 10 files changed, 201 insertions(+), 153 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 654731cccdcd..fd8a49afbec6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -35,6 +35,137 @@ #define FN(reg_name, field_name) \ mi->shifts->field_name, mi->masks->field_name +struct pte_setting { + unsigned int bpp; + unsigned int page_width; + unsigned int page_height; + unsigned char min_pte_before_flip_horiz_scan; + unsigned char min_pte_before_flip_vert_scan; + unsigned char pte_req_per_chunk; + unsigned char param_6; + unsigned char param_7; + unsigned char param_8; +}; + +enum mi_bits_per_pixel { + mi_bpp_8 = 0, + mi_bpp_16, + mi_bpp_32, + mi_bpp_64, + mi_bpp_count, +}; + +enum mi_tiling_format { + mi_tiling_linear = 0, + mi_tiling_1D, + mi_tiling_2D, + mi_tiling_count, +}; + +static const struct pte_setting pte_settings[mi_tiling_count][mi_bpp_count] = { + [mi_tiling_linear] = { + { 8, 4096, 1, 8, 0, 1, 0, 0, 0}, + { 16, 2048, 1, 8, 0, 1, 0, 0, 0}, + { 32, 1024, 1, 8, 0, 1, 0, 0, 0}, + { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */ + }, + [mi_tiling_1D] = { + { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */ + { 16, 256, 8, 2, 0, 1, 0, 0, 0}, + { 32, 128, 8, 4, 0, 1, 0, 0, 0}, + { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */ + }, + [mi_tiling_2D] = { + { 8, 64, 64, 8, 8, 1, 4, 0, 0}, + { 16, 64, 32, 8, 16, 1, 8, 0, 0}, + { 32, 32, 32, 16, 16, 1, 8, 0, 0}, + { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */ + }, +}; + +static enum mi_bits_per_pixel get_mi_bpp( + enum surface_pixel_format format) +{ + if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) + return mi_bpp_64; + else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) + return mi_bpp_32; + else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB1555) + return mi_bpp_16; + else + return mi_bpp_8; +} + +static enum mi_tiling_format get_mi_tiling( + union dc_tiling_info *tiling_info) +{ + switch (tiling_info->gfx8.array_mode) { + case DC_ARRAY_1D_TILED_THIN1: + case DC_ARRAY_1D_TILED_THICK: + case DC_ARRAY_PRT_TILED_THIN1: + return mi_tiling_1D; + case DC_ARRAY_2D_TILED_THIN1: + case DC_ARRAY_2D_TILED_THICK: + case DC_ARRAY_2D_TILED_X_THICK: + case DC_ARRAY_PRT_2D_TILED_THIN1: + case DC_ARRAY_PRT_2D_TILED_THICK: + return mi_tiling_2D; + case DC_ARRAY_LINEAR_GENERAL: + case DC_ARRAY_LINEAR_ALLIGNED: + return mi_tiling_linear; + default: + return mi_tiling_2D; + } +} + +static bool is_vert_scan(enum dc_rotation_angle rotation) +{ + switch (rotation) { + case ROTATION_ANGLE_90: + case ROTATION_ANGLE_270: + return true; + default: + return false; + } +} + +static unsigned int log_2(unsigned int num) +{ + unsigned int result = 0; + + while ((num >>= 1) != 0) + result++; + + return result; +} + +void dce_mem_input_program_pte_vm(struct mem_input *mi, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation) +{ + enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format); + enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); + const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp]; + + unsigned int page_width = log_2(pte->page_width); + unsigned int page_height = log_2(pte->page_height); + unsigned int min_pte_before_flip = is_vert_scan(rotation) ? + pte->min_pte_before_flip_vert_scan : + pte->min_pte_before_flip_horiz_scan; + + REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, + GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff); + + REG_UPDATE_3(DVMM_PTE_CONTROL, + DVMM_PAGE_WIDTH, page_width, + DVMM_PAGE_HEIGHT, page_height, + DVMM_MIN_PTE_BEFORE_FLIP, min_pte_before_flip); + + REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, + DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk, + DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff); +} static void program_urgency_watermark(struct mem_input *mi, uint32_t wm_select, @@ -244,7 +375,7 @@ static void program_grph_pixel_format( GRPH_PRESCALE_B_SIGN, sign); } -bool dce_mem_input_program_surface_config(struct mem_input *mi, +void dce_mem_input_program_surface_config(struct mem_input *mi, enum surface_pixel_format format, union dc_tiling_info *tiling_info, union plane_size *plane_size, @@ -260,8 +391,6 @@ bool dce_mem_input_program_surface_config(struct mem_input *mi, if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN && format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) program_grph_pixel_format(mi, format); - - return true; } static uint32_t get_dmif_switch_time_us( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index d5930a925fcb..a366b3a5b79d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -42,10 +42,22 @@ SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\ SRI(DMIF_BUFFER_CONTROL, PIPE, id) -#define MI_REG_LIST(id)\ +#define MI_DCE_PTE_REG_LIST(id)\ + SRI(DVMM_PTE_CONTROL, DCP, id),\ + SRI(DVMM_PTE_ARB_CONTROL, DCP, id) + +#define MI_DCE8_REG_LIST(id)\ MI_DCE_BASE_REG_LIST(id),\ SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id) +#define MI_DCE11_2_REG_LIST(id)\ + MI_DCE8_REG_LIST(id),\ + SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id) + +#define MI_DCE11_REG_LIST(id)\ + MI_DCE11_2_REG_LIST(id),\ + MI_DCE_PTE_REG_LIST(id) + struct dce_mem_input_registers { /* DCP */ uint32_t GRPH_ENABLE; @@ -58,6 +70,9 @@ struct dce_mem_input_registers { uint32_t HW_ROTATION; uint32_t GRPH_SWAP_CNTL; uint32_t PRESCALE_GRPH_CONTROL; + uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; + uint32_t DVMM_PTE_CONTROL; + uint32_t DVMM_PTE_ARB_CONTROL; /* DMIF_PG */ uint32_t DPG_PIPE_ARBITRATION_CONTROL1; uint32_t DPG_WATERMARK_MASK_CONTROL; @@ -103,6 +118,16 @@ struct dce_mem_input_registers { SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh) +#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh) + +#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\ + SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\ + SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\ + SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\ + SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh) + #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\ SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\ @@ -122,11 +147,19 @@ struct dce_mem_input_registers { SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh) -#define MI_DCE_MASK_SH_LIST(mask_sh)\ - MI_DCP_MASK_SH_LIST(mask_sh,),\ - MI_DMIF_PG_MASK_SH_LIST(mask_sh,),\ - MI_DMIF_PG_MASK_SH_DCE(mask_sh,),\ - MI_GFX8_TILE_MASK_SH_LIST(mask_sh,) +#define MI_DCE8_MASK_SH_LIST(mask_sh)\ + MI_DCP_MASK_SH_LIST(mask_sh, ),\ + MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\ + MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\ + MI_GFX8_TILE_MASK_SH_LIST(mask_sh, ) + +#define MI_DCE11_2_MASK_SH_LIST(mask_sh)\ + MI_DCE8_MASK_SH_LIST(mask_sh),\ + MI_DCP_DCE11_MASK_SH_LIST(mask_sh, ) + +#define MI_DCE11_MASK_SH_LIST(mask_sh)\ + MI_DCE11_2_MASK_SH_LIST(mask_sh),\ + MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) #define MI_REG_FIELD_LIST(type) \ type GRPH_ENABLE; \ @@ -142,6 +175,12 @@ struct dce_mem_input_registers { type GRPH_PRESCALE_R_SIGN; \ type GRPH_PRESCALE_G_SIGN; \ type GRPH_PRESCALE_B_SIGN; \ + type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \ + type DVMM_PAGE_WIDTH; \ + type DVMM_PAGE_HEIGHT; \ + type DVMM_MIN_PTE_BEFORE_FLIP; \ + type DVMM_PTE_REQ_PER_CHUNK; \ + type DVMM_MAX_PTE_REQ_OUTSTANDING; \ type GRPH_DEPTH; \ type GRPH_FORMAT; \ type GRPH_NUM_BANKS; \ @@ -191,7 +230,13 @@ struct dce_mem_input_wa { }; struct mem_input; -bool dce_mem_input_program_surface_config(struct mem_input *mi, + +void dce_mem_input_program_pte_vm(struct mem_input *mi, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + +void dce_mem_input_program_surface_config(struct mem_input *mi, enum surface_pixel_format format, union dc_tiling_info *tiling_info, union plane_size *plane_size, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 16595dc875a1..9ace6d1cca79 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -481,7 +481,7 @@ static const struct resource_create_funcs res_create_funcs = { }; #define mi_inst_regs(id) { \ - MI_REG_LIST(id), \ + MI_DCE8_REG_LIST(id), \ .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ } static const struct dce_mem_input_registers mi_regs[] = { @@ -494,12 +494,12 @@ static const struct dce_mem_input_registers mi_regs[] = { }; static const struct dce_mem_input_shift mi_shifts = { - MI_DCE_MASK_SH_LIST(__SHIFT), + MI_DCE8_MASK_SH_LIST(__SHIFT), .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT }; static const struct dce_mem_input_mask mi_masks = { - MI_DCE_MASK_SH_LIST(_MASK), + MI_DCE8_MASK_SH_LIST(_MASK), .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index c0a68c6f585e..af9d682f8943 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -150,117 +150,6 @@ bool dce110_mem_input_program_surface_flip_and_addr( return true; } -/* Scatter Gather param tables */ -static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = { - { 8, 64, 64, 8, 8, 1, 4, 0, 0}, - { 16, 64, 32, 8, 16, 1, 8, 0, 0}, - { 32, 32, 32, 16, 16, 1, 8, 0, 0}, - { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */ -}; - -static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = { - { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */ - { 16, 256, 8, 2, 0, 1, 0, 0, 0}, - { 32, 128, 8, 4, 0, 1, 0, 0, 0}, - { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */ -}; - -static const unsigned int dvmm_Hw_Setting_Linear[4][9] = { - { 8, 4096, 1, 8, 0, 1, 0, 0, 0}, - { 16, 2048, 1, 8, 0, 1, 0, 0, 0}, - { 32, 1024, 1, 8, 0, 1, 0, 0, 0}, - { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */ -}; - -/* Helper to get table entry from surface info */ -static const unsigned int *get_dvmm_hw_setting( - union dc_tiling_info *tiling_info, - enum surface_pixel_format format) -{ - enum bits_per_pixel { - bpp_8 = 0, - bpp_16, - bpp_32, - bpp_64 - } bpp; - - if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) - bpp = bpp_64; - else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) - bpp = bpp_32; - else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB1555) - bpp = bpp_16; - else - bpp = bpp_8; - - switch (tiling_info->gfx8.array_mode) { - case DC_ARRAY_1D_TILED_THIN1: - case DC_ARRAY_1D_TILED_THICK: - case DC_ARRAY_PRT_TILED_THIN1: - return dvmm_Hw_Setting_1DTiling[bpp]; - case DC_ARRAY_2D_TILED_THIN1: - case DC_ARRAY_2D_TILED_THICK: - case DC_ARRAY_2D_TILED_X_THICK: - case DC_ARRAY_PRT_2D_TILED_THIN1: - case DC_ARRAY_PRT_2D_TILED_THICK: - return dvmm_Hw_Setting_2DTiling[bpp]; - case DC_ARRAY_LINEAR_GENERAL: - case DC_ARRAY_LINEAR_ALLIGNED: - return dvmm_Hw_Setting_Linear[bpp]; - default: - return dvmm_Hw_Setting_2DTiling[bpp]; - } -} - -bool dce110_mem_input_program_pte_vm( - struct mem_input *mem_input, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - enum dc_rotation_angle rotation) -{ - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); - const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format); - - unsigned int page_width = 0; - unsigned int page_height = 0; - unsigned int temp_page_width = pte[1]; - unsigned int temp_page_height = pte[2]; - unsigned int min_pte_before_flip = 0; - uint32_t value = 0; - - while ((temp_page_width >>= 1) != 0) - page_width++; - while ((temp_page_height >>= 1) != 0) - page_height++; - - switch (rotation) { - case ROTATION_ANGLE_90: - case ROTATION_ANGLE_270: - min_pte_before_flip = pte[4]; - break; - default: - min_pte_before_flip = pte[3]; - break; - } - - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT)); - set_reg_field_value(value, 0xff, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT), value); - - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_CONTROL)); - set_reg_field_value(value, page_width, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH); - set_reg_field_value(value, page_height, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT); - set_reg_field_value(value, min_pte_before_flip, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_CONTROL), value); - - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_ARB_CONTROL)); - set_reg_field_value(value, pte[5], DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK); - set_reg_field_value(value, 0xff, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_ARB_CONTROL), value); - - return true; -} - static void program_urgency_watermark( const struct dc_context *ctx, const uint32_t offset, @@ -502,7 +391,7 @@ static struct mem_input_funcs dce110_mem_input_funcs = { .mem_input_program_surface_flip_and_addr = dce110_mem_input_program_surface_flip_and_addr, .mem_input_program_pte_vm = - dce110_mem_input_program_pte_vm, + dce_mem_input_program_pte_vm, .mem_input_program_surface_config = dce_mem_input_program_surface_config, .mem_input_is_flip_pending = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h index 83b2df93ce49..a80a20c09da4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h @@ -107,17 +107,6 @@ bool dce110_mem_input_program_surface_config( struct dc_plane_dcc_param *dcc, bool horizontal_mirror); -/* - * dce110_mem_input_program_pte_vm - * - * This function will program pte vm registers. - */ -bool dce110_mem_input_program_pte_vm( - struct mem_input *mem_input, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - enum dc_rotation_angle rotation); - /* * dce110_mem_input_is_flip_pending * diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index f0310bab4030..757e946d0837 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -584,7 +584,7 @@ static const unsigned int *get_dvmm_hw_setting( } } -bool dce110_mem_input_v_program_pte_vm( +void dce110_mem_input_v_program_pte_vm( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, @@ -655,11 +655,9 @@ bool dce110_mem_input_v_program_pte_vm( set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C); set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C); dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C), value); - - return true; } -bool dce110_mem_input_v_program_surface_config( +void dce110_mem_input_v_program_surface_config( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, @@ -674,8 +672,6 @@ bool dce110_mem_input_v_program_surface_config( program_tiling(mem_input110, tiling_info, format); program_size_and_rotation(mem_input110, rotation, plane_size); program_pixel_format(mem_input110, format); - - return true; } static void program_urgency_watermark( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 959467fa421e..cac3dc425039 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -474,7 +474,7 @@ static const struct resource_create_funcs res_create_funcs = { }; #define mi_inst_regs(id) { \ - MI_REG_LIST(id), \ + MI_DCE11_REG_LIST(id), \ .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ } static const struct dce_mem_input_registers mi_regs[] = { @@ -484,12 +484,12 @@ static const struct dce_mem_input_registers mi_regs[] = { }; static const struct dce_mem_input_shift mi_shifts = { - MI_DCE_MASK_SH_LIST(__SHIFT), + MI_DCE11_MASK_SH_LIST(__SHIFT), .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT }; static const struct dce_mem_input_mask mi_masks = { - MI_DCE_MASK_SH_LIST(_MASK), + MI_DCE11_MASK_SH_LIST(_MASK), .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK }; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index bfb2c3fcd2cb..4e3273c0fa91 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -495,7 +495,7 @@ static const struct resource_create_funcs res_create_funcs = { .create_hwseq = dce112_hwseq_create, }; -#define mi_inst_regs(id) { MI_REG_LIST(id) } +#define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } static const struct dce_mem_input_registers mi_regs[] = { mi_inst_regs(0), mi_inst_regs(1), @@ -506,11 +506,11 @@ static const struct dce_mem_input_registers mi_regs[] = { }; static const struct dce_mem_input_shift mi_shifts = { - MI_DCE_MASK_SH_LIST(__SHIFT) + MI_DCE11_2_MASK_SH_LIST(__SHIFT) }; static const struct dce_mem_input_mask mi_masks = { - MI_DCE_MASK_SH_LIST(_MASK) + MI_DCE11_2_MASK_SH_LIST(_MASK) }; static struct mem_input *dce112_mem_input_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 06720407b6fc..3b626b7883d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -462,7 +462,7 @@ static const struct resource_create_funcs res_create_funcs = { }; #define mi_inst_regs(id) { \ - MI_REG_LIST(id), \ + MI_DCE8_REG_LIST(id), \ .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ } static const struct dce_mem_input_registers mi_regs[] = { @@ -475,12 +475,12 @@ static const struct dce_mem_input_registers mi_regs[] = { }; static const struct dce_mem_input_shift mi_shifts = { - MI_DCE_MASK_SH_LIST(__SHIFT), + MI_DCE8_MASK_SH_LIST(__SHIFT), .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT }; static const struct dce_mem_input_mask mi_masks = { - MI_DCE_MASK_SH_LIST(_MASK), + MI_DCE8_MASK_SH_LIST(_MASK), .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 78dab74edc2d..80566c844758 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -82,13 +82,13 @@ struct mem_input_funcs { const struct dc_plane_address *address, bool flip_immediate); - bool (*mem_input_program_pte_vm)( + void (*mem_input_program_pte_vm)( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, enum dc_rotation_angle rotation); - bool (*mem_input_program_surface_config)( + void (*mem_input_program_surface_config)( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, -- cgit v1.2.3-59-g8ed1b From 1a687574a71f187dedcab3ac6012b0889c5a4e99 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 30 Nov 2016 10:49:51 -0500 Subject: drm/amd/display: restyle display clock calls part 1 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 48 ++++------------------ .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- .../display/dc/gpu/dce112/display_clock_dce112.c | 1 - .../display/dc/gpu/dce112/display_clock_dce112.h | 1 - drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 20 --------- drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 30 -------------- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 - .../amd/display/include/display_clock_interface.h | 35 ++++++++++++---- 12 files changed, 42 insertions(+), 107 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 424a7d4b8731..70dc70685471 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1224,7 +1224,9 @@ bool dc_pre_update_surfaces_to_target( if (prev_disp_clk < context->bw_results.dispclk_khz) { pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg); - core_dc->hwss.set_display_clock(context); + context->res_ctx.pool->display_clock->funcs->set_clock( + context->res_ctx.pool->display_clock, + context->bw_results.dispclk_khz * 115 / 100); core_dc->current_context->bw_results.dispclk_khz = context->bw_results.dispclk_khz; } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 9ace6d1cca79..8f18a9403525 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -984,7 +984,7 @@ static bool construct( dce110_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - dal_display_clock_store_max_clocks_state( + pool->base.display_clock->funcs->store_max_clocks_state( pool->base.display_clock, max_clocks_state); } { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1a682996b531..16ee49dba97b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -497,8 +497,8 @@ static void build_audio_output( if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { audio_output->pll_info.dp_dto_source_clock_in_khz = - dal_display_clock_get_dp_ref_clk_frequency( - pipe_ctx->dis_clk); + pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( + pipe_ctx->dis_clk); } audio_output->pll_info.feed_back_divider = @@ -788,39 +788,6 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); } -/** - * Call display_engine_clock_dce80 to perform the Dclk programming. - */ -void dce110_set_display_clock(struct validate_context *context) -{ - /* Program the display engine clock. - * Check DFS bypass mode support or not. DFSbypass feature is only when - * BIOS GPU info table reports support. */ - - if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) { - /*TODO: set_display_clock_dfs_bypass( - hws, - path_set, - context->res_ctx.pool->display_clock, - context->res_ctx.min_clocks.min_dclk_khz);*/ - } else { - /* - * TODO: need to either port work around from DAL2 function - * getActualRequiredDisplayClock or program displayclock without - * calling vbios. Currently temporily work - * around by increasing the displclk by 15 percent - */ - dal_display_clock_set_clock( - context->res_ctx.pool->display_clock, - context->bw_results.dispclk_khz * 115 / 100); - } - - - /* TODO: When changing display engine clock, DMCU WaitLoop must be - * reconfigured in order to maintain the same delays within DMCU - * programming sequences. */ -} - static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, const struct core_stream *stream) @@ -1267,8 +1234,10 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); if (context->bw_results.dispclk_khz - > dc->current_context->bw_results.dispclk_khz) - dc->hwss.set_display_clock(context); + > dc->current_context->bw_results.dispclk_khz) + context->res_ctx.pool->display_clock->funcs->set_clock( + context->res_ctx.pool->display_clock, + context->bw_results.dispclk_khz * 115 / 100); for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = @@ -1738,7 +1707,9 @@ static void dce110_set_bandwidth(struct core_dc *dc) program_wm_for_pipe(dc, pipe_ctx, dc->current_context); } - dc->hwss.set_display_clock(dc->current_context); + dc->current_context->res_ctx.pool->display_clock->funcs->set_clock( + dc->current_context->res_ctx.pool->display_clock, + dc->current_context->bw_results.dispclk_khz * 115 / 100); } static void dce110_program_front_end_for_pipe( @@ -1959,7 +1930,6 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_display_power_gating = dce110_enable_display_power_gating, .power_down_front_end = dce110_power_down_fe, .pipe_control_lock = dce_pipe_control_lock, - .set_display_clock = dce110_set_display_clock, .set_displaymarks = dce110_set_displaymarks, .increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe, .set_bandwidth = dce110_set_bandwidth, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index cac3dc425039..a63112b2bd36 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1315,7 +1315,7 @@ static bool construct( dce110_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - dal_display_clock_store_max_clocks_state( + pool->base.display_clock->funcs->store_max_clocks_state( pool->base.display_clock, max_clocks_state); } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 4e3273c0fa91..70616019ae47 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1315,7 +1315,7 @@ static bool construct( dce110_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - dal_display_clock_store_max_clocks_state( + pool->base.display_clock->funcs->store_max_clocks_state( pool->base.display_clock, max_clocks_state); } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 3b626b7883d4..dfff2bfff13d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -978,7 +978,7 @@ static bool construct( dce80_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - dal_display_clock_store_max_clocks_state( + pool->base.display_clock->funcs->store_max_clocks_state( pool->base.display_clock, max_clocks_state); } diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c index bf044260c0bb..665832b0718a 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c @@ -383,7 +383,6 @@ bool dal_display_clock_dce112_construct( struct display_clock *dc_base = &dc112->disp_clk_base; dc_base->ctx = ctx; - dc_base->id = CLOCK_SOURCE_ID_DCPLL; dc_base->min_display_clk_threshold_khz = 0; dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID; diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h index 5ab31185d29d..47a149709d91 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h @@ -32,7 +32,6 @@ struct display_clock_dce112 { /* Max display block clocks state*/ enum clocks_state max_clks_state; bool use_max_disp_clk; - uint32_t crystal_freq_khz; uint32_t dentist_vco_freq_khz; /* Cache the status of DFS-bypass feature*/ bool dfs_bypass_enabled; diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c index 73d982732a67..c70c6b25892e 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c @@ -38,13 +38,6 @@ void dal_display_clock_destroy(struct display_clock **disp_clk) *disp_clk = NULL; } -void dal_display_clock_set_clock( - struct display_clock *disp_clk, - uint32_t requested_clock_khz) -{ - disp_clk->funcs->set_clock(disp_clk, requested_clock_khz); -} - bool dal_display_clock_get_min_clocks_state( struct display_clock *disp_clk, enum clocks_state *clocks_state) @@ -80,16 +73,3 @@ bool dal_display_clock_set_min_clocks_state( return true; } -uint32_t dal_display_clock_get_dp_ref_clk_frequency( - struct display_clock *disp_clk) -{ - return disp_clk->funcs->get_dp_ref_clk_frequency(disp_clk); -} - -void dal_display_clock_store_max_clocks_state( - struct display_clock *disp_clk, - enum clocks_state max_clocks_state) -{ - disp_clk->funcs->store_max_clocks_state(disp_clk, max_clocks_state); -} - diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h index 4db8442e717a..68d2ab0500a6 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h @@ -28,34 +28,4 @@ #include "include/display_clock_interface.h" -struct display_clock_funcs { - void (*destroy)(struct display_clock **to_destroy); - void (*set_clock)(struct display_clock *disp_clk, - uint32_t requested_clock_khz); - enum clocks_state (*get_min_clocks_state)( - struct display_clock *disp_clk); - enum clocks_state (*get_required_clocks_state)( - struct display_clock *disp_clk, - struct state_dependent_clocks *req_clocks); - bool (*set_min_clocks_state)(struct display_clock *disp_clk, - enum clocks_state clocks_state); - uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); - void (*store_max_clocks_state)(struct display_clock *disp_clk, - enum clocks_state max_clocks_state); - -}; - -struct display_clock { - struct dc_context *ctx; - const struct display_clock_funcs *funcs; - uint32_t min_display_clk_threshold_khz; - enum clock_source_id id; - - enum clocks_state cur_min_clks_state; -}; -void dal_display_clock_store_max_clocks_state( - struct display_clock *disp_clk, - enum clocks_state max_clocks_state); - - #endif /* __DAL_DISPLAY_CLOCK_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 35a556dd9054..50d499cc01a4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -132,8 +132,6 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, struct validate_context *context); - void (*set_display_clock)(struct validate_context *context); - void (*set_bandwidth)(struct core_dc *dc); void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h index ef519a284e0f..f49253714b1e 100644 --- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h +++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h @@ -56,7 +56,31 @@ struct state_dependent_clocks { uint32_t pixel_clk_khz; }; -struct display_clock; +struct display_clock { + struct dc_context *ctx; + const struct display_clock_funcs *funcs; + uint32_t min_display_clk_threshold_khz; + enum clock_source_id id; + + enum clocks_state cur_min_clks_state; +}; + +struct display_clock_funcs { + void (*destroy)(struct display_clock **to_destroy); + void (*set_clock)(struct display_clock *disp_clk, + uint32_t requested_clock_khz); + enum clocks_state (*get_min_clocks_state)( + struct display_clock *disp_clk); + enum clocks_state (*get_required_clocks_state)( + struct display_clock *disp_clk, + struct state_dependent_clocks *req_clocks); + bool (*set_min_clocks_state)(struct display_clock *disp_clk, + enum clocks_state clocks_state); + uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); + void (*store_max_clocks_state)(struct display_clock *disp_clk, + enum clocks_state max_clocks_state); + +}; struct display_clock *dal_display_clock_dce112_create( struct dc_context *ctx); @@ -68,9 +92,7 @@ struct display_clock *dal_display_clock_dce80_create( struct dc_context *ctx); void dal_display_clock_destroy(struct display_clock **to_destroy); -void dal_display_clock_set_clock( - struct display_clock *disp_clk, - uint32_t requested_clock_khz); + bool dal_display_clock_get_min_clocks_state( struct display_clock *disp_clk, enum clocks_state *clocks_state); @@ -81,10 +103,5 @@ bool dal_display_clock_get_required_clocks_state( bool dal_display_clock_set_min_clocks_state( struct display_clock *disp_clk, enum clocks_state clocks_state); -uint32_t dal_display_clock_get_dp_ref_clk_frequency( - struct display_clock *disp_clk); -void dal_display_clock_store_max_clocks_state( - struct display_clock *disp_clk, - enum clocks_state max_clocks_state); #endif /* __DISPLAY_CLOCK_INTERFACE_H__ */ -- cgit v1.2.3-59-g8ed1b From 5d6d185f32eb0cce16caff13e716d08b594a6046 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 30 Nov 2016 11:03:37 -0500 Subject: drm/amd/display: restyle display clock calls part 2 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 ++-- .../drm/amd/display/dc/dce100/dce100_resource.c | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++-- .../drm/amd/display/dc/dce110/dce110_resource.c | 4 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- drivers/gpu/drm/amd/display/dc/gpu/Makefile | 2 +- .../display/dc/gpu/dce110/display_clock_dce110.h | 2 +- .../display/dc/gpu/dce112/display_clock_dce112.h | 2 +- .../amd/display/dc/gpu/dce80/display_clock_dce80.h | 2 +- drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 75 ---------------------- drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 31 --------- .../amd/display/include/display_clock_interface.h | 11 ---- 13 files changed, 30 insertions(+), 135 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.c delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 70a25546de1e..ab4efde2d030 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1223,12 +1223,13 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) if (link_settings.link_rate == max_link_rate) { cur_min_clock_state = CLOCKS_STATE_INVALID; - if (dal_display_clock_get_min_clocks_state( - pipe_ctx->dis_clk, &cur_min_clock_state)) { + if (pipe_ctx->dis_clk->funcs->get_min_clocks_state) { + cur_min_clock_state = + pipe_ctx->dis_clk->funcs->get_min_clocks_state( + pipe_ctx->dis_clk); if (cur_min_clock_state < CLOCKS_STATE_NOMINAL) - dal_display_clock_set_min_clocks_state( - pipe_ctx->dis_clk, - CLOCKS_STATE_NOMINAL); + pipe_ctx->dis_clk->funcs->set_min_clocks_state( + pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL); } else { } } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 8f18a9403525..fa88eb163ab8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -717,7 +717,9 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.display_clock != NULL) - dal_display_clock_destroy(&pool->base.display_clock); + pool->base.display_clock->funcs->destroy( + &pool->base.display_clock); + pool->base.display_clock = NULL; if (pool->base.irqs != NULL) dal_irq_service_destroy(&pool->base.irqs); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 16ee49dba97b..ca71509af74d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1099,9 +1099,11 @@ static void apply_min_clocks( if (!pre_mode_set) { /* set clock_state without verification */ - if (dal_display_clock_set_min_clocks_state( - pipe_ctx->dis_clk, *clocks_state)) + if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { + pipe_ctx->dis_clk->funcs->set_min_clocks_state( + pipe_ctx->dis_clk, *clocks_state); return; + } /* TODOFPGA */ } @@ -1114,9 +1116,10 @@ static void apply_min_clocks( req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( dc, context, true); - if (dal_display_clock_get_required_clocks_state( - pipe_ctx->dis_clk, &req_clocks, clocks_state)) { - dal_display_clock_set_min_clocks_state( + if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { + *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( + pipe_ctx->dis_clk, &req_clocks); + pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, *clocks_state); } else { } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index a63112b2bd36..6c713396e6ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -700,7 +700,9 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.display_clock != NULL) { - dal_display_clock_destroy(&pool->base.display_clock); + pool->base.display_clock->funcs->destroy( + &pool->base.display_clock); + pool->base.display_clock = NULL; } if (pool->base.irqs != NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 70616019ae47..8792c4ed6e65 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -734,7 +734,9 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.display_clock != NULL) { - dal_display_clock_destroy(&pool->base.display_clock); + pool->base.display_clock->funcs->destroy( + &pool->base.display_clock); + pool->base.display_clock = NULL; } if (pool->base.irqs != NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index dfff2bfff13d..1e829f805d42 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -657,7 +657,9 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.display_clock != NULL) { - dal_display_clock_destroy(&pool->base.display_clock); + pool->base.display_clock->funcs->destroy( + &pool->base.display_clock); + pool->base.display_clock = NULL; } if (pool->base.irqs != NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/gpu/Makefile b/drivers/gpu/drm/amd/display/dc/gpu/Makefile index fd17af1ce88e..0b99a7474950 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpu/Makefile @@ -3,7 +3,7 @@ # It provides the control and status of HW adapter resources, # that are global for the ASIC and sharable between pipes. -GPU = display_clock.o divider_range.o +GPU = divider_range.o AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU)) diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h index 88b4bdd75e56..703cd656b5b0 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h @@ -25,7 +25,7 @@ #ifndef __DAL_DISPLAY_CLOCK_DCE110_H__ #define __DAL_DISPLAY_CLOCK_DCE110_H__ -#include "gpu/display_clock.h" +#include "display_clock_interface.h" struct display_clock_dce110 { struct display_clock disp_clk_base; diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h index 47a149709d91..34afff9a00bc 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h @@ -25,7 +25,7 @@ #ifndef __DAL_DISPLAY_CLOCK_DCE112_H__ #define __DAL_DISPLAY_CLOCK_DCE112_H__ -#include "gpu/display_clock.h" +#include "display_clock_interface.h" struct display_clock_dce112 { struct display_clock disp_clk_base; diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h index c675f1e30870..273a5d902840 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h @@ -25,7 +25,7 @@ #ifndef __DAL_DISPLAY_CLOCK_DCE80_H__ #define __DAL_DISPLAY_CLOCK_DCE80_H__ -#include "gpu/display_clock.h" +#include "display_clock_interface.h" struct display_clock_dce80 { struct display_clock disp_clk; diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c deleted file mode 100644 index c70c6b25892e..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "display_clock.h" - -void dal_display_clock_destroy(struct display_clock **disp_clk) -{ - if (!disp_clk || !*disp_clk) { - BREAK_TO_DEBUGGER(); - return; - } - - (*disp_clk)->funcs->destroy(disp_clk); - - *disp_clk = NULL; -} - -bool dal_display_clock_get_min_clocks_state( - struct display_clock *disp_clk, - enum clocks_state *clocks_state) -{ - if (!disp_clk->funcs->get_min_clocks_state) - return false; - - *clocks_state = disp_clk->funcs->get_min_clocks_state(disp_clk); - return true; -} - -bool dal_display_clock_get_required_clocks_state( - struct display_clock *disp_clk, - struct state_dependent_clocks *req_clocks, - enum clocks_state *clocks_state) -{ - if (!disp_clk->funcs->get_required_clocks_state) - return false; - - *clocks_state = disp_clk->funcs->get_required_clocks_state( - disp_clk, req_clocks); - return true; -} - -bool dal_display_clock_set_min_clocks_state( - struct display_clock *disp_clk, - enum clocks_state clocks_state) -{ - if (!disp_clk->funcs->set_min_clocks_state) - return false; - - disp_clk->funcs->set_min_clocks_state(disp_clk, clocks_state); - return true; -} - diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h deleted file mode 100644 index 68d2ab0500a6..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DAL_DISPLAY_CLOCK_H__ -#define __DAL_DISPLAY_CLOCK_H__ - -#include "include/display_clock_interface.h" - -#endif /* __DAL_DISPLAY_CLOCK_H__*/ diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h index f49253714b1e..a46ceebe2452 100644 --- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h +++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h @@ -93,15 +93,4 @@ struct display_clock *dal_display_clock_dce80_create( void dal_display_clock_destroy(struct display_clock **to_destroy); -bool dal_display_clock_get_min_clocks_state( - struct display_clock *disp_clk, - enum clocks_state *clocks_state); -bool dal_display_clock_get_required_clocks_state( - struct display_clock *disp_clk, - struct state_dependent_clocks *req_clocks, - enum clocks_state *clocks_state); -bool dal_display_clock_set_min_clocks_state( - struct display_clock *disp_clk, - enum clocks_state clocks_state); - #endif /* __DISPLAY_CLOCK_INTERFACE_H__ */ -- cgit v1.2.3-59-g8ed1b From 3bad7c5ccfacca7a893b2960d872878d75a151d7 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 30 Nov 2016 14:26:37 -0500 Subject: drm/amd/display: remove store clock state Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce100/dce100_resource.c | 8 +--- .../drm/amd/display/dc/dce110/dce110_resource.c | 8 +--- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +--- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 +--- .../display/dc/gpu/dce110/display_clock_dce110.c | 47 +++----------------- .../display/dc/gpu/dce110/display_clock_dce110.h | 2 - .../display/dc/gpu/dce112/display_clock_dce112.c | 50 +++------------------- .../display/dc/gpu/dce112/display_clock_dce112.h | 2 - .../amd/display/dc/gpu/dce80/display_clock_dce80.c | 50 +++------------------- .../amd/display/dc/gpu/dce80/display_clock_dce80.h | 2 - .../amd/display/include/display_clock_interface.h | 5 +-- 11 files changed, 29 insertions(+), 161 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index fa88eb163ab8..446f50bb4e0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -981,14 +981,10 @@ static bool construct( /* get static clock information for PPLIB or firmware, save * max_clock_state */ - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) { - enum clocks_state max_clocks_state = + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) + pool->base.display_clock->max_clks_state = dce110_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - - pool->base.display_clock->funcs->store_max_clocks_state( - pool->base.display_clock, max_clocks_state); - } { struct irq_service_init_data init_data; init_data.ctx = dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 6c713396e6ba..d5d888bdf882 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1312,15 +1312,11 @@ static bool construct( /* get static clock information for PPLIB or firmware, save * max_clock_state */ - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) { - enum clocks_state max_clocks_state = + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) + pool->base.display_clock->max_clks_state = dce110_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - pool->base.display_clock->funcs->store_max_clocks_state( - pool->base.display_clock, max_clocks_state); - } - { struct irq_service_init_data init_data; init_data.ctx = dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 8792c4ed6e65..9903c9a4b8a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1312,15 +1312,11 @@ static bool construct( /* get static clock information for PPLIB or firmware, save * max_clock_state */ - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) { - enum clocks_state max_clocks_state = + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) + pool->base.display_clock->max_clks_state = dce110_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - pool->base.display_clock->funcs->store_max_clocks_state( - pool->base.display_clock, max_clocks_state); - } - { struct irq_service_init_data init_data; init_data.ctx = dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 1e829f805d42..51721d10c811 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -975,15 +975,11 @@ static bool construct( } - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) { - enum clocks_state max_clocks_state = + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) + pool->base.display_clock->max_clks_state = dce80_resource_convert_clock_state_pp_to_dc( static_clk_info.max_clocks_state); - pool->base.display_clock->funcs->store_max_clocks_state( - pool->base.display_clock, max_clocks_state); - } - { struct irq_service_init_data init_data; init_data.ctx = dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c index cc13afa326ad..ad7ebc1b434c 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c @@ -103,38 +103,6 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; * static functions *****************************************************************************/ -/* - * store_max_clocks_state - * - * @brief - * Cache the clock state - * - * @param - * struct display_clock *base - [out] cach the state in this structure - * enum clocks_state max_clocks_state - [in] state to be stored - */ -static void store_max_clocks_state( - struct display_clock *base, - enum clocks_state max_clocks_state) -{ - struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base); - - switch (max_clocks_state) { - case CLOCKS_STATE_LOW: - case CLOCKS_STATE_NOMINAL: - case CLOCKS_STATE_PERFORMANCE: - case CLOCKS_STATE_ULTRA_LOW: - dc->max_clks_state = max_clocks_state; - break; - - case CLOCKS_STATE_INVALID: - default: - /*Invalid Clocks State!*/ - ASSERT_CRITICAL(false); - break; - } -} - static enum clocks_state get_min_clocks_state(struct display_clock *base) { return base->cur_min_clks_state; @@ -148,7 +116,7 @@ static bool set_min_clocks_state( struct dm_pp_power_level_change_request level_change_req = { DM_PP_POWER_LEVEL_INVALID}; - if (clocks_state > dc->max_clks_state) { + if (clocks_state > base->max_clks_state) { /*Requested state exceeds max supported state.*/ dm_logger_write(base->ctx->logger, LOG_WARNING, "Requested state exceeds max supported state"); @@ -349,7 +317,7 @@ static enum clocks_state get_required_clocks_state( { int32_t i; struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc); - enum clocks_state low_req_clk = disp_clk->max_clks_state; + enum clocks_state low_req_clk = dc->max_clks_state; if (!req_clocks) { /* NULL pointer*/ @@ -363,7 +331,7 @@ static enum clocks_state get_required_clocks_state( * lowest RequiredState with the lowest state that satisfies * all required clocks */ - for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { + for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { if ((req_clocks->display_clk_khz <= max_clks_by_state[i].display_clk_khz) && (req_clocks->pixel_clk_khz <= @@ -433,7 +401,7 @@ static void set_clock( base->min_display_clk_threshold_khz); pxl_clk_params.target_pixel_clock = requested_clk_khz; - pxl_clk_params.pll_id = base->id; + pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); @@ -459,8 +427,7 @@ static const struct display_clock_funcs funcs = { .get_min_clocks_state = get_min_clocks_state, .get_required_clocks_state = get_required_clocks_state, .set_clock = set_clock, - .set_min_clocks_state = set_min_clocks_state, - .store_max_clocks_state = store_max_clocks_state + .set_min_clocks_state = set_min_clocks_state }; static bool dal_display_clock_dce110_construct( @@ -471,7 +438,6 @@ static bool dal_display_clock_dce110_construct( struct dc_bios *bp = ctx->dc_bios; dc_base->ctx = ctx; - dc_base->id = CLOCK_SOURCE_ID_DCPLL; dc_base->min_display_clk_threshold_khz = 0; dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID; @@ -488,12 +454,11 @@ static bool dal_display_clock_dce110_construct( dc110->gpu_pll_ss_divider = 1000; dc110->ss_on_gpu_pll = false; - dc_base->id = CLOCK_SOURCE_ID_DFS; /* Initially set max clocks state to nominal. This should be updated by * via a pplib call to DAL IRI eventually calling a * DisplayEngineClock_Dce110::StoreMaxClocksState(). This call will come in * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc110->max_clks_state = CLOCKS_STATE_NOMINAL; + dc_base->max_clks_state = CLOCKS_STATE_NOMINAL; dal_divider_range_construct( ÷r_ranges[DIVIDER_RANGE_01], diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h index 703cd656b5b0..50b51c41b0d9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h @@ -29,8 +29,6 @@ struct display_clock_dce110 { struct display_clock disp_clk_base; - /* Max display block clocks state*/ - enum clocks_state max_clks_state; bool use_max_disp_clk; uint32_t dentist_vco_freq_khz; /* Cache the status of DFS-bypass feature*/ diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c index 665832b0718a..d8c8d8a1e2b3 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c @@ -72,41 +72,6 @@ enum divider_range_step_size { static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; #define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000 -/***************************************************************************** - * static functions - *****************************************************************************/ - -/* - * store_max_clocks_state - * - * @brief - * Cache the clock state - * - * @param - * struct display_clock *base - [out] cach the state in this structure - * enum clocks_state max_clocks_state - [in] state to be stored - */ -void dispclk_dce112_store_max_clocks_state( - struct display_clock *base, - enum clocks_state max_clocks_state) -{ - struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base); - - switch (max_clocks_state) { - case CLOCKS_STATE_LOW: - case CLOCKS_STATE_NOMINAL: - case CLOCKS_STATE_PERFORMANCE: - case CLOCKS_STATE_ULTRA_LOW: - dc->max_clks_state = max_clocks_state; - break; - - case CLOCKS_STATE_INVALID: - default: - /*Invalid Clocks State!*/ - ASSERT_CRITICAL(false); - break; - } -} enum clocks_state dispclk_dce112_get_min_clocks_state( struct display_clock *base) @@ -122,7 +87,7 @@ bool dispclk_dce112_set_min_clocks_state( struct dm_pp_power_level_change_request level_change_req = { DM_PP_POWER_LEVEL_INVALID}; - if (clocks_state > dc->max_clks_state) { + if (clocks_state > base->max_clks_state) { /*Requested state exceeds max supported state.*/ dm_logger_write(base->ctx->logger, LOG_WARNING, "Requested state exceeds max supported state"); @@ -302,7 +267,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state( { int32_t i; struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc); - enum clocks_state low_req_clk = disp_clk->max_clks_state; + enum clocks_state low_req_clk = dc->max_clks_state; if (!req_clocks) { /* NULL pointer*/ @@ -316,7 +281,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state( * lowest RequiredState with the lowest state that satisfies * all required clocks */ - for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { + for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { if ((req_clocks->display_clk_khz <= (disp_clk->max_clks_by_state + i)-> display_clk_khz) && @@ -333,7 +298,6 @@ void dispclk_dce112_set_clock( uint32_t requested_clk_khz) { struct bp_set_dce_clock_parameters dce_clk_params; - struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base); struct dc_bios *bp = base->ctx->dc_bios; /* Prepare to program display clock*/ @@ -345,7 +309,7 @@ void dispclk_dce112_set_clock( base->min_display_clk_threshold_khz); dce_clk_params.target_clock_frequency = requested_clk_khz; - dce_clk_params.pll_id = dc->disp_clk_base.id; + dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; bp->funcs->set_dce_clock(bp, &dce_clk_params); @@ -372,8 +336,7 @@ static const struct display_clock_funcs funcs = { .get_min_clocks_state = dispclk_dce112_get_min_clocks_state, .get_required_clocks_state = dispclk_dce112_get_required_clocks_state, .set_clock = dispclk_dce112_set_clock, - .set_min_clocks_state = dispclk_dce112_set_min_clocks_state, - .store_max_clocks_state = dispclk_dce112_store_max_clocks_state, + .set_min_clocks_state = dispclk_dce112_set_min_clocks_state }; bool dal_display_clock_dce112_construct( @@ -399,12 +362,11 @@ bool dal_display_clock_dce112_construct( dc112->gpu_pll_ss_divider = 1000; dc112->ss_on_gpu_pll = false; - dc_base->id = CLOCK_SOURCE_ID_DFS; /* Initially set max clocks state to nominal. This should be updated by * via a pplib call to DAL IRI eventually calling a * DisplayEngineClock_dce112::StoreMaxClocksState(). This call will come in * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc112->max_clks_state = CLOCKS_STATE_NOMINAL; + dc_base->max_clks_state = CLOCKS_STATE_NOMINAL; dc112->disp_clk_base.min_display_clk_threshold_khz = (dc112->dentist_vco_freq_khz / 62); diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h index 34afff9a00bc..398af34720f7 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h @@ -29,8 +29,6 @@ struct display_clock_dce112 { struct display_clock disp_clk_base; - /* Max display block clocks state*/ - enum clocks_state max_clks_state; bool use_max_disp_clk; uint32_t dentist_vco_freq_khz; /* Cache the status of DFS-bypass feature*/ diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c index 89ee8bd96979..b101f7de2d11 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c @@ -95,28 +95,20 @@ static void set_clock( uint32_t requested_clk_khz) { struct bp_pixel_clock_parameters pxl_clk_params; - struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc); struct dc_bios *bp = dc->ctx->dc_bios; /* Prepare to program display clock*/ memset(&pxl_clk_params, 0, sizeof(pxl_clk_params)); pxl_clk_params.target_pixel_clock = requested_clk_khz; - pxl_clk_params.pll_id = dc->id; + pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); - if (disp_clk->dfs_bypass_enabled) { - - /* Cache the fixed display clock*/ - disp_clk->dfs_bypass_disp_clk = - pxl_clk_params.dfs_bypass_display_clock; - } - /* from power down, we need mark the clock state as ClocksStateNominal * from HWReset, so when resume we will call pplib voltage regulator.*/ if (requested_clk_khz == 0) - disp_clk->cur_min_clks_state = CLOCKS_STATE_NOMINAL; + dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL; } static enum clocks_state get_min_clocks_state(struct display_clock *dc) @@ -131,8 +123,7 @@ static enum clocks_state get_required_clocks_state struct state_dependent_clocks *req_clocks) { int32_t i; - struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc); - enum clocks_state low_req_clk = disp_clk->max_clks_state; + enum clocks_state low_req_clk = dc->max_clks_state; if (!req_clocks) { /* NULL pointer*/ @@ -144,7 +135,7 @@ static enum clocks_state get_required_clocks_state * lowest RequiredState with the lowest state that satisfies * all required clocks */ - for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { + for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { if ((req_clocks->display_clk_khz <= max_clks_by_state[i].display_clk_khz) && (req_clocks->pixel_clk_khz <= @@ -158,12 +149,10 @@ static bool set_min_clocks_state( struct display_clock *dc, enum clocks_state clocks_state) { - struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc); - struct dm_pp_power_level_change_request level_change_req = { DM_PP_POWER_LEVEL_INVALID}; - if (clocks_state > disp_clk->max_clks_state) { + if (clocks_state > dc->max_clks_state) { /*Requested state exceeds max supported state.*/ dm_logger_write(dc->ctx->logger, LOG_WARNING, "Requested state exceeds max supported state"); @@ -271,28 +260,6 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc) return dp_ref_clk_khz; } -static void store_max_clocks_state( - struct display_clock *dc, - enum clocks_state max_clocks_state) -{ - struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc); - - switch (max_clocks_state) { - case CLOCKS_STATE_LOW: - case CLOCKS_STATE_NOMINAL: - case CLOCKS_STATE_PERFORMANCE: - case CLOCKS_STATE_ULTRA_LOW: - disp_clk->max_clks_state = max_clocks_state; - break; - - case CLOCKS_STATE_INVALID: - default: - /*Invalid Clocks State!*/ - BREAK_TO_DEBUGGER(); - break; - } -} - static void display_clock_ss_construct( struct display_clock_dce80 *disp_clk) { @@ -411,8 +378,7 @@ static const struct display_clock_funcs funcs = { .get_min_clocks_state = get_min_clocks_state, .get_required_clocks_state = get_required_clocks_state, .set_clock = set_clock, - .set_min_clocks_state = set_min_clocks_state, - .store_max_clocks_state = store_max_clocks_state + .set_min_clocks_state = set_min_clocks_state }; @@ -430,7 +396,6 @@ struct display_clock *dal_display_clock_dce80_create( dc_base = &disp_clk->disp_clk; dc_base->ctx = ctx; - dc_base->id = CLOCK_SOURCE_ID_DCPLL; dc_base->min_display_clk_threshold_khz = 0; dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID; @@ -450,12 +415,11 @@ struct display_clock *dal_display_clock_dce80_create( disp_clk->dfs_bypass_disp_clk = 0; disp_clk->use_max_disp_clk = true;/* false will hang the system! */ - disp_clk->disp_clk.id = CLOCK_SOURCE_ID_DFS; /* Initially set max clocks state to nominal. This should be updated by * via a pplib call to DAL IRI eventually calling a * DisplayEngineClock_Dce50::StoreMaxClocksState(). This call will come in * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - disp_clk->max_clks_state = CLOCKS_STATE_NOMINAL; + dc_base->max_clks_state = CLOCKS_STATE_NOMINAL; /* Initially set current min clocks state to invalid since we * cannot make any assumption about PPLIB's initial state. This will be updated * by HWSS via SetMinClocksState() on first mode set prior to programming diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h index 273a5d902840..1193398b5cea 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h @@ -37,8 +37,6 @@ struct display_clock_dce80 { uint32_t gpu_pll_ss_divider; /* Flag for Enabled SS on GPU PLL*/ bool ss_on_gpu_pll; - /* Max display block clocks state*/ - enum clocks_state max_clks_state; /* Current minimum display block clocks state*/ enum clocks_state cur_min_clks_state; /* DFS-bypass feature variable diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h index a46ceebe2452..bc678a59a3c1 100644 --- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h +++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h @@ -60,7 +60,8 @@ struct display_clock { struct dc_context *ctx; const struct display_clock_funcs *funcs; uint32_t min_display_clk_threshold_khz; - enum clock_source_id id; + /* Max display block clocks state*/ + enum clocks_state max_clks_state; enum clocks_state cur_min_clks_state; }; @@ -77,8 +78,6 @@ struct display_clock_funcs { bool (*set_min_clocks_state)(struct display_clock *disp_clk, enum clocks_state clocks_state); uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); - void (*store_max_clocks_state)(struct display_clock *disp_clk, - enum clocks_state max_clocks_state); }; -- cgit v1.2.3-59-g8ed1b From e9c58bb439bce021da205df09057fe6908ff54c5 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 30 Nov 2016 16:07:50 -0500 Subject: drm/amd/display: remove clocks_state enum Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 3 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 44 +-------------- .../drm/amd/display/dc/dce110/dce110_resource.h | 3 - .../drm/amd/display/dc/dce112/dce112_resource.c | 3 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 24 ++++---- .../display/dc/gpu/dce110/display_clock_dce110.c | 62 +++++---------------- .../display/dc/gpu/dce112/display_clock_dce112.c | 62 +++++---------------- .../display/dc/gpu/dce112/display_clock_dce112.h | 8 +-- .../amd/display/dc/gpu/dce80/display_clock_dce80.c | 64 ++++++---------------- .../amd/display/dc/gpu/dce80/display_clock_dce80.h | 2 +- .../amd/display/include/display_clock_interface.h | 28 ++-------- 13 files changed, 75 insertions(+), 236 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 558eeefecbff..47f22d46c0ca 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1221,9 +1221,9 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) if (link_settings.link_rate == max_link_rate) { if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { - if (pipe_ctx->dis_clk->cur_min_clks_state < CLOCKS_STATE_NOMINAL) + if (pipe_ctx->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL) pipe_ctx->dis_clk->funcs->set_min_clocks_state( - pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL); + pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); } else { } } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 446f50bb4e0a..5716ce1e58f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -983,8 +983,7 @@ static bool construct( */ if (dm_pp_get_static_clocks(ctx, &static_clk_info)) pool->base.display_clock->max_clks_state = - dce110_resource_convert_clock_state_pp_to_dc( - static_clk_info.max_clocks_state); + static_clk_info.max_clocks_state; { struct irq_service_init_data init_data; init_data.ctx = dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ca71509af74d..6ad23f327631 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1084,7 +1084,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( static void apply_min_clocks( struct core_dc *dc, struct validate_context *context, - enum clocks_state *clocks_state, + enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) { struct state_dependent_clocks req_clocks = {0}; @@ -1193,7 +1193,7 @@ enum dc_status dce110_apply_ctx_to_hw( enum dc_status status; int i; bool programmed_audio_dto = false; - enum clocks_state clocks_state = CLOCKS_STATE_INVALID; + enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; /* Reset old context */ /* look up the targets that have been removed since last commit */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index d5d888bdf882..8682c8b2a547 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1188,47 +1188,6 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 1000); } -enum clocks_state dce110_resource_convert_clock_state_pp_to_dc( - enum dm_pp_clocks_state pp_clock_state) -{ - enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID; - - switch (pp_clock_state) { - case DM_PP_CLOCKS_STATE_INVALID: - dc_clocks_state = CLOCKS_STATE_INVALID; - break; - case DM_PP_CLOCKS_STATE_ULTRA_LOW: - dc_clocks_state = CLOCKS_STATE_ULTRA_LOW; - break; - case DM_PP_CLOCKS_STATE_LOW: - dc_clocks_state = CLOCKS_STATE_LOW; - break; - case DM_PP_CLOCKS_STATE_NOMINAL: - dc_clocks_state = CLOCKS_STATE_NOMINAL; - break; - case DM_PP_CLOCKS_STATE_PERFORMANCE: - dc_clocks_state = CLOCKS_STATE_PERFORMANCE; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_4: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_5: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_6: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_7: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7; - break; - default: - dc_clocks_state = CLOCKS_STATE_INVALID; - break; - } - - return dc_clocks_state; -} - const struct resource_caps *dce110_resource_cap( struct hw_asic_id *asic_id) { @@ -1314,8 +1273,7 @@ static bool construct( */ if (dm_pp_get_static_clocks(ctx, &static_clk_info)) pool->base.display_clock->max_clks_state = - dce110_resource_convert_clock_state_pp_to_dc( - static_clk_info.max_clocks_state); + static_clk_info.max_clocks_state; { struct irq_service_init_data init_data; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h index 535623aa0052..0c357fdfa8bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -40,9 +40,6 @@ struct dce110_resource_pool { enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); -enum clocks_state dce110_resource_convert_clock_state_pp_to_dc( - enum dm_pp_clocks_state pp_clock_state); - void dce110_resource_build_bit_depth_reduction_params( const struct core_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 9903c9a4b8a1..c50a215172b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1314,8 +1314,7 @@ static bool construct( */ if (dm_pp_get_static_clocks(ctx, &static_clk_info)) pool->base.display_clock->max_clks_state = - dce110_resource_convert_clock_state_pp_to_dc( - static_clk_info.max_clocks_state); + static_clk_info.max_clocks_state; { struct irq_service_init_data init_data; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 51721d10c811..1d2a31e34617 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -857,41 +857,41 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_bandwidth = dce80_validate_bandwidth }; -static enum clocks_state dce80_resource_convert_clock_state_pp_to_dc( +static enum dm_pp_clocks_state dce80_resource_convert_clock_state_pp_to_dc( enum dm_pp_clocks_state pp_clock_state) { - enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID; + enum dm_pp_clocks_state dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID; switch (pp_clock_state) { case DM_PP_CLOCKS_STATE_INVALID: - dc_clocks_state = CLOCKS_STATE_INVALID; + dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID; break; case DM_PP_CLOCKS_STATE_ULTRA_LOW: - dc_clocks_state = CLOCKS_STATE_ULTRA_LOW; + dc_clocks_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; break; case DM_PP_CLOCKS_STATE_LOW: - dc_clocks_state = CLOCKS_STATE_LOW; + dc_clocks_state = DM_PP_CLOCKS_STATE_LOW; break; case DM_PP_CLOCKS_STATE_NOMINAL: - dc_clocks_state = CLOCKS_STATE_NOMINAL; + dc_clocks_state = DM_PP_CLOCKS_STATE_NOMINAL; break; case DM_PP_CLOCKS_STATE_PERFORMANCE: - dc_clocks_state = CLOCKS_STATE_PERFORMANCE; + dc_clocks_state = DM_PP_CLOCKS_STATE_PERFORMANCE; break; case DM_PP_CLOCKS_DPM_STATE_LEVEL_4: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4; + dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_4; break; case DM_PP_CLOCKS_DPM_STATE_LEVEL_5: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5; + dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_5; break; case DM_PP_CLOCKS_DPM_STATE_LEVEL_6: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6; + dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_6; break; case DM_PP_CLOCKS_DPM_STATE_LEVEL_7: - dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7; + dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_7; break; default: - dc_clocks_state = CLOCKS_STATE_INVALID; + dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID; break; } diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c index 83860208a9c5..9dabaac2c550 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c @@ -105,10 +105,10 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; static bool dce110_set_min_clocks_state( struct display_clock *dc, - enum clocks_state clocks_state) + enum dm_pp_clocks_state clocks_state) { struct dm_pp_power_level_change_request level_change_req = { - DM_PP_POWER_LEVEL_INVALID}; + clocks_state }; if (clocks_state > dc->max_clks_state) { /*Requested state exceeds max supported state.*/ @@ -121,38 +121,6 @@ static bool dce110_set_min_clocks_state( return true; } - switch (clocks_state) { - case CLOCKS_STATE_ULTRA_LOW: - level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW; - break; - case CLOCKS_STATE_LOW: - level_change_req.power_level = DM_PP_POWER_LEVEL_LOW; - break; - case CLOCKS_STATE_NOMINAL: - level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL; - break; - case CLOCKS_STATE_PERFORMANCE: - level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE; - break; - case CLOCKS_DPM_STATE_LEVEL_4: - level_change_req.power_level = DM_PP_POWER_LEVEL_4; - break; - case CLOCKS_DPM_STATE_LEVEL_5: - level_change_req.power_level = DM_PP_POWER_LEVEL_5; - break; - case CLOCKS_DPM_STATE_LEVEL_6: - level_change_req.power_level = DM_PP_POWER_LEVEL_6; - break; - case CLOCKS_DPM_STATE_LEVEL_7: - level_change_req.power_level = DM_PP_POWER_LEVEL_7; - break; - case CLOCKS_STATE_INVALID: - default: - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "Requested state invalid state"); - return false; - } - /* get max clock state from PPLIB */ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req)) dc->cur_min_clks_state = clocks_state; @@ -274,27 +242,27 @@ static bool display_clock_integrated_info_construct( /*update the maximum display clock for each power state*/ for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum clocks_state clk_state = CLOCKS_STATE_INVALID; + enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; switch (i) { case 0: - clk_state = CLOCKS_STATE_ULTRA_LOW; + clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; break; case 1: - clk_state = CLOCKS_STATE_LOW; + clk_state = DM_PP_CLOCKS_STATE_LOW; break; case 2: - clk_state = CLOCKS_STATE_NOMINAL; + clk_state = DM_PP_CLOCKS_STATE_NOMINAL; break; case 3: - clk_state = CLOCKS_STATE_PERFORMANCE; + clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; break; default: - clk_state = CLOCKS_STATE_INVALID; + clk_state = DM_PP_CLOCKS_STATE_INVALID; break; } @@ -316,27 +284,27 @@ static bool display_clock_integrated_info_construct( return true; } -static enum clocks_state get_required_clocks_state( +static enum dm_pp_clocks_state get_required_clocks_state( struct display_clock *dc, struct state_dependent_clocks *req_clocks) { int32_t i; struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc); - enum clocks_state low_req_clk = dc->max_clks_state; + enum dm_pp_clocks_state low_req_clk = dc->max_clks_state; if (!req_clocks) { /* NULL pointer*/ dm_logger_write(dc->ctx->logger, LOG_WARNING, "%s: Invalid parameter", __func__); - return CLOCKS_STATE_INVALID; + return DM_PP_CLOCKS_STATE_INVALID; } /* Iterate from highest supported to lowest valid state, and update * lowest RequiredState with the lowest state that satisfies * all required clocks */ - for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { + for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) { if ((req_clocks->display_clk_khz <= max_clks_by_state[i].display_clk_khz) && (req_clocks->pixel_clk_khz <= @@ -420,7 +388,7 @@ static void dce110_set_clock( /* from power down, we need mark the clock state as ClocksStateNominal * from HWReset, so when resume we will call pplib voltage regulator.*/ if (requested_clk_khz == 0) - base->cur_min_clks_state = CLOCKS_STATE_NOMINAL; + base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; psr_wait_loop(base->ctx, requested_clk_khz); } @@ -444,7 +412,7 @@ static bool dal_display_clock_dce110_construct( dc_base->ctx = ctx; dc_base->min_display_clk_threshold_khz = 0; - dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID; + dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; dc_base->funcs = &funcs; @@ -462,7 +430,7 @@ static bool dal_display_clock_dce110_construct( * via a pplib call to DAL IRI eventually calling a * DisplayEngineClock_Dce110::StoreMaxClocksState(). This call will come in * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc_base->max_clks_state = CLOCKS_STATE_NOMINAL; + dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; dal_divider_range_construct( ÷r_ranges[DIVIDER_RANGE_01], diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c index 4488497c00fa..930548bdd8b2 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c @@ -75,10 +75,10 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; static bool dce112_set_min_clocks_state( struct display_clock *dc, - enum clocks_state clocks_state) + enum dm_pp_clocks_state clocks_state) { struct dm_pp_power_level_change_request level_change_req = { - DM_PP_POWER_LEVEL_INVALID }; + clocks_state }; if (clocks_state > dc->max_clks_state) { /*Requested state exceeds max supported state.*/ @@ -91,38 +91,6 @@ static bool dce112_set_min_clocks_state( return true; } - switch (clocks_state) { - case CLOCKS_STATE_ULTRA_LOW: - level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW; - break; - case CLOCKS_STATE_LOW: - level_change_req.power_level = DM_PP_POWER_LEVEL_LOW; - break; - case CLOCKS_STATE_NOMINAL: - level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL; - break; - case CLOCKS_STATE_PERFORMANCE: - level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE; - break; - case CLOCKS_DPM_STATE_LEVEL_4: - level_change_req.power_level = DM_PP_POWER_LEVEL_4; - break; - case CLOCKS_DPM_STATE_LEVEL_5: - level_change_req.power_level = DM_PP_POWER_LEVEL_5; - break; - case CLOCKS_DPM_STATE_LEVEL_6: - level_change_req.power_level = DM_PP_POWER_LEVEL_6; - break; - case CLOCKS_DPM_STATE_LEVEL_7: - level_change_req.power_level = DM_PP_POWER_LEVEL_7; - break; - case CLOCKS_STATE_INVALID: - default: - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "Requested state invalid state"); - return false; - } - /* get max clock state from PPLIB */ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req)) dc->cur_min_clks_state = clocks_state; @@ -229,27 +197,27 @@ static bool display_clock_integrated_info_construct( /*update the maximum display clock for each power state*/ for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum clocks_state clk_state = CLOCKS_STATE_INVALID; + enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; switch (i) { case 0: - clk_state = CLOCKS_STATE_ULTRA_LOW; + clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; break; case 1: - clk_state = CLOCKS_STATE_LOW; + clk_state = DM_PP_CLOCKS_STATE_LOW; break; case 2: - clk_state = CLOCKS_STATE_NOMINAL; + clk_state = DM_PP_CLOCKS_STATE_NOMINAL; break; case 3: - clk_state = CLOCKS_STATE_PERFORMANCE; + clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; break; default: - clk_state = CLOCKS_STATE_INVALID; + clk_state = DM_PP_CLOCKS_STATE_INVALID; break; } @@ -265,27 +233,27 @@ static bool display_clock_integrated_info_construct( return true; } -enum clocks_state dispclk_dce112_get_required_clocks_state( +enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state( struct display_clock *dc, struct state_dependent_clocks *req_clocks) { int32_t i; struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc); - enum clocks_state low_req_clk = dc->max_clks_state; + enum dm_pp_clocks_state low_req_clk = dc->max_clks_state; if (!req_clocks) { /* NULL pointer*/ dm_logger_write(dc->ctx->logger, LOG_WARNING, "%s: Invalid parameter", __func__); - return CLOCKS_STATE_INVALID; + return DM_PP_CLOCKS_STATE_INVALID; } /* Iterate from highest supported to lowest valid state, and update * lowest RequiredState with the lowest state that satisfies * all required clocks */ - for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { + for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) { if ((req_clocks->display_clk_khz <= (disp_clk->max_clks_by_state + i)-> display_clk_khz) && @@ -321,7 +289,7 @@ void dce112_set_clock( /* from power down, we need mark the clock state as ClocksStateNominal * from HWReset, so when resume we will call pplib voltage regulator.*/ if (requested_clk_khz == 0) - base->cur_min_clks_state = CLOCKS_STATE_NOMINAL; + base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; /*Program DP ref Clock*/ /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ @@ -351,7 +319,7 @@ bool dal_display_clock_dce112_construct( dc_base->ctx = ctx; dc_base->min_display_clk_threshold_khz = 0; - dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID; + dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; dc_base->funcs = &funcs; @@ -369,7 +337,7 @@ bool dal_display_clock_dce112_construct( * via a pplib call to DAL IRI eventually calling a * DisplayEngineClock_dce112::StoreMaxClocksState(). This call will come in * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc_base->max_clks_state = CLOCKS_STATE_NOMINAL; + dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; dc112->disp_clk_base.min_display_clk_threshold_khz = (dc112->dentist_vco_freq_khz / 62); diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h index 0246f930ac35..b750bb1766bd 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h @@ -71,10 +71,10 @@ bool dal_display_clock_dce112_construct( void dispclk_dce112_destroy(struct display_clock **base); -enum clocks_state dispclk_dce112_get_min_clocks_state( +enum dm_pp_clocks_state dispclk_dce112_get_min_clocks_state( struct display_clock *base); -enum clocks_state dispclk_dce112_get_required_clocks_state( +enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state( struct display_clock *dc, struct state_dependent_clocks *req_clocks); @@ -84,10 +84,10 @@ void dce112_set_clock( bool dispclk_dce112_set_min_clocks_state( struct display_clock *base, - enum clocks_state clocks_state); + enum dm_pp_clocks_state clocks_state); void dispclk_dce112_store_max_clocks_state( struct display_clock *base, - enum clocks_state max_clocks_state); + enum dm_pp_clocks_state max_clocks_state); #endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c index 6057042739bf..9d7cb2cb161c 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c @@ -108,27 +108,27 @@ static void dce80_set_clock( /* from power down, we need mark the clock state as ClocksStateNominal * from HWReset, so when resume we will call pplib voltage regulator.*/ if (requested_clk_khz == 0) - dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL; + dc->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; } -static enum clocks_state get_required_clocks_state +static enum dm_pp_clocks_state get_required_clocks_state (struct display_clock *dc, struct state_dependent_clocks *req_clocks) { int32_t i; - enum clocks_state low_req_clk = dc->max_clks_state; + enum dm_pp_clocks_state low_req_clk = dc->max_clks_state; if (!req_clocks) { /* NULL pointer*/ BREAK_TO_DEBUGGER(); - return CLOCKS_STATE_INVALID; + return DM_PP_CLOCKS_STATE_INVALID; } /* Iterate from highest supported to lowest valid state, and update * lowest RequiredState with the lowest state that satisfies * all required clocks */ - for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) { + for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) { if ((req_clocks->display_clk_khz <= max_clks_by_state[i].display_clk_khz) && (req_clocks->pixel_clk_khz <= @@ -140,10 +140,10 @@ static enum clocks_state get_required_clocks_state static bool dce80_set_min_clocks_state( struct display_clock *dc, - enum clocks_state clocks_state) + enum dm_pp_clocks_state clocks_state) { struct dm_pp_power_level_change_request level_change_req = { - DM_PP_POWER_LEVEL_INVALID }; + clocks_state }; if (clocks_state > dc->max_clks_state) { /*Requested state exceeds max supported state.*/ @@ -156,38 +156,6 @@ static bool dce80_set_min_clocks_state( return true; } - switch (clocks_state) { - case CLOCKS_STATE_ULTRA_LOW: - level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW; - break; - case CLOCKS_STATE_LOW: - level_change_req.power_level = DM_PP_POWER_LEVEL_LOW; - break; - case CLOCKS_STATE_NOMINAL: - level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL; - break; - case CLOCKS_STATE_PERFORMANCE: - level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE; - break; - case CLOCKS_DPM_STATE_LEVEL_4: - level_change_req.power_level = DM_PP_POWER_LEVEL_4; - break; - case CLOCKS_DPM_STATE_LEVEL_5: - level_change_req.power_level = DM_PP_POWER_LEVEL_5; - break; - case CLOCKS_DPM_STATE_LEVEL_6: - level_change_req.power_level = DM_PP_POWER_LEVEL_6; - break; - case CLOCKS_DPM_STATE_LEVEL_7: - level_change_req.power_level = DM_PP_POWER_LEVEL_7; - break; - case CLOCKS_STATE_INVALID: - default: - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "Requested state invalid state"); - return false; - } - /* get max clock state from PPLIB */ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req)) dc->cur_min_clks_state = clocks_state; @@ -326,27 +294,27 @@ static bool display_clock_integrated_info_construct( /*update the maximum display clock for each power state*/ for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum clocks_state clk_state = CLOCKS_STATE_INVALID; + enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; switch (i) { case 0: - clk_state = CLOCKS_STATE_ULTRA_LOW; + clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; break; case 1: - clk_state = CLOCKS_STATE_LOW; + clk_state = DM_PP_CLOCKS_STATE_LOW; break; case 2: - clk_state = CLOCKS_STATE_NOMINAL; + clk_state = DM_PP_CLOCKS_STATE_NOMINAL; break; case 3: - clk_state = CLOCKS_STATE_PERFORMANCE; + clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; break; default: - clk_state = CLOCKS_STATE_INVALID; + clk_state = DM_PP_CLOCKS_STATE_INVALID; break; } @@ -402,7 +370,7 @@ struct display_clock *dal_display_clock_dce80_create( dc_base->ctx = ctx; dc_base->min_display_clk_threshold_khz = 0; - dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID; + dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; dc_base->funcs = &funcs; /* @@ -423,12 +391,12 @@ struct display_clock *dal_display_clock_dce80_create( * via a pplib call to DAL IRI eventually calling a * DisplayEngineClock_Dce50::StoreMaxClocksState(). This call will come in * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc_base->max_clks_state = CLOCKS_STATE_NOMINAL; + dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; /* Initially set current min clocks state to invalid since we * cannot make any assumption about PPLIB's initial state. This will be updated * by HWSS via SetMinClocksState() on first mode set prior to programming * state dependent clocks.*/ - disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID; + disp_clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; display_clock_ss_construct(disp_clk); diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h index 1193398b5cea..c155bb6a4321 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h @@ -38,7 +38,7 @@ struct display_clock_dce80 { /* Flag for Enabled SS on GPU PLL*/ bool ss_on_gpu_pll; /* Current minimum display block clocks state*/ - enum clocks_state cur_min_clks_state; + enum dm_pp_clocks_state cur_min_clks_state; /* DFS-bypass feature variable Cache the status of DFS-bypass feature*/ bool dfs_bypass_enabled; diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h index f2deafbd8b12..6ba8c093793d 100644 --- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h +++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h @@ -26,29 +26,11 @@ #ifndef __DISPLAY_CLOCK_INTERFACE_H__ #define __DISPLAY_CLOCK_INTERFACE_H__ +#include "dm_services_types.h" #include "hw_sequencer_types.h" #include "grph_object_defs.h" #include "signal_types.h" -/* Enumeration of all clocks states */ -enum clocks_state { - CLOCKS_STATE_INVALID = 0, - CLOCKS_STATE_ULTRA_LOW, - CLOCKS_STATE_LOW, - CLOCKS_STATE_NOMINAL, - CLOCKS_STATE_PERFORMANCE, - /* Starting from DCE11, Max 8 level DPM state supported */ - CLOCKS_DPM_STATE_LEVEL_INVALID = CLOCKS_STATE_INVALID, - CLOCKS_DPM_STATE_LEVEL_0 = CLOCKS_STATE_ULTRA_LOW, - CLOCKS_DPM_STATE_LEVEL_1 = CLOCKS_STATE_LOW, - CLOCKS_DPM_STATE_LEVEL_2 = CLOCKS_STATE_NOMINAL, - CLOCKS_DPM_STATE_LEVEL_3 = CLOCKS_STATE_PERFORMANCE, - CLOCKS_DPM_STATE_LEVEL_4 = CLOCKS_DPM_STATE_LEVEL_3 + 1, - CLOCKS_DPM_STATE_LEVEL_5 = CLOCKS_DPM_STATE_LEVEL_4 + 1, - CLOCKS_DPM_STATE_LEVEL_6 = CLOCKS_DPM_STATE_LEVEL_5 + 1, - CLOCKS_DPM_STATE_LEVEL_7 = CLOCKS_DPM_STATE_LEVEL_6 + 1, -}; - /* Structure containing all state-dependent clocks * (dependent on "enum clocks_state") */ struct state_dependent_clocks { @@ -61,20 +43,20 @@ struct display_clock { const struct display_clock_funcs *funcs; uint32_t min_display_clk_threshold_khz; /* Max display block clocks state*/ - enum clocks_state max_clks_state; + enum dm_pp_clocks_state max_clks_state; - enum clocks_state cur_min_clks_state; + enum dm_pp_clocks_state cur_min_clks_state; }; struct display_clock_funcs { void (*destroy)(struct display_clock **to_destroy); void (*set_clock)(struct display_clock *disp_clk, uint32_t requested_clock_khz); - enum clocks_state (*get_required_clocks_state)( + enum dm_pp_clocks_state (*get_required_clocks_state)( struct display_clock *disp_clk, struct state_dependent_clocks *req_clocks); bool (*set_min_clocks_state)(struct display_clock *disp_clk, - enum clocks_state clocks_state); + enum dm_pp_clocks_state dm_pp_clocks_state); uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); }; -- cgit v1.2.3-59-g8ed1b From 9a70eba7f2c65b408ee56c7219b0cb4ae588b2bc Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 1 Dec 2016 18:13:25 -0500 Subject: drm/amd/display: consolidate dce8-11.2 display clock code Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/Makefile | 3 +- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 519 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 133 ++++++ .../drm/amd/display/dc/dce100/dce100_resource.c | 22 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 24 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 28 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 70 +-- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 18 +- drivers/gpu/drm/amd/display/dc/gpu/Makefile | 15 - .../display/dc/gpu/dce110/display_clock_dce110.c | 516 -------------------- .../display/dc/gpu/dce110/display_clock_dce110.h | 50 -- .../display/dc/gpu/dce112/display_clock_dce112.c | 152 ------ .../display/dc/gpu/dce112/display_clock_dce112.h | 14 - .../amd/display/dc/gpu/dce80/display_clock_dce80.c | 430 ----------------- .../amd/display/dc/gpu/dce80/display_clock_dce80.h | 54 --- .../amd/display/include/display_clock_interface.h | 15 +- 17 files changed, 747 insertions(+), 1320 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index bfca38170329..6add5977fd39 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -6,7 +6,8 @@ # offset/shift/mask stored in dce_hw struct DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ -dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o +dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ +dce_clocks.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index dc44053e8575..2749c8fa4f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -888,7 +888,9 @@ static const struct audio_funcs funcs = { void dce_aud_destroy(struct audio **audio) { - dm_free(*audio); + struct dce_audio *aud = DCE_AUD(*audio); + + dm_free(aud); *audio = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c new file mode 100644 index 000000000000..77033fe8a8e5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -0,0 +1,519 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce_clocks.h" +#include "dm_services.h" +#include "reg_helper.h" +#include "fixed32_32.h" +#include "bios_parser_interface.h" +#include "dc.h" + + +#define REG(reg) \ + (clk_dce->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + clk_dce->clk_shift->field_name, clk_dce->clk_mask->field_name + +#define CTX \ + clk_dce->base.ctx + +/* Starting point for each divider range.*/ +enum divider_range_start { + DIVIDER_RANGE_01_START = 200, /* 2.00*/ + DIVIDER_RANGE_02_START = 1600, /* 16.00*/ + DIVIDER_RANGE_03_START = 3200, /* 32.00*/ + DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/ +}; + +/* Ranges for divider identifiers (Divider ID or DID) + mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/ +enum divider_id_register_setting { + DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08, + DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40, + DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60, + DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80 +}; + +/* Step size between each divider within a range. + Incrementing the DENTIST_DISPCLK_WDIVIDER by one + will increment the divider by this much.*/ +enum divider_range_step_size { + DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/ + DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/ + DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */ +}; + + +static uint32_t dce_clocks_get_dp_ref_freq(struct display_clock *clk) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); + int dprefclk_wdivider; + int dprefclk_src_sel; + int dp_ref_clk_khz = 600000; + int target_div = INVALID_DIVIDER; + + /* ASSERT DP Reference Clock source is from DFS*/ + REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); + ASSERT(dprefclk_src_sel == 0); + + /* Read the mmDENTIST_DISPCLK_CNTL to get the currently + * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ + REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); + + /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ + target_div = dal_divider_range_get_divider( + clk_dce->divider_ranges, + DIVIDER_RANGE_MAX, + dprefclk_wdivider); + + if (target_div != INVALID_DIVIDER) { + /* Calculate the current DFS clock, in kHz.*/ + dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR + * clk_dce->dentist_vco_freq_khz) / target_div; + } + + /* SW will adjust DP REF Clock average value for all purposes + * (DP DTO / DP Audio DTO and DP GTC) + if clock is spread for all cases: + -if SS enabled on DP Ref clock and HW de-spreading enabled with SW + calculations for DS_INCR/DS_MODULO (this is planned to be default case) + -if SS enabled on DP Ref clock and HW de-spreading enabled with HW + calculations (not planned to be used, but average clock should still + be valid) + -if SS enabled on DP Ref clock and HW de-spreading disabled + (should not be case with CIK) then SW should program all rates + generated according to average value (case as with previous ASICs) + */ + if (clk_dce->ss_on_gpu_pll && clk_dce->gpu_pll_ss_divider != 0) { + struct fixed32_32 ss_percentage = dal_fixed32_32_div_int( + dal_fixed32_32_from_fraction( + clk_dce->gpu_pll_ss_percentage, + clk_dce->gpu_pll_ss_divider), 200); + struct fixed32_32 adj_dp_ref_clk_khz; + + ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one, + ss_percentage); + adj_dp_ref_clk_khz = + dal_fixed32_32_mul_int( + ss_percentage, + dp_ref_clk_khz); + dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz); + } + + return dp_ref_clk_khz; +} + +static enum dm_pp_clocks_state dce_get_required_clocks_state( + struct display_clock *clk, + struct state_dependent_clocks *req_clocks) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); + int i; + enum dm_pp_clocks_state low_req_clk; + + /* Iterate from highest supported to lowest valid state, and update + * lowest RequiredState with the lowest state that satisfies + * all required clocks + */ + for (i = clk->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) + if (req_clocks->display_clk_khz > + clk_dce->max_clks_by_state[i].display_clk_khz + || req_clocks->pixel_clk_khz > + clk_dce->max_clks_by_state[i].pixel_clk_khz) + break; + + low_req_clk = i + 1; + if (low_req_clk > clk->max_clks_state) { + dm_logger_write(clk->ctx->logger, LOG_WARNING, + "%s: clocks unsupported", __func__); + low_req_clk = DM_PP_CLOCKS_STATE_INVALID; + } + + return low_req_clk; +} + +static bool dce_clock_set_min_clocks_state( + struct display_clock *clk, + enum dm_pp_clocks_state clocks_state) +{ + struct dm_pp_power_level_change_request level_change_req = { + clocks_state }; + + if (clocks_state > clk->max_clks_state) { + /*Requested state exceeds max supported state.*/ + dm_logger_write(clk->ctx->logger, LOG_WARNING, + "Requested state exceeds max supported state"); + return false; + } else if (clocks_state == clk->cur_min_clks_state) { + /*if we're trying to set the same state, we can just return + * since nothing needs to be done*/ + return true; + } + + /* get max clock state from PPLIB */ + if (dm_pp_apply_power_level_change_request(clk->ctx, &level_change_req)) + clk->cur_min_clks_state = clocks_state; + + return true; +} + +static void dce_set_clock( + struct display_clock *clk, + uint32_t requested_clk_khz) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); + struct bp_pixel_clock_parameters pxl_clk_params = { 0 }; + struct dc_bios *bp = clk->ctx->dc_bios; + + /* Make sure requested clock isn't lower than minimum threshold*/ + if (requested_clk_khz > 0) + requested_clk_khz = dm_max(requested_clk_khz, + clk_dce->dentist_vco_freq_khz / 64); + + /* Prepare to program display clock*/ + pxl_clk_params.target_pixel_clock = requested_clk_khz; + pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; + + bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); + + if (clk_dce->dfs_bypass_enabled) { + + /* Cache the fixed display clock*/ + clk_dce->dfs_bypass_disp_clk = + pxl_clk_params.dfs_bypass_display_clock; + } + + /* from power down, we need mark the clock state as ClocksStateNominal + * from HWReset, so when resume we will call pplib voltage regulator.*/ + if (requested_clk_khz == 0) + clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; +} + +#define PSR_SET_WAITLOOP 0x31 + +union dce110_dmcu_psr_config_data_wait_loop_reg1 { + struct { + unsigned int wait_loop:16; /* [15:0] */ + unsigned int reserved:16; /* [31:16] */ + } bits; + unsigned int u32; +}; + +static void dce_psr_wait_loop( + struct dce_disp_clk *clk_dce, unsigned int display_clk_khz) +{ + struct dc_context *ctx = clk_dce->base.ctx; + union dce110_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = display_clk_khz / 1000 / 7; + dm_write_reg(ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} + +static void dce_psr_set_clock( + struct display_clock *clk, + uint32_t requested_clk_khz) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); + + dce_set_clock(clk, requested_clk_khz); + dce_psr_wait_loop(clk_dce, requested_clk_khz); +} + +static void polaris_set_clock( + struct display_clock *clk, + uint32_t requested_clk_khz) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); + struct bp_set_dce_clock_parameters dce_clk_params; + struct dc_bios *bp = clk->ctx->dc_bios; + + /* Prepare to program display clock*/ + memset(&dce_clk_params, 0, sizeof(dce_clk_params)); + + /* Make sure requested clock isn't lower than minimum threshold*/ + if (requested_clk_khz > 0) + requested_clk_khz = dm_max(requested_clk_khz, + clk_dce->dentist_vco_freq_khz / 64); + + dce_clk_params.target_clock_frequency = requested_clk_khz; + dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; + dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; + + bp->funcs->set_dce_clock(bp, &dce_clk_params); + + /* from power down, we need mark the clock state as ClocksStateNominal + * from HWReset, so when resume we will call pplib voltage regulator.*/ + if (requested_clk_khz == 0) + clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; + + /*Program DP ref Clock*/ + /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ + dce_clk_params.target_clock_frequency = 0; + dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; + dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = 0; + + bp->funcs->set_dce_clock(bp, &dce_clk_params); +} + +static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce) +{ + struct dc_debug *debug = &clk_dce->base.ctx->dc->debug; + struct dc_bios *bp = clk_dce->base.ctx->dc_bios; + struct integrated_info info = { 0 }; + struct firmware_info fw_info = { 0 }; + int i; + + if (bp->integrated_info) + info = *bp->integrated_info; + + clk_dce->dentist_vco_freq_khz = info.dentist_vco_freq; + if (clk_dce->dentist_vco_freq_khz == 0) { + bp->funcs->get_firmware_info(bp, &fw_info); + clk_dce->dentist_vco_freq_khz = + fw_info.smu_gpu_pll_output_freq; + if (clk_dce->dentist_vco_freq_khz == 0) + clk_dce->dentist_vco_freq_khz = 3600000; + } + + /*update the maximum display clock for each power state*/ + for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { + enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; + + switch (i) { + case 0: + clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; + break; + + case 1: + clk_state = DM_PP_CLOCKS_STATE_LOW; + break; + + case 2: + clk_state = DM_PP_CLOCKS_STATE_NOMINAL; + break; + + case 3: + clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; + break; + + default: + clk_state = DM_PP_CLOCKS_STATE_INVALID; + break; + } + + /*Do not allow bad VBIOS/SBIOS to override with invalid values, + * check for > 100MHz*/ + if (info.disp_clk_voltage[i].max_supported_clk >= 100000) + clk_dce->max_clks_by_state[clk_state].display_clk_khz = + info.disp_clk_voltage[i].max_supported_clk; + } + + if (!debug->disable_dfs_bypass) + if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) + clk_dce->dfs_bypass_enabled = true; + + clk_dce->use_max_disp_clk = debug->max_disp_clk; +} + +static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) +{ + struct dc_bios *bp = clk_dce->base.ctx->dc_bios; + int ss_info_num = bp->funcs->get_ss_entry_number( + bp, AS_SIGNAL_TYPE_GPU_PLL); + + if (ss_info_num) { + struct spread_spectrum_info info = { 0 }; + enum bp_result result = bp->funcs->get_spread_spectrum_info( + bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info); + + /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS + * even if SS not enabled and in that case + * SSInfo.spreadSpectrumPercentage !=0 would be sign + * that SS is enabled + */ + if (result == BP_RESULT_OK && + info.spread_spectrum_percentage != 0) { + clk_dce->ss_on_gpu_pll = true; + clk_dce->gpu_pll_ss_divider = info.spread_percentage_divider; + + if (info.type.CENTER_MODE == 0) { + /* Currently for DP Reference clock we + * need only SS percentage for + * downspread */ + clk_dce->gpu_pll_ss_percentage = + info.spread_spectrum_percentage; + } + } + + } +} + +static const struct display_clock_funcs dce112_funcs = { + .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, + .get_required_clocks_state = dce_get_required_clocks_state, + .set_min_clocks_state = dce_clock_set_min_clocks_state, + .set_clock = polaris_set_clock +}; + +static const struct display_clock_funcs dce110_funcs = { + .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, + .get_required_clocks_state = dce_get_required_clocks_state, + .set_min_clocks_state = dce_clock_set_min_clocks_state, + .set_clock = dce_psr_set_clock +}; + +static const struct display_clock_funcs dce_funcs = { + .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, + .get_required_clocks_state = dce_get_required_clocks_state, + .set_min_clocks_state = dce_clock_set_min_clocks_state, + .set_clock = dce_set_clock +}; + +static void dce_disp_clk_construct( + struct dce_disp_clk *clk_dce, + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask) +{ + struct display_clock *base = &clk_dce->base; + + base->ctx = ctx; + base->funcs = &dce_funcs; + + clk_dce->regs = regs; + clk_dce->clk_shift = clk_shift; + clk_dce->clk_mask = clk_mask; + + clk_dce->dfs_bypass_disp_clk = 0; + clk_dce->gpu_pll_ss_percentage = 0; + clk_dce->gpu_pll_ss_divider = 1000; + clk_dce->ss_on_gpu_pll = false; + base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; + base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; + + dce_clock_read_integrated_info(clk_dce); + dce_clock_read_ss_info(clk_dce); + + dal_divider_range_construct( + &clk_dce->divider_ranges[DIVIDER_RANGE_01], + DIVIDER_RANGE_01_START, + DIVIDER_RANGE_01_STEP_SIZE, + DIVIDER_RANGE_01_BASE_DIVIDER_ID, + DIVIDER_RANGE_02_BASE_DIVIDER_ID); + dal_divider_range_construct( + &clk_dce->divider_ranges[DIVIDER_RANGE_02], + DIVIDER_RANGE_02_START, + DIVIDER_RANGE_02_STEP_SIZE, + DIVIDER_RANGE_02_BASE_DIVIDER_ID, + DIVIDER_RANGE_03_BASE_DIVIDER_ID); + dal_divider_range_construct( + &clk_dce->divider_ranges[DIVIDER_RANGE_03], + DIVIDER_RANGE_03_START, + DIVIDER_RANGE_03_STEP_SIZE, + DIVIDER_RANGE_03_BASE_DIVIDER_ID, + DIVIDER_RANGE_MAX_DIVIDER_ID); +} + +struct display_clock *dce_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask) +{ + struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + + if (clk_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_disp_clk_construct( + clk_dce, ctx, regs, clk_shift, clk_mask); + + return &clk_dce->base; +} + +struct display_clock *dce110_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask) +{ + struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + + if (clk_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_disp_clk_construct( + clk_dce, ctx, regs, clk_shift, clk_mask); + + clk_dce->base.funcs = &dce110_funcs; + + return &clk_dce->base; +} + +struct display_clock *dce112_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask) +{ + struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + + if (clk_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_disp_clk_construct( + clk_dce, ctx, regs, clk_shift, clk_mask); + + clk_dce->base.funcs = &dce112_funcs; + + return &clk_dce->base; +} + +void dce_disp_clk_destroy(struct display_clock **disp_clk) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); + + dm_free(clk_dce); + *disp_clk = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h new file mode 100644 index 000000000000..e3b23749f0a2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -0,0 +1,133 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#ifndef _DCE_CLOCKS_H_ +#define _DCE_CLOCKS_H_ + +#include "display_clock_interface.h" +#include "../gpu/divider_range.h" + + +#define TO_DCE_CLOCKS(clocks)\ + container_of(clocks, struct dce_disp_clk, base) + +#define CLK_COMMON_REG_LIST_DCE_BASE() \ + .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ + .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL, \ + .MASTER_COMM_DATA_REG1 = mmMASTER_COMM_DATA_REG1, \ + .MASTER_COMM_CMD_REG = mmMASTER_COMM_CMD_REG, \ + .MASTER_COMM_CNTL_REG = mmMASTER_COMM_CNTL_REG + +#define CLK_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ + CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ + CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) + + +#define CLK_REG_FIELD_LIST(type) \ + type DPREFCLK_SRC_SEL; \ + type DENTIST_DPREFCLK_WDIVIDER; \ + type MASTER_COMM_CMD_REG_BYTE0; \ + type MASTER_COMM_INTERRUPT + +struct dce_disp_clk_shift { + CLK_REG_FIELD_LIST(uint8_t); +}; + +struct dce_disp_clk_mask { + CLK_REG_FIELD_LIST(uint32_t); +}; + +struct dce_disp_clk_registers { + uint32_t DPREFCLK_CNTL; + uint32_t DENTIST_DISPCLK_CNTL; + uint32_t MASTER_COMM_DATA_REG1; + uint32_t MASTER_COMM_CMD_REG; + uint32_t MASTER_COMM_CNTL_REG; +}; + +/* Array identifiers and count for the divider ranges.*/ +enum divider_range_count { + DIVIDER_RANGE_01 = 0, + DIVIDER_RANGE_02, + DIVIDER_RANGE_03, + DIVIDER_RANGE_MAX /* == 3*/ +}; + +struct dce_disp_clk { + struct display_clock base; + const struct dce_disp_clk_registers *regs; + const struct dce_disp_clk_shift *clk_shift; + const struct dce_disp_clk_mask *clk_mask; + + struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; + struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; + + bool use_max_disp_clk; + uint32_t dentist_vco_freq_khz; + + /* Cache the status of DFS-bypass feature*/ + bool dfs_bypass_enabled; + /* Cache the display clock returned by VBIOS if DFS-bypass is enabled. + * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */ + uint32_t dfs_bypass_disp_clk; + + /* Flag for Enabled SS on GPU PLL */ + bool ss_on_gpu_pll; + /* GPU PLL SS percentage (if down-spread enabled) */ + uint32_t gpu_pll_ss_percentage; + /* GPU PLL SS percentage Divider (100 or 1000) */ + uint32_t gpu_pll_ss_divider; + + +}; + + +struct display_clock *dce_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask); + +struct display_clock *dce110_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask); + +struct display_clock *dce112_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask); + +void dce_disp_clk_destroy(struct display_clock **disp_clk); + +#endif /* _DCE_CLOCKS_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 5716ce1e58f4..c97416f7bc93 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -40,6 +40,7 @@ #include "dce110/dce110_ipp.h" #include "dce/dce_transform.h" #include "dce110/dce110_opp.h" +#include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" @@ -200,6 +201,18 @@ static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = { .reg_name = mm ## block ## id ## _ ## reg_name +static const struct dce_disp_clk_registers disp_clk_regs = { + CLK_COMMON_REG_LIST_DCE_BASE() +}; + +static const struct dce_disp_clk_shift disp_clk_shift = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_disp_clk_mask disp_clk_mask = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE100(id)\ @@ -717,9 +730,7 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.display_clock != NULL) - pool->base.display_clock->funcs->destroy( - &pool->base.display_clock); - pool->base.display_clock = NULL; + dce_disp_clk_destroy(&pool->base.display_clock); if (pool->base.irqs != NULL) dal_irq_service_destroy(&pool->base.irqs); @@ -970,7 +981,10 @@ static bool construct( } } - pool->base.display_clock = dal_display_clock_dce110_create(ctx); + pool->base.display_clock = dce_disp_clk_create(ctx, + &disp_clk_regs, + &disp_clk_shift, + &disp_clk_mask); if (pool->base.display_clock == NULL) { dm_error("DC: failed to create display clock!\n"); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 8682c8b2a547..fa601f7f0b5a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -45,6 +45,7 @@ #include "dce110/dce110_transform_v.h" #include "dce110/dce110_opp.h" #include "dce110/dce110_opp_v.h" +#include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_hwseq.h" #include "dce110/dce110_hw_sequencer.h" @@ -187,6 +188,17 @@ static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = { #define SRI(reg_name, block, id)\ .reg_name = mm ## block ## id ## _ ## reg_name +static const struct dce_disp_clk_registers disp_clk_regs = { + CLK_COMMON_REG_LIST_DCE_BASE() +}; + +static const struct dce_disp_clk_shift disp_clk_shift = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_disp_clk_mask disp_clk_mask = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; #define transform_regs(id)\ [id] = {\ @@ -699,11 +711,8 @@ static void destruct(struct dce110_resource_pool *pool) } } - if (pool->base.display_clock != NULL) { - pool->base.display_clock->funcs->destroy( - &pool->base.display_clock); - pool->base.display_clock = NULL; - } + if (pool->base.display_clock != NULL) + dce_disp_clk_destroy(&pool->base.display_clock); if (pool->base.irqs != NULL) { dal_irq_service_destroy(&pool->base.irqs); @@ -1261,7 +1270,10 @@ static bool construct( } } - pool->base.display_clock = dal_display_clock_dce110_create(ctx); + pool->base.display_clock = dce110_disp_clk_create(ctx, + &disp_clk_regs, + &disp_clk_shift, + &disp_clk_mask); if (pool->base.display_clock == NULL) { dm_error("DC: failed to create display clock!\n"); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index c50a215172b7..3a478300b848 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -41,6 +41,7 @@ #include "dce/dce_audio.h" #include "dce112/dce112_opp.h" #include "dce110/dce110_ipp.h" +#include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_hwseq.h" @@ -204,6 +205,19 @@ static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { #define SRI(reg_name, block, id)\ .reg_name = mm ## block ## id ## _ ## reg_name + +static const struct dce_disp_clk_registers disp_clk_regs = { + CLK_COMMON_REG_LIST_DCE_BASE() +}; + +static const struct dce_disp_clk_shift disp_clk_shift = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_disp_clk_mask disp_clk_mask = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -733,11 +747,8 @@ static void destruct(struct dce110_resource_pool *pool) } } - if (pool->base.display_clock != NULL) { - pool->base.display_clock->funcs->destroy( - &pool->base.display_clock); - pool->base.display_clock = NULL; - } + if (pool->base.display_clock != NULL) + dce_disp_clk_destroy(&pool->base.display_clock); if (pool->base.irqs != NULL) { dal_irq_service_destroy(&pool->base.irqs); @@ -1299,9 +1310,10 @@ static bool construct( } } - pool->base.display_clock = dal_display_clock_dce112_create( - ctx); - + pool->base.display_clock = dce112_disp_clk_create(ctx, + &disp_clk_regs, + &disp_clk_shift, + &disp_clk_mask); if (pool->base.display_clock == NULL) { dm_error("DC: failed to create display clock!\n"); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 1d2a31e34617..517d42dfff0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -45,6 +45,7 @@ #include "dce/dce_transform.h" #include "dce80/dce80_opp.h" #include "dce110/dce110_ipp.h" +#include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" @@ -215,6 +216,19 @@ static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { #define SRI(reg_name, block, id)\ .reg_name = mm ## block ## id ## _ ## reg_name + +static const struct dce_disp_clk_registers disp_clk_regs = { + CLK_COMMON_REG_LIST_DCE_BASE() +}; + +static const struct dce_disp_clk_shift disp_clk_shift = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_disp_clk_mask disp_clk_mask = { + CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE_BASE(id)\ @@ -656,11 +670,8 @@ static void destruct(struct dce110_resource_pool *pool) } } - if (pool->base.display_clock != NULL) { - pool->base.display_clock->funcs->destroy( - &pool->base.display_clock); - pool->base.display_clock = NULL; - } + if (pool->base.display_clock != NULL) + dce_disp_clk_destroy(&pool->base.display_clock); if (pool->base.irqs != NULL) { dal_irq_service_destroy(&pool->base.irqs); @@ -857,47 +868,6 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_bandwidth = dce80_validate_bandwidth }; -static enum dm_pp_clocks_state dce80_resource_convert_clock_state_pp_to_dc( - enum dm_pp_clocks_state pp_clock_state) -{ - enum dm_pp_clocks_state dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID; - - switch (pp_clock_state) { - case DM_PP_CLOCKS_STATE_INVALID: - dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID; - break; - case DM_PP_CLOCKS_STATE_ULTRA_LOW: - dc_clocks_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; - break; - case DM_PP_CLOCKS_STATE_LOW: - dc_clocks_state = DM_PP_CLOCKS_STATE_LOW; - break; - case DM_PP_CLOCKS_STATE_NOMINAL: - dc_clocks_state = DM_PP_CLOCKS_STATE_NOMINAL; - break; - case DM_PP_CLOCKS_STATE_PERFORMANCE: - dc_clocks_state = DM_PP_CLOCKS_STATE_PERFORMANCE; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_4: - dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_4; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_5: - dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_5; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_6: - dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_6; - break; - case DM_PP_CLOCKS_DPM_STATE_LEVEL_7: - dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_7; - break; - default: - dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID; - break; - } - - return dc_clocks_state; -} - static bool construct( uint8_t num_virtual_links, struct core_dc *dc, @@ -967,7 +937,10 @@ static bool construct( } } - pool->base.display_clock = dal_display_clock_dce80_create(ctx); + pool->base.display_clock = dce_disp_clk_create(ctx, + &disp_clk_regs, + &disp_clk_shift, + &disp_clk_mask); if (pool->base.display_clock == NULL) { dm_error("DC: failed to create display clock!\n"); BREAK_TO_DEBUGGER(); @@ -977,8 +950,7 @@ static bool construct( if (dm_pp_get_static_clocks(ctx, &static_clk_info)) pool->base.display_clock->max_clks_state = - dce80_resource_convert_clock_state_pp_to_dc( - static_clk_info.max_clocks_state); + static_clk_info.max_clocks_state; { struct irq_service_init_data init_data; diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 44bad17fa318..460971dc3a70 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -43,15 +43,17 @@ enum dm_pp_clocks_state { /* Starting from DCE11, Max 8 levels of DPM state supported. */ DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID, - DM_PP_CLOCKS_DPM_STATE_LEVEL_0 = DM_PP_CLOCKS_STATE_ULTRA_LOW, - DM_PP_CLOCKS_DPM_STATE_LEVEL_1 = DM_PP_CLOCKS_STATE_LOW, - DM_PP_CLOCKS_DPM_STATE_LEVEL_2 = DM_PP_CLOCKS_STATE_NOMINAL, + DM_PP_CLOCKS_DPM_STATE_LEVEL_0, + DM_PP_CLOCKS_DPM_STATE_LEVEL_1, + DM_PP_CLOCKS_DPM_STATE_LEVEL_2, /* to be backward compatible */ - DM_PP_CLOCKS_DPM_STATE_LEVEL_3 = DM_PP_CLOCKS_STATE_PERFORMANCE, - DM_PP_CLOCKS_DPM_STATE_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1, + DM_PP_CLOCKS_DPM_STATE_LEVEL_3, + DM_PP_CLOCKS_DPM_STATE_LEVEL_4, + DM_PP_CLOCKS_DPM_STATE_LEVEL_5, + DM_PP_CLOCKS_DPM_STATE_LEVEL_6, + DM_PP_CLOCKS_DPM_STATE_LEVEL_7, + + DM_PP_CLOCKS_MAX_STATES }; struct dm_pp_gpu_clock_range { diff --git a/drivers/gpu/drm/amd/display/dc/gpu/Makefile b/drivers/gpu/drm/amd/display/dc/gpu/Makefile index 0b99a7474950..6ab4078405f2 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpu/Makefile @@ -9,24 +9,9 @@ AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU)) AMD_DISPLAY_FILES += $(AMD_DAL_GPU) -############################################################################### -# DCE 80 family -############################################################################### -GPU_DCE80 = display_clock_dce80.o - -AMD_DAL_GPU_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpu/dce80/,$(GPU_DCE80)) - -AMD_DISPLAY_FILES += $(AMD_DAL_GPU_DCE80) - - ############################################################################### # DCE 110 family ############################################################################### -GPU_DCE110 = display_clock_dce110.o - -AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110)) - -AMD_DISPLAY_FILES += $(AMD_DAL_GPU_DCE110) GPU_DCE112 = display_clock_dce112.o diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c deleted file mode 100644 index 9dabaac2c550..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "include/bios_parser_interface.h" -#include "include/fixed32_32.h" -#include "include/logger_interface.h" - -#include "../divider_range.h" - -#include "display_clock_dce110.h" -#include "dc.h" - -#define FROM_DISPLAY_CLOCK(base) \ - container_of(base, struct display_clock_dce110, disp_clk_base) - -#define PSR_SET_WAITLOOP 0x31 - -static struct state_dependent_clocks max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; - -/* Starting point for each divider range.*/ -enum divider_range_start { - DIVIDER_RANGE_01_START = 200, /* 2.00*/ - DIVIDER_RANGE_02_START = 1600, /* 16.00*/ - DIVIDER_RANGE_03_START = 3200, /* 32.00*/ - DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/ -}; - -/* Array identifiers and count for the divider ranges.*/ -enum divider_range_count { - DIVIDER_RANGE_01 = 0, - DIVIDER_RANGE_02, - DIVIDER_RANGE_03, - DIVIDER_RANGE_MAX /* == 3*/ -}; - -/* Ranges for divider identifiers (Divider ID or DID) - mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/ -enum divider_id_register_setting { - DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08, - DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40, - DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60, - DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80 -}; - -/* Step size between each divider within a range. - Incrementing the DENTIST_DISPCLK_WDIVIDER by one - will increment the divider by this much.*/ -enum divider_range_step_size { - DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/ - DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/ - DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */ -}; - -union dce110_dmcu_psr_config_data_wait_loop_reg1 { - struct { - unsigned int waitLoop:16; /* [15:0] */ - unsigned int reserved:16; /* [31:16] */ - } bits; - unsigned int u32All; -}; - -static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; - -#define DCE110_DFS_BYPASS_THRESHOLD_KHZ 400000 -/***************************************************************************** - * static functions - *****************************************************************************/ - -static bool dce110_set_min_clocks_state( - struct display_clock *dc, - enum dm_pp_clocks_state clocks_state) -{ - struct dm_pp_power_level_change_request level_change_req = { - clocks_state }; - - if (clocks_state > dc->max_clks_state) { - /*Requested state exceeds max supported state.*/ - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "Requested state exceeds max supported state"); - return false; - } else if (clocks_state == dc->cur_min_clks_state) { - /*if we're trying to set the same state, we can just return - * since nothing needs to be done*/ - return true; - } - - /* get max clock state from PPLIB */ - if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req)) - dc->cur_min_clks_state = clocks_state; - - return true; -} - -static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc) -{ - uint32_t dispclk_cntl_value; - uint32_t dp_ref_clk_cntl_value; - uint32_t dp_ref_clk_cntl_src_sel_value; - uint32_t dp_ref_clk_khz = 600000; - uint32_t target_div = INVALID_DIVIDER; - struct display_clock_dce110 *disp_clk = FROM_DISPLAY_CLOCK(dc); - - /* ASSERT DP Reference Clock source is from DFS*/ - dp_ref_clk_cntl_value = dm_read_reg(dc->ctx, - mmDPREFCLK_CNTL); - - dp_ref_clk_cntl_src_sel_value = - get_reg_field_value( - dp_ref_clk_cntl_value, - DPREFCLK_CNTL, DPREFCLK_SRC_SEL); - - ASSERT(dp_ref_clk_cntl_src_sel_value == 0); - - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ - dispclk_cntl_value = dm_read_reg(dc->ctx, - mmDENTIST_DISPCLK_CNTL); - - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ - target_div = dal_divider_range_get_divider( - divider_ranges, - DIVIDER_RANGE_MAX, - get_reg_field_value(dispclk_cntl_value, - DENTIST_DISPCLK_CNTL, - DENTIST_DPREFCLK_WDIVIDER)); - - if (target_div != INVALID_DIVIDER) { - /* Calculate the current DFS clock, in kHz.*/ - dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR - * disp_clk->dentist_vco_freq_khz) / target_div; - } - - /* SW will adjust DP REF Clock average value for all purposes - * (DP DTO / DP Audio DTO and DP GTC) - if clock is spread for all cases: - -if SS enabled on DP Ref clock and HW de-spreading enabled with SW - calculations for DS_INCR/DS_MODULO (this is planned to be default case) - -if SS enabled on DP Ref clock and HW de-spreading enabled with HW - calculations (not planned to be used, but average clock should still - be valid) - -if SS enabled on DP Ref clock and HW de-spreading disabled - (should not be case with CIK) then SW should program all rates - generated according to average value (case as with previous ASICs) - */ - if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) { - struct fixed32_32 ss_percentage = dal_fixed32_32_div_int( - dal_fixed32_32_from_fraction( - disp_clk->gpu_pll_ss_percentage, - disp_clk->gpu_pll_ss_divider), 200); - struct fixed32_32 adj_dp_ref_clk_khz; - - ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one, - ss_percentage); - adj_dp_ref_clk_khz = - dal_fixed32_32_mul_int( - ss_percentage, - dp_ref_clk_khz); - dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz); - } - - return dp_ref_clk_khz; -} - -static void destroy(struct display_clock **base) -{ - struct display_clock_dce110 *dc110; - - dc110 = DCLCK110_FROM_BASE(*base); - - dm_free(dc110); - - *base = NULL; -} - -static bool display_clock_integrated_info_construct( - struct display_clock_dce110 *disp_clk) -{ - struct dc_debug *debug = &disp_clk->disp_clk_base.ctx->dc->debug; - struct dc_bios *bp = disp_clk->disp_clk_base.ctx->dc_bios; - struct integrated_info info; - struct firmware_info fw_info; - uint32_t i; - struct display_clock *base = &disp_clk->disp_clk_base; - - memset(&info, 0, sizeof(struct integrated_info)); - memset(&fw_info, 0, sizeof(struct firmware_info)); - - if (bp->integrated_info) - info = *bp->integrated_info; - - disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq; - if (disp_clk->dentist_vco_freq_khz == 0) { - bp->funcs->get_firmware_info(bp, &fw_info); - disp_clk->dentist_vco_freq_khz = - fw_info.smu_gpu_pll_output_freq; - if (disp_clk->dentist_vco_freq_khz == 0) - disp_clk->dentist_vco_freq_khz = 3600000; - } - - base->min_display_clk_threshold_khz = - disp_clk->dentist_vco_freq_khz / 64; - - if (bp->integrated_info == NULL) - return false; - - /*update the maximum display clock for each power state*/ - for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; - - switch (i) { - case 0: - clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; - break; - - case 1: - clk_state = DM_PP_CLOCKS_STATE_LOW; - break; - - case 2: - clk_state = DM_PP_CLOCKS_STATE_NOMINAL; - break; - - case 3: - clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; - break; - - default: - clk_state = DM_PP_CLOCKS_STATE_INVALID; - break; - } - - /*Do not allow bad VBIOS/SBIOS to override with invalid values, - * check for > 100MHz*/ - if (info.disp_clk_voltage[i].max_supported_clk >= 100000) { - max_clks_by_state[clk_state].display_clk_khz = - info.disp_clk_voltage[i].max_supported_clk; - } - } - - disp_clk->dfs_bypass_enabled = false; - if (!debug->disable_dfs_bypass) - if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) - disp_clk->dfs_bypass_enabled = true; - - disp_clk->use_max_disp_clk = debug->max_disp_clk; - - return true; -} - -static enum dm_pp_clocks_state get_required_clocks_state( - struct display_clock *dc, - struct state_dependent_clocks *req_clocks) -{ - int32_t i; - struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc); - enum dm_pp_clocks_state low_req_clk = dc->max_clks_state; - - if (!req_clocks) { - /* NULL pointer*/ - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "%s: Invalid parameter", - __func__); - return DM_PP_CLOCKS_STATE_INVALID; - } - - /* Iterate from highest supported to lowest valid state, and update - * lowest RequiredState with the lowest state that satisfies - * all required clocks - */ - for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) { - if ((req_clocks->display_clk_khz <= - max_clks_by_state[i].display_clk_khz) && - (req_clocks->pixel_clk_khz <= - max_clks_by_state[i].pixel_clk_khz)) - low_req_clk = i; - } - return low_req_clk; -} - -static void psr_wait_loop(struct dc_context *ctx, unsigned int display_clk_khz) -{ - unsigned int dmcu_max_retry_on_wait_reg_ready = 801; - unsigned int dmcu_wait_reg_ready_interval = 100; - unsigned int regValue; - uint32_t masterCmd; - uint32_t masterComCntl; - union dce110_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; - - /* waitDMCUReadyForCmd */ - do { - dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval); - regValue = dm_read_reg(ctx, mmMASTER_COMM_CNTL_REG); - dmcu_max_retry_on_wait_reg_ready--; - } while - /* expected value is 0, loop while not 0*/ - ((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) && - dmcu_max_retry_on_wait_reg_ready > 0); - - masterCmdData1.u32All = 0; - masterCmdData1.bits.waitLoop = display_clk_khz / 1000 / 7; - dm_write_reg(ctx, mmMASTER_COMM_DATA_REG1, masterCmdData1.u32All); - - /* setDMCUParam_Cmd */ - masterCmd = dm_read_reg(ctx, mmMASTER_COMM_CMD_REG); - set_reg_field_value( - masterCmd, - PSR_SET_WAITLOOP, - MASTER_COMM_CMD_REG, - MASTER_COMM_CMD_REG_BYTE0); - - dm_write_reg(ctx, mmMASTER_COMM_CMD_REG, masterCmd); - - /* notifyDMCUMsg */ - masterComCntl = dm_read_reg(ctx, mmMASTER_COMM_CNTL_REG); - set_reg_field_value( - masterComCntl, - 1, - MASTER_COMM_CNTL_REG, - MASTER_COMM_INTERRUPT); - dm_write_reg(ctx, mmMASTER_COMM_CNTL_REG, masterComCntl); -} - -static void dce110_set_clock( - struct display_clock *base, - uint32_t requested_clk_khz) -{ - struct bp_pixel_clock_parameters pxl_clk_params; - struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base); - struct dc_bios *bp = base->ctx->dc_bios; - - /* Prepare to program display clock*/ - memset(&pxl_clk_params, 0, sizeof(pxl_clk_params)); - - /* Make sure requested clock isn't lower than minimum threshold*/ - if (requested_clk_khz > 0) - requested_clk_khz = dm_max(requested_clk_khz, - base->min_display_clk_threshold_khz); - - pxl_clk_params.target_pixel_clock = requested_clk_khz; - pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; - - bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); - - if (dc->dfs_bypass_enabled) { - - /* Cache the fixed display clock*/ - dc->dfs_bypass_disp_clk = - pxl_clk_params.dfs_bypass_display_clock; - } - - /* from power down, we need mark the clock state as ClocksStateNominal - * from HWReset, so when resume we will call pplib voltage regulator.*/ - if (requested_clk_khz == 0) - base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - - psr_wait_loop(base->ctx, requested_clk_khz); -} - - -static const struct display_clock_funcs funcs = { - .destroy = destroy, - .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency, - .get_required_clocks_state = get_required_clocks_state, - .set_clock = dce110_set_clock, - .set_min_clocks_state = dce110_set_min_clocks_state -}; - -static bool dal_display_clock_dce110_construct( - struct display_clock_dce110 *dc110, - struct dc_context *ctx) -{ - struct display_clock *dc_base = &dc110->disp_clk_base; - struct dc_bios *bp = ctx->dc_bios; - - dc_base->ctx = ctx; - dc_base->min_display_clk_threshold_khz = 0; - - dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; - - dc_base->funcs = &funcs; - - dc110->dfs_bypass_disp_clk = 0; - - if (!display_clock_integrated_info_construct(dc110)) - dm_logger_write(dc_base->ctx->logger, LOG_WARNING, - "Cannot obtain VBIOS integrated info\n"); - - dc110->gpu_pll_ss_percentage = 0; - dc110->gpu_pll_ss_divider = 1000; - dc110->ss_on_gpu_pll = false; - -/* Initially set max clocks state to nominal. This should be updated by - * via a pplib call to DAL IRI eventually calling a - * DisplayEngineClock_Dce110::StoreMaxClocksState(). This call will come in - * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - - dal_divider_range_construct( - ÷r_ranges[DIVIDER_RANGE_01], - DIVIDER_RANGE_01_START, - DIVIDER_RANGE_01_STEP_SIZE, - DIVIDER_RANGE_01_BASE_DIVIDER_ID, - DIVIDER_RANGE_02_BASE_DIVIDER_ID); - dal_divider_range_construct( - ÷r_ranges[DIVIDER_RANGE_02], - DIVIDER_RANGE_02_START, - DIVIDER_RANGE_02_STEP_SIZE, - DIVIDER_RANGE_02_BASE_DIVIDER_ID, - DIVIDER_RANGE_03_BASE_DIVIDER_ID); - dal_divider_range_construct( - ÷r_ranges[DIVIDER_RANGE_03], - DIVIDER_RANGE_03_START, - DIVIDER_RANGE_03_STEP_SIZE, - DIVIDER_RANGE_03_BASE_DIVIDER_ID, - DIVIDER_RANGE_MAX_DIVIDER_ID); - - { - uint32_t ss_info_num = - bp->funcs->get_ss_entry_number(bp, - AS_SIGNAL_TYPE_GPU_PLL); - - if (ss_info_num) { - struct spread_spectrum_info info; - enum bp_result result; - - memset(&info, 0, sizeof(info)); - - result = bp->funcs->get_spread_spectrum_info(bp, - AS_SIGNAL_TYPE_GPU_PLL, - 0, - &info); - - /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS - * even if SS not enabled and in that case - * SSInfo.spreadSpectrumPercentage !=0 would be sign - * that SS is enabled - */ - if (result == BP_RESULT_OK && - info.spread_spectrum_percentage != 0) { - dc110->ss_on_gpu_pll = true; - dc110->gpu_pll_ss_divider = - info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - dc110->gpu_pll_ss_percentage = - info.spread_spectrum_percentage; - } - } - - } - } - - return true; -} - -/***************************************************************************** - * public functions - *****************************************************************************/ - -struct display_clock *dal_display_clock_dce110_create( - struct dc_context *ctx) -{ - struct display_clock_dce110 *dc110; - - dc110 = dm_alloc(sizeof(struct display_clock_dce110)); - - if (dc110 == NULL) - return NULL; - - if (dal_display_clock_dce110_construct(dc110, ctx)) - return &dc110->disp_clk_base; - - dm_free(dc110); - - return NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h deleted file mode 100644 index 50b51c41b0d9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#ifndef __DAL_DISPLAY_CLOCK_DCE110_H__ -#define __DAL_DISPLAY_CLOCK_DCE110_H__ - -#include "display_clock_interface.h" - -struct display_clock_dce110 { - struct display_clock disp_clk_base; - bool use_max_disp_clk; - uint32_t dentist_vco_freq_khz; - /* Cache the status of DFS-bypass feature*/ - bool dfs_bypass_enabled; - /* GPU PLL SS percentage (if down-spread enabled) */ - uint32_t gpu_pll_ss_percentage; - /* GPU PLL SS percentage Divider (100 or 1000) */ - uint32_t gpu_pll_ss_divider; - /* Flag for Enabled SS on GPU PLL */ - bool ss_on_gpu_pll; - /* Cache the display clock returned by VBIOS if DFS-bypass is enabled. - * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */ - uint32_t dfs_bypass_disp_clk; -}; - -#define DCLCK110_FROM_BASE(dc_base) \ - container_of(dc_base, struct display_clock_dce110, disp_clk_base) - -#endif /* __DAL_DISPLAY_CLOCK_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c index 930548bdd8b2..e0d67fb6c633 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c @@ -71,102 +71,6 @@ enum divider_range_step_size { static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; -#define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000 - -static bool dce112_set_min_clocks_state( - struct display_clock *dc, - enum dm_pp_clocks_state clocks_state) -{ - struct dm_pp_power_level_change_request level_change_req = { - clocks_state }; - - if (clocks_state > dc->max_clks_state) { - /*Requested state exceeds max supported state.*/ - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "Requested state exceeds max supported state"); - return false; - } else if (clocks_state == dc->cur_min_clks_state) { - /*if we're trying to set the same state, we can just return - * since nothing needs to be done*/ - return true; - } - - /* get max clock state from PPLIB */ - if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req)) - dc->cur_min_clks_state = clocks_state; - - return true; -} - -static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc) -{ - uint32_t dispclk_cntl_value; - uint32_t dp_ref_clk_cntl_value; - uint32_t dp_ref_clk_cntl_src_sel_value; - uint32_t dp_ref_clk_khz = 600000; - uint32_t target_div = INVALID_DIVIDER; - struct display_clock_dce112 *disp_clk = FROM_DISPLAY_CLOCK(dc); - - /* ASSERT DP Reference Clock source is from DFS*/ - dp_ref_clk_cntl_value = dm_read_reg(dc->ctx, - mmDPREFCLK_CNTL); - - dp_ref_clk_cntl_src_sel_value = - get_reg_field_value( - dp_ref_clk_cntl_value, - DPREFCLK_CNTL, DPREFCLK_SRC_SEL); - - ASSERT(dp_ref_clk_cntl_src_sel_value == 0); - - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ - dispclk_cntl_value = dm_read_reg(dc->ctx, - mmDENTIST_DISPCLK_CNTL); - - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ - target_div = dal_divider_range_get_divider( - divider_ranges, - DIVIDER_RANGE_MAX, - get_reg_field_value(dispclk_cntl_value, - DENTIST_DISPCLK_CNTL, - DENTIST_DPREFCLK_WDIVIDER)); - - if (target_div != INVALID_DIVIDER) { - /* Calculate the current DFS clock, in kHz.*/ - dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR - * disp_clk->dentist_vco_freq_khz) / target_div; - } - - /* SW will adjust DP REF Clock average value for all purposes - * (DP DTO / DP Audio DTO and DP GTC) - if clock is spread for all cases: - -if SS enabled on DP Ref clock and HW de-spreading enabled with SW - calculations for DS_INCR/DS_MODULO (this is planned to be default case) - -if SS enabled on DP Ref clock and HW de-spreading enabled with HW - calculations (not planned to be used, but average clock should still - be valid) - -if SS enabled on DP Ref clock and HW de-spreading disabled - (should not be case with CIK) then SW should program all rates - generated according to average value (case as with previous ASICs) - */ - if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) { - struct fixed32_32 ss_percentage = dal_fixed32_32_div_int( - dal_fixed32_32_from_fraction( - disp_clk->gpu_pll_ss_percentage, - disp_clk->gpu_pll_ss_divider), 200); - struct fixed32_32 adj_dp_ref_clk_khz; - - ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one, - ss_percentage); - adj_dp_ref_clk_khz = - dal_fixed32_32_mul_int( - ss_percentage, - dp_ref_clk_khz); - dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz); - } - - return dp_ref_clk_khz; -} void dispclk_dce112_destroy(struct display_clock **base) { @@ -233,38 +137,6 @@ static bool display_clock_integrated_info_construct( return true; } -enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state( - struct display_clock *dc, - struct state_dependent_clocks *req_clocks) -{ - int32_t i; - struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc); - enum dm_pp_clocks_state low_req_clk = dc->max_clks_state; - - if (!req_clocks) { - /* NULL pointer*/ - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "%s: Invalid parameter", - __func__); - return DM_PP_CLOCKS_STATE_INVALID; - } - - /* Iterate from highest supported to lowest valid state, and update - * lowest RequiredState with the lowest state that satisfies - * all required clocks - */ - for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) { - if ((req_clocks->display_clk_khz <= - (disp_clk->max_clks_by_state + i)-> - display_clk_khz) && - (req_clocks->pixel_clk_khz <= - (disp_clk->max_clks_by_state + i)-> - pixel_clk_khz)) - low_req_clk = i; - } - return low_req_clk; -} - void dce112_set_clock( struct display_clock *base, uint32_t requested_clk_khz) @@ -304,10 +176,7 @@ void dce112_set_clock( static const struct display_clock_funcs funcs = { .destroy = dispclk_dce112_destroy, - .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency, - .get_required_clocks_state = dispclk_dce112_get_required_clocks_state, .set_clock = dce112_set_clock, - .set_min_clocks_state = dce112_set_min_clocks_state }; bool dal_display_clock_dce112_construct( @@ -406,24 +275,3 @@ bool dal_display_clock_dce112_construct( return true; } -/***************************************************************************** - * public functions - *****************************************************************************/ - -struct display_clock *dal_display_clock_dce112_create( - struct dc_context *ctx) -{ - struct display_clock_dce112 *dc112; - - dc112 = dm_alloc(sizeof(struct display_clock_dce112)); - - if (dc112 == NULL) - return NULL; - - if (dal_display_clock_dce112_construct(dc112, ctx)) - return &dc112->disp_clk_base; - - dm_free(dc112); - - return NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h index b750bb1766bd..0743c514a60f 100644 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h +++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h @@ -71,23 +71,9 @@ bool dal_display_clock_dce112_construct( void dispclk_dce112_destroy(struct display_clock **base); -enum dm_pp_clocks_state dispclk_dce112_get_min_clocks_state( - struct display_clock *base); - -enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state( - struct display_clock *dc, - struct state_dependent_clocks *req_clocks); - void dce112_set_clock( struct display_clock *base, uint32_t requested_clk_khz); -bool dispclk_dce112_set_min_clocks_state( - struct display_clock *base, - enum dm_pp_clocks_state clocks_state); - -void dispclk_dce112_store_max_clocks_state( - struct display_clock *base, - enum dm_pp_clocks_state max_clocks_state); #endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c deleted file mode 100644 index 9d7cb2cb161c..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "include/bios_parser_interface.h" -#include "include/fixed32_32.h" -#include "include/logger_interface.h" - -#include "../divider_range.h" -#include "display_clock_dce80.h" -#include "dc.h" - -#define DCE80_DFS_BYPASS_THRESHOLD_KHZ 100000 - -/* Max clock values for each state indexed by "enum clocks_state": */ -static struct state_dependent_clocks max_clks_by_state[] = { -/* ClocksStateInvalid - should not be used */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateLow */ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, -/* ClocksStateNominal */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, -/* ClocksStatePerformance */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; - -/* Starting point for each divider range.*/ -enum divider_range_start { - DIVIDER_RANGE_01_START = 200, /* 2.00*/ - DIVIDER_RANGE_02_START = 1600, /* 16.00*/ - DIVIDER_RANGE_03_START = 3200, /* 32.00*/ - DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/ -}; - -/* Ranges for divider identifiers (Divider ID or DID) - mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/ -enum divider_id_register_setting { - DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08, - DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40, - DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60, - DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80 -}; - -/* Step size between each divider within a range. - Incrementing the DENTIST_DISPCLK_WDIVIDER by one - will increment the divider by this much.*/ -enum divider_range_step_size { - DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/ - DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/ - DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */ -}; - -/* Array identifiers and count for the divider ranges.*/ -enum divider_range_count { - DIVIDER_RANGE_01 = 0, - DIVIDER_RANGE_02, - DIVIDER_RANGE_03, - DIVIDER_RANGE_MAX /* == 3*/ -}; - -static struct divider_range divider_ranges[DIVIDER_RANGE_MAX]; - -#define FROM_DISPLAY_CLOCK(base) \ - container_of(base, struct display_clock_dce80, disp_clk) - -static void dce80_set_clock( - struct display_clock *dc, - uint32_t requested_clk_khz) -{ - struct bp_pixel_clock_parameters pxl_clk_params; - struct dc_bios *bp = dc->ctx->dc_bios; - - /* Prepare to program display clock*/ - memset(&pxl_clk_params, 0, sizeof(pxl_clk_params)); - - pxl_clk_params.target_pixel_clock = requested_clk_khz; - pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; - - bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); - - /* from power down, we need mark the clock state as ClocksStateNominal - * from HWReset, so when resume we will call pplib voltage regulator.*/ - if (requested_clk_khz == 0) - dc->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; -} - -static enum dm_pp_clocks_state get_required_clocks_state - (struct display_clock *dc, - struct state_dependent_clocks *req_clocks) -{ - int32_t i; - enum dm_pp_clocks_state low_req_clk = dc->max_clks_state; - - if (!req_clocks) { - /* NULL pointer*/ - BREAK_TO_DEBUGGER(); - return DM_PP_CLOCKS_STATE_INVALID; - } - - /* Iterate from highest supported to lowest valid state, and update - * lowest RequiredState with the lowest state that satisfies - * all required clocks - */ - for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) { - if ((req_clocks->display_clk_khz <= - max_clks_by_state[i].display_clk_khz) && - (req_clocks->pixel_clk_khz <= - max_clks_by_state[i].pixel_clk_khz)) - low_req_clk = i; - } - return low_req_clk; -} - -static bool dce80_set_min_clocks_state( - struct display_clock *dc, - enum dm_pp_clocks_state clocks_state) -{ - struct dm_pp_power_level_change_request level_change_req = { - clocks_state }; - - if (clocks_state > dc->max_clks_state) { - /*Requested state exceeds max supported state.*/ - dm_logger_write(dc->ctx->logger, LOG_WARNING, - "Requested state exceeds max supported state"); - return false; - } else if (clocks_state == dc->cur_min_clks_state) { - /*if we're trying to set the same state, we can just return - * since nothing needs to be done*/ - return true; - } - - /* get max clock state from PPLIB */ - if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req)) - dc->cur_min_clks_state = clocks_state; - - return true; -} - -static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc) -{ - uint32_t dispclk_cntl_value; - uint32_t dp_ref_clk_cntl_value; - uint32_t dp_ref_clk_cntl_src_sel_value; - uint32_t dp_ref_clk_khz = 600000; - uint32_t target_div = INVALID_DIVIDER; - struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc); - - /* ASSERT DP Reference Clock source is from DFS*/ - dp_ref_clk_cntl_value = dm_read_reg(dc->ctx, - mmDPREFCLK_CNTL); - - dp_ref_clk_cntl_src_sel_value = - get_reg_field_value( - dp_ref_clk_cntl_value, - DPREFCLK_CNTL, DPREFCLK_SRC_SEL); - - ASSERT(dp_ref_clk_cntl_src_sel_value == 0); - - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ - dispclk_cntl_value = dm_read_reg(dc->ctx, - mmDENTIST_DISPCLK_CNTL); - - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ - target_div = dal_divider_range_get_divider( - divider_ranges, - DIVIDER_RANGE_MAX, - get_reg_field_value(dispclk_cntl_value, - DENTIST_DISPCLK_CNTL, - DENTIST_DPREFCLK_WDIVIDER)); - - if (target_div != INVALID_DIVIDER) { - /* Calculate the current DFS clock, in kHz.*/ - dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR - * disp_clk->dentist_vco_freq_khz) / target_div; - } - - /* SW will adjust DP REF Clock average value for all purposes - * (DP DTO / DP Audio DTO and DP GTC) - if clock is spread for all cases: - -if SS enabled on DP Ref clock and HW de-spreading enabled with SW - calculations for DS_INCR/DS_MODULO (this is planned to be default case) - -if SS enabled on DP Ref clock and HW de-spreading enabled with HW - calculations (not planned to be used, but average clock should still - be valid) - -if SS enabled on DP Ref clock and HW de-spreading disabled - (should not be case with CIK) then SW should program all rates - generated according to average value (case as with previous ASICs) - */ - if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) { - struct fixed32_32 ss_percentage = dal_fixed32_32_div_int( - dal_fixed32_32_from_fraction( - disp_clk->gpu_pll_ss_percentage, - disp_clk->gpu_pll_ss_divider), 200); - struct fixed32_32 adj_dp_ref_clk_khz; - - ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one, - ss_percentage); - adj_dp_ref_clk_khz = - dal_fixed32_32_mul_int( - ss_percentage, - dp_ref_clk_khz); - dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz); - } - - return dp_ref_clk_khz; -} - -static void display_clock_ss_construct( - struct display_clock_dce80 *disp_clk) -{ - struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios; - uint32_t ss_entry_num = bp->funcs->get_ss_entry_number(bp, - AS_SIGNAL_TYPE_GPU_PLL); - - /*Read SS Info from VBIOS SS Info table for DP Reference Clock spread.*/ - if (ss_entry_num > 0) {/* Should be only one entry */ - struct spread_spectrum_info ss_info; - enum bp_result res; - - memset(&ss_info, 0, sizeof(struct spread_spectrum_info)); - - res = bp->funcs->get_spread_spectrum_info(bp, - AS_SIGNAL_TYPE_GPU_PLL, 0, &ss_info); - - /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS even if - * SS not enabled and in that case - * SSInfo.spreadSpectrumPercentage !=0 would be - * sign that SS is enabled*/ - if (res == BP_RESULT_OK && ss_info.spread_spectrum_percentage != 0) { - disp_clk->ss_on_gpu_pll = true; - disp_clk->gpu_pll_ss_divider = - ss_info.spread_percentage_divider; - if (ss_info.type.CENTER_MODE == 0) - /* Currently we need only SS - * percentage for down-spread*/ - disp_clk->gpu_pll_ss_percentage = - ss_info.spread_spectrum_percentage; - } - } -} - -static bool display_clock_integrated_info_construct( - struct display_clock_dce80 *disp_clk) -{ - struct dc_debug *debug = &disp_clk->disp_clk.ctx->dc->debug; - struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios; - struct integrated_info info = { { { 0 } } }; - struct firmware_info fw_info = { { 0 } }; - uint32_t i; - - if (bp->integrated_info) - info = *bp->integrated_info; - - disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq; - if (disp_clk->dentist_vco_freq_khz == 0) { - bp->funcs->get_firmware_info(bp, &fw_info); - disp_clk->dentist_vco_freq_khz = - fw_info.smu_gpu_pll_output_freq; - if (disp_clk->dentist_vco_freq_khz == 0) - disp_clk->dentist_vco_freq_khz = 3600000; - } - disp_clk->disp_clk.min_display_clk_threshold_khz = - disp_clk->dentist_vco_freq_khz / 64; - - /* TODO: initialise disp_clk->dfs_bypass_disp_clk */ - - /*update the maximum display clock for each power state*/ - for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; - - switch (i) { - case 0: - clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; - break; - - case 1: - clk_state = DM_PP_CLOCKS_STATE_LOW; - break; - - case 2: - clk_state = DM_PP_CLOCKS_STATE_NOMINAL; - break; - - case 3: - clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; - break; - - default: - clk_state = DM_PP_CLOCKS_STATE_INVALID; - break; - } - - /*Do not allow bad VBIOS/SBIOS to override with invalid values, - * check for > 100MHz*/ - if (info.disp_clk_voltage[i].max_supported_clk >= 100000) { - max_clks_by_state[clk_state].display_clk_khz = - info.disp_clk_voltage[i].max_supported_clk; - } - } - - disp_clk->dfs_bypass_enabled = false; - if (!debug->disable_dfs_bypass) - if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) - disp_clk->dfs_bypass_enabled = true; - - disp_clk->use_max_disp_clk = debug->max_disp_clk; - - return true; -} - -static void destroy(struct display_clock **dc) -{ - struct display_clock_dce80 *disp_clk; - - disp_clk = FROM_DISPLAY_CLOCK(*dc); - dm_free(disp_clk); - *dc = NULL; -} - -static const struct display_clock_funcs funcs = { - .destroy = destroy, - .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency, - .get_required_clocks_state = get_required_clocks_state, - .set_clock = dce80_set_clock, - .set_min_clocks_state = dce80_set_min_clocks_state -}; - - -struct display_clock *dal_display_clock_dce80_create( - struct dc_context *ctx) -{ - struct display_clock_dce80 *disp_clk; - struct display_clock *dc_base; - - disp_clk = dm_alloc(sizeof(struct display_clock_dce80)); - - if (disp_clk == NULL) - return NULL; - - dc_base = &disp_clk->disp_clk; - - dc_base->ctx = ctx; - dc_base->min_display_clk_threshold_khz = 0; - - dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; - - dc_base->funcs = &funcs; - /* - * set_dp_ref_clock_source - * set_clock_state - * get_clock_state - * get_dfs_bypass_threshold - */ - - disp_clk->gpu_pll_ss_percentage = 0; - disp_clk->gpu_pll_ss_divider = 1000; - disp_clk->ss_on_gpu_pll = false; - disp_clk->dfs_bypass_enabled = false; - disp_clk->dfs_bypass_disp_clk = 0; - disp_clk->use_max_disp_clk = true;/* false will hang the system! */ - -/* Initially set max clocks state to nominal. This should be updated by - * via a pplib call to DAL IRI eventually calling a - * DisplayEngineClock_Dce50::StoreMaxClocksState(). This call will come in - * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/ - dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; -/* Initially set current min clocks state to invalid since we - * cannot make any assumption about PPLIB's initial state. This will be updated - * by HWSS via SetMinClocksState() on first mode set prior to programming - * state dependent clocks.*/ - disp_clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; - - display_clock_ss_construct(disp_clk); - - if (!display_clock_integrated_info_construct(disp_clk)) { - dm_logger_write(dc_base->ctx->logger, LOG_WARNING, - "Cannot obtain VBIOS integrated info"); - } - - dal_divider_range_construct( - ÷r_ranges[DIVIDER_RANGE_01], - DIVIDER_RANGE_01_START, - DIVIDER_RANGE_01_STEP_SIZE, - DIVIDER_RANGE_01_BASE_DIVIDER_ID, - DIVIDER_RANGE_02_BASE_DIVIDER_ID); - dal_divider_range_construct( - ÷r_ranges[DIVIDER_RANGE_02], - DIVIDER_RANGE_02_START, - DIVIDER_RANGE_02_STEP_SIZE, - DIVIDER_RANGE_02_BASE_DIVIDER_ID, - DIVIDER_RANGE_03_BASE_DIVIDER_ID); - dal_divider_range_construct( - ÷r_ranges[DIVIDER_RANGE_03], - DIVIDER_RANGE_03_START, - DIVIDER_RANGE_03_STEP_SIZE, - DIVIDER_RANGE_03_BASE_DIVIDER_ID, - DIVIDER_RANGE_MAX_DIVIDER_ID); - - dm_free(disp_clk); - return NULL; -} - diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h deleted file mode 100644 index c155bb6a4321..000000000000 --- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#ifndef __DAL_DISPLAY_CLOCK_DCE80_H__ -#define __DAL_DISPLAY_CLOCK_DCE80_H__ - -#include "display_clock_interface.h" - -struct display_clock_dce80 { - struct display_clock disp_clk; - /* DFS input - GPUPLL VCO frequency - from VBIOS Firmware info. */ - uint32_t dentist_vco_freq_khz; - /* GPU PLL SS percentage (if down-spread enabled)*/ - uint32_t gpu_pll_ss_percentage; - /* GPU PLL SS percentage Divider (100 or 1000)*/ - uint32_t gpu_pll_ss_divider; - /* Flag for Enabled SS on GPU PLL*/ - bool ss_on_gpu_pll; - /* Current minimum display block clocks state*/ - enum dm_pp_clocks_state cur_min_clks_state; - /* DFS-bypass feature variable - Cache the status of DFS-bypass feature*/ - bool dfs_bypass_enabled; - /* Cache the display clock returned by VBIOS if DFS-bypass is enabled. - * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */ - uint32_t dfs_bypass_disp_clk; - bool use_max_disp_clk; -}; - -struct display_clock *dal_display_clock_dce80_create( - struct dc_context *ctx); - -#endif /* __DAL_DISPLAY_CLOCK_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h index 6ba8c093793d..53a01381c638 100644 --- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h +++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h @@ -41,10 +41,9 @@ struct state_dependent_clocks { struct display_clock { struct dc_context *ctx; const struct display_clock_funcs *funcs; - uint32_t min_display_clk_threshold_khz; - /* Max display block clocks state*/ - enum dm_pp_clocks_state max_clks_state; + int min_display_clk_threshold_khz; + enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; }; @@ -61,15 +60,7 @@ struct display_clock_funcs { }; -struct display_clock *dal_display_clock_dce112_create( - struct dc_context *ctx); - -struct display_clock *dal_display_clock_dce110_create( - struct dc_context *ctx); - -struct display_clock *dal_display_clock_dce80_create( - struct dc_context *ctx); - void dal_display_clock_destroy(struct display_clock **to_destroy); + #endif /* __DISPLAY_CLOCK_INTERFACE_H__ */ -- cgit v1.2.3-59-g8ed1b From e91dbe3dee1acae4909bcc33288d47a779e8b27f Mon Sep 17 00:00:00 2001 From: Ding Wang Date: Mon, 5 Dec 2016 18:20:51 -0500 Subject: drm/amd/display: Temporarily blocking interlacing mode until it's supported. Signed-off-by: Ding Wang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 12a258763ef1..e70704d1ba87 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1117,6 +1117,10 @@ bool dce110_timing_generator_validate_timing( if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) return false; + /* Temporarily blocking interlacing mode until it's supported */ + if (timing->flags.INTERLACE == 1) + return false; + /* Check maximum number of pixels supported by Timing Generator * (Currently will never fail, in order to fail needs display which * needs more than 8192 horizontal and -- cgit v1.2.3-59-g8ed1b From a33fa99d8b8ec71a69e089e39ab1498d31169640 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 6 Dec 2016 11:26:08 -0500 Subject: drm/amd/display: Fix bunch of warnings in DC Some of those are potential bugs Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 ++- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 5 --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 41 ---------------------- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 2 -- .../drm/amd/display/dc/dce110/dce110_transform_v.c | 3 +- 6 files changed, 5 insertions(+), 53 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c index 0b2bb3992f1a..3b0710ef4716 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c @@ -1709,7 +1709,7 @@ static void calculate_bandwidth( else { data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])); if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) { - data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]))))); + data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]))))); } } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index bd53d27e5414..f552b0468186 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1834,11 +1834,10 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_vendor_info_packet( pipe_ctx->stream, &info_frame.vendor_info_packet); set_spd_info_packet(pipe_ctx->stream, &info_frame.spd_packet); - } - - else if (dc_is_dp_signal(signal)) + } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(pipe_ctx->stream, &info_frame.vsc_packet); set_spd_info_packet(pipe_ctx->stream, &info_frame.spd_packet); + } translate_info_frame(&info_frame, &pipe_ctx->encoder_info_frame); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 80ac5d9efa71..3d1c32122d69 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -465,7 +465,6 @@ static uint32_t dce110_get_pix_clk_dividers_helper ( struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) { - uint32_t addr = 0; uint32_t value = 0; uint32_t field = 0; uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; @@ -731,8 +730,6 @@ static void dce110_program_pixel_clk_resync( enum signal_type signal_type, enum dc_color_depth colordepth) { - uint32_t value = 0; - REG_UPDATE(RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, 0); /* @@ -772,8 +769,6 @@ static void dce112_program_pixel_clk_resync( enum dc_color_depth colordepth, bool enable_ycbcr420) { - uint32_t value = 0; - REG_UPDATE(PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 8e2519b1c9df..262612061c68 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -148,29 +148,6 @@ static int dce_divider_range_calc_divider( } -static int dce_divider_range_calc_did( - struct dce_divider_range *div_range, - int div) -{ - int did; - /* Check before dividing.*/ - if (div_range->div_range_step == 0) { - div_range->div_range_step = 1; - /*div_range_step cannot be zero*/ - BREAK_TO_DEBUGGER(); - } - /* Is this divider within our range?*/ - if ((div < div_range->div_range_start) - || (div >= div_range->div_range_end)) - return INVALID_DID; -/* did = (divider - range_start + (range_step-1)) / range_step) + did_min*/ - did = div - div_range->div_range_start; - did += div_range->div_range_step - 1; - did /= div_range->div_range_step; - did += div_range->did_min; - return did; -} - static int dce_divider_range_get_divider( struct dce_divider_range *div_range, int ranges_num, @@ -189,24 +166,6 @@ static int dce_divider_range_get_divider( return div; } -static int dce_divider_range_get_did( - struct dce_divider_range *div_range, - int ranges_num, - int divider) -{ - int did = INVALID_DID; - int i; - - for (i = 0; i < ranges_num; i++) { - /* CalcDid returns InvalidDid if a divider ID isn't found*/ - did = dce_divider_range_calc_did(&div_range[i], divider); - /* Found a valid return did*/ - if (did != INVALID_DID) - break; - } - return did; -} - static int dce_clocks_get_dp_ref_freq(struct display_clock *clk) { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index f47b6617f662..bbf4d97cb980 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -83,8 +83,6 @@ static bool setup_scaling_configuration( struct dce_transform *xfm_dce, const struct scaler_data *data) { - struct dc_context *ctx = xfm_dce->base.ctx; - if (data->taps.h_taps + data->taps.v_taps <= 2) { /* Set bypass */ REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index 7d8cf7a58f46..feb5f3c29804 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -621,7 +621,8 @@ static void dce110_xfmv_set_pixel_storage_depth( const struct bit_depth_reduction_params *bit_depth_params) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); - int pixel_depth, expan_mode; + int pixel_depth = 0; + int expan_mode = 0; uint32_t reg_data = 0; switch (depth) { -- cgit v1.2.3-59-g8ed1b From 9474980ac470a20d244318db9a7c12be01437805 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 8 Dec 2016 09:47:11 -0500 Subject: drm/amd/display: Added timing sync trace. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 32 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1 - .../gpu/drm/amd/display/include/logger_interface.h | 5 ++++ 5 files changed, 41 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8e1d695fcb77..de99d71f9042 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1488,8 +1488,10 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda core_dc->hwss.prepare_pipe_for_context( core_dc, pipe_ctx, context); } - if (apply_ctx) + if (apply_ctx) { core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); + context_timing_trace(dc, &context->res_ctx); + } } for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 8ca0f1e0369a..78b8e0c5b4e7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -22,6 +22,13 @@ ##__VA_ARGS__); \ } while (0) +#define TIMING_TRACE(...) do {\ + if (dc->debug.timing_trace) \ + dm_logger_write(logger, \ + LOG_SYNC, \ + ##__VA_ARGS__); \ +} while (0) + void pre_surface_trace( const struct dc *dc, const struct dc_surface *const *surfaces, @@ -268,3 +275,28 @@ void post_surface_trace(const struct dc *dc) SURFACE_TRACE("post surface process.\n"); } + +void context_timing_trace( + const struct dc *dc, + struct resource_context *res_ctx) +{ + int i; + struct core_dc *core_dc = DC_TO_CORE(dc); + struct dal_logger *logger = core_dc->ctx->logger; + + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + int h_pos = 0; + int v_pos = 0; + + if (pipe_ctx->stream == NULL) + continue; + + pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos, &v_pos); + TIMING_TRACE("Pipe_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", + pipe_ctx->pipe_idx, + pipe_ctx->stream->public.timing.h_total, + pipe_ctx->stream->public.timing.v_total, + h_pos, v_pos); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e1f2434ee95e..bb7cdde3e37b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -140,6 +140,7 @@ struct dc_debug { bool max_disp_clk; bool target_trace; bool surface_trace; + bool timing_trace; bool validation_trace; bool disable_stutter; bool disable_dcc; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6ad23f327631..99937facf645 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1892,7 +1892,6 @@ static void dce110_apply_ctx_for_surface( program_blender(dc, pipe_ctx); } - } static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index b58d30de8293..08a6911d3a3a 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -31,6 +31,7 @@ struct dc_context; struct dc_link; struct dc_surface_update; +struct resource_context; /* * @@ -85,6 +86,10 @@ void update_surface_trace( void post_surface_trace(const struct dc *dc); +void context_timing_trace( + const struct dc *dc, + struct resource_context *res_ctx); + /* Any function which is empty or have incomplete implementation should be * marked by this macro. -- cgit v1.2.3-59-g8ed1b From 98d2cc2b03d937af36ce5ef227ae57232bbe8471 Mon Sep 17 00:00:00 2001 From: Andrew Wong Date: Mon, 12 Dec 2016 11:17:06 -0500 Subject: drm/amd/display: Change locking of registers when flipping frames. - Introduce GRPH_UPDATE_LOCK around programming surface flip. - Remove the now unused graphic surface lock. - Add macros to get and set four registers - both immediate and H Retrace should not be enabled at the same time Signed-off-by: Andrew Wong Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-------- drivers/gpu/drm/amd/display/dc/dc_helper.c | 14 ++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 11 +++-------- .../gpu/drm/amd/display/dc/dce110/dce110_mem_input.c | 17 +++++++++++++++-- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +-- drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 13 +++++++++++++ 6 files changed, 47 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 41df500817ad..75b6e404d016 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1468,11 +1468,6 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda continue; if (updates[i].flip_addr) { - core_dc->hwss.pipe_control_lock( - core_dc->hwseq, - pipe_ctx->pipe_idx, - PIPE_LOCK_CONTROL_SURFACE, - true); core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); } @@ -1485,7 +1480,6 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda core_dc->hwss.pipe_control_lock( core_dc->hwseq, pipe_ctx->pipe_idx, - PIPE_LOCK_CONTROL_SURFACE | PIPE_LOCK_CONTROL_GRAPHICS | PIPE_LOCK_CONTROL_SCL | PIPE_LOCK_CONTROL_BLENDER | @@ -1515,8 +1509,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda pipe_ctx->pipe_idx, PIPE_LOCK_CONTROL_GRAPHICS | PIPE_LOCK_CONTROL_SCL | - PIPE_LOCK_CONTROL_BLENDER | - PIPE_LOCK_CONTROL_SURFACE, + PIPE_LOCK_CONTROL_BLENDER, false); } break; diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index c5ff7b6d733d..a950dd53bca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -65,6 +65,20 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, return reg_val; } +uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3, + uint8_t shift4, uint32_t mask4, uint32_t *field_value4) +{ + uint32_t reg_val = dm_read_reg(ctx, addr); + *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); + *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); + *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); + *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); + return reg_val; +} + uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index dd1cf5e6e949..cd9a371ae237 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -49,12 +49,11 @@ void dce_pipe_control_lock(struct dce_hwseq *hws, bool lock) { uint32_t lock_val = lock ? 1 : 0; - uint32_t dcp_grph, scl, dcp_grph_surf, blnd, update_lock_mode; + uint32_t dcp_grph, scl, blnd, update_lock_mode; - uint32_t val = REG_GET_5(BLND_V_UPDATE_LOCK[blnd_inst], + uint32_t val = REG_GET_4(BLND_V_UPDATE_LOCK[blnd_inst], BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph, BLND_SCL_V_UPDATE_LOCK, &scl, - BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf, BLND_BLND_V_UPDATE_LOCK, &blnd, BLND_V_UPDATE_LOCK_MODE, &update_lock_mode); @@ -64,19 +63,15 @@ void dce_pipe_control_lock(struct dce_hwseq *hws, if (control_mask & PIPE_LOCK_CONTROL_SCL) scl = lock_val; - if (control_mask & PIPE_LOCK_CONTROL_SURFACE) - dcp_grph_surf = lock_val; - if (control_mask & PIPE_LOCK_CONTROL_BLENDER) blnd = lock_val; if (control_mask & PIPE_LOCK_CONTROL_MODE) update_lock_mode = lock_val; - REG_SET_5(BLND_V_UPDATE_LOCK[blnd_inst], val, + REG_SET_4(BLND_V_UPDATE_LOCK[blnd_inst], val, BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph, BLND_SCL_V_UPDATE_LOCK, scl, - BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, dcp_grph_surf, BLND_BLND_V_UPDATE_LOCK, blnd, BLND_V_UPDATE_LOCK_MODE, update_lock_mode); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index af9d682f8943..a20feaedfca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -113,16 +113,25 @@ bool dce110_mem_input_program_surface_flip_and_addr( struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); uint32_t value = 0; + uint32_t value_old = 0; + uint32_t lock_value = 0; + + lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); + set_reg_field_value(lock_value, 1, GRPH_UPDATE, GRPH_UPDATE_LOCK); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value); value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL)); + value_old = value; if (flip_immediate) { - set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); + set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); } else { set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); } - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value); + if (value != value_old) { + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value); + } switch (address->type) { case PLN_ADDR_TYPE_GRAPHICS: @@ -147,6 +156,10 @@ bool dce110_mem_input_program_surface_flip_and_addr( if (flip_immediate) mem_input->current_address = *address; + lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); + set_reg_field_value(lock_value, 0, GRPH_UPDATE, GRPH_UPDATE_LOCK); + dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value); + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 50d499cc01a4..fcaf2c71e4eb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -40,8 +40,7 @@ enum pipe_lock_control { PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0, PIPE_LOCK_CONTROL_BLENDER = 1 << 1, PIPE_LOCK_CONTROL_SCL = 1 << 2, - PIPE_LOCK_CONTROL_SURFACE = 1 << 3, - PIPE_LOCK_CONTROL_MODE = 1 << 4 + PIPE_LOCK_CONTROL_MODE = 1 << 3 }; struct dce_hwseq; diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h index dbc8424f7b69..a07817472089 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -143,6 +143,13 @@ FN(reg_name, f2), v2, \ FN(reg_name, f3), v3) +#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ + generic_reg_get4(CTX, REG(reg_name), \ + FN(reg_name, f1), v1, \ + FN(reg_name, f2), v2, \ + FN(reg_name, f3), v3, \ + FN(reg_name, f4), v4) + #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ generic_reg_get5(CTX, REG(reg_name), \ FN(reg_name, f1), v1, \ @@ -280,6 +287,12 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3); +uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3, + uint8_t shift4, uint32_t mask4, uint32_t *field_value4); + uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, -- cgit v1.2.3-59-g8ed1b From fb735a9f29f94fcb29fee224b8da704a510a5a3a Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Tue, 13 Dec 2016 13:59:41 -0500 Subject: drm/amd/display: Add in/out transfer functions to DC Refactor part 1 of degamma/regamma programming. End goal is to have source and output transfer function in which dc can use to decide how to program the degamma and regamma HW. Gamma will be explicitly applied through dc_update_surfaces_for_target. Color module should build the logical curve with all adjustments applied and pass enough information for dc to program HW PWL. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 38 +++++++++++-- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 64 ++++++++++++++++------ drivers/gpu/drm/amd/display/dc/dc.h | 40 +++++++++++++- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 36 ++++-------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 ++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +- 6 files changed, 135 insertions(+), 52 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9a35e3bb8283..f20701a507da 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1455,6 +1455,34 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda surface->public.gamma_correction = updates[i].gamma; } + + if (updates[i].in_transfer_func && + updates[i].in_transfer_func != + surface->public.in_transfer_func) { + if (surface->public.in_transfer_func != NULL) + dc_transfer_func_release( + surface->public. + in_transfer_func); + + dc_transfer_func_retain( + updates[i].in_transfer_func); + surface->public.in_transfer_func = + updates[i].in_transfer_func; + } + + if (updates[i].out_transfer_func && + updates[i].out_transfer_func != + surface->public.out_transfer_func) { + if (surface->public.out_transfer_func != NULL) + dc_transfer_func_release( + surface->public. + out_transfer_func); + + dc_transfer_func_retain( + updates[i].out_transfer_func); + surface->public.out_transfer_func = + updates[i].out_transfer_func; + } } } @@ -1474,7 +1502,6 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda if (updates[i].plane_info || updates[i].scaling_info || is_new_pipe_surface[j]) { - apply_ctx = true; if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { @@ -1489,9 +1516,12 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda } } - if (updates[i].gamma) - core_dc->hwss.prepare_pipe_for_context( - core_dc, pipe_ctx, context); + if (is_new_pipe_surface[j] || + updates[i].gamma || + updates[i].in_transfer_func || + updates[i].out_transfer_func) + core_dc->hwss.set_gamma_correction( + pipe_ctx, pipe_ctx->surface); } if (apply_ctx) { core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 06d8b326714a..8d2668406f3a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -45,11 +45,18 @@ struct gamma { int ref_count; }; +struct transfer_func { + struct core_transfer_func protected; + int ref_count; +}; + #define DC_SURFACE_TO_SURFACE(dc_surface) container_of(dc_surface, struct surface, protected.public) #define CORE_SURFACE_TO_SURFACE(core_surface) container_of(core_surface, struct surface, protected) #define DC_GAMMA_TO_GAMMA(dc_gamma) \ container_of(dc_gamma, struct gamma, protected.public) +#define DC_TRANSFER_FUNC_TO_TRANSFER_FUNC(dc_tf) \ + container_of(dc_tf, struct transfer_func, protected.public) #define CORE_GAMMA_TO_GAMMA(core_gamma) \ container_of(core_gamma, struct gamma, protected) @@ -66,6 +73,12 @@ static void destruct(struct surface *surface) { if (surface->protected.public.gamma_correction != NULL) dc_gamma_release(surface->protected.public.gamma_correction); + if (surface->protected.public.in_transfer_func != NULL) + dc_transfer_func_release( + surface->protected.public.in_transfer_func); + if (surface->protected.public.out_transfer_func != NULL) + dc_transfer_func_release( + surface->protected.public.out_transfer_func); } /******************************************************************************* @@ -163,16 +176,6 @@ void dc_surface_release(const struct dc_surface *dc_surface) } } -static bool construct_gamma(struct gamma *gamma) -{ - return true; -} - -static void destruct_gamma(struct gamma *gamma) -{ - -} - void dc_gamma_retain(const struct dc_gamma *dc_gamma) { struct gamma *gamma = DC_GAMMA_TO_GAMMA(dc_gamma); @@ -185,10 +188,8 @@ void dc_gamma_release(const struct dc_gamma *dc_gamma) struct gamma *gamma = DC_GAMMA_TO_GAMMA(dc_gamma); --gamma->ref_count; - if (gamma->ref_count == 0) { - destruct_gamma(gamma); + if (gamma->ref_count == 0) dm_free(gamma); - } } struct dc_gamma *dc_create_gamma() @@ -198,17 +199,44 @@ struct dc_gamma *dc_create_gamma() if (gamma == NULL) goto alloc_fail; - if (false == construct_gamma(gamma)) - goto construct_fail; - dc_gamma_retain(&gamma->protected.public); return &gamma->protected.public; -construct_fail: - dm_free(gamma); +alloc_fail: + return NULL; +} + +void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf) +{ + struct transfer_func *tf = DC_TRANSFER_FUNC_TO_TRANSFER_FUNC(dc_tf); + + ++tf->ref_count; +} + +void dc_transfer_func_release(const struct dc_transfer_func *dc_tf) +{ + struct transfer_func *tf = DC_TRANSFER_FUNC_TO_TRANSFER_FUNC(dc_tf); + --tf->ref_count; + + if (tf->ref_count == 0) + dm_free(tf); +} + +struct dc_transfer_func *dc_create_transfer_func(const struct dc *dc) +{ + struct core_dc *core_dc = DC_TO_CORE(dc); + struct transfer_func *tf = dm_alloc(sizeof(*tf)); + + if (tf == NULL) + goto alloc_fail; + + dc_transfer_func_retain(&tf->protected.public); + + return &tf->protected.public; alloc_fail: return NULL; } + diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7733292d42f8..aeb0c3be24d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -201,7 +201,8 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); enum { RGB_256X3X16 = 256, - FLOAT_GAMMA_RAMP_MAX = 1025 + FLOAT_GAMMA_RAMP_MAX = 1025, + TRANSFER_FUNC_POINTS = 1025 }; enum dc_gamma_ramp_type { @@ -236,6 +237,31 @@ struct dc_gamma { uint32_t size; }; +enum dc_transfer_func_type { + TF_TYPE_PREDEFINED, + TF_TYPE_DISTRIBUTED_POINTS, +}; + +struct dc_transfer_func_distributed_points { + uint16_t red[TRANSFER_FUNC_POINTS]; + uint16_t green[TRANSFER_FUNC_POINTS]; + uint16_t blue[TRANSFER_FUNC_POINTS]; + uint16_t end_exponent; + uint16_t x_point_at_y1; +}; + +enum dc_transfer_func_predefined { + TRANSFER_FUNCTION_SRGB, + TRANSFER_FUNCTION_BT709, + TRANSFER_FUNCTION_LINEAR, +}; + +struct dc_transfer_func { + enum dc_transfer_func_type type; + enum dc_transfer_func_predefined tf; + struct dc_transfer_func_distributed_points tf_pts; +}; + struct dc_surface { bool visible; bool flip_immediate; @@ -256,7 +282,11 @@ struct dc_surface { bool horizontal_mirror; enum plane_stereo_format stereo_format; + /* TO BE REMOVED AFTER BELOW TRANSFER FUNCTIONS IMPLEMENTED */ const struct dc_gamma *gamma_correction; + + const struct dc_transfer_func *in_transfer_func; + const struct dc_transfer_func *out_transfer_func; }; struct dc_plane_info { @@ -287,8 +317,12 @@ struct dc_surface_update { /* following updates require alloc/sleep/spin that is not isr safe, * null means no updates */ + /* gamma TO BE REMOVED */ struct dc_gamma *gamma; + struct dc_transfer_func *in_transfer_func; + struct dc_transfer_func *out_transfer_func; + }; /* @@ -316,6 +350,10 @@ void dc_gamma_retain(const struct dc_gamma *dc_gamma); void dc_gamma_release(const struct dc_gamma *dc_gamma); struct dc_gamma *dc_create_gamma(void); +void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf); +void dc_transfer_func_release(const struct dc_transfer_func *dc_tf); +struct dc_transfer_func *dc_create_transfer_func(const struct dc *dc); + /* * This structure holds a surface address. There could be multiple addresses * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 99937facf645..f6984e9ed169 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -231,16 +231,20 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } -static bool set_gamma_ramp( - struct input_pixel_processor *ipp, - struct output_pixel_processor *opp, - const struct core_gamma *ramp, +static bool dce110_set_gamma_correction( + struct pipe_ctx *pipe_ctx, const struct core_surface *surface) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct output_pixel_processor *opp = pipe_ctx->opp; + const struct core_gamma *ramp = NULL; struct ipp_prescale_params prescale_params = { 0 }; struct pwl_params *regamma_params; bool result = false; + if (surface->public.gamma_correction) + ramp = DC_GAMMA_TO_CORE(surface->public.gamma_correction); + regamma_params = dm_alloc(sizeof(struct pwl_params)); if (regamma_params == NULL) goto regamma_alloc_fail; @@ -1842,33 +1846,13 @@ static void dce110_program_front_end_for_pipe( pipe_ctx->scl_data.recout.y); } - - -static void dce110_prepare_pipe_for_surface_commit( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) { - struct core_gamma *gamma = NULL; - - dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context); - - if (pipe_ctx->surface->public.gamma_correction) - gamma = DC_GAMMA_TO_CORE( - pipe_ctx->surface->public.gamma_correction); - - dc->hwss.set_gamma_correction( - pipe_ctx->ipp, - pipe_ctx->opp, - gamma, pipe_ctx->surface); -} - static void dce110_prepare_pipe_for_context( struct core_dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { dce110_power_on_pipe_if_needed(dc, pipe_ctx, context); - dce110_prepare_pipe_for_surface_commit(dc, pipe_ctx, context); + dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context); } static void dce110_apply_ctx_for_surface( @@ -1920,7 +1904,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, .update_pending_status = dce110_update_pending_status, - .set_gamma_correction = set_gamma_ramp, + .set_gamma_correction = dce110_set_gamma_correction, .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dce110_enable_timing_synchronization, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 3cf9bfb6decd..a67d6756095d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -66,6 +66,11 @@ struct core_gamma { struct dc_context *ctx; }; +struct core_transfer_func { + struct dc_transfer_func public; + struct dc_context *ctx; +}; + void enable_surface_flip_reporting(struct dc_surface *dc_surface, uint32_t controller_id); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index fcaf2c71e4eb..89a08342a51f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -78,9 +78,7 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx); bool (*set_gamma_correction)( - struct input_pixel_processor *ipp, - struct output_pixel_processor *opp, - const struct core_gamma *ramp, + struct pipe_ctx *pipe_ctx, const struct core_surface *surface); void (*power_down)(struct core_dc *dc); -- cgit v1.2.3-59-g8ed1b From 90e508ba253c9e43711a7bf16230cdb13d0b1440 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Thu, 15 Dec 2016 12:09:46 -0500 Subject: drm/amd/display: Refactor output transfer function to stream Refactor part 3 - Moving output transfer function from surface to stream Split HWSS to program degamma and regamma separately. Degamma should be dependent on input transfer function. And Regamma should depend on the desired output transfer function. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 11 ++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 23 +++++--- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 + drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 6 +- drivers/gpu/drm/amd/display/dc/dc.h | 9 +-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 65 ++++++++++++++++++---- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 7 ++- 8 files changed, 97 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index c073f4558cf4..364f2c970b6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -513,6 +513,7 @@ static void fill_gamma_from_crtc( struct dc_gamma *gamma; struct drm_crtc_state *state = crtc->state; struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data; + struct dc_transfer_func *input_tf; gamma = dc_create_gamma(); @@ -529,6 +530,16 @@ static void fill_gamma_from_crtc( gamma->size = sizeof(gamma->gamma_ramp_rgb256x3x16); dc_surface->gamma_correction = gamma; + + input_tf = dc_create_transfer_func(); + + if (input_tf == NULL) + return; + + input_tf->type = TF_TYPE_PREDEFINED; + input_tf->tf = TRANSFER_FUNCTION_SRGB; + + dc_surface->in_transfer_func = input_tf; } static void fill_plane_attributes( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f20701a507da..df1bae8ea92b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1394,6 +1394,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + struct core_stream *stream = pipe_ctx->stream; if (pipe_ctx->surface != surface) continue; @@ -1472,15 +1473,14 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda if (updates[i].out_transfer_func && updates[i].out_transfer_func != - surface->public.out_transfer_func) { - if (surface->public.out_transfer_func != NULL) + stream->public.out_transfer_func) { + if (stream->public.out_transfer_func != NULL) dc_transfer_func_release( - surface->public. + stream->public. out_transfer_func); - dc_transfer_func_retain( updates[i].out_transfer_func); - surface->public.out_transfer_func = + stream->public.out_transfer_func = updates[i].out_transfer_func; } } @@ -1516,12 +1516,19 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda } } + if (is_new_pipe_surface[j] || + updates[i].in_transfer_func) + core_dc->hwss.set_input_transfer_func( + pipe_ctx, pipe_ctx->surface); + if (is_new_pipe_surface[j] || updates[i].gamma || - updates[i].in_transfer_func || updates[i].out_transfer_func) - core_dc->hwss.set_gamma_correction( - pipe_ctx, pipe_ctx->surface); + core_dc->hwss.set_output_transfer_func( + pipe_ctx, + pipe_ctx->surface, + pipe_ctx->stream); + } if (apply_ctx) { core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 8d6aa607e1f5..237436e22720 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -89,6 +89,9 @@ static bool construct(struct core_stream *stream, static void destruct(struct core_stream *stream) { dc_sink_release(&stream->sink->public); + if (stream->public.out_transfer_func != NULL) + dc_transfer_func_release( + stream->public.out_transfer_func); } void dc_stream_retain(const struct dc_stream *dc_stream) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 8d2668406f3a..3ec1f363e43e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -76,9 +76,6 @@ static void destruct(struct surface *surface) if (surface->protected.public.in_transfer_func != NULL) dc_transfer_func_release( surface->protected.public.in_transfer_func); - if (surface->protected.public.out_transfer_func != NULL) - dc_transfer_func_release( - surface->protected.public.out_transfer_func); } /******************************************************************************* @@ -223,9 +220,8 @@ void dc_transfer_func_release(const struct dc_transfer_func *dc_tf) dm_free(tf); } -struct dc_transfer_func *dc_create_transfer_func(const struct dc *dc) +struct dc_transfer_func *dc_create_transfer_func() { - struct core_dc *core_dc = DC_TO_CORE(dc); struct transfer_func *tf = dm_alloc(sizeof(*tf)); if (tf == NULL) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 36f1c96605e8..ffea10c73275 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -254,6 +254,7 @@ struct dc_transfer_func_distributed_points { enum dc_transfer_func_predefined { TRANSFER_FUNCTION_SRGB, TRANSFER_FUNCTION_BT709, + TRANSFER_FUNCTION_PQ, TRANSFER_FUNCTION_LINEAR, }; @@ -287,7 +288,6 @@ struct dc_surface { const struct dc_gamma *gamma_correction; const struct dc_transfer_func *in_transfer_func; - const struct dc_transfer_func *out_transfer_func; }; struct dc_plane_info { @@ -353,7 +353,7 @@ struct dc_gamma *dc_create_gamma(void); void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf); void dc_transfer_func_release(const struct dc_transfer_func *dc_tf); -struct dc_transfer_func *dc_create_transfer_func(const struct dc *dc); +struct dc_transfer_func *dc_create_transfer_func(void); /* * This structure holds a surface address. There could be multiple addresses @@ -527,10 +527,11 @@ struct dc_stream { struct freesync_context freesync_ctx; - /* TODO: dithering */ - /* TODO: transfer function (CSC/regamma/gamut remap) */ + const struct dc_transfer_func *out_transfer_func; struct colorspace_transform gamut_remap_matrix; struct csc_transform csc_color_matrix; + + /* TODO: dithering */ /* TODO: custom INFO packets */ /* TODO: ABM info (DMCU) */ /* TODO: PSR info */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index f6984e9ed169..72017d5a8252 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -231,11 +231,61 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } -static bool dce110_set_gamma_correction( +static bool dce110_set_degamma( struct pipe_ctx *pipe_ctx, const struct core_surface *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; + const struct core_transfer_func *tf = NULL; + struct ipp_prescale_params prescale_params = { 0 }; + bool result = true; + + if (ipp == NULL) + return false; + + if (surface->public.in_transfer_func) + tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); + + build_prescale_params(&prescale_params, surface); + ipp->funcs->ipp_program_prescale(ipp, &prescale_params); + + if (tf == NULL) { + /* Default case if no input transfer function specified */ + ipp->funcs->ipp_set_degamma(ipp, + IPP_DEGAMMA_MODE_BYPASS); + } else if (tf->public.type == TF_TYPE_PREDEFINED) { + switch (tf->public.tf) { + case TRANSFER_FUNCTION_SRGB: + ipp->funcs->ipp_set_degamma(ipp, + IPP_DEGAMMA_MODE_HW_sRGB); + break; + case TRANSFER_FUNCTION_BT709: + ipp->funcs->ipp_set_degamma(ipp, + IPP_DEGAMMA_MODE_HW_xvYCC); + break; + case TRANSFER_FUNCTION_LINEAR: + ipp->funcs->ipp_set_degamma(ipp, + IPP_DEGAMMA_MODE_BYPASS); + break; + case TRANSFER_FUNCTION_PQ: + result = false; + break; + default: + result = false; + } + } else { + /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ + result = false; + } + + return result; +} + +static bool dce110_set_output_transfer_func( + struct pipe_ctx *pipe_ctx, + const struct core_surface *surface, /* Surface - To be removed */ + const struct core_stream *stream) +{ struct output_pixel_processor *opp = pipe_ctx->opp; const struct core_gamma *ramp = NULL; struct ipp_prescale_params prescale_params = { 0 }; @@ -253,20 +303,10 @@ static bool dce110_set_gamma_correction( opp->funcs->opp_power_on_regamma_lut(opp, true); - if (ipp) { - build_prescale_params(&prescale_params, surface); - ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - } - if (ramp && calculate_regamma_params(regamma_params, ramp, surface)) { - opp->funcs->opp_program_regamma_pwl(opp, regamma_params); - if (ipp) - ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { - if (ipp) - ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); } @@ -1904,7 +1944,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, .update_pending_status = dce110_update_pending_status, - .set_gamma_correction = dce110_set_gamma_correction, + .set_input_transfer_func = dce110_set_degamma, + .set_output_transfer_func = dce110_set_output_transfer_func, .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dce110_enable_timing_synchronization, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index a67d6756095d..c2d35c2c28bf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -55,6 +55,9 @@ struct core_target { #define DC_GAMMA_TO_CORE(dc_gamma) \ container_of(dc_gamma, struct core_gamma, public) +#define DC_TRANSFER_FUNC_TO_CORE(dc_transfer_func) \ + container_of(dc_transfer_func, struct core_transfer_func, public) + struct core_surface { struct dc_surface public; struct dc_surface_status status; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 89a08342a51f..0e803ca83bb9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -77,10 +77,15 @@ struct hw_sequencer_funcs { void (*update_pending_status)( struct pipe_ctx *pipe_ctx); - bool (*set_gamma_correction)( + bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, const struct core_surface *surface); + bool (*set_output_transfer_func)( + struct pipe_ctx *pipe_ctx, + const struct core_surface *surface, + const struct core_stream *stream); + void (*power_down)(struct core_dc *dc); void (*enable_accelerated_mode)(struct core_dc *dc); -- cgit v1.2.3-59-g8ed1b From e63d86dc9b59d72cf25c6bc75e641bceed4fcd40 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Fri, 16 Dec 2016 12:12:03 -0500 Subject: drm/amd/display: Implement PQ curve based on output transfer function Refactor part 5 - Regamma programming should be dependent on Output transfer function type Program sRGB gamma or PQ transfer function based on output transfer function. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c | 93 ++++++++++++++++++++-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +- drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h | 3 +- 3 files changed, 92 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c index 854796aa0c71..973be8f649cc 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c @@ -791,6 +791,82 @@ static inline struct fixed31_32 calculate_oem_mapped_value( max_index); } +static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y) +{ + /* consts for PQ gamma formula. */ + const struct fixed31_32 m1 = + dal_fixed31_32_from_fraction(159301758, 1000000000); + const struct fixed31_32 m2 = + dal_fixed31_32_from_fraction(7884375, 100000); + const struct fixed31_32 c1 = + dal_fixed31_32_from_fraction(8359375, 10000000); + const struct fixed31_32 c2 = + dal_fixed31_32_from_fraction(188515625, 10000000); + const struct fixed31_32 c3 = + dal_fixed31_32_from_fraction(186875, 10000); + + struct fixed31_32 l_pow_m1; + struct fixed31_32 base; + + if (dal_fixed31_32_lt(in_x, dal_fixed31_32_zero)) + in_x = dal_fixed31_32_zero; + + l_pow_m1 = dal_fixed31_32_pow(in_x, m1); + base = dal_fixed31_32_div( + dal_fixed31_32_add(c1, + (dal_fixed31_32_mul(c2, l_pow_m1))), + dal_fixed31_32_add(dal_fixed31_32_one, + (dal_fixed31_32_mul(c3, l_pow_m1)))); + *out_y = dal_fixed31_32_pow(base, m2); +} + +static void build_regamma_curve_pq(struct pwl_float_data_ex *rgb_regamma, + struct pwl_float_data *rgb_oem, + struct pixel_gamma_point *coeff128_oem, + const struct core_gamma *ramp, + const struct core_surface *surface, + uint32_t hw_points_num, + const struct hw_x_point *coordinate_x, + const struct gamma_pixel *axis_x, + struct dividers dividers) +{ + uint32_t i; + + struct pwl_float_data_ex *rgb = rgb_regamma; + const struct hw_x_point *coord_x = coordinate_x; + struct fixed31_32 x; + struct fixed31_32 output; + struct fixed31_32 scaling_factor = + dal_fixed31_32_from_fraction(8, 1000); + + /* use coord_x to retrieve coordinates chosen base on given user curve + * the x values are exponentially distributed and currently it is hard + * coded, the user curve shape is ignored. Need to recalculate coord_x + * based on input curve, translation from 256/1025 to 128 PWL points. + */ + for (i = 0; i <= hw_points_num; i++) { + /* Multiply 0.008 as regamma is 0-1 and FP16 input is 0-125. + * FP 1.0 = 80nits + */ + x = dal_fixed31_32_mul(coord_x->adjusted_x, scaling_factor); + + compute_pq(x, &output); + + /* should really not happen? */ + if (dal_fixed31_32_lt(output, dal_fixed31_32_zero)) + output = dal_fixed31_32_zero; + else if (dal_fixed31_32_lt(dal_fixed31_32_one, output)) + output = dal_fixed31_32_one; + + rgb->r = output; + rgb->g = output; + rgb->b = output; + + ++coord_x; + ++rgb; + } +} + static void build_regamma_curve(struct pwl_float_data_ex *rgb_regamma, struct pwl_float_data *rgb_oem, struct pixel_gamma_point *coeff128_oem, @@ -1286,7 +1362,8 @@ static bool convert_to_custom_float( bool calculate_regamma_params(struct pwl_params *params, const struct core_gamma *ramp, - const struct core_surface *surface) + const struct core_surface *surface, + const struct core_stream *stream) { struct gamma_curve *arr_curve_points = params->arr_curve_points; struct curve_points *arr_points = params->arr_points; @@ -1301,7 +1378,6 @@ bool calculate_regamma_params(struct pwl_params *params, struct pixel_gamma_point *coeff128_oem = NULL; struct pixel_gamma_point *coeff128 = NULL; - bool ret = false; coordinates_x = dm_alloc(sizeof(*coordinates_x)*(256 + 3)); @@ -1341,9 +1417,16 @@ bool calculate_regamma_params(struct pwl_params *params, setup_distribution_points(arr_curve_points, arr_points, ¶ms->hw_points_num, coordinates_x); - build_regamma_curve(rgb_regamma, rgb_oem, coeff128_oem, - ramp, surface, params->hw_points_num, - coordinates_x, axix_x_256, dividers); + if (stream->public.out_transfer_func && + stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { + build_regamma_curve_pq(rgb_regamma, rgb_oem, coeff128_oem, + ramp, surface, params->hw_points_num, + coordinates_x, axix_x_256, dividers); + } else { + build_regamma_curve(rgb_regamma, rgb_oem, coeff128_oem, + ramp, surface, params->hw_points_num, + coordinates_x, axix_x_256, dividers); + } map_regamma_hw_to_x_user(coeff128, rgb_oem, rgb_resulted, rgb_user, coordinates_x, axix_x_256, &ramp->public, rgb_regamma, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 72017d5a8252..2f790753b559 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -303,7 +303,8 @@ static bool dce110_set_output_transfer_func( opp->funcs->opp_power_on_regamma_lut(opp, true); - if (ramp && calculate_regamma_params(regamma_params, ramp, surface)) { + if (ramp && calculate_regamma_params( + regamma_params, ramp, surface, stream)) { opp->funcs->opp_program_regamma_pwl(opp, regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { diff --git a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h index e2c63fd4fe92..0712268856c2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h @@ -14,6 +14,7 @@ bool calculate_regamma_params(struct pwl_params *params, const struct core_gamma *ramp, - const struct core_surface *surface); + const struct core_surface *surface, + const struct core_stream *stream); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ */ -- cgit v1.2.3-59-g8ed1b From ab3ee7a556343c9549ccbefb9d31039377806f28 Mon Sep 17 00:00:00 2001 From: Zeyu Fan Date: Wed, 14 Dec 2016 18:54:41 -0500 Subject: drm/amd/display: OPP refactor and consolidation for DCE. Signed-off-by: Zeyu Fan Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 996 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 418 +++++++++ .../drm/amd/display/dc/dce100/dce100_resource.c | 61 +- drivers/gpu/drm/amd/display/dc/dce110/Makefile | 4 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c | 77 -- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h | 149 --- .../gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c | 363 -------- .../drm/amd/display/dc/dce110/dce110_opp_csc_v.c | 2 +- .../amd/display/dc/dce110/dce110_opp_formatter.c | 627 ------------- .../drm/amd/display/dc/dce110/dce110_opp_regamma.c | 537 ----------- .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 2 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 60 +- drivers/gpu/drm/amd/display/dc/dce112/Makefile | 3 +- drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c | 72 -- drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h | 48 - .../amd/display/dc/dce112/dce112_opp_formatter.c | 215 ----- .../drm/amd/display/dc/dce112/dce112_resource.c | 70 +- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 5 +- drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c | 136 --- drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.h | 130 --- .../gpu/drm/amd/display/dc/dce80/dce80_opp_csc.c | 363 -------- .../drm/amd/display/dc/dce80/dce80_opp_formatter.c | 577 ------------ .../drm/amd/display/dc/dce80/dce80_opp_regamma.c | 543 ----------- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 45 +- 26 files changed, 1547 insertions(+), 3960 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_csc.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_formatter.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_regamma.c (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 6add5977fd39..5ad59a27738c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -7,7 +7,7 @@ DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ -dce_clocks.o +dce_clocks.o dce_opp.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c new file mode 100644 index 000000000000..80443a1cccd2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -0,0 +1,996 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "basics/conversion.h" + +#include "dce_opp.h" + +#include "gamma_types.h" + +#include "reg_helper.h" + +#define REG(reg)\ + (opp110->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + opp110->opp_shift->field_name, opp110->opp_mask->field_name + +#define CTX \ + opp110->base.ctx + +enum { + MAX_PWL_ENTRY = 128, + MAX_REGIONS_NUMBER = 16 +}; + +enum { + MAX_LUT_ENTRY = 256, + MAX_NUMBER_OF_ENTRIES = 256 +}; + + +enum { + OUTPUT_CSC_MATRIX_SIZE = 12 +}; + +static const struct out_csc_color_matrix global_color_matrix[] = { +{ COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, +{ COLOR_SPACE_SRGB_LIMITED, + { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, +{ COLOR_SPACE_YCBCR601, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, + 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, + 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, +/* TODO: correct values below */ +{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } +}; + +enum csc_color_mode { + /* 00 - BITS2:0 Bypass */ + CSC_COLOR_MODE_GRAPHICS_BYPASS, + /* 01 - hard coded coefficient TV RGB */ + CSC_COLOR_MODE_GRAPHICS_PREDEFINED, + /* 04 - programmable OUTPUT CSC coefficient */ + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, +}; + + + + + + + + + + + + + + + + + + +/* + ***************************************************************************** + * Function: regamma_config_regions_and_segments + * + * build regamma curve by using predefined hw points + * uses interface parameters ,like EDID coeff. + * + * @param : parameters interface parameters + * @return void + * + * @note + * + * @see + * + ***************************************************************************** + */ +static void regamma_config_regions_and_segments( + struct dce110_opp *opp110, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + uint32_t value = 0; + + { + REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); + } + { + REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); + + } + { + REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, + REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); + } + { + REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, + REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[2].custom_float_slope, + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_y); + } + + curve = params->arr_curve_points; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } +} + +static void program_pwl( + struct dce110_opp *opp110, + const struct pwl_params *params) +{ + uint32_t value; + int retval; + + { + uint8_t max_tries = 10; + uint8_t counter = 0; + + /* Power on LUT memory */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 1); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); + + while (counter < max_tries) { + if (REG(DCFE_MEM_PWR_STATUS)) { + value = REG_READ(DCFE_MEM_PWR_STATUS); + REG_GET(DCFE_MEM_PWR_STATUS, + DCP_REGAMMA_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } else { + value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); + REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } + } + + if (counter == max_tries) { + dm_logger_write(opp110->base.ctx->logger, LOG_WARNING, + "%s: regamma lut was not powered on " + "in a timely manner," + " programming still proceeds\n", + __func__); + } + } + + REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, + REGAMMA_LUT_WRITE_EN_MASK, 7); + + REG_WRITE(REGAMMA_LUT_INDEX, 0); + + /* Program REGAMMA_LUT_DATA */ + { + uint32_t i = 0; + const struct pwl_result_data *rgb = params->rgb_resulted; + + while (i != params->hw_points_num) { + + REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); + + ++rgb; + ++i; + } + } + + /* we are done with DCP LUT memory; re-enable low power mode */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 0); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); +} + +bool dce110_opp_program_regamma_pwl( + struct output_pixel_processor *opp, + const struct pwl_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + /* Setup regions */ + regamma_config_regions_and_segments(opp110, params); + + /* Program PWL */ + program_pwl(opp110, params); + + return true; +} + +void dce110_opp_power_on_regamma_lut( + struct output_pixel_processor *opp, + bool power_on) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE_2(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, power_on, + DCP_LUT_MEM_PWR_DIS, power_on); + else + REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, + DCP_LUT_LIGHT_SLEEP_DIS, power_on); + +} + +void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, + enum opp_regamma mode) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + REG_SET(REGAMMA_CONTROL, 0, + GRPH_REGAMMA_MODE, mode); +} + +/** + * set_truncation + * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp + * 2) enable truncation + * 3) HW remove 12bit FMT support for DCE11 power saving reason. + */ +static void set_truncation( + struct dce110_opp *opp110, + const struct bit_depth_reduction_params *params) +{ + /*Disable truncation*/ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_TRUNCATE_EN, 0, + FMT_TRUNCATE_DEPTH, 0, + FMT_TRUNCATE_MODE, 0); + /* no 10bpc trunc on DCE11*/ + if (params->flags.TRUNCATE_ENABLED == 0 || + params->flags.TRUNCATE_DEPTH == 2) + return; + + /*Set truncation depth and Enable truncation*/ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_TRUNCATE_EN, 1, + FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_MODE, + FMT_TRUNCATE_MODE, params->flags.TRUNCATE_DEPTH); + +} + +/** + * set_spatial_dither + * 1) set spatial dithering mode: pattern of seed + * 2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp + * 3) set random seed + * 4) set random mode + * lfsr is reset every frame or not reset + * RGB dithering method + * 0: RGB data are all dithered with x^28+x^3+1 + * 1: R data is dithered with x^28+x^3+1 + * G data is dithered with x^28+X^9+1 + * B data is dithered with x^28+x^13+1 + * enable high pass filter or not + * 5) enable spatical dithering + */ +static void set_spatial_dither( + struct dce110_opp *opp110, + const struct bit_depth_reduction_params *params) +{ + /*Disable spatial (random) dithering*/ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_SPATIAL_DITHER_EN, 0, + FMT_SPATIAL_DITHER_DEPTH, 0, + FMT_SPATIAL_DITHER_MODE, 0); + + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_HIGHPASS_RANDOM_ENABLE, 0, + FMT_FRAME_RANDOM_ENABLE, 0, + FMT_RGB_RANDOM_ENABLE, 0); + + REG_UPDATE(FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_EN, 0); + + /* no 10bpc on DCE11*/ + if (params->flags.SPATIAL_DITHER_ENABLED == 0 || + params->flags.SPATIAL_DITHER_DEPTH == 2) + return; + + /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ + + if (opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX && + opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP) { + if (params->flags.FRAME_RANDOM == 1) { + if (params->flags.SPATIAL_DITHER_DEPTH == 0 || + params->flags.SPATIAL_DITHER_DEPTH == 1) { + REG_UPDATE_2(FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15, + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2); + } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { + REG_UPDATE_2(FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3, + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1); + } else + return; + } else { + REG_UPDATE_2(FMT_CONTROL, + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0, + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0); + } + } + /* Set seed for random values for + * spatial dithering for R,G,B channels + */ + REG_UPDATE(FMT_DITHER_RAND_R_SEED, + FMT_RAND_R_SEED, params->r_seed_value); + + REG_UPDATE(FMT_DITHER_RAND_G_SEED, + FMT_RAND_G_SEED, params->g_seed_value); + + REG_UPDATE(FMT_DITHER_RAND_B_SEED, + FMT_RAND_B_SEED, params->b_seed_value); + + /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero + * offset for the R/Cr channel, lower 4LSB + * is forced to zeros. Typically set to 0 + * RGB and 0x80000 YCbCr. + */ + /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero + * offset for the G/Y channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB + * and 0x80000 YCbCr. + */ + /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero + * offset for the B/Cb channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB and + * 0x80000 YCbCr. + */ + + /* Disable High pass filter + * Reset only at startup + * Set RGB data dithered with x^28+x^3+1 + */ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM, + FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM, + FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); + + /* Set spatial dithering bit depth + * Set spatial dithering mode + * (default is Seed patterrn AAAA...) + * Enable spatial dithering + */ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH, + FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE, + FMT_SPATIAL_DITHER_EN, 1); +} + +/** + * SetTemporalDither (Frame Modulation) + * 1) set temporal dither depth + * 2) select pattern: from hard-coded pattern or programmable pattern + * 3) select optimized strips for BGR or RGB LCD sub-pixel + * 4) set s matrix + * 5) set t matrix + * 6) set grey level for 0.25, 0.5, 0.75 + * 7) enable temporal dithering + */ + +static void set_temporal_dither( + struct dce110_opp *opp110, + const struct bit_depth_reduction_params *params) +{ + /*Disable temporal (frame modulation) dithering first*/ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_EN, 0, + FMT_TEMPORAL_DITHER_RESET, 0, + FMT_TEMPORAL_DITHER_OFFSET, 0); + + REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_DEPTH, 0, + FMT_TEMPORAL_LEVEL, 0); + + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_25FRC_SEL, 0, + FMT_50FRC_SEL, 0, + FMT_75FRC_SEL, 0); + + /* no 10bpc dither on DCE11*/ + if (params->flags.FRAME_MODULATION_ENABLED == 0 || + params->flags.FRAME_MODULATION_DEPTH == 2) + return; + + /* Set temporal dithering depth*/ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_DEPTH, params->flags.FRAME_MODULATION_DEPTH, + FMT_TEMPORAL_DITHER_RESET, 0, + FMT_TEMPORAL_DITHER_OFFSET, 0); + + /*Select legacy pattern based on FRC and Temporal level*/ + if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) { + REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0); + /*Set s matrix*/ + REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0); + /*Set t matrix*/ + REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0); + } + + /*Select patterns for 0.25, 0.5 and 0.75 grey level*/ + REG_UPDATE(FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_LEVEL, params->flags.TEMPORAL_LEVEL); + + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_25FRC_SEL, params->flags.FRC25, + FMT_50FRC_SEL, params->flags.FRC50, + FMT_75FRC_SEL, params->flags.FRC75); + + /*Enable bit reduction by temporal (frame modulation) dithering*/ + REG_UPDATE(FMT_BIT_DEPTH_CONTROL, + FMT_TEMPORAL_DITHER_EN, 1); +} + +/** + * Set Clamping + * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) + * 1 for 8 bpc + * 2 for 10 bpc + * 3 for 12 bpc + * 7 for programable + * 2) Enable clamp if Limited range requested + */ +void dce110_opp_set_clamping( + struct dce110_opp *opp110, + const struct clamping_and_pixel_encoding_params *params) +{ + uint32_t clamp_cntl_value = 0; + + REG_SET_2(FMT_CLAMP_CNTL, 0, + FMT_CLAMP_DATA_EN, 0, + FMT_CLAMP_COLOR_FORMAT, 0); + + switch (params->clamping_level) { + case CLAMPING_FULL_RANGE: + break; + case CLAMPING_LIMITED_RANGE_8BPC: + REG_SET_2(FMT_CLAMP_CNTL, 0, + FMT_CLAMP_DATA_EN, 1, + FMT_CLAMP_COLOR_FORMAT, 1); + break; + case CLAMPING_LIMITED_RANGE_10BPC: + REG_SET_2(FMT_CLAMP_CNTL, 0, + FMT_CLAMP_DATA_EN, 1, + FMT_CLAMP_COLOR_FORMAT, 2); + break; + case CLAMPING_LIMITED_RANGE_12BPC: + REG_SET_2(FMT_CLAMP_CNTL, 0, + FMT_CLAMP_DATA_EN, 1, + FMT_CLAMP_COLOR_FORMAT, 3); + break; + case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: + /*Set clamp control*/ + REG_SET_2(FMT_CLAMP_CNTL, 0, + FMT_CLAMP_DATA_EN, 1, + FMT_CLAMP_COLOR_FORMAT, 7); + + /*set the defaults*/ + REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, + FMT_CLAMP_LOWER_R, 0x10, + FMT_CLAMP_UPPER_R, 0xFEF); + + REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, + FMT_CLAMP_LOWER_G, 0x10, + FMT_CLAMP_UPPER_G, 0xFEF); + + REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, + FMT_CLAMP_LOWER_B, 0x10, + FMT_CLAMP_UPPER_B, 0xFEF); + break; + default: + break; + } +} + +/** + * set_pixel_encoding + * + * Set Pixel Encoding + * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly + * 1: YCbCr 4:2:2 + */ +static void set_pixel_encoding( + struct dce110_opp *opp110, + const struct clamping_and_pixel_encoding_params *params) +{ + if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS) + REG_UPDATE_3(FMT_CONTROL, + FMT_PIXEL_ENCODING, 0, + FMT_SUBSAMPLING_MODE, 0, + FMT_CBCR_BIT_REDUCTION_BYPASS, 0); + else + REG_UPDATE_2(FMT_CONTROL, + FMT_PIXEL_ENCODING, 0, + FMT_SUBSAMPLING_MODE, 0); + + if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(FMT_CONTROL, + FMT_PIXEL_ENCODING, 1, + FMT_SUBSAMPLING_ORDER, 0); + } + if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) { + REG_UPDATE_3(FMT_CONTROL, + FMT_PIXEL_ENCODING, 2, + FMT_SUBSAMPLING_MODE, 2, + FMT_CBCR_BIT_REDUCTION_BYPASS, 1); + } + +} + +void dce110_opp_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + set_truncation(opp110, params); + set_spatial_dither(opp110, params); + set_temporal_dither(opp110, params); +} + +void dce110_opp_program_clamping_and_pixel_encoding( + struct output_pixel_processor *opp, + const struct clamping_and_pixel_encoding_params *params) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + + dce110_opp_set_clamping(opp110, params); + set_pixel_encoding(opp110, params); +} + +static void program_formatter_420_memory(struct output_pixel_processor *opp) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + uint32_t fmt_mem_cntl_value; + + /* Program source select*/ + /* Use HW default source select for FMT_MEMORYx_CONTROL */ + /* Use that value for FMT_SRC_SELECT as well*/ + REG_GET(CONTROL, + FMT420_MEM0_SOURCE_SEL, &fmt_mem_cntl_value); + + REG_UPDATE(FMT_CONTROL, + FMT_SRC_SELECT, fmt_mem_cntl_value); + + /* Turn on the memory */ + REG_UPDATE(CONTROL, + FMT420_MEM0_PWR_FORCE, 0); +} + +void dce110_opp_set_dyn_expansion( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + bool enable_dyn_exp = false; + + REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, + FMT_DYNAMIC_EXP_EN, 0, + FMT_DYNAMIC_EXP_MODE, 0); + /* From HW programming guide: + FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output + FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/ + if (color_sp == COLOR_SPACE_SRGB) + enable_dyn_exp = true; + + /*00 - 10-bit -> 12-bit dynamic expansion*/ + /*01 - 8-bit -> 12-bit dynamic expansion*/ + if (signal == SIGNAL_TYPE_HDMI_TYPE_A) { + switch (color_dpth) { + case COLOR_DEPTH_888: + REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, + FMT_DYNAMIC_EXP_EN, enable_dyn_exp ? 1:0, + FMT_DYNAMIC_EXP_MODE, 1); + break; + case COLOR_DEPTH_101010: + REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, + FMT_DYNAMIC_EXP_EN, enable_dyn_exp ? 1:0, + FMT_DYNAMIC_EXP_MODE, 0); + break; + case COLOR_DEPTH_121212: + break; + default: + break; + } + } +} + +static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + uint8_t counter = 10; + + /* clear previous phase lock status*/ + REG_UPDATE(FMT_CONTROL, + FMT_420_PIXEL_PHASE_LOCKED_CLEAR, 1); + + /* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/ + REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10); + +} + +void dce110_opp_program_fmt( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping) +{ + /* dithering is affected by , hence should be + * programmed afterwards */ + + if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420) + program_formatter_420_memory(opp); + + dce110_opp_program_bit_depth_reduction( + opp, + fmt_bit_depth); + + dce110_opp_program_clamping_and_pixel_encoding( + opp, + clamping); + + if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420) + program_formatter_reset_dig_resync_fifo(opp); + + return; +} + +static void program_color_matrix( + struct dce110_opp *opp110, + const struct out_csc_color_matrix *tbl_entry, + enum grph_color_adjust_option options) +{ + { + REG_SET_2(OUTPUT_CSC_C11_C12, 0, + OUTPUT_CSC_C11, tbl_entry->regval[0], + OUTPUT_CSC_C12, tbl_entry->regval[1]); + } + { + REG_SET_2(OUTPUT_CSC_C13_C14, 0, + OUTPUT_CSC_C11, tbl_entry->regval[2], + OUTPUT_CSC_C12, tbl_entry->regval[3]); + } + { + REG_SET_2(OUTPUT_CSC_C21_C22, 0, + OUTPUT_CSC_C11, tbl_entry->regval[4], + OUTPUT_CSC_C12, tbl_entry->regval[5]); + } + { + REG_SET_2(OUTPUT_CSC_C23_C24, 0, + OUTPUT_CSC_C11, tbl_entry->regval[6], + OUTPUT_CSC_C12, tbl_entry->regval[7]); + } + { + REG_SET_2(OUTPUT_CSC_C31_C32, 0, + OUTPUT_CSC_C11, tbl_entry->regval[8], + OUTPUT_CSC_C12, tbl_entry->regval[9]); + } + { + REG_SET_2(OUTPUT_CSC_C33_C34, 0, + OUTPUT_CSC_C11, tbl_entry->regval[10], + OUTPUT_CSC_C12, tbl_entry->regval[11]); + } +} + +static bool configure_graphics_mode( + struct dce110_opp *opp110, + enum csc_color_mode config, + enum graphics_csc_adjust_type csc_adjust_type, + enum dc_color_space color_space) +{ + struct dc_context *ctx = opp110->base.ctx; + + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + + if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { + if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 4); + } else { + + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + break; + case COLOR_SPACE_SRGB_LIMITED: + /* TV RGB */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 1); + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YPBPR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 2); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YPBPR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 3); + break; + default: + return false; + } + } + } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + break; + break; + case COLOR_SPACE_SRGB_LIMITED: + /* TV RGB */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 1); + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YPBPR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 2); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YPBPR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 3); + break; + default: + return false; + } + + } else + /* by pass */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + + return true; +} + +void dce110_opp_set_csc_adjustment( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + + program_color_matrix( + opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); + + /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ + configure_graphics_mode(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW, + tbl_entry->color_space); +} + +void dce110_opp_set_csc_default( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust) +{ + struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_PREDEFINED; + + if (default_adjust->force_hw_default == false) { + const struct out_csc_color_matrix *elm; + /* currently parameter not in use */ + enum grph_color_adjust_option option = + GRPH_COLOR_MATRIX_HW_DEFAULT; + uint32_t i; + /* + * HW default false we program locally defined matrix + * HW default true we use predefined hw matrix and we + * do not need to program matrix + * OEM wants the HW default via runtime parameter. + */ + option = GRPH_COLOR_MATRIX_SW; + + for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { + elm = &global_color_matrix[i]; + if (elm->color_space != default_adjust->out_color_space) + continue; + /* program the matrix with default values from this + * file */ + program_color_matrix(opp110, elm, option); + config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + break; + } + } + + /* configure the what we programmed : + * 1. Default values from this file + * 2. Use hardware default from ROM_A and we do not need to program + * matrix */ + + configure_graphics_mode(opp110, config, + default_adjust->csc_adjust_type, + default_adjust->out_color_space); +} + + +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +static const struct opp_funcs funcs = { + .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, + .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, + .opp_set_csc_default = dce110_opp_set_csc_default, + .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, + .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode, + .opp_destroy = dce110_opp_destroy, + .opp_program_fmt = dce110_opp_program_fmt, + .opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction +}; + +bool dce110_opp_construct(struct dce110_opp *opp110, + struct dc_context *ctx, + uint32_t inst, + const struct dce_opp_registers *regs, + const struct dce_opp_shift *opp_shift, + const struct dce_opp_mask *opp_mask) +{ + opp110->base.funcs = &funcs; + + opp110->base.ctx = ctx; + + opp110->base.inst = inst; + + opp110->regs = regs; + opp110->opp_shift = opp_shift; + opp110->opp_mask = opp_mask; + + return true; +} + +void dce110_opp_destroy(struct output_pixel_processor **opp) +{ + dm_free(FROM_DCE11_OPP(*opp)); + *opp = NULL; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h new file mode 100644 index 000000000000..1c01a83ecc50 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -0,0 +1,418 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPP_DCE_H__ +#define __DC_OPP_DCE_H__ + +#include "dc_types.h" +#include "opp.h" +#include "core_types.h" + +#include "gamma_types.h" /* decprecated */ + +struct gamma_parameters; + +#define FROM_DCE11_OPP(opp)\ + container_of(opp, struct dce110_opp, base) + +enum dce110_opp_reg_type { + DCE110_OPP_REG_DCP = 0, + DCE110_OPP_REG_DCFE, + DCE110_OPP_REG_FMT, + + DCE110_OPP_REG_MAX +}; + +#define OPP_COMMON_REG_LIST_BASE(id) \ + SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ + SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ + SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ + SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ + SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ + SRI(REGAMMA_LUT_INDEX, DCP, id), \ + SRI(REGAMMA_LUT_DATA, DCP, id), \ + SRI(REGAMMA_CONTROL, DCP, id), \ + SRI(OUTPUT_CSC_C11_C12, DCP, id), \ + SRI(OUTPUT_CSC_C13_C14, DCP, id), \ + SRI(OUTPUT_CSC_C21_C22, DCP, id), \ + SRI(OUTPUT_CSC_C23_C24, DCP, id), \ + SRI(OUTPUT_CSC_C31_C32, DCP, id), \ + SRI(OUTPUT_CSC_C33_C34, DCP, id), \ + SRI(OUTPUT_CSC_CONTROL, DCP, id), \ + SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ + SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ + SRI(FMT_CONTROL, FMT, id), \ + SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ + SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ + SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ + SRI(FMT_CLAMP_CNTL, FMT, id), \ + SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ + SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ + SRI(FMT_CLAMP_COMPONENT_B, FMT, id) + +#define OPP_DCE_80_REG_LIST(id) \ + OPP_COMMON_REG_LIST_BASE(id), \ + SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \ + SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) + +#define OPP_DCE_100_REG_LIST(id) \ + OPP_COMMON_REG_LIST_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ + SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \ + SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) + +#define OPP_DCE_110_REG_LIST(id) \ + OPP_COMMON_REG_LIST_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ + SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ + SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) + +#define OPP_DCE_112_REG_LIST(id) \ + OPP_COMMON_REG_LIST_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ + SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ + SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ + SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ + SRI(CONTROL, FMT_MEMORY, id) + +#define OPP_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ + OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ + OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ + OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ + OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ + OPP_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ + OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ + OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ + OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ + OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ + OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ + OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ + OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ + OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ + OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ + OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ + OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ + OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ + OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) + +#define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) + +#define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) + +#define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ + OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) + +#define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ + OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) + +#define OPP_REG_FIELD_LIST(type) \ + type DCP_REGAMMA_MEM_PWR_DIS; \ + type DCP_LUT_MEM_PWR_DIS; \ + type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ + type DCP_LUT_LIGHT_SLEEP_DIS; \ + type REGAMMA_CNTLA_EXP_REGION_START; \ + type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ + type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ + type REGAMMA_CNTLA_EXP_REGION_END; \ + type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ + type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ + type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ + type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ + type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ + type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ + type DCP_REGAMMA_MEM_PWR_STATE; \ + type REGAMMA_LUT_MEM_PWR_STATE; \ + type REGAMMA_LUT_WRITE_EN_MASK; \ + type GRPH_REGAMMA_MODE; \ + type OUTPUT_CSC_C11; \ + type OUTPUT_CSC_C12; \ + type OUTPUT_CSC_GRPH_MODE; \ + type FMT_DYNAMIC_EXP_EN; \ + type FMT_DYNAMIC_EXP_MODE; \ + type FMT_TRUNCATE_EN; \ + type FMT_TRUNCATE_DEPTH; \ + type FMT_TRUNCATE_MODE; \ + type FMT_SPATIAL_DITHER_EN; \ + type FMT_SPATIAL_DITHER_DEPTH; \ + type FMT_SPATIAL_DITHER_MODE; \ + type FMT_TEMPORAL_DITHER_EN; \ + type FMT_TEMPORAL_DITHER_RESET; \ + type FMT_TEMPORAL_DITHER_OFFSET; \ + type FMT_TEMPORAL_DITHER_DEPTH; \ + type FMT_TEMPORAL_LEVEL; \ + type FMT_25FRC_SEL; \ + type FMT_50FRC_SEL; \ + type FMT_75FRC_SEL; \ + type FMT_HIGHPASS_RANDOM_ENABLE; \ + type FMT_FRAME_RANDOM_ENABLE; \ + type FMT_RGB_RANDOM_ENABLE; \ + type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ + type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ + type FMT_RAND_R_SEED; \ + type FMT_RAND_G_SEED; \ + type FMT_RAND_B_SEED; \ + type FMT420_MEM0_SOURCE_SEL; \ + type FMT420_MEM0_PWR_FORCE; \ + type FMT_SRC_SELECT; \ + type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \ + type FMT_420_PIXEL_PHASE_LOCKED; \ + type FMT_CLAMP_DATA_EN; \ + type FMT_CLAMP_COLOR_FORMAT; \ + type FMT_CLAMP_LOWER_R; \ + type FMT_CLAMP_UPPER_R; \ + type FMT_CLAMP_LOWER_G; \ + type FMT_CLAMP_UPPER_G; \ + type FMT_CLAMP_LOWER_B; \ + type FMT_CLAMP_UPPER_B; \ + type FMT_PIXEL_ENCODING; \ + type FMT_SUBSAMPLING_ORDER; \ + type FMT_SUBSAMPLING_MODE; \ + type FMT_CBCR_BIT_REDUCTION_BYPASS;\ + +struct dce_opp_shift { + OPP_REG_FIELD_LIST(uint8_t) +}; + +struct dce_opp_mask { + OPP_REG_FIELD_LIST(uint32_t) +}; + +struct dce_opp_registers { + uint32_t DCFE_MEM_PWR_CTRL; + uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; + uint32_t REGAMMA_CNTLA_START_CNTL; + uint32_t REGAMMA_CNTLA_SLOPE_CNTL; + uint32_t REGAMMA_CNTLA_END_CNTL1; + uint32_t REGAMMA_CNTLA_END_CNTL2; + uint32_t REGAMMA_CNTLA_REGION_0_1; + uint32_t REGAMMA_CNTLA_REGION_2_3; + uint32_t REGAMMA_CNTLA_REGION_4_5; + uint32_t REGAMMA_CNTLA_REGION_6_7; + uint32_t REGAMMA_CNTLA_REGION_8_9; + uint32_t REGAMMA_CNTLA_REGION_10_11; + uint32_t REGAMMA_CNTLA_REGION_12_13; + uint32_t REGAMMA_CNTLA_REGION_14_15; + uint32_t REGAMMA_LUT_WRITE_EN_MASK; + uint32_t REGAMMA_LUT_INDEX; + uint32_t DCFE_MEM_PWR_STATUS; + uint32_t REGAMMA_LUT_DATA; + uint32_t REGAMMA_CONTROL; + uint32_t OUTPUT_CSC_C11_C12; + uint32_t OUTPUT_CSC_C13_C14; + uint32_t OUTPUT_CSC_C21_C22; + uint32_t OUTPUT_CSC_C23_C24; + uint32_t OUTPUT_CSC_C31_C32; + uint32_t OUTPUT_CSC_C33_C34; + uint32_t OUTPUT_CSC_CONTROL; + uint32_t FMT_DYNAMIC_EXP_CNTL; + uint32_t FMT_BIT_DEPTH_CONTROL; + uint32_t FMT_CONTROL; + uint32_t FMT_DITHER_RAND_R_SEED; + uint32_t FMT_DITHER_RAND_G_SEED; + uint32_t FMT_DITHER_RAND_B_SEED; + uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; + uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; + uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; + uint32_t CONTROL; + uint32_t FMT_CLAMP_CNTL; + uint32_t FMT_CLAMP_COMPONENT_R; + uint32_t FMT_CLAMP_COMPONENT_G; + uint32_t FMT_CLAMP_COMPONENT_B; +}; + +struct dce110_regamma { + struct gamma_curve arr_curve_points[16]; + struct curve_points arr_points[3]; + uint32_t hw_points_num; + struct hw_x_point *coordinates_x; + struct pwl_result_data *rgb_resulted; + + /* re-gamma curve */ + struct pwl_float_data_ex *rgb_regamma; + /* coeff used to map user evenly distributed points + * to our hardware points (predefined) for gamma 256 */ + struct pixel_gamma_point *coeff128; + struct pixel_gamma_point *coeff128_oem; + /* coeff used to map user evenly distributed points + * to our hardware points (predefined) for gamma 1025 */ + struct pixel_gamma_point *coeff128_dx; + /* evenly distributed points, gamma 256 software points 0-255 */ + struct gamma_pixel *axis_x_256; + /* evenly distributed points, gamma 1025 software points 0-1025 */ + struct gamma_pixel *axis_x_1025; + /* OEM supplied gamma for regamma LUT */ + struct pwl_float_data *rgb_oem; + /* user supplied gamma */ + struct pwl_float_data *rgb_user; + uint32_t extra_points; + bool use_half_points; + struct fixed31_32 x_max1; + struct fixed31_32 x_max2; + struct fixed31_32 x_min; + struct fixed31_32 divider1; + struct fixed31_32 divider2; + struct fixed31_32 divider3; +}; + +/* OPP RELATED */ +#define TO_DCE110_OPP(opp)\ + container_of(opp, struct dce110_opp, base) + +struct dce110_opp { + struct output_pixel_processor base; + const struct dce_opp_registers *regs; + const struct dce_opp_shift *opp_shift; + const struct dce_opp_mask *opp_mask; + struct dce110_regamma regamma; +}; + +bool dce110_opp_construct(struct dce110_opp *opp110, + struct dc_context *ctx, + uint32_t inst, + const struct dce_opp_registers *regs, + const struct dce_opp_shift *opp_shift, + const struct dce_opp_mask *opp_mask); + +void dce110_opp_destroy(struct output_pixel_processor **opp); + +/* REGAMMA RELATED */ +void dce110_opp_power_on_regamma_lut( + struct output_pixel_processor *opp, + bool power_on); + +bool dce110_opp_program_regamma_pwl( + struct output_pixel_processor *opp, + const struct pwl_params *params); + +void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, + enum opp_regamma mode); + +void dce110_opp_set_csc_adjustment( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry); + +void dce110_opp_set_csc_default( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust); + +/* FORMATTER RELATED */ +void dce110_opp_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + +void dce110_opp_program_clamping_and_pixel_encoding( + struct output_pixel_processor *opp, + const struct clamping_and_pixel_encoding_params *params); + +void dce110_opp_set_dyn_expansion( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); + +void dce110_opp_program_fmt( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + +void dce110_opp_set_clamping( + struct dce110_opp *opp110, + const struct clamping_and_pixel_encoding_params *params); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index c97416f7bc93..161d4eee4423 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -39,7 +39,7 @@ #include "dce110/dce110_mem_input_v.h" #include "dce110/dce110_ipp.h" #include "dce/dce_transform.h" -#include "dce110/dce110_opp.h" +#include "dce/dce_opp.h" #include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" @@ -302,6 +302,29 @@ static const struct dce_stream_encoder_mask se_mask = { SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) }; +#define opp_regs(id)\ +[id] = {\ + OPP_DCE_100_REG_LIST(id),\ +} + +static const struct dce_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3), + opp_regs(4), + opp_regs(5) +}; + +static const struct dce_opp_shift opp_shift = { + OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) +}; + +static const struct dce_opp_mask opp_mask = { + OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) +}; + + #define audio_regs(id)\ [id] = {\ AUD_COMMON_REG_LIST(id)\ @@ -348,35 +371,6 @@ static const struct dce110_clk_src_mask cs_mask = { #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 -static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = { -{ - .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT_CONTROL), - .dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), - .dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), - .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), - .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), - .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), - .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), - .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -} -}; - static const struct bios_registers bios_regs = { .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 }; @@ -615,8 +609,7 @@ struct link_encoder *dce100_link_encoder_create( struct output_pixel_processor *dce100_opp_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offset) + uint32_t inst) { struct dce110_opp *opp = dm_alloc(sizeof(struct dce110_opp)); @@ -625,7 +618,7 @@ struct output_pixel_processor *dce100_opp_create( return NULL; if (dce110_opp_construct(opp, - ctx, inst, offset)) + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) return &opp->base; BREAK_TO_DEBUGGER(); @@ -1052,7 +1045,7 @@ static bool construct( goto res_create_fail; } - pool->base.opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]); + pool->base.opps[i] = dce100_opp_create(ctx, i); if (pool->base.opps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index cd7a9095fa06..9c42afcac325 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -3,8 +3,8 @@ # It provides the control and status of HW CRTC block. DCE110 = dce110_ipp.o dce110_ipp_cursor.o \ -dce110_ipp_gamma.o dce110_opp.o dce110_opp_csc.o \ -dce110_timing_generator.o dce110_opp_formatter.o dce110_opp_regamma.o \ +dce110_ipp_gamma.o \ +dce110_timing_generator.o \ dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \ dce110_resource.o \ dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c deleted file mode 100644 index 698ec2f55d0f..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -/* include DCE11 register header files */ -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "dce110_opp.h" - -#include "gamma_types.h" - -enum { - MAX_LUT_ENTRY = 256, - MAX_NUMBER_OF_ENTRIES = 256 -}; - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -static const struct opp_funcs funcs = { - .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, - .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, - .opp_set_csc_default = dce110_opp_set_csc_default, - .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, - .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, - .opp_set_regamma_mode = dce110_opp_set_regamma_mode, - .opp_destroy = dce110_opp_destroy, - .opp_program_fmt = dce110_opp_program_fmt, -}; - -bool dce110_opp_construct(struct dce110_opp *opp110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offsets) -{ - opp110->base.funcs = &funcs; - - opp110->base.ctx = ctx; - - opp110->base.inst = inst; - - opp110->offsets = *offsets; - - return true; -} - -void dce110_opp_destroy(struct output_pixel_processor **opp) -{ - dm_free(FROM_DCE11_OPP(*opp)); - *opp = NULL; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h deleted file mode 100644 index 2fbb2415cc97..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h +++ /dev/null @@ -1,149 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_OPP_DCE110_H__ -#define __DC_OPP_DCE110_H__ - -#include "dc_types.h" -#include "opp.h" -#include "core_types.h" - -#include "gamma_types.h" /* decprecated */ - -struct gamma_parameters; - -#define FROM_DCE11_OPP(opp)\ - container_of(opp, struct dce110_opp, base) - -enum dce110_opp_reg_type { - DCE110_OPP_REG_DCP = 0, - DCE110_OPP_REG_DCFE, - DCE110_OPP_REG_FMT, - - DCE110_OPP_REG_MAX -}; - -struct dce110_regamma { - struct gamma_curve arr_curve_points[16]; - struct curve_points arr_points[3]; - uint32_t hw_points_num; - struct hw_x_point *coordinates_x; - struct pwl_result_data *rgb_resulted; - - /* re-gamma curve */ - struct pwl_float_data_ex *rgb_regamma; - /* coeff used to map user evenly distributed points - * to our hardware points (predefined) for gamma 256 */ - struct pixel_gamma_point *coeff128; - struct pixel_gamma_point *coeff128_oem; - /* coeff used to map user evenly distributed points - * to our hardware points (predefined) for gamma 1025 */ - struct pixel_gamma_point *coeff128_dx; - /* evenly distributed points, gamma 256 software points 0-255 */ - struct gamma_pixel *axis_x_256; - /* evenly distributed points, gamma 1025 software points 0-1025 */ - struct gamma_pixel *axis_x_1025; - /* OEM supplied gamma for regamma LUT */ - struct pwl_float_data *rgb_oem; - /* user supplied gamma */ - struct pwl_float_data *rgb_user; - uint32_t extra_points; - bool use_half_points; - struct fixed31_32 x_max1; - struct fixed31_32 x_max2; - struct fixed31_32 x_min; - struct fixed31_32 divider1; - struct fixed31_32 divider2; - struct fixed31_32 divider3; -}; - -/* OPP RELATED */ -#define TO_DCE110_OPP(opp)\ - container_of(opp, struct dce110_opp, base) - -struct dce110_opp_reg_offsets { - uint32_t fmt_offset; - uint32_t fmt_mem_offset; - uint32_t dcp_offset; - uint32_t dcfe_offset; -}; - -struct dce110_opp { - struct output_pixel_processor base; - struct dce110_opp_reg_offsets offsets; - struct dce110_regamma regamma; -}; - -bool dce110_opp_construct(struct dce110_opp *opp110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offsets); - -void dce110_opp_destroy(struct output_pixel_processor **opp); - -/* REGAMMA RELATED */ -void dce110_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on); - -bool dce110_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *params); - -void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode); - -void dce110_opp_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry); - -void dce110_opp_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust); - -/* FORMATTER RELATED */ -void dce110_opp_program_bit_depth_reduction( - struct output_pixel_processor *opp, - const struct bit_depth_reduction_params *params); - -void dce110_opp_program_clamping_and_pixel_encoding( - struct output_pixel_processor *opp, - const struct clamping_and_pixel_encoding_params *params); - -void dce110_opp_set_dyn_expansion( - struct output_pixel_processor *opp, - enum dc_color_space color_sp, - enum dc_color_depth color_dpth, - enum signal_type signal); - -void dce110_opp_program_fmt( - struct output_pixel_processor *opp, - struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping); - -void dce110_opp_set_clamping( - struct dce110_opp *opp110, - const struct clamping_and_pixel_encoding_params *params); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c deleted file mode 100644 index b46db202ddbb..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "dce110_opp.h" -#include "basics/conversion.h" - -/* include DCE11 register header files */ -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#define DCP_REG(reg)\ - (reg + opp110->offsets.dcp_offset) - -enum { - OUTPUT_CSC_MATRIX_SIZE = 12 -}; - -static const struct out_csc_color_matrix global_color_matrix[] = { -{ COLOR_SPACE_SRGB, - { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, -{ COLOR_SPACE_SRGB_LIMITED, - { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, -{ COLOR_SPACE_YCBCR601, - { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, - 0xF6B9, 0xE00, 0x1000} }, -{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, - 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, -/* TODO: correct values below */ -{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, - 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, -{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, - 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } -}; - -enum csc_color_mode { - /* 00 - BITS2:0 Bypass */ - CSC_COLOR_MODE_GRAPHICS_BYPASS, - /* 01 - hard coded coefficient TV RGB */ - CSC_COLOR_MODE_GRAPHICS_PREDEFINED, - /* 04 - programmable OUTPUT CSC coefficient */ - CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, -}; - -static void program_color_matrix( - struct dce110_opp *opp110, - const struct out_csc_color_matrix *tbl_entry, - enum grph_color_adjust_option options) -{ - struct dc_context *ctx = opp110->base.ctx; - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[0], - OUTPUT_CSC_C11_C12, - OUTPUT_CSC_C11); - - set_reg_field_value( - value, - tbl_entry->regval[1], - OUTPUT_CSC_C11_C12, - OUTPUT_CSC_C12); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[2], - OUTPUT_CSC_C13_C14, - OUTPUT_CSC_C13); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[3], - OUTPUT_CSC_C13_C14, - OUTPUT_CSC_C14); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[4], - OUTPUT_CSC_C21_C22, - OUTPUT_CSC_C21); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[5], - OUTPUT_CSC_C21_C22, - OUTPUT_CSC_C22); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[6], - OUTPUT_CSC_C23_C24, - OUTPUT_CSC_C23); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[7], - OUTPUT_CSC_C23_C24, - OUTPUT_CSC_C24); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[8], - OUTPUT_CSC_C31_C32, - OUTPUT_CSC_C31); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[9], - OUTPUT_CSC_C31_C32, - OUTPUT_CSC_C32); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[10], - OUTPUT_CSC_C33_C34, - OUTPUT_CSC_C33); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[11], - OUTPUT_CSC_C33_C34, - OUTPUT_CSC_C34); - - dm_write_reg(ctx, addr, value); - } -} - -static bool configure_graphics_mode( - struct dce110_opp *opp110, - enum csc_color_mode config, - enum graphics_csc_adjust_type csc_adjust_type, - enum dc_color_space color_space) -{ - struct dc_context *ctx = opp110->base.ctx; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL); - uint32_t value = dm_read_reg(ctx, addr); - - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - - if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { - if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { - set_reg_field_value( - value, - 4, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - } else { - - switch (color_space) { - case COLOR_SPACE_SRGB: - /* by pass */ - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_SRGB_LIMITED: - /* TV RGB */ - set_reg_field_value( - value, - 1, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: - case COLOR_SPACE_YCBCR601_LIMITED: - /* YCbCr601 */ - set_reg_field_value( - value, - 2, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: - case COLOR_SPACE_YCBCR709_LIMITED: - /* YCbCr709 */ - set_reg_field_value( - value, - 3, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - default: - return false; - } - } - } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { - switch (color_space) { - case COLOR_SPACE_SRGB: - /* by pass */ - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_SRGB_LIMITED: - /* TV RGB */ - set_reg_field_value( - value, - 1, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: - case COLOR_SPACE_YCBCR601_LIMITED: - /* YCbCr601 */ - set_reg_field_value( - value, - 2, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: - case COLOR_SPACE_YCBCR709_LIMITED: - /* YCbCr709 */ - set_reg_field_value( - value, - 3, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - default: - return false; - } - - } else - /* by pass */ - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - - addr = DCP_REG(mmOUTPUT_CSC_CONTROL); - dm_write_reg(ctx, addr, value); - - return true; -} - -void dce110_opp_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - enum csc_color_mode config = - CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - - program_color_matrix( - opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); - - /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ - configure_graphics_mode(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW, - tbl_entry->color_space); -} - -void dce110_opp_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - enum csc_color_mode config = - CSC_COLOR_MODE_GRAPHICS_PREDEFINED; - - if (default_adjust->force_hw_default == false) { - const struct out_csc_color_matrix *elm; - /* currently parameter not in use */ - enum grph_color_adjust_option option = - GRPH_COLOR_MATRIX_HW_DEFAULT; - uint32_t i; - /* - * HW default false we program locally defined matrix - * HW default true we use predefined hw matrix and we - * do not need to program matrix - * OEM wants the HW default via runtime parameter. - */ - option = GRPH_COLOR_MATRIX_SW; - - for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { - elm = &global_color_matrix[i]; - if (elm->color_space != default_adjust->out_color_space) - continue; - /* program the matrix with default values from this - * file */ - program_color_matrix(opp110, elm, option); - config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - break; - } - } - - /* configure the what we programmed : - * 1. Default values from this file - * 2. Use hardware default from ROM_A and we do not need to program - * matrix */ - - configure_graphics_mode(opp110, config, - default_adjust->csc_adjust_type, - default_adjust->out_color_space); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c index 975466f6e424..6995a3de7564 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c @@ -24,7 +24,7 @@ */ #include "dm_services.h" -#include "dce110_opp.h" +#include "dce/dce_opp.h" #include "basics/conversion.h" /* include DCE11 register header files */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c deleted file mode 100644 index eac20775c23f..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_formatter.c +++ /dev/null @@ -1,627 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "dce110_opp.h" - -#define FMT_REG(reg)\ - (reg + opp110->offsets.fmt_offset) -/** - * set_truncation - * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp - * 2) enable truncation - * 3) HW remove 12bit FMT support for DCE11 power saving reason. - */ -static void set_truncation( - struct dce110_opp *opp110, - const struct bit_depth_reduction_params *params) -{ - uint32_t value = 0; - uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - - /*Disable truncation*/ - value = dm_read_reg(opp110->base.ctx, addr); - set_reg_field_value(value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN); - set_reg_field_value(value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH); - set_reg_field_value(value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE); - - dm_write_reg(opp110->base.ctx, addr, value); - - /* no 10bpc trunc on DCE11*/ - if (params->flags.TRUNCATE_ENABLED == 0 || - params->flags.TRUNCATE_DEPTH == 2) - return; - - /*Set truncation depth and Enable truncation*/ - set_reg_field_value(value, 1, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN); - set_reg_field_value(value, params->flags.TRUNCATE_MODE, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE); - set_reg_field_value(value, params->flags.TRUNCATE_DEPTH, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH); - - dm_write_reg(opp110->base.ctx, addr, value); - -} - -/** - * set_spatial_dither - * 1) set spatial dithering mode: pattern of seed - * 2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp - * 3) set random seed - * 4) set random mode - * lfsr is reset every frame or not reset - * RGB dithering method - * 0: RGB data are all dithered with x^28+x^3+1 - * 1: R data is dithered with x^28+x^3+1 - * G data is dithered with x^28+X^9+1 - * B data is dithered with x^28+x^13+1 - * enable high pass filter or not - * 5) enable spatical dithering - */ -static void set_spatial_dither( - struct dce110_opp *opp110, - const struct bit_depth_reduction_params *params) -{ - uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - uint32_t depth_cntl_value = 0; - uint32_t fmt_cntl_value = 0; - uint32_t dither_r_value = 0; - uint32_t dither_g_value = 0; - uint32_t dither_b_value = 0; - - /*Disable spatial (random) dithering*/ - depth_cntl_value = dm_read_reg(opp110->base.ctx, addr); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE); - - dm_write_reg(opp110->base.ctx, addr, depth_cntl_value); - - /* no 10bpc on DCE11*/ - if (params->flags.SPATIAL_DITHER_ENABLED == 0 || - params->flags.SPATIAL_DITHER_DEPTH == 2) - return; - - addr = FMT_REG(mmFMT_CONTROL); - fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr); - /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ - if (params->flags.FRAME_RANDOM == 1) { - if (params->flags.SPATIAL_DITHER_DEPTH == 0 || - params->flags.SPATIAL_DITHER_DEPTH == 1) { - set_reg_field_value(fmt_cntl_value, 15, - FMT_CONTROL, - FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX); - set_reg_field_value(fmt_cntl_value, 2, - FMT_CONTROL, - FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP); - } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { - set_reg_field_value(fmt_cntl_value, 3, - FMT_CONTROL, - FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX); - set_reg_field_value(fmt_cntl_value, 1, - FMT_CONTROL, - FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP); - } else - return; - } else { - set_reg_field_value(fmt_cntl_value, 0, - FMT_CONTROL, - FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX); - set_reg_field_value(fmt_cntl_value, 0, - FMT_CONTROL, - FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP); - } - - dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value); - - /*Set seed for random values for - * spatial dithering for R,G,B channels*/ - addr = FMT_REG(mmFMT_DITHER_RAND_R_SEED); - set_reg_field_value(dither_r_value, params->r_seed_value, - FMT_DITHER_RAND_R_SEED, - FMT_RAND_R_SEED); - dm_write_reg(opp110->base.ctx, addr, dither_r_value); - - addr = FMT_REG(mmFMT_DITHER_RAND_G_SEED); - set_reg_field_value(dither_g_value, - params->g_seed_value, - FMT_DITHER_RAND_G_SEED, - FMT_RAND_G_SEED); - dm_write_reg(opp110->base.ctx, addr, dither_g_value); - - addr = FMT_REG(mmFMT_DITHER_RAND_B_SEED); - set_reg_field_value(dither_b_value, params->b_seed_value, - FMT_DITHER_RAND_B_SEED, - FMT_RAND_B_SEED); - dm_write_reg(opp110->base.ctx, addr, dither_b_value); - - /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero - * offset for the R/Cr channel, lower 4LSB - * is forced to zeros. Typically set to 0 - * RGB and 0x80000 YCbCr. - */ - /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero - * offset for the G/Y channel, lower 4LSB is - * forced to zeros. Typically set to 0 RGB - * and 0x80000 YCbCr. - */ - /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero - * offset for the B/Cb channel, lower 4LSB is - * forced to zeros. Typically set to 0 RGB and - * 0x80000 YCbCr. - */ - - /*Set spatial dithering bit depth*/ - set_reg_field_value(depth_cntl_value, - params->flags.SPATIAL_DITHER_DEPTH, - FMT_BIT_DEPTH_CONTROL, - FMT_SPATIAL_DITHER_DEPTH); - - /* Set spatial dithering mode - * (default is Seed patterrn AAAA...) - */ - set_reg_field_value(depth_cntl_value, - params->flags.SPATIAL_DITHER_MODE, - FMT_BIT_DEPTH_CONTROL, - FMT_SPATIAL_DITHER_MODE); - - /*Reset only at startup*/ - set_reg_field_value(depth_cntl_value, - params->flags.FRAME_RANDOM, - FMT_BIT_DEPTH_CONTROL, - FMT_FRAME_RANDOM_ENABLE); - - /*Set RGB data dithered with x^28+x^3+1*/ - set_reg_field_value(depth_cntl_value, - params->flags.RGB_RANDOM, - FMT_BIT_DEPTH_CONTROL, - FMT_RGB_RANDOM_ENABLE); - - /*Disable High pass filter*/ - set_reg_field_value(depth_cntl_value, - params->flags.HIGHPASS_RANDOM, - FMT_BIT_DEPTH_CONTROL, - FMT_HIGHPASS_RANDOM_ENABLE); - - /*Enable spatial dithering*/ - set_reg_field_value(depth_cntl_value, - 1, - FMT_BIT_DEPTH_CONTROL, - FMT_SPATIAL_DITHER_EN); - - addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - dm_write_reg(opp110->base.ctx, addr, depth_cntl_value); - -} - -/** - * SetTemporalDither (Frame Modulation) - * 1) set temporal dither depth - * 2) select pattern: from hard-coded pattern or programmable pattern - * 3) select optimized strips for BGR or RGB LCD sub-pixel - * 4) set s matrix - * 5) set t matrix - * 6) set grey level for 0.25, 0.5, 0.75 - * 7) enable temporal dithering - */ -static void set_temporal_dither( - struct dce110_opp *opp110, - const struct bit_depth_reduction_params *params) -{ - uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - uint32_t value; - - /*Disable temporal (frame modulation) dithering first*/ - value = dm_read_reg(opp110->base.ctx, addr); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_EN); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_RESET); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_OFFSET); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_DEPTH); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_LEVEL); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_25FRC_SEL); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_50FRC_SEL); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_75FRC_SEL); - - dm_write_reg(opp110->base.ctx, addr, value); - - /* no 10bpc dither on DCE11*/ - if (params->flags.FRAME_MODULATION_ENABLED == 0 || - params->flags.FRAME_MODULATION_DEPTH == 2) - return; - - /* Set temporal dithering depth*/ - set_reg_field_value(value, - params->flags.FRAME_MODULATION_DEPTH, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_DEPTH); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_RESET); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_OFFSET); - - /*Select legacy pattern based on FRC and Temporal level*/ - addr = FMT_REG(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL); - dm_write_reg(opp110->base.ctx, addr, 0); - /*Set s matrix*/ - addr = FMT_REG( - mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX); - dm_write_reg(opp110->base.ctx, addr, 0); - /*Set t matrix*/ - addr = FMT_REG( - mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX); - dm_write_reg(opp110->base.ctx, addr, 0); - - /*Select patterns for 0.25, 0.5 and 0.75 grey level*/ - set_reg_field_value(value, - params->flags.TEMPORAL_LEVEL, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_LEVEL); - - set_reg_field_value(value, - params->flags.FRC25, - FMT_BIT_DEPTH_CONTROL, - FMT_25FRC_SEL); - - set_reg_field_value(value, - params->flags.FRC50, - FMT_BIT_DEPTH_CONTROL, - FMT_50FRC_SEL); - - set_reg_field_value(value, - params->flags.FRC75, - FMT_BIT_DEPTH_CONTROL, - FMT_75FRC_SEL); - - /*Enable bit reduction by temporal (frame modulation) dithering*/ - set_reg_field_value(value, - 1, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_EN); - - addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - dm_write_reg(opp110->base.ctx, addr, value); - -} - -/** - * Set Clamping - * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) - * 1 for 8 bpc - * 2 for 10 bpc - * 3 for 12 bpc - * 7 for programable - * 2) Enable clamp if Limited range requested - */ -void dce110_opp_set_clamping( - struct dce110_opp *opp110, - const struct clamping_and_pixel_encoding_params *params) -{ - uint32_t clamp_cntl_value = 0; - uint32_t red_clamp_value = 0; - uint32_t green_clamp_value = 0; - uint32_t blue_clamp_value = 0; - uint32_t addr = FMT_REG(mmFMT_CLAMP_CNTL); - - clamp_cntl_value = dm_read_reg(opp110->base.ctx, addr); - - set_reg_field_value(clamp_cntl_value, - 0, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 0, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - switch (params->clamping_level) { - case CLAMPING_FULL_RANGE: - break; - - case CLAMPING_LIMITED_RANGE_8BPC: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - break; - - case CLAMPING_LIMITED_RANGE_10BPC: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 2, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - break; - case CLAMPING_LIMITED_RANGE_12BPC: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 3, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - break; - case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 7, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - /*set the defaults*/ - set_reg_field_value(red_clamp_value, - 0x10, - FMT_CLAMP_COMPONENT_R, - FMT_CLAMP_LOWER_R); - - set_reg_field_value(red_clamp_value, - 0xFEF, - FMT_CLAMP_COMPONENT_R, - FMT_CLAMP_UPPER_R); - - addr = FMT_REG(mmFMT_CLAMP_COMPONENT_R); - dm_write_reg(opp110->base.ctx, addr, red_clamp_value); - - set_reg_field_value(green_clamp_value, - 0x10, - FMT_CLAMP_COMPONENT_G, - FMT_CLAMP_LOWER_G); - - set_reg_field_value(green_clamp_value, - 0xFEF, - FMT_CLAMP_COMPONENT_G, - FMT_CLAMP_UPPER_G); - - addr = FMT_REG(mmFMT_CLAMP_COMPONENT_G); - dm_write_reg(opp110->base.ctx, addr, green_clamp_value); - - set_reg_field_value(blue_clamp_value, - 0x10, - FMT_CLAMP_COMPONENT_B, - FMT_CLAMP_LOWER_B); - - set_reg_field_value(blue_clamp_value, - 0xFEF, - FMT_CLAMP_COMPONENT_B, - FMT_CLAMP_UPPER_B); - - addr = FMT_REG(mmFMT_CLAMP_COMPONENT_B); - dm_write_reg(opp110->base.ctx, addr, blue_clamp_value); - - break; - - default: - break; - } - - addr = FMT_REG(mmFMT_CLAMP_CNTL); - /*Set clamp control*/ - dm_write_reg(opp110->base.ctx, addr, clamp_cntl_value); - -} - -/** - * set_pixel_encoding - * - * Set Pixel Encoding - * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly - * 1: YCbCr 4:2:2 - */ -static void set_pixel_encoding( - struct dce110_opp *opp110, - const struct clamping_and_pixel_encoding_params *params) -{ - uint32_t fmt_cntl_value; - uint32_t addr = FMT_REG(mmFMT_CONTROL); - - /*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/ - fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr); - - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - set_reg_field_value(fmt_cntl_value, - 1, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - /*00 - Pixels drop mode ,01 - Pixels average mode*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_SUBSAMPLING_MODE); - - /*00 - Cb before Cr ,01 - Cr before Cb*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_SUBSAMPLING_ORDER); - } - dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value); - -} - -void dce110_opp_program_bit_depth_reduction( - struct output_pixel_processor *opp, - const struct bit_depth_reduction_params *params) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - set_truncation(opp110, params); - set_spatial_dither(opp110, params); - set_temporal_dither(opp110, params); -} - -void dce110_opp_program_clamping_and_pixel_encoding( - struct output_pixel_processor *opp, - const struct clamping_and_pixel_encoding_params *params) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - dce110_opp_set_clamping(opp110, params); - set_pixel_encoding(opp110, params); -} - -void dce110_opp_set_dyn_expansion( - struct output_pixel_processor *opp, - enum dc_color_space color_sp, - enum dc_color_depth color_dpth, - enum signal_type signal) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - uint32_t value; - bool enable_dyn_exp = false; - uint32_t addr = FMT_REG(mmFMT_DYNAMIC_EXP_CNTL); - - value = dm_read_reg(opp->ctx, addr); - - set_reg_field_value(value, 0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); - set_reg_field_value(value, 0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); - - /* From HW programming guide: - FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output - FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/ - if (color_sp == COLOR_SPACE_SRGB) - enable_dyn_exp = true; - - /*00 - 10-bit -> 12-bit dynamic expansion*/ - /*01 - 8-bit -> 12-bit dynamic expansion*/ - if (signal == SIGNAL_TYPE_HDMI_TYPE_A) { - switch (color_dpth) { - case COLOR_DEPTH_888: - set_reg_field_value(value, enable_dyn_exp ? 1:0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); - set_reg_field_value(value, 1, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); - break; - case COLOR_DEPTH_101010: - set_reg_field_value(value, enable_dyn_exp ? 1:0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); - set_reg_field_value(value, 0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); - break; - case COLOR_DEPTH_121212: - break; - default: - break; - } - } - - dm_write_reg(opp->ctx, addr, value); -} - -void dce110_opp_program_fmt( - struct output_pixel_processor *opp, - struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping) -{ - /* dithering is affected by , hence should be - * programmed afterwards */ - dce110_opp_program_bit_depth_reduction( - opp, - fmt_bit_depth); - - dce110_opp_program_clamping_and_pixel_encoding( - opp, - clamping); - - return; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c deleted file mode 100644 index 62051abcfe2f..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -/* include DCE11 register header files */ -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "dce110_opp.h" -#include "gamma_types.h" - -#define DCP_REG(reg)\ - (reg + opp110->offsets.dcp_offset) - -#define DCFE_REG(reg)\ - (reg + opp110->offsets.dcfe_offset) - -enum { - MAX_PWL_ENTRY = 128, - MAX_REGIONS_NUMBER = 16 - -}; - -/* - ***************************************************************************** - * Function: regamma_config_regions_and_segments - * - * build regamma curve by using predefined hw points - * uses interface parameters ,like EDID coeff. - * - * @param : parameters interface parameters - * @return void - * - * @note - * - * @see - * - ***************************************************************************** - */ -static void regamma_config_regions_and_segments( - struct dce110_opp *opp110, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - uint32_t value = 0; - - { - set_reg_field_value( - value, - params->arr_points[0].custom_float_x, - REGAMMA_CNTLA_START_CNTL, - REGAMMA_CNTLA_EXP_REGION_START); - - set_reg_field_value( - value, - 0, - REGAMMA_CNTLA_START_CNTL, - REGAMMA_CNTLA_EXP_REGION_START_SEGMENT); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_START_CNTL), - value); - } - { - value = 0; - set_reg_field_value( - value, - params->arr_points[0].custom_float_slope, - REGAMMA_CNTLA_SLOPE_CNTL, - REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_SLOPE_CNTL), value); - } - { - value = 0; - set_reg_field_value( - value, - params->arr_points[1].custom_float_x, - REGAMMA_CNTLA_END_CNTL1, - REGAMMA_CNTLA_EXP_REGION_END); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_END_CNTL1), value); - } - { - value = 0; - set_reg_field_value( - value, - params->arr_points[2].custom_float_slope, - REGAMMA_CNTLA_END_CNTL2, - REGAMMA_CNTLA_EXP_REGION_END_BASE); - - set_reg_field_value( - value, - params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_END_CNTL2, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value); - } - - curve = params->arr_curve_points; - - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS); - - dm_write_reg( - opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_0_1), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_2_3), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_4_5), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_6_7), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_8_9), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_10_11), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_12_13), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_14_15), - value); - } -} - -static void program_pwl( - struct dce110_opp *opp110, - const struct pwl_params *params) -{ - uint32_t value; - - { - uint8_t max_tries = 10; - uint8_t counter = 0; - - /* Power on LUT memory */ - value = dm_read_reg(opp110->base.ctx, - DCFE_REG(mmDCFE_MEM_PWR_CTRL)); - - set_reg_field_value( - value, - 1, - DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS); - - dm_write_reg(opp110->base.ctx, - DCFE_REG(mmDCFE_MEM_PWR_CTRL), value); - - while (counter < max_tries) { - value = - dm_read_reg( - opp110->base.ctx, - DCFE_REG(mmDCFE_MEM_PWR_STATUS)); - - if (get_reg_field_value( - value, - DCFE_MEM_PWR_STATUS, - DCP_REGAMMA_MEM_PWR_STATE) == 0) - break; - - ++counter; - } - - if (counter == max_tries) { - dm_logger_write(opp110->base.ctx->logger, LOG_WARNING, - "%s: regamma lut was not powered on " - "in a timely manner," - " programming still proceeds\n", - __func__); - } - } - - value = 0; - - set_reg_field_value( - value, - 7, - REGAMMA_LUT_WRITE_EN_MASK, - REGAMMA_LUT_WRITE_EN_MASK); - - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_LUT_WRITE_EN_MASK), value); - dm_write_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_LUT_INDEX), 0); - - /* Program REGAMMA_LUT_DATA */ - { - const uint32_t addr = DCP_REG(mmREGAMMA_LUT_DATA); - - uint32_t i = 0; - - const struct pwl_result_data *rgb = params->rgb_resulted; - - while (i != params->hw_points_num) { - dm_write_reg(opp110->base.ctx, addr, rgb->red_reg); - dm_write_reg(opp110->base.ctx, addr, rgb->green_reg); - dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg); - - dm_write_reg(opp110->base.ctx, addr, - rgb->delta_red_reg); - dm_write_reg(opp110->base.ctx, addr, - rgb->delta_green_reg); - dm_write_reg(opp110->base.ctx, addr, - rgb->delta_blue_reg); - - ++rgb; - ++i; - } - } - - /* we are done with DCP LUT memory; re-enable low power mode */ - value = dm_read_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL)); - - set_reg_field_value( - value, - 0, - DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS); - - dm_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value); -} - -bool dce110_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *params) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - /* Setup regions */ - regamma_config_regions_and_segments(opp110, params); - - /* Program PWL */ - program_pwl(opp110, params); - - return true; -} - -void dce110_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - uint32_t value = - dm_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL)); - - set_reg_field_value( - value, - power_on, - DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS); - - set_reg_field_value( - value, - power_on, - DCFE_MEM_PWR_CTRL, - DCP_LUT_MEM_PWR_DIS); - - dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value); -} - -void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - uint32_t value = dm_read_reg(opp110->base.ctx, - DCP_REG(mmREGAMMA_CONTROL)); - - set_reg_field_value( - value, - mode, - REGAMMA_CONTROL, - GRPH_REGAMMA_MODE); - - dm_write_reg(opp110->base.ctx, DCP_REG(mmREGAMMA_CONTROL), - value); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index 3b3a9175b2c3..81fcbc52e4ab 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -29,7 +29,7 @@ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" -#include "dce110_opp.h" +#include "dce/dce_opp.h" #include "gamma_types.h" static void power_on_lut(struct output_pixel_processor *opp, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 4b32397529ec..dfd63a71d214 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -29,7 +29,7 @@ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" -#include "dce110_opp.h" +#include "dce/dce_opp.h" #include "dce110_opp_v.h" #include "gamma_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index fa601f7f0b5a..d4e1ca933b40 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -43,7 +43,7 @@ #include "dce110/dce110_ipp.h" #include "dce/dce_transform.h" #include "dce110/dce110_transform_v.h" -#include "dce110/dce110_opp.h" +#include "dce/dce_opp.h" #include "dce110/dce110_opp_v.h" #include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" @@ -283,6 +283,28 @@ static const struct dce_stream_encoder_mask se_mask = { SE_COMMON_MASK_SH_LIST_DCE110(_MASK) }; +#define opp_regs(id)\ +[id] = {\ + OPP_DCE_110_REG_LIST(id),\ +} + +static const struct dce_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3), + opp_regs(4), + opp_regs(5) +}; + +static const struct dce_opp_shift opp_shift = { + OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) +}; + +static const struct dce_opp_mask opp_mask = { + OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) +}; + #define audio_regs(id)\ [id] = {\ AUD_COMMON_REG_LIST(id)\ @@ -307,34 +329,7 @@ static const struct dce_aduio_mask audio_mask = { }; /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ -static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = { -{ - .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -} -}; + #define clk_src_regs(id)\ [id] = {\ @@ -603,8 +598,7 @@ struct link_encoder *dce110_link_encoder_create( static struct output_pixel_processor *dce110_opp_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offsets) + uint32_t inst) { struct dce110_opp *opp = dm_alloc(sizeof(struct dce110_opp)); @@ -613,7 +607,7 @@ static struct output_pixel_processor *dce110_opp_create( return NULL; if (dce110_opp_construct(opp, - ctx, inst, offsets)) + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) return &opp->base; BREAK_TO_DEBUGGER(); @@ -1329,7 +1323,7 @@ static bool construct( goto res_create_fail; } - pool->base.opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]); + pool->base.opps[i] = dce110_opp_create(ctx, i); if (pool->base.opps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile index 34fba0730bed..2d536fbc60c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile @@ -3,8 +3,7 @@ # It provides the control and status of HW CRTC block. DCE112 = dce112_compressor.o dce112_hw_sequencer.o \ -dce112_resource.o dce112_mem_input.o dce112_opp_formatter.o \ -dce112_opp.o +dce112_resource.o dce112_mem_input.o AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112)) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c deleted file mode 100644 index 23c2d1086b3b..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -/* include DCE11 register header files */ -#include "dce/dce_11_2_d.h" -#include "dce/dce_11_2_sh_mask.h" - -#include "dce112_opp.h" - -#include "gamma_types.h" - -enum { - MAX_LUT_ENTRY = 256, - MAX_NUMBER_OF_ENTRIES = 256 -}; - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -static struct opp_funcs funcs = { - .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, - .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, - .opp_set_csc_default = dce110_opp_set_csc_default, - .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, - .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, - .opp_set_regamma_mode = dce110_opp_set_regamma_mode, - .opp_destroy = dce110_opp_destroy, - .opp_program_fmt = dce112_opp_program_fmt, - .opp_program_bit_depth_reduction = - dce110_opp_program_bit_depth_reduction -}; - -bool dce112_opp_construct(struct dce110_opp *opp110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offsets) -{ - opp110->base.funcs = &funcs; - - opp110->base.ctx = ctx; - - opp110->base.inst = inst; - - opp110->offsets = *offsets; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h deleted file mode 100644 index 9443b87776c6..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_OPP_DCE112_H__ -#define __DC_OPP_DCE112_H__ - -#include "dc_types.h" -#include "opp.h" -#include "../dce110/dce110_opp.h" -#include "core_types.h" - -void dce112_opp_program_clamping_and_pixel_encoding( - struct output_pixel_processor *opp, - const struct clamping_and_pixel_encoding_params *params); - -void dce112_opp_program_fmt( - struct output_pixel_processor *opp, - struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping); - -bool dce112_opp_construct(struct dce110_opp *opp110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offsets); - - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c deleted file mode 100644 index 2d9072138834..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "dce/dce_11_2_d.h" -#include "dce/dce_11_2_sh_mask.h" - -#include "dce112_opp.h" - -#define FMT_REG(reg)\ - (reg + opp110->offsets.fmt_offset) -#define FMT_MEM_REG(reg)\ - (reg + opp110->offsets.fmt_mem_offset) - -/** - * Set Clamping - * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) - * 1 for 8 bpc - * 2 for 10 bpc - * 3 for 12 bpc - * 7 for programable - * 2) Enable clamp if Limited range requested - */ - -/** - * set_pixel_encoding - * - * Set Pixel Encoding - * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly - * 1: YCbCr 4:2:2 - * 2: YCbCr 4:2:0 - */ -static void set_pixel_encoding( - struct dce110_opp *opp110, - const struct clamping_and_pixel_encoding_params *params) -{ - uint32_t fmt_cntl_value; - uint32_t addr = FMT_REG(mmFMT_CONTROL); - - /*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/ - fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr); - - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - /*00 - Pixels drop mode HW default*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_SUBSAMPLING_MODE); - - /* By default no bypass*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_CBCR_BIT_REDUCTION_BYPASS); - - if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - set_reg_field_value(fmt_cntl_value, - 1, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - /*00 - Cb before Cr ,01 - Cr before Cb*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_SUBSAMPLING_ORDER); - } - - if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) { - set_reg_field_value(fmt_cntl_value, - 2, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - /* 02 - Subsampling mode, 3 taps*/ - set_reg_field_value(fmt_cntl_value, - 2, - FMT_CONTROL, - FMT_SUBSAMPLING_MODE); - - /* 00 - Enable CbCr bit reduction bypass to preserve precision*/ - set_reg_field_value(fmt_cntl_value, - 1, - FMT_CONTROL, - FMT_CBCR_BIT_REDUCTION_BYPASS); - } - dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value); - -} - -void dce112_opp_program_clamping_and_pixel_encoding( - struct output_pixel_processor *opp, - const struct clamping_and_pixel_encoding_params *params) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - dce110_opp_set_clamping(opp110, params); - set_pixel_encoding(opp110, params); -} - -static void program_formatter_420_memory(struct output_pixel_processor *opp) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - uint32_t fmt_cntl_value; - uint32_t fmt_mem_cntl_value; - uint32_t fmt_cntl_addr = FMT_REG(mmFMT_CONTROL); - uint32_t fmt_mem_cntl_addr = FMT_MEM_REG(mmFMT_MEMORY0_CONTROL); - - fmt_mem_cntl_value = dm_read_reg(opp110->base.ctx, fmt_mem_cntl_addr); - fmt_cntl_value = dm_read_reg(opp110->base.ctx, fmt_cntl_addr); - /* Program source select*/ - /* Use HW default source select for FMT_MEMORYx_CONTROL */ - /* Use that value for FMT_SRC_SELECT as well*/ - set_reg_field_value(fmt_cntl_value, - get_reg_field_value(fmt_mem_cntl_value, FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL), - FMT_CONTROL, - FMT_SRC_SELECT); - dm_write_reg(opp110->base.ctx, fmt_cntl_addr, fmt_cntl_value); - - /* Turn on the memory */ - set_reg_field_value(fmt_mem_cntl_value, - 0, - FMT_MEMORY0_CONTROL, - FMT420_MEM0_PWR_FORCE); - dm_write_reg(opp110->base.ctx, fmt_mem_cntl_addr, fmt_mem_cntl_value); -} - -static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - uint32_t value; - uint32_t addr = FMT_REG(mmFMT_CONTROL); - uint8_t counter = 10; - - - value = dm_read_reg(opp110->base.ctx, addr); - - /* clear previous phase lock status*/ - set_reg_field_value(value, - 1, - FMT_CONTROL, - FMT_420_PIXEL_PHASE_LOCKED_CLEAR); - dm_write_reg(opp110->base.ctx, addr, value); - - /* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/ - while (counter > 0) { - value = dm_read_reg(opp110->base.ctx, addr); - - if (get_reg_field_value( - value, - FMT_CONTROL, - FMT_420_PIXEL_PHASE_LOCKED) == 1) - break; - - msleep(10); - counter--; - } - - if (counter == 0) - dm_logger_write(opp->ctx->logger, LOG_ERROR, - "%s:opp program formattter reset dig resync info time out.\n", - __func__); -} - -void dce112_opp_program_fmt( - struct output_pixel_processor *opp, - struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping) -{ - /* dithering is affected by , hence should be - * programmed afterwards */ - - if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420) - program_formatter_420_memory(opp); - - dce110_opp_program_bit_depth_reduction( - opp, - fmt_bit_depth); - - dce112_opp_program_clamping_and_pixel_encoding( - opp, - clamping); - - if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420) - program_formatter_reset_dig_resync_fifo(opp); - - return; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 85d8b31acd02..2711893b71e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -39,7 +39,7 @@ #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" #include "dce/dce_audio.h" -#include "dce112/dce112_opp.h" +#include "dce/dce_opp.h" #include "dce110/dce110_ipp.h" #include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" @@ -306,6 +306,28 @@ static const struct dce_stream_encoder_mask se_mask = { SE_COMMON_MASK_SH_LIST_DCE112(_MASK) }; +#define opp_regs(id)\ +[id] = {\ + OPP_DCE_112_REG_LIST(id),\ +} + +static const struct dce_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3), + opp_regs(4), + opp_regs(5) +}; + +static const struct dce_opp_shift opp_shift = { + OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) +}; + +static const struct dce_opp_mask opp_mask = { + OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) +}; + #define audio_regs(id)\ [id] = {\ AUD_COMMON_REG_LIST(id)\ @@ -328,42 +350,6 @@ static const struct dce_aduio_mask audio_mask = { AUD_COMMON_MASK_SH_LIST(_MASK) }; - -static const struct dce110_opp_reg_offsets dce112_opp_reg_offsets[] = { -{ - .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .fmt_mem_offset = (mmFMT_MEMORY0_CONTROL - mmFMT_MEMORY0_CONTROL), - .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .fmt_mem_offset = (mmFMT_MEMORY1_CONTROL - mmFMT_MEMORY0_CONTROL), - .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .fmt_mem_offset = (mmFMT_MEMORY2_CONTROL - mmFMT_MEMORY0_CONTROL), - .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .fmt_mem_offset = (mmFMT_MEMORY3_CONTROL - mmFMT_MEMORY0_CONTROL), - .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .fmt_mem_offset = (mmFMT_MEMORY4_CONTROL - mmFMT_MEMORY0_CONTROL), - .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .fmt_mem_offset = (mmFMT_MEMORY5_CONTROL - mmFMT_MEMORY0_CONTROL), - .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -} -}; - #define clk_src_regs(index, id)\ [index] = {\ CS_COMMON_REG_LIST_DCE_112(id),\ @@ -631,8 +617,7 @@ void dce112_ipp_destroy(struct input_pixel_processor **ipp) struct output_pixel_processor *dce112_opp_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_opp_reg_offsets *offset) + uint32_t inst) { struct dce110_opp *opp = dm_alloc(sizeof(struct dce110_opp)); @@ -640,8 +625,8 @@ struct output_pixel_processor *dce112_opp_create( if (!opp) return NULL; - if (dce112_opp_construct(opp, - ctx, inst, offset)) + if (dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) return &opp->base; BREAK_TO_DEBUGGER(); @@ -1381,8 +1366,7 @@ static bool construct( pool->base.opps[i] = dce112_opp_create( ctx, - i, - &dce112_opp_reg_offsets[i]); + i); if (pool->base.opps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index 9979b8441a8d..0261d1bfccb5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -2,9 +2,8 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. -DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_opp.o \ - dce80_opp_formatter.o dce80_opp_regamma.o \ - dce80_timing_generator.o dce80_opp_csc.o\ +DCE80 = dce80_ipp.o dce80_ipp_gamma.o \ + dce80_timing_generator.o \ dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \ dce80_resource.o diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c deleted file mode 100644 index b69e8a5d844d..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -/* include DCE8 register header files */ -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "dce80_opp.h" - -#define FROM_OPP(opp)\ - container_of(opp, struct dce80_opp, base) - -enum { - MAX_LUT_ENTRY = 256, - MAX_NUMBER_OF_ENTRIES = 256 -}; - -static const struct dce80_opp_reg_offsets reg_offsets[] = { -{ - .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .crtc_offset = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), - .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .crtc_offset = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), - .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .crtc_offset = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), - .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .crtc_offset = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), - .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .crtc_offset = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), - .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .crtc_offset = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), - .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -} -}; - -static const struct opp_funcs funcs = { - .opp_power_on_regamma_lut = dce80_opp_power_on_regamma_lut, - .opp_set_csc_adjustment = dce80_opp_set_csc_adjustment, - .opp_set_csc_default = dce80_opp_set_csc_default, - .opp_set_dyn_expansion = dce80_opp_set_dyn_expansion, - .opp_program_regamma_pwl = dce80_opp_program_regamma_pwl, - .opp_set_regamma_mode = dce80_opp_set_regamma_mode, - .opp_destroy = dce80_opp_destroy, - .opp_program_fmt = dce110_opp_program_fmt, -}; - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -bool dce80_opp_construct(struct dce80_opp *opp80, - struct dc_context *ctx, - uint32_t inst) -{ - if (inst >= ARRAY_SIZE(reg_offsets)) - return false; - - opp80->base.funcs = &funcs; - - opp80->base.ctx = ctx; - - opp80->base.inst = inst; - - opp80->offsets = reg_offsets[inst]; - - return true; -} - -void dce80_opp_destroy(struct output_pixel_processor **opp) -{ - dm_free(FROM_OPP(*opp)); - *opp = NULL; -} - -struct output_pixel_processor *dce80_opp_create( - struct dc_context *ctx, - uint32_t inst) -{ - struct dce80_opp *opp = - dm_alloc(sizeof(struct dce80_opp)); - - if (!opp) - return NULL; - - if (dce80_opp_construct(opp, - ctx, inst)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - dm_free(opp); - return NULL; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.h deleted file mode 100644 index 965cce37f7e3..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.h +++ /dev/null @@ -1,130 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_OPP_DCE80_H__ -#define __DC_OPP_DCE80_H__ - -#include "dc_types.h" -#include "opp.h" -#include "gamma_types.h" -#include "../dce110/dce110_opp.h" - -struct gamma_parameters; - -struct dce80_regamma { - struct gamma_curve arr_curve_points[16]; - struct curve_points arr_points[3]; - uint32_t hw_points_num; - struct hw_x_point *coordinates_x; - struct pwl_result_data *rgb_resulted; - - /* re-gamma curve */ - struct pwl_float_data_ex *rgb_regamma; - /* coeff used to map user evenly distributed points - * to our hardware points (predefined) for gamma 256 */ - struct pixel_gamma_point *coeff128; - struct pixel_gamma_point *coeff128_oem; - /* coeff used to map user evenly distributed points - * to our hardware points (predefined) for gamma 1025 */ - struct pixel_gamma_point *coeff128_dx; - /* evenly distributed points, gamma 256 software points 0-255 */ - struct gamma_pixel *axis_x_256; - /* evenly distributed points, gamma 1025 software points 0-1025 */ - struct gamma_pixel *axis_x_1025; - /* OEM supplied gamma for regamma LUT */ - struct pwl_float_data *rgb_oem; - /* user supplied gamma */ - struct pwl_float_data *rgb_user; - uint32_t extra_points; - bool use_half_points; - struct fixed31_32 x_max1; - struct fixed31_32 x_max2; - struct fixed31_32 x_min; - struct fixed31_32 divider1; - struct fixed31_32 divider2; - struct fixed31_32 divider3; -}; - -/* OPP RELATED */ -#define TO_DCE80_OPP(opp)\ - container_of(opp, struct dce80_opp, base) - -struct dce80_opp_reg_offsets { - uint32_t fmt_offset; - uint32_t dcp_offset; - uint32_t crtc_offset; -}; - -struct dce80_opp { - struct output_pixel_processor base; - struct dce80_opp_reg_offsets offsets; - struct dce80_regamma regamma; -}; - -bool dce80_opp_construct(struct dce80_opp *opp80, - struct dc_context *ctx, - uint32_t inst); - -void dce80_opp_destroy(struct output_pixel_processor **opp); - -struct output_pixel_processor *dce80_opp_create( - struct dc_context *ctx, - uint32_t inst); - -/* REGAMMA RELATED */ -void dce80_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on); - -bool dce80_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *pamras); - -void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode); - -void dce80_opp_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry); - -void dce80_opp_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust); - -/* FORMATTER RELATED */ -void dce80_opp_program_bit_depth_reduction( - struct output_pixel_processor *opp, - const struct bit_depth_reduction_params *params); - -void dce80_opp_program_clamping_and_pixel_encoding( - struct output_pixel_processor *opp, - const struct clamping_and_pixel_encoding_params *params); - -void dce80_opp_set_dyn_expansion( - struct output_pixel_processor *opp, - enum dc_color_space color_sp, - enum dc_color_depth color_dpth, - enum signal_type signal); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_csc.c deleted file mode 100644 index bdb9e0a77982..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_csc.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "dce80_opp.h" -#include "basics/conversion.h" - -/* include DCE8 register header files */ -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#define DCP_REG(reg)\ - (reg + opp80->offsets.dcp_offset) - -enum { - OUTPUT_CSC_MATRIX_SIZE = 12 -}; - -static const struct out_csc_color_matrix global_color_matrix[] = { -{ COLOR_SPACE_SRGB, - { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, -{ COLOR_SPACE_SRGB_LIMITED, - { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, -{ COLOR_SPACE_YCBCR601, - { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, - 0xF6B9, 0xE00, 0x1000} }, -{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, - 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, -/* TODO: correct values below */ -{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, - 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, -{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, - 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } -}; - -enum csc_color_mode { - /* 00 - BITS2:0 Bypass */ - CSC_COLOR_MODE_GRAPHICS_BYPASS, - /* 01 - hard coded coefficient TV RGB */ - CSC_COLOR_MODE_GRAPHICS_PREDEFINED, - /* 04 - programmable OUTPUT CSC coefficient */ - CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, -}; - -static void program_color_matrix( - struct dce80_opp *opp80, - const struct out_csc_color_matrix *tbl_entry, - enum grph_color_adjust_option options) -{ - struct dc_context *ctx = opp80->base.ctx; - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[0], - OUTPUT_CSC_C11_C12, - OUTPUT_CSC_C11); - - set_reg_field_value( - value, - tbl_entry->regval[1], - OUTPUT_CSC_C11_C12, - OUTPUT_CSC_C12); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[2], - OUTPUT_CSC_C13_C14, - OUTPUT_CSC_C13); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[3], - OUTPUT_CSC_C13_C14, - OUTPUT_CSC_C14); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[4], - OUTPUT_CSC_C21_C22, - OUTPUT_CSC_C21); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[5], - OUTPUT_CSC_C21_C22, - OUTPUT_CSC_C22); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[6], - OUTPUT_CSC_C23_C24, - OUTPUT_CSC_C23); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[7], - OUTPUT_CSC_C23_C24, - OUTPUT_CSC_C24); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[8], - OUTPUT_CSC_C31_C32, - OUTPUT_CSC_C31); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[9], - OUTPUT_CSC_C31_C32, - OUTPUT_CSC_C32); - - dm_write_reg(ctx, addr, value); - } - { - uint32_t value = 0; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34); - /* fixed S2.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[10], - OUTPUT_CSC_C33_C34, - OUTPUT_CSC_C33); - /* fixed S0.13 format */ - set_reg_field_value( - value, - tbl_entry->regval[11], - OUTPUT_CSC_C33_C34, - OUTPUT_CSC_C34); - - dm_write_reg(ctx, addr, value); - } -} - -static bool configure_graphics_mode( - struct dce80_opp *opp80, - enum csc_color_mode config, - enum graphics_csc_adjust_type csc_adjust_type, - enum dc_color_space color_space) -{ - struct dc_context *ctx = opp80->base.ctx; - uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL); - uint32_t value = dm_read_reg(ctx, addr); - - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - - if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { - if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { - set_reg_field_value( - value, - 4, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - } else { - - switch (color_space) { - case COLOR_SPACE_SRGB: - /* by pass */ - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_SRGB_LIMITED: - /* TV RGB */ - set_reg_field_value( - value, - 1, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: - case COLOR_SPACE_YCBCR601_LIMITED: - /* YCbCr601 */ - set_reg_field_value( - value, - 2, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: - case COLOR_SPACE_YCBCR709_LIMITED: - /* YCbCr709 */ - set_reg_field_value( - value, - 3, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - default: - return false; - } - } - } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { - switch (color_space) { - case COLOR_SPACE_SRGB: - /* by pass */ - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_SRGB_LIMITED: - /* TV RGB */ - set_reg_field_value( - value, - 1, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: - case COLOR_SPACE_YCBCR601_LIMITED: - /* YCbCr601 */ - set_reg_field_value( - value, - 2, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: - case COLOR_SPACE_YCBCR709_LIMITED: - /* YCbCr709 */ - set_reg_field_value( - value, - 3, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - break; - default: - return false; - } - - } else - /* by pass */ - set_reg_field_value( - value, - 0, - OUTPUT_CSC_CONTROL, - OUTPUT_CSC_GRPH_MODE); - - addr = DCP_REG(mmOUTPUT_CSC_CONTROL); - dm_write_reg(ctx, addr, value); - - return true; -} - -void dce80_opp_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - enum csc_color_mode config = - CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - - program_color_matrix(opp80, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); - - /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ - configure_graphics_mode(opp80, config, GRAPHICS_CSC_ADJUST_TYPE_SW, - tbl_entry->color_space); -} - -void dce80_opp_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - enum csc_color_mode config = - CSC_COLOR_MODE_GRAPHICS_PREDEFINED; - - if (default_adjust->force_hw_default == false) { - const struct out_csc_color_matrix *elm; - /* currently parameter not in use */ - enum grph_color_adjust_option option = - GRPH_COLOR_MATRIX_HW_DEFAULT; - uint32_t i; - /* - * HW default false we program locally defined matrix - * HW default true we use predefined hw matrix and we - * do not need to program matrix - * OEM wants the HW default via runtime parameter. - */ - option = GRPH_COLOR_MATRIX_SW; - - for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { - elm = &global_color_matrix[i]; - if (elm->color_space != default_adjust->out_color_space) - continue; - /* program the matrix with default values from this - * file */ - program_color_matrix(opp80, elm, option); - config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - break; - } - } - - /* configure the what we programmed : - * 1. Default values from this file - * 2. Use hardware default from ROM_A and we do not need to program - * matrix */ - - configure_graphics_mode(opp80, config, - default_adjust->csc_adjust_type, - default_adjust->out_color_space); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_formatter.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_formatter.c deleted file mode 100644 index 433296a4ed12..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_formatter.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "dce80_opp.h" - -#define FMT_REG(reg)\ - (reg + opp80->offsets.fmt_offset) - -/** - * set_truncation - * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp - * 2) enable truncation - * 3) HW remove 12bit FMT support for DCE8 power saving reason. - */ -static void set_truncation( - struct dce80_opp *opp80, - const struct bit_depth_reduction_params *params) -{ - uint32_t value = 0; - uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - - /*Disable truncation*/ - value = dm_read_reg(opp80->base.ctx, addr); - set_reg_field_value(value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN); - set_reg_field_value(value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH); - set_reg_field_value(value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE); - - dm_write_reg(opp80->base.ctx, addr, value); - - /* no 10bpc trunc on DCE8*/ - if (params->flags.TRUNCATE_ENABLED == 0 || - params->flags.TRUNCATE_DEPTH == 2) - return; - - /*Set truncation depth and Enable truncation*/ - set_reg_field_value(value, 1, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN); - set_reg_field_value(value, params->flags.TRUNCATE_MODE, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE); - set_reg_field_value(value, params->flags.TRUNCATE_DEPTH, - FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH); - - dm_write_reg(opp80->base.ctx, addr, value); - -} - -/** - * set_spatial_dither - * 1) set spatial dithering mode: pattern of seed - * 2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp - * 3) set random seed - * 4) set random mode - * lfsr is reset every frame or not reset - * RGB dithering method - * 0: RGB data are all dithered with x^28+x^3+1 - * 1: R data is dithered with x^28+x^3+1 - * G data is dithered with x^28+X^9+1 - * B data is dithered with x^28+x^13+1 - * enable high pass filter or not - * 5) enable spatical dithering - */ -static void set_spatial_dither( - struct dce80_opp *opp80, - const struct bit_depth_reduction_params *params) -{ - uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - uint32_t depth_cntl_value = 0; - uint32_t dither_r_value = 0; - uint32_t dither_g_value = 0; - uint32_t dither_b_value = 0; - - /*Disable spatial (random) dithering*/ - depth_cntl_value = dm_read_reg(opp80->base.ctx, addr); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE); - set_reg_field_value(depth_cntl_value, 0, - FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE); - - dm_write_reg(opp80->base.ctx, addr, depth_cntl_value); - - /* no 10bpc on DCE8*/ - if (params->flags.SPATIAL_DITHER_ENABLED == 0 || - params->flags.SPATIAL_DITHER_DEPTH == 2) - return; - - /*Set seed for random values for - * spatial dithering for R,G,B channels*/ - addr = FMT_REG(mmFMT_DITHER_RAND_R_SEED); - set_reg_field_value(dither_r_value, params->r_seed_value, - FMT_DITHER_RAND_R_SEED, - FMT_RAND_R_SEED); - dm_write_reg(opp80->base.ctx, addr, dither_r_value); - - addr = FMT_REG(mmFMT_DITHER_RAND_G_SEED); - set_reg_field_value(dither_g_value, - params->g_seed_value, - FMT_DITHER_RAND_G_SEED, - FMT_RAND_G_SEED); - dm_write_reg(opp80->base.ctx, addr, dither_g_value); - - addr = FMT_REG(mmFMT_DITHER_RAND_B_SEED); - set_reg_field_value(dither_b_value, params->b_seed_value, - FMT_DITHER_RAND_B_SEED, - FMT_RAND_B_SEED); - dm_write_reg(opp80->base.ctx, addr, dither_b_value); - - /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero - * offset for the R/Cr channel, lower 4LSB - * is forced to zeros. Typically set to 0 - * RGB and 0x80000 YCbCr. - */ - /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero - * offset for the G/Y channel, lower 4LSB is - * forced to zeros. Typically set to 0 RGB - * and 0x80000 YCbCr. - */ - /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero - * offset for the B/Cb channel, lower 4LSB is - * forced to zeros. Typically set to 0 RGB and - * 0x80000 YCbCr. - */ - - /*Set spatial dithering bit depth*/ - set_reg_field_value(depth_cntl_value, - params->flags.SPATIAL_DITHER_DEPTH, - FMT_BIT_DEPTH_CONTROL, - FMT_SPATIAL_DITHER_DEPTH); - - /* Set spatial dithering mode - * (default is Seed patterrn AAAA...) - */ - set_reg_field_value(depth_cntl_value, - params->flags.SPATIAL_DITHER_MODE, - FMT_BIT_DEPTH_CONTROL, - FMT_SPATIAL_DITHER_MODE); - - /*Reset only at startup*/ - set_reg_field_value(depth_cntl_value, - params->flags.FRAME_RANDOM, - FMT_BIT_DEPTH_CONTROL, - FMT_FRAME_RANDOM_ENABLE); - - /*Set RGB data dithered with x^28+x^3+1*/ - set_reg_field_value(depth_cntl_value, - params->flags.RGB_RANDOM, - FMT_BIT_DEPTH_CONTROL, - FMT_RGB_RANDOM_ENABLE); - - /*Disable High pass filter*/ - set_reg_field_value(depth_cntl_value, - params->flags.HIGHPASS_RANDOM, - FMT_BIT_DEPTH_CONTROL, - FMT_HIGHPASS_RANDOM_ENABLE); - - /*Enable spatial dithering*/ - set_reg_field_value(depth_cntl_value, - 1, - FMT_BIT_DEPTH_CONTROL, - FMT_SPATIAL_DITHER_EN); - - addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - dm_write_reg(opp80->base.ctx, addr, depth_cntl_value); - -} - -/** - * SetTemporalDither (Frame Modulation) - * 1) set temporal dither depth - * 2) select pattern: from hard-coded pattern or programmable pattern - * 3) select optimized strips for BGR or RGB LCD sub-pixel - * 4) set s matrix - * 5) set t matrix - * 6) set grey level for 0.25, 0.5, 0.75 - * 7) enable temporal dithering - */ -static void set_temporal_dither( - struct dce80_opp *opp80, - const struct bit_depth_reduction_params *params) -{ - uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - uint32_t value; - - /*Disable temporal (frame modulation) dithering first*/ - value = dm_read_reg(opp80->base.ctx, addr); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_EN); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_RESET); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_OFFSET); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_DEPTH); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_LEVEL); - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_25FRC_SEL); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_50FRC_SEL); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_75FRC_SEL); - - dm_write_reg(opp80->base.ctx, addr, value); - - /* no 10bpc dither on DCE8*/ - if (params->flags.FRAME_MODULATION_ENABLED == 0 || - params->flags.FRAME_MODULATION_DEPTH == 2) - return; - - /* Set temporal dithering depth*/ - set_reg_field_value(value, - params->flags.FRAME_MODULATION_DEPTH, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_DEPTH); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_RESET); - - set_reg_field_value(value, - 0, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_OFFSET); - - /*Select legacy pattern based on FRC and Temporal level*/ - addr = FMT_REG(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL); - dm_write_reg(opp80->base.ctx, addr, 0); - /*Set s matrix*/ - addr = FMT_REG( - mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX); - dm_write_reg(opp80->base.ctx, addr, 0); - /*Set t matrix*/ - addr = FMT_REG( - mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX); - dm_write_reg(opp80->base.ctx, addr, 0); - - /*Select patterns for 0.25, 0.5 and 0.75 grey level*/ - set_reg_field_value(value, - params->flags.TEMPORAL_LEVEL, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_LEVEL); - - set_reg_field_value(value, - params->flags.FRC25, - FMT_BIT_DEPTH_CONTROL, - FMT_25FRC_SEL); - - set_reg_field_value(value, - params->flags.FRC50, - FMT_BIT_DEPTH_CONTROL, - FMT_50FRC_SEL); - - set_reg_field_value(value, - params->flags.FRC75, - FMT_BIT_DEPTH_CONTROL, - FMT_75FRC_SEL); - - /*Enable bit reduction by temporal (frame modulation) dithering*/ - set_reg_field_value(value, - 1, - FMT_BIT_DEPTH_CONTROL, - FMT_TEMPORAL_DITHER_EN); - - addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL); - dm_write_reg(opp80->base.ctx, addr, value); - -} - -/** - * Set Clamping - * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) - * 1 for 8 bpc - * 2 for 10 bpc - * 3 for 12 bpc - * 7 for programable - * 2) Enable clamp if Limited range requested - */ -static void set_clamping( - struct dce80_opp *opp80, - const struct clamping_and_pixel_encoding_params *params) -{ - uint32_t clamp_cntl_value = 0; - uint32_t red_clamp_value = 0; - uint32_t green_clamp_value = 0; - uint32_t blue_clamp_value = 0; - uint32_t addr = FMT_REG(mmFMT_CLAMP_CNTL); - - clamp_cntl_value = dm_read_reg(opp80->base.ctx, addr); - - set_reg_field_value(clamp_cntl_value, - 0, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 0, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - switch (params->clamping_level) { - case CLAMPING_FULL_RANGE: - break; - - case CLAMPING_LIMITED_RANGE_8BPC: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - break; - - case CLAMPING_LIMITED_RANGE_10BPC: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 2, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - break; - case CLAMPING_LIMITED_RANGE_12BPC: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 3, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - break; - case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: - set_reg_field_value(clamp_cntl_value, - 1, - FMT_CLAMP_CNTL, - FMT_CLAMP_DATA_EN); - - set_reg_field_value(clamp_cntl_value, - 7, - FMT_CLAMP_CNTL, - FMT_CLAMP_COLOR_FORMAT); - - /*set the defaults*/ - set_reg_field_value(red_clamp_value, - 0x10, - FMT_CLAMP_COMPONENT_R, - FMT_CLAMP_LOWER_R); - - set_reg_field_value(red_clamp_value, - 0xFEF, - FMT_CLAMP_COMPONENT_R, - FMT_CLAMP_UPPER_R); - - addr = FMT_REG(mmFMT_CLAMP_COMPONENT_R); - dm_write_reg(opp80->base.ctx, addr, red_clamp_value); - - set_reg_field_value(green_clamp_value, - 0x10, - FMT_CLAMP_COMPONENT_G, - FMT_CLAMP_LOWER_G); - - set_reg_field_value(green_clamp_value, - 0xFEF, - FMT_CLAMP_COMPONENT_G, - FMT_CLAMP_UPPER_G); - - addr = FMT_REG(mmFMT_CLAMP_COMPONENT_G); - dm_write_reg(opp80->base.ctx, addr, green_clamp_value); - - set_reg_field_value(blue_clamp_value, - 0x10, - FMT_CLAMP_COMPONENT_B, - FMT_CLAMP_LOWER_B); - - set_reg_field_value(blue_clamp_value, - 0xFEF, - FMT_CLAMP_COMPONENT_B, - FMT_CLAMP_UPPER_B); - - addr = FMT_REG(mmFMT_CLAMP_COMPONENT_B); - dm_write_reg(opp80->base.ctx, addr, blue_clamp_value); - - break; - - default: - break; - } - - addr = FMT_REG(mmFMT_CLAMP_CNTL); - /*Set clamp control*/ - dm_write_reg(opp80->base.ctx, addr, clamp_cntl_value); - -} - -/** - * set_pixel_encoding - * - * Set Pixel Encoding - * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly - * 1: YCbCr 4:2:2 - */ -static void set_pixel_encoding( - struct dce80_opp *opp80, - const struct clamping_and_pixel_encoding_params *params) -{ - uint32_t fmt_cntl_value; - uint32_t addr = FMT_REG(mmFMT_CONTROL); - - /*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/ - fmt_cntl_value = dm_read_reg(opp80->base.ctx, addr); - - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - set_reg_field_value(fmt_cntl_value, - 1, - FMT_CONTROL, - FMT_PIXEL_ENCODING); - - /*00 - Pixels drop mode ,01 - Pixels average mode*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_SUBSAMPLING_MODE); - - /*00 - Cb before Cr ,01 - Cr before Cb*/ - set_reg_field_value(fmt_cntl_value, - 0, - FMT_CONTROL, - FMT_SUBSAMPLING_ORDER); - } - dm_write_reg(opp80->base.ctx, addr, fmt_cntl_value); - -} - -void dce80_opp_program_bit_depth_reduction( - struct output_pixel_processor *opp, - const struct bit_depth_reduction_params *params) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - - set_truncation(opp80, params); - set_spatial_dither(opp80, params); - set_temporal_dither(opp80, params); -} - -void dce80_opp_program_clamping_and_pixel_encoding( - struct output_pixel_processor *opp, - const struct clamping_and_pixel_encoding_params *params) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - - set_clamping(opp80, params); - set_pixel_encoding(opp80, params); -} - -void dce80_opp_set_dyn_expansion( - struct output_pixel_processor *opp, - enum dc_color_space color_sp, - enum dc_color_depth color_dpth, - enum signal_type signal) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - uint32_t value; - bool enable_dyn_exp = false; - uint32_t addr = FMT_REG(mmFMT_DYNAMIC_EXP_CNTL); - - value = dm_read_reg(opp->ctx, addr); - - set_reg_field_value(value, 0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); - set_reg_field_value(value, 0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); - - /* From HW programming guide: - FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output - FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/ - if (color_sp == COLOR_SPACE_SRGB) - enable_dyn_exp = true; - - /*00 - 10-bit -> 12-bit dynamic expansion*/ - /*01 - 8-bit -> 12-bit dynamic expansion*/ - if (signal == SIGNAL_TYPE_HDMI_TYPE_A) { - switch (color_dpth) { - case COLOR_DEPTH_888: - set_reg_field_value(value, enable_dyn_exp ? 1:0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); - set_reg_field_value(value, 1, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); - break; - case COLOR_DEPTH_101010: - set_reg_field_value(value, enable_dyn_exp ? 1:0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN); - set_reg_field_value(value, 0, - FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE); - break; - case COLOR_DEPTH_121212: - break; - default: - break; - } - } - - dm_write_reg(opp->ctx, addr, value); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_regamma.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_regamma.c deleted file mode 100644 index 648e3ef35d91..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_regamma.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -/* include DCE8 register header files */ -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "dce80_opp.h" -#include "gamma_types.h" - -#define DCP_REG(reg)\ - (reg + opp80->offsets.dcp_offset) - -#define DCFE_REG(reg)\ - (reg + opp80->offsets.crtc_offset) - -enum { - MAX_PWL_ENTRY = 128, - MAX_REGIONS_NUMBER = 16 - -}; - -struct curve_config { - uint32_t offset; - int8_t segments[MAX_REGIONS_NUMBER]; - int8_t begin; -}; - -/* - ***************************************************************************** - * Function: regamma_config_regions_and_segments - * - * build regamma curve by using predefined hw points - * uses interface parameters ,like EDID coeff. - * - * @param : parameters interface parameters - * @return void - * - * @note - * - * @see - * - ***************************************************************************** - */ -static void regamma_config_regions_and_segments( - struct dce80_opp *opp80, const struct pwl_params *params) -{ - const struct gamma_curve *curve; - uint32_t value = 0; - - { - set_reg_field_value( - value, - params->arr_points[0].custom_float_x, - REGAMMA_CNTLA_START_CNTL, - REGAMMA_CNTLA_EXP_REGION_START); - - set_reg_field_value( - value, - 0, - REGAMMA_CNTLA_START_CNTL, - REGAMMA_CNTLA_EXP_REGION_START_SEGMENT); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_START_CNTL), - value); - } - { - value = 0; - set_reg_field_value( - value, - params->arr_points[0].custom_float_slope, - REGAMMA_CNTLA_SLOPE_CNTL, - REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_SLOPE_CNTL), value); - } - { - value = 0; - set_reg_field_value( - value, - params->arr_points[1].custom_float_x, - REGAMMA_CNTLA_END_CNTL1, - REGAMMA_CNTLA_EXP_REGION_END); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_END_CNTL1), value); - } - { - value = 0; - set_reg_field_value( - value, - params->arr_points[2].custom_float_slope, - REGAMMA_CNTLA_END_CNTL2, - REGAMMA_CNTLA_EXP_REGION_END_BASE); - - set_reg_field_value( - value, - params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_END_CNTL2, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value); - } - - curve = params->arr_curve_points; - - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_0_1, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS); - - dm_write_reg( - opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_0_1), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_2_3, - REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_2_3), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_4_5, - REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_4_5), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_6_7, - REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_6_7), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_8_9, - REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_8_9), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_10_11, - REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_10_11), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_12_13, - REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_12_13), - value); - } - - curve += 2; - { - value = 0; - set_reg_field_value( - value, - curve[0].offset, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET); - - set_reg_field_value( - value, - curve[0].segments_num, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS); - - set_reg_field_value( - value, - curve[1].offset, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET); - - set_reg_field_value( - value, - curve[1].segments_num, - REGAMMA_CNTLA_REGION_14_15, - REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CNTLA_REGION_14_15), - value); - } -} - -static void program_pwl( - struct dce80_opp *opp80, - const struct pwl_params *params) -{ - uint32_t value; - - { - uint8_t max_tries = 10; - uint8_t counter = 0; - - /* Power on LUT memory */ - value = dm_read_reg(opp80->base.ctx, - DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL)); - - set_reg_field_value( - value, - 1, - DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS); - - dm_write_reg(opp80->base.ctx, - DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL), value); - - while (counter < max_tries) { - value = - dm_read_reg( - opp80->base.ctx, - DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL)); - - if (get_reg_field_value( - value, - DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_MEM_PWR_STATE) == 0) - break; - - ++counter; - } - - if (counter == max_tries) { - dm_logger_write(opp80->base.ctx->logger, LOG_WARNING, - "%s: regamma lut was not powered on " - "in a timely manner," - " programming still proceeds\n", - __func__); - } - } - - value = 0; - - set_reg_field_value( - value, - 7, - REGAMMA_LUT_WRITE_EN_MASK, - REGAMMA_LUT_WRITE_EN_MASK); - - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_LUT_WRITE_EN_MASK), value); - dm_write_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_LUT_INDEX), 0); - - /* Program REGAMMA_LUT_DATA */ - { - const uint32_t addr = DCP_REG(mmREGAMMA_LUT_DATA); - - uint32_t i = 0; - - const struct pwl_result_data *rgb = - params->rgb_resulted; - - while (i != params->hw_points_num) { - dm_write_reg(opp80->base.ctx, addr, rgb->red_reg); - dm_write_reg(opp80->base.ctx, addr, rgb->green_reg); - dm_write_reg(opp80->base.ctx, addr, rgb->blue_reg); - - dm_write_reg(opp80->base.ctx, addr, - rgb->delta_red_reg); - dm_write_reg(opp80->base.ctx, addr, - rgb->delta_green_reg); - dm_write_reg(opp80->base.ctx, addr, - rgb->delta_blue_reg); - - ++rgb; - ++i; - } - } - - /* we are done with DCP LUT memory; re-enable low power mode */ - value = dm_read_reg(opp80->base.ctx, - DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL)); - - set_reg_field_value( - value, - 0, - DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS); - - dm_write_reg(opp80->base.ctx, DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL), - value); -} - -void dce80_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - - uint32_t value = - dm_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL)); - - set_reg_field_value( - value, - power_on, - DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS); - - set_reg_field_value( - value, - power_on, - DCFE_MEM_LIGHT_SLEEP_CNTL, - DCP_LUT_LIGHT_SLEEP_DIS); - - dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL), value); -} - -bool dce80_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *params) -{ - - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - - regamma_config_regions_and_segments(opp80, params); - - program_pwl(opp80, params); - - return true; -} - -void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode) -{ - struct dce80_opp *opp80 = TO_DCE80_OPP(opp); - uint32_t value = dm_read_reg(opp80->base.ctx, - DCP_REG(mmREGAMMA_CONTROL)); - - set_reg_field_value( - value, - mode, - REGAMMA_CONTROL, - GRPH_REGAMMA_MODE); - - dm_write_reg(opp80->base.ctx, DCP_REG(mmREGAMMA_CONTROL), value); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 517d42dfff0c..56a63d985440 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -43,7 +43,7 @@ #include "dce80/dce80_mem_input.h" #include "dce80/dce80_ipp.h" #include "dce/dce_transform.h" -#include "dce80/dce80_opp.h" +#include "dce/dce_opp.h" #include "dce110/dce110_ipp.h" #include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" @@ -317,6 +317,28 @@ static const struct dce_stream_encoder_mask se_mask = { SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) }; +#define opp_regs(id)\ +[id] = {\ + OPP_DCE_80_REG_LIST(id),\ +} + +static const struct dce_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3), + opp_regs(4), + opp_regs(5) +}; + +static const struct dce_opp_shift opp_shift = { + OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) +}; + +static const struct dce_opp_mask opp_mask = { + OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) +}; + #define audio_regs(id)\ [id] = {\ AUD_COMMON_REG_LIST(id)\ @@ -419,6 +441,25 @@ static struct timing_generator *dce80_timing_generator_create( return NULL; } +static struct output_pixel_processor *dce80_opp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce110_opp *opp = + dm_alloc(sizeof(struct dce110_opp)); + + if (!opp) + return NULL; + + if (dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) + return &opp->base; + + BREAK_TO_DEBUGGER(); + dm_free(opp); + return NULL; +} + static struct stream_encoder *dce80_stream_encoder_create( enum engine_id eng_id, struct dc_context *ctx) @@ -631,7 +672,7 @@ static void destruct(struct dce110_resource_pool *pool) for (i = 0; i < pool->base.pipe_count; i++) { if (pool->base.opps[i] != NULL) - dce80_opp_destroy(&pool->base.opps[i]); + dce110_opp_destroy(&pool->base.opps[i]); if (pool->base.transforms[i] != NULL) dce80_transform_destroy(&pool->base.transforms[i]); -- cgit v1.2.3-59-g8ed1b From 1964cb736aaa094379d47aa1dc056a5531cecbd6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 13 Dec 2016 16:41:05 +1000 Subject: drm/amd/display: remove dc hub - this seems unused. Signed-off-by: Dave Airlie Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 27 ---------------------- drivers/gpu/drm/amd/display/dc/dc.h | 17 -------------- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 1 - .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 1 - drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 -- 5 files changed, 48 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index df1bae8ea92b..891075e39ecf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1871,30 +1871,3 @@ const struct dc_stream_status *dc_stream_get_status( return &stream->status; } -bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) -{ - int i; - struct core_dc *core_dc = DC_TO_CORE(dc); - struct mem_input *mi = NULL; - - for (i = 0; i < core_dc->res_pool->pipe_count; i++) { - if (core_dc->res_pool->mis[i] != NULL) { - mi = core_dc->res_pool->mis[i]; - break; - } - } - if (mi == NULL) { - dm_error("no mem_input!\n"); - return false; - } - - if (mi->funcs->mem_input_update_dchub) - mi->funcs->mem_input_update_dchub(mi, dh_data); - else - ASSERT(mi->funcs->mem_input_update_dchub); - - - return true; - -} - diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ffea10c73275..f786a17de1fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -159,21 +159,6 @@ struct dc { struct dc_debug debug; }; -enum frame_buffer_mode { - FRAME_BUFFER_MODE_LOCAL_ONLY = 0, - FRAME_BUFFER_MODE_ZFB_ONLY, - FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, -} ; - -struct dchub_init_data { - bool dchub_initialzied; - bool dchub_info_valid; - int64_t zfb_phys_addr_base; - int64_t zfb_mc_base_addr; - uint64_t zfb_size_in_byte; - enum frame_buffer_mode fb_mode; -}; - struct dc_init_data { struct hw_asic_id asic_id; void *driver; /* ctx */ @@ -194,8 +179,6 @@ struct dc *dc_create(const struct dc_init_data *init_params); void dc_destroy(struct dc **dc); -bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); - /******************************************************************************* * Surface Interfaces ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index a20feaedfca4..1643fb5d4b04 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -409,7 +409,6 @@ static struct mem_input_funcs dce110_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, - .mem_input_update_dchub = NULL }; /*****************************************/ /* Constructor, Destructor */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c index ebb8df3cdf4a..704a7ce62080 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c @@ -54,7 +54,6 @@ static struct mem_input_funcs dce80_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, - .mem_input_update_dchub = NULL }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 80566c844758..2c0774f95c1c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -99,8 +99,6 @@ struct mem_input_funcs { bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); - void (*mem_input_update_dchub)(struct mem_input *mem_input, - struct dchub_init_data *dh_data); }; #endif -- cgit v1.2.3-59-g8ed1b From b76794d2e7198cf7c73f1b65dbc6dc796ac92685 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Mon, 19 Dec 2016 12:54:40 -0500 Subject: drm/amd/display: 4k split black out due to incorrect cursor - add handling to program both cursor for left and right pipe - add guard to disable cursor in case where cursor isn't visible to prevent pipe hang Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_target.c | 83 ++++++++++------------ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 9 +++ drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 3 +- .../drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 3 +- 5 files changed, 53 insertions(+), 48 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_target.c b/drivers/gpu/drm/amd/display/dc/core/dc_target.c index 48eb7b0e0350..2531df74871a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_target.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_target.c @@ -148,56 +148,49 @@ bool dc_target_set_cursor_attributes( struct dc_target *dc_target, const struct dc_cursor_attributes *attributes) { - uint8_t i, j; - struct core_target *target; - struct core_dc *core_dc; - struct resource_context *res_ctx; + int i, j; + struct core_target *target = DC_TARGET_TO_CORE(dc_target); + struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); + struct resource_context *res_ctx = &core_dc->current_context->res_ctx; + bool ret = false; if (NULL == dc_target) { dm_error("DC: dc_target is NULL!\n"); return false; - } if (NULL == attributes) { dm_error("DC: attributes is NULL!\n"); return false; - } - target = DC_TARGET_TO_CORE(dc_target); - core_dc = DC_TO_CORE(target->ctx->dc); - res_ctx = &core_dc->current_context->res_ctx; + for (i = 0; i < dc_target->stream_count; i++) { + const struct dc_stream *stream = dc_target->streams[i]; - for (i = 0; i < target->public.stream_count; i++) { for (j = 0; j < MAX_PIPES; j++) { - struct input_pixel_processor *ipp = - res_ctx->pipe_ctx[j].ipp; + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j]; - if (res_ctx->pipe_ctx[j].stream != - DC_STREAM_TO_CORE(target->public.streams[i])) - continue; + if (&pipe_ctx->stream->public == stream) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; - /* As of writing of this code cursor is on the top - * plane so we only need to set it on first pipe we - * find. May need to make this code dce specific later. - */ - if (ipp->funcs->ipp_cursor_set_attributes( - ipp, attributes)) - return true; + if (ipp->funcs->ipp_cursor_set_attributes( + ipp, attributes)) + ret = true; + } } } - return false; + return ret; } bool dc_target_set_cursor_position( struct dc_target *dc_target, const struct dc_cursor_position *position) { - uint8_t i, j; - struct core_target *target; - struct core_dc *core_dc; - struct resource_context *res_ctx; + int i, j; + struct core_target *target = DC_TARGET_TO_CORE(dc_target); + struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); + struct resource_context *res_ctx = &core_dc->current_context->res_ctx; + bool ret = false; if (NULL == dc_target) { dm_error("DC: dc_target is NULL!\n"); @@ -209,29 +202,29 @@ bool dc_target_set_cursor_position( return false; } - target = DC_TARGET_TO_CORE(dc_target); - core_dc = DC_TO_CORE(target->ctx->dc); - res_ctx = &core_dc->current_context->res_ctx; + for (i = 0; i < dc_target->stream_count; i++) { + const struct dc_stream *stream = dc_target->streams[i]; - for (i = 0; i < target->public.stream_count; i++) { for (j = 0; j < MAX_PIPES; j++) { - struct input_pixel_processor *ipp = - res_ctx->pipe_ctx[j].ipp; - - if (res_ctx->pipe_ctx[j].stream != - DC_STREAM_TO_CORE(target->public.streams[i])) - continue; - - /* As of writing of this code cursor is on the top - * plane so we only need to set it on first pipe we - * find. May need to make this code dce specific later. - */ - ipp->funcs->ipp_cursor_set_position(ipp, position); - return true; + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j]; + + if (&pipe_ctx->stream->public == stream) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct dc_cursor_mi_param param = { + .pixel_clk_khz = stream->timing.pix_clk_khz, + .ref_clk_khz = 48000,/*todo refclk*/ + .viewport_x_start = pipe_ctx->scl_data.viewport.x, + .viewport_width = pipe_ctx->scl_data.viewport.width, + .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, + }; + + ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m); + ret = true; + } } } - return false; + return ret; } uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target) diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 5605a5c96da7..bd603374a3c9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -27,6 +27,7 @@ #define DC_HW_TYPES_H #include "os_types.h" +#include "fixed31_32.h" /****************************************************************************** * Data types for Virtual HW Layer of DAL3. @@ -359,6 +360,14 @@ struct dc_cursor_position { bool hot_spot_enable; }; +struct dc_cursor_mi_param { + unsigned int pixel_clk_khz; + unsigned int ref_clk_khz; + unsigned int viewport_x_start; + unsigned int viewport_width; + struct fixed31_32 h_scale_ratio; +}; + /* IPP related types */ /* Used by both ipp amd opp functions*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h index 60eebdecfa10..56fe3274407c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h @@ -54,7 +54,8 @@ void dce110_ipp_destroy(struct input_pixel_processor **ipp); /* CURSOR RELATED */ void dce110_ipp_cursor_set_position( struct input_pixel_processor *ipp, - const struct dc_cursor_position *position); + const struct dc_cursor_position *position, + const struct dc_cursor_mi_param *param); bool dce110_ipp_cursor_set_attributes( struct input_pixel_processor *ipp, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c index 95f6ca3ba5df..1cab12ba8447 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c @@ -72,7 +72,8 @@ static void program_address( void dce110_ipp_cursor_set_position( struct input_pixel_processor *ipp, - const struct dc_cursor_position *position) + const struct dc_cursor_position *position, + const struct dc_cursor_mi_param *param) { struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 7e5f3e02a719..81de97568d11 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -83,7 +83,8 @@ struct ipp_funcs { /*** cursor ***/ void (*ipp_cursor_set_position)( struct input_pixel_processor *ipp, - const struct dc_cursor_position *position); + const struct dc_cursor_position *position, + const struct dc_cursor_mi_param *param); bool (*ipp_cursor_set_attributes)( struct input_pixel_processor *ipp, -- cgit v1.2.3-59-g8ed1b From d7194cf6b8ddf0344e70834397d0b1af2cc5fe05 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Tue, 20 Dec 2016 20:24:24 -0500 Subject: drm/amd/display: Implement gamma correction using input LUT The dc_gamma in dc_surface will be programmed to the input LUT if provided. If dc_gamma is not provided in dc_surface regamma may be used to emulate gamma. Some refactor and cleanup included as well. Signed-off-by: Aric Cyr Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 17 +- drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c | 29 +- drivers/gpu/drm/amd/display/dc/dc.h | 36 --- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 10 + drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 2 - drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 4 - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 17 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c | 1 + drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 11 +- .../drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 304 ++++++--------------- .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 1 - .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 2 - .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 4 - drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c | 1 + drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h | 2 - .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c | 5 - drivers/gpu/drm/amd/display/dc/inc/gamma_types.h | 38 --- drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 4 + drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 - drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 - drivers/gpu/drm/amd/display/modules/color/color.c | 6 +- 21 files changed, 138 insertions(+), 359 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/gamma_types.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 364f2c970b6e..f969bfedb368 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -521,14 +521,11 @@ static void fill_gamma_from_crtc( return; for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) { - gamma->gamma_ramp_rgb256x3x16.red[i] = lut[i].red; - gamma->gamma_ramp_rgb256x3x16.green[i] = lut[i].green; - gamma->gamma_ramp_rgb256x3x16.blue[i] = lut[i].blue; + gamma->red[i] = lut[i].red; + gamma->green[i] = lut[i].green; + gamma->blue[i] = lut[i].blue; } - gamma->type = GAMMA_RAMP_RBG256X3X16; - gamma->size = sizeof(gamma->gamma_ramp_rgb256x3x16); - dc_surface->gamma_correction = gamma; input_tf = dc_create_transfer_func(); @@ -822,6 +819,12 @@ static void fill_stream_properties_from_drm_display_mode( stream->output_color_space = get_output_color_space(timing_out); + { + struct dc_transfer_func *tf = dc_create_transfer_func(); + tf->type = TF_TYPE_PREDEFINED; + tf->tf = TRANSFER_FUNCTION_SRGB; + stream->out_transfer_func = tf; + } } static void fill_audio_info( @@ -3066,7 +3069,7 @@ static bool is_dp_capable_without_timing_msa( dc_read_dpcd(dc, amdgpu_connector->dc_link->link_index, DP_DOWN_STREAM_PORT_COUNT, &dpcd_data, sizeof(dpcd_data)) ) - capable = dpcd_data & DP_MSA_TIMING_PAR_IGNORED? true:false; + capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; return capable; } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c index f33135b53a80..ca2234e4b7d2 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c @@ -573,7 +573,7 @@ static bool find_software_points( uint32_t *index_right, enum hw_point_position *pos) { - const uint32_t max_number = RGB_256X3X16 + 3; + const uint32_t max_number = INPUT_LUT_ENTRIES + 3; struct fixed31_32 left, right; @@ -686,12 +686,12 @@ static bool build_custom_gamma_mapping_coefficients_worker( return false; } - if (index_left >= RGB_256X3X16 + 3) { + if (index_left >= INPUT_LUT_ENTRIES + 3) { BREAK_TO_DEBUGGER(); return false; } - if (index_right >= RGB_256X3X16 + 3) { + if (index_right >= INPUT_LUT_ENTRIES + 3) { BREAK_TO_DEBUGGER(); return false; } @@ -958,20 +958,13 @@ static bool scale_gamma(struct pwl_float_data *pwl_rgb, const struct core_gamma *ramp, struct dividers dividers) { - const struct dc_gamma_ramp_rgb256x3x16 *gamma; + const struct dc_gamma *gamma = &ramp->public; const uint16_t max_driver = 0xFFFF; const uint16_t max_os = 0xFF00; uint16_t scaler = max_os; - uint32_t i; + uint32_t i = 0; struct pwl_float_data *rgb = pwl_rgb; - struct pwl_float_data *rgb_last = rgb + RGB_256X3X16 - 1; - - if (ramp->public.type == GAMMA_RAMP_RBG256X3X16) - gamma = &ramp->public.gamma_ramp_rgb256x3x16; - else - return false; /* invalid option */ - - i = 0; + struct pwl_float_data *rgb_last = rgb + INPUT_LUT_ENTRIES - 1; do { if ((gamma->red[i] > max_os) || @@ -981,7 +974,7 @@ static bool scale_gamma(struct pwl_float_data *pwl_rgb, break; } ++i; - } while (i != RGB_256X3X16); + } while (i != INPUT_LUT_ENTRIES); i = 0; @@ -995,7 +988,7 @@ static bool scale_gamma(struct pwl_float_data *pwl_rgb, ++rgb; ++i; - } while (i != RGB_256X3X16); + } while (i != INPUT_LUT_ENTRIES); rgb->r = dal_fixed31_32_mul(rgb_last->r, dividers.divider1); @@ -1110,7 +1103,7 @@ static bool calculate_interpolated_hardware_curve( return false; coeff = coeff128; - max_entries += RGB_256X3X16; + max_entries += INPUT_LUT_ENTRIES; /* TODO: float point case */ @@ -1440,13 +1433,13 @@ bool calculate_regamma_params(struct pwl_params *params, coordinates_x = dm_alloc(sizeof(*coordinates_x)*(256 + 3)); if (!coordinates_x) goto coordinates_x_alloc_fail; - rgb_user = dm_alloc(sizeof(*rgb_user) * (FLOAT_GAMMA_RAMP_MAX + 3)); + rgb_user = dm_alloc(sizeof(*rgb_user) * (TRANSFER_FUNC_POINTS + 3)); if (!rgb_user) goto rgb_user_alloc_fail; rgb_regamma = dm_alloc(sizeof(*rgb_regamma) * (256 + 3)); if (!rgb_regamma) goto rgb_regamma_alloc_fail; - rgb_oem = dm_alloc(sizeof(*rgb_oem) * (FLOAT_GAMMA_RAMP_MAX + 3)); + rgb_oem = dm_alloc(sizeof(*rgb_oem) * (TRANSFER_FUNC_POINTS + 3)); if (!rgb_oem) goto rgb_oem_alloc_fail; axix_x_256 = dm_alloc(sizeof(*axix_x_256) * (256 + 3)); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 478bdee52cd5..0ee6f41b6047 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -183,43 +183,9 @@ void dc_destroy(struct dc **dc); ******************************************************************************/ enum { - RGB_256X3X16 = 256, - FLOAT_GAMMA_RAMP_MAX = 1025, TRANSFER_FUNC_POINTS = 1025 }; -enum dc_gamma_ramp_type { - GAMMA_RAMP_RBG256X3X16, - GAMMA_RAMP_FLOAT, -}; - -struct float_rgb { - struct fixed32_32 red; - struct fixed32_32 green; - struct fixed32_32 blue; -}; - -struct dc_gamma_ramp_float { - struct float_rgb scale; - struct float_rgb offset; - struct float_rgb gamma_curve[FLOAT_GAMMA_RAMP_MAX]; -}; - -struct dc_gamma_ramp_rgb256x3x16 { - uint16_t red[RGB_256X3X16]; - uint16_t green[RGB_256X3X16]; - uint16_t blue[RGB_256X3X16]; -}; - -struct dc_gamma { - enum dc_gamma_ramp_type type; - union { - struct dc_gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16; - struct dc_gamma_ramp_float gamma_ramp_float; - }; - uint32_t size; -}; - enum dc_transfer_func_type { TF_TYPE_PREDEFINED, TF_TYPE_DISTRIBUTED_POINTS, @@ -266,9 +232,7 @@ struct dc_surface { bool horizontal_mirror; enum plane_stereo_format stereo_format; - /* TO BE REMOVED AFTER BELOW TRANSFER FUNCTIONS IMPLEMENTED */ const struct dc_gamma *gamma_correction; - const struct dc_transfer_func *in_transfer_func; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 499f6b2a31f8..00958bdbb417 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -370,6 +370,16 @@ struct dc_cursor_mi_param { /* IPP related types */ +enum { + INPUT_LUT_ENTRIES = 256 +}; + +struct dc_gamma { + uint16_t red[INPUT_LUT_ENTRIES]; + uint16_t green[INPUT_LUT_ENTRIES]; + uint16_t blue[INPUT_LUT_ENTRIES]; +}; + /* Used by both ipp amd opp functions*/ /* TODO: to be consolidated with enum color_space */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 653f93dd281f..46b128708c7e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -28,8 +28,6 @@ #include "dce_opp.h" -#include "gamma_types.h" - #include "reg_helper.h" #define REG(reg)\ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index 1c01a83ecc50..f2828f044b96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -29,10 +29,6 @@ #include "opp.h" #include "core_types.h" -#include "gamma_types.h" /* decprecated */ - -struct gamma_parameters; - #define FROM_DCE11_OPP(opp)\ container_of(opp, struct dce110_opp, base) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2f790753b559..e4cef9da5de1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -228,10 +228,11 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, break; default: ASSERT(false); + break; } } -static bool dce110_set_degamma( +static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct core_surface *surface) { @@ -249,6 +250,9 @@ static bool dce110_set_degamma( build_prescale_params(&prescale_params, surface); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); + if (surface->public.gamma_correction) + ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); + if (tf == NULL) { /* Default case if no input transfer function specified */ ipp->funcs->ipp_set_degamma(ipp, @@ -272,6 +276,7 @@ static bool dce110_set_degamma( break; default: result = false; + break; } } else { /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ @@ -303,8 +308,11 @@ static bool dce110_set_output_transfer_func( opp->funcs->opp_power_on_regamma_lut(opp, true); - if (ramp && calculate_regamma_params( - regamma_params, ramp, surface, stream)) { + if (stream->public.out_transfer_func && + stream->public.out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { + opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); + } else if (ramp && calculate_regamma_params(regamma_params, ramp, surface, stream)) { opp->funcs->opp_program_regamma_pwl(opp, regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { @@ -1318,7 +1326,6 @@ enum dc_status dce110_apply_ctx_to_hw( * instead of per pipe. */ struct audio_output audio_output; - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; build_audio_output(pipe_ctx, &audio_output); @@ -1945,7 +1952,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, .update_pending_status = dce110_update_pending_status, - .set_input_transfer_func = dce110_set_degamma, + .set_input_transfer_func = dce110_set_input_transfer_func, .set_output_transfer_func = dce110_set_output_transfer_func, .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c index dd69f6060bb9..86fa7657a756 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c @@ -35,6 +35,7 @@ static const struct ipp_funcs funcs = { .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, .ipp_cursor_set_position = dce110_ipp_cursor_set_position, .ipp_program_prescale = dce110_ipp_program_prescale, + .ipp_program_input_lut = dce110_ipp_program_input_lut, .ipp_set_degamma = dce110_ipp_set_degamma, }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h index 56fe3274407c..a374ef2c9d0b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h @@ -28,9 +28,6 @@ #include "ipp.h" -struct gamma_parameters; -struct dev_c_lut; - #define TO_DCE110_IPP(input_pixel_processor)\ container_of(input_pixel_processor, struct dce110_ipp, base) @@ -69,9 +66,9 @@ bool dce110_ipp_set_degamma( void dce110_ipp_program_prescale( struct input_pixel_processor *ipp, struct ipp_prescale_params *params); -/* - * Helper functions to be resused in other ASICs - */ -void dce110_helper_select_lut(struct dce110_ipp *ipp110); + +void dce110_ipp_program_input_lut( + struct input_pixel_processor *ipp, + const struct dc_gamma *gamma); #endif /*__DC_IPP_DCE110_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c index 79a6a6dd72fc..c68914bf7af0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c @@ -32,21 +32,39 @@ #include "dce/dce_11_0_sh_mask.h" #include "dce110_ipp.h" -#include "gamma_types.h" #define DCP_REG(reg)\ - (reg + ipp110->offsets.dcp_offset) + (mm##reg + ipp110->offsets.dcp_offset) + +#define DCP_REG_SET_N(reg_name, n, ...) \ + generic_reg_update_ex(ipp110->base.ctx, \ + DCP_REG(reg_name), \ + 0, n, __VA_ARGS__) + +#define DCP_REG_SET(reg, field1, val1) \ + DCP_REG_SET_N(reg, 1, FD(reg##__##field1), val1) + +#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ + DCP_REG_SET_N(reg, 2, \ + FD(reg##__##field1), val1, \ + FD(reg##__##field2), val2) + +#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ + DCP_REG_SET_N(reg, 3, \ + FD(reg##__##field1), val1, \ + FD(reg##__##field2), val2, \ + FD(reg##__##field3), val3) + +#define DCP_REG_UPDATE_N(reg_name, n, ...) \ + generic_reg_update_ex(ipp110->base.ctx, \ + DCP_REG(reg_name), \ + dm_read_reg(ipp110->base.ctx, DCP_REG(reg_name)), \ + n, __VA_ARGS__) + +#define DCP_REG_UPDATE(reg, field, val) \ + DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) -enum { - MAX_INPUT_LUT_ENTRY = 256 -}; -/*PROTOTYPE DECLARATIONS*/ -static void set_lut_inc( - struct dce110_ipp *ipp110, - uint8_t inc, - bool is_float, - bool is_signed); bool dce110_ipp_set_degamma( struct input_pixel_processor *ipp, @@ -61,25 +79,11 @@ bool dce110_ipp_set_degamma( ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); - set_reg_field_value( - value, - degamma_type, - DEGAMMA_CONTROL, - GRPH_DEGAMMA_MODE); - - set_reg_field_value( - value, - degamma_type, - DEGAMMA_CONTROL, - CURSOR_DEGAMMA_MODE); - - set_reg_field_value( - value, - degamma_type, + DCP_REG_SET_3( DEGAMMA_CONTROL, - CURSOR2_DEGAMMA_MODE); - - dm_write_reg(ipp110->base.ctx, DCP_REG(mmDEGAMMA_CONTROL), value); + GRPH_DEGAMMA_MODE, degamma_type, + CURSOR_DEGAMMA_MODE, degamma_type, + CURSOR2_DEGAMMA_MODE, degamma_type); return true; } @@ -90,214 +94,70 @@ void dce110_ipp_program_prescale( { struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - uint32_t prescale_control = 0; - uint32_t prescale_value = 0; - uint32_t legacy_lut_control = 0; + /* set to bypass mode first before change */ + DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS, 1); - prescale_control = dm_read_reg(ipp110->base.ctx, - DCP_REG(mmPRESCALE_GRPH_CONTROL)); + DCP_REG_SET_2(PRESCALE_VALUES_GRPH_R, + GRPH_PRESCALE_SCALE_R, params->scale, + GRPH_PRESCALE_BIAS_R, params->bias); - if (params->mode != IPP_PRESCALE_MODE_BYPASS) { + DCP_REG_SET_2(PRESCALE_VALUES_GRPH_G, + GRPH_PRESCALE_SCALE_G, params->scale, + GRPH_PRESCALE_BIAS_G, params->bias); - set_reg_field_value( - prescale_control, - 0, - PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS); - - /* - * If prescale is in use, then legacy lut should - * be bypassed - */ - legacy_lut_control = dm_read_reg(ipp110->base.ctx, - DCP_REG(mmINPUT_GAMMA_CONTROL)); - - set_reg_field_value( - legacy_lut_control, - 1, - INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE); - - dm_write_reg(ipp110->base.ctx, - DCP_REG(mmINPUT_GAMMA_CONTROL), - legacy_lut_control); - } else { - set_reg_field_value( - prescale_control, - 1, - PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS); - } + DCP_REG_SET_2(PRESCALE_VALUES_GRPH_B, + GRPH_PRESCALE_SCALE_B, params->scale, + GRPH_PRESCALE_BIAS_B, params->bias); - set_reg_field_value( - prescale_value, - params->scale, - PRESCALE_VALUES_GRPH_R, - GRPH_PRESCALE_SCALE_R); - - set_reg_field_value( - prescale_value, - params->bias, - PRESCALE_VALUES_GRPH_R, - GRPH_PRESCALE_BIAS_R); - - dm_write_reg(ipp110->base.ctx, - DCP_REG(mmPRESCALE_GRPH_CONTROL), - prescale_control); - - dm_write_reg(ipp110->base.ctx, - DCP_REG(mmPRESCALE_VALUES_GRPH_R), - prescale_value); - - dm_write_reg(ipp110->base.ctx, - DCP_REG(mmPRESCALE_VALUES_GRPH_G), - prescale_value); - - dm_write_reg(ipp110->base.ctx, - DCP_REG(mmPRESCALE_VALUES_GRPH_B), - prescale_value); -} - -static void set_lut_inc( - struct dce110_ipp *ipp110, - uint8_t inc, - bool is_float, - bool is_signed) -{ - const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL); - - uint32_t value = dm_read_reg(ipp110->base.ctx, addr); - - set_reg_field_value( - value, - inc, - DC_LUT_CONTROL, - DC_LUT_INC_R); - - set_reg_field_value( - value, - inc, - DC_LUT_CONTROL, - DC_LUT_INC_G); - - set_reg_field_value( - value, - inc, - DC_LUT_CONTROL, - DC_LUT_INC_B); - - set_reg_field_value( - value, - is_float, - DC_LUT_CONTROL, - DC_LUT_DATA_R_FLOAT_POINT_EN); - - set_reg_field_value( - value, - is_float, - DC_LUT_CONTROL, - DC_LUT_DATA_G_FLOAT_POINT_EN); - - set_reg_field_value( - value, - is_float, - DC_LUT_CONTROL, - DC_LUT_DATA_B_FLOAT_POINT_EN); - - set_reg_field_value( - value, - is_signed, - DC_LUT_CONTROL, - DC_LUT_DATA_R_SIGNED_EN); - - set_reg_field_value( - value, - is_signed, - DC_LUT_CONTROL, - DC_LUT_DATA_G_SIGNED_EN); - - set_reg_field_value( - value, - is_signed, - DC_LUT_CONTROL, - DC_LUT_DATA_B_SIGNED_EN); - - dm_write_reg(ipp110->base.ctx, addr, value); + if (params->mode != IPP_PRESCALE_MODE_BYPASS) { + /* If prescale is in use, then legacy lut should be bypassed */ + DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 0); + DCP_REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 1); + } } -void dce110_helper_select_lut(struct dce110_ipp *ipp110) +static void dce110_helper_select_lut(struct dce110_ipp *ipp110) { - uint32_t value = 0; - - set_lut_inc(ipp110, 0, false, false); - - { - const uint32_t addr = DCP_REG(mmDC_LUT_WRITE_EN_MASK); - - value = dm_read_reg(ipp110->base.ctx, addr); - - /* enable all */ - set_reg_field_value( - value, - 0x7, - DC_LUT_WRITE_EN_MASK, - DC_LUT_WRITE_EN_MASK); - - dm_write_reg(ipp110->base.ctx, addr, value); - } - - { - const uint32_t addr = DCP_REG(mmDC_LUT_RW_MODE); - - value = dm_read_reg(ipp110->base.ctx, addr); + /* enable all */ + DCP_REG_SET(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, 0x7); - set_reg_field_value( - value, - 0, - DC_LUT_RW_MODE, - DC_LUT_RW_MODE); + /* 256 entry mode */ + DCP_REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); - dm_write_reg(ipp110->base.ctx, addr, value); - } - - { - const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL); + /* LUT-256, unsigned, integer, new u0.12 format */ + DCP_REG_SET_3(DC_LUT_CONTROL, + DC_LUT_DATA_R_FORMAT, 3, + DC_LUT_DATA_G_FORMAT, 3, + DC_LUT_DATA_B_FORMAT, 3); - value = dm_read_reg(ipp110->base.ctx, addr); + /* start from index 0 */ + DCP_REG_SET(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, 0); +} - /* 00 - new u0.12 */ - set_reg_field_value( - value, - 3, - DC_LUT_CONTROL, - DC_LUT_DATA_R_FORMAT); +void dce110_ipp_program_input_lut( + struct input_pixel_processor *ipp, + const struct dc_gamma *gamma) +{ + int i; + struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - set_reg_field_value( - value, - 3, - DC_LUT_CONTROL, - DC_LUT_DATA_G_FORMAT); + dce110_helper_select_lut(ipp110); - set_reg_field_value( - value, - 3, - DC_LUT_CONTROL, - DC_LUT_DATA_B_FORMAT); + /* power on LUT memory and give it time to settle */ + DCP_REG_SET(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1); + udelay(10); - dm_write_reg(ipp110->base.ctx, addr, value); + for (i = 0; i < INPUT_LUT_ENTRIES; i++) { + DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]); + DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]); + DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]); } - { - const uint32_t addr = DCP_REG(mmDC_LUT_RW_INDEX); - - value = dm_read_reg(ipp110->base.ctx, addr); + /* power off LUT memory */ + DCP_REG_SET(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0); - set_reg_field_value( - value, - 0, - DC_LUT_RW_INDEX, - DC_LUT_RW_INDEX); - - dm_write_reg(ipp110->base.ctx, addr, value); - } + /* bypass prescale, enable legacy LUT */ + DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); + DCP_REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index 81fcbc52e4ab..8164aa6bcb00 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -30,7 +30,6 @@ #include "dce/dce_11_0_sh_mask.h" #include "dce/dce_opp.h" -#include "gamma_types.h" static void power_on_lut(struct output_pixel_processor *opp, bool power_on, bool inputgamma, bool regamma) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index dfd63a71d214..0a9b384303d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -32,8 +32,6 @@ #include "dce/dce_opp.h" #include "dce110_opp_v.h" -#include "gamma_types.h" - /*****************************************/ /* Constructor, Destructor */ /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h index dcdbf86fccc1..ac5937786ce3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -29,10 +29,6 @@ #include "opp.h" #include "core_types.h" -#include "gamma_types.h" /* decprecated */ - -struct gamma_parameters; - bool dce110_opp_v_construct(struct dce110_opp *opp110, struct dc_context *ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c index 86826c229d39..c195acb6e1a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c @@ -37,6 +37,7 @@ static const struct ipp_funcs funcs = { .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, .ipp_cursor_set_position = dce110_ipp_cursor_set_position, .ipp_program_prescale = dce110_ipp_program_prescale, + .ipp_program_input_lut = dce110_ipp_program_input_lut, .ipp_set_degamma = dce110_ipp_set_degamma, }; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h index d350138e5feb..06e8598d395f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h @@ -33,8 +33,6 @@ struct dce110_ipp; struct dce110_ipp_reg_offsets; -struct gamma_parameters; -struct dev_c_lut; bool dce80_ipp_construct( struct dce110_ipp *ipp, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c index eacb14e40d52..760168df5290 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c @@ -34,15 +34,10 @@ #include "dce80_ipp.h" #include "dce110/dce110_ipp.h" -#include "gamma_types.h" #define DCP_REG(reg)\ (reg + ipp80->offsets.dcp_offset) -enum { - MAX_INPUT_LUT_ENTRY = 256 -}; - /*PROTOTYPE DECLARATIONS*/ static void set_legacy_input_gamma_mode( diff --git a/drivers/gpu/drm/amd/display/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/display/dc/inc/gamma_types.h deleted file mode 100644 index 7948d2cc0715..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/gamma_types.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#ifndef GAMMA_TYPES_H_ - -#define GAMMA_TYPES_H_ - -#include "dc_types.h" - -/* TODO: Used in IPP and OPP */ - -struct dev_c_lut16 { - uint16_t red; - uint16_t green; - uint16_t blue; -}; -#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index e9ed167c9e41..0457bc7a44d4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -110,6 +110,10 @@ struct ipp_funcs { struct input_pixel_processor *ipp, struct ipp_prescale_params *params); + void (*ipp_program_input_lut)( + struct input_pixel_processor *ipp, + const struct dc_gamma *gamma); + /*** DEGAMMA RELATED ***/ bool (*ipp_set_degamma)( struct input_pixel_processor *ipp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index e615997be20e..a1f31a4410a3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -30,7 +30,6 @@ #include "transform.h" struct fixed31_32; -struct gamma_parameters; /* TODO: Need cleanup */ enum clamping_range { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 0e803ca83bb9..895c446cebf9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -28,8 +28,6 @@ #include "core_types.h" #include "timing_generator.h" -struct gamma_parameters; - enum pipe_gating_control { PIPE_GATING_CONTROL_DISABLE = 0, PIPE_GATING_CONTROL_ENABLE, diff --git a/drivers/gpu/drm/amd/display/modules/color/color.c b/drivers/gpu/drm/amd/display/modules/color/color.c index 6d1b20f6bf98..5c578aecf21c 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color.c +++ b/drivers/gpu/drm/amd/display/modules/color/color.c @@ -2433,7 +2433,7 @@ bool mod_color_set_input_gamma_correction(struct mod_color *mod_color, if (surface != NULL) { struct dc_transfer_func *input_tf = - dc_create_transfer_func(core_color->dc); + dc_create_transfer_func(); struct dc_surface_update updates = {0}; if (input_tf != NULL) { @@ -2724,7 +2724,7 @@ bool mod_color_update_gamut_info(struct mod_color *mod_color, /* 3. ---- SET DEGAMMA ---- */ struct dc_transfer_func *input_tf = NULL; - input_tf = dc_create_transfer_func(core_color->dc); + input_tf = dc_create_transfer_func(); if (input_tf != NULL) { input_tf->type = TF_TYPE_PREDEFINED; @@ -2747,7 +2747,7 @@ bool mod_color_update_gamut_info(struct mod_color *mod_color, /* 4. ---- SET REGAMMA ---- */ struct dc_transfer_func *output_tf = NULL; - output_tf = dc_create_transfer_func(core_color->dc); + output_tf = dc_create_transfer_func(); if (output_tf != NULL) { output_tf->type = TF_TYPE_PREDEFINED; -- cgit v1.2.3-59-g8ed1b From 8c737fcc24b01ef36da5f78aace70d444485abf9 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 22 Dec 2016 13:07:11 -0500 Subject: drm/amd/display: Fixed crash caused by unnecessary clock source in split pipe. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 20 ++++++++++---------- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- 3 files changed, 13 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index eac597d0c790..386b3cc14fbe 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -211,27 +211,28 @@ bool resource_construct( void resource_unreference_clock_source( struct resource_context *res_ctx, - struct clock_source *clock_source) + struct clock_source **clock_source) { int i; for (i = 0; i < res_ctx->pool->clk_src_count; i++) { - if (res_ctx->pool->clock_sources[i] != clock_source) + if (res_ctx->pool->clock_sources[i] != *clock_source) continue; res_ctx->clock_source_ref_count[i]--; if (res_ctx->clock_source_ref_count[i] == 0) - clock_source->funcs->cs_power_down(clock_source); + (*clock_source)->funcs->cs_power_down(*clock_source); break; } - if (res_ctx->pool->dp_clock_source == clock_source) { + if (res_ctx->pool->dp_clock_source == *clock_source) { res_ctx->dp_clock_source_ref_count--; if (res_ctx->dp_clock_source_ref_count == 0) - clock_source->funcs->cs_power_down(clock_source); + (*clock_source)->funcs->cs_power_down(*clock_source); } + *clock_source = NULL; } void resource_reference_clock_source( @@ -288,11 +289,6 @@ static bool is_sharable_clk_src( if (pipe_with_clk_src->clock_source == NULL) return false; - if (pipe_with_clk_src->stream == NULL) { - ASSERT(0); - return false; - } - if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) return false; @@ -1148,6 +1144,10 @@ enum dc_status resource_map_pool_resources( pipe_ctx->stream = stream; copy_pipe_ctx(old_pipe_ctx, pipe_ctx); + /* Split pipe resource, do not acquire back end */ + if (!pipe_ctx->stream_enc) + continue; + set_stream_engine_in_use( &context->res_ctx, pipe_ctx->stream_enc); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e4cef9da5de1..6a7cb3e9294a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1028,7 +1028,7 @@ static void switch_dp_clock_sources( if (clk_src && clk_src != pipe_ctx->clock_source) { resource_unreference_clock_source( - res_ctx, pipe_ctx->clock_source); + res_ctx, &pipe_ctx->clock_source); pipe_ctx->clock_source = clk_src; resource_reference_clock_source(res_ctx, clk_src); @@ -1056,7 +1056,7 @@ static void reset_single_pipe_hw_ctx( pipe_ctx->mi->funcs->free_mem_input( pipe_ctx->mi, context->target_count); resource_unreference_clock_source( - &context->res_ctx, pipe_ctx->clock_source); + &context->res_ctx, &pipe_ctx->clock_source); dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 8dd676de6b07..adf297ec33b6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -94,7 +94,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx); void resource_unreference_clock_source( struct resource_context *res_ctx, - struct clock_source *clock_source); + struct clock_source **clock_source); void resource_reference_clock_source( struct resource_context *res_ctx, -- cgit v1.2.3-59-g8ed1b From 7fc698a0c0e5901923a6d6c04a59aceefffe4c9b Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 3 Jan 2017 12:40:40 -0500 Subject: drm/amd/display: limit HBR3 support to Polaris and up - also fix YCbCr420 supported on Polaris and up Signed-off-by: Tony Cheng Reviewed-by: Hersen Wu Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 31 ++++------------------ .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 1 + .../drm/amd/display/dc/dce100/dce100_resource.c | 11 ++++++-- .../drm/amd/display/dc/dce110/dce110_resource.c | 11 ++++++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 15 +++++++++-- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 11 ++++++-- 6 files changed, 46 insertions(+), 34 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index aa6b3449913c..323493b9e129 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -927,10 +927,14 @@ bool dce110_link_encoder_validate_dp_output( bool dce110_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, const struct dce110_link_enc_registers *link_regs, const struct dce110_link_enc_aux_registers *aux_regs, const struct dce110_link_enc_hpd_registers *hpd_regs) { + struct bp_encoder_cap_info bp_cap_info = {0}; + const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; + enc110->base.funcs = &dce110_lnk_enc_funcs; enc110->base.ctx = init_data->ctx; enc110->base.id = init_data->encoder; @@ -941,12 +945,10 @@ bool dce110_link_encoder_construct( enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; - enc110->base.features.flags.raw = 0; + enc110->base.features = *enc_features; enc110->base.transmitter = init_data->transmitter; - enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212; - if (enc110->base.ctx->dc->debug.disable_hdmi_deep_color) enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_888; @@ -1013,10 +1015,6 @@ bool dce110_link_encoder_construct( init_data->channel); /* Override features with DCE-specific values */ - { - struct bp_encoder_cap_info bp_cap_info = {0}; - const struct dc_vbios_funcs *bp_funcs = enc110->base.ctx->dc_bios->funcs; - if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info( enc110->base.ctx->dc_bios, enc110->base.id, &bp_cap_info)) @@ -1024,26 +1022,7 @@ bool dce110_link_encoder_construct( bp_cap_info.DP_HBR2_CAP; enc110->base.features.flags.bits.IS_HBR3_CAPABLE = bp_cap_info.DP_HBR3_EN; - } - - /* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes, - * IS_HBR3_CAPABLE = 0. - */ - /* test pattern 3 support */ - enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true; - /* test pattern 4 support */ - enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true; - - /* - dal_adapter_service_is_feature_supported(as, - FEATURE_SUPPORT_DP_Y_ONLY); -*/ - enc110->base.features.flags.bits.IS_YCBCR_CAPABLE = true; - /* - dal_adapter_service_is_feature_supported(as, - FEATURE_SUPPORT_DP_YUV); - */ return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 1635b239402f..b3667df5250b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -236,6 +236,7 @@ struct dce110_abm_backlight_registers { bool dce110_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, const struct dce110_link_enc_registers *link_regs, const struct dce110_link_enc_aux_registers *aux_regs, const struct dce110_link_enc_hpd_registers *hpd_regs); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 161d4eee4423..082f1f053a3a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -581,6 +581,14 @@ static struct input_pixel_processor *dce100_ipp_create( return NULL; } +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 300000, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_YCBCR_CAPABLE = true +}; + struct link_encoder *dce100_link_encoder_create( const struct encoder_init_data *enc_init_data) { @@ -593,12 +601,11 @@ struct link_encoder *dce100_link_encoder_create( if (dce110_link_encoder_construct( enc110, enc_init_data, + &link_enc_feature, &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_hpd_regs[enc_init_data->hpd_source])) { - enc110->base.features.ycbcr420_supported = false; - enc110->base.features.max_hdmi_pixel_clock = 300000; return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index d4e1ca933b40..ae90da8c1b8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -570,6 +570,14 @@ static struct input_pixel_processor *dce110_ipp_create( return NULL; } +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 594000, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_YCBCR_CAPABLE = true +}; + struct link_encoder *dce110_link_encoder_create( const struct encoder_init_data *enc_init_data) { @@ -582,12 +590,11 @@ struct link_encoder *dce110_link_encoder_create( if (dce110_link_encoder_construct( enc110, enc_init_data, + &link_enc_feature, &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_hpd_regs[enc_init_data->hpd_source])) { - enc110->base.features.ycbcr420_supported = false; - enc110->base.features.max_hdmi_pixel_clock = 594000; return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 2711893b71e5..c63030e9f515 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -564,6 +564,18 @@ static struct transform *dce112_transform_create( dm_free(transform); return NULL; } + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .ycbcr420_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true, + .flags.bits.IS_YCBCR_CAPABLE = true +}; + struct link_encoder *dce112_link_encoder_create( const struct encoder_init_data *enc_init_data) { @@ -576,12 +588,11 @@ struct link_encoder *dce112_link_encoder_create( if (dce110_link_encoder_construct( enc110, enc_init_data, + &link_enc_feature, &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_hpd_regs[enc_init_data->hpd_source])) { - enc110->base.features.ycbcr420_supported = false; - enc110->base.features.max_hdmi_pixel_clock = 600000; return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 56a63d985440..e2bfa7efce1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -611,6 +611,14 @@ static struct input_pixel_processor *dce80_ipp_create( return NULL; } +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 297000, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_YCBCR_CAPABLE = true +}; + struct link_encoder *dce80_link_encoder_create( const struct encoder_init_data *enc_init_data) { @@ -623,12 +631,11 @@ struct link_encoder *dce80_link_encoder_create( if (dce110_link_encoder_construct( enc110, enc_init_data, + &link_enc_feature, &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_hpd_regs[enc_init_data->hpd_source])) { - enc110->base.features.ycbcr420_supported = false; - enc110->base.features.max_hdmi_pixel_clock = 297000; return &enc110->base; } -- cgit v1.2.3-59-g8ed1b From e5cf325b0c21e626c402b57a055f02c478e3df40 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 4 Jan 2017 18:48:07 -0500 Subject: drm/amd/display: Fix warnings in DC Signed-off-by: Harry Wentland Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++++----- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 6 ------ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 - drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 2 -- 4 files changed, 4 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2b08f5ae5e33..3e3379529b69 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1731,14 +1731,15 @@ static void set_hdr_static_info_packet( struct core_stream *stream, struct hw_info_packet *info_packet) { - uint16_t i; + uint16_t i = 0; enum signal_type signal = stream->signal; + struct dc_hdr_static_metadata hdr_metadata; + uint32_t data; if (!surface) return; - struct dc_hdr_static_metadata hdr_metadata = - surface->public.hdr_static_ctx; + hdr_metadata = surface->public.hdr_static_ctx; if (dc_is_hdmi_signal(signal)) { info_packet->valid = true; @@ -1757,8 +1758,6 @@ static void set_hdr_static_info_packet( i = 2; } - uint32_t data; - data = hdr_metadata.is_hdr; info_packet->sb[i++] = data ? 0x02 : 0x00; info_packet->sb[i++] = 0x00; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 46b128708c7e..167f523df657 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -119,7 +119,6 @@ static void regamma_config_regions_and_segments( const struct pwl_params *params) { const struct gamma_curve *curve; - uint32_t value = 0; { REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, @@ -565,8 +564,6 @@ void dce110_opp_set_clamping( struct dce110_opp *opp110, const struct clamping_and_pixel_encoding_params *params) { - uint32_t clamp_cntl_value = 0; - REG_SET_2(FMT_CLAMP_CNTL, 0, FMT_CLAMP_DATA_EN, 0, FMT_CLAMP_COLOR_FORMAT, 0); @@ -731,7 +728,6 @@ void dce110_opp_set_dyn_expansion( static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp) { struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - uint8_t counter = 10; /* clear previous phase lock status*/ REG_UPDATE(FMT_CONTROL, @@ -810,8 +806,6 @@ static bool configure_graphics_mode( enum graphics_csc_adjust_type csc_adjust_type, enum dc_color_space color_space) { - struct dc_context *ctx = opp110->base.ctx; - REG_SET(OUTPUT_CSC_CONTROL, 0, OUTPUT_CSC_GRPH_MODE, 0); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6a7cb3e9294a..2b61fdf3f03d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -293,7 +293,6 @@ static bool dce110_set_output_transfer_func( { struct output_pixel_processor *opp = pipe_ctx->opp; const struct core_gamma *ramp = NULL; - struct ipp_prescale_params prescale_params = { 0 }; struct pwl_params *regamma_params; bool result = false; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c index c68914bf7af0..f05cc9e981f3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c @@ -72,8 +72,6 @@ bool dce110_ipp_set_degamma( { struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - uint32_t value = 0; - uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || -- cgit v1.2.3-59-g8ed1b From b06b7680e341151c8c60b07ddc6f5e63e7392c17 Mon Sep 17 00:00:00 2001 From: Leon Elazar Date: Thu, 5 Jan 2017 17:47:43 -0500 Subject: drm/amd/display: blank mechanism for supporting MPO blank/unblanck functionality apply_ctx_for_surface will update planes visibility by manipulating Blender and CRTC HW modules. Signed-off-by: Leon Elazar Reviewed-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 42 +++++++++++++++++++--- 2 files changed, 37 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 25e7d7bc282b..2277f9bf4bb1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1246,10 +1246,6 @@ bool dc_pre_update_surfaces_to_target( core_dc, &context->res_ctx.pipe_ctx[j], context); - - if (!new_surfaces[i]->visible) - context->res_ctx.pipe_ctx[j].tg->funcs->set_blank( - context->res_ctx.pipe_ctx[j].tg, true); } unexpected_fail: diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2b61fdf3f03d..7c27a820e5be 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1409,20 +1409,52 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) pipe_ctx->opp, &default_adjust); } -static void program_blender(const struct core_dc *dc, + +/******************************************************************************* + * In order to turn on/off specific surface we will program + * Blender + CRTC + * + * In case that we have two surfaces and they have a different visibility + * we can't turn off the CRTC since it will turn off the entire display + * + * |----------------------------------------------- | + * |bottom pipe|curr pipe | | | + * |Surface |Surface | Blender | CRCT | + * |visibility |visibility | Configuration| | + * |------------------------------------------------| + * | off | off | CURRENT_PIPE | blank | + * | off | on | CURRENT_PIPE | unblank | + * | on | off | OTHER_PIPE | unblank | + * | on | on | BLENDING | unblank | + * -------------------------------------------------| + * + ******************************************************************************/ +static void program_surface_visibility(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; + bool blank_target = false; if (pipe_ctx->bottom_pipe) { + + /* For now we are supporting only two pipes */ + ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); + if (pipe_ctx->bottom_pipe->surface->public.visible) { if (pipe_ctx->surface->public.visible) blender_mode = BLND_MODE_BLENDING; else blender_mode = BLND_MODE_OTHER_PIPE; - } - } + + } else if (!pipe_ctx->surface->public.visible) + blank_target = true; + + } else if (!pipe_ctx->surface->public.visible) + blank_target = true; + dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); + pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); + } /** @@ -1495,7 +1527,7 @@ static void set_plane_config( pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; program_scaler(dc, pipe_ctx); - program_blender(dc, pipe_ctx); + program_surface_visibility(dc, pipe_ctx); mi->funcs->mem_input_program_surface_config( mi, @@ -1920,7 +1952,7 @@ static void dce110_apply_ctx_for_surface( continue; dce110_program_front_end_for_pipe(dc, pipe_ctx); - program_blender(dc, pipe_ctx); + program_surface_visibility(dc, pipe_ctx); } } -- cgit v1.2.3-59-g8ed1b From 4b5e7d620901778b24a2980bbc9941eff9b47f77 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Fri, 6 Jan 2017 16:23:18 -0500 Subject: drm/amd/display: set blank functionality 1. remove the sleep mechanism while set_blank true from the timing generator. Since Hw sequencer is the one that manages the flow he will be responsible for wait for blanck in a critical places. Signed-off-by: Leon Elazar Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 20 +++++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 12 +++---- .../display/dc/dce110/dce110_timing_generator.c | 28 +--------------- .../display/dc/dce110/dce110_timing_generator.h | 2 +- .../display/dc/dce110/dce110_timing_generator_v.c | 39 +++------------------- .../drm/amd/display/dc/inc/hw/timing_generator.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++ 7 files changed, 37 insertions(+), 69 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index d5cffa51ca96..9f462a299ff3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -91,3 +91,23 @@ void color_space_to_black_color( break; } } + +bool hwss_wait_for_blank_complete( + struct timing_generator *tg) +{ + int counter; + + for (counter = 0; counter < 100; counter++) { + if (tg->funcs->is_blanked(tg)) + break; + + msleep(1); + } + + if (counter == 100) { + dm_error("DC: failed to blank crtc!\n"); + return false; + } + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7c27a820e5be..965e47a5acfa 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,7 +623,7 @@ static void program_scaler(const struct core_dc *dc, &pipe_ctx->scl_data); } -static enum dc_status prog_pixclk_crtc_otg( +static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, struct core_dc *dc) @@ -641,6 +641,7 @@ static enum dc_status prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, &black_color); + /* * Must blank CRTC after disabling power gating and before any * programming, otherwise CRTC will be hung in bad state @@ -1047,7 +1048,8 @@ static void reset_single_pipe_hw_ctx( struct validate_context *context) { core_link_disable_stream(pipe_ctx); - if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) { + pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); + if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { dm_error("DC: failed to blank crtc!\n"); BREAK_TO_DEBUGGER(); } @@ -1560,9 +1562,6 @@ static void update_plane_addr(const struct core_dc *dc, surface->public.flip_immediate); surface->status.requested_address = surface->public.address; - - if (surface->public.visible) - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false); } void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) @@ -1718,6 +1717,7 @@ static void init_hw(struct core_dc *dc) /* Blank controller using driver code instead of * command table. */ tg->funcs->set_blank(tg, true); + hwss_wait_for_blank_complete(tg); } for (i = 0; i < dc->res_pool->audio_count; i++) { @@ -2002,7 +2002,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_drr = set_drr, .set_static_screen_control = set_static_screen_control, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, - .prog_pixclk_crtc_otg = prog_pixclk_crtc_otg, + .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, }; bool dce110_hw_sequencer_construct(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index e70704d1ba87..f4b8576a0546 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1808,7 +1808,7 @@ bool dce110_tg_is_blanked(struct timing_generator *tg) return false; } -bool dce110_tg_set_blank(struct timing_generator *tg, +void dce110_tg_set_blank(struct timing_generator *tg, bool enable_blanking) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); @@ -1824,8 +1824,6 @@ bool dce110_tg_set_blank(struct timing_generator *tg, value = 0; if (enable_blanking) { - int counter; - set_reg_field_value( value, 1, @@ -1834,32 +1832,8 @@ bool dce110_tg_set_blank(struct timing_generator *tg, dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), value); - for (counter = 0; counter < 100; counter++) { - value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL)); - - if (get_reg_field_value( - value, - CRTC_BLANK_CONTROL, - CRTC_BLANK_DATA_EN) == 1 && - get_reg_field_value( - value, - CRTC_BLANK_CONTROL, - CRTC_CURRENT_BLANK_STATE) == 1) - break; - - msleep(1); - } - - if (counter == 100) { - dm_logger_write(tg->ctx->logger, LOG_ERROR, - "timing generator %d blank timing out.\n", - tg110->controller_id); - return false; - } } else dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), 0); - - return true; } bool dce110_tg_validate_timing(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 39906502ad5c..dcb49fe452c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -257,7 +257,7 @@ void dce110_tg_program_timing(struct timing_generator *tg, bool dce110_tg_is_blanked(struct timing_generator *tg); -bool dce110_tg_set_blank(struct timing_generator *tg, +void dce110_tg_set_blank(struct timing_generator *tg, bool enable_blanking); bool dce110_tg_validate_timing(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 3bf3179e07c5..682a3de7ba48 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -72,12 +72,11 @@ static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) return true; } -static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) +static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t addr = mmCRTCV_BLANK_CONTROL; uint32_t value = dm_read_reg(tg->ctx, addr); - uint8_t counter = 100; set_reg_field_value( value, @@ -92,35 +91,9 @@ static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) CRTC_BLANK_DE_MODE); dm_write_reg(tg->ctx, addr, value); - - while (counter > 0) { - value = dm_read_reg(tg->ctx, addr); - - if (get_reg_field_value( - value, - CRTCV_BLANK_CONTROL, - CRTC_BLANK_DATA_EN) == 1 && - get_reg_field_value( - value, - CRTCV_BLANK_CONTROL, - CRTC_CURRENT_BLANK_STATE) == 1) - break; - - msleep(1); - counter--; - } - - if (!counter) { - dm_logger_write(tg->ctx->logger, LOG_ERROR, - "timing generator %d blank timing out.\n", - tg110->controller_id); - return false; - } - - return true; } -static bool dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg) +static void dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg) { uint32_t addr = mmCRTCV_BLANK_CONTROL; uint32_t value = dm_read_reg(tg->ctx, addr); @@ -138,8 +111,6 @@ static bool dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg) CRTC_BLANK_DE_MODE); dm_write_reg(tg->ctx, addr, value); - - return true; } static bool dce110_timing_generator_v_is_in_vertical_blank( @@ -429,13 +400,13 @@ static void dce110_timing_generator_v_enable_advanced_request( dm_write_reg(tg->ctx, addr, value); } -static bool dce110_timing_generator_v_set_blank(struct timing_generator *tg, +static void dce110_timing_generator_v_set_blank(struct timing_generator *tg, bool enable_blanking) { if (enable_blanking) - return dce110_timing_generator_v_blank_crtc(tg); + dce110_timing_generator_v_blank_crtc(tg); else - return dce110_timing_generator_v_unblank_crtc(tg); + dce110_timing_generator_v_unblank_crtc(tg); } static void dce110_timing_generator_v_program_timing(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 6ac609f6f89f..baa9445833fb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -129,7 +129,7 @@ struct timing_generator_funcs { uint32_t early_cntl); void (*wait_for_state)(struct timing_generator *tg, enum crtc_state state); - bool (*set_blank)(struct timing_generator *tg, + void (*set_blank)(struct timing_generator *tg, bool enable_blanking); bool (*is_blanked)(struct timing_generator *tg); void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 895c446cebf9..562c8978fe9c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -151,4 +151,7 @@ void color_space_to_black_color( enum dc_color_space colorspace, struct tg_color *black_color); +bool hwss_wait_for_blank_complete( + struct timing_generator *tg); + #endif /* __DC_HW_SEQUENCER_H__ */ -- cgit v1.2.3-59-g8ed1b From 00c91d0d480a0c5f6507da80f7e13dab7e6b7c79 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Mon, 9 Jan 2017 16:26:58 -0500 Subject: drm/amd/display: Support 64-bit Polaris11 5k VSR - pass full asic_id info into bw_calc_init instead of only version enum - 64-bit Polaris11 needs an extra microsecond of dmif_urgent_latency - add helper to convert from asic_id.family to bw_calc version enum Signed-off-by: Joshua Aberback Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c | 40 ++++++++++++++++++---- .../drm/amd/display/dc/dce110/dce110_resource.c | 5 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 2 +- 4 files changed, 37 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c index 3b0710ef4716..aa187736b534 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c @@ -27,11 +27,34 @@ #include "bandwidth_calcs.h" #include "dc.h" #include "core_types.h" +#include "dal_asic_id.h" /******************************************************************************* * Private Functions ******************************************************************************/ +static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id) +{ + switch (asic_id.chip_family) { + + case FAMILY_CZ: + if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev)) + return BW_CALCS_VERSION_STONEY; + return BW_CALCS_VERSION_CARRIZO; + + case FAMILY_VI: + if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev)) + // || ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev) + return BW_CALCS_VERSION_POLARIS10; + if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev)) + return BW_CALCS_VERSION_POLARIS11; + return BW_CALCS_VERSION_INVALID; + + default: + return BW_CALCS_VERSION_INVALID; + } +} + static void calculate_bandwidth( const struct bw_calcs_dceip *dceip, const struct bw_calcs_vbios *vbios, @@ -1954,18 +1977,20 @@ static void calculate_bandwidth( ******************************************************************************/ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, struct bw_calcs_vbios *bw_vbios, - enum bw_calcs_version version) + struct hw_asic_id asic_id) { struct bw_calcs_dceip dceip = { 0 }; struct bw_calcs_vbios vbios = { 0 }; + enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id); + dceip.version = version; switch (version) { case BW_CALCS_VERSION_CARRIZO: vbios.memory_type = bw_def_gddr5; vbios.dram_channel_width_in_bits = 64; - vbios.number_of_dram_channels = 2; + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; vbios.number_of_dram_banks = 8; vbios.high_yclk = bw_int_to_fixed(1600); vbios.mid_yclk = bw_int_to_fixed(1600); @@ -2075,7 +2100,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, case BW_CALCS_VERSION_POLARIS10: vbios.memory_type = bw_def_gddr5; vbios.dram_channel_width_in_bits = 32; - vbios.number_of_dram_channels = 8; + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; vbios.number_of_dram_banks = 8; vbios.high_yclk = bw_int_to_fixed(6000); vbios.mid_yclk = bw_int_to_fixed(3200); @@ -2185,7 +2210,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, case BW_CALCS_VERSION_POLARIS11: vbios.memory_type = bw_def_gddr5; vbios.dram_channel_width_in_bits = 32; - vbios.number_of_dram_channels = 4; + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; vbios.number_of_dram_banks = 8; vbios.high_yclk = bw_int_to_fixed(6000); vbios.mid_yclk = bw_int_to_fixed(3200); @@ -2206,7 +2231,10 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, vbios.high_voltage_max_phyclk = bw_int_to_fixed(810); vbios.data_return_bus_width = bw_int_to_fixed(32); vbios.trc = bw_int_to_fixed(48); - vbios.dmifmc_urgent_latency = bw_int_to_fixed(3); + if (vbios.number_of_dram_channels == 2) // 64-bit + vbios.dmifmc_urgent_latency = bw_int_to_fixed(4); + else + vbios.dmifmc_urgent_latency = bw_int_to_fixed(3); vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5); vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0); vbios.nbp_state_change_latency = bw_int_to_fixed(45); @@ -2295,7 +2323,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, case BW_CALCS_VERSION_STONEY: vbios.memory_type = bw_def_gddr5; vbios.dram_channel_width_in_bits = 64; - vbios.number_of_dram_channels = 1; + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; vbios.number_of_dram_banks = 8; vbios.high_yclk = bw_int_to_fixed(1866); vbios.mid_yclk = bw_int_to_fixed(1866); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index ae90da8c1b8c..968ee99003fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1349,10 +1349,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - if (ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev)) - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_STONEY); - else - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO); + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index c63030e9f515..7fca2eb188cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1394,7 +1394,7 @@ static bool construct( if (!dce112_hw_sequencer_construct(dc)) goto res_create_fail; - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_POLARIS11); + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h index f9b871b6199b..16f06fa2d69c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h @@ -483,7 +483,7 @@ struct bw_calcs_output { void bw_calcs_init( struct bw_calcs_dceip *bw_dceip, struct bw_calcs_vbios *bw_vbios, - enum bw_calcs_version version); + struct hw_asic_id asic_id); /** * Return: -- cgit v1.2.3-59-g8ed1b From 624d7c4708b27be2dc095579394efadd80f090dd Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 9 Jan 2017 09:42:33 -0500 Subject: drm/amd/display: Pass visible flag into surface programming Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 ++- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 3 ++- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 ++++-- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h | 3 ++- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 ++- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h | 3 ++- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 3 ++- 7 files changed, 16 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index e9005e0048e6..130935fffba3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -372,7 +372,8 @@ void dce_mem_input_program_surface_config(struct mem_input *mi, union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror) + bool horizontal_mirror, + bool visible) { REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index 022272d30fe4..f90d586656ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -243,7 +243,8 @@ void dce_mem_input_program_surface_config(struct mem_input *mi, union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror); + bool horizontal_mirror, + bool visible); void dce_mem_input_allocate_dmif(struct mem_input *mi, uint32_t h_total, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 965e47a5acfa..751dbb88c265 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1538,7 +1538,8 @@ static void set_plane_config( &surface->public.plane_size, surface->public.rotation, NULL, - false); + false, + pipe_ctx->surface->public.visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( @@ -1877,8 +1878,9 @@ static void dce110_program_front_end_for_pipe( &surface->public.tiling_info, &surface->public.plane_size, surface->public.rotation, + NULL, false, - false); + pipe_ctx->surface->public.visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h index a80a20c09da4..4aec18c94c49 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h @@ -105,7 +105,8 @@ bool dce110_mem_input_program_surface_config( union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror); + bool horizontal_mirror, + bool visible); /* * dce110_mem_input_is_flip_pending diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 757e946d0837..b12506adcba4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -664,7 +664,8 @@ void dce110_mem_input_v_program_surface_config( union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizotal_mirror) + bool horizotal_mirror, + bool visible) { struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h index 5b1796ccefc0..44cf066279c0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h @@ -89,6 +89,7 @@ bool dce110_mem_input_v_program_surface_config( enum surface_pixel_format format, union dc_tiling_info *tiling_info, union plane_size *plane_size, - enum dc_rotation_angle rotation); + enum dc_rotation_angle rotation, + bool visible); #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 2c0774f95c1c..ed980aed1677 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -95,7 +95,8 @@ struct mem_input_funcs { union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror); + bool horizontal_mirror, + bool visible); bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); -- cgit v1.2.3-59-g8ed1b From ab2541b67395088b9de8ebf3943ef9ef86bccc41 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Thu, 29 Dec 2016 15:27:12 -0500 Subject: drm/amd/display: Remove dc_target object dc_target does not fit well into DRM framework so removed it. This will prevent the driver from leveraging the pipe-split code for tiled displays, so will have to be handled at a higher level. Most places that used dc_target now directly use dc_stream instead. Signed-off-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 47 ++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 349 +++++++--------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 292 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 437 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 183 +++++++++ drivers/gpu/drm/amd/display/dc/core/dc_target.c | 333 ---------------- drivers/gpu/drm/amd/display/dc/dc.h | 194 ++++----- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 - .../drm/amd/display/dc/dce100/dce100_resource.c | 89 ++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 103 +++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 144 ++++--- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 89 ++--- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 19 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 13 +- 20 files changed, 977 insertions(+), 1337 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_target.c (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 3a3adfa16ada..0d92126b4c4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -428,8 +428,8 @@ struct amdgpu_crtc { int otg_inst; uint32_t flip_flags; - /* After Set Mode target will be non-NULL */ - struct dc_target *target; + /* After Set Mode stream will be non-NULL */ + const struct dc_stream *stream; }; struct amdgpu_encoder_atom_dig { @@ -550,7 +550,7 @@ struct amdgpu_connector { const struct dc_sink *dc_sink; const struct dc_link *dc_link; const struct dc_sink *dc_em_sink; - const struct dc_target *target; + const struct dc_stream *stream; void *con_priv; bool dac_load_detect; bool detected_by_load; /* if the connection status was determined by load */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2af4ac0bffcb..214cd38b8135 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -68,12 +68,12 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) else { struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; - if (NULL == acrtc->target) { - DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc); + if (NULL == acrtc->stream) { + DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); return 0; } - return dc_target_get_vblank_counter(acrtc->target); + return dc_stream_get_vblank_counter(acrtc->stream); } } @@ -85,12 +85,12 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, else { struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; - if (NULL == acrtc->target) { - DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc); + if (NULL == acrtc->stream) { + DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); return 0; } - return dc_target_get_scanoutpos(acrtc->target, vbl, position); + return dc_stream_get_scanoutpos(acrtc->stream, vbl, position); } return 0; @@ -461,7 +461,7 @@ static int dm_suspend(void *handle) drm_modeset_lock_all(adev->ddev); list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) + if (acrtc->stream) drm_crtc_vblank_off(crtc); } drm_modeset_unlock_all(adev->ddev); @@ -655,7 +655,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) drm_modeset_lock_all(ddev); list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) + if (acrtc->stream) drm_crtc_vblank_on(crtc); } drm_modeset_unlock_all(ddev); @@ -740,7 +740,7 @@ void amdgpu_dm_update_connector_after_detect( if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && aconnector->dc_em_sink) { - /* For S3 resume with headless use eml_sink to fake target + /* For S3 resume with headless use eml_sink to fake stream * because on resume connecotr->sink is set ti NULL */ mutex_lock(&dev->mode_config.mutex); @@ -1184,7 +1184,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) return -1; } - for (i = 0; i < dm->dc->caps.max_targets; i++) { + for (i = 0; i < dm->dc->caps.max_streams; i++) { acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); if (!acrtc) goto fail; @@ -1199,7 +1199,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) } } - dm->display_indexes_num = dm->dc->caps.max_targets; + dm->display_indexes_num = dm->dc->caps.max_streams; /* loops over all connectors on the board */ for (i = 0; i < link_cnt; i++) { @@ -1318,7 +1318,7 @@ static void dm_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) { struct amdgpu_crtc *acrtc; - struct dc_target *target; + const struct dc_stream *stream; struct dc_flip_addrs addr = { {0} }; /* @@ -1336,7 +1336,7 @@ static void dm_page_flip(struct amdgpu_device *adev, * a little longer to lock up all cores. * * The reason we should lock on dal_mutex is so that we can be sure - * nobody messes with acrtc->target after we read and check its value. + * nobody messes with acrtc->stream after we read and check its value. * * We might be able to fix our concurrency issues with a work queue * where we schedule all work items (mode_set, page_flip, etc.) and @@ -1345,14 +1345,14 @@ static void dm_page_flip(struct amdgpu_device *adev, */ acrtc = adev->mode_info.crtcs[crtc_id]; - target = acrtc->target; + stream = acrtc->stream; /* * Received a page flip call after the display has been reset. * Just return in this case. Everything should be clean-up on reset. */ - if (!target) { + if (!stream) { WARN_ON(1); return; } @@ -1368,7 +1368,7 @@ static void dm_page_flip(struct amdgpu_device *adev, dc_flip_surface_addrs( adev->dm.dc, - dc_target_get_status(target)->surfaces, + dc_stream_get_status(stream)->surfaces, &addr, 1); } @@ -1376,25 +1376,22 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, struct drm_file *filp) { struct mod_freesync_params freesync_params; - uint8_t num_targets; + uint8_t num_streams; uint8_t i; - struct dc_target *target; struct amdgpu_device *adev = dev->dev_private; int r = 0; /* Get freesync enable flag from DRM */ - num_targets = dc_get_current_target_count(adev->dm.dc); + num_streams = dc_get_current_stream_count(adev->dm.dc); - for (i = 0; i < num_targets; i++) { - - target = dc_get_target_at_index(adev->dm.dc, i); + for (i = 0; i < num_streams; i++) { + const struct dc_stream *stream; + stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, - target->streams, - target->stream_count, - &freesync_params); + &stream, 1, &freesync_params); } return r; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index e1b5f7d7b6da..c32fc6d26088 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -120,14 +120,14 @@ static void dm_set_cursor( position.x_hotspot = xorigin; position.y_hotspot = yorigin; - if (!dc_target_set_cursor_attributes( - amdgpu_crtc->target, + if (!dc_stream_set_cursor_attributes( + amdgpu_crtc->stream, &attributes)) { DRM_ERROR("DC failed to set cursor attributes\n"); } - if (!dc_target_set_cursor_position( - amdgpu_crtc->target, + if (!dc_stream_set_cursor_position( + amdgpu_crtc->stream, &position)) { DRM_ERROR("DC failed to set cursor position\n"); } @@ -260,10 +260,10 @@ static int dm_crtc_cursor_set( position.y = 0; position.hot_spot_enable = false; - if (amdgpu_crtc->target) { + if (amdgpu_crtc->stream) { /*set cursor visible false*/ - dc_target_set_cursor_position( - amdgpu_crtc->target, + dc_stream_set_cursor_position( + amdgpu_crtc->stream, &position); } /*unpin old cursor buffer and update cache*/ @@ -346,9 +346,9 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, position.x_hotspot = xorigin; position.y_hotspot = yorigin; - if (amdgpu_crtc->target) { - if (!dc_target_set_cursor_position( - amdgpu_crtc->target, + if (amdgpu_crtc->stream) { + if (!dc_stream_set_cursor_position( + amdgpu_crtc->stream, &position)) { DRM_ERROR("DC failed to set cursor position\n"); return -EINVAL; @@ -367,7 +367,7 @@ static void dm_crtc_cursor_reset(struct drm_crtc *crtc) __func__, amdgpu_crtc->cursor_bo); - if (amdgpu_crtc->cursor_bo && amdgpu_crtc->target) { + if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) { dm_set_cursor( amdgpu_crtc, amdgpu_crtc->cursor_addr, @@ -635,7 +635,7 @@ static void update_stream_scaling_settings( struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private; enum amdgpu_rmx_type rmx_type; - struct rect src = { 0 }; /* viewport in target space*/ + struct rect src = { 0 }; /* viewport in composition space*/ struct rect dst = { 0 }; /* stream addressable area */ /* Full screen scaling by default */ @@ -684,11 +684,11 @@ static void dm_dc_surface_commit( struct dc_surface *dc_surface; const struct dc_surface *dc_surfaces[1]; const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct dc_target *dc_target = acrtc->target; + const struct dc_stream *dc_stream = acrtc->stream; - if (!dc_target) { + if (!dc_stream) { dm_error( - "%s: Failed to obtain target on crtc (%d)!\n", + "%s: Failed to obtain stream on crtc (%d)!\n", __func__, acrtc->crtc_id); goto fail; @@ -712,11 +712,11 @@ static void dm_dc_surface_commit( dc_surfaces[0] = dc_surface; - if (false == dc_commit_surfaces_to_target( + if (false == dc_commit_surfaces_to_stream( dc, dc_surfaces, 1, - dc_target)) { + dc_stream)) { dm_error( "%s: Failed to attach surface!\n", __func__); @@ -957,15 +957,14 @@ static void decide_crtc_timing_for_drm_display_mode( } } -static struct dc_target *create_target_for_sink( +static struct dc_stream *create_stream_for_sink( const struct amdgpu_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; const struct drm_connector *drm_connector; - struct dc_target *target = NULL; - struct dc_stream *stream; + struct dc_stream *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -1022,19 +1021,10 @@ static struct dc_target *create_target_for_sink( drm_connector, aconnector->dc_sink); - target = dc_create_target_for_streams(&stream, 1); - dc_stream_release(stream); - - if (NULL == target) { - DRM_ERROR("Failed to create target with streams!\n"); - goto target_create_fail; - } - +stream_create_fail: dm_state_null: drm_connector_null: -target_create_fail: -stream_create_fail: - return target; + return stream; } void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) @@ -1316,8 +1306,7 @@ int amdgpu_dm_connector_mode_valid( struct amdgpu_device *adev = connector->dev->dev_private; struct dc_validation_set val_set = { 0 }; /* TODO: Unhardcode stream count */ - struct dc_stream *streams[1]; - struct dc_target *target; + struct dc_stream *stream; struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || @@ -1335,39 +1324,31 @@ int amdgpu_dm_connector_mode_valid( if (NULL == dc_sink) { DRM_ERROR("dc_sink is NULL!\n"); - goto stream_create_fail; + goto null_sink; } - streams[0] = dc_create_stream_for_sink(dc_sink); - - if (NULL == streams[0]) { + stream = dc_create_stream_for_sink(dc_sink); + if (NULL == stream) { DRM_ERROR("Failed to create stream for sink!\n"); goto stream_create_fail; } drm_mode_set_crtcinfo(mode, 0); - fill_stream_properties_from_drm_display_mode(streams[0], mode, connector); - - target = dc_create_target_for_streams(streams, 1); - val_set.target = target; - - if (NULL == val_set.target) { - DRM_ERROR("Failed to create target with stream!\n"); - goto target_create_fail; - } + fill_stream_properties_from_drm_display_mode(stream, mode, connector); + val_set.stream = stream; val_set.surface_count = 0; - streams[0]->src.width = mode->hdisplay; - streams[0]->src.height = mode->vdisplay; - streams[0]->dst = streams[0]->src; + stream->src.width = mode->hdisplay; + stream->src.height = mode->vdisplay; + stream->dst = stream->src; if (dc_validate_resources(adev->dm.dc, &val_set, 1)) result = MODE_OK; - dc_target_release(target); -target_create_fail: - dc_stream_release(streams[0]); + dc_stream_release(stream); + stream_create_fail: +null_sink: /* TODO: error handling*/ return result; } @@ -1562,15 +1543,14 @@ static void dm_plane_helper_cleanup_fb( } } -int dm_create_validation_set_for_target(struct drm_connector *connector, +int dm_create_validation_set_for_connector(struct drm_connector *connector, struct drm_display_mode *mode, struct dc_validation_set *val_set) { int result = MODE_ERROR; const struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ - struct dc_stream *streams[1]; - struct dc_target *target; + struct dc_stream *stream; if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) @@ -1581,35 +1561,24 @@ int dm_create_validation_set_for_target(struct drm_connector *connector, return result; } - streams[0] = dc_create_stream_for_sink(dc_sink); + stream = dc_create_stream_for_sink(dc_sink); - if (NULL == streams[0]) { + if (NULL == stream) { DRM_ERROR("Failed to create stream for sink!\n"); return result; } drm_mode_set_crtcinfo(mode, 0); - fill_stream_properties_from_drm_display_mode(streams[0], mode, connector); + fill_stream_properties_from_drm_display_mode(stream, mode, connector); - target = dc_create_target_for_streams(streams, 1); - val_set->target = target; + val_set->stream = stream; - if (NULL == val_set->target) { - DRM_ERROR("Failed to create target with stream!\n"); - goto fail; - } - - streams[0]->src.width = mode->hdisplay; - streams[0]->src.height = mode->vdisplay; - streams[0]->dst = streams[0]->src; + stream->src.width = mode->hdisplay; + stream->src.height = mode->vdisplay; + stream->dst = stream->src; return MODE_OK; - -fail: - dc_stream_release(streams[0]); - return result; - } static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { @@ -2262,23 +2231,21 @@ static bool is_scaling_state_different( return false; } -static void remove_target(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) +static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) { - int i; - /* * we evade vblanks and pflips on crtc that * should be changed */ manage_dm_interrupts(adev, acrtc, false); + /* this is the update mode case */ if (adev->dm.freesync_module) - for (i = 0; i < acrtc->target->stream_count; i++) - mod_freesync_remove_stream( - adev->dm.freesync_module, - acrtc->target->streams[i]); - dc_target_release(acrtc->target); - acrtc->target = NULL; + mod_freesync_remove_stream(adev->dm.freesync_module, + acrtc->stream); + + dc_stream_release(acrtc->stream); + acrtc->stream = NULL; acrtc->otg_inst = -1; acrtc->enabled = false; } @@ -2293,20 +2260,20 @@ int amdgpu_dm_atomic_commit( struct drm_plane *plane; struct drm_plane_state *new_plane_state; struct drm_plane_state *old_plane_state; - uint32_t i, j; + uint32_t i; int32_t ret = 0; - uint32_t commit_targets_count = 0; + uint32_t commit_streams_count = 0; uint32_t new_crtcs_count = 0; uint32_t flip_crtcs_count = 0; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; - struct dc_target *commit_targets[MAX_TARGETS]; - struct amdgpu_crtc *new_crtcs[MAX_TARGETS]; - struct dc_target *new_target; - struct drm_crtc *flip_crtcs[MAX_TARGETS]; - struct amdgpu_flip_work *work[MAX_TARGETS] = {0}; - struct amdgpu_bo *new_abo[MAX_TARGETS] = {0}; + const struct dc_stream *commit_streams[MAX_STREAMS]; + struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; + const struct dc_stream *new_stream; + struct drm_crtc *flip_crtcs[MAX_STREAMS]; + struct amdgpu_flip_work *work[MAX_STREAMS] = {0}; + struct amdgpu_bo *new_abo[MAX_STREAMS] = {0}; /* In this step all new fb would be pinned */ @@ -2422,19 +2389,19 @@ int amdgpu_dm_atomic_commit( case DM_COMMIT_ACTION_DPMS_ON: case DM_COMMIT_ACTION_SET: { struct dm_connector_state *dm_state = NULL; - new_target = NULL; + new_stream = NULL; if (aconnector) dm_state = to_dm_connector_state(aconnector->base.state); - new_target = create_target_for_sink( + new_stream = create_stream_for_sink( aconnector, &crtc->state->mode, dm_state); DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); - if (!new_target) { + if (!new_stream) { /* * this could happen because of issues with * userspace notifications delivery. @@ -2450,23 +2417,23 @@ int amdgpu_dm_atomic_commit( * have a sink to keep the pipe running so that * hw state is consistent with the sw state */ - DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n", + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } - if (acrtc->target) - remove_target(adev, acrtc); + if (acrtc->stream) + remove_stream(adev, acrtc); /* * this loop saves set mode crtcs * we needed to enable vblanks once all - * resources acquired in dc after dc_commit_targets + * resources acquired in dc after dc_commit_streams */ new_crtcs[new_crtcs_count] = acrtc; new_crtcs_count++; - acrtc->target = new_target; + acrtc->stream = new_stream; acrtc->enabled = true; acrtc->hw_mode = crtc->state->mode; crtc->hwmode = crtc->state->mode; @@ -2483,10 +2450,8 @@ int amdgpu_dm_atomic_commit( dm_state = to_dm_connector_state(aconnector->base.state); /* Scaling update */ - update_stream_scaling_settings( - &crtc->state->mode, - dm_state, - acrtc->target->streams[0]); + update_stream_scaling_settings(&crtc->state->mode, + dm_state, acrtc->stream); break; } @@ -2494,8 +2459,8 @@ int amdgpu_dm_atomic_commit( case DM_COMMIT_ACTION_RESET: DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); /* i.e. reset mode */ - if (acrtc->target) - remove_target(adev, acrtc); + if (acrtc->stream) + remove_stream(adev, acrtc); break; } /* switch() */ } /* for_each_crtc_in_state() */ @@ -2504,20 +2469,20 @@ int amdgpu_dm_atomic_commit( struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) { - commit_targets[commit_targets_count] = acrtc->target; - ++commit_targets_count; + if (acrtc->stream) { + commit_streams[commit_streams_count] = acrtc->stream; + ++commit_streams_count; } } /* - * Add streams after required streams from new and replaced targets + * Add streams after required streams from new and replaced streams * are removed from freesync module */ if (adev->dm.freesync_module) { for (i = 0; i < new_crtcs_count; i++) { struct amdgpu_connector *aconnector = NULL; - new_target = new_crtcs[i]->target; + new_stream = new_crtcs[i]->stream; aconnector = amdgpu_dm_find_first_crct_matching_connector( state, @@ -2531,22 +2496,20 @@ int amdgpu_dm_atomic_commit( continue; } - for (j = 0; j < new_target->stream_count; j++) - mod_freesync_add_stream( - adev->dm.freesync_module, - new_target->streams[j], &aconnector->caps); + mod_freesync_add_stream(adev->dm.freesync_module, + new_stream, &aconnector->caps); } } - /* DC is optimized not to do anything if 'targets' didn't change. */ - dc_commit_targets(dm->dc, commit_targets, commit_targets_count); + /* DC is optimized not to do anything if 'streams' didn't change. */ + dc_commit_streams(dm->dc, commit_streams, commit_streams_count); list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target != NULL) + if (acrtc->stream != NULL) acrtc->otg_inst = - dc_target_get_status(acrtc->target)->primary_otg_inst; + dc_stream_get_status(acrtc->stream)->primary_otg_inst; } /* update planes when needed */ @@ -2566,7 +2529,7 @@ int amdgpu_dm_atomic_commit( /* Surfaces are created under two scenarios: * 1. This commit is not a page flip. - * 2. This commit is a page flip, and targets are created. + * 2. This commit is a page flip, and streams are created. */ if (!page_flip_needed( plane_state, @@ -2618,13 +2581,9 @@ int amdgpu_dm_atomic_commit( */ struct amdgpu_crtc *acrtc = new_crtcs[i]; - if (adev->dm.freesync_module) { - for (j = 0; j < acrtc->target->stream_count; j++) - mod_freesync_notify_mode_change( - adev->dm.freesync_module, - acrtc->target->streams, - acrtc->target->stream_count); - } + if (adev->dm.freesync_module) + mod_freesync_notify_mode_change( + adev->dm.freesync_module, &acrtc->stream, 1); manage_dm_interrupts(adev, acrtc, true); dm_crtc_cursor_reset(&acrtc->base); @@ -2682,20 +2641,19 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); struct amdgpu_crtc *disconnected_acrtc; const struct dc_sink *sink; - struct dc_target *commit_targets[6]; - struct dc_target *current_target; - uint32_t commit_targets_count = 0; - int i; + const struct dc_stream *commit_streams[MAX_STREAMS]; + const struct dc_stream *current_stream; + uint32_t commit_streams_count = 0; if (!aconnector->dc_sink || !connector->state || !connector->encoder) return; disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); - if (!disconnected_acrtc || !disconnected_acrtc->target) + if (!disconnected_acrtc || !disconnected_acrtc->stream) return; - sink = disconnected_acrtc->target->streams[0]->sink; + sink = disconnected_acrtc->stream->sink; /* * If the previous sink is not released and different from the current, @@ -2706,8 +2664,8 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector struct dm_connector_state *dm_state = to_dm_connector_state(aconnector->base.state); - struct dc_target *new_target = - create_target_for_sink( + struct dc_stream *new_stream = + create_stream_for_sink( aconnector, &disconnected_acrtc->base.state->mode, dm_state); @@ -2720,56 +2678,51 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector manage_dm_interrupts(adev, disconnected_acrtc, false); /* this is the update mode case */ - current_target = disconnected_acrtc->target; + current_stream = disconnected_acrtc->stream; - disconnected_acrtc->target = new_target; + disconnected_acrtc->stream = new_stream; disconnected_acrtc->enabled = true; disconnected_acrtc->hw_mode = disconnected_acrtc->base.state->mode; - commit_targets_count = 0; + commit_streams_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) { - commit_targets[commit_targets_count] = acrtc->target; - ++commit_targets_count; + if (acrtc->stream) { + commit_streams[commit_streams_count] = acrtc->stream; + ++commit_streams_count; } } - /* DC is optimized not to do anything if 'targets' didn't change. */ - if (!dc_commit_targets(dc, commit_targets, - commit_targets_count)) { + /* DC is optimized not to do anything if 'streams' didn't change. */ + if (!dc_commit_streams(dc, commit_streams, + commit_streams_count)) { DRM_INFO("Failed to restore connector state!\n"); - dc_target_release(disconnected_acrtc->target); - disconnected_acrtc->target = current_target; + dc_stream_release(disconnected_acrtc->stream); + disconnected_acrtc->stream = current_stream; manage_dm_interrupts(adev, disconnected_acrtc, true); return; } if (adev->dm.freesync_module) { + mod_freesync_remove_stream(adev->dm.freesync_module, + current_stream); - for (i = 0; i < current_target->stream_count; i++) - mod_freesync_remove_stream( - adev->dm.freesync_module, - current_target->streams[i]); - - for (i = 0; i < new_target->stream_count; i++) - mod_freesync_add_stream( - adev->dm.freesync_module, - new_target->streams[i], - &aconnector->caps); + mod_freesync_add_stream(adev->dm.freesync_module, + new_stream, &aconnector->caps); } + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target != NULL) { + if (acrtc->stream != NULL) { acrtc->otg_inst = - dc_target_get_status(acrtc->target)->primary_otg_inst; + dc_stream_get_status(acrtc->stream)->primary_otg_inst; } } - dc_target_release(current_target); + dc_stream_release(current_stream); dm_dc_surface_commit(dc, &disconnected_acrtc->base); @@ -2782,13 +2735,13 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_target *target, + const struct dc_stream *stream, const struct dc_surface *surface) { uint32_t i = 0; while (i < set_count) { - if (val_sets[i].target == target) + if (val_sets[i].stream == stream) break; ++i; } @@ -2799,23 +2752,23 @@ static uint32_t add_val_sets_surface( return val_sets[i].surface_count; } -static uint32_t update_in_val_sets_target( +static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, struct drm_crtc **crtcs, uint32_t set_count, - const struct dc_target *old_target, - const struct dc_target *new_target, + const struct dc_stream *old_stream, + const struct dc_stream *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; while (i < set_count) { - if (val_sets[i].target == old_target) + if (val_sets[i].stream == old_stream) break; ++i; } - val_sets[i].target = new_target; + val_sets[i].stream = new_stream; crtcs[i] = crtc; if (i == set_count) { @@ -2829,12 +2782,12 @@ static uint32_t update_in_val_sets_target( static uint32_t remove_from_val_sets( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_target *target) + const struct dc_stream *stream) { int i; for (i = 0; i < set_count; i++) - if (val_sets[i].target == target) + if (val_sets[i].stream == stream) break; if (i == set_count) { @@ -2861,10 +2814,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, int i, j; int ret; int set_count; - int new_target_count; - struct dc_validation_set set[MAX_TARGETS] = {{ 0 }}; - struct dc_target *new_targets[MAX_TARGETS] = { 0 }; - struct drm_crtc *crtc_set[MAX_TARGETS] = { 0 }; + int new_stream_count; + struct dc_validation_set set[MAX_STREAMS] = {{ 0 }}; + struct dc_stream *new_streams[MAX_STREAMS] = { 0 }; + struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 }; struct amdgpu_device *adev = dev->dev_private; struct dc *dc = adev->dm.dc; bool need_to_validate = false; @@ -2880,14 +2833,14 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, ret = -EINVAL; /* copy existing configuration */ - new_target_count = 0; + new_stream_count = 0; set_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) { - set[set_count].target = acrtc->target; + if (acrtc->stream) { + set[set_count].stream = acrtc->stream; crtc_set[set_count] = crtc; ++set_count; } @@ -2908,7 +2861,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, switch (action) { case DM_COMMIT_ACTION_DPMS_ON: case DM_COMMIT_ACTION_SET: { - struct dc_target *new_target = NULL; + struct dc_stream *new_stream = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_state = NULL; @@ -2919,30 +2872,30 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dm_state = to_dm_connector_state(conn_state); } - new_target = create_target_for_sink(aconnector, &crtc_state->mode, dm_state); + new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state); /* - * we can have no target on ACTION_SET if a display + * we can have no stream on ACTION_SET if a display * was disconnected during S3, in this case it not and * error, the OS will be updated after detection, and * do the right thing on next atomic commit */ - if (!new_target) { - DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n", + if (!new_stream) { + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } - new_targets[new_target_count] = new_target; - set_count = update_in_val_sets_target( + new_streams[new_stream_count] = new_stream; + set_count = update_in_val_sets_stream( set, crtc_set, set_count, - acrtc->target, - new_target, + acrtc->stream, + new_stream, crtc); - new_target_count++; + new_stream_count++; need_to_validate = true; break; } @@ -2952,7 +2905,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_state = NULL; struct dm_connector_state *old_dm_state = NULL; - struct dc_target *new_target; + struct dc_stream *new_stream; if (!aconnector) break; @@ -2970,24 +2923,24 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (!is_scaling_state_different(dm_state, old_dm_state)) break; - new_target = create_target_for_sink(aconnector, &crtc_state->mode, dm_state); + new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state); - if (!new_target) { - DRM_ERROR("%s: Failed to create new target for crtc %d\n", + if (!new_stream) { + DRM_ERROR("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } - new_targets[new_target_count] = new_target; - set_count = update_in_val_sets_target( + new_streams[new_stream_count] = new_stream; + set_count = update_in_val_sets_stream( set, crtc_set, set_count, - acrtc->target, - new_target, + acrtc->stream, + new_stream, crtc); - new_target_count++; + new_stream_count++; need_to_validate = true; break; @@ -2995,11 +2948,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, case DM_COMMIT_ACTION_DPMS_OFF: case DM_COMMIT_ACTION_RESET: /* i.e. reset mode */ - if (acrtc->target) { + if (acrtc->stream) { set_count = remove_from_val_sets( set, set_count, - acrtc->target); + acrtc->stream); } break; } @@ -3035,7 +2988,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, /* Surfaces are created under two scenarios: * 1. This commit is not a page flip. - * 2. This commit is a page flip, and targets are created. + * 2. This commit is a page flip, and streams are created. */ crtc_state = drm_atomic_get_crtc_state(state, crtc); if (!page_flip_needed(plane_state, old_plane_state, @@ -3080,7 +3033,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, add_val_sets_surface( set, set_count, - set[i].target, + set[i].stream, surface); need_to_validate = true; @@ -3097,8 +3050,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dc_surface_release(set[i].surfaces[j]); } } - for (i = 0; i < new_target_count; i++) - dc_target_release(new_targets[i]); + for (i = 0; i < new_stream_count; i++) + dc_stream_release(new_streams[i]); if (ret != 0) DRM_ERROR("Atomic check failed.\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 4f7bd3bae44e..6ed1480a8bc3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -59,7 +59,7 @@ int amdgpu_dm_atomic_commit( int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); -int dm_create_validation_set_for_target( +int dm_create_validation_set_for_stream( struct drm_connector *connector, struct drm_display_mode *mode, struct dc_validation_set *val_set); diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 26e2b50e4954..2df163bc83e9 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -13,7 +13,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI include $(AMD_DC) -DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_target.o dc_sink.o \ +DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE)) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a7348573ebca..7d4299b9ee1f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -49,15 +49,6 @@ #include "dm_helpers.h" #include "mem_input.h" -/******************************************************************************* - * Private structures - ******************************************************************************/ - -struct dc_target_sync_report { - uint32_t h_count; - uint32_t v_count; -}; - /******************************************************************************* * Private functions ******************************************************************************/ @@ -221,7 +212,7 @@ static void stream_update_scaling( struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(dc); struct validate_context *cur_ctx = core_dc->current_context; - int i, j; + int i; if (src) stream->public.src = *src; @@ -229,20 +220,18 @@ static void stream_update_scaling( if (dst) stream->public.dst = *dst; - for (i = 0; i < cur_ctx->target_count; i++) { - struct core_target *target = cur_ctx->targets[i]; - struct dc_target_status *status = &cur_ctx->target_status[i]; + for (i = 0; i < cur_ctx->stream_count; i++) { + struct core_stream *cur_stream = cur_ctx->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - if (target->public.streams[j] != dc_stream) - continue; + if (stream == cur_stream) { + struct dc_stream_status *status = &cur_ctx->stream_status[i]; if (status->surface_count) - if (!dc_commit_surfaces_to_target( + if (!dc_commit_surfaces_to_stream( &core_dc->public, status->surfaces, status->surface_count, - &target->public)) + &cur_stream->public)) /* Need to debug validation */ BREAK_TO_DEBUGGER(); @@ -634,7 +623,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) full_pipe_count = core_dc->res_pool->pipe_count; if (core_dc->res_pool->underlay_pipe_index >= 0) full_pipe_count--; - core_dc->public.caps.max_targets = min( + core_dc->public.caps.max_streams = min( full_pipe_count, core_dc->res_pool->stream_enc_count); @@ -675,20 +664,20 @@ static bool is_validation_required( const struct validate_context *context = dc->current_context; int i, j; - if (context->target_count != set_count) + if (context->stream_count != set_count) return true; for (i = 0; i < set_count; i++) { - if (set[i].surface_count != context->target_status[i].surface_count) + if (set[i].surface_count != context->stream_status[i].surface_count) return true; - if (!is_target_unchanged(DC_TARGET_TO_CORE(set[i].target), context->targets[i])) + if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) return true; for (j = 0; j < set[i].surface_count; j++) { struct dc_surface temp_surf = { 0 }; - temp_surf = *context->target_status[i].surfaces[j]; + temp_surf = *context->stream_status[i].surfaces[j]; temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; @@ -737,7 +726,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_target *dc_target) + const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -748,7 +737,7 @@ bool dc_validate_guaranteed( goto context_alloc_fail; result = core_dc->res_pool->funcs->validate_guaranteed( - core_dc, dc_target, context); + core_dc, stream, context); resource_validate_ctx_destruct(context); dm_free(context); @@ -838,18 +827,18 @@ static void program_timing_sync( } } -static bool targets_changed( +static bool streams_changed( struct core_dc *dc, - struct dc_target *targets[], - uint8_t target_count) + const struct dc_stream *streams[], + uint8_t stream_count) { uint8_t i; - if (target_count != dc->current_context->target_count) + if (stream_count != dc->current_context->stream_count) return true; - for (i = 0; i < dc->current_context->target_count; i++) { - if (&dc->current_context->targets[i]->public != targets[i]) + for (i = 0; i < dc->current_context->stream_count; i++) { + if (&dc->current_context->streams[i]->public != streams[i]) return true; } @@ -860,74 +849,72 @@ static void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg) { - uint8_t i, j, k; - uint8_t num_cfgs = 0; - - for (i = 0; i < context->target_count; i++) { - const struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - const struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct dm_pp_single_disp_config *cfg = - &pp_display_cfg->disp_configs[num_cfgs]; - const struct pipe_ctx *pipe_ctx = NULL; - - for (k = 0; k < MAX_PIPES; k++) - if (stream == - context->res_ctx.pipe_ctx[k].stream) { - pipe_ctx = &context->res_ctx.pipe_ctx[k]; - break; - } + int j; + int num_cfgs = 0; - ASSERT(pipe_ctx != NULL); - - num_cfgs++; - cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->pipe_idx; - cfg->src_height = stream->public.src.height; - cfg->src_width = stream->public.src.width; - cfg->ddi_channel_mapping = - stream->sink->link->ddi_channel_mapping.raw; - cfg->transmitter = - stream->sink->link->link_enc->transmitter; - cfg->link_settings.lane_count = stream->sink->link->public.cur_link_settings.lane_count; - cfg->link_settings.link_rate = stream->sink->link->public.cur_link_settings.link_rate; - cfg->link_settings.link_spread = stream->sink->link->public.cur_link_settings.link_spread; - cfg->sym_clock = stream->phy_pix_clk; - /* Round v_refresh*/ - cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; - cfg->v_refresh /= stream->public.timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) - / stream->public.timing.v_total; - } + for (j = 0; j < context->stream_count; j++) { + int k; + + const struct core_stream *stream = context->streams[j]; + struct dm_pp_single_disp_config *cfg = + &pp_display_cfg->disp_configs[num_cfgs]; + const struct pipe_ctx *pipe_ctx = NULL; + + for (k = 0; k < MAX_PIPES; k++) + if (stream == context->res_ctx.pipe_ctx[k].stream) { + pipe_ctx = &context->res_ctx.pipe_ctx[k]; + break; + } + + ASSERT(pipe_ctx != NULL); + + num_cfgs++; + cfg->signal = pipe_ctx->stream->signal; + cfg->pipe_idx = pipe_ctx->pipe_idx; + cfg->src_height = stream->public.src.height; + cfg->src_width = stream->public.src.width; + cfg->ddi_channel_mapping = + stream->sink->link->ddi_channel_mapping.raw; + cfg->transmitter = + stream->sink->link->link_enc->transmitter; + cfg->link_settings.lane_count = + stream->sink->link->public.cur_link_settings.lane_count; + cfg->link_settings.link_rate = + stream->sink->link->public.cur_link_settings.link_rate; + cfg->link_settings.link_spread = + stream->sink->link->public.cur_link_settings.link_spread; + cfg->sym_clock = stream->phy_pix_clk; + /* Round v_refresh*/ + cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; + cfg->v_refresh /= stream->public.timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) + / stream->public.timing.v_total; } + pp_display_cfg->display_count = num_cfgs; } static uint32_t get_min_vblank_time_us(const struct validate_context *context) { - uint8_t i, j; + uint8_t j; uint32_t min_vertical_blank_time = -1; - for (i = 0; i < context->target_count; i++) { - const struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - const struct dc_stream *stream = - target->public.streams[j]; + for (j = 0; j < context->stream_count; j++) { + const struct dc_stream *stream = &context->streams[j]->public; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; vertical_blank_in_pixels = stream->timing.h_total * (stream->timing.v_total - stream->timing.v_addressable); + vertical_blank_time = vertical_blank_in_pixels * 1000 / stream->timing.pix_clk_khz; + if (min_vertical_blank_time > vertical_blank_time) min_vertical_blank_time = vertical_blank_time; } - } + return min_vertical_blank_time; } @@ -995,7 +982,7 @@ void pplib_apply_display_requirements( /* TODO: is this still applicable?*/ if (pp_display_cfg->display_count == 1) { const struct dc_crtc_timing *timing = - &context->targets[0]->public.streams[0]->timing; + &context->streams[0]->public.timing; pp_display_cfg->crtc_index = pp_display_cfg->disp_configs[0].pipe_idx; @@ -1011,34 +998,32 @@ void pplib_apply_display_requirements( } -bool dc_commit_targets( +bool dc_commit_streams( struct dc *dc, - struct dc_target *targets[], - uint8_t target_count) + const struct dc_stream *streams[], + uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_bios *dcb = core_dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; - struct dc_validation_set set[MAX_TARGETS]; + struct dc_validation_set set[MAX_STREAMS]; int i, j, k; - if (false == targets_changed(core_dc, targets, target_count)) + if (false == streams_changed(core_dc, streams, stream_count)) return DC_OK; - dm_logger_write(core_dc->ctx->logger, LOG_DC, - "%s: %d targets\n", - __func__, - target_count); + dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n", + __func__, stream_count); - for (i = 0; i < target_count; i++) { - struct dc_target *target = targets[i]; + for (i = 0; i < stream_count; i++) { + const struct dc_stream *stream = streams[i]; - dc_target_log(target, + dc_stream_log(stream, core_dc->ctx->logger, LOG_DC); - set[i].target = targets[i]; + set[i].stream = stream; set[i].surface_count = 0; } @@ -1047,7 +1032,7 @@ bool dc_commit_targets( if (context == NULL) goto context_alloc_fail; - result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, target_count, context); + result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, stream_count, context); if (result != DC_OK){ dm_logger_write(core_dc->ctx->logger, LOG_ERROR, "%s: Context validation failed! dc_status:%d\n", @@ -1068,13 +1053,12 @@ bool dc_commit_targets( program_timing_sync(core_dc, context); - for (i = 0; i < context->target_count; i++) { - struct dc_target *dc_target = &context->targets[i]->public; - struct core_sink *sink = DC_SINK_TO_CORE(dc_target->streams[0]->sink); + for (i = 0; i < context->stream_count; i++) { + const struct core_sink *sink = context->streams[i]->sink; - for (j = 0; j < context->target_status[i].surface_count; j++) { + for (j = 0; j < context->stream_status[i].surface_count; j++) { const struct dc_surface *dc_surface = - context->target_status[i].surfaces[j]; + context->stream_status[i].surfaces[j]; for (k = 0; k < context->res_ctx.pool->pipe_count; k++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[k]; @@ -1088,11 +1072,11 @@ bool dc_commit_targets( } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", - dc_target->streams[0]->timing.h_addressable, - dc_target->streams[0]->timing.v_addressable, - dc_target->streams[0]->timing.h_total, - dc_target->streams[0]->timing.v_total, - dc_target->streams[0]->timing.pix_clk_khz); + context->streams[i]->public.timing.h_addressable, + context->streams[i]->public.timing.v_addressable, + context->streams[i]->public.timing.h_total, + context->streams[i]->public.timing.v_total, + context->streams[i]->public.timing.pix_clk_khz); } pplib_apply_display_requirements(core_dc, @@ -1116,43 +1100,42 @@ context_alloc_fail: return (result == DC_OK); } -bool dc_pre_update_surfaces_to_target( +bool dc_pre_update_surfaces_to_stream( struct dc *dc, const struct dc_surface *const *new_surfaces, uint8_t new_surface_count, - struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i, j; struct core_dc *core_dc = DC_TO_CORE(dc); uint32_t prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct dc_target_status *target_status = NULL; + struct dc_stream_status *stream_status = NULL; struct validate_context *context; struct validate_context *temp_context; bool ret = true; pre_surface_trace(dc, new_surfaces, new_surface_count); - if (core_dc->current_context->target_count == 0) + if (core_dc->current_context->stream_count == 0) return false; - /* Cannot commit surface to a target that is not commited */ - for (i = 0; i < core_dc->current_context->target_count; i++) - if (target == core_dc->current_context->targets[i]) + /* Cannot commit surface to a stream that is not commited */ + for (i = 0; i < core_dc->current_context->stream_count; i++) + if (dc_stream == &core_dc->current_context->streams[i]->public) break; - if (i == core_dc->current_context->target_count) + if (i == core_dc->current_context->stream_count) return false; - target_status = &core_dc->current_context->target_status[i]; + stream_status = &core_dc->current_context->stream_status[i]; - if (new_surface_count == target_status->surface_count) { + if (new_surface_count == stream_status->surface_count) { bool skip_pre = true; - for (i = 0; i < target_status->surface_count; i++) { + for (i = 0; i < stream_status->surface_count; i++) { struct dc_surface temp_surf = { 0 }; - temp_surf = *target_status->surfaces[i]; + temp_surf = *stream_status->surfaces[i]; temp_surf.clip_rect = new_surfaces[i]->clip_rect; temp_surf.dst_rect.x = new_surfaces[i]->dst_rect.x; temp_surf.dst_rect.y = new_surfaces[i]->dst_rect.y; @@ -1178,13 +1161,13 @@ bool dc_pre_update_surfaces_to_target( resource_validate_ctx_copy_construct(core_dc->current_context, context); dm_logger_write(core_dc->ctx->logger, LOG_DC, - "%s: commit %d surfaces to target 0x%x\n", + "%s: commit %d surfaces to stream 0x%x\n", __func__, new_surface_count, - dc_target); + dc_stream); if (!resource_attach_surfaces_to_context( - new_surfaces, new_surface_count, dc_target, context)) { + new_surfaces, new_surface_count, dc_stream, context)) { BREAK_TO_DEBUGGER(); ret = false; goto unexpected_fail; @@ -1256,7 +1239,7 @@ val_ctx_fail: return ret; } -bool dc_post_update_surfaces_to_target(struct dc *dc) +bool dc_post_update_surfaces_to_stream(struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); int i; @@ -1282,22 +1265,27 @@ bool dc_post_update_surfaces_to_target(struct dc *dc) return true; } -bool dc_commit_surfaces_to_target( +bool dc_commit_surfaces_to_stream( struct dc *dc, const struct dc_surface **new_surfaces, uint8_t new_surface_count, - struct dc_target *dc_target) + const struct dc_stream *dc_stream) { - struct dc_surface_update updates[MAX_SURFACES] = { 0 }; - struct dc_flip_addrs flip_addr[MAX_SURFACES] = { 0 }; - struct dc_plane_info plane_info[MAX_SURFACES] = { 0 }; - struct dc_scaling_info scaling_info[MAX_SURFACES] = { 0 }; + struct dc_surface_update updates[MAX_SURFACES]; + struct dc_flip_addrs flip_addr[MAX_SURFACES]; + struct dc_plane_info plane_info[MAX_SURFACES]; + struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; - if (!dc_pre_update_surfaces_to_target( - dc, new_surfaces, new_surface_count, dc_target)) + if (!dc_pre_update_surfaces_to_stream( + dc, new_surfaces, new_surface_count, dc_stream)) return false; + memset(updates, 0, sizeof(updates)); + memset(flip_addr, 0, sizeof(flip_addr)); + memset(plane_info, 0, sizeof(plane_info)); + memset(scaling_info, 0, sizeof(scaling_info)); + for (i = 0; i < new_surface_count; i++) { updates[i].surface = new_surfaces[i]; updates[i].gamma = @@ -1321,13 +1309,13 @@ bool dc_commit_surfaces_to_target( updates[i].plane_info = &plane_info[i]; updates[i].scaling_info = &scaling_info[i]; } - dc_update_surfaces_for_target(dc, updates, new_surface_count, dc_target); + dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream); - return dc_post_update_surfaces_to_target(dc); + return dc_post_update_surfaces_to_stream(dc); } -void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *updates, - int surface_count, struct dc_target *dc_target) +void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, + int surface_count, const struct dc_stream *dc_stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct validate_context *context = core_dc->temp_flip_context; @@ -1377,21 +1365,21 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda can_skip_context_building = false; } - if (!can_skip_context_building && dc_target) { - struct core_target *target = DC_TARGET_TO_CORE(dc_target); + if (!can_skip_context_building && dc_stream) { + const struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); - if (core_dc->current_context->target_count == 0) + if (core_dc->current_context->stream_count == 0) return; - /* Cannot commit surface to a target that is not commited */ - for (i = 0; i < core_dc->current_context->target_count; i++) - if (target == core_dc->current_context->targets[i]) + /* Cannot commit surface to a stream that is not commited */ + for (i = 0; i < core_dc->current_context->stream_count; i++) + if (stream == core_dc->current_context->streams[i]) break; - if (i == core_dc->current_context->target_count) + if (i == core_dc->current_context->stream_count) return; if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, dc_target, context)) { + new_surfaces, surface_count, dc_stream, context)) { BREAK_TO_DEBUGGER(); return; } @@ -1578,17 +1566,17 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda core_dc->current_context = context; } -uint8_t dc_get_current_target_count(const struct dc *dc) +uint8_t dc_get_current_stream_count(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - return core_dc->current_context->target_count; + return core_dc->current_context->stream_count; } -struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i) +struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); - if (i < core_dc->current_context->target_count) - return &(core_dc->current_context->targets[i]->public); + if (i < core_dc->current_context->stream_count) + return &(core_dc->current_context->streams[i]->public); return NULL; } @@ -1687,8 +1675,8 @@ void dc_set_power_state( core_dc->hwss.init_hw(core_dc); break; default: - /* NULL means "reset/release all DC targets" */ - dc_commit_targets(dc, NULL, 0); + /* NULL means "reset/release all DC streams" */ + dc_commit_streams(dc, NULL, 0); core_dc->hwss.power_down(core_dc); @@ -1882,11 +1870,3 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink } } -const struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream) -{ - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); - - return &stream->status; -} - diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4bb6b1d9c970..1f87b948678b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -591,12 +591,12 @@ enum dc_status resource_build_scaling_params_for_context( return DC_OK; } -static void detach_surfaces_for_target( +static void detach_surfaces_for_stream( struct validate_context *context, - const struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_target->streams[0]); + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; @@ -646,15 +646,15 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( } /* - * A free_pipe for a target is defined here as a pipe with a stream that belongs - * to the target but has no surface attached yet + * A free_pipe for a stream is defined here as a pipe + * that has no surface attached yet */ -static struct pipe_ctx *acquire_free_pipe_for_target( +static struct pipe_ctx *acquire_free_pipe_for_stream( struct resource_context *res_ctx, - const struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_target->streams[0]); + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -688,12 +688,12 @@ static struct pipe_ctx *acquire_free_pipe_for_target( } -static void release_free_pipes_for_target( +static void release_free_pipes_for_stream( struct resource_context *res_ctx, - const struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_target->streams[0]); + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && @@ -706,12 +706,12 @@ static void release_free_pipes_for_target( bool resource_attach_surfaces_to_context( const struct dc_surface * const *surfaces, int surface_count, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { int i; struct pipe_ctx *tail_pipe; - struct dc_target_status *target_status = NULL; + struct dc_stream_status *stream_status = NULL; if (surface_count > MAX_SURFACE_NUM) { @@ -720,13 +720,13 @@ bool resource_attach_surfaces_to_context( return false; } - for (i = 0; i < context->target_count; i++) - if (&context->targets[i]->public == dc_target) { - target_status = &context->target_status[i]; + for (i = 0; i < context->stream_count; i++) + if (&context->streams[i]->public == dc_stream) { + stream_status = &context->stream_status[i]; break; } - if (target_status == NULL) { - dm_error("Existing target not found; failed to attach surfaces\n"); + if (stream_status == NULL) { + dm_error("Existing stream not found; failed to attach surfaces\n"); return false; } @@ -734,16 +734,16 @@ bool resource_attach_surfaces_to_context( for (i = 0; i < surface_count; i++) dc_surface_retain(surfaces[i]); - detach_surfaces_for_target(context, dc_target); + detach_surfaces_for_stream(context, dc_stream); /* release existing surfaces*/ - for (i = 0; i < target_status->surface_count; i++) - dc_surface_release(target_status->surfaces[i]); + for (i = 0; i < stream_status->surface_count; i++) + dc_surface_release(stream_status->surfaces[i]); - for (i = surface_count; i < target_status->surface_count; i++) - target_status->surfaces[i] = NULL; + for (i = surface_count; i < stream_status->surface_count; i++) + stream_status->surfaces[i] = NULL; - target_status->surface_count = 0; + stream_status->surface_count = 0; if (surface_count == 0) return true; @@ -751,11 +751,11 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); - struct pipe_ctx *free_pipe = acquire_free_pipe_for_target( - &context->res_ctx, dc_target); + struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( + &context->res_ctx, dc_stream); if (!free_pipe) { - target_status->surfaces[i] = NULL; + stream_status->surfaces[i] = NULL; return false; } @@ -769,13 +769,13 @@ bool resource_attach_surfaces_to_context( tail_pipe = free_pipe; } - release_free_pipes_for_target(&context->res_ctx, dc_target); + release_free_pipes_for_stream(&context->res_ctx, dc_stream); /* assign new surfaces*/ for (i = 0; i < surface_count; i++) - target_status->surfaces[i] = surfaces[i]; + stream_status->surfaces[i] = surfaces[i]; - target_status->surface_count = surface_count; + stream_status->surface_count = surface_count; return true; } @@ -819,25 +819,14 @@ static bool are_stream_backends_same( return true; } -bool is_target_unchanged( - const struct core_target *old_target, const struct core_target *target) +bool is_stream_unchanged( + const struct core_stream *old_stream, const struct core_stream *stream) { - int i; - - if (old_target == target) + if (old_stream == stream) return true; - if (old_target->public.stream_count != target->public.stream_count) - return false; - - for (i = 0; i < old_target->public.stream_count; i++) { - const struct core_stream *old_stream = DC_STREAM_TO_CORE( - old_target->public.streams[i]); - const struct core_stream *stream = DC_STREAM_TO_CORE( - target->public.streams[i]); - if (!are_stream_backends_same(old_stream, stream)) - return false; - } + if (!are_stream_backends_same(old_stream, stream)) + return false; return true; } @@ -851,23 +840,23 @@ bool resource_validate_attach_surfaces( int i, j; for (i = 0; i < set_count; i++) { - for (j = 0; j < old_context->target_count; j++) - if (is_target_unchanged( - old_context->targets[j], - context->targets[i])) { + for (j = 0; j < old_context->stream_count; j++) + if (is_stream_unchanged( + old_context->streams[j], + context->streams[i])) { if (!resource_attach_surfaces_to_context( - old_context->target_status[j].surfaces, - old_context->target_status[j].surface_count, - &context->targets[i]->public, + old_context->stream_status[j].surfaces, + old_context->stream_status[j].surface_count, + &context->streams[i]->public, context)) return false; - context->target_status[i] = old_context->target_status[j]; + context->stream_status[i] = old_context->stream_status[j]; } if (set[i].surface_count != 0) if (!resource_attach_surfaces_to_context( set[i].surfaces, set[i].surface_count, - &context->targets[i]->public, + &context->streams[i]->public, context)) return false; @@ -1001,20 +990,15 @@ static void update_stream_signal(struct core_stream *stream) } bool resource_is_stream_unchanged( - const struct validate_context *old_context, struct core_stream *stream) + const struct validate_context *old_context, const struct core_stream *stream) { - int i, j; - - for (i = 0; i < old_context->target_count; i++) { - struct core_target *old_target = old_context->targets[i]; + int i; - for (j = 0; j < old_target->public.stream_count; j++) { - struct core_stream *old_stream = - DC_STREAM_TO_CORE(old_target->public.streams[j]); + for (i = 0; i < old_context->stream_count; i++) { + const struct core_stream *old_stream = old_context->streams[i]; - if (are_stream_backends_same(old_stream, stream)) + if (are_stream_backends_same(old_stream, stream)) return true; - } } return false; @@ -1036,23 +1020,19 @@ static struct core_stream *find_pll_sharable_stream( const struct core_stream *stream_needs_pll, struct validate_context *context) { - int i, j; + int i; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream_has_pll = context->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream_has_pll = - DC_STREAM_TO_CORE(target->public.streams[j]); + /* We are looking for non dp, non virtual stream */ + if (resource_are_streams_timing_synchronizable( + stream_needs_pll, stream_has_pll) + && !dc_is_dp_signal(stream_has_pll->signal) + && stream_has_pll->sink->link->public.connector_signal + != SIGNAL_TYPE_VIRTUAL) + return stream_has_pll; - /* We are looking for non dp, non virtual stream */ - if (resource_are_streams_timing_synchronizable( - stream_needs_pll, stream_has_pll) - && !dc_is_dp_signal(stream_has_pll->signal) - && stream_has_pll->sink->link->public.connector_signal - != SIGNAL_TYPE_VIRTUAL) - return stream_has_pll; - } } return NULL; @@ -1091,25 +1071,20 @@ static void calculate_phy_pix_clks( const struct core_dc *dc, struct validate_context *context) { - int i, j; - - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + int i; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; - update_stream_signal(stream); + update_stream_signal(stream); - /* update actual pixel clock on all streams */ - if (dc_is_hdmi_signal(stream->signal)) - stream->phy_pix_clk = get_norm_pix_clk( - &stream->public.timing); - else - stream->phy_pix_clk = - stream->public.timing.pix_clk_khz; - } + /* update actual pixel clock on all streams */ + if (dc_is_hdmi_signal(stream->signal)) + stream->phy_pix_clk = get_norm_pix_clk( + &stream->public.timing); + else + stream->phy_pix_clk = + stream->public.timing.pix_clk_khz; } } @@ -1117,136 +1092,122 @@ enum dc_status resource_map_pool_resources( const struct core_dc *dc, struct validate_context *context) { - int i, j, k; + int i, j; calculate_phy_pix_clks(dc, context); - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - - if (!resource_is_stream_unchanged(dc->current_context, stream)) - continue; - - /* mark resources used for stream that is already active */ - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; - const struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[k]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; - if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) - continue; + if (!resource_is_stream_unchanged(dc->current_context, stream)) + continue; - pipe_ctx->stream = stream; - copy_pipe_ctx(old_pipe_ctx, pipe_ctx); + /* mark resources used for stream that is already active */ + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; + const struct pipe_ctx *old_pipe_ctx = + &dc->current_context->res_ctx.pipe_ctx[j]; - /* Split pipe resource, do not acquire back end */ - if (!pipe_ctx->stream_enc) - continue; + if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) + continue; - set_stream_engine_in_use( - &context->res_ctx, - pipe_ctx->stream_enc); - - /* Switch to dp clock source only if there is - * no non dp stream that shares the same timing - * with the dp stream. - */ - if (dc_is_dp_signal(pipe_ctx->stream->signal) && - !find_pll_sharable_stream(stream, context)) - pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; + pipe_ctx->stream = stream; + copy_pipe_ctx(old_pipe_ctx, pipe_ctx); - resource_reference_clock_source( - &context->res_ctx, - pipe_ctx->clock_source); + /* Split pipe resource, do not acquire back end */ + if (!pipe_ctx->stream_enc) + continue; - set_audio_in_use(&context->res_ctx, - pipe_ctx->audio); - } + set_stream_engine_in_use( + &context->res_ctx, + pipe_ctx->stream_enc); + + /* Switch to dp clock source only if there is + * no non dp stream that shares the same timing + * with the dp stream. + */ + if (dc_is_dp_signal(pipe_ctx->stream->signal) && + !find_pll_sharable_stream(stream, context)) + pipe_ctx->clock_source = + context->res_ctx.pool->dp_clock_source; + + resource_reference_clock_source( + &context->res_ctx, + pipe_ctx->clock_source); + + set_audio_in_use(&context->res_ctx, + pipe_ctx->audio); } } - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct pipe_ctx *pipe_ctx = NULL; - int pipe_idx = -1; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; - /* acquire new resources */ - pipe_idx = acquire_first_free_pipe( - &context->res_ctx, stream); - if (pipe_idx < 0) - return DC_NO_CONTROLLER_RESOURCE; - - - pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct pipe_ctx *pipe_ctx = NULL; + int pipe_idx = -1; - pipe_ctx->stream_enc = - find_first_free_match_stream_enc_for_link( - &context->res_ctx, stream); - - if (!pipe_ctx->stream_enc) - return DC_NO_STREAM_ENG_RESOURCE; - - set_stream_engine_in_use( + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; + /* acquire new resources */ + pipe_idx = acquire_first_free_pipe(&context->res_ctx, stream); + if (pipe_idx < 0) + return DC_NO_CONTROLLER_RESOURCE; + + + pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + + pipe_ctx->stream_enc = + find_first_free_match_stream_enc_for_link( + &context->res_ctx, stream); + + if (!pipe_ctx->stream_enc) + return DC_NO_STREAM_ENG_RESOURCE; + + set_stream_engine_in_use( + &context->res_ctx, + pipe_ctx->stream_enc); + + /* TODO: Add check if ASIC support and EDID audio */ + if (!stream->sink->converter_disable_audio && + dc_is_audio_capable_signal(pipe_ctx->stream->signal) && + stream->public.audio_info.mode_count) { + pipe_ctx->audio = find_first_free_audio( + &context->res_ctx); + + /* + * Audio assigned in order first come first get. + * There are asics which has number of audio + * resources less then number of pipes + */ + if (pipe_ctx->audio) + set_audio_in_use( &context->res_ctx, - pipe_ctx->stream_enc); - - /* TODO: Add check if ASIC support and EDID audio */ - if (!stream->sink->converter_disable_audio && - dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->public.audio_info.mode_count) { - pipe_ctx->audio = find_first_free_audio( - &context->res_ctx); - - /* - * Audio assigned in order first come first get. - * There are asics which has number of audio - * resources less then number of pipes - */ - if (pipe_ctx->audio) - set_audio_in_use( - &context->res_ctx, - pipe_ctx->audio); - } - - if (j == 0) { - context->target_status[i].primary_otg_inst = - pipe_ctx->tg->inst; - } + pipe_ctx->audio); } + + context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst; } return DC_OK; } -/* first target in the context is used to populate the rest */ -void validate_guaranteed_copy_target( +/* first stream in the context is used to populate the rest */ +void validate_guaranteed_copy_streams( struct validate_context *context, - int max_targets) + int max_streams) { int i; - for (i = 1; i < max_targets; i++) { - context->targets[i] = context->targets[0]; + for (i = 1; i < max_streams; i++) { + context->streams[i] = context->streams[0]; copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], &context->res_ctx.pipe_ctx[i]); context->res_ctx.pipe_ctx[i].stream = context->res_ctx.pipe_ctx[0].stream; - dc_target_retain(&context->targets[i]->public); - context->target_count++; + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } } @@ -1875,18 +1836,19 @@ void resource_validate_ctx_destruct(struct validate_context *context) { int i, j; - for (i = 0; i < context->target_count; i++) { - for (j = 0; j < context->target_status[i].surface_count; j++) + for (i = 0; i < context->stream_count; i++) { + for (j = 0; j < context->stream_status[i].surface_count; j++) dc_surface_release( - context->target_status[i].surfaces[j]); + context->stream_status[i].surfaces[j]); - context->target_status[i].surface_count = 0; - dc_target_release(&context->targets[i]->public); + context->stream_status[i].surface_count = 0; + dc_stream_release(&context->streams[i]->public); + context->streams[i] = NULL; } } /* - * Copy src_ctx into dst_ctx and retain all surfaces and targets referenced + * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced * by the src_ctx */ void resource_validate_ctx_copy_construct( @@ -1908,11 +1870,11 @@ void resource_validate_ctx_copy_construct( } - for (i = 0; i < dst_ctx->target_count; i++) { - dc_target_retain(&dst_ctx->targets[i]->public); - for (j = 0; j < dst_ctx->target_status[i].surface_count; j++) + for (i = 0; i < dst_ctx->stream_count; i++) { + dc_stream_retain(&dst_ctx->streams[i]->public); + for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) dc_surface_retain( - dst_ctx->target_status[i].surfaces[j]); + dst_ctx->stream_status[i].surfaces[j]); } } @@ -1968,53 +1930,48 @@ enum dc_status resource_map_clock_resources( const struct core_dc *dc, struct validate_context *context) { - int i, j, k; + int i, j; /* acquire new resources */ - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + const struct core_stream *stream = context->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; + + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (context->res_ctx.pipe_ctx[j].stream != stream) continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = + context->res_ctx.pool->dp_clock_source; + else { + pipe_ctx->clock_source = NULL; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (!dc->public.config.disable_disp_pll_sharing) + resource_find_used_clk_src_for_sharing( + &context->res_ctx, + pipe_ctx); - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + if (pipe_ctx->clock_source == NULL) pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; - else { - pipe_ctx->clock_source = NULL; - - if (!dc->public.config.disable_disp_pll_sharing) - resource_find_used_clk_src_for_sharing( - &context->res_ctx, - pipe_ctx); - - if (pipe_ctx->clock_source == NULL) - pipe_ctx->clock_source = - dc_resource_find_first_free_pll(&context->res_ctx); - } + dc_resource_find_first_free_pll(&context->res_ctx); + } - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - resource_reference_clock_source( - &context->res_ctx, - pipe_ctx->clock_source); + resource_reference_clock_source( + &context->res_ctx, + pipe_ctx->clock_source); - /* only one cs per stream regardless of mpo */ - break; - } + /* only one cs per stream regardless of mpo */ + break; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index cda67a78dbfd..bc1f387d1992 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -27,6 +27,8 @@ #include "dc.h" #include "core_types.h" #include "resource.h" +#include "ipp.h" +#include "timing_generator.h" /******************************************************************************* * Private definitions @@ -146,3 +148,184 @@ construct_fail: alloc_fail: return NULL; } + +const struct dc_stream_status *dc_stream_get_status( + const struct dc_stream *dc_stream) +{ + uint8_t i; + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + + for (i = 0; i < dc->current_context->stream_count; i++) + if (stream == dc->current_context->streams[i]) + return &dc->current_context->stream_status[i]; + + return NULL; +} + +/** + * Update the cursor attributes and set cursor surface address + */ +bool dc_stream_set_cursor_attributes( + const struct dc_stream *dc_stream, + const struct dc_cursor_attributes *attributes) +{ + int i; + struct core_stream *stream; + struct core_dc *core_dc; + struct resource_context *res_ctx; + bool ret = false; + + if (NULL == dc_stream) { + dm_error("DC: dc_stream is NULL!\n"); + return false; + } + if (NULL == attributes) { + dm_error("DC: attributes is NULL!\n"); + return false; + } + + stream = DC_STREAM_TO_CORE(dc_stream); + core_dc = DC_TO_CORE(stream->ctx->dc); + res_ctx = &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->stream == stream) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; + + if (ipp->funcs->ipp_cursor_set_attributes( + ipp, attributes)) + ret = true; + } + } + + return ret; +} + +bool dc_stream_set_cursor_position( + const struct dc_stream *dc_stream, + const struct dc_cursor_position *position) +{ + int i; + struct core_stream *stream; + struct core_dc *core_dc; + struct resource_context *res_ctx; + bool ret = false; + + if (NULL == dc_stream) { + dm_error("DC: dc_stream is NULL!\n"); + return false; + } + + if (NULL == position) { + dm_error("DC: cursor position is NULL!\n"); + return false; + } + + stream = DC_STREAM_TO_CORE(dc_stream); + core_dc = DC_TO_CORE(stream->ctx->dc); + res_ctx = &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->stream == stream) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct dc_cursor_mi_param param = { + .pixel_clk_khz = dc_stream->timing.pix_clk_khz, + .ref_clk_khz = 48000,/*todo refclk*/ + .viewport_x_start = pipe_ctx->scl_data.viewport.x, + .viewport_width = pipe_ctx->scl_data.viewport.width, + .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, + }; + + ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m); + ret = true; + } + } + + return ret; +} + +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) +{ + uint8_t i; + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct resource_context *res_ctx = + &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct timing_generator *tg = res_ctx->pipe_ctx[i].tg; + + if (res_ctx->pipe_ctx[i].stream != stream) + continue; + + return tg->funcs->get_frame_count(tg); + } + + return 0; +} + +uint32_t dc_stream_get_scanoutpos( + const struct dc_stream *dc_stream, + uint32_t *vbl, + uint32_t *position) +{ + uint8_t i; + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct resource_context *res_ctx = + &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct timing_generator *tg = res_ctx->pipe_ctx[i].tg; + + if (res_ctx->pipe_ctx[i].stream != stream) + continue; + + return tg->funcs->get_scanoutpos(tg, vbl, position); + } + + return 0; +} + + +void dc_stream_log( + const struct dc_stream *stream, + struct dal_logger *dm_logger, + enum dc_log_type log_type) +{ + const struct core_stream *core_stream = + DC_STREAM_TO_CORE(stream); + + dm_logger_write(dm_logger, + log_type, + "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n", + core_stream, + core_stream->public.src.x, + core_stream->public.src.y, + core_stream->public.src.width, + core_stream->public.src.height, + core_stream->public.dst.x, + core_stream->public.dst.y, + core_stream->public.dst.width, + core_stream->public.dst.height); + dm_logger_write(dm_logger, + log_type, + "\tpix_clk_khz: %d, h_total: %d, v_total: %d\n", + core_stream->public.timing.pix_clk_khz, + core_stream->public.timing.h_total, + core_stream->public.timing.v_total); + dm_logger_write(dm_logger, + log_type, + "\tsink name: %s, serial: %d\n", + core_stream->sink->public.edid_caps.display_name, + core_stream->sink->public.edid_caps.serial_number); + dm_logger_write(dm_logger, + log_type, + "\tlink: %d\n", + core_stream->sink->link->public.link_index); +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_target.c b/drivers/gpu/drm/amd/display/dc/core/dc_target.c deleted file mode 100644 index 2d25b00b4bff..000000000000 --- a/drivers/gpu/drm/amd/display/dc/core/dc_target.c +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "core_types.h" -#include "hw_sequencer.h" -#include "resource.h" -#include "ipp.h" -#include "timing_generator.h" - -struct target { - struct core_target protected; - int ref_count; -}; - -#define DC_TARGET_TO_TARGET(dc_target) \ - container_of(dc_target, struct target, protected.public) -#define CORE_TARGET_TO_TARGET(core_target) \ - container_of(core_target, struct target, protected) - -static void construct( - struct core_target *target, - struct dc_context *ctx, - struct dc_stream *dc_streams[], - uint8_t stream_count) -{ - uint8_t i; - for (i = 0; i < stream_count; i++) { - target->public.streams[i] = dc_streams[i]; - dc_stream_retain(dc_streams[i]); - } - - target->ctx = ctx; - target->public.stream_count = stream_count; -} - -static void destruct(struct core_target *core_target) -{ - int i; - - for (i = 0; i < core_target->public.stream_count; i++) { - dc_stream_release( - (struct dc_stream *)core_target->public.streams[i]); - core_target->public.streams[i] = NULL; - } -} - -void dc_target_retain(const struct dc_target *dc_target) -{ - struct target *target = DC_TARGET_TO_TARGET(dc_target); - - ASSERT(target->ref_count > 0); - target->ref_count++; -} - -void dc_target_release(const struct dc_target *dc_target) -{ - struct target *target = DC_TARGET_TO_TARGET(dc_target); - struct core_target *protected = DC_TARGET_TO_CORE(dc_target); - - ASSERT(target->ref_count > 0); - target->ref_count--; - - if (target->ref_count == 0) { - destruct(protected); - dm_free(target); - } -} - -const struct dc_target_status *dc_target_get_status( - const struct dc_target* dc_target) -{ - uint8_t i; - struct core_target* target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *dc = DC_TO_CORE(target->ctx->dc); - - for (i = 0; i < dc->current_context->target_count; i++) - if (target == dc->current_context->targets[i]) - return &dc->current_context->target_status[i]; - - return NULL; -} - -struct dc_target *dc_create_target_for_streams( - struct dc_stream *dc_streams[], - uint8_t stream_count) -{ - struct core_stream *stream; - struct target *target; - - if (0 == stream_count) - goto target_alloc_fail; - - stream = DC_STREAM_TO_CORE(dc_streams[0]); - - target = dm_alloc(sizeof(struct target)); - - if (NULL == target) - goto target_alloc_fail; - - construct(&target->protected, stream->ctx, dc_streams, stream_count); - - target->ref_count++; - - return &target->protected.public; - -target_alloc_fail: - return NULL; -} - -bool dc_target_is_connected_to_sink( - const struct dc_target * dc_target, - const struct dc_sink *dc_sink) -{ - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - uint8_t i; - for (i = 0; i < target->public.stream_count; i++) { - if (target->public.streams[i]->sink == dc_sink) - return true; - } - return false; -} - -/** - * Update the cursor attributes and set cursor surface address - */ -bool dc_target_set_cursor_attributes( - struct dc_target *dc_target, - const struct dc_cursor_attributes *attributes) -{ - int i, j; - struct core_target *target; - struct core_dc *core_dc; - struct resource_context *res_ctx; - bool ret = false; - - if (NULL == dc_target) { - dm_error("DC: dc_target is NULL!\n"); - return false; - } - if (NULL == attributes) { - dm_error("DC: attributes is NULL!\n"); - return false; - } - - target = DC_TARGET_TO_CORE(dc_target); - core_dc = DC_TO_CORE(target->ctx->dc); - res_ctx = &core_dc->current_context->res_ctx; - - for (i = 0; i < dc_target->stream_count; i++) { - const struct dc_stream *stream = dc_target->streams[i]; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j]; - - if (&pipe_ctx->stream->public == stream) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; - - if (ipp->funcs->ipp_cursor_set_attributes( - ipp, attributes)) - ret = true; - } - } - } - - return ret; -} - -bool dc_target_set_cursor_position( - struct dc_target *dc_target, - const struct dc_cursor_position *position) -{ - int i, j; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); - struct resource_context *res_ctx = &core_dc->current_context->res_ctx; - bool ret = false; - - if (NULL == dc_target) { - dm_error("DC: dc_target is NULL!\n"); - return false; - } - - if (NULL == position) { - dm_error("DC: cursor position is NULL!\n"); - return false; - } - - for (i = 0; i < dc_target->stream_count; i++) { - const struct dc_stream *stream = dc_target->streams[i]; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j]; - - if (&pipe_ctx->stream->public == stream) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_cursor_mi_param param = { - .pixel_clk_khz = stream->timing.pix_clk_khz, - .ref_clk_khz = 48000,/*todo refclk*/ - .viewport_x_start = pipe_ctx->scl_data.viewport.x, - .viewport_width = pipe_ctx->scl_data.viewport.width, - .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, - }; - - ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m); - ret = true; - } - } - } - - return ret; -} - -uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target) -{ - uint8_t i, j; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); - struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; - - for (i = 0; i < target->public.stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - struct timing_generator *tg = res_ctx->pipe_ctx[j].tg; - - if (res_ctx->pipe_ctx[j].stream != - DC_STREAM_TO_CORE(target->public.streams[i])) - continue; - - return tg->funcs->get_frame_count(tg); - } - } - - return 0; -} - -uint32_t dc_target_get_scanoutpos( - const struct dc_target *dc_target, - uint32_t *vbl, - uint32_t *position) -{ - uint8_t i, j; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); - struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; - - for (i = 0; i < target->public.stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - struct timing_generator *tg = res_ctx->pipe_ctx[j].tg; - - if (res_ctx->pipe_ctx[j].stream != - DC_STREAM_TO_CORE(target->public.streams[i])) - continue; - - return tg->funcs->get_scanoutpos(tg, vbl, position); - } - } - - return 0; -} - -void dc_target_log( - const struct dc_target *dc_target, - struct dal_logger *dm_logger, - enum dc_log_type log_type) -{ - int i; - - const struct core_target *core_target = - CONST_DC_TARGET_TO_CORE(dc_target); - - dm_logger_write(dm_logger, - log_type, - "core_target 0x%x: stream_count=%d\n", - core_target, - core_target->public.stream_count); - - for (i = 0; i < core_target->public.stream_count; i++) { - const struct core_stream *core_stream = - DC_STREAM_TO_CORE(core_target->public.streams[i]); - - dm_logger_write(dm_logger, - log_type, - "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n", - core_stream, - core_stream->public.src.x, - core_stream->public.src.y, - core_stream->public.src.width, - core_stream->public.src.height, - core_stream->public.dst.x, - core_stream->public.dst.y, - core_stream->public.dst.width, - core_stream->public.dst.height); - dm_logger_write(dm_logger, - log_type, - "\tpix_clk_khz: %d, h_total: %d, v_total: %d\n", - core_stream->public.timing.pix_clk_khz, - core_stream->public.timing.h_total, - core_stream->public.timing.v_total); - dm_logger_write(dm_logger, - log_type, - "\tsink name: %s, serial: %d\n", - core_stream->sink->public.edid_caps.display_name, - core_stream->sink->public.edid_caps.serial_number); - dm_logger_write(dm_logger, - log_type, - "\tlink: %d\n", - core_stream->sink->link->public.link_index); - } -} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e8cb7a4dee80..b814e7b76bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -32,8 +32,8 @@ #include "gpio_types.h" #include "link_service_types.h" -#define MAX_TARGETS 6 #define MAX_SURFACES 3 +#define MAX_STREAMS 6 #define MAX_SINKS_PER_LINK 4 /******************************************************************************* @@ -41,7 +41,7 @@ ******************************************************************************/ struct dc_caps { - uint32_t max_targets; + uint32_t max_streams; uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; @@ -139,7 +139,6 @@ struct dc_config { struct dc_debug { bool surface_visual_confirm; bool max_disp_clk; - bool target_trace; bool surface_trace; bool timing_trace; bool validation_trace; @@ -351,95 +350,91 @@ void dc_flip_surface_addrs(struct dc *dc, uint32_t count); /* - * Set up surface attributes and associate to a target - * The surfaces parameter is an absolute set of all surface active for the target. - * If no surfaces are provided, the target will be blanked; no memory read. + * Set up surface attributes and associate to a stream + * The surfaces parameter is an absolute set of all surface active for the stream. + * If no surfaces are provided, the stream will be blanked; no memory read. * Any flip related attribute changes must be done through this interface. * * After this call: - * Surfaces attributes are programmed and configured to be composed into target. + * Surfaces attributes are programmed and configured to be composed into stream. * This does not trigger a flip. No surface address is programmed. */ -bool dc_commit_surfaces_to_target( +bool dc_commit_surfaces_to_stream( struct dc *dc, const struct dc_surface **dc_surfaces, uint8_t surface_count, - struct dc_target *dc_target); + const struct dc_stream *stream); -bool dc_pre_update_surfaces_to_target( +bool dc_pre_update_surfaces_to_stream( struct dc *dc, const struct dc_surface *const *new_surfaces, uint8_t new_surface_count, - struct dc_target *dc_target); + const struct dc_stream *stream); -bool dc_post_update_surfaces_to_target( +bool dc_post_update_surfaces_to_stream( struct dc *dc); -void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *updates, - int surface_count, struct dc_target *dc_target); +void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, + int surface_count, const struct dc_stream *stream); /******************************************************************************* - * Target Interfaces + * Stream Interfaces ******************************************************************************/ -#define MAX_STREAM_NUM 1 +struct dc_stream { + const struct dc_sink *sink; + struct dc_crtc_timing timing; -struct dc_target { - uint8_t stream_count; - const struct dc_stream *streams[MAX_STREAM_NUM]; -}; + enum dc_color_space output_color_space; -/* - * Target status is returned from dc_target_get_status in order to get the - * the IRQ source, current frame counter and currently attached surfaces. - */ -struct dc_target_status { - int primary_otg_inst; - int cur_frame_count; - int surface_count; - const struct dc_surface *surfaces[MAX_SURFACE_NUM]; -}; + struct rect src; /* composition area */ + struct rect dst; /* stream addressable area */ -struct dc_target *dc_create_target_for_streams( - struct dc_stream *dc_streams[], - uint8_t stream_count); + struct audio_info audio_info; + + bool ignore_msa_timing_param; + + struct freesync_context freesync_ctx; + + const struct dc_transfer_func *out_transfer_func; + struct colorspace_transform gamut_remap_matrix; + struct csc_transform csc_color_matrix; + + /* TODO: dithering */ + /* TODO: custom INFO packets */ + /* TODO: ABM info (DMCU) */ + /* TODO: PSR info */ + /* TODO: CEA VIC */ +}; /* - * Get the current target status. + * Log the current stream state. */ -const struct dc_target_status *dc_target_get_status( - const struct dc_target* dc_target); - -void dc_target_retain(const struct dc_target *dc_target); -void dc_target_release(const struct dc_target *dc_target); -void dc_target_log( - const struct dc_target *dc_target, +void dc_stream_log( + const struct dc_stream *stream, struct dal_logger *dc_logger, enum dc_log_type log_type); -uint8_t dc_get_current_target_count(const struct dc *dc); -struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i); +uint8_t dc_get_current_stream_count(const struct dc *dc); +struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); -bool dc_target_is_connected_to_sink( - const struct dc_target *dc_target, - const struct dc_sink *dc_sink); - -uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target); +/* + * Return the current frame counter. + */ +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); /* TODO: Return parsed values rather than direct register read * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -uint32_t dc_target_get_scanoutpos( - const struct dc_target *dc_target, - uint32_t *vbl, - uint32_t *position); +uint32_t dc_stream_get_scanoutpos( + const struct dc_stream *stream, uint32_t *vbl, uint32_t *position); /* - * Structure to store surface/target associations for validation + * Structure to store surface/stream associations for validation */ struct dc_validation_set { - const struct dc_target *target; + const struct dc_stream *stream; const struct dc_surface *surfaces[MAX_SURFACES]; uint8_t surface_count; }; @@ -456,8 +451,8 @@ bool dc_validate_resources( uint8_t set_count); /* - * This function takes a target and checks if it is guaranteed to be supported. - * Guaranteed means that MAX_COFUNC*target is supported. + * This function takes a stream and checks if it is guaranteed to be supported. + * Guaranteed means that MAX_COFUNC similar streams are supported. * * After this call: * No hardware is programmed for call. Only validation is done. @@ -465,49 +460,20 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_target *dc_target); + const struct dc_stream *stream); /* - * Set up streams and links associated to targets to drive sinks - * The targets parameter is an absolute set of all active targets. + * Set up streams and links associated to drive sinks + * The streams parameter is an absolute set of all active streams. * * After this call: * Phy, Encoder, Timing Generator are programmed and enabled. - * New targets are enabled with blank stream; no memory read. + * New streams are enabled with blank stream; no memory read. */ -bool dc_commit_targets( +bool dc_commit_streams( struct dc *dc, - struct dc_target *targets[], - uint8_t target_count); - -/******************************************************************************* - * Stream Interfaces - ******************************************************************************/ -struct dc_stream { - const struct dc_sink *sink; - struct dc_crtc_timing timing; - - enum dc_color_space output_color_space; - - struct rect src; /* viewport in target space*/ - struct rect dst; /* stream addressable area */ - - struct audio_info audio_info; - - bool ignore_msa_timing_param; - - struct freesync_context freesync_ctx; - - const struct dc_transfer_func *out_transfer_func; - struct colorspace_transform gamut_remap_matrix; - struct csc_transform csc_color_matrix; - - /* TODO: dithering */ - /* TODO: custom INFO packets */ - /* TODO: ABM info (DMCU) */ - /* TODO: PSR info */ - /* TODO: CEA VIC */ -}; + const struct dc_stream *streams[], + uint8_t stream_count); /** * Create a new default stream for the requested sink @@ -518,6 +484,10 @@ void dc_stream_retain(const struct dc_stream *dc_stream); void dc_stream_release(const struct dc_stream *dc_stream); struct dc_stream_status { + int primary_otg_inst; + int surface_count; + const struct dc_surface *surfaces[MAX_SURFACE_NUM]; + /* * link this stream passes through */ @@ -691,15 +661,15 @@ struct dc_sink_init_data { struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); /******************************************************************************* - * Cursor interfaces - To manages the cursor within a target + * Cursor interfaces - To manages the cursor within a stream ******************************************************************************/ /* TODO: Deprecated once we switch to dc_set_cursor_position */ -bool dc_target_set_cursor_attributes( - struct dc_target *dc_target, +bool dc_stream_set_cursor_attributes( + const struct dc_stream *stream, const struct dc_cursor_attributes *attributes); -bool dc_target_set_cursor_position( - struct dc_target *dc_target, +bool dc_stream_set_cursor_position( + const struct dc_stream *stream, const struct dc_cursor_position *position); /* Newer interfaces */ @@ -708,36 +678,6 @@ struct dc_cursor { struct dc_cursor_attributes attributes; }; -/* - * Create a new cursor with default values for a given target. - */ -struct dc_cursor *dc_create_cursor_for_target( - const struct dc *dc, - struct dc_target *dc_target); - -/** - * Commit cursor attribute changes such as pixel format and dimensions and - * surface address. - * - * After this call: - * Cursor address and format is programmed to the new values. - * Cursor position is unmodified. - */ -bool dc_commit_cursor( - const struct dc *dc, - struct dc_cursor *cursor); - -/* - * Optimized cursor position update - * - * After this call: - * Cursor position will be programmed as well as enable/disable bit. - */ -bool dc_set_cursor_position( - const struct dc *dc, - struct dc_cursor *cursor, - struct dc_cursor_position *pos); - /******************************************************************************* * Interrupt interfaces ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ae9fcca121e6..242dd7b3b6b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -34,7 +34,6 @@ /* forward declarations */ struct dc_surface; -struct dc_target; struct dc_stream; struct dc_link; struct dc_sink; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 082f1f053a3a..ae0e7eac2c9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -741,53 +741,48 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + /* TODO: validate audio ASIC caps, encoder */ + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -818,9 +813,9 @@ static bool dce100_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -846,9 +841,9 @@ enum dc_status dce100_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -858,7 +853,7 @@ enum dc_status dce100_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -876,16 +871,16 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -896,8 +891,8 @@ enum dc_status dce100_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 751dbb88c265..415b12accd2c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -753,7 +753,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->public.timing.h_total, stream->public.timing.v_total, stream->public.timing.pix_clk_khz, - context->target_count); + context->stream_count); return DC_OK; } @@ -1055,7 +1055,7 @@ static void reset_single_pipe_hw_ctx( } pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); pipe_ctx->mi->funcs->free_mem_input( - pipe_ctx->mi, context->target_count); + pipe_ctx->mi, context->stream_count); resource_unreference_clock_source( &context->res_ctx, &pipe_ctx->clock_source); @@ -1254,7 +1254,7 @@ enum dc_status dce110_apply_ctx_to_hw( dc->hwss.reset_hw_ctx_wrap(dc, context); /* Skip applying if no targets */ - if (context->target_count <= 0) + if (context->stream_count <= 0) return DC_OK; if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { @@ -1761,7 +1761,7 @@ static void dce110_power_on_pipe_if_needed( pipe_ctx->stream->public.timing.h_total, pipe_ctx->stream->public.timing.v_total, pipe_ctx->stream->public.timing.pix_clk_khz, - context->target_count); + context->stream_count); /* TODO unhardcode*/ color_space_to_black_color(dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 968ee99003fc..cfbb4ef21f8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -817,58 +817,53 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!is_surface_pixel_format_supported(pipe_ctx, - context->res_ctx.pool->underlay_pipe_index)) - return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; + if (!is_surface_pixel_format_supported(pipe_ctx, + context->res_ctx.pool->underlay_pipe_index)) + return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ + /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -901,9 +896,9 @@ enum dc_status dce110_validate_bandwidth( dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: %dx%d@%d Bandwidth validation failed!\n", __func__, - context->targets[0]->public.streams[0]->timing.h_addressable, - context->targets[0]->public.streams[0]->timing.v_addressable, - context->targets[0]->public.streams[0]->timing.pix_clk_khz); + context->streams[0]->public.timing.h_addressable, + context->streams[0]->public.timing.v_addressable, + context->streams[0]->public.timing.pix_clk_khz); if (memcmp(&dc->current_context->bw_results, &context->bw_results, sizeof(context->bw_results))) { @@ -972,9 +967,9 @@ static bool dce110_validate_surface_sets( return false; if (set[i].surfaces[0]->src_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->src_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -988,7 +983,7 @@ static bool dce110_validate_surface_sets( || set[i].surfaces[1]->src_rect.height > 1080) return false; - if (set[i].target->streams[0]->timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) return false; } } @@ -1012,9 +1007,9 @@ enum dc_status dce110_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -1024,7 +1019,7 @@ enum dc_status dce110_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -1042,16 +1037,16 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -1062,8 +1057,8 @@ enum dc_status dce110_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 7fca2eb188cf..64fae91dd5eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -779,54 +779,49 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ + /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -917,45 +912,40 @@ enum dc_status resource_map_phy_clock_resources( const struct core_dc *dc, struct validate_context *context) { - uint8_t i, j, k; + uint8_t i, j; /* acquire new resources */ - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; - else - pipe_ctx->clock_source = - find_matching_pll(&context->res_ctx, - stream); + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = + context->res_ctx.pool->dp_clock_source; + else + pipe_ctx->clock_source = + find_matching_pll(&context->res_ctx, + stream); - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - resource_reference_clock_source( - &context->res_ctx, - pipe_ctx->clock_source); + resource_reference_clock_source( + &context->res_ctx, + pipe_ctx->clock_source); - /* only one cs per stream regardless of mpo */ - break; - } + /* only one cs per stream regardless of mpo */ + break; } } @@ -976,9 +966,9 @@ static bool dce112_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -1004,9 +994,9 @@ enum dc_status dce112_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -1016,7 +1006,7 @@ enum dc_status dce112_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -1034,16 +1024,16 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -1054,8 +1044,8 @@ enum dc_status dce112_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index f21eb57857d4..faa8c45a3544 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -43,7 +43,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context); enum dc_status dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index e2bfa7efce1c..bee3a41ffe9f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -731,54 +731,49 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ + /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -810,9 +805,9 @@ static bool dce80_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -838,9 +833,9 @@ enum dc_status dce80_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -850,7 +845,7 @@ enum dc_status dce80_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -868,16 +863,16 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -888,8 +883,8 @@ enum dc_status dce80_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index b5a5207a4df0..7a6444dc2957 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -21,7 +21,6 @@ struct core_dc { uint8_t link_count; struct core_link *links[MAX_PIPES * 2]; - /* TODO: determine max number of targets*/ struct validate_context *current_context; struct validate_context *temp_flip_context; struct validate_context *scratch_val_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index c2d35c2c28bf..66bfcdb57c4c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -32,21 +32,10 @@ #include "dc_bios_types.h" struct core_stream; -/********* core_target *************/ - -#define CONST_DC_TARGET_TO_CORE(dc_target) \ - container_of(dc_target, const struct core_target, public) -#define DC_TARGET_TO_CORE(dc_target) \ - container_of(dc_target, struct core_target, public) #define MAX_PIPES 6 #define MAX_CLOCK_SOURCES 7 -struct core_target { - struct dc_target public; - - struct dc_context *ctx; -}; /********* core_surface **********/ #define DC_SURFACE_TO_CORE(dc_surface) \ @@ -215,7 +204,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *stream, struct validate_context *context); enum dc_status (*validate_bandwidth)( @@ -312,9 +301,9 @@ struct resource_context { }; struct validate_context { - struct core_target *targets[MAX_PIPES]; - struct dc_target_status target_status[MAX_PIPES]; - uint8_t target_count; + struct core_stream *streams[MAX_PIPES]; + struct dc_stream_status stream_status[MAX_PIPES]; + uint8_t stream_count; struct resource_context res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index adf297ec33b6..d96c64bb0a70 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -118,25 +118,26 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( bool resource_attach_surfaces_to_context( const struct dc_surface *const *surfaces, int surface_count, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context); struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx); bool resource_is_stream_unchanged( - const struct validate_context *old_context, struct core_stream *stream); + const struct validate_context *old_context, const struct core_stream *stream); + +bool is_stream_unchanged( + const struct core_stream *old_stream, const struct core_stream *stream); -bool is_target_unchanged( - const struct core_target *old_target, const struct core_target *target); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, const struct validate_context *old_context, struct validate_context *context); -void validate_guaranteed_copy_target( +void validate_guaranteed_copy_streams( struct validate_context *context, - int max_targets); + int max_streams); void resource_validate_ctx_update_pointer_after_copy( const struct validate_context *src_ctx, -- cgit v1.2.3-59-g8ed1b From fcd2f4bf8bbe73ac860d1be275a22a54a8d8d385 Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Thu, 5 Jan 2017 17:12:20 -0500 Subject: drm/amd/display: Output Transfer Function Regamma Refactor - Create translation function to translate logical format to hw format - Refactor to use transfer function in dc instead of input gamma Signed-off-by: Amy Zhang Acked-by: Harry Wentland Reviewed-by: Anthony Koo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 9 + drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c | 1481 -------------------- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +- drivers/gpu/drm/amd/display/dc/dc.h | 11 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 440 +++++- drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h | 20 - drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 2 - drivers/gpu/drm/amd/display/include/fixed31_32.h | 8 + 9 files changed, 466 insertions(+), 1517 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c index 5a6e46843502..546ed67c6f83 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c @@ -246,6 +246,15 @@ struct fixed31_32 dal_fixed31_32_add( return res; } +struct fixed31_32 dal_fixed31_32_add_int( + struct fixed31_32 arg1, + int32_t arg2) +{ + return dal_fixed31_32_add( + arg1, + dal_fixed31_32_from_int(arg2)); +} + struct fixed31_32 dal_fixed31_32_sub_int( struct fixed31_32 arg1, int32_t arg2) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 4001933e7808..4bb08aea6a03 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -3,7 +3,7 @@ # It calculates Bandwidth and Watermarks values for HW programming # -BW_CALCS = bandwidth_calcs.o bw_fixed.o gamma_calcs.o +BW_CALCS = bandwidth_calcs.o bw_fixed.o AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS)) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c deleted file mode 100644 index fd300db833c7..000000000000 --- a/drivers/gpu/drm/amd/display/dc/calcs/gamma_calcs.c +++ /dev/null @@ -1,1481 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "gamma_calcs.h" - -struct curve_config { - uint32_t offset; - int8_t segments[16]; - int8_t begin; -}; - -static bool build_custom_float( - struct fixed31_32 value, - const struct custom_float_format *format, - bool *negative, - uint32_t *mantissa, - uint32_t *exponenta) -{ - uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; - - const struct fixed31_32 mantissa_constant_plus_max_fraction = - dal_fixed31_32_from_fraction( - (1LL << (format->mantissa_bits + 1)) - 1, - 1LL << format->mantissa_bits); - - struct fixed31_32 mantiss; - - if (dal_fixed31_32_eq( - value, - dal_fixed31_32_zero)) { - *negative = false; - *mantissa = 0; - *exponenta = 0; - return true; - } - - if (dal_fixed31_32_lt( - value, - dal_fixed31_32_zero)) { - *negative = format->sign; - value = dal_fixed31_32_neg(value); - } else { - *negative = false; - } - - if (dal_fixed31_32_lt( - value, - dal_fixed31_32_one)) { - uint32_t i = 1; - - do { - value = dal_fixed31_32_shl(value, 1); - ++i; - } while (dal_fixed31_32_lt( - value, - dal_fixed31_32_one)); - - --i; - - if (exp_offset <= i) { - *mantissa = 0; - *exponenta = 0; - return true; - } - - *exponenta = exp_offset - i; - } else if (dal_fixed31_32_le( - mantissa_constant_plus_max_fraction, - value)) { - uint32_t i = 1; - - do { - value = dal_fixed31_32_shr(value, 1); - ++i; - } while (dal_fixed31_32_lt( - mantissa_constant_plus_max_fraction, - value)); - - *exponenta = exp_offset + i - 1; - } else { - *exponenta = exp_offset; - } - - mantiss = dal_fixed31_32_sub( - value, - dal_fixed31_32_one); - - if (dal_fixed31_32_lt( - mantiss, - dal_fixed31_32_zero) || - dal_fixed31_32_lt( - dal_fixed31_32_one, - mantiss)) - mantiss = dal_fixed31_32_zero; - else - mantiss = dal_fixed31_32_shl( - mantiss, - format->mantissa_bits); - - *mantissa = dal_fixed31_32_floor(mantiss); - - return true; -} - -static bool setup_custom_float( - const struct custom_float_format *format, - bool negative, - uint32_t mantissa, - uint32_t exponenta, - uint32_t *result) -{ - uint32_t i = 0; - uint32_t j = 0; - - uint32_t value = 0; - - /* verification code: - * once calculation is ok we can remove it - */ - - const uint32_t mantissa_mask = - (1 << (format->mantissa_bits + 1)) - 1; - - const uint32_t exponenta_mask = - (1 << (format->exponenta_bits + 1)) - 1; - - if (mantissa & ~mantissa_mask) { - BREAK_TO_DEBUGGER(); - mantissa = mantissa_mask; - } - - if (exponenta & ~exponenta_mask) { - BREAK_TO_DEBUGGER(); - exponenta = exponenta_mask; - } - - /* end of verification code */ - - while (i < format->mantissa_bits) { - uint32_t mask = 1 << i; - - if (mantissa & mask) - value |= mask; - - ++i; - } - - while (j < format->exponenta_bits) { - uint32_t mask = 1 << j; - - if (exponenta & mask) - value |= mask << i; - - ++j; - } - - if (negative && format->sign) - value |= 1 << (i + j); - - *result = value; - - return true; -} - -static bool build_hw_curve_configuration( - const struct curve_config *curve_config, - struct gamma_curve *gamma_curve, - struct curve_points *curve_points, - struct hw_x_point *points, - uint32_t *number_of_points) -{ - const int8_t max_regions_number = ARRAY_SIZE(curve_config->segments); - - int8_t i; - - uint8_t segments_calculation[8] = { 0 }; - - struct fixed31_32 region1 = dal_fixed31_32_zero; - struct fixed31_32 region2; - struct fixed31_32 increment; - - uint32_t index = 0; - uint32_t segments = 0; - uint32_t max_number; - - int8_t num_regions = 0; - - bool result = false; - - if (!number_of_points) { - BREAK_TO_DEBUGGER(); - return false; - } - - max_number = *number_of_points; - - i = 0; - - while (i != max_regions_number) { - gamma_curve[i].offset = 0; - gamma_curve[i].segments_num = 0; - - ++i; - } - - i = 0; - - while (i != max_regions_number) { - /* number should go in uninterruptible sequence */ - if (curve_config->segments[i] == -1) - break; - - ASSERT(curve_config->segments[i] >= 0); - - segments += (1 << curve_config->segments[i]); - ++num_regions; - - ++i; - } - - if (segments > max_number) { - BREAK_TO_DEBUGGER(); - } else { - int32_t divisor; - uint32_t offset = 0; - int8_t begin = curve_config->begin; - int32_t region_number = 0; - - i = begin; - - while ((index < max_number) && - (region_number < max_regions_number) && - (i < (begin + num_regions))) { - int32_t j = 0; - - segments = curve_config->segments[region_number]; - divisor = 1 << segments; - - if (segments == -1) { - if (i > 0) { - region1 = dal_fixed31_32_shl( - dal_fixed31_32_one, - i - 1); - region2 = dal_fixed31_32_shl( - dal_fixed31_32_one, - i); - } else { - region1 = dal_fixed31_32_shr( - dal_fixed31_32_one, - -(i - 1)); - region2 = dal_fixed31_32_shr( - dal_fixed31_32_one, - -i); - } - - break; - } - - if (i > -1) { - region1 = dal_fixed31_32_shl( - dal_fixed31_32_one, - i); - region2 = dal_fixed31_32_shl( - dal_fixed31_32_one, - i + 1); - } else { - region1 = dal_fixed31_32_shr( - dal_fixed31_32_one, - -i); - region2 = dal_fixed31_32_shr( - dal_fixed31_32_one, - -(i + 1)); - } - - gamma_curve[region_number].offset = offset; - gamma_curve[region_number].segments_num = segments; - - offset += divisor; - - ++segments_calculation[segments]; - - increment = dal_fixed31_32_div_int( - dal_fixed31_32_sub( - region2, - region1), - divisor); - - points[index].x = region1; - points[index].adjusted_x = region1; - - ++index; - ++region_number; - - while ((index < max_number) && (j < divisor - 1)) { - region1 = dal_fixed31_32_add( - region1, - increment); - - points[index].x = region1; - points[index].adjusted_x = region1; - - ++index; - ++j; - } - - ++i; - } - - points[index].x = region1; - points[index].adjusted_x = region1; - - *number_of_points = index; - - result = true; - } - - curve_points[0].x = points[0].adjusted_x; - curve_points[0].offset = dal_fixed31_32_zero; - - curve_points[1].x = points[index - 1].adjusted_x; - curve_points[1].offset = dal_fixed31_32_zero; - - curve_points[2].x = points[index].adjusted_x; - curve_points[2].offset = dal_fixed31_32_zero; - - return result; -} - -static bool setup_distribution_points_pq( - struct gamma_curve *arr_curve_points, - struct curve_points *arr_points, - uint32_t *hw_points_num, - struct hw_x_point *coordinates_x, - enum surface_pixel_format format) -{ - struct curve_config cfg; - - cfg.offset = 0; - cfg.segments[0] = 2; - cfg.segments[1] = 2; - cfg.segments[2] = 2; - cfg.segments[3] = 2; - cfg.segments[4] = 2; - cfg.segments[5] = 2; - cfg.segments[6] = 3; - cfg.segments[7] = 4; - cfg.segments[8] = 4; - cfg.segments[9] = 4; - cfg.segments[10] = 4; - cfg.segments[11] = 5; - cfg.segments[12] = 5; - cfg.segments[13] = 5; - cfg.segments[14] = 5; - cfg.segments[15] = 5; - - if (format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || - format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) - cfg.begin = -11; - else - cfg.begin = -16; - - if (!build_hw_curve_configuration( - &cfg, arr_curve_points, - arr_points, - coordinates_x, hw_points_num)) { - ASSERT_CRITICAL(false); - return false; - } - return true; -} - -static bool setup_distribution_points( - struct gamma_curve *arr_curve_points, - struct curve_points *arr_points, - uint32_t *hw_points_num, - struct hw_x_point *coordinates_x) -{ - struct curve_config cfg; - - cfg.offset = 0; - cfg.segments[0] = 3; - cfg.segments[1] = 4; - cfg.segments[2] = 4; - cfg.segments[3] = 4; - cfg.segments[4] = 4; - cfg.segments[5] = 4; - cfg.segments[6] = 4; - cfg.segments[7] = 4; - cfg.segments[8] = 5; - cfg.segments[9] = 5; - cfg.segments[10] = 0; - cfg.segments[11] = -1; - cfg.segments[12] = -1; - cfg.segments[13] = -1; - cfg.segments[14] = -1; - cfg.segments[15] = -1; - - cfg.begin = -10; - - if (!build_hw_curve_configuration( - &cfg, arr_curve_points, - arr_points, - coordinates_x, hw_points_num)) { - ASSERT_CRITICAL(false); - return false; - } - return true; -} - -struct dividers { - struct fixed31_32 divider1; - struct fixed31_32 divider2; - struct fixed31_32 divider3; -}; - -static void build_regamma_coefficients(struct gamma_coefficients *coefficients) -{ - /* sRGB should apply 2.4 */ - static const int32_t numerator01[3] = { 31308, 31308, 31308 }; - static const int32_t numerator02[3] = { 12920, 12920, 12920 }; - static const int32_t numerator03[3] = { 55, 55, 55 }; - static const int32_t numerator04[3] = { 55, 55, 55 }; - static const int32_t numerator05[3] = { 2400, 2400, 2400 }; - - const int32_t *numerator1; - const int32_t *numerator2; - const int32_t *numerator3; - const int32_t *numerator4; - const int32_t *numerator5; - - uint32_t i = 0; - - numerator1 = numerator01; - numerator2 = numerator02; - numerator3 = numerator03; - numerator4 = numerator04; - numerator5 = numerator05; - - do { - coefficients->a0[i] = dal_fixed31_32_from_fraction( - numerator1[i], 10000000); - coefficients->a1[i] = dal_fixed31_32_from_fraction( - numerator2[i], 1000); - coefficients->a2[i] = dal_fixed31_32_from_fraction( - numerator3[i], 1000); - coefficients->a3[i] = dal_fixed31_32_from_fraction( - numerator4[i], 1000); - coefficients->user_gamma[i] = dal_fixed31_32_from_fraction( - numerator5[i], 1000); - - ++i; - } while (i != ARRAY_SIZE(coefficients->a0)); -} - -static struct fixed31_32 translate_from_linear_space( - struct fixed31_32 arg, - struct fixed31_32 a0, - struct fixed31_32 a1, - struct fixed31_32 a2, - struct fixed31_32 a3, - struct fixed31_32 gamma) -{ - const struct fixed31_32 one = dal_fixed31_32_from_int(1); - - if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0))) - return dal_fixed31_32_sub( - a2, - dal_fixed31_32_mul( - dal_fixed31_32_add( - one, - a3), - dal_fixed31_32_pow( - dal_fixed31_32_neg(arg), - dal_fixed31_32_recip(gamma)))); - else if (dal_fixed31_32_le(a0, arg)) - return dal_fixed31_32_sub( - dal_fixed31_32_mul( - dal_fixed31_32_add( - one, - a3), - dal_fixed31_32_pow( - arg, - dal_fixed31_32_recip(gamma))), - a2); - else - return dal_fixed31_32_mul( - arg, - a1); -} - -static inline struct fixed31_32 translate_from_linear_space_ex( - struct fixed31_32 arg, - struct gamma_coefficients *coeff, - uint32_t color_index) -{ - return translate_from_linear_space( - arg, - coeff->a0[color_index], - coeff->a1[color_index], - coeff->a2[color_index], - coeff->a3[color_index], - coeff->user_gamma[color_index]); -} - -static bool find_software_points( - const struct gamma_pixel *axis_x_256, - struct fixed31_32 hw_point, - enum channel_name channel, - uint32_t *index_to_start, - uint32_t *index_left, - uint32_t *index_right, - enum hw_point_position *pos) -{ - const uint32_t max_number = INPUT_LUT_ENTRIES + 3; - - struct fixed31_32 left, right; - - uint32_t i = *index_to_start; - - while (i < max_number) { - if (channel == CHANNEL_NAME_RED) { - left = axis_x_256[i].r; - - if (i < max_number - 1) - right = axis_x_256[i + 1].r; - else - right = axis_x_256[max_number - 1].r; - } else if (channel == CHANNEL_NAME_GREEN) { - left = axis_x_256[i].g; - - if (i < max_number - 1) - right = axis_x_256[i + 1].g; - else - right = axis_x_256[max_number - 1].g; - } else { - left = axis_x_256[i].b; - - if (i < max_number - 1) - right = axis_x_256[i + 1].b; - else - right = axis_x_256[max_number - 1].b; - } - - if (dal_fixed31_32_le(left, hw_point) && - dal_fixed31_32_le(hw_point, right)) { - *index_to_start = i; - *index_left = i; - - if (i < max_number - 1) - *index_right = i + 1; - else - *index_right = max_number - 1; - - *pos = HW_POINT_POSITION_MIDDLE; - - return true; - } else if ((i == *index_to_start) && - dal_fixed31_32_le(hw_point, left)) { - *index_to_start = i; - *index_left = i; - *index_right = i; - - *pos = HW_POINT_POSITION_LEFT; - - return true; - } else if ((i == max_number - 1) && - dal_fixed31_32_le(right, hw_point)) { - *index_to_start = i; - *index_left = i; - *index_right = i; - - *pos = HW_POINT_POSITION_RIGHT; - - return true; - } - - ++i; - } - - return false; -} - -static bool build_custom_gamma_mapping_coefficients_worker( - struct pixel_gamma_point *coeff, - const struct hw_x_point *coordinates_x, - const struct gamma_pixel *axis_x_256, - enum channel_name channel, - uint32_t number_of_points, - enum surface_pixel_format pixel_format) -{ - uint32_t i = 0; - - while (i <= number_of_points) { - struct fixed31_32 coord_x; - - uint32_t index_to_start = 0; - uint32_t index_left = 0; - uint32_t index_right = 0; - - enum hw_point_position hw_pos; - - struct gamma_point *point; - - struct fixed31_32 left_pos; - struct fixed31_32 right_pos; - - /* - * TODO: confirm enum in surface_pixel_format - * if (pixel_format == PIXEL_FORMAT_FP16) - *coord_x = coordinates_x[i].adjusted_x; - *else - */ - if (channel == CHANNEL_NAME_RED) - coord_x = coordinates_x[i].regamma_y_red; - else if (channel == CHANNEL_NAME_GREEN) - coord_x = coordinates_x[i].regamma_y_green; - else - coord_x = coordinates_x[i].regamma_y_blue; - - if (!find_software_points( - axis_x_256, coord_x, channel, - &index_to_start, &index_left, &index_right, &hw_pos)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (index_left >= INPUT_LUT_ENTRIES + 3) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (index_right >= INPUT_LUT_ENTRIES + 3) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (channel == CHANNEL_NAME_RED) { - point = &coeff[i].r; - - left_pos = axis_x_256[index_left].r; - right_pos = axis_x_256[index_right].r; - } else if (channel == CHANNEL_NAME_GREEN) { - point = &coeff[i].g; - - left_pos = axis_x_256[index_left].g; - right_pos = axis_x_256[index_right].g; - } else { - point = &coeff[i].b; - - left_pos = axis_x_256[index_left].b; - right_pos = axis_x_256[index_right].b; - } - - if (hw_pos == HW_POINT_POSITION_MIDDLE) - point->coeff = dal_fixed31_32_div( - dal_fixed31_32_sub( - coord_x, - left_pos), - dal_fixed31_32_sub( - right_pos, - left_pos)); - else if (hw_pos == HW_POINT_POSITION_LEFT) - point->coeff = dal_fixed31_32_zero; - else if (hw_pos == HW_POINT_POSITION_RIGHT) - point->coeff = dal_fixed31_32_from_int(2); - else { - BREAK_TO_DEBUGGER(); - return false; - } - - point->left_index = index_left; - point->right_index = index_right; - point->pos = hw_pos; - - ++i; - } - - return true; -} - -static inline bool build_oem_custom_gamma_mapping_coefficients( - struct pixel_gamma_point *coeff128_oem, - const struct hw_x_point *coordinates_x, - const struct gamma_pixel *axis_x_256, - uint32_t number_of_points, - enum surface_pixel_format pixel_format) -{ - int i; - - for (i = 0; i < 3; i++) { - if (!build_custom_gamma_mapping_coefficients_worker( - coeff128_oem, coordinates_x, axis_x_256, i, - number_of_points, pixel_format)) - return false; - } - return true; -} - -static struct fixed31_32 calculate_mapped_value( - struct pwl_float_data *rgb, - const struct pixel_gamma_point *coeff, - enum channel_name channel, - uint32_t max_index) -{ - const struct gamma_point *point; - - struct fixed31_32 result; - - if (channel == CHANNEL_NAME_RED) - point = &coeff->r; - else if (channel == CHANNEL_NAME_GREEN) - point = &coeff->g; - else - point = &coeff->b; - - if ((point->left_index < 0) || (point->left_index > max_index)) { - BREAK_TO_DEBUGGER(); - return dal_fixed31_32_zero; - } - - if ((point->right_index < 0) || (point->right_index > max_index)) { - BREAK_TO_DEBUGGER(); - return dal_fixed31_32_zero; - } - - if (point->pos == HW_POINT_POSITION_MIDDLE) - if (channel == CHANNEL_NAME_RED) - result = dal_fixed31_32_add( - dal_fixed31_32_mul( - point->coeff, - dal_fixed31_32_sub( - rgb[point->right_index].r, - rgb[point->left_index].r)), - rgb[point->left_index].r); - else if (channel == CHANNEL_NAME_GREEN) - result = dal_fixed31_32_add( - dal_fixed31_32_mul( - point->coeff, - dal_fixed31_32_sub( - rgb[point->right_index].g, - rgb[point->left_index].g)), - rgb[point->left_index].g); - else - result = dal_fixed31_32_add( - dal_fixed31_32_mul( - point->coeff, - dal_fixed31_32_sub( - rgb[point->right_index].b, - rgb[point->left_index].b)), - rgb[point->left_index].b); - else if (point->pos == HW_POINT_POSITION_LEFT) { - BREAK_TO_DEBUGGER(); - result = dal_fixed31_32_zero; - } else { - BREAK_TO_DEBUGGER(); - result = dal_fixed31_32_one; - } - - return result; -} - -static inline struct fixed31_32 calculate_oem_mapped_value( - struct pwl_float_data *rgb_oem, - const struct pixel_gamma_point *coeff, - uint32_t index, - enum channel_name channel, - uint32_t max_index) -{ - return calculate_mapped_value( - rgb_oem, - coeff + index, - channel, - max_index); -} - -static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y) -{ - /* consts for PQ gamma formula. */ - const struct fixed31_32 m1 = - dal_fixed31_32_from_fraction(159301758, 1000000000); - const struct fixed31_32 m2 = - dal_fixed31_32_from_fraction(7884375, 100000); - const struct fixed31_32 c1 = - dal_fixed31_32_from_fraction(8359375, 10000000); - const struct fixed31_32 c2 = - dal_fixed31_32_from_fraction(188515625, 10000000); - const struct fixed31_32 c3 = - dal_fixed31_32_from_fraction(186875, 10000); - - struct fixed31_32 l_pow_m1; - struct fixed31_32 base; - - if (dal_fixed31_32_lt(in_x, dal_fixed31_32_zero)) - in_x = dal_fixed31_32_zero; - - l_pow_m1 = dal_fixed31_32_pow(in_x, m1); - base = dal_fixed31_32_div( - dal_fixed31_32_add(c1, - (dal_fixed31_32_mul(c2, l_pow_m1))), - dal_fixed31_32_add(dal_fixed31_32_one, - (dal_fixed31_32_mul(c3, l_pow_m1)))); - *out_y = dal_fixed31_32_pow(base, m2); -} - -static void build_regamma_curve_pq(struct pwl_float_data_ex *rgb_regamma, - struct pwl_float_data *rgb_oem, - struct pixel_gamma_point *coeff128_oem, - const struct core_gamma *ramp, - const struct core_surface *surface, - uint32_t hw_points_num, - const struct hw_x_point *coordinate_x, - const struct gamma_pixel *axis_x, - struct dividers dividers) -{ - uint32_t i; - - struct pwl_float_data_ex *rgb = rgb_regamma; - const struct hw_x_point *coord_x = coordinate_x; - struct fixed31_32 x; - struct fixed31_32 output; - struct fixed31_32 scaling_factor = - dal_fixed31_32_from_fraction(8, 1000); - - /* use coord_x to retrieve coordinates chosen base on given user curve - * the x values are exponentially distributed and currently it is hard - * coded, the user curve shape is ignored. Need to recalculate coord_x - * based on input curve, translation from 256/1025 to 128 PWL points. - */ - for (i = 0; i <= hw_points_num; i++) { - /* Multiply 0.008 as regamma is 0-1 and FP16 input is 0-125. - * FP 1.0 = 80nits - */ - x = dal_fixed31_32_mul(coord_x->adjusted_x, scaling_factor); - - compute_pq(x, &output); - - /* should really not happen? */ - if (dal_fixed31_32_lt(output, dal_fixed31_32_zero)) - output = dal_fixed31_32_zero; - else if (dal_fixed31_32_lt(dal_fixed31_32_one, output)) - output = dal_fixed31_32_one; - - rgb->r = output; - rgb->g = output; - rgb->b = output; - - ++coord_x; - ++rgb; - } -} - -static void build_regamma_curve(struct pwl_float_data_ex *rgb_regamma, - struct pwl_float_data *rgb_oem, - struct pixel_gamma_point *coeff128_oem, - const struct core_gamma *ramp, - const struct core_surface *surface, - uint32_t hw_points_num, - const struct hw_x_point *coordinate_x, - const struct gamma_pixel *axis_x, - struct dividers dividers) -{ - uint32_t i; - - struct gamma_coefficients coeff; - struct pwl_float_data_ex *rgb = rgb_regamma; - const struct hw_x_point *coord_x = coordinate_x; - - build_regamma_coefficients(&coeff); - - /* Use opp110->regamma.coordinates_x to retrieve - * coordinates chosen base on given user curve (future task). - * The x values are exponentially distributed and currently - * it is hard-coded, the user curve shape is ignored. - * The future task is to recalculate opp110- - * regamma.coordinates_x based on input/user curve, - * translation from 256/1025 to 128 pwl points. - */ - - i = 0; - - while (i != hw_points_num + 1) { - rgb->r = translate_from_linear_space_ex( - coord_x->adjusted_x, &coeff, 0); - rgb->g = translate_from_linear_space_ex( - coord_x->adjusted_x, &coeff, 1); - rgb->b = translate_from_linear_space_ex( - coord_x->adjusted_x, &coeff, 2); - - ++coord_x; - ++rgb; - ++i; - } -} - -static bool scale_gamma(struct pwl_float_data *pwl_rgb, - const struct core_gamma *ramp, - struct dividers dividers) -{ - const struct dc_gamma *gamma = &ramp->public; - const uint16_t max_driver = 0xFFFF; - const uint16_t max_os = 0xFF00; - uint16_t scaler = max_os; - uint32_t i = 0; - struct pwl_float_data *rgb = pwl_rgb; - struct pwl_float_data *rgb_last = rgb + INPUT_LUT_ENTRIES - 1; - - do { - if ((gamma->red[i] > max_os) || - (gamma->green[i] > max_os) || - (gamma->blue[i] > max_os)) { - scaler = max_driver; - break; - } - ++i; - } while (i != INPUT_LUT_ENTRIES); - - i = 0; - - do { - rgb->r = dal_fixed31_32_from_fraction( - gamma->red[i], scaler); - rgb->g = dal_fixed31_32_from_fraction( - gamma->green[i], scaler); - rgb->b = dal_fixed31_32_from_fraction( - gamma->blue[i], scaler); - - ++rgb; - ++i; - } while (i != INPUT_LUT_ENTRIES); - - rgb->r = dal_fixed31_32_mul(rgb_last->r, - dividers.divider1); - rgb->g = dal_fixed31_32_mul(rgb_last->g, - dividers.divider1); - rgb->b = dal_fixed31_32_mul(rgb_last->b, - dividers.divider1); - - ++rgb; - - rgb->r = dal_fixed31_32_mul(rgb_last->r, - dividers.divider2); - rgb->g = dal_fixed31_32_mul(rgb_last->g, - dividers.divider2); - rgb->b = dal_fixed31_32_mul(rgb_last->b, - dividers.divider2); - - ++rgb; - - rgb->r = dal_fixed31_32_mul(rgb_last->r, - dividers.divider3); - rgb->g = dal_fixed31_32_mul(rgb_last->g, - dividers.divider3); - rgb->b = dal_fixed31_32_mul(rgb_last->b, - dividers.divider3); - - return true; -} - -static void build_evenly_distributed_points( - struct gamma_pixel *points, - uint32_t numberof_points, - struct fixed31_32 max_value, - struct dividers dividers) -{ - struct gamma_pixel *p = points; - struct gamma_pixel *p_last = p + numberof_points - 1; - - uint32_t i = 0; - - do { - struct fixed31_32 value = dal_fixed31_32_div_int( - dal_fixed31_32_mul_int(max_value, i), - numberof_points - 1); - - p->r = value; - p->g = value; - p->b = value; - - ++p; - ++i; - } while (i != numberof_points); - - p->r = dal_fixed31_32_div(p_last->r, dividers.divider1); - p->g = dal_fixed31_32_div(p_last->g, dividers.divider1); - p->b = dal_fixed31_32_div(p_last->b, dividers.divider1); - - ++p; - - p->r = dal_fixed31_32_div(p_last->r, dividers.divider2); - p->g = dal_fixed31_32_div(p_last->g, dividers.divider2); - p->b = dal_fixed31_32_div(p_last->b, dividers.divider2); - - ++p; - - p->r = dal_fixed31_32_div(p_last->r, dividers.divider3); - p->g = dal_fixed31_32_div(p_last->g, dividers.divider3); - p->b = dal_fixed31_32_div(p_last->b, dividers.divider3); -} - -static inline void copy_rgb_regamma_to_coordinates_x( - struct hw_x_point *coordinates_x, - uint32_t hw_points_num, - const struct pwl_float_data_ex *rgb_ex) -{ - struct hw_x_point *coords = coordinates_x; - uint32_t i = 0; - const struct pwl_float_data_ex *rgb_regamma = rgb_ex; - - while (i <= hw_points_num) { - coords->regamma_y_red = rgb_regamma->r; - coords->regamma_y_green = rgb_regamma->g; - coords->regamma_y_blue = rgb_regamma->b; - - ++coords; - ++rgb_regamma; - ++i; - } -} - -static bool calculate_interpolated_hardware_curve( - struct pwl_result_data *rgb, - struct pixel_gamma_point *coeff128, - struct pwl_float_data *rgb_user, - const struct hw_x_point *coordinates_x, - const struct gamma_pixel *axis_x_256, - uint32_t number_of_points, - enum surface_pixel_format pixel_format) -{ - - const struct pixel_gamma_point *coeff; - struct pixel_gamma_point *coeff_128 = coeff128; - uint32_t max_entries = 3 - 1; - struct pwl_result_data *rgb_resulted = rgb; - - uint32_t i = 0; - - if (!build_oem_custom_gamma_mapping_coefficients( - coeff_128, coordinates_x, axis_x_256, - number_of_points, - pixel_format)) - return false; - - coeff = coeff128; - max_entries += INPUT_LUT_ENTRIES; - - /* TODO: float point case */ - - while (i <= number_of_points) { - rgb_resulted->red = calculate_mapped_value( - rgb_user, coeff, CHANNEL_NAME_RED, max_entries); - rgb_resulted->green = calculate_mapped_value( - rgb_user, coeff, CHANNEL_NAME_GREEN, max_entries); - rgb_resulted->blue = calculate_mapped_value( - rgb_user, coeff, CHANNEL_NAME_BLUE, max_entries); - - ++coeff; - ++rgb_resulted; - ++i; - } - - return true; -} - -static bool map_regamma_hw_to_x_user( - struct pixel_gamma_point *coeff128, - struct pwl_float_data *rgb_oem, - struct pwl_result_data *rgb_resulted, - struct pwl_float_data *rgb_user, - struct hw_x_point *coords_x, - const struct gamma_pixel *axis_x, - const struct dc_gamma *gamma, - const struct pwl_float_data_ex *rgb_regamma, - struct dividers dividers, - uint32_t hw_points_num, - const struct core_surface *surface) -{ - /* setup to spare calculated ideal regamma values */ - - struct pixel_gamma_point *coeff = coeff128; - - struct hw_x_point *coords = coords_x; - - copy_rgb_regamma_to_coordinates_x(coords, hw_points_num, rgb_regamma); - - return calculate_interpolated_hardware_curve( - rgb_resulted, coeff, rgb_user, coords, axis_x, - hw_points_num, surface->public.format); -} - -static void build_new_custom_resulted_curve( - struct pwl_result_data *rgb_resulted, - uint32_t hw_points_num) -{ - struct pwl_result_data *rgb = rgb_resulted; - struct pwl_result_data *rgb_plus_1 = rgb + 1; - - uint32_t i; - - i = 0; - - while (i != hw_points_num + 1) { - rgb->red = dal_fixed31_32_clamp( - rgb->red, dal_fixed31_32_zero, - dal_fixed31_32_one); - rgb->green = dal_fixed31_32_clamp( - rgb->green, dal_fixed31_32_zero, - dal_fixed31_32_one); - rgb->blue = dal_fixed31_32_clamp( - rgb->blue, dal_fixed31_32_zero, - dal_fixed31_32_one); - - ++rgb; - ++i; - } - - rgb = rgb_resulted; - - i = 1; - - while (i != hw_points_num + 1) { - if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) - rgb_plus_1->red = rgb->red; - if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) - rgb_plus_1->green = rgb->green; - if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) - rgb_plus_1->blue = rgb->blue; - - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); - - ++rgb_plus_1; - ++rgb; - ++i; - } -} - -static void rebuild_curve_configuration_magic( - struct curve_points *arr_points, - struct pwl_result_data *rgb_resulted, - const struct hw_x_point *coordinates_x, - uint32_t hw_points_num, - enum dc_transfer_func_predefined tf) -{ - struct fixed31_32 y_r; - struct fixed31_32 y_g; - struct fixed31_32 y_b; - - struct fixed31_32 y1_min; - struct fixed31_32 y3_max; - - y_r = rgb_resulted[0].red; - y_g = rgb_resulted[0].green; - y_b = rgb_resulted[0].blue; - - y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); - - arr_points[0].x = coordinates_x[0].adjusted_x; - arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); - - /* this should be cleaned up as it's confusing my understanding (KK) is - * that REGAMMA_CNTLA_EXP_REGION_END is the X value for the region end - * REGAMMA_CNTLA_EXP_REGION_END_BASE is Y value for the above X - * REGAMMA_CNTLA_EXP_REGION_END_SLOPE is the slope beyond (X,Y) above - * currently when programming REGION_END = m_arrPoints[1].x, - * REGION_END_BASE = m_arrPoints[1].y, REGION_END_SLOPE=1 - * we don't use m_arrPoints[2] at all after this function, - * and its purpose isn't clear to me - */ - arr_points[1].x = coordinates_x[hw_points_num].adjusted_x; - arr_points[2].x = coordinates_x[hw_points_num].adjusted_x; - - y_r = rgb_resulted[hw_points_num].red; - y_g = rgb_resulted[hw_points_num].green; - y_b = rgb_resulted[hw_points_num].blue; - - /* see comment above, m_arrPoints[1].y should be the Y value for the - * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) - */ - y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); - - arr_points[1].y = y3_max; - arr_points[2].y = y3_max; - - arr_points[2].slope = dal_fixed31_32_zero; - - /* for PQ, we want to have a straight line from last HW X point, and the - * slope to be such that we hit 1.0 at 10000 nits. - */ - if (tf == TRANSFER_FUNCTION_PQ) { - const struct fixed31_32 end_value = - dal_fixed31_32_from_int(125); - - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); - } -} - -static bool convert_to_custom_float_format( - struct fixed31_32 value, - const struct custom_float_format *format, - uint32_t *result) -{ - uint32_t mantissa; - uint32_t exponenta; - bool negative; - - return build_custom_float( - value, format, &negative, &mantissa, &exponenta) && - setup_custom_float( - format, negative, mantissa, exponenta, result); -} - -static bool convert_to_custom_float( - struct pwl_result_data *rgb_resulted, - struct curve_points *arr_points, - uint32_t hw_points_num) -{ - struct custom_float_format fmt; - - struct pwl_result_data *rgb = rgb_resulted; - - uint32_t i = 0; - - fmt.exponenta_bits = 6; - fmt.mantissa_bits = 12; - fmt.sign = true; - - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { - BREAK_TO_DEBUGGER(); - return false; - } - - fmt.mantissa_bits = 10; - fmt.sign = false; - - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - arr_points[2].slope, - &fmt, - &arr_points[2].custom_float_slope)) { - BREAK_TO_DEBUGGER(); - return false; - } - - fmt.mantissa_bits = 12; - fmt.sign = true; - - while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { - BREAK_TO_DEBUGGER(); - return false; - } - - ++rgb; - ++i; - } - - return true; -} - -bool calculate_regamma_params(struct pwl_params *params, - const struct core_gamma *ramp, - const struct core_surface *surface, - const struct core_stream *stream) -{ - struct gamma_curve *arr_curve_points = params->arr_curve_points; - struct curve_points *arr_points = params->arr_points; - struct pwl_result_data *rgb_resulted = params->rgb_resulted; - struct dividers dividers; - - struct hw_x_point *coordinates_x = NULL; - struct pwl_float_data *rgb_user = NULL ; - struct pwl_float_data_ex *rgb_regamma = NULL; - struct pwl_float_data *rgb_oem = NULL; - struct gamma_pixel *axix_x_256 = NULL; - struct pixel_gamma_point *coeff128_oem = NULL; - struct pixel_gamma_point *coeff128 = NULL; - - enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB; - - bool ret = false; - - coordinates_x = dm_alloc(sizeof(*coordinates_x)*(256 + 3)); - if (!coordinates_x) - goto coordinates_x_alloc_fail; - rgb_user = dm_alloc(sizeof(*rgb_user) * (TRANSFER_FUNC_POINTS + 3)); - if (!rgb_user) - goto rgb_user_alloc_fail; - rgb_regamma = dm_alloc(sizeof(*rgb_regamma) * (256 + 3)); - if (!rgb_regamma) - goto rgb_regamma_alloc_fail; - rgb_oem = dm_alloc(sizeof(*rgb_oem) * (TRANSFER_FUNC_POINTS + 3)); - if (!rgb_oem) - goto rgb_oem_alloc_fail; - axix_x_256 = dm_alloc(sizeof(*axix_x_256) * (256 + 3)); - if (!axix_x_256) - goto axix_x_256_alloc_fail; - coeff128_oem = dm_alloc(sizeof(*coeff128_oem) * (256 + 3)); - if (!coeff128_oem) - goto coeff128_oem_alloc_fail; - coeff128 = dm_alloc(sizeof(*coeff128) * (256 + 3)); - if (!coeff128) - goto coeff128_alloc_fail; - - dividers.divider1 = dal_fixed31_32_from_fraction(3, 2); - dividers.divider2 = dal_fixed31_32_from_int(2); - dividers.divider3 = dal_fixed31_32_from_fraction(5, 2); - - if (stream->public.out_transfer_func) - tf = stream->public.out_transfer_func->tf; - - build_evenly_distributed_points( - axix_x_256, - 256, - dal_fixed31_32_one, - dividers); - - scale_gamma(rgb_user, ramp, dividers); - - if (tf == TRANSFER_FUNCTION_PQ) { - setup_distribution_points_pq(arr_curve_points, arr_points, - ¶ms->hw_points_num, coordinates_x, - surface->public.format); - build_regamma_curve_pq(rgb_regamma, rgb_oem, coeff128_oem, - ramp, surface, params->hw_points_num, - coordinates_x, axix_x_256, dividers); - } else { - setup_distribution_points(arr_curve_points, arr_points, - ¶ms->hw_points_num, coordinates_x); - build_regamma_curve(rgb_regamma, rgb_oem, coeff128_oem, - ramp, surface, params->hw_points_num, - coordinates_x, axix_x_256, dividers); - } - - map_regamma_hw_to_x_user(coeff128, rgb_oem, rgb_resulted, rgb_user, - coordinates_x, axix_x_256, &ramp->public, rgb_regamma, - dividers, params->hw_points_num, surface); - - build_new_custom_resulted_curve(rgb_resulted, params->hw_points_num); - - rebuild_curve_configuration_magic( - arr_points, - rgb_resulted, - coordinates_x, - params->hw_points_num, - tf); - - convert_to_custom_float(rgb_resulted, arr_points, - params->hw_points_num); - - ret = true; - - dm_free(coeff128); -coeff128_alloc_fail: - dm_free(coeff128_oem); -coeff128_oem_alloc_fail: - dm_free(axix_x_256); -axix_x_256_alloc_fail: - dm_free(rgb_oem); -rgb_oem_alloc_fail: - dm_free(rgb_regamma); -rgb_regamma_alloc_fail: - dm_free(rgb_user); -rgb_user_alloc_fail: - dm_free(coordinates_x); -coordinates_x_alloc_fail: - return ret; - -} - diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7d4299b9ee1f..948f82a56472 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1519,23 +1519,23 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda if (dc->debug.disable_color_module) continue; /* skip below color updates */ - if (updates[i].hdr_static_metadata) { - resource_build_info_frame(pipe_ctx); - core_dc->hwss.update_info_frame(pipe_ctx); - } if (is_new_pipe_surface[j] || updates[i].in_transfer_func) core_dc->hwss.set_input_transfer_func( pipe_ctx, pipe_ctx->surface); if (is_new_pipe_surface[j] || - updates[i].gamma || updates[i].out_transfer_func) core_dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->surface, pipe_ctx->stream); + if (updates[i].hdr_static_metadata) { + resource_build_info_frame(pipe_ctx); + core_dc->hwss.update_info_frame(pipe_ctx); + } + } if (apply_ctx) { core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b814e7b76bbc..f53b41339951 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -213,11 +213,14 @@ enum dc_transfer_func_type { }; struct dc_transfer_func_distributed_points { - uint16_t red[TRANSFER_FUNC_POINTS]; - uint16_t green[TRANSFER_FUNC_POINTS]; - uint16_t blue[TRANSFER_FUNC_POINTS]; + struct fixed31_32 red[TRANSFER_FUNC_POINTS]; + struct fixed31_32 green[TRANSFER_FUNC_POINTS]; + struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; + uint16_t end_exponent; - uint16_t x_point_at_y1; + uint16_t x_point_at_y1_red; + uint16_t x_point_at_y1_green; + uint16_t x_point_at_y1_blue; }; enum dc_transfer_func_predefined { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 415b12accd2c..6e70cf7b99ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -42,7 +42,6 @@ #include "stream_encoder.h" #include "link_encoder.h" #include "clock_source.h" -#include "gamma_calcs.h" #include "audio.h" #include "dce/dce_hwseq.h" @@ -286,6 +285,436 @@ static bool dce110_set_input_transfer_func( return result; } +static bool build_custom_float( + struct fixed31_32 value, + const struct custom_float_format *format, + bool *negative, + uint32_t *mantissa, + uint32_t *exponenta) +{ + uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; + + const struct fixed31_32 mantissa_constant_plus_max_fraction = + dal_fixed31_32_from_fraction( + (1LL << (format->mantissa_bits + 1)) - 1, + 1LL << format->mantissa_bits); + + struct fixed31_32 mantiss; + + if (dal_fixed31_32_eq( + value, + dal_fixed31_32_zero)) { + *negative = false; + *mantissa = 0; + *exponenta = 0; + return true; + } + + if (dal_fixed31_32_lt( + value, + dal_fixed31_32_zero)) { + *negative = format->sign; + value = dal_fixed31_32_neg(value); + } else { + *negative = false; + } + + if (dal_fixed31_32_lt( + value, + dal_fixed31_32_one)) { + uint32_t i = 1; + + do { + value = dal_fixed31_32_shl(value, 1); + ++i; + } while (dal_fixed31_32_lt( + value, + dal_fixed31_32_one)); + + --i; + + if (exp_offset <= i) { + *mantissa = 0; + *exponenta = 0; + return true; + } + + *exponenta = exp_offset - i; + } else if (dal_fixed31_32_le( + mantissa_constant_plus_max_fraction, + value)) { + uint32_t i = 1; + + do { + value = dal_fixed31_32_shr(value, 1); + ++i; + } while (dal_fixed31_32_lt( + mantissa_constant_plus_max_fraction, + value)); + + *exponenta = exp_offset + i - 1; + } else { + *exponenta = exp_offset; + } + + mantiss = dal_fixed31_32_sub( + value, + dal_fixed31_32_one); + + if (dal_fixed31_32_lt( + mantiss, + dal_fixed31_32_zero) || + dal_fixed31_32_lt( + dal_fixed31_32_one, + mantiss)) + mantiss = dal_fixed31_32_zero; + else + mantiss = dal_fixed31_32_shl( + mantiss, + format->mantissa_bits); + + *mantissa = dal_fixed31_32_floor(mantiss); + + return true; +} + +static bool setup_custom_float( + const struct custom_float_format *format, + bool negative, + uint32_t mantissa, + uint32_t exponenta, + uint32_t *result) +{ + uint32_t i = 0; + uint32_t j = 0; + + uint32_t value = 0; + + /* verification code: + * once calculation is ok we can remove it + */ + + const uint32_t mantissa_mask = + (1 << (format->mantissa_bits + 1)) - 1; + + const uint32_t exponenta_mask = + (1 << (format->exponenta_bits + 1)) - 1; + + if (mantissa & ~mantissa_mask) { + BREAK_TO_DEBUGGER(); + mantissa = mantissa_mask; + } + + if (exponenta & ~exponenta_mask) { + BREAK_TO_DEBUGGER(); + exponenta = exponenta_mask; + } + + /* end of verification code */ + + while (i < format->mantissa_bits) { + uint32_t mask = 1 << i; + + if (mantissa & mask) + value |= mask; + + ++i; + } + + while (j < format->exponenta_bits) { + uint32_t mask = 1 << j; + + if (exponenta & mask) + value |= mask << i; + + ++j; + } + + if (negative && format->sign) + value |= 1 << (i + j); + + *result = value; + + return true; +} + +static bool convert_to_custom_float_format( + struct fixed31_32 value, + const struct custom_float_format *format, + uint32_t *result) +{ + uint32_t mantissa; + uint32_t exponenta; + bool negative; + + return build_custom_float( + value, format, &negative, &mantissa, &exponenta) && + setup_custom_float( + format, negative, mantissa, exponenta, result); +} + +static bool convert_to_custom_float( + struct pwl_result_data *rgb_resulted, + struct curve_points *arr_points, + uint32_t hw_points_num) +{ + struct custom_float_format fmt; + + struct pwl_result_data *rgb = rgb_resulted; + + uint32_t i = 0; + + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = true; + + if (!convert_to_custom_float_format( + arr_points[0].x, + &fmt, + &arr_points[0].custom_float_x)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + arr_points[0].offset, + &fmt, + &arr_points[0].custom_float_offset)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + arr_points[0].slope, + &fmt, + &arr_points[0].custom_float_slope)) { + BREAK_TO_DEBUGGER(); + return false; + } + + fmt.mantissa_bits = 10; + fmt.sign = false; + + if (!convert_to_custom_float_format( + arr_points[1].x, + &fmt, + &arr_points[1].custom_float_x)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + arr_points[1].y, + &fmt, + &arr_points[1].custom_float_y)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + arr_points[2].slope, + &fmt, + &arr_points[2].custom_float_slope)) { + BREAK_TO_DEBUGGER(); + return false; + } + + fmt.mantissa_bits = 12; + fmt.sign = true; + + while (i != hw_points_num) { + if (!convert_to_custom_float_format( + rgb->red, + &fmt, + &rgb->red_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + rgb->green, + &fmt, + &rgb->green_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + rgb->blue, + &fmt, + &rgb->blue_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + rgb->delta_red, + &fmt, + &rgb->delta_red_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + rgb->delta_green, + &fmt, + &rgb->delta_green_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + if (!convert_to_custom_float_format( + rgb->delta_blue, + &fmt, + &rgb->delta_blue_reg)) { + BREAK_TO_DEBUGGER(); + return false; + } + + ++rgb; + ++i; + } + + return true; +} + +static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func + *output_tf, struct pwl_params *regamma_params) +{ + if (output_tf == NULL || regamma_params == NULL) + return false; + + struct gamma_curve *arr_curve_points = regamma_params->arr_curve_points; + struct curve_points *arr_points = regamma_params->arr_points; + struct pwl_result_data *rgb_resulted = regamma_params->rgb_resulted; + struct fixed31_32 y_r; + struct fixed31_32 y_g; + struct fixed31_32 y_b; + struct fixed31_32 y1_min; + struct fixed31_32 y3_max; + + int32_t segment_start, segment_end; + uint32_t hw_points, start_index; + uint32_t i, j; + + memset(regamma_params, 0, sizeof(struct pwl_params)); + + if (output_tf->tf == TRANSFER_FUNCTION_PQ) { + /* 16 segments x 16 points + * segments are from 2^-11 to 2^5 + */ + segment_start = -11; + segment_end = 5; + + } else { + /* 10 segments x 16 points + * segment is from 2^-10 to 2^0 + */ + segment_start = -10; + segment_end = 0; + } + + hw_points = (segment_end - segment_start) * 16; + j = 0; + /* (segment + 25) * 32, every 2nd point */ + start_index = (segment_start + 25) * 32; + for (i = start_index; i <= 1025; i += 2) { + if (j > hw_points) + break; + rgb_resulted[j].red = output_tf->tf_pts.red[i]; + rgb_resulted[j].green = output_tf->tf_pts.green[i]; + rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; + j++; + } + + arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), + dal_fixed31_32_from_int(segment_start)); + arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), + dal_fixed31_32_from_int(segment_end)); + arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), + dal_fixed31_32_from_int(segment_end)); + + y_r = rgb_resulted[0].red; + y_g = rgb_resulted[0].green; + y_b = rgb_resulted[0].blue; + + y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); + + arr_points[0].y = y1_min; + arr_points[0].slope = dal_fixed31_32_div( + arr_points[0].y, + arr_points[0].x); + + y_r = rgb_resulted[hw_points - 1].red; + y_g = rgb_resulted[hw_points - 1].green; + y_b = rgb_resulted[hw_points - 1].blue; + + /* see comment above, m_arrPoints[1].y should be the Y value for the + * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) + */ + y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); + + arr_points[1].y = y3_max; + arr_points[2].y = y3_max; + + arr_points[1].slope = dal_fixed31_32_zero; + arr_points[2].slope = dal_fixed31_32_zero; + + if (output_tf->tf == TRANSFER_FUNCTION_PQ) { + /* for PQ, we want to have a straight line from last HW X point, + * and the slope to be such that we hit 1.0 at 10000 nits. + */ + const struct fixed31_32 end_value = + dal_fixed31_32_from_int(125); + + arr_points[1].slope = dal_fixed31_32_div( + dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), + dal_fixed31_32_sub(end_value, arr_points[1].x)); + arr_points[2].slope = dal_fixed31_32_div( + dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), + dal_fixed31_32_sub(end_value, arr_points[1].x)); + } + + regamma_params->hw_points_num = hw_points; + + for (i = 0; i < segment_end - segment_start; i++) { + regamma_params->arr_curve_points[i].offset = i * 16; + regamma_params->arr_curve_points[i].segments_num = 4; + } + + struct pwl_result_data *rgb = rgb_resulted; + struct pwl_result_data *rgb_plus_1 = rgb_resulted + 1; + + i = 1; + + while (i != hw_points + 1) { + if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) + rgb_plus_1->red = rgb->red; + if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) + rgb_plus_1->green = rgb->green; + if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) + rgb_plus_1->blue = rgb->blue; + + rgb->delta_red = dal_fixed31_32_sub( + rgb_plus_1->red, + rgb->red); + rgb->delta_green = dal_fixed31_32_sub( + rgb_plus_1->green, + rgb->green); + rgb->delta_blue = dal_fixed31_32_sub( + rgb_plus_1->blue, + rgb->blue); + + ++rgb_plus_1; + ++rgb; + ++i; + } + + convert_to_custom_float(rgb_resulted, arr_points, hw_points); + + return true; +} + static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, const struct core_surface *surface, /* Surface - To be removed */ @@ -308,10 +737,13 @@ static bool dce110_set_output_transfer_func( opp->funcs->opp_power_on_regamma_lut(opp, true); if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { + stream->public.out_transfer_func->type == + TF_TYPE_PREDEFINED && + stream->public.out_transfer_func->tf == + TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); - } else if (ramp && calculate_regamma_params(regamma_params, ramp, surface, stream)) { + } else if (dce110_translate_regamma_to_hw_format( + stream->public.out_transfer_func, regamma_params)) { opp->funcs->opp_program_regamma_pwl(opp, regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { diff --git a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h deleted file mode 100644 index 0712268856c2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * gamma_calcs.h - * - * Created on: Feb 9, 2016 - * Author: yonsun - */ - -#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ -#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ - -#include "opp.h" -#include "core_types.h" -#include "dc.h" - -bool calculate_regamma_params(struct pwl_params *params, - const struct core_gamma *ramp, - const struct core_surface *surface, - const struct core_stream *stream); - -#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index a1f31a4410a3..bef5e2cacbe3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -138,9 +138,7 @@ struct custom_float_value { struct hw_x_point { uint32_t custom_float_x; - uint32_t custom_float_x_adjusted; struct fixed31_32 x; - struct fixed31_32 adjusted_x; struct fixed31_32 regamma_y_red; struct fixed31_32 regamma_y_green; struct fixed31_32 regamma_y_blue; diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index c28de167250f..5a4364dfd2f7 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -190,6 +190,14 @@ struct fixed31_32 dal_fixed31_32_add( struct fixed31_32 arg1, struct fixed31_32 arg2); +/* + * @brief + * result = arg1 + arg2 + */ +struct fixed31_32 dal_fixed31_32_add_int( + struct fixed31_32 arg1, + int32_t arg2); + /* * @brief * result = arg1 - arg2 -- cgit v1.2.3-59-g8ed1b From cc0cb445ae56890a322abe2cc8df63b1ccab74fb Mon Sep 17 00:00:00 2001 From: Leon Elazar Date: Wed, 11 Jan 2017 14:33:36 -0500 Subject: drm/amd/display: Fixing some fallout from dc_target removal Also avoid allocating memory dce110_set_output_transfer_func if not needed Signed-off-by: Leon Elazar Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +++-- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 7 +++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 30 +++++----------------- .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 7 +++++ .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 6 ++++- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 4 +++ .../drm/amd/display/dc/dce110/dce110_resource.c | 17 +++++++++--- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 1 - drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + 9 files changed, 49 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index bc1f387d1992..47816c5ee0e0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -192,7 +192,8 @@ bool dc_stream_set_cursor_attributes( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if (pipe_ctx->stream == stream) { + if ((pipe_ctx->stream == stream) && + (pipe_ctx->ipp != NULL)) { struct input_pixel_processor *ipp = pipe_ctx->ipp; if (ipp->funcs->ipp_cursor_set_attributes( @@ -231,7 +232,8 @@ bool dc_stream_set_cursor_position( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if (pipe_ctx->stream == stream) { + if ((pipe_ctx->stream == stream) && + (pipe_ctx->ipp != NULL)) { struct input_pixel_processor *ipp = pipe_ctx->ipp; struct dc_cursor_mi_param param = { .pixel_clk_khz = dc_stream->timing.pix_clk_khz, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 167f523df657..061de9e8249d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -973,6 +973,10 @@ bool dce110_opp_construct(struct dce110_opp *opp110, opp110->base.inst = inst; + opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params)); + if (opp110->base.regamma_params == NULL) + return false; + opp110->regs = regs; opp110->opp_shift = opp_shift; opp110->opp_mask = opp_mask; @@ -982,6 +986,9 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp) { + dm_free((*opp)->regamma_params); + (*opp)->regamma_params = NULL; + dm_free(FROM_DCE11_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6e70cf7b99ef..1a9ba127b781 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -721,43 +721,27 @@ static bool dce110_set_output_transfer_func( const struct core_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; - const struct core_gamma *ramp = NULL; - struct pwl_params *regamma_params; - bool result = false; - - if (surface->public.gamma_correction) - ramp = DC_GAMMA_TO_CORE(surface->public.gamma_correction); - - regamma_params = dm_alloc(sizeof(struct pwl_params)); - if (regamma_params == NULL) - goto regamma_alloc_fail; - - regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; opp->funcs->opp_power_on_regamma_lut(opp, true); + opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + stream->public.out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->public.out_transfer_func, regamma_params)) { - opp->funcs->opp_program_regamma_pwl(opp, regamma_params); - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); + stream->public.out_transfer_func, opp->regamma_params)) { + opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params); + opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); } opp->funcs->opp_power_on_regamma_lut(opp, false); - result = true; - - dm_free(regamma_params); - -regamma_alloc_fail: - return result; + return true; } static enum dc_status bios_parser_crtc_source_select( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index 8164aa6bcb00..876445f14c85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -548,3 +548,10 @@ void dce110_opp_power_on_regamma_lut_v( dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value); } + +void dce110_opp_set_regamma_mode_v( + struct output_pixel_processor *opp, + enum opp_regamma mode) +{ + // TODO: need to implement the function +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 0a9b384303d0..95b3d2eb8428 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -42,7 +42,7 @@ static const struct opp_funcs funcs = { .opp_set_csc_default = dce110_opp_v_set_csc_default, .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment, .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, - .opp_set_regamma_mode = dce110_opp_set_regamma_mode, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v, .opp_destroy = dce110_opp_destroy, .opp_program_fmt = dce110_opp_program_fmt, .opp_program_bit_depth_reduction = @@ -56,6 +56,10 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110, opp110->base.ctx = ctx; + opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params)); + if (opp110->base.regamma_params == NULL) + return false; + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h index ac5937786ce3..cb26c515d30f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -49,4 +49,8 @@ void dce110_opp_power_on_regamma_lut_v( struct output_pixel_processor *opp, bool power_on); +void dce110_opp_set_regamma_mode_v( + struct output_pixel_processor *opp, + enum opp_regamma mode); + #endif /* __DC_OPP_DCE110_V_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index cfbb4ef21f8b..82cddb6425a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1114,14 +1114,22 @@ static const struct resource_funcs dce110_res_pool_funcs = { dce110_resource_build_bit_depth_reduction_params }; -static void underlay_create(struct dc_context *ctx, struct resource_pool *pool) +static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) { struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); - dce110_opp_v_construct(dce110_oppv, ctx); + if ((dce110_tgv == NULL) || + (dce110_xfmv == NULL) || + (dce110_miv == NULL) || + (dce110_oppv == NULL)) + return false; + + if (!dce110_opp_v_construct(dce110_oppv, ctx)) + return false; + dce110_timing_generator_v_construct(dce110_tgv, ctx); dce110_mem_input_v_construct(dce110_miv, ctx); dce110_transform_v_construct(dce110_xfmv, ctx); @@ -1135,6 +1143,8 @@ static void underlay_create(struct dc_context *ctx, struct resource_pool *pool) /* update the public caps to indicate an underlay is available */ ctx->dc->caps.max_slave_planes = 1; ctx->dc->caps.max_slave_planes = 1; + + return true; } static void bw_calcs_data_update_from_pplib(struct core_dc *dc) @@ -1334,7 +1344,8 @@ static bool construct( } } - underlay_create(ctx, &pool->base); + if (!underlay_create(ctx, &pool->base)) + goto res_create_fail; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 3b0e616f7066..b8735b27e9bc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -65,7 +65,6 @@ struct pwl_result_data { }; struct pwl_params { - uint32_t *data; struct gamma_curve arr_curve_points[16]; struct curve_points arr_points[3]; struct pwl_result_data rgb_resulted[256 + 3]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index bef5e2cacbe3..a10c4e296960 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -202,6 +202,7 @@ enum opp_regamma { struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; + struct pwl_params *regamma_params; const struct opp_funcs *funcs; }; -- cgit v1.2.3-59-g8ed1b From 6235b23cb92ba5bf30430400b216ea2114afe777 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Sat, 14 Jan 2017 18:57:57 -0500 Subject: drm/amd/display: remove hw_crtc_timing Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 2 +- .../drm/amd/display/include/hw_sequencer_types.h | 40 ---------------------- 4 files changed, 3 insertions(+), 43 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index c510e95eb948..7e6661bda970 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -681,7 +681,7 @@ static void dce110_stream_encoder_dp_unblank( uint64_t m_vid_l = n_vid; - m_vid_l *= param->crtc_timing.pixel_clock; + m_vid_l *= param->pixel_clk_khz; m_vid_l = div_u64(m_vid_l, param->link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1a9ba127b781..b51668e3bb52 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -886,7 +886,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, struct encoder_unblank_param params = { { 0 } }; /* only 3 items below are used by unblank */ - params.crtc_timing.pixel_clock = + params.pixel_clk_khz = pipe_ctx->stream->public.timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index cb369af29d69..674bebfe3bd2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -36,8 +36,8 @@ struct encoder_info_frame { }; struct encoder_unblank_param { - struct hw_crtc_timing crtc_timing; struct dc_link_settings link_settings; + unsigned int pixel_clk_khz; }; struct encoder_set_dp_phy_pattern_param { diff --git a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h index 6bbca1b4d736..f99a03266149 100644 --- a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h +++ b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h @@ -40,46 +40,6 @@ struct drr_params { uint32_t vertical_total_max; }; -/* CRTC timing structure */ -struct hw_crtc_timing { - uint32_t h_total; - uint32_t h_addressable; - uint32_t h_overscan_left; - uint32_t h_overscan_right; - uint32_t h_sync_start; - uint32_t h_sync_width; - - uint32_t v_total; - uint32_t v_addressable; - uint32_t v_overscan_top; - uint32_t v_overscan_bottom; - uint32_t v_sync_start; - uint32_t v_sync_width; - - /* in KHz */ - uint32_t pixel_clock; - - struct { - uint32_t INTERLACED:1; - uint32_t DOUBLESCAN:1; - uint32_t PIXEL_REPETITION:4; /* 1...10 */ - uint32_t HSYNC_POSITIVE_POLARITY:1; - uint32_t VSYNC_POSITIVE_POLARITY:1; - /* frame should be packed for 3D - * (currently this refers to HDMI 1.4a FramePacking format */ - uint32_t HORZ_COUNT_BY_TWO:1; - uint32_t PACK_3D_FRAME:1; - /* 0 - left eye polarity, 1 - right eye polarity */ - uint32_t RIGHT_EYE_3D_POLARITY:1; - /* DVI-DL High-Color mode */ - uint32_t HIGH_COLOR_DL_MODE:1; - uint32_t Y_ONLY:1; - /* HDMI 2.0 - Support scrambling for TMDS character - * rates less than or equal to 340Mcsc */ - uint32_t LTE_340MCSC_SCRAMBLE:1; - } flags; -}; - /* TODO hw_info_frame and hw_info_packet structures are same as in encoder * merge it*/ struct hw_info_packet { -- cgit v1.2.3-59-g8ed1b From 306dadf01aba27bed2daa49a782b22586af64c93 Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Fri, 13 Jan 2017 16:19:36 -0500 Subject: drm/amd/display: Set default degamma to sRGB instead of bypass Signed-off-by: Amy Zhang Acked-by: Harry Wentland Reviewed-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index b51668e3bb52..ee393a168c84 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -255,7 +255,7 @@ static bool dce110_set_input_transfer_func( if (tf == NULL) { /* Default case if no input transfer function specified */ ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_BYPASS); + IPP_DEGAMMA_MODE_HW_sRGB); } else if (tf->public.type == TF_TYPE_PREDEFINED) { switch (tf->public.tf) { case TRANSFER_FUNCTION_SRGB: -- cgit v1.2.3-59-g8ed1b From 534db198866070fdb655423637afdce6cf0c05db Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Fri, 13 Jan 2017 16:49:26 -0500 Subject: drm/amd/display: HDR Enablement For Applications - Made sure dest color space is updated in stream and info frame - Optimized segment distribution algorithm for regamma mapping Signed-off-by: Amy Zhang Acked-by: Harry Wentland Reviewed-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++++ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 6 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 94 ++++++++++++++++++---- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 11 +++ 4 files changed, 107 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fe79a2890247..8b41c7708562 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1310,6 +1310,20 @@ static void set_avi_info_frame( info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 = COLORIMETRY_NO_DATA; + if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || + color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || + color_space == COLOR_SPACE_2020_YCBCR) { + info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 = + COLORIMETRYEX_BT2020RGBYCBCR; + info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 = + COLORIMETRY_EXTENDED; + } else if (color_space == COLOR_SPACE_ADOBERGB) { + info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 = + COLORIMETRYEX_ADOBERGB; + info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 = + COLORIMETRY_EXTENDED; + } + /* TODO: un-hardcode aspect ratio */ aspect = stream->public.timing.aspect_ratio; diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 00958bdbb417..a17e7bc96f9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -444,7 +444,11 @@ enum dc_color_space { COLOR_SPACE_YCBCR601, COLOR_SPACE_YCBCR709, COLOR_SPACE_YCBCR601_LIMITED, - COLOR_SPACE_YCBCR709_LIMITED + COLOR_SPACE_YCBCR709_LIMITED, + COLOR_SPACE_2020_RGB_FULLRANGE, + COLOR_SPACE_2020_RGB_LIMITEDRANGE, + COLOR_SPACE_2020_YCBCR, + COLOR_SPACE_ADOBERGB, }; enum dc_quantization_range { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ee393a168c84..e9fd83e9af79 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -594,39 +594,88 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func struct fixed31_32 y3_max; int32_t segment_start, segment_end; - uint32_t hw_points, start_index; - uint32_t i, j; + uint32_t i, j, k, seg_distr[16], increment, start_index; + uint32_t hw_points = 0; memset(regamma_params, 0, sizeof(struct pwl_params)); if (output_tf->tf == TRANSFER_FUNCTION_PQ) { - /* 16 segments x 16 points + /* 16 segments * segments are from 2^-11 to 2^5 */ segment_start = -11; segment_end = 5; + seg_distr[0] = 2; + seg_distr[1] = 2; + seg_distr[2] = 2; + seg_distr[3] = 2; + seg_distr[4] = 2; + seg_distr[5] = 2; + seg_distr[6] = 3; + seg_distr[7] = 4; + seg_distr[8] = 4; + seg_distr[9] = 4; + seg_distr[10] = 4; + seg_distr[11] = 5; + seg_distr[12] = 5; + seg_distr[13] = 5; + seg_distr[14] = 5; + seg_distr[15] = 5; + } else { - /* 10 segments x 16 points + /* 10 segments * segment is from 2^-10 to 2^0 */ segment_start = -10; segment_end = 0; + + seg_distr[0] = 3; + seg_distr[1] = 4; + seg_distr[2] = 4; + seg_distr[3] = 4; + seg_distr[4] = 4; + seg_distr[5] = 4; + seg_distr[6] = 4; + seg_distr[7] = 4; + seg_distr[8] = 5; + seg_distr[9] = 5; + seg_distr[10] = -1; + seg_distr[11] = -1; + seg_distr[12] = -1; + seg_distr[13] = -1; + seg_distr[14] = -1; + seg_distr[15] = -1; + } + + for (k = 0; k < 16; k++) { + if (seg_distr[k] != -1) + hw_points += (1 << seg_distr[k]); } - hw_points = (segment_end - segment_start) * 16; j = 0; - /* (segment + 25) * 32, every 2nd point */ - start_index = (segment_start + 25) * 32; - for (i = start_index; i <= 1025; i += 2) { - if (j > hw_points) - break; - rgb_resulted[j].red = output_tf->tf_pts.red[i]; - rgb_resulted[j].green = output_tf->tf_pts.green[i]; - rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; - j++; + for (k = 0; k < (segment_end - segment_start); k++) { + increment = 32 / (1 << seg_distr[k]); + start_index = (segment_start + k + 25) * 32; + for (i = start_index; i < start_index + 32; i += increment) { + if (j == hw_points - 1) + break; + rgb_resulted[j].red = output_tf->tf_pts.red[i]; + rgb_resulted[j].green = output_tf->tf_pts.green[i]; + rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; + j++; + } } + /* last point */ + start_index = (segment_end + 25) * 32; + rgb_resulted[hw_points - 1].red = + output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = + output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = + output_tf->tf_pts.blue[start_index]; + arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), @@ -677,11 +726,22 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func regamma_params->hw_points_num = hw_points; - for (i = 0; i < segment_end - segment_start; i++) { - regamma_params->arr_curve_points[i].offset = i * 16; - regamma_params->arr_curve_points[i].segments_num = 4; + i = 1; + for (k = 0; k < 16 && i < 16; k++) { + if (seg_distr[k] != -1) { + regamma_params->arr_curve_points[k].segments_num = + seg_distr[k]; + regamma_params->arr_curve_points[i].offset = + regamma_params->arr_curve_points[k]. + offset + (1 << seg_distr[k]); + } + i++; } + if (seg_distr[k] != -1) + regamma_params->arr_curve_points[k].segments_num = + seg_distr[k]; + struct pwl_result_data *rgb = rgb_resulted; struct pwl_result_data *rgb_plus_1 = rgb_resulted + 1; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index ef743b70b3e9..a510d3fe48ec 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -47,6 +47,17 @@ enum colorimetry { COLORIMETRY_EXTENDED = 3 }; +enum colorimetry_ext { + COLORIMETRYEX_XVYCC601 = 0, + COLORIMETRYEX_XVYCC709 = 1, + COLORIMETRYEX_SYCC601 = 2, + COLORIMETRYEX_ADOBEYCC601 = 3, + COLORIMETRYEX_ADOBERGB = 4, + COLORIMETRYEX_BT2020YCC = 5, + COLORIMETRYEX_BT2020RGBYCBCR = 6, + COLORIMETRYEX_RESERVED = 7 +}; + enum active_format_info { ACTIVE_FORMAT_NO_DATA = 0, ACTIVE_FORMAT_VALID = 1 -- cgit v1.2.3-59-g8ed1b From 8693049a896c2c3a2bb74f0efde62318636beaef Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Mon, 16 Jan 2017 20:50:47 -0500 Subject: drm/amd/display: rename BGRA8888 to ABGR8888 DC actually support ABGR8888 instead of BGRA8888 (R/B swap rather than endian swap) , rename to avoid confusion Signed-off-by: Tony Cheng Acked-by: Harry Wentland Reviewed-by: Yongqiang Sun Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c index 54388c0e29e0..946379852b2a 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c @@ -2530,7 +2530,7 @@ static void populate_initial_data( data->bytes_per_pixel[num_displays + 4] = 2; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: @@ -2626,7 +2626,7 @@ static void populate_initial_data( data->bytes_per_pixel[num_displays + 4] = 2; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 8b41c7708562..ee1c3b029394 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -341,7 +341,7 @@ static enum pixel_format convert_pixel_format_to_dalsurface( case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: dal_pixel_format = PIXEL_FORMAT_ARGB8888; break; - case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: dal_pixel_format = PIXEL_FORMAT_ARGB8888; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 5c1b2f833fe2..53c73de75da9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -174,7 +174,7 @@ enum surface_pixel_format { /*32 bpp*/ SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, /*32 bpp swaped*/ - SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, + SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, /*swaped*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 130935fffba3..e14a21cedfd5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -302,7 +302,7 @@ static void program_grph_pixel_format( uint32_t grph_depth, grph_format; uint32_t sign = 0, floating = 0; - if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 || + if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 || /*todo: doesn't look like we handle BGRA here, * should problem swap endian*/ format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 || @@ -331,7 +331,7 @@ static void program_grph_pixel_format( grph_format = 1; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: grph_depth = 2; grph_format = 0; break; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e9fd83e9af79..6dbfc570b8c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -214,7 +214,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, switch (surface->public.format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: prescale_params->scale = 0x2020; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index b12506adcba4..aac47955e9bf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -405,7 +405,7 @@ static void program_pixel_format( grph_format = 1; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: grph_depth = 2; grph_format = 0; break; -- cgit v1.2.3-59-g8ed1b From 9c1a57d79dbc96e808ea81aa1385f2d9d03570a0 Mon Sep 17 00:00:00 2001 From: Leon Elazar Date: Tue, 17 Jan 2017 16:16:04 -0500 Subject: drm/amd/display: check surface size is at least as large as stream Signed-off-by: Leon Elazar Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 82cddb6425a0..0b8f8927162f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -967,9 +967,9 @@ static bool dce110_validate_surface_sets( return false; if (set[i].surfaces[0]->src_rect.width - != set[i].stream->src.width + < set[i].stream->src.width || set[i].surfaces[0]->src_rect.height - != set[i].stream->src.height) + < set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index fa8699d3b9ef..7c12185b1dbe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -966,9 +966,9 @@ static bool dce112_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].stream->src.width + < set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].stream->src.height) + < set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) -- cgit v1.2.3-59-g8ed1b From 86e2e1bee07134f712cb6b807b7f0205057bd11e Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Fri, 20 Jan 2017 15:54:13 -0500 Subject: drm/amd/display: Check we got a stream in update_info_frame Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6dbfc570b8c6..ce56f23806bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -837,6 +837,11 @@ static enum dc_status bios_parser_crtc_source_select( void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) { + ASSERT(pipe_ctx->stream); + + if (pipe_ctx->stream_enc == NULL) + return; /* this is not root pipe */ + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( pipe_ctx->stream_enc, -- cgit v1.2.3-59-g8ed1b From 23ae4f8e59c926df806ba837b2a2040984077641 Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Tue, 24 Jan 2017 09:50:05 -0500 Subject: drm/amd/display: Fix Warnings - Remove mixed declarations and unused variables Signed-off-by: Amy Zhang Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 24 +++++++++++++--------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ce56f23806bc..c3e0865f3148 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -581,12 +581,10 @@ static bool convert_to_custom_float( static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, struct pwl_params *regamma_params) { - if (output_tf == NULL || regamma_params == NULL) - return false; - - struct gamma_curve *arr_curve_points = regamma_params->arr_curve_points; - struct curve_points *arr_points = regamma_params->arr_points; - struct pwl_result_data *rgb_resulted = regamma_params->rgb_resulted; + struct curve_points *arr_points; + struct pwl_result_data *rgb_resulted; + struct pwl_result_data *rgb; + struct pwl_result_data *rgb_plus_1; struct fixed31_32 y_r; struct fixed31_32 y_g; struct fixed31_32 y_b; @@ -594,8 +592,14 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func struct fixed31_32 y3_max; int32_t segment_start, segment_end; - uint32_t i, j, k, seg_distr[16], increment, start_index; - uint32_t hw_points = 0; + uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; + + if (output_tf == NULL || regamma_params == NULL) + return false; + + arr_points = regamma_params->arr_points; + rgb_resulted = regamma_params->rgb_resulted; + hw_points = 0; memset(regamma_params, 0, sizeof(struct pwl_params)); @@ -742,8 +746,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; - struct pwl_result_data *rgb = rgb_resulted; - struct pwl_result_data *rgb_plus_1 = rgb_resulted + 1; + rgb = rgb_resulted; + rgb_plus_1 = rgb_resulted + 1; i = 1; -- cgit v1.2.3-59-g8ed1b From 7ec6b963b17a51159c38e2446499a69edf5b20e5 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 25 Jan 2017 14:51:39 -0500 Subject: drm/amd/display: Expose hw sequencer gamma function Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c3e0865f3148..6acb9faf29f1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -578,7 +578,7 @@ static bool convert_to_custom_float( return true; } -static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func +bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, struct pwl_params *regamma_params) { struct curve_points *arr_points; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index a6b4d0d2429f..68632dd28155 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -58,5 +58,8 @@ void dce110_power_down(struct core_dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); +bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func + *output_tf, struct pwl_params *regamma_params); + #endif /* __DC_HWSS_DCE110_H__ */ -- cgit v1.2.3-59-g8ed1b From 5e7773a219f7821163ad2b17be0d02f8be8ce0c6 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Mon, 23 Jan 2017 16:55:20 -0500 Subject: drm/amd/display: DMCU Compile and Load Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 16 -- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12 -- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 214 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 157 +++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 127 ++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 91 +++++++++ .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 40 +--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 6 + .../drm/amd/display/dc/dce110/dce110_resource.c | 52 +++++ .../drm/amd/display/dc/dce112/dce112_resource.c | 51 +++++ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 + drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 40 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 42 ++++ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 1 - 16 files changed, 788 insertions(+), 70 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 474c2d42525d..152c694cc044 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -268,19 +268,6 @@ static bool init_dmcu_backlight_settings(struct dc *dc) return true; } - -static bool set_abm_level(struct dc *dc, unsigned int abm_level) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - int i; - - for (i = 0; i < core_dc->link_count; i++) - dc_link_set_abm_level(&core_dc->links[i]->public, - abm_level); - - return true; -} - static bool set_psr_enable(struct dc *dc, bool enable) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -409,9 +396,6 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) core_dc->public.stream_funcs.init_dmcu_backlight_settings = init_dmcu_backlight_settings; - core_dc->public.stream_funcs.set_abm_level = - set_abm_level; - core_dc->public.stream_funcs.set_psr_enable = set_psr_enable; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index f4f46d4f0cf0..84efc25d0e33 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1432,18 +1432,6 @@ bool dc_link_init_dmcu_backlight_settings(const struct dc_link *dc_link) return true; } -bool dc_link_set_abm_level(const struct dc_link *dc_link, uint32_t level) -{ - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - - dm_logger_write(ctx->logger, LOG_BACKLIGHT, - "New abm level: %d (0x%X)\n", level, level); - - link->link_enc->funcs->set_dmcu_abm_level(link->link_enc, level); - return true; -} - bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) { struct core_link *link = DC_LINK_TO_CORE(dc_link); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f485f70bf3ef..8cb53b626641 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -103,7 +103,6 @@ struct dc_stream_funcs { bool (*set_backlight)(struct dc *dc, unsigned int backlight_level, unsigned int frame_ramp, const struct dc_stream *stream); bool (*init_dmcu_backlight_settings)(struct dc *dc); - bool (*set_abm_level)(struct dc *dc, unsigned int abm_level); bool (*set_psr_enable)(struct dc *dc, bool enable); bool (*setup_psr)(struct dc *dc, const struct dc_stream *stream); }; @@ -575,8 +574,6 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, bool dc_link_init_dmcu_backlight_settings(const struct dc_link *dc_link); -bool dc_link_set_abm_level(const struct dc_link *dc_link, uint32_t level); - bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_setup_psr(const struct dc_link *dc_link, @@ -730,4 +727,5 @@ bool dc_submit_i2c( uint32_t link_index, struct i2c_command *cmd); + #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 5ad59a27738c..05562553b656 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -7,7 +7,7 @@ DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ -dce_clocks.o dce_opp.o +dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c new file mode 100644 index 000000000000..ce49bee8e038 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -0,0 +1,214 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce_abm.h" +#include "dm_services.h" +#include "reg_helper.h" +#include "fixed32_32.h" +#include "dc.h" + +#define TO_DCE_ABM(abm)\ + container_of(abm, struct dce_abm, base) + +#define REG(reg) \ + (abm_dce->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name + +#define CTX \ + abm_dce->base.ctx + +#define MCP_ABM_LEVEL_SET 0x65 + +static unsigned int get_current_backlight(struct dce_abm *abm_dce) +{ + uint64_t current_backlight; + uint32_t round_result; + uint32_t pwm_period_cntl, bl_period, bl_int_count; + uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en; + uint32_t bl_period_mask, bl_pwm_mask; + + pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); + REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); + REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); + + bl_pwm_cntl = REG_READ(BL_PWM_CNTL); + REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); + REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); + + if (bl_int_count == 0) + bl_int_count = 16; + + bl_period_mask = (1 << bl_int_count) - 1; + bl_period &= bl_period_mask; + + bl_pwm_mask = bl_period_mask << (16 - bl_int_count); + + if (fractional_duty_cycle_en == 0) + bl_pwm &= bl_pwm_mask; + else + bl_pwm &= 0xFFFF; + + current_backlight = bl_pwm << (1 + bl_int_count); + + if (bl_period == 0) + bl_period = 0xFFFF; + + current_backlight /= bl_period; + current_backlight = (current_backlight + 1) >> 1; + + current_backlight = (uint64_t)(current_backlight) * bl_period; + + round_result = (uint32_t)(current_backlight & 0xFFFFFFFF); + + round_result = (round_result >> (bl_int_count-1)) & 1; + + current_backlight >>= bl_int_count; + current_backlight += round_result; + + return (uint32_t)(current_backlight); +} + +void dce_abm_init(struct abm *abm) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + unsigned int backlight = get_current_backlight(abm_dce); + + REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); + REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); + REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); + REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); + REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); + + REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, + ABM1_HG_NUM_OF_BINS_SEL, 0, + ABM1_HG_VMAX_SEL, 1, + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0); + + REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, + ABM1_IPCSC_COEFF_SEL_R, 2, + ABM1_IPCSC_COEFF_SEL_G, 4, + ABM1_IPCSC_COEFF_SEL_B, 2); + + REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, + BL1_PWM_CURRENT_ABM_LEVEL, backlight); + + REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, + BL1_PWM_TARGET_ABM_LEVEL, backlight); + + REG_UPDATE(BL1_PWM_USER_LEVEL, + BL1_PWM_USER_LEVEL, backlight); + + REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, + ABM1_LS_MIN_PIXEL_VALUE_THRES, 0, + ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000); + + REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1, + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1, + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); +} + +bool dce_abm_set_level(struct abm *abm, uint32_t level) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + struct dc_context *ctx = abm_dce->base.ctx; + + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + unsigned int value; + + /* waitDMCUReadyForCmd */ + do { + dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval); + REG_GET(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, &value); + dmcu_max_retry_on_wait_reg_ready--; + } while + /* expected value is 0, loop while not 0*/ + ((value & abm_dce->abm_mask->MASTER_COMM_INTERRUPT) && + dmcu_max_retry_on_wait_reg_ready > 0); + + /* setDMCUParam_ABMLevel */ + REG_UPDATE_2(MASTER_COMM_CMD_REG, + MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, + MASTER_COMM_CMD_REG_BYTE2, level); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + return true; +} + +static const struct abm_funcs dce_funcs = { + .abm_init = dce_abm_init, + .set_abm_level = dce_abm_set_level, +}; + +static void dce_abm_construct( + struct dce_abm *abm_dce, + struct dc_context *ctx, + const struct dce_abm_registers *regs, + const struct dce_abm_shift *abm_shift, + const struct dce_abm_mask *abm_mask) +{ + struct abm *base = &abm_dce->base; + + base->ctx = ctx; + base->funcs = &dce_funcs; + + abm_dce->regs = regs; + abm_dce->abm_shift = abm_shift; + abm_dce->abm_mask = abm_mask; +} + +struct abm *dce_abm_create( + struct dc_context *ctx, + const struct dce_abm_registers *regs, + const struct dce_abm_shift *abm_shift, + const struct dce_abm_mask *abm_mask) +{ + struct dce_abm *abm_dce = dm_alloc(sizeof(*abm_dce)); + + if (abm_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask); + + abm_dce->base.funcs = &dce_funcs; + + return &abm_dce->base; +} + +void dce_abm_destroy(struct abm **abm) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(*abm); + + dm_free(abm_dce); + *abm = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h new file mode 100644 index 000000000000..cf40e303cbcf --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -0,0 +1,157 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#ifndef _DCE_ABM_H_ +#define _DCE_ABM_H_ + +#include "abm.h" + +#define ABM_COMMON_REG_LIST_DCE_BASE() \ + SR(BL_PWM_PERIOD_CNTL), \ + SR(BL_PWM_CNTL), \ + SR(MASTER_COMM_CNTL_REG), \ + SR(MASTER_COMM_CMD_REG) + +#define ABM_DCE110_COMMON_REG_LIST() \ + ABM_COMMON_REG_LIST_DCE_BASE(), \ + SR(DC_ABM1_HG_SAMPLE_RATE), \ + SR(DC_ABM1_LS_SAMPLE_RATE), \ + SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ + SR(DC_ABM1_HG_MISC_CTRL), \ + SR(DC_ABM1_IPCSC_COEFF_SEL), \ + SR(BL1_PWM_CURRENT_ABM_LEVEL), \ + SR(BL1_PWM_TARGET_ABM_LEVEL), \ + SR(BL1_PWM_USER_LEVEL), \ + SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ + SR(DC_ABM1_HGLS_REG_READ_PROGRESS) + +#define ABM_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \ + ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \ + ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \ + ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \ + ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ + ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ + ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) + +#define ABM_MASK_SH_LIST_DCE110(mask_sh) \ + ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + ABM_SF(DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) + +#define ABM_REG_FIELD_LIST(type) \ + type ABM1_HG_NUM_OF_BINS_SEL; \ + type ABM1_HG_VMAX_SEL; \ + type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ + type ABM1_IPCSC_COEFF_SEL_R; \ + type ABM1_IPCSC_COEFF_SEL_G; \ + type ABM1_IPCSC_COEFF_SEL_B; \ + type BL1_PWM_CURRENT_ABM_LEVEL; \ + type BL1_PWM_TARGET_ABM_LEVEL; \ + type BL1_PWM_USER_LEVEL; \ + type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ + type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ + type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ + type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ + type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ + type BL_PWM_PERIOD; \ + type BL_PWM_PERIOD_BITCNT; \ + type BL_ACTIVE_INT_FRAC_CNT; \ + type BL_PWM_FRACTIONAL_EN; \ + type MASTER_COMM_INTERRUPT; \ + type MASTER_COMM_CMD_REG_BYTE0; \ + type MASTER_COMM_CMD_REG_BYTE2 + +struct dce_abm_shift { + ABM_REG_FIELD_LIST(uint8_t); +}; + +struct dce_abm_mask { + ABM_REG_FIELD_LIST(uint32_t); +}; + +struct dce_abm_registers { + uint32_t BL_PWM_PERIOD_CNTL; + uint32_t BL_PWM_CNTL; + uint32_t DC_ABM1_HG_SAMPLE_RATE; + uint32_t DC_ABM1_LS_SAMPLE_RATE; + uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; + uint32_t DC_ABM1_HG_MISC_CTRL; + uint32_t DC_ABM1_IPCSC_COEFF_SEL; + uint32_t BL1_PWM_CURRENT_ABM_LEVEL; + uint32_t BL1_PWM_TARGET_ABM_LEVEL; + uint32_t BL1_PWM_USER_LEVEL; + uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; + uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; + uint32_t MASTER_COMM_CNTL_REG; + uint32_t MASTER_COMM_CMD_REG; +}; + +struct dce_abm { + struct abm base; + const struct dce_abm_registers *regs; + const struct dce_abm_shift *abm_shift; + const struct dce_abm_mask *abm_mask; +}; + +struct abm *dce_abm_create( + struct dc_context *ctx, + const struct dce_abm_registers *regs, + const struct dce_abm_shift *abm_shift, + const struct dce_abm_mask *abm_mask); + +void dce_abm_destroy(struct abm **abm); + +#endif /* _DCE_ABM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c new file mode 100644 index 000000000000..eb0e95f57aa9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -0,0 +1,127 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce_dmcu.h" +#include "dm_services.h" +#include "reg_helper.h" +#include "fixed32_32.h" +#include "dc.h" + +#define TO_DCE_DMCU(dmcu)\ + container_of(dmcu, struct dce_dmcu, base) + +#define REG(reg) \ + (dmcu_dce->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name + +#define CTX \ + dmcu_dce->base.ctx + +bool dce_dmcu_load_iram(struct dmcu *dmcu, + unsigned int start_offset, + const char *src, + unsigned int bytes) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int count = 0; + uint32_t status; + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_WR_ADDR_AUTO_INC, 1); + + do { + dm_delay_in_microseconds(dmcu->ctx, 2); + REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &status); + count++; + } while + ((status & dmcu_dce->dmcu_mask->DMCU_IRAM_MEM_PWR_STATE) && count < 10); + + REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); + + for (count = 0; count < bytes; count++) + REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_WR_ADDR_AUTO_INC, 0); + + return true; +} + +static const struct dmcu_funcs dce_funcs = { + .load_iram = dce_dmcu_load_iram, +}; + +static void dce_dmcu_construct( + struct dce_dmcu *dmcu_dce, + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask) +{ + struct dmcu *base = &dmcu_dce->base; + + base->ctx = ctx; + base->funcs = &dce_funcs; + + dmcu_dce->regs = regs; + dmcu_dce->dmcu_shift = dmcu_shift; + dmcu_dce->dmcu_mask = dmcu_mask; +} + +struct dmcu *dce_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask) +{ + struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + + if (dmcu_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_dmcu_construct( + dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); + + dmcu_dce->base.funcs = &dce_funcs; + + return &dmcu_dce->base; +} + +void dce_dmcu_destroy(struct dmcu **dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); + + dm_free(dmcu_dce); + *dmcu = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h new file mode 100644 index 000000000000..b026157a2eea --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h @@ -0,0 +1,91 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#ifndef _DCE_DMCU_H_ +#define _DCE_DMCU_H_ + +#include "dmcu.h" + +#define DMCU_COMMON_REG_LIST_DCE_BASE() \ + SR(DMCU_RAM_ACCESS_CTRL), \ + SR(DMCU_IRAM_WR_CTRL), \ + SR(DMCU_IRAM_WR_DATA) + +#define DMCU_DCE110_COMMON_REG_LIST() \ + DMCU_COMMON_REG_LIST_DCE_BASE(), \ + SR(DCI_MEM_PWR_STATUS) + +#define DMCU_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_HOST_ACCESS_EN, mask_sh), \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_WR_ADDR_AUTO_INC, mask_sh) + +#define DMCU_MASK_SH_LIST_DCE110(mask_sh) \ + DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + DMCU_SF(DCI_MEM_PWR_STATUS, \ + DMCU_IRAM_MEM_PWR_STATE, mask_sh) + +#define DMCU_REG_FIELD_LIST(type) \ + type DMCU_IRAM_MEM_PWR_STATE; \ + type IRAM_HOST_ACCESS_EN; \ + type IRAM_WR_ADDR_AUTO_INC + +struct dce_dmcu_shift { + DMCU_REG_FIELD_LIST(uint8_t); +}; + +struct dce_dmcu_mask { + DMCU_REG_FIELD_LIST(uint32_t); +}; + +struct dce_dmcu_registers { + uint32_t DMCU_RAM_ACCESS_CTRL; + uint32_t DCI_MEM_PWR_STATUS; + uint32_t DMU_MEM_PWR_CNTL; + uint32_t DMCU_IRAM_WR_CTRL; + uint32_t DMCU_IRAM_WR_DATA; +}; + +struct dce_dmcu { + struct dmcu base; + const struct dce_dmcu_registers *regs; + const struct dce_dmcu_shift *dmcu_shift; + const struct dce_dmcu_mask *dmcu_mask; +}; + +struct dmcu *dce_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask); + +void dce_dmcu_destroy(struct dmcu **dmcu); + +#endif /* _DCE_ABM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index e9d1a54bffd3..f9325626c26e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -142,7 +142,6 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { dce110_link_encoder_set_dmcu_backlight_level, .init_dmcu_backlight_settings = dce110_link_encoder_init_dmcu_backlight_settings, - .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level, .set_dmcu_psr_enable = dce110_link_encoder_set_dmcu_psr_enable, .setup_dmcu_psr = dce110_link_encoder_setup_dmcu_psr, .backlight_control = dce110_link_encoder_edp_backlight_control, @@ -1769,8 +1768,7 @@ void dce110_link_encoder_init_dmcu_backlight_settings( * Bios bug w/a - period resets to zero, * restoring to cache values which is always correct */ - REG_GET(BL_PWM_CNTL, - BL_ACTIVE_INT_FRAC_CNT, &value); + REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); if (value == 0 || bl_pwm_cntl == 1) { if (stored_backlight_registers.vBL_PWM_CNTL != 0) { pwmCntl = stored_backlight_registers.vBL_PWM_CNTL; @@ -1810,36 +1808,6 @@ void dce110_link_encoder_init_dmcu_backlight_settings( /* Enable the backlight output */ REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); - -} - -void dce110_link_encoder_set_dmcu_abm_level( - struct link_encoder *enc, uint32_t level) -{ - struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - struct dc_context *ctx = enc110->base.ctx; - - unsigned int dmcu_max_retry_on_wait_reg_ready = 801; - unsigned int dmcu_wait_reg_ready_interval = 100; - unsigned int regValue; - - /* waitDMCUReadyForCmd */ - do { - dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval); - regValue = REG_READ(MASTER_COMM_CNTL_REG); - dmcu_max_retry_on_wait_reg_ready--; - } while - /* expected value is 0, loop while not 0*/ - ((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) && - dmcu_max_retry_on_wait_reg_ready > 0); - - /* setDMCUParam_ABMLevel */ - REG_UPDATE_2(MASTER_COMM_CMD_REG, - MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, - MASTER_COMM_CMD_REG_BYTE2, level); - - /* notifyDMCUMsg */ - REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } static void get_dmcu_psr_state(struct link_encoder *enc, uint32_t *psr_state) @@ -1856,10 +1824,8 @@ static void get_dmcu_psr_state(struct link_encoder *enc, uint32_t *psr_state) do { dm_delay_in_microseconds(ctx, 2); - REG_GET(DCI_MEM_PWR_STATUS, - DMCU_IRAM_MEM_PWR_STATE, &value); - } while - (value != 0 && count++ < 10); + REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &value); + } while (value != 0 && count++ < 10); /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6acb9faf29f1..d67f1100c3d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -42,6 +42,7 @@ #include "stream_encoder.h" #include "link_encoder.h" #include "clock_source.h" +#include "abm.h" #include "audio.h" #include "dce/dce_hwseq.h" @@ -2166,6 +2167,7 @@ static void init_hw(struct core_dc *dc) int i; struct dc_bios *bp; struct transform *xfm; + struct abm *abm; bp = dc->ctx->dc_bios; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -2210,6 +2212,10 @@ static void init_hw(struct core_dc *dc) struct audio *audio = dc->res_pool->audios[i]; audio->funcs->hw_init(audio); } + + abm = dc->res_pool->abm; + if (abm != NULL) + abm->funcs->abm_init(abm); } /* TODO: move this to apply_ctx_tohw some how?*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 0b8f8927162f..8dc69be15182 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -49,6 +49,8 @@ #include "dce/dce_clock_source.h" #include "dce/dce_hwseq.h" #include "dce110/dce110_hw_sequencer.h" +#include "dce/dce_abm.h" +#include "dce/dce_dmcu.h" #include "reg_helper.h" @@ -200,6 +202,30 @@ static const struct dce_disp_clk_mask disp_clk_mask = { CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) }; +static const struct dce_dmcu_registers dmcu_regs = { + DMCU_DCE110_COMMON_REG_LIST() +}; + +static const struct dce_dmcu_shift dmcu_shift = { + DMCU_MASK_SH_LIST_DCE110(__SHIFT) +}; + +static const struct dce_dmcu_mask dmcu_mask = { + DMCU_MASK_SH_LIST_DCE110(_MASK) +}; + +static const struct dce_abm_registers abm_regs = { + ABM_DCE110_COMMON_REG_LIST() +}; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCE110(__SHIFT) +}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCE110(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -712,6 +738,12 @@ static void destruct(struct dce110_resource_pool *pool) } } + if (pool->base.abm != NULL) + dce_abm_destroy(&pool->base.abm); + + if (pool->base.dmcu != NULL) + dce_dmcu_destroy(&pool->base.dmcu); + if (pool->base.display_clock != NULL) dce_disp_clk_destroy(&pool->base.display_clock); @@ -1286,6 +1318,26 @@ static bool construct( goto res_create_fail; } + pool->base.dmcu = dce_dmcu_create(ctx, + &dmcu_regs, + &dmcu_shift, + &dmcu_mask); + if (pool->base.dmcu == NULL) { + dm_error("DC: failed to create dmcu!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } + + pool->base.abm = dce_abm_create(ctx, + &abm_regs, + &abm_shift, + &abm_mask); + if (pool->base.abm == NULL) { + dm_error("DC: failed to create abm!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } + /* get static clock information for PPLIB or firmware, save * max_clock_state */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index cc826efac58d..7e99b2b96794 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -46,6 +46,8 @@ #include "dce/dce_hwseq.h" #include "dce112/dce112_hw_sequencer.h" +#include "dce/dce_abm.h" +#include "dce/dce_dmcu.h" #include "reg_helper.h" @@ -218,6 +220,30 @@ static const struct dce_disp_clk_mask disp_clk_mask = { CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) }; +static const struct dce_dmcu_registers dmcu_regs = { + DMCU_DCE110_COMMON_REG_LIST() +}; + +static const struct dce_dmcu_shift dmcu_shift = { + DMCU_MASK_SH_LIST_DCE110(__SHIFT) +}; + +static const struct dce_dmcu_mask dmcu_mask = { + DMCU_MASK_SH_LIST_DCE110(_MASK) +}; + +static const struct dce_abm_registers abm_regs = { + ABM_DCE110_COMMON_REG_LIST() +}; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCE110(__SHIFT) +}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCE110(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -719,6 +745,12 @@ static void destruct(struct dce110_resource_pool *pool) } } + if (pool->base.abm != NULL) + dce_abm_destroy(&pool->base.abm); + + if (pool->base.dmcu != NULL) + dce_dmcu_destroy(&pool->base.dmcu); + if (pool->base.display_clock != NULL) dce_disp_clk_destroy(&pool->base.display_clock); @@ -1283,6 +1315,25 @@ static bool construct( goto res_create_fail; } + pool->base.dmcu = dce_dmcu_create(ctx, + &dmcu_regs, + &dmcu_shift, + &dmcu_mask); + if (pool->base.dmcu == NULL) { + dm_error("DC: failed to create dmcu!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } + + pool->base.abm = dce_abm_create(ctx, + &abm_regs, + &abm_shift, + &abm_mask); + if (pool->base.abm == NULL) { + dm_error("DC: failed to create abm!\n"); + BREAK_TO_DEBUGGER(); + goto res_create_fail; + } /* get static clock information for PPLIB or firmware, save * max_clock_state diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b349b5768b6e..1a81e83d1785 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -259,6 +259,9 @@ struct resource_pool { struct display_clock *display_clock; struct irq_service *irqs; + struct abm *abm; + struct dmcu *dmcu; + const struct resource_funcs *funcs; const struct resource_caps *res_cap; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h new file mode 100644 index 000000000000..9c9a6877387a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -0,0 +1,40 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_ABM_H__ +#define __DC_ABM_H__ + +#include "dm_services_types.h" + +struct abm { + struct dc_context *ctx; + const struct abm_funcs *funcs; +}; + +struct abm_funcs { + void (*abm_init)(struct abm *abm); + bool (*set_abm_level)(struct abm *abm, unsigned int abm_level); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h new file mode 100644 index 000000000000..62012f091836 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -0,0 +1,42 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DMCU_H__ +#define __DC_DMCU_H__ + +#include "dm_services_types.h" + +struct dmcu { + struct dc_context *ctx; + const struct dmcu_funcs *funcs; +}; + +struct dmcu_funcs { + bool (*load_iram)(struct dmcu *dmcu, + unsigned int start_offset, + const char *src, + unsigned int bytes); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index ac4010b9c638..949eae6d5402 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -225,7 +225,6 @@ struct link_encoder_funcs { void (*set_dmcu_backlight_level)(struct link_encoder *enc, uint32_t level, uint32_t frame_ramp, uint32_t controller_id); void (*init_dmcu_backlight_settings)(struct link_encoder *enc); - void (*set_dmcu_abm_level)(struct link_encoder *enc, uint32_t level); void (*set_dmcu_psr_enable)(struct link_encoder *enc, bool enable); void (*setup_dmcu_psr)(struct link_encoder *enc, struct psr_dmcu_context *psr_context); -- cgit v1.2.3-59-g8ed1b From 6728b30c974e38711f70dc38edf68503bf71c4a9 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Tue, 24 Jan 2017 15:19:42 -0500 Subject: drm/amd/display: Move backlight from encoder to ABM Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 34 --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 63 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 5 - drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 264 +++++++++++++++++++-- drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 35 ++- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 260 -------------------- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 24 -- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 5 + .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 5 - drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 - .../amd/display/dc/virtual/virtual_link_encoder.c | 13 - 12 files changed, 316 insertions(+), 400 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 152c694cc044..499ef561bbfc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -240,34 +240,6 @@ static void stream_update_scaling( } } -static bool set_backlight(struct dc *dc, unsigned int backlight_level, - unsigned int frame_ramp, const struct dc_stream *stream) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - int i; - - if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) { - for (i = 0; i < core_dc->link_count; i++) - dc_link_set_backlight_level(&core_dc->links[i]->public, - backlight_level, frame_ramp, stream); - } - - return true; - -} - -static bool init_dmcu_backlight_settings(struct dc *dc) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - int i; - - for (i = 0; i < core_dc->link_count; i++) - dc_link_init_dmcu_backlight_settings - (&core_dc->links[i]->public); - - return true; -} - static bool set_psr_enable(struct dc *dc, bool enable) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -390,12 +362,6 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) core_dc->public.stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->public.stream_funcs.set_backlight = - set_backlight; - - core_dc->public.stream_funcs.init_dmcu_backlight_settings = - init_dmcu_backlight_settings; - core_dc->public.stream_funcs.set_psr_enable = set_psr_enable; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 84efc25d0e33..2bceb3aa24b5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -37,6 +37,7 @@ #include "link_encoder.h" #include "hw_sequencer.h" #include "resource.h" +#include "abm.h" #include "fixed31_32.h" #include "dpcd_defs.h" @@ -1386,48 +1387,40 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream) { struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct core_stream *core_stream = NULL; + struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; - uint32_t dmcu_status; - dm_logger_write(ctx->logger, LOG_BACKLIGHT, - "New Backlight level: %d (0x%X)\n", level, level); + if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) + return false; - dmcu_status = dm_read_reg(ctx, mmDMCU_STATUS); + dm_logger_write(link->ctx->logger, LOG_BACKLIGHT, + "New Backlight level: %d (0x%X)\n", level, level); - /* If DMCU is in reset state, DMCU is uninitialized */ - if (get_reg_field_value(dmcu_status, mmDMCU_STATUS, UC_IN_RESET)) { - link->link_enc->funcs->set_lcd_backlight_level(link->link_enc, - level); - } else { - for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) - /* dmcu -1 for all controller id values, - * therefore +1 here - */ - controller_id = core_dc->current_context->res_ctx. - pipe_ctx[i].tg->inst + 1; + if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD) { + if (stream != NULL) { + core_stream = DC_STREAM_TO_CORE(stream); + for (i = 0; i < MAX_PIPES; i++) { + if (core_dc->current_context->res_ctx. + pipe_ctx[i].stream + == core_stream) + /* DMCU -1 for all controller id values, + * therefore +1 here + */ + controller_id = + core_dc->current_context-> + res_ctx.pipe_ctx[i].tg->inst + + 1; + } } - - link->link_enc->funcs->set_dmcu_backlight_level - (link->link_enc, level, - frame_ramp, controller_id); + abm->funcs->set_backlight_level( + abm, + level, + frame_ramp, + controller_id); } - return true; -} - - -bool dc_link_init_dmcu_backlight_settings(const struct dc_link *dc_link) -{ - struct core_link *link = DC_LINK_TO_CORE(dc_link); - - if (link->link_enc->funcs->init_dmcu_backlight_settings != NULL) - link->link_enc->funcs-> - init_dmcu_backlight_settings(link->link_enc); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8cb53b626641..1308af59d839 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -100,9 +100,6 @@ struct dc_stream_funcs { const struct rect *dst); bool (*set_gamut_remap)(struct dc *dc, const struct dc_stream **stream, int num_streams); - bool (*set_backlight)(struct dc *dc, unsigned int backlight_level, - unsigned int frame_ramp, const struct dc_stream *stream); - bool (*init_dmcu_backlight_settings)(struct dc *dc); bool (*set_psr_enable)(struct dc *dc, bool enable); bool (*setup_psr)(struct dc *dc, const struct dc_stream *stream); }; @@ -572,8 +569,6 @@ const struct graphics_object_id dc_get_link_id_at_index( bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream); -bool dc_link_init_dmcu_backlight_settings(const struct dc_link *dc_link); - bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_setup_psr(const struct dc_link *dc_link, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index ce49bee8e038..f4696bf14a70 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -29,6 +29,9 @@ #include "fixed32_32.h" #include "dc.h" +#include "atom.h" + + #define TO_DCE_ABM(abm)\ container_of(abm, struct dce_abm, base) @@ -43,6 +46,19 @@ abm_dce->base.ctx #define MCP_ABM_LEVEL_SET 0x65 +#define MCP_ABM_PIPE_SET 0x66 +#define MCP_BL_SET 0x67 + +struct abm_backlight_registers { + unsigned int BL_PWM_CNTL; + unsigned int BL_PWM_CNTL2; + unsigned int BL_PWM_PERIOD_CNTL; + unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; +}; + +/* registers setting needs to be save and restored used at InitBacklight */ +static struct abm_backlight_registers stored_backlight_registers = {0}; + static unsigned int get_current_backlight(struct dce_abm *abm_dce) { @@ -93,7 +109,147 @@ static unsigned int get_current_backlight(struct dce_abm *abm_dce) return (uint32_t)(current_backlight); } -void dce_abm_init(struct abm *abm) +static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level) +{ + uint32_t backlight_24bit; + uint32_t backlight_17bit; + uint32_t backlight_16bit; + uint32_t masked_pwm_period; + uint8_t rounding_bit; + uint8_t bit_count; + uint64_t active_duty_cycle; + uint32_t pwm_period_bitcnt; + + /* + * 1. Convert 8-bit value to 17 bit U1.16 format + * (1 integer, 16 fractional bits) + */ + + /* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value, + * effectively multiplying value by 256/255 + * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF + */ + backlight_24bit = level * 0x10101; + + /* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8 + * used for rounding, take most significant bit of fraction for + * rounding, e.g. for 0xEFEFEF, rounding bit is 1 + */ + rounding_bit = (backlight_24bit >> 7) & 1; + + /* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit + * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1 + */ + backlight_17bit = (backlight_24bit >> 8) + rounding_bit; + + /* + * 2. Find 16 bit backlight active duty cycle, where 0 <= backlight + * active duty cycle <= backlight period + */ + + /* 2.1 Apply bitmask for backlight period value based on value of BITCNT + */ + REG_GET_2(BL_PWM_PERIOD_CNTL, + BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt, + BL_PWM_PERIOD, &masked_pwm_period); + + if (pwm_period_bitcnt == 0) + bit_count = 16; + else + bit_count = pwm_period_bitcnt; + + /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ + masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); + + /* 2.2 Calculate integer active duty cycle required upper 16 bits + * contain integer component, lower 16 bits contain fractional component + * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 + */ + active_duty_cycle = backlight_17bit * masked_pwm_period; + + /* 2.3 Calculate 16 bit active duty cycle from integer and fractional + * components shift by bitCount then mask 16 bits and add rounding bit + * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 + */ + backlight_16bit = active_duty_cycle >> bit_count; + backlight_16bit &= 0xFFFF; + backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; + + /* + * 3. Program register with updated value + */ + + /* 3.1 Lock group 2 backlight registers */ + + REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK, + BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, + BL_PWM_GRP1_REG_LOCK, 1); + + // 3.2 Write new active duty cycle + REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); + + /* 3.3 Unlock group 2 backlight registers */ + REG_UPDATE(BL_PWM_GRP1_REG_LOCK, + BL_PWM_GRP1_REG_LOCK, 0); + + /* 5.4.4 Wait for pending bit to be cleared */ + REG_WAIT(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, + 0, 10, 1000); +} + +static void dmcu_set_backlight_level( + struct dce_abm *abm_dce, + uint32_t level, + uint32_t frame_ramp, + uint32_t controller_id) +{ + unsigned int backlight_16_bit = (level * 0x10101) >> 8; + unsigned int backlight_17_bit = backlight_16_bit + + (((backlight_16_bit & 0x80) >> 7) & 1); + uint32_t rampingBoundary = 0xFFFF; + uint32_t s2; + + /* set ramping boundary */ + REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); + + /* setDMCUParam_Pipe */ + REG_UPDATE_2(MASTER_COMM_CMD_REG, + MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET, + MASTER_COMM_CMD_REG_BYTE1, controller_id); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, + 0, 100, 800); + + /* setDMCUParam_BL */ + REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit); + + /* write ramp */ + if (controller_id == 0) + frame_ramp = 0; + REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* UpdateRequestedBacklightLevel */ + s2 = REG_READ(BIOS_SCRATCH_2); + + s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; + level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >> + ATOM_S2_CURRENT_BL_LEVEL_SHIFT); + s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); + + REG_WRITE(BIOS_SCRATCH_2, s2); +} + +static void dce_abm_init(struct abm *abm) { struct dce_abm *abm_dce = TO_DCE_ABM(abm); unsigned int backlight = get_current_backlight(abm_dce); @@ -133,24 +289,13 @@ void dce_abm_init(struct abm *abm) ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); } -bool dce_abm_set_level(struct abm *abm, uint32_t level) +static bool dce_abm_set_level(struct abm *abm, uint32_t level) { struct dce_abm *abm_dce = TO_DCE_ABM(abm); struct dc_context *ctx = abm_dce->base.ctx; - unsigned int dmcu_max_retry_on_wait_reg_ready = 801; - unsigned int dmcu_wait_reg_ready_interval = 100; - unsigned int value; - - /* waitDMCUReadyForCmd */ - do { - dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval); - REG_GET(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, &value); - dmcu_max_retry_on_wait_reg_ready--; - } while - /* expected value is 0, loop while not 0*/ - ((value & abm_dce->abm_mask->MASTER_COMM_INTERRUPT) && - dmcu_max_retry_on_wait_reg_ready > 0); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + 100, 800); /* setDMCUParam_ABMLevel */ REG_UPDATE_2(MASTER_COMM_CMD_REG, @@ -163,9 +308,98 @@ bool dce_abm_set_level(struct abm *abm, uint32_t level) return true; } +static bool dce_abm_init_backlight(struct abm *abm) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + uint32_t value; + + /* It must not be 0, so we have to restore them + * Bios bug w/a - period resets to zero, + * restoring to cache values which is always correct + */ + REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); + if (value == 0 || value == 1) { + if (stored_backlight_registers.BL_PWM_CNTL != 0) { + REG_WRITE(BL_PWM_CNTL, + stored_backlight_registers.BL_PWM_CNTL); + REG_WRITE(BL_PWM_CNTL2, + stored_backlight_registers.BL_PWM_CNTL2); + REG_WRITE(BL_PWM_PERIOD_CNTL, + stored_backlight_registers.BL_PWM_PERIOD_CNTL); + REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, + BL_PWM_REF_DIV, + stored_backlight_registers. + LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); + } else { + /* TODO: Note: This should not really happen since VBIOS + * should have initialized PWM registers on boot. + */ + REG_WRITE(BL_PWM_CNTL, 0xC000FA00); + REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); + } + } else { + stored_backlight_registers.BL_PWM_CNTL = + REG_READ(BL_PWM_CNTL); + stored_backlight_registers.BL_PWM_CNTL2 = + REG_READ(BL_PWM_CNTL2); + stored_backlight_registers.BL_PWM_PERIOD_CNTL = + REG_READ(BL_PWM_PERIOD_CNTL); + + REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, + &stored_backlight_registers. + LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); + } + + /* Have driver take backlight control + * TakeBacklightControl(true) + */ + value = REG_READ(BIOS_SCRATCH_2); + value |= ATOM_S2_VRI_BRIGHT_ENABLE; + REG_WRITE(BIOS_SCRATCH_2, value); + + /* Enable the backlight output */ + REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); + + /* Unlock group 2 backlight registers */ + REG_UPDATE(BL_PWM_GRP1_REG_LOCK, + BL_PWM_GRP1_REG_LOCK, 0); + + return true; +} + +static bool dce_abm_set_backlight_level( + struct abm *abm, + unsigned int backlight_level, + unsigned int frame_ramp, + unsigned int controller_id) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + unsigned int dmcu_uc_reset; + + dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT, + "New Backlight level: %d (0x%X)\n", + backlight_level, backlight_level); + + REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); + + /* If DMCU is in reset state, DMCU is uninitialized */ + if (dmcu_uc_reset) { + driver_set_backlight_level(abm_dce, backlight_level); + } else { + dmcu_set_backlight_level(abm_dce, + backlight_level, + frame_ramp, + controller_id); + } + + return true; +} + static const struct abm_funcs dce_funcs = { .abm_init = dce_abm_init, .set_abm_level = dce_abm_set_level, + .init_backlight = dce_abm_init_backlight, + .set_backlight_level = dce_abm_set_backlight_level }; static void dce_abm_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index cf40e303cbcf..56087b36bdeb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -32,8 +32,13 @@ #define ABM_COMMON_REG_LIST_DCE_BASE() \ SR(BL_PWM_PERIOD_CNTL), \ SR(BL_PWM_CNTL), \ + SR(BL_PWM_CNTL2), \ + SR(BL_PWM_GRP1_REG_LOCK), \ + SR(LVTMA_PWRSEQ_REF_DIV), \ SR(MASTER_COMM_CNTL_REG), \ - SR(MASTER_COMM_CMD_REG) + SR(MASTER_COMM_CMD_REG), \ + SR(MASTER_COMM_DATA_REG1), \ + SR(DMCU_STATUS) #define ABM_DCE110_COMMON_REG_LIST() \ ABM_COMMON_REG_LIST_DCE_BASE(), \ @@ -46,7 +51,8 @@ SR(BL1_PWM_TARGET_ABM_LEVEL), \ SR(BL1_PWM_USER_LEVEL), \ SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ - SR(DC_ABM1_HGLS_REG_READ_PROGRESS) + SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ + SR(BIOS_SCRATCH_2) #define ABM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -56,9 +62,16 @@ ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \ ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \ ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \ + ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \ + ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \ + ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \ + ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \ + ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \ ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ - ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) + ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ + ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \ + ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh) #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ @@ -91,6 +104,7 @@ ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) + #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ type ABM1_HG_VMAX_SEL; \ @@ -112,7 +126,14 @@ type BL_PWM_FRACTIONAL_EN; \ type MASTER_COMM_INTERRUPT; \ type MASTER_COMM_CMD_REG_BYTE0; \ - type MASTER_COMM_CMD_REG_BYTE2 + type MASTER_COMM_CMD_REG_BYTE1; \ + type MASTER_COMM_CMD_REG_BYTE2; \ + type BL_PWM_REF_DIV; \ + type BL_PWM_EN; \ + type UC_IN_RESET; \ + type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \ + type BL_PWM_GRP1_REG_LOCK; \ + type BL_PWM_GRP1_REG_UPDATE_PENDING struct dce_abm_shift { ABM_REG_FIELD_LIST(uint8_t); @@ -125,6 +146,8 @@ struct dce_abm_mask { struct dce_abm_registers { uint32_t BL_PWM_PERIOD_CNTL; uint32_t BL_PWM_CNTL; + uint32_t BL_PWM_CNTL2; + uint32_t LVTMA_PWRSEQ_REF_DIV; uint32_t DC_ABM1_HG_SAMPLE_RATE; uint32_t DC_ABM1_LS_SAMPLE_RATE; uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; @@ -137,6 +160,10 @@ struct dce_abm_registers { uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; uint32_t MASTER_COMM_CNTL_REG; uint32_t MASTER_COMM_CMD_REG; + uint32_t MASTER_COMM_DATA_REG1; + uint32_t BIOS_SCRATCH_2; + uint32_t DMCU_STATUS; + uint32_t BL_PWM_GRP1_REG_LOCK; }; struct dce_abm { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index f9325626c26e..3847764688dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -38,15 +38,6 @@ #include "dce/dce_11_0_sh_mask.h" #include "dce/dce_11_0_enum.h" -#ifndef ATOM_S2_CURRENT_BL_LEVEL_MASK -#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L -#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L -#endif - -#ifndef ATOM_S2_CURRENT_BL_LEVEL_SHIFT -#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 -#endif - #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L #endif @@ -96,13 +87,6 @@ /* For current ASICs pixel clock - 600MHz */ #define MAX_ENCODER_CLOCK 600000 -/* Set the ABM Pipe */ -#define MCP_ABM_PIPE_SET 0x66 -/* Set the ABM level */ -#define MCP_ABM_LEVEL_SET 0x65 -/* Set backlight level */ -#define MCP_BL_SET 0x67 - /* PSR related commands */ #define PSR_ENABLE 0x20 #define PSR_EXIT 0x21 @@ -111,9 +95,6 @@ /*TODO: Used for psr wakeup for set backlight level*/ static unsigned int psr_crtc_offset; -/* registers setting needs to be save and restored used at InitBacklight */ -static struct dce110_abm_backlight_registers stored_backlight_registers; - enum { DP_MST_UPDATE_MAX_RETRY = 50 }; @@ -137,11 +118,6 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, .update_mst_stream_allocation_table = dce110_link_encoder_update_mst_stream_allocation_table, - .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level, - .set_dmcu_backlight_level = - dce110_link_encoder_set_dmcu_backlight_level, - .init_dmcu_backlight_settings = - dce110_link_encoder_init_dmcu_backlight_settings, .set_dmcu_psr_enable = dce110_link_encoder_set_dmcu_psr_enable, .setup_dmcu_psr = dce110_link_encoder_setup_dmcu_psr, .backlight_control = dce110_link_encoder_edp_backlight_control, @@ -1574,242 +1550,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table( } while (retries < DP_MST_UPDATE_MAX_RETRY); } -void dce110_link_encoder_set_lcd_backlight_level( - struct link_encoder *enc, - uint32_t level) -{ - struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - - const uint32_t backlight_update_pending_max_retry = 1000; - - uint32_t backlight_lock; - - uint32_t i; - uint32_t backlight_24bit; - uint32_t backlight_17bit; - uint32_t backlight_16bit; - uint32_t masked_pwm_period; - uint8_t rounding_bit; - uint8_t bit_count; - uint64_t active_duty_cycle; - uint32_t pwm_period_bitcnt; - - backlight_lock = REG_READ(BL_PWM_GRP1_REG_LOCK); - - /* - * 1. Convert 8-bit value to 17 bit U1.16 format - * (1 integer, 16 fractional bits) - */ - - /* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value, - * effectively multiplying value by 256/255 - * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF - */ - backlight_24bit = level * 0x10101; - - /* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8 - * used for rounding, take most significant bit of fraction for - * rounding, e.g. for 0xEFEFEF, rounding bit is 1 - */ - rounding_bit = (backlight_24bit >> 7) & 1; - - /* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit - * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1 - */ - backlight_17bit = (backlight_24bit >> 8) + rounding_bit; - - /* - * 2. Find 16 bit backlight active duty cycle, where 0 <= backlight - * active duty cycle <= backlight period - */ - - /* 2.1 Apply bitmask for backlight period value based on value of BITCNT - */ - { - REG_GET(BL_PWM_PERIOD_CNTL, - BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt); - - if (pwm_period_bitcnt == 0) - bit_count = 16; - else - bit_count = pwm_period_bitcnt; - } - - /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ - masked_pwm_period = - REG_GET(BL_PWM_PERIOD_CNTL, - BL_PWM_PERIOD, &masked_pwm_period) - & ((1 << bit_count) - 1); - - /* 2.2 Calculate integer active duty cycle required upper 16 bits - * contain integer component, lower 16 bits contain fractional component - * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 - */ - active_duty_cycle = backlight_17bit * masked_pwm_period; - - /* 2.3 Calculate 16 bit active duty cycle from integer and fractional - * components shift by bitCount then mask 16 bits and add rounding bit - * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 - */ - backlight_16bit = active_duty_cycle >> bit_count; - backlight_16bit &= 0xFFFF; - backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; - - REG_UPDATE(BL_PWM_CNTL, - BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); - - /* - * 3. Program register with updated value - */ - - /* 3.1 Lock group 2 backlight registers */ - - REG_UPDATE(BL_PWM_GRP1_REG_LOCK, - BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1); - - REG_UPDATE(BL_PWM_GRP1_REG_LOCK, - BL_PWM_GRP1_REG_LOCK, 1); - - /* 3.3 Unlock group 2 backlight registers */ - REG_UPDATE(BL_PWM_GRP1_REG_LOCK, - BL_PWM_GRP1_REG_LOCK, 0); - - /* 5.4.4 Wait for pending bit to be cleared */ - for (i = 0; i < backlight_update_pending_max_retry; ++i) { - REG_GET(BL_PWM_GRP1_REG_LOCK, - BL_PWM_GRP1_REG_UPDATE_PENDING, &backlight_lock); - if (!backlight_lock) - break; - - udelay(10); - } -} - -void dce110_link_encoder_set_dmcu_backlight_level( - struct link_encoder *enc, - uint32_t level, - uint32_t frame_ramp, - uint32_t controller_id) -{ - struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - struct dc_context *ctx = enc110->base.ctx; - unsigned int dmcu_max_retry_on_wait_reg_ready = 801; - unsigned int dmcu_wait_reg_ready_interval = 100; - unsigned int backlight_17bit = level * 0x10101; - unsigned char temp_uchar = - (unsigned char)(((backlight_17bit & 0x80) >> 7) & 1); - unsigned int regValue; - uint32_t rampingBoundary = 0xFFFF; - uint32_t s2; - - backlight_17bit = (backlight_17bit >> 8) + temp_uchar; - - /* set ramping boundary */ - REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); - - /* setDMCUParam_Pipe */ - REG_UPDATE_2(MASTER_COMM_CMD_REG, - MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET, - MASTER_COMM_CMD_REG_BYTE1, controller_id); - - /* notifyDMCUMsg */ - REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); - - /* waitDMCUReadyForCmd */ - do { - dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval); - regValue = REG_READ(MASTER_COMM_CNTL_REG); - dmcu_max_retry_on_wait_reg_ready--; - } while - /* expected value is 0, loop while not 0*/ - ((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) && - dmcu_max_retry_on_wait_reg_ready > 0); - - /* setDMCUParam_BL */ - REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17bit); - - /* write ramp */ - REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); - - /* setDMCUParam_Cmd */ - REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); - - /* notifyDMCUMsg */ - REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); - - /* UpdateRequestedBacklightLevel */ - s2 = REG_READ(BIOS_SCRATCH_2); - - s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; - level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >> - ATOM_S2_CURRENT_BL_LEVEL_SHIFT); - s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); - - REG_WRITE(BIOS_SCRATCH_2, s2); -} - -void dce110_link_encoder_init_dmcu_backlight_settings( - struct link_encoder *enc) -{ - struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - uint32_t bl_pwm_cntl; - uint32_t pwmCntl; - uint32_t pwmCntl2; - uint32_t periodCntl; - uint32_t s2; - uint32_t value; - - if (enc->ctx->dc->debug.disable_dmcu) - return; - - bl_pwm_cntl = REG_READ(BL_PWM_CNTL); - - /* It must not be 0, so we have to restore them - * Bios bug w/a - period resets to zero, - * restoring to cache values which is always correct - */ - REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); - if (value == 0 || bl_pwm_cntl == 1) { - if (stored_backlight_registers.vBL_PWM_CNTL != 0) { - pwmCntl = stored_backlight_registers.vBL_PWM_CNTL; - REG_WRITE(BL_PWM_CNTL, pwmCntl); - - pwmCntl2 = stored_backlight_registers.vBL_PWM_CNTL2; - REG_WRITE(BL_PWM_CNTL2, pwmCntl2); - - periodCntl = - stored_backlight_registers.vBL_PWM_PERIOD_CNTL; - REG_WRITE(BL_PWM_PERIOD_CNTL, periodCntl); - - REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, - BL_PWM_REF_DIV, - stored_backlight_registers. - vLVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); - } - } else { - stored_backlight_registers.vBL_PWM_CNTL = - REG_READ(BL_PWM_CNTL); - stored_backlight_registers.vBL_PWM_CNTL2 = - REG_READ(BL_PWM_CNTL2); - stored_backlight_registers.vBL_PWM_PERIOD_CNTL = - REG_READ(BL_PWM_PERIOD_CNTL); - - REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, - &stored_backlight_registers. - vLVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); - } - - /* Have driver take backlight control - * TakeBacklightControl(true) - */ - s2 = REG_READ(BIOS_SCRATCH_2); - s2 |= ATOM_S2_VRI_BRIGHT_ENABLE; - REG_WRITE(BIOS_SCRATCH_2, s2); - - /* Enable the backlight output */ - REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); -} - static void get_dmcu_psr_state(struct link_encoder *enc, uint32_t *psr_state) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index b3667df5250b..053f72b91b3c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -226,13 +226,6 @@ union dce110_dmcu_psr_config_data_reg3 { unsigned int u32All; }; -struct dce110_abm_backlight_registers { - unsigned int vBL_PWM_CNTL; - unsigned int vBL_PWM_CNTL2; - unsigned int vBL_PWM_PERIOD_CNTL; - unsigned int vLVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; -}; - bool dce110_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, @@ -317,23 +310,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table); -void dce110_link_encoder_set_lcd_backlight_level( - struct link_encoder *enc, - uint32_t level); - -void dce110_link_encoder_set_dmcu_backlight_level( - struct link_encoder *enc, - uint32_t level, - uint32_t frame_ramp, - uint32_t controller_id); - -void dce110_link_encoder_init_dmcu_backlight_settings( - struct link_encoder *enc); - -void dce110_link_encoder_set_dmcu_abm_level( - struct link_encoder *enc, - uint32_t level); - void dce110_link_encoder_set_dmcu_psr_enable( struct link_encoder *enc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d67f1100c3d9..a1a5dc6fcb67 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2214,8 +2214,10 @@ static void init_hw(struct core_dc *dc) } abm = dc->res_pool->abm; - if (abm != NULL) + if (abm != NULL) { + abm->funcs->init_backlight(abm); abm->funcs->abm_init(abm); + } } /* TODO: move this to apply_ctx_tohw some how?*/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index 9c9a6877387a..7d07b7922391 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -35,6 +35,11 @@ struct abm { struct abm_funcs { void (*abm_init)(struct abm *abm); bool (*set_abm_level)(struct abm *abm, unsigned int abm_level); + bool (*init_backlight)(struct abm *abm); + bool (*set_backlight_level)(struct abm *abm, + unsigned int backlight_level, + unsigned int frame_ramp, + unsigned int controller_id); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 949eae6d5402..7b37b963666e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -220,11 +220,6 @@ struct link_encoder_funcs { void (*update_mst_stream_allocation_table)( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table); - void (*set_lcd_backlight_level) (struct link_encoder *enc, - uint32_t level); - void (*set_dmcu_backlight_level)(struct link_encoder *enc, - uint32_t level, uint32_t frame_ramp, uint32_t controller_id); - void (*init_dmcu_backlight_settings)(struct link_encoder *enc); void (*set_dmcu_psr_enable)(struct link_encoder *enc, bool enable); void (*setup_dmcu_psr)(struct link_encoder *enc, struct psr_dmcu_context *psr_context); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 562c8978fe9c..758a568589bb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -94,10 +94,6 @@ struct hw_sequencer_funcs { int group_size, struct pipe_ctx *grouped_pipes[]); - /* backlight control */ - void (*encoder_set_lcd_backlight_level)( - struct link_encoder *enc, uint32_t level); - void (*enable_display_pipe_clock_gating)( struct dc_context *ctx, bool clock_gating); diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 869dedca0b17..12df49927f09 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -72,16 +72,6 @@ static void virtual_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table) {} -static void virtual_link_encoder_set_lcd_backlight_level( - struct link_encoder *enc, - uint32_t level) {} - -static void virtual_link_encoder_set_dmcu_backlight_level( - struct link_encoder *enc, - uint32_t level, - uint32_t frame_ramp, - uint32_t controller_id) {} - static void virtual_link_encoder_edp_backlight_control( struct link_encoder *enc, bool enable) {} @@ -115,9 +105,6 @@ static const struct link_encoder_funcs virtual_lnk_enc_funcs = { .dp_set_phy_pattern = virtual_link_encoder_dp_set_phy_pattern, .update_mst_stream_allocation_table = virtual_link_encoder_update_mst_stream_allocation_table, - .set_lcd_backlight_level = virtual_link_encoder_set_lcd_backlight_level, - .set_dmcu_backlight_level = - virtual_link_encoder_set_dmcu_backlight_level, .backlight_control = virtual_link_encoder_edp_backlight_control, .power_control = virtual_link_encoder_edp_power_control, .connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe, -- cgit v1.2.3-59-g8ed1b From 71f7256e41ad036215a69e6bf561f7d4a541f150 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 30 Jan 2017 17:35:59 -0500 Subject: drm/amd/display: remove CV-specific timing standard Signed-off-by: Charlene Liu Reviewed-by: Jordan Lazare Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 5 ----- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 -- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 4 ---- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c | 5 ----- 4 files changed, 16 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 9f462a299ff3..6cd1e93b5084 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -66,11 +66,6 @@ void color_space_to_black_color( } switch (colorspace) { - case COLOR_SPACE_YPBPR601: - *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_TV]; - break; - - case COLOR_SPACE_YPBPR709: case COLOR_SPACE_YCBCR601: case COLOR_SPACE_YCBCR709: case COLOR_SPACE_YCBCR601_LIMITED: diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 53c73de75da9..21092f33c83b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -435,8 +435,6 @@ enum dc_color_space { COLOR_SPACE_UNKNOWN, COLOR_SPACE_SRGB, COLOR_SPACE_SRGB_LIMITED, - COLOR_SPACE_YPBPR601, - COLOR_SPACE_YPBPR709, COLOR_SPACE_YCBCR601, COLOR_SPACE_YCBCR709, COLOR_SPACE_YCBCR601_LIMITED, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 62f01911639f..9247afd4d42f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -827,14 +827,12 @@ static bool configure_graphics_mode( OUTPUT_CSC_GRPH_MODE, 1); break; case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: case COLOR_SPACE_YCBCR601_LIMITED: /* YCbCr601 */ REG_SET(OUTPUT_CSC_CONTROL, 0, OUTPUT_CSC_GRPH_MODE, 2); break; case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: case COLOR_SPACE_YCBCR709_LIMITED: /* YCbCr709 */ REG_SET(OUTPUT_CSC_CONTROL, 0, @@ -858,14 +856,12 @@ static bool configure_graphics_mode( OUTPUT_CSC_GRPH_MODE, 1); break; case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: case COLOR_SPACE_YCBCR601_LIMITED: /* YCbCr601 */ REG_SET(OUTPUT_CSC_CONTROL, 0, OUTPUT_CSC_GRPH_MODE, 2); break; case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: case COLOR_SPACE_YCBCR709_LIMITED: /* YCbCr709 */ REG_SET(OUTPUT_CSC_CONTROL, 0, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c index 6995a3de7564..019effe4c99c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c @@ -383,8 +383,6 @@ static bool configure_graphics_mode_v( /* not supported for underlay on CZ */ return false; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: case COLOR_SPACE_YCBCR601_LIMITED: /* YCbCr601 */ set_reg_field_value( @@ -394,7 +392,6 @@ static bool configure_graphics_mode_v( OUTPUT_CSC_MODE); break; case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: case COLOR_SPACE_YCBCR709_LIMITED: /* YCbCr709 */ set_reg_field_value( @@ -421,7 +418,6 @@ static bool configure_graphics_mode_v( /* not supported for underlay on CZ */ return false; case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YPBPR601: case COLOR_SPACE_YCBCR601_LIMITED: /* YCbCr601 */ set_reg_field_value( @@ -431,7 +427,6 @@ static bool configure_graphics_mode_v( OUTPUT_CSC_MODE); break; case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YPBPR709: case COLOR_SPACE_YCBCR709_LIMITED: /* YCbCr709 */ set_reg_field_value( -- cgit v1.2.3-59-g8ed1b From cc4d99b8a888e16093b985d6a11fbd37ab92697c Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 1 Feb 2017 20:35:53 -0500 Subject: drm/amd/display: HDMI YCbCr422 12bpc pixel format issue Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++++- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 30 ++++++++++---------- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 29 ++++++++++---------- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 32 +++++++++++++++++----- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 16 +++++++---- .../drm/amd/display/dc/dce110/dce110_resource.c | 3 ++ drivers/gpu/drm/amd/display/dc/inc/clock_source.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + 8 files changed, 76 insertions(+), 44 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index ec5de329b091..2b929393f68a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1267,6 +1267,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; struct core_link *link = stream->sink->link; + enum dc_color_depth display_color_depth; if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) dal_ddc_service_write_scdc_data( @@ -1277,10 +1278,14 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) memset(&stream->sink->link->public.cur_link_settings, 0, sizeof(struct dc_link_settings)); + display_color_depth = stream->public.timing.display_color_depth; + if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + display_color_depth = COLOR_DEPTH_888; + link->link_enc->funcs->enable_tmds_output( link->link_enc, pipe_ctx->clock_source->id, - stream->public.timing.display_color_depth, + display_color_depth, pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A, pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK, stream->phy_pix_clk); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 3d8a85e48b05..856a33ad8ec1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1045,25 +1045,25 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) pix_clk /= 2; - - switch (timing->display_color_depth) { - case COLOR_DEPTH_888: - normalized_pix_clk = pix_clk; - break; - case COLOR_DEPTH_101010: - normalized_pix_clk = (pix_clk * 30) / 24; + if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { + switch (timing->display_color_depth) { + case COLOR_DEPTH_888: + normalized_pix_clk = pix_clk; + break; + case COLOR_DEPTH_101010: + normalized_pix_clk = (pix_clk * 30) / 24; + break; + case COLOR_DEPTH_121212: + normalized_pix_clk = (pix_clk * 36) / 24; break; - case COLOR_DEPTH_121212: - normalized_pix_clk = (pix_clk * 36) / 24; + case COLOR_DEPTH_161616: + normalized_pix_clk = (pix_clk * 48) / 24; break; - case COLOR_DEPTH_161616: - normalized_pix_clk = (pix_clk * 48) / 24; - break; - default: - ASSERT(0); + default: + ASSERT(0); break; + } } - return normalized_pix_clk; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 78f43274a03a..a9f39218ce82 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -390,25 +390,24 @@ static bool pll_adjust_pix_clk( struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { 0 }; enum bp_result bp_result; - switch (pix_clk_params->signal_type) { case SIGNAL_TYPE_HDMI_TYPE_A: { requested_clk_khz = pix_clk_params->requested_pix_clk; - - switch (pix_clk_params->color_depth) { - case COLOR_DEPTH_101010: - requested_clk_khz = (requested_clk_khz * 5) >> 2; - break; /* x1.25*/ - case COLOR_DEPTH_121212: - requested_clk_khz = (requested_clk_khz * 6) >> 2; - break; /* x1.5*/ - case COLOR_DEPTH_161616: - requested_clk_khz = requested_clk_khz * 2; - break; /* x2.0*/ - default: - break; + if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { + switch (pix_clk_params->color_depth) { + case COLOR_DEPTH_101010: + requested_clk_khz = (requested_clk_khz * 5) >> 2; + break; /* x1.25*/ + case COLOR_DEPTH_121212: + requested_clk_khz = (requested_clk_khz * 6) >> 2; + break; /* x1.5*/ + case COLOR_DEPTH_161616: + requested_clk_khz = requested_clk_khz * 2; + break; /* x2.0*/ + default: + break; + } } - actual_pix_clk_khz = requested_clk_khz; } break; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 9247afd4d42f..a2f57cf603aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -366,19 +366,37 @@ static void set_truncation( FMT_TRUNCATE_EN, 0, FMT_TRUNCATE_DEPTH, 0, FMT_TRUNCATE_MODE, 0); - /* no 10bpc trunc on DCE11*/ + + + if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + /* 8bpc trunc on YCbCr422*/ + if (params->flags.TRUNCATE_DEPTH == 1) + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_TRUNCATE_EN, 1, + FMT_TRUNCATE_DEPTH, 1, + FMT_TRUNCATE_MODE, 0); + else if (params->flags.TRUNCATE_DEPTH == 2) + /* 10bpc trunc on YCbCr422*/ + REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, + FMT_TRUNCATE_EN, 1, + FMT_TRUNCATE_DEPTH, 2, + FMT_TRUNCATE_MODE, 0); + return; + } + /* on other format-to do */ if (params->flags.TRUNCATE_ENABLED == 0 || - params->flags.TRUNCATE_DEPTH == 2) + params->flags.TRUNCATE_DEPTH == 2) return; - /*Set truncation depth and Enable truncation*/ REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, - FMT_TRUNCATE_EN, 1, - FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_MODE, - FMT_TRUNCATE_MODE, params->flags.TRUNCATE_DEPTH); - + FMT_TRUNCATE_EN, 1, + FMT_TRUNCATE_DEPTH, + params->flags.TRUNCATE_MODE, + FMT_TRUNCATE_MODE, + params->flags.TRUNCATE_DEPTH); } + /** * set_spatial_dither * 1) set spatial dithering mode: pattern of seed diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 7e6661bda970..a28d9c7ba17e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -367,14 +367,20 @@ static void dce110_stream_encoder_hdmi_set_stream_attribute( HDMI_DEEP_COLOR_ENABLE, 1); break; case COLOR_DEPTH_121212: - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 2, - HDMI_DEEP_COLOR_ENABLE, 1); + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 1); + } break; case COLOR_DEPTH_161616: REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 3, - HDMI_DEEP_COLOR_ENABLE, 1); + HDMI_DEEP_COLOR_DEPTH, 3, + HDMI_DEEP_COLOR_ENABLE, 1); break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 8dc69be15182..4c108d0fb164 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -814,6 +814,9 @@ void dce110_resource_build_bit_depth_reduction_params( fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; + + fmt_bit_depth->pixel_encoding = + stream->public.timing.pixel_encoding; } return; diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h index c91c7815ec6e..47ef90495376 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h @@ -94,7 +94,7 @@ struct pixel_clk_params { enum dc_color_depth color_depth; struct csdp_ref_clk_ds_params de_spread_params; /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/ - + enum dc_pixel_encoding pixel_encoding; struct pixel_clk_flags flags; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index a10c4e296960..e01b831a7e7f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -86,6 +86,7 @@ struct bit_depth_reduction_params { uint32_t r_seed_value; uint32_t b_seed_value; uint32_t g_seed_value; + enum dc_pixel_encoding pixel_encoding; }; enum wide_gamut_regamma_mode { -- cgit v1.2.3-59-g8ed1b From a99240d5f8e14fc081e2cccad6ac46b48cea7def Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 2 Feb 2017 17:08:19 -0500 Subject: drm/amd/display: use disp clock value in context rather than bw_results Signed-off-by: Dmytro Laktyushkin Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 ++++++-------- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++++----- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- 6 files changed, 15 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9d2f78f21748..4c405f4b880e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -925,7 +925,7 @@ void pplib_apply_display_requirements( /* TODO: dce11.2*/ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - pp_display_cfg->disp_clk_khz = context->bw_results.dispclk_khz; + pp_display_cfg->disp_clk_khz = context->dispclk_khz; fill_display_configs(context, pp_display_cfg); @@ -1065,8 +1065,7 @@ bool dc_pre_update_surfaces_to_stream( { int i, j; struct core_dc *core_dc = DC_TO_CORE(dc); - int prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz; - int new_disp_clk; + int prev_disp_clk = core_dc->current_context->dispclk_khz; struct dc_stream_status *stream_status = NULL; struct validate_context *context; struct validate_context *temp_context; @@ -1152,17 +1151,16 @@ bool dc_pre_update_surfaces_to_stream( ret = false; goto unexpected_fail; } - new_disp_clk = context->bw_results.dispclk_khz; if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) - && prev_disp_clk < new_disp_clk) { + && prev_disp_clk < context->dispclk_khz) { pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg); context->res_ctx.pool->display_clock->funcs->set_clock( context->res_ctx.pool->display_clock, - new_disp_clk * 115 / 100); - core_dc->current_context->bw_results.dispclk_khz = new_disp_clk; - core_dc->current_context->dispclk_khz = new_disp_clk; + context->dispclk_khz * 115 / 100); + core_dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; + core_dc->current_context->dispclk_khz = context->dispclk_khz; } for (i = 0; i < new_surface_count; i++) diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 800b22e70c7e..55501b381692 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -770,7 +770,7 @@ enum dc_status dce100_validate_bandwidth( struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ - context->bw_results.dispclk_khz = 681000; + context->dispclk_khz = 681000; return DC_OK; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index a1a5dc6fcb67..5e99f6c27c9a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1651,7 +1651,7 @@ static void apply_min_clocks( /* get the required state based on state dependent clocks: * display clock and pixel clock */ - req_clocks.display_clk_khz = context->bw_results.dispclk_khz; + req_clocks.display_clk_khz = context->dispclk_khz; req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( dc, context, true); @@ -1776,11 +1776,11 @@ enum dc_status dce110_apply_ctx_to_hw( /*TODO: when pplib works*/ apply_min_clocks(dc, context, &clocks_state, true); - if (context->bw_results.dispclk_khz - > dc->current_context->bw_results.dispclk_khz) + if (context->dispclk_khz + > dc->current_context->dispclk_khz) context->res_ctx.pool->display_clock->funcs->set_clock( context->res_ctx.pool->display_clock, - context->bw_results.dispclk_khz * 115 / 100); + context->dispclk_khz * 115 / 100); for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = @@ -2289,7 +2289,7 @@ static void dce110_set_bandwidth(struct core_dc *dc) dc->current_context->res_ctx.pool->display_clock->funcs->set_clock( dc->current_context->res_ctx.pool->display_clock, - dc->current_context->bw_results.dispclk_khz * 115 / 100); + dc->current_context->dispclk_khz * 115 / 100); } static void dce110_program_front_end_for_pipe( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 4c108d0fb164..ee4fda514de6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -926,6 +926,7 @@ enum dc_status dce110_validate_bandwidth( result = DC_FAIL_BANDWIDTH_VALIDATE; else result = DC_OK; + context->dispclk_khz = context->bw_results.dispclk_khz; if (result == DC_FAIL_BANDWIDTH_VALIDATE) dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 7e99b2b96794..54af84ebf2bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -857,6 +857,7 @@ enum dc_status dce112_validate_bandwidth( result = DC_FAIL_BANDWIDTH_VALIDATE; else result = DC_OK; + context->dispclk_khz = context->bw_results.dispclk_khz; if (result == DC_FAIL_BANDWIDTH_VALIDATE) dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index fea60aa5d297..3de8bfb47dce 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -785,7 +785,7 @@ enum dc_status dce80_validate_bandwidth( struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ - context->bw_results.dispclk_khz = 681000; + context->dispclk_khz = 681000; context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; return DC_OK; -- cgit v1.2.3-59-g8ed1b From ab8812a3861efd3d60a4079711f2d1b08b8af50e Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Wed, 8 Feb 2017 11:28:33 -0500 Subject: drm/amd/display: Audio is not switching to DP when HDMI/DP hot plug/unplug Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 100 +++++++++++++++------ 1 file changed, 75 insertions(+), 25 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5e99f6c27c9a..6a5cec0d4e1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1732,7 +1732,6 @@ enum dc_status dce110_apply_ctx_to_hw( struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; int i; - bool programmed_audio_dto = false; enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; /* Reset old context */ @@ -1782,6 +1781,80 @@ enum dc_status dce110_apply_ctx_to_hw( context->res_ctx.pool->display_clock, context->dispclk_khz * 115 / 100); + /* program audio wall clock. use HDMI as clock source if HDMI + * audio active. Otherwise, use DP as clock source + * first, loop to find any HDMI audio, if not, loop find DP audio + */ + /* Setup audio rate clock source */ + /* Issue: + * Audio lag happened on DP monitor when unplug a HDMI monitor + * + * Cause: + * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL + * is set to either dto0 or dto1, audio should work fine. + * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, + * set to dto0 will cause audio lag. + * + * Solution: + * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, + * find first available pipe with audio, setup audio wall DTO per topology + * instead of per pipe. + */ + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) + continue; + + if (pipe_ctx->top_pipe) + continue; + + if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) + continue; + + if (pipe_ctx->audio != NULL) { + struct audio_output audio_output; + + build_audio_output(pipe_ctx, &audio_output); + + pipe_ctx->audio->funcs->wall_dto_setup( + pipe_ctx->audio, + pipe_ctx->stream->signal, + &audio_output.crtc_info, + &audio_output.pll_info); + break; + } + } + + /* no HDMI audio is found, try DP audio */ + if (i == context->res_ctx.pool->pipe_count) { + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) + continue; + + if (pipe_ctx->top_pipe) + continue; + + if (!dc_is_dp_signal(pipe_ctx->stream->signal)) + continue; + + if (pipe_ctx->audio != NULL) { + struct audio_output audio_output; + + build_audio_output(pipe_ctx, &audio_output); + + pipe_ctx->audio->funcs->wall_dto_setup( + pipe_ctx->audio, + pipe_ctx->stream->signal, + &audio_output.crtc_info, + &audio_output.pll_info); + break; + } + } + } + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; @@ -1797,21 +1870,7 @@ enum dc_status dce110_apply_ctx_to_hw( continue; if (context->res_ctx.pipe_ctx[i].audio != NULL) { - /* Setup audio rate clock source */ - /* Issue: - * Audio lag happened on DP monitor when unplug a HDMI monitor - * - * Cause: - * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL - * is set to either dto0 or dto1, audio should work fine. - * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, - * set to dto0 will cause audio lag. - * - * Solution: - * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, - * find first available pipe with audio, setup audio wall DTO per topology - * instead of per pipe. - */ + struct audio_output audio_output; build_audio_output(pipe_ctx, &audio_output); @@ -1833,15 +1892,6 @@ enum dc_status dce110_apply_ctx_to_hw( pipe_ctx->stream->signal, &audio_output.crtc_info, &pipe_ctx->stream->public.audio_info); - - if (!programmed_audio_dto) { - pipe_ctx->audio->funcs->wall_dto_setup( - pipe_ctx->audio, - pipe_ctx->stream->signal, - &audio_output.crtc_info, - &audio_output.pll_info); - programmed_audio_dto = true; - } } status = apply_single_controller_ctx_to_hw( -- cgit v1.2.3-59-g8ed1b From e266fdf6944749e100b065b5a95c7bb33d2aa2d6 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Tue, 7 Feb 2017 10:41:37 -0600 Subject: drm/amd/display: Enable regamma 25 segments and use double buffer. Moved custom floating point calculation to the shared place between dce's. Signed-off-by: Vitaly Prosyak Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 +- .../gpu/drm/amd/display/dc/calcs/custom_float.c | 197 +++++++++++++++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 171 +----------------- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 3 - drivers/gpu/drm/amd/display/dc/inc/custom_float.h | 40 +++++ 5 files changed, 240 insertions(+), 173 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c create mode 100644 drivers/gpu/drm/amd/display/dc/inc/custom_float.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 4bb08aea6a03..2f4c8e771b8f 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -3,7 +3,7 @@ # It calculates Bandwidth and Watermarks values for HW programming # -BW_CALCS = bandwidth_calcs.o bw_fixed.o +BW_CALCS = bandwidth_calcs.o bw_fixed.o custom_float.o AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS)) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c b/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c new file mode 100644 index 000000000000..7243c37f569e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c @@ -0,0 +1,197 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "dm_services.h" +#include "custom_float.h" + + +static bool build_custom_float( + struct fixed31_32 value, + const struct custom_float_format *format, + bool *negative, + uint32_t *mantissa, + uint32_t *exponenta) +{ + uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; + + const struct fixed31_32 mantissa_constant_plus_max_fraction = + dal_fixed31_32_from_fraction( + (1LL << (format->mantissa_bits + 1)) - 1, + 1LL << format->mantissa_bits); + + struct fixed31_32 mantiss; + + if (dal_fixed31_32_eq( + value, + dal_fixed31_32_zero)) { + *negative = false; + *mantissa = 0; + *exponenta = 0; + return true; + } + + if (dal_fixed31_32_lt( + value, + dal_fixed31_32_zero)) { + *negative = format->sign; + value = dal_fixed31_32_neg(value); + } else { + *negative = false; + } + + if (dal_fixed31_32_lt( + value, + dal_fixed31_32_one)) { + uint32_t i = 1; + + do { + value = dal_fixed31_32_shl(value, 1); + ++i; + } while (dal_fixed31_32_lt( + value, + dal_fixed31_32_one)); + + --i; + + if (exp_offset <= i) { + *mantissa = 0; + *exponenta = 0; + return true; + } + + *exponenta = exp_offset - i; + } else if (dal_fixed31_32_le( + mantissa_constant_plus_max_fraction, + value)) { + uint32_t i = 1; + + do { + value = dal_fixed31_32_shr(value, 1); + ++i; + } while (dal_fixed31_32_lt( + mantissa_constant_plus_max_fraction, + value)); + + *exponenta = exp_offset + i - 1; + } else { + *exponenta = exp_offset; + } + + mantiss = dal_fixed31_32_sub( + value, + dal_fixed31_32_one); + + if (dal_fixed31_32_lt( + mantiss, + dal_fixed31_32_zero) || + dal_fixed31_32_lt( + dal_fixed31_32_one, + mantiss)) + mantiss = dal_fixed31_32_zero; + else + mantiss = dal_fixed31_32_shl( + mantiss, + format->mantissa_bits); + + *mantissa = dal_fixed31_32_floor(mantiss); + + return true; +} + +static bool setup_custom_float( + const struct custom_float_format *format, + bool negative, + uint32_t mantissa, + uint32_t exponenta, + uint32_t *result) +{ + uint32_t i = 0; + uint32_t j = 0; + + uint32_t value = 0; + + /* verification code: + * once calculation is ok we can remove it + */ + + const uint32_t mantissa_mask = + (1 << (format->mantissa_bits + 1)) - 1; + + const uint32_t exponenta_mask = + (1 << (format->exponenta_bits + 1)) - 1; + + if (mantissa & ~mantissa_mask) { + BREAK_TO_DEBUGGER(); + mantissa = mantissa_mask; + } + + if (exponenta & ~exponenta_mask) { + BREAK_TO_DEBUGGER(); + exponenta = exponenta_mask; + } + + /* end of verification code */ + + while (i < format->mantissa_bits) { + uint32_t mask = 1 << i; + + if (mantissa & mask) + value |= mask; + + ++i; + } + + while (j < format->exponenta_bits) { + uint32_t mask = 1 << j; + + if (exponenta & mask) + value |= mask << i; + + ++j; + } + + if (negative && format->sign) + value |= 1 << (i + j); + + *result = value; + + return true; +} + +bool convert_to_custom_float_format( + struct fixed31_32 value, + const struct custom_float_format *format, + uint32_t *result) +{ + uint32_t mantissa; + uint32_t exponenta; + bool negative; + + return build_custom_float( + value, format, &negative, &mantissa, &exponenta) && + setup_custom_float( + format, negative, mantissa, exponenta, result); +} + + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6a5cec0d4e1f..88a2fa99f5da 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -49,6 +49,7 @@ /* include DCE11 register header files */ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" +#include "custom_float.h" struct dce110_hw_seq_reg_offsets { uint32_t crtc; @@ -286,174 +287,6 @@ static bool dce110_set_input_transfer_func( return result; } -static bool build_custom_float( - struct fixed31_32 value, - const struct custom_float_format *format, - bool *negative, - uint32_t *mantissa, - uint32_t *exponenta) -{ - uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; - - const struct fixed31_32 mantissa_constant_plus_max_fraction = - dal_fixed31_32_from_fraction( - (1LL << (format->mantissa_bits + 1)) - 1, - 1LL << format->mantissa_bits); - - struct fixed31_32 mantiss; - - if (dal_fixed31_32_eq( - value, - dal_fixed31_32_zero)) { - *negative = false; - *mantissa = 0; - *exponenta = 0; - return true; - } - - if (dal_fixed31_32_lt( - value, - dal_fixed31_32_zero)) { - *negative = format->sign; - value = dal_fixed31_32_neg(value); - } else { - *negative = false; - } - - if (dal_fixed31_32_lt( - value, - dal_fixed31_32_one)) { - uint32_t i = 1; - - do { - value = dal_fixed31_32_shl(value, 1); - ++i; - } while (dal_fixed31_32_lt( - value, - dal_fixed31_32_one)); - - --i; - - if (exp_offset <= i) { - *mantissa = 0; - *exponenta = 0; - return true; - } - - *exponenta = exp_offset - i; - } else if (dal_fixed31_32_le( - mantissa_constant_plus_max_fraction, - value)) { - uint32_t i = 1; - - do { - value = dal_fixed31_32_shr(value, 1); - ++i; - } while (dal_fixed31_32_lt( - mantissa_constant_plus_max_fraction, - value)); - - *exponenta = exp_offset + i - 1; - } else { - *exponenta = exp_offset; - } - - mantiss = dal_fixed31_32_sub( - value, - dal_fixed31_32_one); - - if (dal_fixed31_32_lt( - mantiss, - dal_fixed31_32_zero) || - dal_fixed31_32_lt( - dal_fixed31_32_one, - mantiss)) - mantiss = dal_fixed31_32_zero; - else - mantiss = dal_fixed31_32_shl( - mantiss, - format->mantissa_bits); - - *mantissa = dal_fixed31_32_floor(mantiss); - - return true; -} - -static bool setup_custom_float( - const struct custom_float_format *format, - bool negative, - uint32_t mantissa, - uint32_t exponenta, - uint32_t *result) -{ - uint32_t i = 0; - uint32_t j = 0; - - uint32_t value = 0; - - /* verification code: - * once calculation is ok we can remove it - */ - - const uint32_t mantissa_mask = - (1 << (format->mantissa_bits + 1)) - 1; - - const uint32_t exponenta_mask = - (1 << (format->exponenta_bits + 1)) - 1; - - if (mantissa & ~mantissa_mask) { - BREAK_TO_DEBUGGER(); - mantissa = mantissa_mask; - } - - if (exponenta & ~exponenta_mask) { - BREAK_TO_DEBUGGER(); - exponenta = exponenta_mask; - } - - /* end of verification code */ - - while (i < format->mantissa_bits) { - uint32_t mask = 1 << i; - - if (mantissa & mask) - value |= mask; - - ++i; - } - - while (j < format->exponenta_bits) { - uint32_t mask = 1 << j; - - if (exponenta & mask) - value |= mask << i; - - ++j; - } - - if (negative && format->sign) - value |= 1 << (i + j); - - *result = value; - - return true; -} - -static bool convert_to_custom_float_format( - struct fixed31_32 value, - const struct custom_float_format *format, - uint32_t *result) -{ - uint32_t mantissa; - uint32_t exponenta; - bool negative; - - return build_custom_float( - value, format, &negative, &mantissa, &exponenta) && - setup_custom_float( - format, negative, mantissa, exponenta, result); -} - static bool convert_to_custom_float( struct pwl_result_data *rgb_resulted, struct curve_points *arr_points, @@ -579,7 +412,7 @@ static bool convert_to_custom_float( return true; } -bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func +static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, struct pwl_params *regamma_params) { struct curve_points *arr_points; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 68632dd28155..a6b4d0d2429f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -58,8 +58,5 @@ void dce110_power_down(struct core_dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); -bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params); - #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/custom_float.h b/drivers/gpu/drm/amd/display/dc/inc/custom_float.h new file mode 100644 index 000000000000..f57239672216 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/custom_float.h @@ -0,0 +1,40 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef CUSTOM_FLOAT_H_ +#define CUSTOM_FLOAT_H_ + +#include "bw_fixed.h" +#include "hw_shared.h" +#include "opp.h" + + +bool convert_to_custom_float_format( + struct fixed31_32 value, + const struct custom_float_format *format, + uint32_t *result); + + +#endif //CUSTOM_FLOAT_H_ -- cgit v1.2.3-59-g8ed1b From a37656b99aca947967f32931bfd5ba04133154d8 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 8 Feb 2017 22:13:52 -0500 Subject: drm/amd/display: report cursor size base on the ASIC Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 1 + 5 files changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d7f848495d8a..13e7134fccb8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,6 +47,8 @@ struct dc_caps { uint32_t max_slave_planes; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; + + unsigned int max_cursor_size; }; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 55501b381692..9ed7c06132fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -984,6 +984,7 @@ static bool construct( pool->base.pipe_count = res_cap.num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 40; + dc->public.caps.max_cursor_size = 128; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index ee4fda514de6..f6e546addbd3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1274,6 +1274,7 @@ static bool construct( dc->public.caps.max_downscale_ratio = 150; dc->public.caps.i2c_speed_in_khz = 100; + dc->public.caps.max_cursor_size = 128; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 54af84ebf2bc..526c106f6ebf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1256,6 +1256,7 @@ static bool construct( pool->base.pipe_count = pool->base.res_cap->num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 100; + dc->public.caps.max_cursor_size = 128; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 3de8bfb47dce..272c7fc31406 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -935,6 +935,7 @@ static bool construct( pool->base.pipe_count = res_cap.num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 40; + dc->public.caps.max_cursor_size = 128; /************************************************* * Create resources * -- cgit v1.2.3-59-g8ed1b From b3c64dff24e829c0b61b340fbaf0efaf20ce5d58 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 10 Feb 2017 17:51:27 -0500 Subject: drm/amd/display: color distortion after DPMS+ background color fix Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 88a2fa99f5da..0afb3c64b651 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1054,6 +1054,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( if (!pipe_ctx_old->stream) { core_link_enable_stream(pipe_ctx); + resource_build_info_frame(pipe_ctx); + dce110_update_info_frame(pipe_ctx); if (dc_is_dp_signal(pipe_ctx->stream->signal)) dce110_unblank_stream(pipe_ctx, &stream->sink->link->public.cur_link_settings); -- cgit v1.2.3-59-g8ed1b From e166ad43d5c1312f258ef4adabe1fac2b9da7e18 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Tue, 14 Feb 2017 07:19:36 +0100 Subject: drm/amd/dc: hw_sequencer: fix semicolon.cocci warnings Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by: Julia Lawall Signed-off-by: Fengguang Wu Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 0afb3c64b651..9b6d251a1c22 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2070,7 +2070,7 @@ static void init_hw(struct core_dc *dc) true); } - dce_clock_gating_power_up(dc->hwseq, false);; + dce_clock_gating_power_up(dc->hwseq, false); /***************************************/ for (i = 0; i < dc->link_count; i++) { -- cgit v1.2.3-59-g8ed1b From 70063a5957126087f167ff3890784d7b3b36c844 Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Thu, 16 Feb 2017 11:04:48 -0500 Subject: drm/amd/display: Add bypass case for PQ transfer function - Source and destination color space should be the same for app control case - Bypass degamma, regamma, and gamut remap - Add hdr supported check for info frame Signed-off-by: Amy Zhang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 ++++- 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 991828f503aa..4d556b379524 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1675,7 +1675,7 @@ static void set_hdr_static_info_packet( hdr_metadata = surface->public.hdr_static_ctx; - if (!hdr_metadata.is_hdr) + if (!hdr_metadata.hdr_supported) return; if (dc_is_hdmi_signal(signal)) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 13e7134fccb8..71d7dde79ae0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -186,6 +186,7 @@ enum { }; struct dc_hdr_static_metadata { + bool hdr_supported; bool is_hdr; /* display chromaticities and white point in units of 0.00001 */ @@ -207,6 +208,7 @@ struct dc_hdr_static_metadata { enum dc_transfer_func_type { TF_TYPE_PREDEFINED, TF_TYPE_DISTRIBUTED_POINTS, + TF_TYPE_BYPASS }; struct dc_transfer_func_distributed_points { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 9b6d251a1c22..9c9183f96e04 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -279,6 +279,8 @@ static bool dce110_set_input_transfer_func( result = false; break; } + } else if (tf->public.type == TF_TYPE_BYPASS) { + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); } else { /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ result = false; @@ -428,7 +430,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t segment_start, segment_end; uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL) + if (output_tf == NULL || regamma_params == NULL || + output_tf->type == TF_TYPE_BYPASS) return false; arr_points = regamma_params->arr_points; -- cgit v1.2.3-59-g8ed1b From 87b58768eccd311fdc7694c09966754d5ce90538 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 16 Feb 2017 22:28:46 -0500 Subject: drm/amd/display: audio bug fix part 1: Add missing audio ACR Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 8 +-- drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 2 + .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 + .../drm/amd/display/dc/dce/dce_stream_encoder.c | 81 +++++++++++++++------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 31 +++++++++ .../drm/amd/display/dc/dce110/dce110_resource.c | 1 + 6 files changed, 95 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index 2749c8fa4f1f..596e039ee315 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -828,11 +828,9 @@ void dce_aud_wall_dto_setup( REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); - /* DAL2 code separate DCCG_AUDIO_DTO_SEL and - DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different - location. merge together should not hurt */ - /*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1; - dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/ + REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, + DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); + } } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h index c244887ba15e..b98ee2d2a9c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h @@ -93,6 +93,7 @@ struct dce_audio_shift { uint8_t DCCG_AUDIO_DTO0_PHASE; uint8_t DCCG_AUDIO_DTO1_MODULE; uint8_t DCCG_AUDIO_DTO1_PHASE; + uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO; }; struct dce_aduio_mask { @@ -109,6 +110,7 @@ struct dce_aduio_mask { uint32_t DCCG_AUDIO_DTO0_PHASE; uint32_t DCCG_AUDIO_DTO1_MODULE; uint32_t DCCG_AUDIO_DTO1_PHASE; + uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO; }; struct dce_audio { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 60fdf58fc5cc..305a9d86a5d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -871,6 +871,8 @@ static bool dce110_link_encoder_validate_hdmi_output( if (max_deep_color < crtc_timing->display_color_depth) return false; + if (crtc_timing->display_color_depth < COLOR_DEPTH_888) + return false; if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index a28d9c7ba17e..aba392ff5095 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -848,7 +848,7 @@ struct audio_clock_info { /* 148.5MHz/1.001*/ /* 148.5MHz*/ -static const struct audio_clock_info audio_clock_info_table[12] = { +static const struct audio_clock_info audio_clock_info_table[16] = { {2517, 4576, 28125, 7007, 31250, 6864, 28125}, {2518, 4576, 28125, 7007, 31250, 6864, 28125}, {2520, 4096, 25200, 6272, 28000, 6144, 25200}, @@ -860,37 +860,63 @@ static const struct audio_clock_info audio_clock_info_table[12] = { {7417, 11648, 210937, 17836, 234375, 11648, 140625}, {7425, 4096, 74250, 6272, 82500, 6144, 74250}, {14835, 11648, 421875, 8918, 234375, 5824, 140625}, - {14850, 4096, 148500, 6272, 165000, 6144, 148500} + {14850, 4096, 148500, 6272, 165000, 6144, 148500}, + {29670, 5824, 421875, 4459, 234375, 5824, 281250}, + {29700, 3072, 222750, 4704, 247500, 5120, 247500}, + {59340, 5824, 843750, 8918, 937500, 5824, 562500}, + {59400, 3072, 445500, 9408, 990000, 6144, 594000} }; -static const struct audio_clock_info audio_clock_info_table_36bpc[12] = { - {2517, 9152, 84375, 7007, 48875, 9152, 56250}, - {2518, 9152, 84375, 7007, 48875, 9152, 56250}, - {2520, 4096, 37800, 6272, 42000, 6144, 37800}, - {2700, 4096, 40500, 6272, 45000, 6144, 40500}, - {2702, 8192, 81081, 6272, 45045, 8192, 54054}, - {2703, 8192, 81081, 6272, 45045, 8192, 54054}, - {5400, 4096, 81000, 6272, 90000, 6144, 81000}, - {5405, 4096, 81081, 6272, 90090, 6144, 81081}, +static const struct audio_clock_info audio_clock_info_table_30bpc[14] = { + {2517, 9152, 70312, 14014, 78125, 9152, 46875}, + {2518, 9152, 70312, 14014, 78125, 9152, 46875}, + {2520, 4096, 31500, 6272, 35000, 6144, 31500}, + {2700, 4096, 33750, 6272, 37500, 6144, 33750}, + {2702, 8192, 67567, 12544, 75075, 8192, 45045}, + {2703, 8192, 67567, 12544, 75075, 8192, 45045}, + {5400, 4096, 67500, 6272, 75000, 6144, 67500}, + {5405, 8192, 135135, 6272, 75075, 8192, 90090}, + {7417, 11648, 263672, 17836, 292969, 11648, 175181}, + {7425, 8192, 185625, 6272, 103125, 12288, 185625}, + {14835, 11648, 527344, 17836, 585938, 11648, 351563}, + {14850, 4096, 185625, 6272, 206250, 6144, 185625}, + {29670, 11648, 527344, 17836, 585938, 11648, 703125}, + {29700, 6144, 556875, 4704, 309375, 5120, 309375} +}; +static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { + {2517, 9152, 84375, 7007, 48875, 9152, 56250}, + {2518, 9152, 84375, 7007, 48875, 9152, 56250}, + {2520, 4096, 37800, 6272, 42000, 6144, 37800}, + {2700, 4096, 40500, 6272, 45000, 6144, 40500}, + {2702, 8192, 81081, 6272, 45045, 8192, 54054}, + {2703, 8192, 81081, 6272, 45045, 8192, 54054}, + {5400, 4096, 81000, 6272, 90000, 6144, 81000}, + {5405, 4096, 81081, 6272, 90090, 6144, 81081}, {7417, 11648, 316406, 17836, 351562, 11648, 210937}, - {7425, 4096, 111375, 6272, 123750, 6144, 111375}, + {7425, 4096, 111375, 6272, 123750, 6144, 111375}, {14835, 11648, 632812, 17836, 703125, 11648, 421875}, - {14850, 4096, 222750, 6272, 247500, 6144, 222750} + {14850, 4096, 222750, 6272, 247500, 6144, 222750}, + {29670, 5824, 632812, 8918, 703125, 5824, 421875}, + {29700, 4096, 445500, 4704, 371250, 5120, 371250} }; -static const struct audio_clock_info audio_clock_info_table_48bpc[12] = { - {2517, 4576, 56250, 7007, 62500, 6864, 56250}, - {2518, 4576, 56250, 7007, 62500, 6864, 56250}, - {2520, 4096, 50400, 6272, 56000, 6144, 50400}, - {2700, 4096, 54000, 6272, 60000, 6144, 54000}, - {2702, 4096, 54054, 6267, 60060, 8192, 54054}, - {2703, 4096, 54054, 6272, 60060, 8192, 54054}, - {5400, 4096, 108000, 6272, 120000, 6144, 108000}, - {5405, 4096, 108108, 6272, 120120, 6144, 108108}, +static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { + {2517, 4576, 56250, 7007, 62500, 6864, 56250}, + {2518, 4576, 56250, 7007, 62500, 6864, 56250}, + {2520, 4096, 50400, 6272, 56000, 6144, 50400}, + {2700, 4096, 54000, 6272, 60000, 6144, 54000}, + {2702, 4096, 54054, 6267, 60060, 8192, 54054}, + {2703, 4096, 54054, 6272, 60060, 8192, 54054}, + {5400, 4096, 108000, 6272, 120000, 6144, 108000}, + {5405, 4096, 108108, 6272, 120120, 6144, 108108}, {7417, 11648, 421875, 17836, 468750, 11648, 281250}, - {7425, 4096, 148500, 6272, 165000, 6144, 148500}, - {14835, 11648, 843750, 8918, 468750, 11648, 281250}, - {14850, 4096, 297000, 6272, 330000, 6144, 297000} + {7425, 4096, 148500, 6272, 165000, 6144, 148500}, + {14835, 11648, 843750, 8918, 468750, 11648, 281250}, + {14850, 4096, 297000, 6272, 330000, 6144, 297000}, + {29670, 5824, 843750, 4459, 468750, 5824, 562500}, + {29700, 3072, 445500, 4704, 495000, 5120, 495000} + + }; union audio_cea_channels speakers_to_channels( @@ -973,6 +999,11 @@ bool get_audio_clock_info( audio_array_size = ARRAY_SIZE( audio_clock_info_table_36bpc); break; + case COLOR_DEPTH_101010: + clock_info = audio_clock_info_table_30bpc; + audio_array_size = ARRAY_SIZE( + audio_clock_info_table_30bpc); + break; default: clock_info = audio_clock_info_table; audio_array_size = ARRAY_SIZE( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 9c9183f96e04..76a397d90adc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -868,6 +868,37 @@ static void build_audio_output( audio_output->crtc_info.calculated_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk; +/*for HDMI, audio ACR is with deep color ratio factor*/ + if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && + audio_output->crtc_info.requested_pixel_clock == + stream->public.timing.pix_clk_khz) { + if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + audio_output->crtc_info.requested_pixel_clock = + audio_output->crtc_info.requested_pixel_clock/2; + audio_output->crtc_info.calculated_pixel_clock = + pipe_ctx->pix_clk_params.requested_pix_clk/2; + } + + if (pipe_ctx->pix_clk_params.pixel_encoding != PIXEL_ENCODING_YCBCR422) { + switch (pipe_ctx->pix_clk_params.color_depth) { + case COLOR_DEPTH_888: + break; + case COLOR_DEPTH_101010: + audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 30) / 24; + break; + case COLOR_DEPTH_121212: + audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 36) / 24; + break; + case COLOR_DEPTH_161616: + audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 48) / 24; + break; + default: + ASSERT(0); + break; + } + } + } + if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { audio_output->pll_info.dp_dto_source_clock_in_khz = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index f6e546addbd3..074fb978e076 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -776,6 +776,7 @@ static void get_pixel_clock_parameters( pixel_clk_params->flags.DISPLAY_BLANKED = 1; pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420); + pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; } void dce110_resource_build_bit_depth_reduction_params( -- cgit v1.2.3-59-g8ed1b From 181a888fcd723c4bc63f43aac50713c34ae9102e Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 17 Feb 2017 13:59:11 -0500 Subject: drm/amd/display: fix incorrect programming for YCbCr422 and YCbCr420 Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 12 +++++++++--- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 +++++++++-------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 3 +++ 3 files changed, 21 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index aba392ff5095..e4092fd458a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -362,9 +362,15 @@ static void dce110_stream_encoder_hdmi_set_stream_attribute( REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); break; case COLOR_DEPTH_101010: - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 1, - HDMI_DEEP_COLOR_ENABLE, 1); + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 1); + } break; case COLOR_DEPTH_121212: if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 76a397d90adc..6915cc46754b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -861,10 +861,6 @@ static void build_audio_output( audio_output->crtc_info.requested_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk; - /* - * TODO - Investigate why calculated pixel clk has to be - * requested pixel clk - */ audio_output->crtc_info.calculated_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk; @@ -1044,15 +1040,14 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->public.timing.display_color_depth, pipe_ctx->stream->signal); + /* FPGA does not program backend */ + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { pipe_ctx->opp->funcs->opp_program_fmt( pipe_ctx->opp, &stream->bit_depth_params, &stream->clamping); - - /* FPGA does not program backend */ - if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) return DC_OK; - + } /* TODO: move to stream encoder */ if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { @@ -1065,6 +1060,12 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->sink->link->link_enc, pipe_ctx->stream->signal); +/*vbios crtc_source_selection and encoder_setup will override fmt_C*/ + pipe_ctx->opp->funcs->opp_program_fmt( + pipe_ctx->opp, + &stream->bit_depth_params, + &stream->clamping); + if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( pipe_ctx->stream_enc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 074fb978e076..478c8d27f3bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -777,6 +777,9 @@ static void get_pixel_clock_parameters( pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420); pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; + if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { + pixel_clk_params->color_depth = COLOR_DEPTH_888; + } } void dce110_resource_build_bit_depth_reduction_params( -- cgit v1.2.3-59-g8ed1b From 4b679bc3cab09f2af44bd34dfc197939a4602aa8 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 22 Feb 2017 13:46:29 -0500 Subject: drm/amd/display: HDMI deep color mode audio issue Signed-off-by: Charlene Liu Acked-by: Harry Wentland Reviewed-by: Charlene Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++++++-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 11 +++++---- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 9 ++++++++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 - .../drm/amd/display/dc/dce/dce_stream_encoder.c | 26 +++++----------------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 --------------- 6 files changed, 28 insertions(+), 46 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4d556b379524..407ce60f253e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1101,9 +1101,14 @@ enum dc_status resource_map_pool_resources( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - if (!resource_is_stream_unchanged(dc->current_context, stream)) + if (!resource_is_stream_unchanged(dc->current_context, stream)) { + if (stream != NULL && dc->current_context->streams[i] != NULL) { + stream->bit_depth_params = + dc->current_context->streams[i]->bit_depth_params; + stream->clamping = dc->current_context->streams[i]->clamping; continue; - + } + } /* mark resources used for stream that is already active */ for (j = 0; j < MAX_PIPES; j++) { struct pipe_ctx *pipe_ctx = diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index e1f579bcd789..4e1a933be021 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -305,7 +305,7 @@ void dc_stream_log( dm_logger_write(dm_logger, log_type, - "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n", + "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", core_stream, core_stream->public.src.x, core_stream->public.src.y, @@ -314,13 +314,16 @@ void dc_stream_log( core_stream->public.dst.x, core_stream->public.dst.y, core_stream->public.dst.width, - core_stream->public.dst.height); + core_stream->public.dst.height, + core_stream->public.output_color_space); dm_logger_write(dm_logger, log_type, - "\tpix_clk_khz: %d, h_total: %d, v_total: %d\n", + "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", core_stream->public.timing.pix_clk_khz, core_stream->public.timing.h_total, - core_stream->public.timing.v_total); + core_stream->public.timing.v_total, + core_stream->public.timing.pixel_encoding, + core_stream->public.timing.display_color_depth); dm_logger_write(dm_logger, log_type, "\tsink name: %s, serial: %d\n", diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index 596e039ee315..7f52e39ec92a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -773,6 +773,15 @@ void dce_aud_wall_dto_setup( crtc_info->calculated_pixel_clock, &clock_info); + dm_logger_write(audio->ctx->logger, LOG_HW_SET_MODE,\ + "\n************************%s:Input::requested_pixel_clock = %d"\ + "calculated_pixel_clock =%d\n"\ + "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ + crtc_info->requested_pixel_clock,\ + crtc_info->calculated_pixel_clock,\ + clock_info.audio_dto_module,\ + clock_info.audio_dto_phase); + /* On TN/SI, Program DTO source select and DTO select before programming DTO modulo and DTO phase. These bits must be programmed first, otherwise there will be no HDMI audio at boot diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 26742e038274..a2a2ecf8d077 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -874,7 +874,6 @@ static bool dce110_program_pix_clk( bp_pc_params.flags.SET_XTALIN_REF_SRC = !pll_settings->use_external_clk; if (pix_clk_params->flags.SUPPORT_YCBCR420) { - bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk / 2; bp_pc_params.flags.SUPPORT_YUV_420 = 1; } } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index e4092fd458a1..d6662fa2f4e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -873,22 +873,6 @@ static const struct audio_clock_info audio_clock_info_table[16] = { {59400, 3072, 445500, 9408, 990000, 6144, 594000} }; -static const struct audio_clock_info audio_clock_info_table_30bpc[14] = { - {2517, 9152, 70312, 14014, 78125, 9152, 46875}, - {2518, 9152, 70312, 14014, 78125, 9152, 46875}, - {2520, 4096, 31500, 6272, 35000, 6144, 31500}, - {2700, 4096, 33750, 6272, 37500, 6144, 33750}, - {2702, 8192, 67567, 12544, 75075, 8192, 45045}, - {2703, 8192, 67567, 12544, 75075, 8192, 45045}, - {5400, 4096, 67500, 6272, 75000, 6144, 67500}, - {5405, 8192, 135135, 6272, 75075, 8192, 90090}, - {7417, 11648, 263672, 17836, 292969, 11648, 175181}, - {7425, 8192, 185625, 6272, 103125, 12288, 185625}, - {14835, 11648, 527344, 17836, 585938, 11648, 351563}, - {14850, 4096, 185625, 6272, 206250, 6144, 185625}, - {29670, 11648, 527344, 17836, 585938, 11648, 703125}, - {29700, 6144, 556875, 4704, 309375, 5120, 309375} -}; static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { {2517, 9152, 84375, 7007, 48875, 9152, 56250}, {2518, 9152, 84375, 7007, 48875, 9152, 56250}, @@ -1005,11 +989,6 @@ bool get_audio_clock_info( audio_array_size = ARRAY_SIZE( audio_clock_info_table_36bpc); break; - case COLOR_DEPTH_101010: - clock_info = audio_clock_info_table_30bpc; - audio_array_size = ARRAY_SIZE( - audio_clock_info_table_30bpc); - break; default: clock_info = audio_clock_info_table; audio_array_size = ARRAY_SIZE( @@ -1114,6 +1093,11 @@ static void dce110_se_setup_hdmi_audio( crtc_info->requested_pixel_clock, crtc_info->calculated_pixel_clock, &audio_clock_info)) { + dm_logger_write(enc->ctx->logger, LOG_HW_SET_MODE, + "\n*********************%s:Input::requested_pixel_clock = %d"\ + "calculated_pixel_clock = %d \n", __func__,\ + crtc_info->requested_pixel_clock,\ + crtc_info->calculated_pixel_clock); /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6915cc46754b..2f68bf20dfe2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -873,25 +873,7 @@ static void build_audio_output( audio_output->crtc_info.requested_pixel_clock/2; audio_output->crtc_info.calculated_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk/2; - } - if (pipe_ctx->pix_clk_params.pixel_encoding != PIXEL_ENCODING_YCBCR422) { - switch (pipe_ctx->pix_clk_params.color_depth) { - case COLOR_DEPTH_888: - break; - case COLOR_DEPTH_101010: - audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 30) / 24; - break; - case COLOR_DEPTH_121212: - audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 36) / 24; - break; - case COLOR_DEPTH_161616: - audio_output->crtc_info.calculated_pixel_clock = (audio_output->crtc_info.calculated_pixel_clock * 48) / 24; - break; - default: - ASSERT(0); - break; - } } } -- cgit v1.2.3-59-g8ed1b From d5b4f2bcff03c6cafb0a890360f1f8fbc99071a1 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 22 Feb 2017 18:26:20 -0500 Subject: drm/amd/display: 420 clock divided by 2 twice Signed-off-by: Charlene Liu Acked-by: Harry Wentland Reviewed-by: Krunoslav Kovac Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 478c8d27f3bd..cd3942df70a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -780,6 +780,9 @@ static void get_pixel_clock_parameters( if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { pixel_clk_params->color_depth = COLOR_DEPTH_888; } + if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; + } } void dce110_resource_build_bit_depth_reduction_params( -- cgit v1.2.3-59-g8ed1b From 5936223f7b51e122beb511265e2112777f7a887e Mon Sep 17 00:00:00 2001 From: Jordan Lazare Date: Thu, 23 Feb 2017 14:07:29 -0500 Subject: drm/amd/display: Fix gamma colour corruption for 10 bit surfaces Gamma LUT shouldn't be used for 10-bit and above. Should instead be using prescale and bypassing input gamma. Signed-off-by: Jordan Lazare Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 15 ++++- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 3 +- .../gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c | 71 ---------------------- 3 files changed, 15 insertions(+), 74 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2f68bf20dfe2..2d2daa694a30 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -233,6 +233,19 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } + +/* Only use LUT for 8 bit formats */ +static bool use_lut(const struct core_surface *surface) +{ + switch (surface->public.format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + return true; + default: + return false; + } +} + static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct core_surface *surface) @@ -251,7 +264,7 @@ static bool dce110_set_input_transfer_func( build_prescale_params(&prescale_params, surface); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - if (surface->public.gamma_correction) + if (surface->public.gamma_correction && use_lut(surface)) ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); if (tf == NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index 0261d1bfccb5..8d2c3dbfced1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -2,8 +2,7 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. -DCE80 = dce80_ipp.o dce80_ipp_gamma.o \ - dce80_timing_generator.o \ +DCE80 = dce80_ipp.o dce80_timing_generator.o \ dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \ dce80_resource.o diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c deleted file mode 100644 index 760168df5290..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp_gamma.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "include/logger_interface.h" -#include "include/fixed31_32.h" -#include "basics/conversion.h" - -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "dce80_ipp.h" -#include "dce110/dce110_ipp.h" - -#define DCP_REG(reg)\ - (reg + ipp80->offsets.dcp_offset) - -/*PROTOTYPE DECLARATIONS*/ - -static void set_legacy_input_gamma_mode( - struct dce110_ipp *ipp80, - bool is_legacy); - -void dce80_ipp_set_legacy_input_gamma_mode( - struct input_pixel_processor *ipp, - bool is_legacy) -{ - struct dce110_ipp *ipp80 = TO_DCE80_IPP(ipp); - - set_legacy_input_gamma_mode(ipp80, is_legacy); -} - -static void set_legacy_input_gamma_mode( - struct dce110_ipp *ipp80, - bool is_legacy) -{ - const uint32_t addr = DCP_REG(mmINPUT_GAMMA_CONTROL); - uint32_t value = dm_read_reg(ipp80->base.ctx, addr); - - set_reg_field_value( - value, - !is_legacy, - INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE); - - dm_write_reg(ipp80->base.ctx, addr, value); -} - -- cgit v1.2.3-59-g8ed1b From 1781958ff41b28b3cd7b4a2ed691c932031c5515 Mon Sep 17 00:00:00 2001 From: Leon Elazar Date: Thu, 23 Feb 2017 16:10:43 -0500 Subject: drm/amd/display: Surface Validation Fixes + Audio Mask 1. dc: Adding missing mask for audio register DCCG_AUDIO_DTO_SOURCE 2. Changing the surface validation to check the limits of the clip rect instead of the source rect. Signed-off-by: Leon Elazar Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 1 + drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h index b98ee2d2a9c7..0dc5ff137c7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h @@ -48,6 +48,7 @@ #define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\ SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\ SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index cd3942df70a7..80b2359a3cb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1009,10 +1009,10 @@ static bool dce110_validate_surface_sets( if (set[i].surface_count > 2) return false; - if (set[i].surfaces[0]->src_rect.width - < set[i].stream->src.width - || set[i].surfaces[0]->src_rect.height - < set[i].stream->src.height) + if (set[i].surfaces[0]->clip_rect.width + > set[i].stream->src.width + || set[i].surfaces[0]->clip_rect.height + > set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 526c106f6ebf..ce6c69fd1041 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -975,9 +975,9 @@ static bool dce112_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - < set[i].stream->src.width + > set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - < set[i].stream->src.height) + > set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 272c7fc31406..fbbdd0ee2d4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -805,9 +805,9 @@ static bool dce80_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].stream->src.width + > set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].stream->src.height) + > set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) -- cgit v1.2.3-59-g8ed1b From 648013696767f0266aa7bd44407786a99f7a7910 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 24 Feb 2017 11:31:23 -0500 Subject: drm/amd/display: Fix warnings in DC Signed-off-by: Harry Wentland Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 1 - drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c | 1 - 4 files changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 6516c275e0c7..e0d9572768cb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1068,7 +1068,6 @@ bool dc_pre_update_surfaces_to_stream( int prev_disp_clk = core_dc->current_context->dispclk_khz; struct dc_stream_status *stream_status = NULL; struct validate_context *context; - struct validate_context *temp_context; bool ret = true; pre_surface_trace(dc, new_surfaces, new_surface_count); @@ -1425,7 +1424,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FULL) { for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - struct core_stream *stream = pipe_ctx->stream; if (pipe_ctx->surface != surface) continue; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 21fedd447bd1..943895faee49 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -121,7 +121,7 @@ const struct dc_surface_status *dc_surface_get_status( const struct dc_surface *dc_surface) { struct dc_surface_status *surface_status; - struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface);; + struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface); struct core_dc *core_dc; int i; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 7005ebb28d46..45a3079c0973 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -292,7 +292,6 @@ static void dce_abm_init(struct abm *abm) static bool dce_abm_set_level(struct abm *abm, uint32_t level) { struct dce_abm *abm_dce = TO_DCE_ABM(abm); - struct dc_context *ctx = abm_dce->base.ctx; REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 682a3de7ba48..c95b69446ced 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -74,7 +74,6 @@ static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) { - struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t addr = mmCRTCV_BLANK_CONTROL; uint32_t value = dm_read_reg(tg->ctx, addr); -- cgit v1.2.3-59-g8ed1b From 45209ef7197bd4b5e7e224ff46fa9a3eca25c3bd Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 24 Feb 2017 14:19:40 -0500 Subject: drm/amd/display: remove apply_clk_constraints, used validate_bandwidth universally Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Dmytro Laktyushkin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 50 ++++++++++++++-------- .../drm/amd/display/dc/dce100/dce100_resource.c | 10 +++-- .../drm/amd/display/dc/dce110/dce110_resource.c | 18 ++++---- .../drm/amd/display/dc/dce112/dce112_resource.c | 18 ++++---- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/core_status.h | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +-- 8 files changed, 59 insertions(+), 50 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e0d9572768cb..da0f72071ef5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1144,12 +1144,11 @@ bool dc_pre_update_surfaces_to_stream( } } - if (core_dc->res_pool->funcs->validate_bandwidth) - if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, context) != DC_OK) { - BREAK_TO_DEBUGGER(); - ret = false; - goto unexpected_fail; - } + if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { + BREAK_TO_DEBUGGER(); + ret = false; + goto unexpected_fail; + } if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) && prev_disp_clk < context->dispclk_khz) { @@ -1184,28 +1183,36 @@ val_ctx_fail: bool dc_post_update_surfaces_to_stream(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); int i; + struct core_dc *core_dc = DC_TO_CORE(dc); + struct validate_context *context = dm_alloc(sizeof(struct validate_context)); + + if (!context) { + dm_error("%s: failed to create validate ctx\n", __func__); + return false; + } + resource_validate_ctx_copy_construct(core_dc->current_context, context); post_surface_trace(dc); - for (i = 0; i < core_dc->current_context->res_ctx.pool->pipe_count; i++) - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == NULL) { - core_dc->current_context->res_ctx.pipe_ctx[i].pipe_idx = i; + for (i = 0; i < context->res_ctx.pool->pipe_count; i++) + if (context->res_ctx.pipe_ctx[i].stream == NULL) { + context->res_ctx.pipe_ctx[i].pipe_idx = i; core_dc->hwss.power_down_front_end( - core_dc, &core_dc->current_context->res_ctx.pipe_ctx[i]); - } - if (core_dc->res_pool->funcs->validate_bandwidth) - if (core_dc->res_pool->funcs->validate_bandwidth( - core_dc, core_dc->current_context) != DC_OK) { - BREAK_TO_DEBUGGER(); - return false; + core_dc, &context->res_ctx.pipe_ctx[i]); } + if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { + BREAK_TO_DEBUGGER(); + return false; + } core_dc->hwss.set_bandwidth(core_dc); - pplib_apply_display_requirements( - core_dc, core_dc->current_context, &core_dc->current_context->pp_display_cfg); + /*TODO: dce specific*/ + pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg); + + resource_validate_ctx_destruct(core_dc->current_context); + core_dc->current_context = context; return true; } @@ -1472,6 +1479,11 @@ void dc_update_surfaces_for_stream(struct dc *dc, *(updates[i].hdr_static_metadata); } + if (update_type == UPDATE_TYPE_FULL && + !core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { + BREAK_TO_DEBUGGER(); + return; + } if (!surface_count) /* reset */ core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 9ed7c06132fe..fc85efafb104 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -765,14 +765,14 @@ static enum dc_status validate_mapped_resource( return DC_OK; } -enum dc_status dce100_validate_bandwidth( +bool dce100_validate_bandwidth( const struct core_dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ context->dispclk_khz = 681000; - return DC_OK; + return false; } static bool dce100_validate_surface_sets( @@ -840,7 +840,8 @@ enum dc_status dce100_validate_with_context( result = resource_build_scaling_params_for_context(dc, context); if (result == DC_OK) - result = dce100_validate_bandwidth(dc, context); + if (!dce100_validate_bandwidth(dc, context)) + result = DC_FAIL_BANDWIDTH_VALIDATE; return result; } @@ -873,7 +874,8 @@ enum dc_status dce100_validate_guaranteed( } if (result == DC_OK) - result = dce100_validate_bandwidth(dc, context); + if (!dce100_validate_bandwidth(dc, context)) + result = DC_FAIL_BANDWIDTH_VALIDATE; return result; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 80b2359a3cb4..b9d0b5eeca13 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -912,30 +912,28 @@ static enum dc_status validate_mapped_resource( return DC_OK; } -enum dc_status dce110_validate_bandwidth( +bool dce110_validate_bandwidth( const struct core_dc *dc, struct validate_context *context) { - enum dc_status result = DC_ERROR_UNEXPECTED; + bool result = false; dm_logger_write( dc->ctx->logger, LOG_BANDWIDTH_CALCS, "%s: start", __func__); - if (!bw_calcs( + if (bw_calcs( dc->ctx, &dc->bw_dceip, &dc->bw_vbios, context->res_ctx.pipe_ctx, context->res_ctx.pool->pipe_count, &context->bw_results)) - result = DC_FAIL_BANDWIDTH_VALIDATE; - else - result = DC_OK; + result = true; context->dispclk_khz = context->bw_results.dispclk_khz; - if (result == DC_FAIL_BANDWIDTH_VALIDATE) + if (!result) dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: %dx%d@%d Bandwidth validation failed!\n", __func__, @@ -1073,7 +1071,8 @@ enum dc_status dce110_validate_with_context( result = resource_build_scaling_params_for_context(dc, context); if (result == DC_OK) - result = dce110_validate_bandwidth(dc, context); + if (!dce110_validate_bandwidth(dc, context)) + result = DC_FAIL_BANDWIDTH_VALIDATE; return result; } @@ -1106,7 +1105,8 @@ enum dc_status dce110_validate_guaranteed( } if (result == DC_OK) - result = dce110_validate_bandwidth(dc, context); + if (!dce110_validate_bandwidth(dc, context)) + result = DC_FAIL_BANDWIDTH_VALIDATE; return result; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index ce6c69fd1041..32aa1b5bf1f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -836,30 +836,28 @@ static enum dc_status validate_mapped_resource( return DC_OK; } -enum dc_status dce112_validate_bandwidth( +bool dce112_validate_bandwidth( const struct core_dc *dc, struct validate_context *context) { - enum dc_status result = DC_ERROR_UNEXPECTED; + bool result = false; dm_logger_write( dc->ctx->logger, LOG_BANDWIDTH_CALCS, "%s: start", __func__); - if (!bw_calcs( + if (bw_calcs( dc->ctx, &dc->bw_dceip, &dc->bw_vbios, context->res_ctx.pipe_ctx, context->res_ctx.pool->pipe_count, &context->bw_results)) - result = DC_FAIL_BANDWIDTH_VALIDATE; - else - result = DC_OK; + result = true; context->dispclk_khz = context->bw_results.dispclk_khz; - if (result == DC_FAIL_BANDWIDTH_VALIDATE) + if (!result) dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: Bandwidth validation failed!", __func__); @@ -1026,7 +1024,8 @@ enum dc_status dce112_validate_with_context( result = resource_build_scaling_params_for_context(dc, context); if (result == DC_OK) - result = dce112_validate_bandwidth(dc, context); + if (!dce112_validate_bandwidth(dc, context)) + result = DC_FAIL_BANDWIDTH_VALIDATE; return result; } @@ -1059,7 +1058,8 @@ enum dc_status dce112_validate_guaranteed( } if (result == DC_OK) - result = dce112_validate_bandwidth(dc, context); + if (!dce112_validate_bandwidth(dc, context)) + result = DC_FAIL_BANDWIDTH_VALIDATE; return result; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index faa8c45a3544..dc842aace766 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -46,7 +46,7 @@ enum dc_status dce112_validate_guaranteed( const struct dc_stream *dc_stream, struct validate_context *context); -enum dc_status dce112_validate_bandwidth( +bool dce112_validate_bandwidth( const struct core_dc *dc, struct validate_context *context); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index fbbdd0ee2d4c..a3e8182885b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -780,7 +780,7 @@ static enum dc_status validate_mapped_resource( return DC_OK; } -enum dc_status dce80_validate_bandwidth( +bool dce80_validate_bandwidth( const struct core_dc *dc, struct validate_context *context) { @@ -788,7 +788,7 @@ enum dc_status dce80_validate_bandwidth( context->dispclk_khz = 681000; context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; - return DC_OK; + return true; } static bool dce80_validate_surface_sets( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h index 23d52aea55dd..128617dabc4a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -41,7 +41,6 @@ enum dc_status { DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11, DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */ DC_FAIL_SCALING = 13, - DC_FAIL_CLK_CONSTRAINT = 14, DC_ERROR_UNEXPECTED = -1 }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 124df6795b34..e8fe333c5918 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -207,11 +207,7 @@ struct resource_funcs { const struct dc_stream *stream, struct validate_context *context); - enum dc_status (*validate_bandwidth)( - const struct core_dc *dc, - struct validate_context *context); - - struct validate_context *(*apply_clk_constraints)( + bool (*validate_bandwidth)( const struct core_dc *dc, struct validate_context *context); -- cgit v1.2.3-59-g8ed1b From cf43759306002e29f025344504dc680a9a0b3ac8 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 22 Feb 2017 17:52:22 -0500 Subject: drm/amd/display: bandwidth update fix Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 173 +------------ .../amd/display/dc/dce100/dce100_hw_sequencer.c | 15 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 279 ++++++++++++--------- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 16 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 9 +- 5 files changed, 179 insertions(+), 313 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index da0f72071ef5..0ec2c4f39735 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -795,159 +795,6 @@ static bool streams_changed( return false; } -static void fill_display_configs( - const struct validate_context *context, - struct dm_pp_display_configuration *pp_display_cfg) -{ - int j; - int num_cfgs = 0; - - for (j = 0; j < context->stream_count; j++) { - int k; - - const struct core_stream *stream = context->streams[j]; - struct dm_pp_single_disp_config *cfg = - &pp_display_cfg->disp_configs[num_cfgs]; - const struct pipe_ctx *pipe_ctx = NULL; - - for (k = 0; k < MAX_PIPES; k++) - if (stream == context->res_ctx.pipe_ctx[k].stream) { - pipe_ctx = &context->res_ctx.pipe_ctx[k]; - break; - } - - ASSERT(pipe_ctx != NULL); - - num_cfgs++; - cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->pipe_idx; - cfg->src_height = stream->public.src.height; - cfg->src_width = stream->public.src.width; - cfg->ddi_channel_mapping = - stream->sink->link->ddi_channel_mapping.raw; - cfg->transmitter = - stream->sink->link->link_enc->transmitter; - cfg->link_settings.lane_count = - stream->sink->link->public.cur_link_settings.lane_count; - cfg->link_settings.link_rate = - stream->sink->link->public.cur_link_settings.link_rate; - cfg->link_settings.link_spread = - stream->sink->link->public.cur_link_settings.link_spread; - cfg->sym_clock = stream->phy_pix_clk; - /* Round v_refresh*/ - cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; - cfg->v_refresh /= stream->public.timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) - / stream->public.timing.v_total; - } - - pp_display_cfg->display_count = num_cfgs; -} - -static uint32_t get_min_vblank_time_us(const struct validate_context *context) -{ - uint8_t j; - uint32_t min_vertical_blank_time = -1; - - for (j = 0; j < context->stream_count; j++) { - const struct dc_stream *stream = &context->streams[j]->public; - uint32_t vertical_blank_in_pixels = 0; - uint32_t vertical_blank_time = 0; - - vertical_blank_in_pixels = stream->timing.h_total * - (stream->timing.v_total - - stream->timing.v_addressable); - - vertical_blank_time = vertical_blank_in_pixels - * 1000 / stream->timing.pix_clk_khz; - - if (min_vertical_blank_time > vertical_blank_time) - min_vertical_blank_time = vertical_blank_time; - } - - return min_vertical_blank_time; -} - -static int determine_sclk_from_bounding_box( - const struct core_dc *dc, - int required_sclk) -{ - int i; - - /* - * Some asics do not give us sclk levels, so we just report the actual - * required sclk - */ - if (dc->sclk_lvls.num_levels == 0) - return required_sclk; - - for (i = 0; i < dc->sclk_lvls.num_levels; i++) { - if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) - return dc->sclk_lvls.clocks_in_khz[i]; - } - /* - * even maximum level could not satisfy requirement, this - * is unexpected at this stage, should have been caught at - * validation time - */ - ASSERT(0); - return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; -} - -void pplib_apply_display_requirements( - struct core_dc *dc, - const struct validate_context *context, - struct dm_pp_display_configuration *pp_display_cfg) -{ - pp_display_cfg->all_displays_in_sync = - context->bw_results.all_displays_in_sync; - pp_display_cfg->nb_pstate_switch_disable = - context->bw_results.nbp_state_change_enable == false; - pp_display_cfg->cpu_cc6_disable = - context->bw_results.cpuc_state_change_enable == false; - pp_display_cfg->cpu_pstate_disable = - context->bw_results.cpup_state_change_enable == false; - pp_display_cfg->cpu_pstate_separation_time = - context->bw_results.blackout_recovery_time_us; - - pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk - / MEMORY_TYPE_MULTIPLIER; - - pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( - dc, - context->bw_results.required_sclk); - - pp_display_cfg->min_engine_clock_deep_sleep_khz - = context->bw_results.required_sclk_deep_sleep; - - pp_display_cfg->avail_mclk_switch_time_us = - get_min_vblank_time_us(context); - /* TODO: dce11.2*/ - pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - - pp_display_cfg->disp_clk_khz = context->dispclk_khz; - - fill_display_configs(context, pp_display_cfg); - - /* TODO: is this still applicable?*/ - if (pp_display_cfg->display_count == 1) { - const struct dc_crtc_timing *timing = - &context->streams[0]->public.timing; - - pp_display_cfg->crtc_index = - pp_display_cfg->disp_configs[0].pipe_idx; - pp_display_cfg->line_time_in_us = timing->h_total * 1000 - / timing->pix_clk_khz; - } - - if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( - struct dm_pp_display_configuration)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); - - dc->prev_display_config = *pp_display_cfg; - -} - bool dc_commit_streams( struct dc *dc, const struct dc_stream *streams[], @@ -1036,9 +883,6 @@ bool dc_commit_streams( context->streams[i]->public.timing.pix_clk_khz); } - pplib_apply_display_requirements(core_dc, - context, &context->pp_display_cfg); - resource_validate_ctx_destruct(core_dc->current_context); if (core_dc->temp_flip_context != core_dc->current_context) { @@ -1065,7 +909,6 @@ bool dc_pre_update_surfaces_to_stream( { int i, j; struct core_dc *core_dc = DC_TO_CORE(dc); - int prev_disp_clk = core_dc->current_context->dispclk_khz; struct dc_stream_status *stream_status = NULL; struct validate_context *context; bool ret = true; @@ -1150,16 +993,7 @@ bool dc_pre_update_surfaces_to_stream( goto unexpected_fail; } - if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) - && prev_disp_clk < context->dispclk_khz) { - pplib_apply_display_requirements(core_dc, context, - &context->pp_display_cfg); - context->res_ctx.pool->display_clock->funcs->set_clock( - context->res_ctx.pool->display_clock, - context->dispclk_khz * 115 / 100); - core_dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; - core_dc->current_context->dispclk_khz = context->dispclk_khz; - } + core_dc->hwss.set_bandwidth(core_dc, context, false); for (i = 0; i < new_surface_count; i++) for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { @@ -1206,10 +1040,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) return false; } - core_dc->hwss.set_bandwidth(core_dc); - - /*TODO: dce specific*/ - pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg); + core_dc->hwss.set_bandwidth(core_dc, context, true); resource_validate_ctx_destruct(core_dc->current_context); core_dc->current_context = context; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index e2fe024e1182..bd8e19f1038b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -104,22 +104,18 @@ static bool dce100_enable_display_power_gating( return false; } -static void set_display_mark_for_pipe_if_needed(struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - /* Do nothing until we have proper bandwitdth calcs */ -} - static void set_displaymarks( const struct core_dc *dc, struct validate_context *context) { /* Do nothing until we have proper bandwitdth calcs */ } -static void set_bandwidth(struct core_dc *dc) +static void set_bandwidth( + struct core_dc *dc, + struct validate_context *context, + bool decrease_allowed) { - /* Do nothing until we have proper bandwitdth calcs */ + dc->hwss.set_displaymarks(dc, context); } @@ -132,7 +128,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc) /* TODO: dce80 is empty implementation at the moment*/ dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.set_displaymarks = set_displaymarks; - dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed; dc->hwss.set_bandwidth = set_bandwidth; return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2d2daa694a30..d9dcb37a4f65 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1209,93 +1209,6 @@ static uint32_t compute_pstate_blackout_duration( return total_dest_line_time_ns; } -/* get the index of the pipe_ctx if there were no gaps in the pipe_ctx array*/ -int get_bw_result_idx( - struct resource_context *res_ctx, - int pipe_idx) -{ - int i, collapsed_idx; - - if (res_ctx->pipe_ctx[pipe_idx].top_pipe) - return 3; - - collapsed_idx = 0; - for (i = 0; i < pipe_idx; i++) { - if (res_ctx->pipe_ctx[i].stream) - collapsed_idx++; - } - - return collapsed_idx; -} - -static bool is_watermark_set_a_greater( - const struct bw_watermarks *set_a, - const struct bw_watermarks *set_b) -{ - if (set_a->a_mark > set_b->a_mark - || set_a->b_mark > set_b->b_mark - || set_a->c_mark > set_b->c_mark - || set_a->d_mark > set_b->d_mark) - return true; - return false; -} - -static bool did_watermarks_increase( - struct pipe_ctx *pipe_ctx, - struct validate_context *context, - struct validate_context *old_context) -{ - int collapsed_pipe_idx = get_bw_result_idx(&context->res_ctx, - pipe_ctx->pipe_idx); - int old_collapsed_pipe_idx = get_bw_result_idx(&old_context->res_ctx, - pipe_ctx->pipe_idx); - struct pipe_ctx *old_pipe_ctx = &old_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - - if (!old_pipe_ctx->stream) - return true; - - if (is_watermark_set_a_greater( - &context->bw_results.nbp_state_change_wm_ns[collapsed_pipe_idx], - &old_context->bw_results.nbp_state_change_wm_ns[old_collapsed_pipe_idx])) - return true; - if (is_watermark_set_a_greater( - &context->bw_results.stutter_exit_wm_ns[collapsed_pipe_idx], - &old_context->bw_results.stutter_exit_wm_ns[old_collapsed_pipe_idx])) - return true; - if (is_watermark_set_a_greater( - &context->bw_results.urgent_wm_ns[collapsed_pipe_idx], - &old_context->bw_results.urgent_wm_ns[old_collapsed_pipe_idx])) - return true; - - return false; -} - -static void program_wm_for_pipe(struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - int total_dest_line_time_ns = compute_pstate_blackout_duration( - dc->bw_vbios.blackout_duration, - pipe_ctx->stream); - int bw_result_idx = get_bw_result_idx(&context->res_ctx, - pipe_ctx->pipe_idx); - - pipe_ctx->mi->funcs->mem_input_program_display_marks( - pipe_ctx->mi, - context->bw_results.nbp_state_change_wm_ns[bw_result_idx], - context->bw_results.stutter_exit_wm_ns[bw_result_idx], - context->bw_results.urgent_wm_ns[bw_result_idx], - total_dest_line_time_ns); - - if (pipe_ctx->top_pipe) - pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( - pipe_ctx->mi, - context->bw_results.nbp_state_change_wm_ns[bw_result_idx + 1], - context->bw_results.stutter_exit_wm_ns[bw_result_idx + 1], - context->bw_results.urgent_wm_ns[bw_result_idx + 1], - total_dest_line_time_ns); -} - void dce110_set_displaymarks( const struct core_dc *dc, struct validate_context *context) @@ -1589,7 +1502,7 @@ static void reset_hw_ctx_wrap( } } -/*TODO: const validate_context*/ + enum dc_status dce110_apply_ctx_to_hw( struct core_dc *dc, struct validate_context *context) @@ -1768,7 +1681,7 @@ enum dc_status dce110_apply_ctx_to_hw( return status; } - dc->hwss.set_displaymarks(dc, context); + dc->hwss.set_bandwidth(dc, context, true); /* to save power */ apply_min_clocks(dc, context, &clocks_state, false); @@ -1777,6 +1690,7 @@ enum dc_status dce110_apply_ctx_to_hw( switch_dp_clock_sources(dc, &context->res_ctx); + return DC_OK; } @@ -2135,7 +2049,6 @@ static void init_hw(struct core_dc *dc) } } -/* TODO: move this to apply_ctx_tohw some how?*/ static void dce110_power_on_pipe_if_needed( struct core_dc *dc, struct pipe_ctx *pipe_ctx, @@ -2180,31 +2093,175 @@ static void dce110_power_on_pipe_if_needed( } } -static void dce110_increase_watermarks_for_pipe( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) +static void fill_display_configs( + const struct validate_context *context, + struct dm_pp_display_configuration *pp_display_cfg) +{ + int j; + int num_cfgs = 0; + + for (j = 0; j < context->stream_count; j++) { + int k; + + const struct core_stream *stream = context->streams[j]; + struct dm_pp_single_disp_config *cfg = + &pp_display_cfg->disp_configs[num_cfgs]; + const struct pipe_ctx *pipe_ctx = NULL; + + for (k = 0; k < MAX_PIPES; k++) + if (stream == context->res_ctx.pipe_ctx[k].stream) { + pipe_ctx = &context->res_ctx.pipe_ctx[k]; + break; + } + + ASSERT(pipe_ctx != NULL); + + num_cfgs++; + cfg->signal = pipe_ctx->stream->signal; + cfg->pipe_idx = pipe_ctx->pipe_idx; + cfg->src_height = stream->public.src.height; + cfg->src_width = stream->public.src.width; + cfg->ddi_channel_mapping = + stream->sink->link->ddi_channel_mapping.raw; + cfg->transmitter = + stream->sink->link->link_enc->transmitter; + cfg->link_settings.lane_count = + stream->sink->link->public.cur_link_settings.lane_count; + cfg->link_settings.link_rate = + stream->sink->link->public.cur_link_settings.link_rate; + cfg->link_settings.link_spread = + stream->sink->link->public.cur_link_settings.link_spread; + cfg->sym_clock = stream->phy_pix_clk; + /* Round v_refresh*/ + cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; + cfg->v_refresh /= stream->public.timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) + / stream->public.timing.v_total; + } + + pp_display_cfg->display_count = num_cfgs; +} + +static uint32_t get_min_vblank_time_us(const struct validate_context *context) { - if (did_watermarks_increase(pipe_ctx, context, dc->current_context)) - program_wm_for_pipe(dc, pipe_ctx, context); + uint8_t j; + uint32_t min_vertical_blank_time = -1; + + for (j = 0; j < context->stream_count; j++) { + const struct dc_stream *stream = &context->streams[j]->public; + uint32_t vertical_blank_in_pixels = 0; + uint32_t vertical_blank_time = 0; + + vertical_blank_in_pixels = stream->timing.h_total * + (stream->timing.v_total + - stream->timing.v_addressable); + + vertical_blank_time = vertical_blank_in_pixels + * 1000 / stream->timing.pix_clk_khz; + + if (min_vertical_blank_time > vertical_blank_time) + min_vertical_blank_time = vertical_blank_time; + } + + return min_vertical_blank_time; } -static void dce110_set_bandwidth(struct core_dc *dc) +static int determine_sclk_from_bounding_box( + const struct core_dc *dc, + int required_sclk) { int i; - for (i = 0; i < dc->current_context->res_ctx.pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + /* + * Some asics do not give us sclk levels, so we just report the actual + * required sclk + */ + if (dc->sclk_lvls.num_levels == 0) + return required_sclk; - if (!pipe_ctx->stream) - continue; + for (i = 0; i < dc->sclk_lvls.num_levels; i++) { + if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) + return dc->sclk_lvls.clocks_in_khz[i]; + } + /* + * even maximum level could not satisfy requirement, this + * is unexpected at this stage, should have been caught at + * validation time + */ + ASSERT(0); + return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; +} + +static void pplib_apply_display_requirements( + struct core_dc *dc, + struct validate_context *context) +{ + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + + pp_display_cfg->all_displays_in_sync = + context->bw_results.all_displays_in_sync; + pp_display_cfg->nb_pstate_switch_disable = + context->bw_results.nbp_state_change_enable == false; + pp_display_cfg->cpu_cc6_disable = + context->bw_results.cpuc_state_change_enable == false; + pp_display_cfg->cpu_pstate_disable = + context->bw_results.cpup_state_change_enable == false; + pp_display_cfg->cpu_pstate_separation_time = + context->bw_results.blackout_recovery_time_us; + + pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk + / MEMORY_TYPE_MULTIPLIER; + + pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( + dc, + context->bw_results.required_sclk); + + pp_display_cfg->min_engine_clock_deep_sleep_khz + = context->bw_results.required_sclk_deep_sleep; + + pp_display_cfg->avail_mclk_switch_time_us = + get_min_vblank_time_us(context); + /* TODO: dce11.2*/ + pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - program_wm_for_pipe(dc, pipe_ctx, dc->current_context); + pp_display_cfg->disp_clk_khz = context->dispclk_khz; + + fill_display_configs(context, pp_display_cfg); + + /* TODO: is this still applicable?*/ + if (pp_display_cfg->display_count == 1) { + const struct dc_crtc_timing *timing = + &context->streams[0]->public.timing; + + pp_display_cfg->crtc_index = + pp_display_cfg->disp_configs[0].pipe_idx; + pp_display_cfg->line_time_in_us = timing->h_total * 1000 + / timing->pix_clk_khz; + } + + if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( + struct dm_pp_display_configuration)) != 0) + dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); + + dc->prev_display_config = *pp_display_cfg; +} + +static void dce110_set_bandwidth( + struct core_dc *dc, + struct validate_context *context, + bool decrease_allowed) +{ + dc->hwss.set_displaymarks(dc, context); + + if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { + context->res_ctx.pool->display_clock->funcs->set_clock( + context->res_ctx.pool->display_clock, + context->dispclk_khz * 115 / 100); + dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; + dc->current_context->dispclk_khz = context->dispclk_khz; } - dc->current_context->res_ctx.pool->display_clock->funcs->set_clock( - dc->current_context->res_ctx.pool->display_clock, - dc->current_context->dispclk_khz * 115 / 100); + pplib_apply_display_requirements(dc, context); } static void dce110_program_front_end_for_pipe( @@ -2335,15 +2392,6 @@ static void dce110_program_front_end_for_pipe( pipe_ctx->scl_data.recout.y); } -static void dce110_prepare_pipe_for_context( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - dce110_power_on_pipe_if_needed(dc, pipe_ctx, context); - dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context); -} - static void dce110_apply_ctx_for_surface( struct core_dc *dc, struct core_surface *surface, @@ -2388,7 +2436,7 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) static const struct hw_sequencer_funcs dce110_funcs = { .init_hw = init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, - .prepare_pipe_for_context = dce110_prepare_pipe_for_context, + .prepare_pipe_for_context = dce110_power_on_pipe_if_needed, .apply_ctx_for_surface = dce110_apply_ctx_for_surface, .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, @@ -2407,7 +2455,6 @@ static const struct hw_sequencer_funcs dce110_funcs = { .power_down_front_end = dce110_power_down_fe, .pipe_control_lock = dce_pipe_control_lock, .set_displaymarks = dce110_set_displaymarks, - .increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, .set_static_screen_control = set_static_screen_control, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index c7a2b768bcd1..85a54d963f8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -106,23 +106,18 @@ static bool dce80_enable_display_power_gating( return false; } - -static void set_display_mark_for_pipe_if_needed(struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - /* Do nothing until we have proper bandwitdth calcs */ -} - static void set_displaymarks( const struct core_dc *dc, struct validate_context *context) { /* Do nothing until we have proper bandwitdth calcs */ } -static void set_bandwidth(struct core_dc *dc) +static void set_bandwidth( + struct core_dc *dc, + struct validate_context *context, + bool decrease_allowed) { - /* Do nothing until we have proper bandwitdth calcs */ + dc->hwss.set_displaymarks(dc, context); } @@ -133,7 +128,6 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc) dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating; dc->hwss.pipe_control_lock = dce_pipe_control_lock; dc->hwss.set_displaymarks = set_displaymarks; - dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed; dc->hwss.set_bandwidth = set_bandwidth; return true; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 758a568589bb..7b780c610631 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -124,11 +124,10 @@ struct hw_sequencer_funcs { const struct core_dc *dc, struct validate_context *context); - void (*increase_watermarks_for_pipe)(struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context); - - void (*set_bandwidth)(struct core_dc *dc); + void (*set_bandwidth)( + struct core_dc *dc, + struct validate_context *context, + bool decrease_allowed); void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, int vmin, int vmax); -- cgit v1.2.3-59-g8ed1b From ce9c088051e198b19eb533b24c605b7cedbe5b9c Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 22 Feb 2017 18:14:52 -0500 Subject: drm/amd/display: move visual confirm recout adjustment to scaler Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 --------- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 6 ++++++ drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c | 6 ++++++ 3 files changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 0ec2c4f39735..852932aec436 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -980,11 +980,6 @@ bool dc_pre_update_surfaces_to_stream( resource_build_scaling_params( new_surfaces[i], &context->res_ctx.pipe_ctx[j]); - - if (dc->debug.surface_visual_confirm) { - context->res_ctx.pipe_ctx[j].scl_data.recout.height -= 2; - context->res_ctx.pipe_ctx[j].scl_data.recout.width -= 2; - } } if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { @@ -1267,10 +1262,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, continue; resource_build_scaling_params(updates[i].surface, pipe_ctx); - if (dc->debug.surface_visual_confirm) { - pipe_ctx->scl_data.recout.height -= 2; - pipe_ctx->scl_data.recout.width -= 2; - } } } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index d8ffbff9a268..c861fd7b5767 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -27,6 +27,7 @@ #include "reg_helper.h" #include "opp.h" #include "basics/conversion.h" +#include "dc.h" #define REG(reg) \ (xfm_dce->regs->reg) @@ -121,6 +122,11 @@ static void program_overscan( int overscan_bottom = data->v_active - data->recout.y - data->recout.height; + if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) { + overscan_bottom += 2; + overscan_right += 2; + } + if (overscan_right < 0) { BREAK_TO_DEBUGGER(); overscan_right = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index feb5f3c29804..28963996693c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -25,6 +25,7 @@ #include "dce110_transform_v.h" #include "dm_services.h" +#include "dc.h" #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" @@ -232,6 +233,11 @@ static void program_overscan( int overscan_right = data->h_active - data->recout.x - data->recout.width; int overscan_bottom = data->v_active - data->recout.y - data->recout.height; + if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) { + overscan_bottom += 2; + overscan_right += 2; + } + if (overscan_right < 0) { BREAK_TO_DEBUGGER(); overscan_right = 0; -- cgit v1.2.3-59-g8ed1b From b2d0a103e6a0a823b46dd2d7f8c2de82c419e286 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 1 Mar 2017 18:27:17 -0500 Subject: drm/amd/display: add init calculation to scaler params Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Dmytro Laktyushkin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 245 ++++++++++++++++++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 11 + drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 +- 5 files changed, 229 insertions(+), 37 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index edcb731a3aea..b9ca9688f8a3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -971,8 +971,7 @@ bool dc_pre_update_surfaces_to_stream( DC_SURFACE_TO_CORE(new_surfaces[i])) continue; - resource_build_scaling_params( - new_surfaces[i], &context->res_ctx.pipe_ctx[j]); + resource_build_scaling_params(&context->res_ctx.pipe_ctx[j]); } if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { @@ -1364,7 +1363,7 @@ void dc_update_surfaces_for_stream(struct dc *dc, if (pipe_ctx->surface != surface) continue; - resource_build_scaling_params(updates[i].surface, pipe_ctx); + resource_build_scaling_params(pipe_ctx); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 326019407cb1..d4b338fa4ab9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -401,15 +401,17 @@ static void rect_swap_helper(struct rect *rect) rect->y = temp; } -static void calculate_viewport( - const struct dc_surface *surface, - struct pipe_ctx *pipe_ctx) +static void calculate_viewport(struct pipe_ctx *pipe_ctx) { + const struct dc_surface *surface = &pipe_ctx->surface->public; + struct scaler_data *data = &pipe_ctx->scl_data; struct rect stream_src = pipe_ctx->stream->public.src; struct rect src = surface->src_rect; struct rect dst = surface->dst_rect; struct rect surface_clip = surface->clip_rect; struct rect clip = {0}; + int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 + || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; if (surface->rotation == ROTATION_ANGLE_90 || @@ -442,27 +444,45 @@ static void calculate_viewport( /* offset = src.ofs + (clip.ofs - dst.ofs) * scl_ratio * num_pixels = clip.num_pix * scl_ratio */ - pipe_ctx->scl_data.viewport.x = src.x + (clip.x - dst.x) * + data->viewport.x = src.x + (clip.x - dst.x) * src.width / dst.width; - pipe_ctx->scl_data.viewport.width = clip.width * + data->viewport.width = clip.width * src.width / dst.width; - pipe_ctx->scl_data.viewport.y = src.y + (clip.y - dst.y) * + data->viewport.y = src.y + (clip.y - dst.y) * src.height / dst.height; - pipe_ctx->scl_data.viewport.height = clip.height * + data->viewport.height = clip.height * src.height / dst.height; - /* Minimum viewport such that 420/422 chroma vp is non 0 */ - if (pipe_ctx->scl_data.viewport.width < 2) - pipe_ctx->scl_data.viewport.width = 2; - if (pipe_ctx->scl_data.viewport.height < 2) - pipe_ctx->scl_data.viewport.height = 2; + /* Round down, compensate in init */ + data->viewport_c.x = data->viewport.x / vpc_div; + data->viewport_c.y = data->viewport.y / vpc_div; + data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? + dal_fixed31_32_half : dal_fixed31_32_zero; + data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? + dal_fixed31_32_half : dal_fixed31_32_zero; + /* Round up, assume original video size always even dimensions */ + data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div; + data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; + + /* Handle hsplit */ + if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { + data->viewport.width /= 2; + data->viewport_c.width /= 2; + data->viewport.x += data->viewport.width; + data->viewport_c.x += data->viewport_c.width; + /* Floor primary pipe, ceil 2ndary pipe */ + data->viewport.width += data->viewport.width % 2; + data->viewport_c.width += data->viewport_c.width % 2; + } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { + data->viewport.width /= 2; + data->viewport_c.width /= 2; + } } -static void calculate_recout( - const struct dc_surface *surface, - struct pipe_ctx *pipe_ctx) +static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { + const struct dc_surface *surface = &pipe_ctx->surface->public; struct core_stream *stream = pipe_ctx->stream; struct rect clip = surface->clip_rect; @@ -493,12 +513,26 @@ static void calculate_recout( pipe_ctx->scl_data.recout.height = stream->public.dst.y + stream->public.dst.height - pipe_ctx->scl_data.recout.y; + + /* Handle hsplit */ + if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { + pipe_ctx->scl_data.recout.width /= 2; + pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width; + /* Floor primary pipe, ceil 2ndary pipe */ + pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2; + } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { + pipe_ctx->scl_data.recout.width /= 2; + } + + recout_skip->width = pipe_ctx->scl_data.recout.x - stream->public.dst.x - + surface->dst_rect.x * stream->public.dst.width / stream->public.src.width; + recout_skip->height = pipe_ctx->scl_data.recout.y - stream->public.dst.y - + surface->dst_rect.y * stream->public.dst.height / stream->public.src.height; } -static void calculate_scaling_ratios( - const struct dc_surface *surface, - struct pipe_ctx *pipe_ctx) +static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { + const struct dc_surface *surface = &pipe_ctx->surface->public; struct core_stream *stream = pipe_ctx->stream; const uint32_t in_w = stream->public.src.width; const uint32_t in_h = stream->public.src.height; @@ -525,31 +559,179 @@ static void calculate_scaling_ratios( pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz; pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert; - if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12) { + if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12 + || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) { pipe_ctx->scl_data.ratios.horz_c.value /= 2; pipe_ctx->scl_data.ratios.vert_c.value /= 2; } } -bool resource_build_scaling_params( - const struct dc_surface *surface, - struct pipe_ctx *pipe_ctx) +static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - bool res; + struct scaler_data *data = &pipe_ctx->scl_data; + struct rect src = pipe_ctx->surface->public.src_rect; + int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 + || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; + + /* + * Init calculated according to formula: + * init = (scaling_ratio + number_of_taps + 1) / 2 + * init_bot = init + scaling_ratio + * init_c = init + truncated_vp_c_offset(from calculate viewport) + */ + data->inits.h = dal_fixed31_32_div_int( + dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2); + + data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int( + dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)); + + data->inits.v = dal_fixed31_32_div_int( + dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2); + + data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int( + dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)); + + + /* Adjust for viewport end clip-off */ + if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) { + int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x; + int int_part = dal_fixed31_32_floor(data->inits.h); + + data->viewport.width += int_part < vp_clip ? int_part : vp_clip; + } + if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) { + int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y; + int int_part = dal_fixed31_32_floor(data->inits.v); + + data->viewport.height += int_part < vp_clip ? int_part : vp_clip; + } + if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) { + int vp_clip = (src.x + src.width) / vpc_div - + data->viewport_c.width - data->viewport_c.x; + int int_part = dal_fixed31_32_floor(data->inits.h_c); + + data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip; + } + if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) { + int vp_clip = (src.y + src.height) / vpc_div - + data->viewport_c.height - data->viewport_c.y; + int int_part = dal_fixed31_32_floor(data->inits.v_c); + + data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip; + } + + /* Adjust for non-0 viewport offset */ + if (data->viewport.x) { + int int_part; + + data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int( + data->ratios.horz, recout_skip->width)); + int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x; + if (int_part < data->taps.h_taps) { + int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ? + (data->taps.h_taps - int_part) : data->viewport.x; + data->viewport.x -= int_adj; + data->viewport.width += int_adj; + int_part += int_adj; + } else if (int_part > data->taps.h_taps) { + data->viewport.x += int_part - data->taps.h_taps; + data->viewport.width -= int_part - data->taps.h_taps; + int_part = data->taps.h_taps; + } + data->inits.h.value &= 0xffffffff; + data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part); + } + + if (data->viewport_c.x) { + int int_part; + + data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int( + data->ratios.horz_c, recout_skip->width)); + int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x; + if (int_part < data->taps.h_taps_c) { + int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ? + (data->taps.h_taps_c - int_part) : data->viewport_c.x; + data->viewport_c.x -= int_adj; + data->viewport_c.width += int_adj; + int_part += int_adj; + } else if (int_part > data->taps.h_taps_c) { + data->viewport_c.x += int_part - data->taps.h_taps_c; + data->viewport_c.width -= int_part - data->taps.h_taps_c; + int_part = data->taps.h_taps_c; + } + data->inits.h_c.value &= 0xffffffff; + data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part); + } + + if (data->viewport.y) { + int int_part; + + data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int( + data->ratios.vert, recout_skip->height)); + int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y; + if (int_part < data->taps.v_taps) { + int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ? + (data->taps.v_taps - int_part) : data->viewport.y; + data->viewport.y -= int_adj; + data->viewport.height += int_adj; + int_part += int_adj; + } else if (int_part > data->taps.v_taps) { + data->viewport.y += int_part - data->taps.v_taps; + data->viewport.height -= int_part - data->taps.v_taps; + int_part = data->taps.v_taps; + } + data->inits.v.value &= 0xffffffff; + data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part); + } + + if (data->viewport_c.y) { + int int_part; + + data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int( + data->ratios.vert_c, recout_skip->height)); + int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y; + if (int_part < data->taps.v_taps_c) { + int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ? + (data->taps.v_taps_c - int_part) : data->viewport_c.y; + data->viewport_c.y -= int_adj; + data->viewport_c.height += int_adj; + int_part += int_adj; + } else if (int_part > data->taps.v_taps_c) { + data->viewport_c.y += int_part - data->taps.v_taps_c; + data->viewport_c.height -= int_part - data->taps.v_taps_c; + int_part = data->taps.v_taps_c; + } + data->inits.v_c.value &= 0xffffffff; + data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part); + } + + /* Interlaced inits based on final vert inits */ + data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); + data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); +} + +bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) +{ + const struct dc_surface *surface = &pipe_ctx->surface->public; struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct view recout_skip = { 0 }; + bool res = false; + /* Important: scaling ratio calculation requires pixel format, * lb depth calculation requires recout and taps require scaling ratios. + * Inits require viewport, taps, ratios and recout of split pipe */ - pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(surface->format); + pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( + pipe_ctx->surface->public.format); + + calculate_scaling_ratios(pipe_ctx); - calculate_viewport(surface, pipe_ctx); + calculate_viewport(pipe_ctx); if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16) return false; - calculate_scaling_ratios(surface, pipe_ctx); - - calculate_recout(surface, pipe_ctx); + calculate_recout(pipe_ctx, &recout_skip); /** * Setting line buffer pixel depth to 24bpp yields banding @@ -572,6 +754,9 @@ bool resource_build_scaling_params( pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); } + if (res) + calculate_inits_and_adj_vp(pipe_ctx, &recout_skip); + dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER, "%s: Viewport:\nheight:%d width:%d x:%d " "y:%d\n dst_rect:\nheight:%d width:%d x:%d " @@ -599,9 +784,7 @@ enum dc_status resource_build_scaling_params_for_context( for (i = 0; i < MAX_PIPES; i++) { if (context->res_ctx.pipe_ctx[i].surface != NULL && context->res_ctx.pipe_ctx[i].stream != NULL) - if (!resource_build_scaling_params( - &context->res_ctx.pipe_ctx[i].surface->public, - &context->res_ctx.pipe_ctx[i])) + if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) return DC_FAIL_SCALING; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d9dcb37a4f65..041830e05b67 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -927,6 +927,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, color->color_b_cb = color_value; break; case PIXEL_FORMAT_420BPP12: + case PIXEL_FORMAT_420BPP15: /* set boarder color to green */ color->color_g_y = color_value; break; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 9c5cb0ee4243..8325a0a47179 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -147,13 +147,24 @@ struct line_buffer_params { enum lb_pixel_depth depth; }; +struct scl_inits { + struct fixed31_32 h; + struct fixed31_32 h_c; + struct fixed31_32 v; + struct fixed31_32 v_bot; + struct fixed31_32 v_c; + struct fixed31_32 v_c_bot; +}; + struct scaler_data { int h_active; int v_active; struct scaling_taps taps; struct rect viewport; + struct rect viewport_c; struct rect recout; struct scaling_ratios ratios; + struct scl_inits inits; struct sharpness_adj sharpness; enum pixel_format format; struct line_buffer_params lb_params; diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index d96c64bb0a70..eb9c96634578 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -82,9 +82,7 @@ enum dc_status resource_map_pool_resources( const struct core_dc *dc, struct validate_context *context); -bool resource_build_scaling_params( - const struct dc_surface *surface, - struct pipe_ctx *pipe_ctx); +bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( const struct core_dc *dc, -- cgit v1.2.3-59-g8ed1b From 2c8ad2d5a20c8b7425b547dd4a969ffecad29b39 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:20:24 -0400 Subject: drm/amd/display: Enable DCE12 support This wires DCE12 support into DC and enables it. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 + drivers/gpu/drm/amd/display/Kconfig | 7 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 ++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 22 ++- drivers/gpu/drm/amd/display/dc/Makefile | 4 + drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 ++ .../amd/display/dc/bios/bios_parser_interface.c | 14 ++ drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 ++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 29 ++++ drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 ++ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++ drivers/gpu/drm/amd/display/dc/dc.h | 27 ++++ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +++++++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 ++ .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 ++ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +++++ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +++++ drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 ++++++++++ .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 ++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 ++++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +++++++- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 + .../display/dc/dce110/dce110_timing_generator.h | 3 + drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 ++ .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 + drivers/gpu/drm/amd/display/dc/dm_services.h | 89 ++++++++++++ drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 ++++ drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 ++ drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 ++ drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +- drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 ++ drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 ++ .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 + .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 + drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 ++ drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 + drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 + drivers/gpu/drm/amd/display/include/dal_types.h | 3 + 44 files changed, 1143 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2efb486e283d..96955c9b4cdf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1984,8 +1984,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_STONEY: case CHIP_POLARIS11: case CHIP_POLARIS10: + case CHIP_POLARIS12: case CHIP_TONGA: case CHIP_FIJI: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case CHIP_VEGA10: +#endif #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) return amdgpu_dc != 0; #else diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 47c8e2940a91..32826a0eafe7 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,6 +17,13 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. +config DRM_AMD_DC_DCE12_0 + bool "Vega10 family" + depends on DRM_AMD_DC + help + Choose this option if you want to have + VG family for display engine. + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a69ce27b8ed6..9157772a0af3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -888,6 +888,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) struct dc_interrupt_params int_params = {0}; int r; int i; + unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; + + if (adev->asic_type == CHIP_VEGA10) + client_id = AMDGPU_IH_CLIENTID_DCE; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; @@ -904,7 +908,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) /* Use VBLANK interrupt */ for (i = 1; i <= adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); if (r) { DRM_ERROR("Failed to add crtc irq id!\n"); @@ -927,7 +931,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) /* Use GRPH_PFLIP interrupt */ for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); + r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); if (r) { DRM_ERROR("Failed to add page flip irq id!\n"); return r; @@ -948,8 +952,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) } /* HPD */ - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, - &adev->hpd_irq); + r = amdgpu_irq_add_id(adev, client_id, + VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); if (r) { DRM_ERROR("Failed to add hpd irq id!\n"); return r; @@ -1119,6 +1123,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_POLARIS11: case CHIP_POLARIS10: case CHIP_POLARIS12: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case CHIP_VEGA10: +#endif if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); return -1; @@ -1312,6 +1319,7 @@ static const struct amdgpu_display_funcs dm_display_funcs = { }; + #if defined(CONFIG_DEBUG_KERNEL_DC) static ssize_t s3_debug_store( @@ -1384,6 +1392,13 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case CHIP_VEGA10: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + break; +#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 1ddc56cfbdc4..df53092abc39 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -402,6 +402,16 @@ bool dm_pp_notify_wm_clock_changes( return false; } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dm_pp_notify_wm_clock_changes_soc15( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) +{ + /* TODO: to be implemented */ + return false; +} +#endif + bool dm_pp_apply_power_level_change_request( const struct dc_context *ctx, struct dm_pp_power_level_change_request *level_change_req) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 098a801ae745..01aaf968854d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -494,7 +494,7 @@ static void fill_plane_attributes_from_fb( memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); - /* Fill GFX8 params */ + /* Fill GFX params */ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { unsigned bankw, bankh, mtaspect, tile_split, num_banks; @@ -523,6 +523,26 @@ static void fill_plane_attributes_from_fb( surface->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) + if (adev->asic_type == CHIP_VEGA10) { + /* Fill GFX9 params */ + surface->tiling_info.gfx9.num_pipes = + adev->gfx.config.gb_addr_config_fields.num_pipes; + surface->tiling_info.gfx9.num_banks = + adev->gfx.config.gb_addr_config_fields.num_banks; + surface->tiling_info.gfx9.pipe_interleave = + adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; + surface->tiling_info.gfx9.num_shader_engines = + adev->gfx.config.gb_addr_config_fields.num_se; + surface->tiling_info.gfx9.max_compressed_frags = + adev->gfx.config.gb_addr_config_fields.max_compress_frags; + surface->tiling_info.gfx9.swizzle = + AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); + surface->tiling_info.gfx9.shaderEnable = 1; + } +#endif + + surface->plane_size.grph.surface_size.x = 0; surface->plane_size.grph.surface_size.y = 0; surface->plane_size.grph.surface_size.width = fb->width; diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 2df163bc83e9..a580cab6bf56 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -4,6 +4,10 @@ DC_LIBS = basics bios calcs dce gpio i2caux irq virtual +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +DC_LIBS += dce120 +endif + DC_LIBS += dce112 DC_LIBS += dce110 DC_LIBS += dce100 diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 876614d37412..770248429a81 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -4,6 +4,10 @@ BIOS = bios_parser.o bios_parser_interface.o bios_parser_helper.o command_table.o command_table_helper.o +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +BIOS += command_table2.o command_table_helper2.o bios_parser2.o +endif + AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) AMD_DISPLAY_FILES += $(AMD_DAL_BIOS) @@ -21,3 +25,7 @@ AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o + +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o +endif diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c index 42272c35df2d..7fe2a791ef42 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c @@ -29,6 +29,10 @@ #include "bios_parser_interface.h" #include "bios_parser.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "bios_parser2.h" +#endif + struct dc_bios *dal_bios_parser_create( struct bp_init_data *init, @@ -36,7 +40,17 @@ struct dc_bios *dal_bios_parser_create( { struct dc_bios *bios = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + bios = firmware_parser_create(init, dce_version); + + if (bios == NULL) + /* TODO: remove dce_version from bios_parser. + * cannot remove today because dal enum to bp enum translation is dce specific + */ + bios = bios_parser_create(init, dce_version); +#else bios = bios_parser_create(init, dce_version); +#endif return bios; } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index ab8d1e931846..aa98762346d2 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -50,6 +50,11 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi return BW_CALCS_VERSION_POLARIS11; return BW_CALCS_VERSION_INVALID; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case FAMILY_AI: + return BW_CALCS_VERSION_VEGA10; +#endif + default: return BW_CALCS_VERSION_INVALID; } @@ -2430,6 +2435,118 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case BW_CALCS_VERSION_VEGA10: + vbios.memory_type = bw_def_hbm; + vbios.dram_channel_width_in_bits = 128; + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; + vbios.number_of_dram_banks = 16; + vbios.high_yclk = bw_int_to_fixed(2400); + vbios.mid_yclk = bw_int_to_fixed(1700); + vbios.low_yclk = bw_int_to_fixed(1000); + vbios.low_sclk = bw_int_to_fixed(300); + vbios.mid1_sclk = bw_int_to_fixed(350); + vbios.mid2_sclk = bw_int_to_fixed(400); + vbios.mid3_sclk = bw_int_to_fixed(500); + vbios.mid4_sclk = bw_int_to_fixed(600); + vbios.mid5_sclk = bw_int_to_fixed(700); + vbios.mid6_sclk = bw_int_to_fixed(760); + vbios.high_sclk = bw_int_to_fixed(776); + vbios.low_voltage_max_dispclk = bw_int_to_fixed(460); + vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670); + vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133); + vbios.low_voltage_max_phyclk = bw_int_to_fixed(540); + vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810); + vbios.high_voltage_max_phyclk = bw_int_to_fixed(810); + vbios.data_return_bus_width = bw_int_to_fixed(32); + vbios.trc = bw_int_to_fixed(48); + vbios.dmifmc_urgent_latency = bw_int_to_fixed(3); + vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10); + vbios.stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10); + vbios.nbp_state_change_latency = bw_int_to_fixed(39); + vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10); + vbios.scatter_gather_enable = false; + vbios.down_spread_percentage = bw_frc_to_fixed(5, 10); + vbios.cursor_width = 32; + vbios.average_compression_rate = 4; + vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8; + vbios.blackout_duration = bw_int_to_fixed(0); /* us */ + vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0); + + dceip.large_cursor = false; + dceip.dmif_request_buffer_size = bw_int_to_fixed(2304); + dceip.dmif_pipe_en_fbc_chunk_tracker = true; + dceip.cursor_max_outstanding_group_num = 1; + dceip.lines_interleaved_into_lb = 2; + dceip.chunk_width = 256; + dceip.number_of_graphics_pipes = 6; + dceip.number_of_underlay_pipes = 0; + dceip.low_power_tiling_mode = 0; + dceip.display_write_back_supported = true; + dceip.argb_compression_support = true; + dceip.underlay_vscaler_efficiency6_bit_per_component = + bw_frc_to_fixed(35556, 10000); + dceip.underlay_vscaler_efficiency8_bit_per_component = + bw_frc_to_fixed(34286, 10000); + dceip.underlay_vscaler_efficiency10_bit_per_component = + bw_frc_to_fixed(32, 10); + dceip.underlay_vscaler_efficiency12_bit_per_component = + bw_int_to_fixed(3); + dceip.graphics_vscaler_efficiency6_bit_per_component = + bw_frc_to_fixed(35, 10); + dceip.graphics_vscaler_efficiency8_bit_per_component = + bw_frc_to_fixed(34286, 10000); + dceip.graphics_vscaler_efficiency10_bit_per_component = + bw_frc_to_fixed(32, 10); + dceip.graphics_vscaler_efficiency12_bit_per_component = + bw_int_to_fixed(3); + dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3); + dceip.max_dmif_buffer_allocated = 4; + dceip.graphics_dmif_size = 24576; + dceip.underlay_luma_dmif_size = 19456; + dceip.underlay_chroma_dmif_size = 23552; + dceip.pre_downscaler_enabled = true; + dceip.underlay_downscale_prefetch_enabled = false; + dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1); + dceip.lb_size_per_component444 = bw_int_to_fixed(245952); + dceip.graphics_lb_nodownscaling_multi_line_prefetching = true; + dceip.stutter_and_dram_clock_state_change_gated_before_cursor = + bw_int_to_fixed(1); + dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed( + 82176); + dceip.underlay420_chroma_lb_size_per_component = + bw_int_to_fixed(164352); + dceip.underlay422_lb_size_per_component = bw_int_to_fixed( + 82176); + dceip.cursor_chunk_width = bw_int_to_fixed(64); + dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4); + dceip.underlay_maximum_width_efficient_for_tiling = + bw_int_to_fixed(1920); + dceip.underlay_maximum_height_efficient_for_tiling = + bw_int_to_fixed(1080); + dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display = + bw_frc_to_fixed(3, 10); + dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation = + bw_int_to_fixed(25); + dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed( + 2); + dceip.maximum_total_outstanding_pte_requests_allowed_by_saw = + bw_int_to_fixed(128); + dceip.limit_excessive_outstanding_dmif_requests = true; + dceip.linear_mode_line_request_alternation_slice = + bw_int_to_fixed(64); + dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode = + 32; + dceip.display_write_back420_luma_mcifwr_buffer_size = 12288; + dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192; + dceip.request_efficiency = bw_frc_to_fixed(8, 10); + dceip.dispclk_per_request = bw_int_to_fixed(2); + dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100); + dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100); + dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; + dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); + break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b9ca9688f8a3..28ed8eaee1ff 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1815,3 +1815,32 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink } } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) +{ + int i; + struct core_dc *core_dc = DC_TO_CORE(dc); + struct mem_input *mi = NULL; + + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + if (core_dc->res_pool->mis[i] != NULL) { + mi = core_dc->res_pool->mis[i]; + break; + } + } + if (mi == NULL) { + dm_error("no mem_input!\n"); + return false; + } + + if (mi->funcs->mem_input_update_dchub) + mi->funcs->mem_input_update_dchub(mi, dh_data); + else + ASSERT(mi->funcs->mem_input_update_dchub); + + + return true; + +} +#endif + diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 85ddf5fc4291..079558ab81c0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -141,6 +141,12 @@ void pre_surface_trace( surface->format, surface->rotation, surface->stereo_format); + +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) + SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", + surface->tiling_info.gfx9.swizzle); +#endif + SURFACE_TRACE("\n"); } SURFACE_TRACE("\n"); @@ -221,6 +227,11 @@ void update_surface_trace( update->plane_info->tiling_info.gfx8.pipe_config, update->plane_info->tiling_info.gfx8.array_mode, update->plane_info->visible); + + #if defined (CONFIG_DRM_AMD_DC_DCE12_0) + SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", + update->plane_info->tiling_info.gfx9.swizzle); + #endif } if (update->scaling_info) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 5ca72afe8f6f..f13da7c227f4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1217,6 +1217,25 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); } else { +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + uint32_t dp_phyclk_in_khz; + const struct clocks_value clocks_value = + pipe_ctx->dis_clk->cur_clocks_value; + + /* 27mhz = 27000000hz= 27000khz */ + dp_phyclk_in_khz = link_settings.link_rate * 27000; + + if (((clocks_value.max_non_dp_phyclk_in_khz != 0) && + (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) || + (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) { + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, + dp_phyclk_in_khz, + false, + true); + } +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 6119973c7f0a..77ef3304d2bc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -39,6 +39,9 @@ #include "dce100/dce100_resource.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/dce120_resource.h" +#endif enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) { @@ -65,6 +68,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) dc_version = DCE_VERSION_11_2; } break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case FAMILY_AI: + dc_version = DCE_VERSION_12_0; + break; +#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -97,6 +105,12 @@ struct resource_pool *dc_create_resource_pool( res_pool = dce112_create_resource_pool( num_virtual_links, dc); break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + res_pool = dce120_create_resource_pool( + num_virtual_links, dc); + break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c6c0cf500ae8..bc15065e489b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,6 +55,9 @@ struct dc_caps { struct dc_dcc_surface_param { enum surface_pixel_format format; struct dc_size surface_size; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + enum swizzle_mode_values swizzle_mode; +#endif enum dc_scan_direction scan; }; @@ -143,6 +146,9 @@ struct dc_debug { bool disable_stutter; bool disable_dcc; bool disable_dfs_bypass; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + bool disable_pplib_clock_request; +#endif bool disable_clock_gate; bool disable_dmcu; bool force_abm_enable; @@ -157,6 +163,23 @@ struct dc { struct dc_debug debug; }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +enum frame_buffer_mode { + FRAME_BUFFER_MODE_LOCAL_ONLY = 0, + FRAME_BUFFER_MODE_ZFB_ONLY, + FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, +} ; + +struct dchub_init_data { + bool dchub_initialzied; + bool dchub_info_valid; + int64_t zfb_phys_addr_base; + int64_t zfb_mc_base_addr; + uint64_t zfb_size_in_byte; + enum frame_buffer_mode fb_mode; +}; +#endif + struct dc_init_data { struct hw_asic_id asic_id; void *driver; /* ctx */ @@ -177,6 +200,10 @@ struct dc *dc_create(const struct dc_init_data *init_params); void dc_destroy(struct dc **dc); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); +#endif + /******************************************************************************* * Surface Interfaces ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 75e16ac70f5f..63813404276d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -259,6 +259,36 @@ enum tile_mode_values { DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, }; +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) +enum swizzle_mode_values { + DC_SW_LINEAR = 0, + DC_SW_256B_S = 1, + DC_SW_256_D = 2, + DC_SW_256_R = 3, + DC_SW_4KB_S = 5, + DC_SW_4KB_D = 6, + DC_SW_4KB_R = 7, + DC_SW_64KB_S = 9, + DC_SW_64KB_D = 10, + DC_SW_64KB_R = 11, + DC_SW_VAR_S = 13, + DC_SW_VAR_D = 14, + DC_SW_VAR_R = 15, + DC_SW_64KB_S_T = 17, + DC_SW_64KB_D_T = 18, + DC_SW_4KB_S_X = 21, + DC_SW_4KB_D_X = 22, + DC_SW_4KB_R_X = 23, + DC_SW_64KB_S_X = 25, + DC_SW_64KB_D_X = 26, + DC_SW_64KB_R_X = 27, + DC_SW_VAR_S_X = 29, + DC_SW_VAR_D_X = 30, + DC_SW_VAR_R_X = 31, + DC_SW_MAX +}; +#endif + union dc_tiling_info { struct { @@ -323,6 +353,22 @@ union dc_tiling_info { enum array_mode_values array_mode; } gfx8; +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) + struct { + unsigned int num_pipes; + unsigned int num_banks; + unsigned int pipe_interleave; + unsigned int num_shader_engines; + unsigned int num_rb_per_se; + unsigned int max_compressed_frags; + bool shaderEnable; + + enum swizzle_mode_values swizzle; + bool meta_linear; + bool rb_aligned; + bool pipe_aligned; + } gfx9; +#endif }; /* Rotation angle */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 1d6a9da45ba6..f53dc157db97 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -585,6 +585,9 @@ static uint32_t dce110_get_pix_clk_dividers( pll_settings, pix_clk_params); break; case DCE_VERSION_11_2: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: +#endif dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -868,6 +871,9 @@ static bool dce110_program_pix_clk( break; case DCE_VERSION_11_2: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: +#endif if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index ac1febafcaa4..9c743e51c091 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -80,6 +80,20 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = { /*ClocksStatePerformance*/ { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +static struct state_dependent_clocks dce120_max_clks_by_state[] = { +/*ClocksStateInvalid - should not be used*/ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/*ClocksStateLow*/ +{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 }, +/*ClocksStateNominal*/ +{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, +/*ClocksStatePerformance*/ +{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; +#endif + /* Starting point for each divider range.*/ enum dce_divider_range_start { DIVIDER_RANGE_01_START = 200, /* 2.00*/ @@ -483,6 +497,103 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) } } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +static bool dce_apply_clock_voltage_request( + struct display_clock *clk, + enum dm_pp_clock_type clocks_type, + int clocks_in_khz, + bool pre_mode_set, + bool update_dp_phyclk) +{ + struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; + + switch (clocks_type) { + case DM_PP_CLOCK_TYPE_DISPLAY_CLK: + case DM_PP_CLOCK_TYPE_PIXELCLK: + case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: + break; + default: + BREAK_TO_DEBUGGER(); + return false; + } + + clock_voltage_req.clk_type = clocks_type; + clock_voltage_req.clocks_in_khz = clocks_in_khz; + + /* to pplib */ + if (pre_mode_set) { + switch (clocks_type) { + case DM_PP_CLOCK_TYPE_DISPLAY_CLK: + if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) { + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + clk->cur_clocks_value.dispclk_notify_pplib_done = true; + } else + clk->cur_clocks_value.dispclk_notify_pplib_done = false; + /* no matter incrase or decrase clock, update current clock value */ + clk->cur_clocks_value.dispclk_in_khz = clocks_in_khz; + break; + case DM_PP_CLOCK_TYPE_PIXELCLK: + if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) { + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + clk->cur_clocks_value.pixelclk_notify_pplib_done = true; + } else + clk->cur_clocks_value.pixelclk_notify_pplib_done = false; + /* no matter incrase or decrase clock, update current clock value */ + clk->cur_clocks_value.max_pixelclk_in_khz = clocks_in_khz; + break; + case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: + if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) { + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + clk->cur_clocks_value.phyclk_notigy_pplib_done = true; + } else + clk->cur_clocks_value.phyclk_notigy_pplib_done = false; + /* no matter incrase or decrase clock, update current clock value */ + clk->cur_clocks_value.max_non_dp_phyclk_in_khz = clocks_in_khz; + break; + default: + ASSERT(0); + break; + } + } else { + switch (clocks_type) { + case DM_PP_CLOCK_TYPE_DISPLAY_CLK: + if (!clk->cur_clocks_value.dispclk_notify_pplib_done) + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + break; + case DM_PP_CLOCK_TYPE_PIXELCLK: + if (!clk->cur_clocks_value.pixelclk_notify_pplib_done) + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + break; + case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: + if (!clk->cur_clocks_value.phyclk_notigy_pplib_done) + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + break; + default: + ASSERT(0); + break; + } + } + + if (update_dp_phyclk && (clocks_in_khz > + clk->cur_clocks_value.max_dp_phyclk_in_khz)) + clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz; + + return true; +} + +static const struct display_clock_funcs dce120_funcs = { + .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, + .apply_clock_voltage_request = dce_apply_clock_voltage_request, + .set_clock = dce112_set_clock +}; +#endif + static const struct display_clock_funcs dce112_funcs = { .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, .get_required_clocks_state = dce_get_required_clocks_state, @@ -623,6 +734,44 @@ struct display_clock *dce112_disp_clk_create( return &clk_dce->base; } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct display_clock *dce120_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask) +{ + struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dm_pp_clock_levels_with_voltage clk_level_info = {0}; + + if (clk_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + memcpy(clk_dce->max_clks_by_state, + dce120_max_clks_by_state, + sizeof(dce120_max_clks_by_state)); + + dce_disp_clk_construct( + clk_dce, ctx, regs, clk_shift, clk_mask); + + clk_dce->base.funcs = &dce120_funcs; + + /* new in dce120 */ + if (!ctx->dc->debug.disable_pplib_clock_request && + dm_pp_get_clock_levels_by_type_with_voltage( + ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clk_level_info) + && clk_level_info.num_levels) + clk_dce->max_displ_clk_in_khz = + clk_level_info.data[clk_level_info.num_levels - 1].clocks_in_khz; + else + clk_dce->max_displ_clk_in_khz = 1133000; + + return &clk_dce->base; +} +#endif + void dce_disp_clk_destroy(struct display_clock **disp_clk) { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h index 020ab9d5434d..18787f6d4e2a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -45,6 +45,14 @@ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ + CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ + CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ + CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ + CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#endif + #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ type DENTIST_DPREFCLK_WDIVIDER; \ @@ -118,6 +126,10 @@ struct dce_disp_clk { int gpu_pll_ss_divider; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + /* max disp_clk from PPLIB for max validation display clock*/ + int max_displ_clk_in_khz; +#endif }; @@ -139,6 +151,14 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct display_clock *dce120_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask); +#endif + void dce_disp_clk_destroy(struct display_clock **disp_clk); #endif /* _DCE_CLOCKS_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 70e0652be071..ff7984b08095 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -186,6 +186,14 @@ struct dce_hwseq_registers { HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ + HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#endif + #define HWSEQ_REG_FIED_LIST(type) \ type DCFE_CLOCK_ENABLE; \ type DCFEV_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index f337d607e36c..f6a1006a6472 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -31,6 +31,13 @@ #define TO_DCE110_LINK_ENC(link_encoder)\ container_of(link_encoder, struct dce110_link_encoder, base) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +/* Not found regs in dce120 spec + * BIOS_SCRATCH_2 + * DP_DPHY_INTERNAL_CTRL + */ +#endif + #define AUX_REG_LIST(id)\ SRI(AUX_CONTROL, DP_AUX, id), \ SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) @@ -79,6 +86,13 @@ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SR(DCI_MEM_PWR_STATUS) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + #define LE_DCE120_REG_LIST(id)\ + LE_COMMON_REG_LIST_BASE(id), \ + SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ + SR(DCI_MEM_PWR_STATUS) +#endif + #define LE_DCE80_REG_LIST(id)\ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ LE_COMMON_REG_LIST_BASE(id) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index e14a21cedfd5..c494f712b5b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -187,6 +187,20 @@ static void program_nbp_watermark(struct mem_input *mi, REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, nbp_wm); } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { + REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, + PSTATE_CHANGE_WATERMARK_MASK, wm_select); + + REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL, + PSTATE_CHANGE_ENABLE, 1, + PSTATE_CHANGE_URGENT_DURING_REQUEST, 1, + PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1); + + REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, + PSTATE_CHANGE_WATERMARK, nbp_wm); + } +#endif } static void program_stutter_watermark(struct mem_input *mi, @@ -196,6 +210,12 @@ static void program_stutter_watermark(struct mem_input *mi, REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (REG(DPG_PIPE_STUTTER_CONTROL2)) + REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, + STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); + else +#endif REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); } @@ -234,6 +254,21 @@ void dce_mem_input_program_display_marks(struct mem_input *mi, static void program_tiling(struct mem_input *mi, const union dc_tiling_info *info) { +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (mi->masks->GRPH_SW_MODE) { /* GFX9 */ + REG_UPDATE_6(GRPH_CONTROL, + GRPH_SW_MODE, info->gfx9.swizzle, + GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), + GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), + GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), + GRPH_COLOR_EXPANSION_MODE, 1, + GRPH_SE_ENABLE, info->gfx9.shaderEnable); + /* TODO: DCP0_GRPH_CONTROL__GRPH_SE_ENABLE where to get info + GRPH_SE_ENABLE, 1, + GRPH_Z, 0); + */ + } +#endif if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index ec053c241901..9e18c2a34e85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -58,6 +58,15 @@ MI_DCE11_2_REG_LIST(id),\ MI_DCE_PTE_REG_LIST(id) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define MI_DCE12_REG_LIST(id)\ + MI_DCE_BASE_REG_LIST(id),\ + MI_DCE_PTE_REG_LIST(id),\ + SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ + SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ + SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id) +#endif + struct dce_mem_input_registers { /* DCP */ uint32_t GRPH_ENABLE; @@ -163,6 +172,31 @@ struct dce_mem_input_registers { MI_DCE11_2_MASK_SH_LIST(mask_sh),\ MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) + +#define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ + SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) + +#define MI_DCE12_MASK_SH_LIST(mask_sh)\ + MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ + MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ + MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_) +#endif + #define MI_REG_FIELD_LIST(type) \ type GRPH_ENABLE; \ type GRPH_X_START; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index a5afc0298d6f..4784ced6fc80 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -107,6 +107,14 @@ enum dce110_opp_reg_type { SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ SRI(CONTROL, FMT_MEMORY, id) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define OPP_DCE_120_REG_LIST(id) \ + OPP_COMMON_REG_LIST_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ + SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ + SRI(CONTROL, FMT_MEMORY, id) +#endif + #define OPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -197,6 +205,70 @@ enum dce110_opp_reg_type { OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ + OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ + OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ + OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ + OPP_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ + OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ + OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ + OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) +#endif + #define OPP_REG_FIELD_LIST(type) \ type DCP_REGAMMA_MEM_PWR_DIS; \ type DCP_LUT_MEM_PWR_DIS; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index 458a37000956..c784c1b961c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -187,6 +187,91 @@ #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ + SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ + SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ + SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ + SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ + SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ + SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ + SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ + SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ + SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) +#endif + +#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) + #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ @@ -209,6 +294,21 @@ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ + SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) +#endif + struct dce_stream_encoder_shift { uint8_t AFMT_GENERIC_INDEX; uint8_t AFMT_GENERIC0_UPDATE; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index b2cf9bfb0094..aa6bc4fc80c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -153,6 +153,74 @@ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ + XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ + XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ + XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ + XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ + XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ + XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ + XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ + XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ + XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ + XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ + XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ + XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ + XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ + XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ + XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) +#endif + #define XFM_REG_FIELD_LIST(type) \ type OUT_CLAMP_MIN_B_CB; \ type OUT_CLAMP_MAX_B_CB; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 041830e05b67..66d5f346f195 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1396,9 +1396,12 @@ static uint32_t get_max_pixel_clock_for_all_paths( return max_pix_clk; } -/* - * Find clock state based on clock requested. if clock value is 0, simply +/* Find clock state based on clock requested. if clock value is 0, simply * set clock state as requested without finding clock state by clock value + *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. + * + * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value + * etc support for dcn1.0 */ static void apply_min_clocks( struct core_dc *dc, @@ -1425,6 +1428,30 @@ static void apply_min_clocks( } /* TODOFPGA */ +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + /* TODO: This is incorrect. Figure out how to fix. */ + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAY_CLK, + pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_PIXELCLK, + pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, + pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, + pre_mode_set, + false); + return; +#endif } /* get the required state based on state dependent clocks: @@ -1441,6 +1468,28 @@ static void apply_min_clocks( pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, *clocks_state); } else { +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAY_CLK, + req_clocks.display_clk_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_PIXELCLK, + req_clocks.pixel_clk_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, + req_clocks.pixel_clk_khz, + pre_mode_set, + false); +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index 1643fb5d4b04..3ffb845f843a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -409,6 +409,9 @@ static struct mem_input_funcs dce110_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + .mem_input_update_dchub = NULL +#endif }; /*****************************************/ /* Constructor, Destructor */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index dcb49fe452c5..55f0a94e7cae 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -108,6 +108,9 @@ struct dce110_timing_generator { uint32_t min_h_front_porch; uint32_t min_h_back_porch; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + /* DCE 12 */ +#endif uint32_t min_h_sync_width; uint32_t min_v_sync_width; uint32_t min_v_blank; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile new file mode 100644 index 000000000000..3c6b3fa98ddc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for the 'controller' sub-component of DAL. +# It provides the control and status of HW CRTC block. + + +DCE120 = dce120_resource.o dce120_timing_generator.o \ +dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \ +dce120_mem_input.o dce120_hw_sequencer.o + +AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c index 704a7ce62080..2f22931f457b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c @@ -54,6 +54,9 @@ static struct mem_input_funcs dce80_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + .mem_input_update_dchub = NULL +#endif }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 73c0f1f83999..bdc7cb045eed 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -192,6 +192,89 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + +/* These macros need to be used with soc15 registers in order to retrieve + * the actual offset. + */ +#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX]) +#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX]) + +#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ + dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) + +#define dm_read_reg_soc15(ctx, reg, inst_offset) \ + dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) + +#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ + generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ + dm_read_reg_func(ctx, mm##reg_name + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + inst_offset, __func__), \ + n, __VA_ARGS__) + +#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ + generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ + n, __VA_ARGS__) + +#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ + get_reg_field_value_ex(\ + (reg_value),\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) + +#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ + (reg_value) = set_reg_field_value_ex(\ + (reg_value),\ + (value),\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) + +/* TODO get rid of this pos*/ +static inline bool wait_reg_func( + const struct dc_context *ctx, + uint32_t addr, + uint32_t mask, + uint8_t shift, + uint32_t condition_value, + unsigned int interval_us, + unsigned int timeout_us) +{ + uint32_t field_value; + uint32_t reg_val; + unsigned int count = 0; + + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) + timeout_us *= 655; /* 6553 give about 30 second before time out */ + + do { + /* try once without sleeping */ + if (count > 0) { + if (interval_us >= 1000) + msleep(interval_us/1000); + else + udelay(interval_us); + } + reg_val = dm_read_reg(ctx, addr); + field_value = get_reg_field_value_ex(reg_val, mask, shift); + count += interval_us; + + } while (field_value != condition_value && count <= timeout_us); + + ASSERT(count <= timeout_us); + + return count <= timeout_us; +} + +#define wait_reg(ctx, inst_offset, reg_name, reg_field, condition_value)\ + wait_reg_func(\ + ctx,\ + mm##reg_name + inst_offset + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX],\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT,\ + condition_value,\ + 20000,\ + 200000) + +#endif /************************************** * Power Play (PP) interfaces **************************************/ @@ -254,6 +337,12 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dm_pp_notify_wm_clock_changes_soc15( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); +#endif + /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 460971dc3a70..8d2661583f21 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -141,6 +141,33 @@ struct dm_pp_wm_sets_with_clock_ranges { struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct dm_pp_clock_range_for_dmif_wm_set_soc15 { + enum dm_pp_wm_set_id wm_set_id; + uint32_t wm_min_dcfclk_clk_in_khz; + uint32_t wm_max_dcfclk_clk_in_khz; + uint32_t wm_min_memg_clk_in_khz; + uint32_t wm_max_mem_clk_in_khz; +}; + +struct dm_pp_clock_range_for_mcif_wm_set_soc15 { + enum dm_pp_wm_set_id wm_set_id; + uint32_t wm_min_socclk_clk_in_khz; + uint32_t wm_max_socclk_clk_in_khz; + uint32_t wm_min_memg_clk_in_khz; + uint32_t wm_max_mem_clk_in_khz; +}; + +struct dm_pp_wm_sets_with_clock_ranges_soc15 { + uint32_t num_wm_dmif_sets; + uint32_t num_wm_mcif_sets; + struct dm_pp_clock_range_for_dmif_wm_set_soc15 + wm_dmif_clocks_ranges[MAX_WM_SETS]; + struct dm_pp_clock_range_for_mcif_wm_set_soc15 + wm_mcif_clocks_ranges[MAX_WM_SETS]; +}; +#endif + #define MAX_DISPLAY_CONFIGS 6 struct dm_pp_display_configuration { diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index a15c257fd2fa..8cf12a8ca28f 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -28,6 +28,17 @@ AMD_DAL_GPIO_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpio/dce110/,$(GPIO_DCE110)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110) +############################################################################### +# DCE 12x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o + +AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) + +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) +endif + ############################################################################### # Diagnostics on FPGA ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index f1a6fa7391c6..66ea3b31b980 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -44,6 +44,10 @@ #include "dce110/hw_factory_dce110.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/hw_factory_dce120.h" +#endif + #include "diagnostics/hw_factory_diag.h" /* @@ -72,6 +76,11 @@ bool dal_hw_factory_init( case DCE_VERSION_11_2: dal_hw_factory_dce110_init(factory); return true; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + dal_hw_factory_dce120_init(factory); + return true; +#endif default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 23e097fa5ace..10e86447f179 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -42,7 +42,9 @@ #include "dce80/hw_translate_dce80.h" #include "dce110/hw_translate_dce110.h" - +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/hw_translate_dce120.h" +#endif #include "diagnostics/hw_translate_diag.h" /* @@ -68,6 +70,11 @@ bool dal_hw_translate_init( case DCE_VERSION_11_2: dal_hw_translate_dce110_init(translate); return true; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + dal_hw_translate_dce120_init(translate); + return true; +#endif default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 83dfc437aae4..99aa5d8fb9a7 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -47,6 +47,17 @@ AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) +############################################################################### +# DCE 120 family +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +I2CAUX_DCE120 = i2caux_dce120.o + +AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120)) + +AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120) +endif + ############################################################################### # Diagnostics on FPGA ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index 5391655af23a..ea3bd75e0555 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -57,6 +57,10 @@ #include "dce112/i2caux_dce112.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/i2caux_dce120.h" +#endif + #include "diagnostics/i2caux_diag.h" /* @@ -80,6 +84,10 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce110_create(ctx); case DCE_VERSION_10_0: return dal_i2caux_dce100_create(ctx); + #if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + return dal_i2caux_dce120_create(ctx); + #endif default: BREAK_TO_DEBUGGER(); return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h index 16f06fa2d69c..a7eaecd32aea 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h @@ -40,6 +40,9 @@ enum bw_calcs_version { BW_CALCS_VERSION_POLARIS10, BW_CALCS_VERSION_POLARIS11, BW_CALCS_VERSION_STONEY, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + BW_CALCS_VERSION_VEGA10 +#endif }; /******************************************************************************* diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index e163f5818dd9..bf77aa6172e1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -28,6 +28,18 @@ #include "dm_services_types.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct clocks_value { + int dispclk_in_khz; + int max_pixelclk_in_khz; + int max_non_dp_phyclk_in_khz; + int max_dp_phyclk_in_khz; + bool dispclk_notify_pplib_done; + bool pixelclk_notify_pplib_done; + bool phyclk_notigy_pplib_done; +}; +#endif + /* Structure containing all state-dependent clocks * (dependent on "enum clocks_state") */ struct state_dependent_clocks { @@ -41,6 +53,9 @@ struct display_clock { enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + struct clocks_value cur_clocks_value; +#endif }; struct display_clock_funcs { @@ -56,6 +71,14 @@ struct display_clock_funcs { int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + bool (*apply_clock_voltage_request)( + struct display_clock *disp_clk, + enum dm_pp_clock_type clocks_type, + int clocks_in_khz, + bool pre_mode_set, + bool update_dp_phyclk); +#endif }; #endif /* __DISPLAY_CLOCK_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index ed980aed1677..6c0600696d02 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -100,6 +100,10 @@ struct mem_input_funcs { bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + void (*mem_input_update_dchub)(struct mem_input *mem_input, + struct dchub_init_data *dh_data); +#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 02710333ce0a..140e49811dd1 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -26,3 +26,15 @@ IRQ_DCE11 = irq_service_dce110.o AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11) + +############################################################################### +# DCE 12x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +IRQ_DCE12 = irq_service_dce120.o + +AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) +endif + diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index fbaa2fc00ddb..a1b6d83b1cbb 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -33,6 +33,9 @@ #include "dce80/irq_service_dce80.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/irq_service_dce120.h" +#endif #include "reg_helper.h" #include "irq_service.h" diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 46f1e88f5e27..15c0b8c14b30 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -123,6 +123,10 @@ #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ #define FAMILY_CZ 135 /* Carrizo */ +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define FAMILY_AI 141 +#endif + #define FAMILY_UNKNOWN 0xFF #endif /* __DAL_ASIC_ID_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index ada5b19e85eb..e24c1ef58d2f 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -38,6 +38,9 @@ enum dce_version { DCE_VERSION_10_0, DCE_VERSION_11_0, DCE_VERSION_11_2, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + DCE_VERSION_12_0, +#endif DCE_VERSION_MAX, }; -- cgit v1.2.3-59-g8ed1b From 8fa9ca2ec6919656db87391a1633692ee8d57c22 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:21:43 -0400 Subject: drm/amd/display: Remove DCE12 guards Signed-off-by: Jordan Lazare Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- drivers/gpu/drm/amd/display/Kconfig | 7 ------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 2 -- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 2 -- drivers/gpu/drm/amd/display/dc/Makefile | 3 --- drivers/gpu/drm/amd/display/dc/bios/Makefile | 4 ---- .../drm/amd/display/dc/bios/bios_parser_interface.c | 10 +--------- .../drm/amd/display/dc/bios/command_table_helper2.c | 2 -- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 4 ---- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 6 +----- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ------ drivers/gpu/drm/amd/display/dc/dc.h | 8 -------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 6 ------ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 6 ------ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 -- drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 18 +++++++----------- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 8 ++------ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 4 ---- .../gpu/drm/amd/display/dc/dce/dce_stream_encoder.h | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 -- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 ----- .../gpu/drm/amd/display/dc/dce110/dce110_mem_input.c | 2 -- .../amd/display/dc/dce110/dce110_timing_generator.h | 2 -- .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 14 +++++--------- drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 2 -- drivers/gpu/drm/amd/display/dc/dm_services.h | 4 ---- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 -- drivers/gpu/drm/amd/display/dc/gpio/Makefile | 2 -- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 ---- drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 4 ---- drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 2 -- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 ---- drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 2 -- drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h | 6 ------ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 -- drivers/gpu/drm/amd/display/dc/irq/Makefile | 2 -- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 2 -- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 -- drivers/gpu/drm/amd/display/include/dal_types.h | 2 -- 45 files changed, 16 insertions(+), 175 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 96955c9b4cdf..df95dd8439b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1987,9 +1987,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_POLARIS12: case CHIP_TONGA: case CHIP_FIJI: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case CHIP_VEGA10: -#endif #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) return amdgpu_dc != 0; #else diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 32826a0eafe7..47c8e2940a91 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,13 +17,6 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. -config DRM_AMD_DC_DCE12_0 - bool "Vega10 family" - depends on DRM_AMD_DC - help - Choose this option if you want to have - VG family for display engine. - config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9157772a0af3..97d949affcfb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1123,9 +1123,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_POLARIS11: case CHIP_POLARIS10: case CHIP_POLARIS12: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case CHIP_VEGA10: -#endif if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); return -1; @@ -1392,13 +1390,11 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case CHIP_VEGA10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; -#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index df53092abc39..a8a53b85905a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -402,7 +402,6 @@ bool dm_pp_notify_wm_clock_changes( return false; } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dm_pp_notify_wm_clock_changes_soc15( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) @@ -410,7 +409,6 @@ bool dm_pp_notify_wm_clock_changes_soc15( /* TODO: to be implemented */ return false; } -#endif bool dm_pp_apply_power_level_change_request( const struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 01aaf968854d..1c1c643439b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -523,7 +523,6 @@ static void fill_plane_attributes_from_fb( surface->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) if (adev->asic_type == CHIP_VEGA10) { /* Fill GFX9 params */ surface->tiling_info.gfx9.num_pipes = @@ -540,7 +539,6 @@ static void fill_plane_attributes_from_fb( AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); surface->tiling_info.gfx9.shaderEnable = 1; } -#endif surface->plane_size.grph.surface_size.x = 0; diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index a580cab6bf56..1a79762425ea 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -4,10 +4,7 @@ DC_LIBS = basics bios calcs dce gpio i2caux irq virtual -ifdef CONFIG_DRM_AMD_DC_DCE12_0 DC_LIBS += dce120 -endif - DC_LIBS += dce112 DC_LIBS += dce110 DC_LIBS += dce100 diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 770248429a81..a26cc605462d 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -4,9 +4,7 @@ BIOS = bios_parser.o bios_parser_interface.o bios_parser_helper.o command_table.o command_table_helper.o -ifdef CONFIG_DRM_AMD_DC_DCE12_0 BIOS += command_table2.o command_table_helper2.o bios_parser2.o -endif AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) @@ -26,6 +24,4 @@ AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o -ifdef CONFIG_DRM_AMD_DC_DCE12_0 AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o -endif diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c index 7fe2a791ef42..0079a1e26efd 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c @@ -29,9 +29,7 @@ #include "bios_parser_interface.h" #include "bios_parser.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "bios_parser2.h" -#endif struct dc_bios *dal_bios_parser_create( @@ -40,17 +38,11 @@ struct dc_bios *dal_bios_parser_create( { struct dc_bios *bios = NULL; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bios = firmware_parser_create(init, dce_version); + /* Fall back to old bios parser for older asics */ if (bios == NULL) - /* TODO: remove dce_version from bios_parser. - * cannot remove today because dal enum to bp enum translation is dce specific - */ bios = bios_parser_create(init, dce_version); -#else - bios = bios_parser_create(init, dce_version); -#endif return bios; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index b0dcad260be6..1cc3df1d5698 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -53,11 +53,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCE_VERSION_11_2: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; -#endif default: /* Unsupported DCE */ diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index aa98762346d2..c855e49eb116 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -50,10 +50,8 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi return BW_CALCS_VERSION_POLARIS11; return BW_CALCS_VERSION_INVALID; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case FAMILY_AI: return BW_CALCS_VERSION_VEGA10; -#endif default: return BW_CALCS_VERSION_INVALID; @@ -2435,7 +2433,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case BW_CALCS_VERSION_VEGA10: vbios.memory_type = bw_def_hbm; vbios.dram_channel_width_in_bits = 128; @@ -2546,7 +2543,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); break; -#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 28ed8eaee1ff..d6041e842347 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1815,7 +1815,6 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink } } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) { int i; @@ -1842,5 +1841,4 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) return true; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 079558ab81c0..fb48b8909e7f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -142,10 +142,8 @@ void pre_surface_trace( surface->rotation, surface->stereo_format); -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", surface->tiling_info.gfx9.swizzle); -#endif SURFACE_TRACE("\n"); } @@ -228,10 +226,8 @@ void update_surface_trace( update->plane_info->tiling_info.gfx8.array_mode, update->plane_info->visible); - #if defined (CONFIG_DRM_AMD_DC_DCE12_0) - SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", + SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", update->plane_info->tiling_info.gfx9.swizzle); - #endif } if (update->scaling_info) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index f13da7c227f4..74dd272d7452 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1217,7 +1217,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); } else { -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) uint32_t dp_phyclk_in_khz; const struct clocks_value clocks_value = pipe_ctx->dis_clk->cur_clocks_value; @@ -1235,7 +1234,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) false, true); } -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 77ef3304d2bc..ad37d0efca2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -39,9 +39,7 @@ #include "dce100/dce100_resource.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/dce120_resource.h" -#endif enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) { @@ -68,11 +66,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) dc_version = DCE_VERSION_11_2; } break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case FAMILY_AI: dc_version = DCE_VERSION_12_0; break; -#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -105,12 +101,10 @@ struct resource_pool *dc_create_resource_pool( res_pool = dce112_create_resource_pool( num_virtual_links, dc); break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: res_pool = dce120_create_resource_pool( num_virtual_links, dc); break; -#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index bc15065e489b..106addc937ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,9 +55,7 @@ struct dc_caps { struct dc_dcc_surface_param { enum surface_pixel_format format; struct dc_size surface_size; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) enum swizzle_mode_values swizzle_mode; -#endif enum dc_scan_direction scan; }; @@ -146,9 +144,7 @@ struct dc_debug { bool disable_stutter; bool disable_dcc; bool disable_dfs_bypass; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool disable_pplib_clock_request; -#endif bool disable_clock_gate; bool disable_dmcu; bool force_abm_enable; @@ -163,7 +159,6 @@ struct dc { struct dc_debug debug; }; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) enum frame_buffer_mode { FRAME_BUFFER_MODE_LOCAL_ONLY = 0, FRAME_BUFFER_MODE_ZFB_ONLY, @@ -178,7 +173,6 @@ struct dchub_init_data { uint64_t zfb_size_in_byte; enum frame_buffer_mode fb_mode; }; -#endif struct dc_init_data { struct hw_asic_id asic_id; @@ -200,9 +194,7 @@ struct dc *dc_create(const struct dc_init_data *init_params); void dc_destroy(struct dc **dc); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); -#endif /******************************************************************************* * Surface Interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 63813404276d..33e3377f69fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -259,7 +259,6 @@ enum tile_mode_values { DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, }; -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) enum swizzle_mode_values { DC_SW_LINEAR = 0, DC_SW_256B_S = 1, @@ -287,7 +286,6 @@ enum swizzle_mode_values { DC_SW_VAR_R_X = 31, DC_SW_MAX }; -#endif union dc_tiling_info { @@ -353,7 +351,6 @@ union dc_tiling_info { enum array_mode_values array_mode; } gfx8; -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) struct { unsigned int num_pipes; unsigned int num_banks; @@ -368,7 +365,6 @@ union dc_tiling_info { bool rb_aligned; bool pipe_aligned; } gfx9; -#endif }; /* Rotation angle */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index f53dc157db97..bd4524ef3a37 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -585,9 +585,7 @@ static uint32_t dce110_get_pix_clk_dividers( pll_settings, pix_clk_params); break; case DCE_VERSION_11_2: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: -#endif dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -871,9 +869,7 @@ static bool dce110_program_pix_clk( break; case DCE_VERSION_11_2: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: -#endif if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 9c743e51c091..263f8900e39c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -80,7 +80,6 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = { /*ClocksStatePerformance*/ { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) static struct state_dependent_clocks dce120_max_clks_by_state[] = { /*ClocksStateInvalid - should not be used*/ { .display_clk_khz = 0, .pixel_clk_khz = 0 }, @@ -92,7 +91,6 @@ static struct state_dependent_clocks dce120_max_clks_by_state[] = { { .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, /*ClocksStatePerformance*/ { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; -#endif /* Starting point for each divider range.*/ enum dce_divider_range_start { @@ -497,7 +495,6 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) } } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) static bool dce_apply_clock_voltage_request( struct display_clock *clk, enum dm_pp_clock_type clocks_type, @@ -592,7 +589,6 @@ static const struct display_clock_funcs dce120_funcs = { .apply_clock_voltage_request = dce_apply_clock_voltage_request, .set_clock = dce112_set_clock }; -#endif static const struct display_clock_funcs dce112_funcs = { .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, @@ -734,7 +730,6 @@ struct display_clock *dce112_disp_clk_create( return &clk_dce->base; } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct display_clock *dce120_disp_clk_create( struct dc_context *ctx, const struct dce_disp_clk_registers *regs, @@ -770,7 +765,6 @@ struct display_clock *dce120_disp_clk_create( return &clk_dce->base; } -#endif void dce_disp_clk_destroy(struct display_clock **disp_clk) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h index 18787f6d4e2a..2fd00e45395c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -45,13 +45,11 @@ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) -#endif #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ @@ -126,10 +124,8 @@ struct dce_disp_clk { int gpu_pll_ss_divider; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* max disp_clk from PPLIB for max validation display clock*/ int max_displ_clk_in_khz; -#endif }; @@ -151,13 +147,11 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct display_clock *dce120_disp_clk_create( struct dc_context *ctx, const struct dce_disp_clk_registers *regs, const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask); -#endif void dce_disp_clk_destroy(struct display_clock **disp_clk); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index ff7984b08095..c66585188ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -186,13 +186,11 @@ struct dce_hwseq_registers { HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) -#endif #define HWSEQ_REG_FIED_LIST(type) \ type DCFE_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index f6a1006a6472..25ba583dbb8f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -31,12 +31,10 @@ #define TO_DCE110_LINK_ENC(link_encoder)\ container_of(link_encoder, struct dce110_link_encoder, base) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* Not found regs in dce120 spec * BIOS_SCRATCH_2 * DP_DPHY_INTERNAL_CTRL */ -#endif #define AUX_REG_LIST(id)\ SRI(AUX_CONTROL, DP_AUX, id), \ @@ -86,16 +84,14 @@ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SR(DCI_MEM_PWR_STATUS) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) - #define LE_DCE120_REG_LIST(id)\ - LE_COMMON_REG_LIST_BASE(id), \ - SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ - SR(DCI_MEM_PWR_STATUS) -#endif +#define LE_DCE120_REG_LIST(id)\ + LE_COMMON_REG_LIST_BASE(id), \ + SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ + SR(DCI_MEM_PWR_STATUS) - #define LE_DCE80_REG_LIST(id)\ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id) +#define LE_DCE80_REG_LIST(id)\ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + LE_COMMON_REG_LIST_BASE(id) struct dce110_link_enc_aux_registers { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index c494f712b5b5..7acd87152811 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -187,7 +187,7 @@ static void program_nbp_watermark(struct mem_input *mi, REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, nbp_wm); } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, wm_select); @@ -200,7 +200,6 @@ static void program_nbp_watermark(struct mem_input *mi, REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, nbp_wm); } -#endif } static void program_stutter_watermark(struct mem_input *mi, @@ -210,12 +209,10 @@ static void program_stutter_watermark(struct mem_input *mi, REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) if (REG(DPG_PIPE_STUTTER_CONTROL2)) REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); else -#endif REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); } @@ -254,7 +251,6 @@ void dce_mem_input_program_display_marks(struct mem_input *mi, static void program_tiling(struct mem_input *mi, const union dc_tiling_info *info) { -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) if (mi->masks->GRPH_SW_MODE) { /* GFX9 */ REG_UPDATE_6(GRPH_CONTROL, GRPH_SW_MODE, info->gfx9.swizzle, @@ -268,7 +264,7 @@ static void program_tiling(struct mem_input *mi, GRPH_Z, 0); */ } -#endif + if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index 9e18c2a34e85..6af533bdf98c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -58,14 +58,12 @@ MI_DCE11_2_REG_LIST(id),\ MI_DCE_PTE_REG_LIST(id) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define MI_DCE12_REG_LIST(id)\ MI_DCE_BASE_REG_LIST(id),\ MI_DCE_PTE_REG_LIST(id),\ SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id) -#endif struct dce_mem_input_registers { /* DCP */ @@ -172,7 +170,6 @@ struct dce_mem_input_registers { MI_DCE11_2_MASK_SH_LIST(mask_sh),\ MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ @@ -195,7 +192,6 @@ struct dce_mem_input_registers { MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_) -#endif #define MI_REG_FIELD_LIST(type) \ type GRPH_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index 4784ced6fc80..03ce9ba50b64 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -107,13 +107,11 @@ enum dce110_opp_reg_type { SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ SRI(CONTROL, FMT_MEMORY, id) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define OPP_DCE_120_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(CONTROL, FMT_MEMORY, id) -#endif #define OPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -205,7 +203,6 @@ enum dce110_opp_reg_type { OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ @@ -267,7 +264,6 @@ enum dce110_opp_reg_type { OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) -#endif #define OPP_REG_FIELD_LIST(type) \ type DCP_REGAMMA_MEM_PWR_DIS; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index c784c1b961c6..c2f4050fc6dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -187,7 +187,6 @@ #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ @@ -267,7 +266,6 @@ SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) -#endif #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) @@ -294,7 +292,6 @@ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ @@ -307,7 +304,6 @@ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) -#endif struct dce_stream_encoder_shift { uint8_t AFMT_GENERIC_INDEX; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index aa6bc4fc80c5..da2a02434665 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -153,7 +153,6 @@ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ @@ -219,7 +218,6 @@ XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) -#endif #define XFM_REG_FIELD_LIST(type) \ type OUT_CLAMP_MIN_B_CB; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 66d5f346f195..cb7a673e15e9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1427,8 +1427,6 @@ static void apply_min_clocks( return; } - /* TODOFPGA */ -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* TODO: This is incorrect. Figure out how to fix. */ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( pipe_ctx->dis_clk, @@ -1451,7 +1449,6 @@ static void apply_min_clocks( pre_mode_set, false); return; -#endif } /* get the required state based on state dependent clocks: @@ -1468,7 +1465,6 @@ static void apply_min_clocks( pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, *clocks_state); } else { -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( pipe_ctx->dis_clk, DM_PP_CLOCK_TYPE_DISPLAY_CLK, @@ -1489,7 +1485,6 @@ static void apply_min_clocks( req_clocks.pixel_clk_khz, pre_mode_set, false); -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index 3ffb845f843a..a20feaedfca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -409,9 +409,7 @@ static struct mem_input_funcs dce110_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) .mem_input_update_dchub = NULL -#endif }; /*****************************************/ /* Constructor, Destructor */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 55f0a94e7cae..378509b8e56c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -108,9 +108,7 @@ struct dce110_timing_generator { uint32_t min_h_front_porch; uint32_t min_h_back_porch; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* DCE 12 */ -#endif uint32_t min_h_sync_width; uint32_t min_v_sync_width; uint32_t min_v_blank; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 9a1984b36592..efa58889058b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -909,6 +909,7 @@ static bool construct( { unsigned int i; struct dc_context *ctx = dc->ctx; + struct irq_service_init_data irq_init_data; ctx->dc_bios->regs = &bios_regs; @@ -997,15 +998,10 @@ static bool construct( goto res_create_fail; } - { - #if defined(CONFIG_DRM_AMD_DC_DCE12_0) - struct irq_service_init_data init_data; - init_data.ctx = dc->ctx; - pool->base.irqs = dal_irq_service_dce120_create(&init_data); - if (!pool->base.irqs) - goto irqs_create_fail; - #endif - } + irq_init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); + if (!pool->base.irqs) + goto irqs_create_fail; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c index 2f22931f457b..ebb8df3cdf4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c @@ -54,9 +54,7 @@ static struct mem_input_funcs dce80_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) .mem_input_update_dchub = NULL -#endif }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index bdc7cb045eed..cf6ecfcadd5e 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -192,7 +192,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* These macros need to be used with soc15 registers in order to retrieve * the actual offset. @@ -274,7 +273,6 @@ static inline bool wait_reg_func( 20000,\ 200000) -#endif /************************************** * Power Play (PP) interfaces **************************************/ @@ -337,11 +335,9 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dm_pp_notify_wm_clock_changes_soc15( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); -#endif /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 8d2661583f21..c631dec489e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -141,7 +141,6 @@ struct dm_pp_wm_sets_with_clock_ranges { struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; }; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct dm_pp_clock_range_for_dmif_wm_set_soc15 { enum dm_pp_wm_set_id wm_set_id; uint32_t wm_min_dcfclk_clk_in_khz; @@ -166,7 +165,6 @@ struct dm_pp_wm_sets_with_clock_ranges_soc15 { struct dm_pp_clock_range_for_mcif_wm_set_soc15 wm_mcif_clocks_ranges[MAX_WM_SETS]; }; -#endif #define MAX_DISPLAY_CONFIGS 6 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 8cf12a8ca28f..5e831aff4830 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -31,13 +31,11 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110) ############################################################################### # DCE 12x ############################################################################### -ifdef CONFIG_DRM_AMD_DC_DCE12_0 GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) -endif ############################################################################### # Diagnostics on FPGA diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 66ea3b31b980..29ba83d2c211 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -44,9 +44,7 @@ #include "dce110/hw_factory_dce110.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/hw_factory_dce120.h" -#endif #include "diagnostics/hw_factory_diag.h" @@ -76,11 +74,9 @@ bool dal_hw_factory_init( case DCE_VERSION_11_2: dal_hw_factory_dce110_init(factory); return true; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: dal_hw_factory_dce120_init(factory); return true; -#endif default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 10e86447f179..872edda54536 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -42,9 +42,7 @@ #include "dce80/hw_translate_dce80.h" #include "dce110/hw_translate_dce110.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/hw_translate_dce120.h" -#endif #include "diagnostics/hw_translate_diag.h" /* @@ -70,11 +68,9 @@ bool dal_hw_translate_init( case DCE_VERSION_11_2: dal_hw_translate_dce110_init(translate); return true; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: dal_hw_translate_dce120_init(translate); return true; -#endif default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 99aa5d8fb9a7..a636768d06d5 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -50,13 +50,11 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) ############################################################################### # DCE 120 family ############################################################################### -ifdef CONFIG_DRM_AMD_DC_DCE12_0 I2CAUX_DCE120 = i2caux_dce120.o AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120)) AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120) -endif ############################################################################### # Diagnostics on FPGA diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index ea3bd75e0555..bd84b932aaae 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -57,9 +57,7 @@ #include "dce112/i2caux_dce112.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/i2caux_dce120.h" -#endif #include "diagnostics/i2caux_diag.h" @@ -84,10 +82,8 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce110_create(ctx); case DCE_VERSION_10_0: return dal_i2caux_dce100_create(ctx); - #if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: return dal_i2caux_dce120_create(ctx); - #endif default: BREAK_TO_DEBUGGER(); return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h index a7eaecd32aea..81fab9ef3637 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h @@ -40,9 +40,7 @@ enum bw_calcs_version { BW_CALCS_VERSION_POLARIS10, BW_CALCS_VERSION_POLARIS11, BW_CALCS_VERSION_STONEY, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) BW_CALCS_VERSION_VEGA10 -#endif }; /******************************************************************************* diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index bf77aa6172e1..79aa75c150ec 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -28,7 +28,6 @@ #include "dm_services_types.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct clocks_value { int dispclk_in_khz; int max_pixelclk_in_khz; @@ -38,7 +37,6 @@ struct clocks_value { bool pixelclk_notify_pplib_done; bool phyclk_notigy_pplib_done; }; -#endif /* Structure containing all state-dependent clocks * (dependent on "enum clocks_state") */ @@ -53,9 +51,7 @@ struct display_clock { enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct clocks_value cur_clocks_value; -#endif }; struct display_clock_funcs { @@ -71,14 +67,12 @@ struct display_clock_funcs { int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool (*apply_clock_voltage_request)( struct display_clock *disp_clk, enum dm_pp_clock_type clocks_type, int clocks_in_khz, bool pre_mode_set, bool update_dp_phyclk); -#endif }; #endif /* __DISPLAY_CLOCK_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 6c0600696d02..7ec4027700d8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -100,10 +100,8 @@ struct mem_input_funcs { bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) void (*mem_input_update_dchub)(struct mem_input *mem_input, struct dchub_init_data *dh_data); -#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 140e49811dd1..222f36e3074f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -30,11 +30,9 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11) ############################################################################### # DCE 12x ############################################################################### -ifdef CONFIG_DRM_AMD_DC_DCE12_0 IRQ_DCE12 = irq_service_dce120.o AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) -endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index a1b6d83b1cbb..5255c14254df 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -33,9 +33,7 @@ #include "dce80/irq_service_dce80.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/irq_service_dce120.h" -#endif #include "reg_helper.h" #include "irq_service.h" diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 15c0b8c14b30..6dab058f8f3c 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -123,9 +123,7 @@ #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ #define FAMILY_CZ 135 /* Carrizo */ -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define FAMILY_AI 141 -#endif #define FAMILY_UNKNOWN 0xFF diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index e24c1ef58d2f..0cefde14aa02 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -38,9 +38,7 @@ enum dce_version { DCE_VERSION_10_0, DCE_VERSION_11_0, DCE_VERSION_11_2, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) DCE_VERSION_12_0, -#endif DCE_VERSION_MAX, }; -- cgit v1.2.3-59-g8ed1b From 745cc746da42a3a8a48fb7a6b8c4ee2c3f2cdf8b Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 14 Mar 2017 12:30:29 -0400 Subject: drm/amd/display: remove dc_pre_update_surfaces_to_stream from dc use Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Dmytro Laktyushkin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 115 ++------------------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 45 -------- .../drm/amd/display/dc/dce110/dce110_resource.c | 48 +++++++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 - 6 files changed, 54 insertions(+), 169 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 26f227ddd025..6409d4d1d7f8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -900,106 +900,7 @@ bool dc_pre_update_surfaces_to_stream( uint8_t new_surface_count, const struct dc_stream *dc_stream) { - int i, j; - struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream_status *stream_status = NULL; - struct validate_context *context; - bool ret = true; - - pre_surface_trace(dc, new_surfaces, new_surface_count); - - if (core_dc->current_context->stream_count == 0) - return false; - - /* Cannot commit surface to a stream that is not commited */ - for (i = 0; i < core_dc->current_context->stream_count; i++) - if (dc_stream == &core_dc->current_context->streams[i]->public) - break; - - if (i == core_dc->current_context->stream_count) - return false; - - stream_status = &core_dc->current_context->stream_status[i]; - - if (new_surface_count == stream_status->surface_count) { - bool skip_pre = true; - - for (i = 0; i < stream_status->surface_count; i++) { - struct dc_surface temp_surf = { 0 }; - - temp_surf = *stream_status->surfaces[i]; - temp_surf.clip_rect = new_surfaces[i]->clip_rect; - temp_surf.dst_rect.x = new_surfaces[i]->dst_rect.x; - temp_surf.dst_rect.y = new_surfaces[i]->dst_rect.y; - - if (memcmp(&temp_surf, new_surfaces[i], sizeof(temp_surf)) != 0) { - skip_pre = false; - break; - } - } - - if (skip_pre) - return true; - } - - context = dm_alloc(sizeof(struct validate_context)); - - if (!context) { - dm_error("%s: failed to create validate ctx\n", __func__); - ret = false; - goto val_ctx_fail; - } - - resource_validate_ctx_copy_construct(core_dc->current_context, context); - - dm_logger_write(core_dc->ctx->logger, LOG_DC, - "%s: commit %d surfaces to stream 0x%x\n", - __func__, - new_surface_count, - dc_stream); - - if (!resource_attach_surfaces_to_context( - new_surfaces, new_surface_count, dc_stream, context)) { - BREAK_TO_DEBUGGER(); - ret = false; - goto unexpected_fail; - } - - for (i = 0; i < new_surface_count; i++) - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { - if (context->res_ctx.pipe_ctx[j].surface != - DC_SURFACE_TO_CORE(new_surfaces[i])) - continue; - - resource_build_scaling_params(&context->res_ctx.pipe_ctx[j]); - } - - if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { - BREAK_TO_DEBUGGER(); - ret = false; - goto unexpected_fail; - } - - core_dc->hwss.set_bandwidth(core_dc, context, false); - - for (i = 0; i < new_surface_count; i++) - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { - if (context->res_ctx.pipe_ctx[j].surface != - DC_SURFACE_TO_CORE(new_surfaces[i])) - continue; - - core_dc->hwss.prepare_pipe_for_context( - core_dc, - &context->res_ctx.pipe_ctx[j], - context); - } - -unexpected_fail: - resource_validate_ctx_destruct(context); - dm_free(context); -val_ctx_fail: - - return ret; + return true; } bool dc_post_update_surfaces_to_stream(struct dc *dc) @@ -1050,10 +951,6 @@ bool dc_commit_surfaces_to_stream( struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; - if (!dc_pre_update_surfaces_to_stream( - dc, new_surfaces, new_surface_count, dc_stream)) - return false; - memset(updates, 0, sizeof(updates)); memset(flip_addr, 0, sizeof(flip_addr)); memset(plane_info, 0, sizeof(plane_info)); @@ -1423,10 +1320,12 @@ void dc_update_surfaces_and_stream(struct dc *dc, *(srf_updates[i].hdr_static_metadata); } - if (update_type == UPDATE_TYPE_FULL && - !core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { - BREAK_TO_DEBUGGER(); - return; + if (update_type == UPDATE_TYPE_FULL) { + if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { + BREAK_TO_DEBUGGER(); + return; + } else + core_dc->hwss.set_bandwidth(core_dc, context, false); } if (!surface_count) /* reset */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ad37d0efca2e..6700d6b27a8a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -900,10 +900,11 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( * that has no surface attached yet */ static struct pipe_ctx *acquire_free_pipe_for_stream( - struct resource_context *res_ctx, + struct validate_context *context, const struct dc_stream *dc_stream) { int i; + struct resource_context *res_ctx = &context->res_ctx; struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -934,7 +935,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( if(!res_ctx->pool->funcs->acquire_idle_pipe_for_layer) return NULL; - return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(res_ctx, stream); + return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(context, stream); } @@ -1001,8 +1002,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); - struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - &context->res_ctx, dc_stream); + struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(context, dc_stream); if (!free_pipe) { stream_status->surfaces[i] = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index cb7a673e15e9..e5e52c705954 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2094,50 +2094,6 @@ static void init_hw(struct core_dc *dc) } } -static void dce110_power_on_pipe_if_needed( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - struct dc_bios *dcb = dc->ctx->dc_bios; - struct tg_color black_color = {0}; - - if (!old_pipe_ctx->stream && pipe_ctx->stream) { - dc->hwss.enable_display_power_gating( - dc, - pipe_ctx->pipe_idx, - dcb, PIPE_GATING_CONTROL_DISABLE); - - /* - * This is for powering on underlay, so crtc does not - * need to be enabled - */ - - pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, - &pipe_ctx->stream->public.timing, - false); - - pipe_ctx->tg->funcs->enable_advanced_request( - pipe_ctx->tg, - true, - &pipe_ctx->stream->public.timing); - - pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, - pipe_ctx->stream->public.timing.h_total, - pipe_ctx->stream->public.timing.v_total, - pipe_ctx->stream->public.timing.pix_clk_khz, - context->stream_count); - - /* TODO unhardcode*/ - color_space_to_black_color(dc, - COLOR_SPACE_YCBCR601, &black_color); - pipe_ctx->tg->funcs->set_blank_color( - pipe_ctx->tg, - &black_color); - } -} - static void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg) @@ -2481,7 +2437,6 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) static const struct hw_sequencer_funcs dce110_funcs = { .init_hw = init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, - .prepare_pipe_for_context = dce110_power_on_pipe_if_needed, .apply_ctx_for_surface = dce110_apply_ctx_for_surface, .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index b9d0b5eeca13..e3002031c40d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1111,16 +1111,17 @@ enum dc_status dce110_validate_guaranteed( return result; } -static struct pipe_ctx *dce110_acquire_idle_pipe_for_layer( - struct resource_context *res_ctx, +static struct pipe_ctx *dce110_acquire_underlay( + struct validate_context *context, struct core_stream *stream) { + struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct resource_context *res_ctx = &context->res_ctx; unsigned int underlay_idx = res_ctx->pool->underlay_pipe_index; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; - if (res_ctx->pipe_ctx[underlay_idx].stream) { + if (res_ctx->pipe_ctx[underlay_idx].stream) return NULL; - } pipe_ctx->tg = res_ctx->pool->timing_generators[underlay_idx]; pipe_ctx->mi = res_ctx->pool->mis[underlay_idx]; @@ -1132,8 +1133,43 @@ static struct pipe_ctx *dce110_acquire_idle_pipe_for_layer( pipe_ctx->stream = stream; - return pipe_ctx; + if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) { + struct tg_color black_color = {0}; + struct dc_bios *dcb = dc->ctx->dc_bios; + + dc->hwss.enable_display_power_gating( + dc, + pipe_ctx->pipe_idx, + dcb, PIPE_GATING_CONTROL_DISABLE); + + /* + * This is for powering on underlay, so crtc does not + * need to be enabled + */ + + pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, + &stream->public.timing, + false); + + pipe_ctx->tg->funcs->enable_advanced_request( + pipe_ctx->tg, + true, + &stream->public.timing); + + pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, + stream->public.timing.h_total, + stream->public.timing.v_total, + stream->public.timing.pix_clk_khz, + context->stream_count); + + color_space_to_black_color(dc, + COLOR_SPACE_YCBCR601, &black_color); + pipe_ctx->tg->funcs->set_blank_color( + pipe_ctx->tg, + &black_color); + } + return pipe_ctx; } static void dce110_destroy_resource_pool(struct resource_pool **pool) @@ -1152,7 +1188,7 @@ static const struct resource_funcs dce110_res_pool_funcs = { .validate_with_context = dce110_validate_with_context, .validate_guaranteed = dce110_validate_guaranteed, .validate_bandwidth = dce110_validate_bandwidth, - .acquire_idle_pipe_for_layer = dce110_acquire_idle_pipe_for_layer, + .acquire_idle_pipe_for_layer = dce110_acquire_underlay, .build_bit_depth_reduction_params = dce110_resource_build_bit_depth_reduction_params }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index faec2292cc27..7f3c6da1ebd7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -210,7 +210,7 @@ struct resource_funcs { struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( - struct resource_context *res_ctx, + struct validate_context *context, struct core_stream *stream); void (*build_bit_depth_reduction_params)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 98a04cd46178..bcb267295cb9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -57,11 +57,6 @@ struct hw_sequencer_funcs { void (*reset_hw_ctx_wrap)( struct core_dc *dc, struct validate_context *context); - void (*prepare_pipe_for_context)( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context); - void (*apply_ctx_for_surface)( struct core_dc *dc, struct core_surface *surface, -- cgit v1.2.3-59-g8ed1b From 18f7a1e4083a5be0ce02df736d3f9a82246dd89b Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 23 Mar 2017 10:34:06 -0400 Subject: drm/amd/display: Power on front end during set mode. Signed-off-by: Yongqiang Sun Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 +++++ 2 files changed, 8 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e5e52c705954..2a3a39e31717 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1722,6 +1722,9 @@ enum dc_status dce110_apply_ctx_to_hw( context, dc); + if (dc->hwss.power_on_front_end) + dc->hwss.power_on_front_end(dc, pipe_ctx, context); + if (DC_OK != status) return status; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index bcb267295cb9..077dc7573c52 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -104,6 +104,11 @@ struct hw_sequencer_funcs { enum pipe_gating_control power_gating); void (*power_down_front_end)(struct core_dc *dc, struct pipe_ctx *pipe); + + void (*power_on_front_end)(struct core_dc *dc, + struct pipe_ctx *pipe, + struct validate_context *context); + void (*update_info_frame)(struct pipe_ctx *pipe_ctx); void (*enable_stream)(struct pipe_ctx *pipe_ctx); -- cgit v1.2.3-59-g8ed1b From 5e141de45218d36a6b98c783834684fd0d617f7a Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 21 Mar 2017 18:17:12 -0400 Subject: drm/amd/display: Rename bandwidth_calcs.h to dce_calcs.h Signed-off-by: Harry Wentland Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 2 +- .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 504 -------------------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 506 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 +- 8 files changed, 512 insertions(+), 510 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 4820660f51d6..5ac614f433f8 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -24,7 +24,7 @@ */ #include "dm_services.h" -#include "bandwidth_calcs.h" +#include "dce_calcs.h" #include "dc.h" #include "core_types.h" #include "dal_asic_id.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c0889ad8357e..b3891228b499 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -35,7 +35,7 @@ #include "clock_source.h" #include "dc_bios_types.h" -#include "bandwidth_calcs.h" +#include "dce_calcs.h" #include "bios_parser_interface.h" #include "include/irq_service_interface.h" #include "transform.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index aac47955e9bf..9c32b5bbdff5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -31,7 +31,7 @@ #include "gmc/gmc_8_2_sh_mask.h" #include "include/logger_interface.h" -#include "inc/bandwidth_calcs.h" +#include "inc/dce_calcs.h" #include "dce110_mem_input.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c index ebb8df3cdf4a..933e3d819f27 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c @@ -31,7 +31,7 @@ #include "gmc/gmc_7_1_sh_mask.h" #include "include/logger_interface.h" -#include "inc/bandwidth_calcs.h" +#include "inc/dce_calcs.h" #include "../dce110/dce110_mem_input.h" #include "dce80_mem_input.h" diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h deleted file mode 100644 index 81fab9ef3637..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -/** - * Bandwidth and Watermark calculations interface. - * (Refer to "DCEx_mode_support.xlsm" from Perforce.) - */ -#ifndef __BANDWIDTH_CALCS_H__ -#define __BANDWIDTH_CALCS_H__ - -#include "bw_fixed.h" - -struct pipe_ctx; - -enum bw_calcs_version { - BW_CALCS_VERSION_INVALID, - BW_CALCS_VERSION_CARRIZO, - BW_CALCS_VERSION_POLARIS10, - BW_CALCS_VERSION_POLARIS11, - BW_CALCS_VERSION_STONEY, - BW_CALCS_VERSION_VEGA10 -}; - -/******************************************************************************* - * There are three types of input into Calculations: - * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP - * 2. board-level values - these are generally coming from VBIOS parser - * 3. mode/configuration values - depending Mode, Scaling number of Displays etc. - ******************************************************************************/ - -enum bw_defines { - //Common - bw_def_no = 0, - bw_def_none = 0, - bw_def_yes = 1, - bw_def_ok = 1, - bw_def_high = 2, - bw_def_mid = 1, - bw_def_low = 0, - - //Internal - bw_defs_start = 255, - bw_def_underlay422, - bw_def_underlay420_luma, - bw_def_underlay420_chroma, - bw_def_underlay444, - bw_def_graphics, - bw_def_display_write_back420_luma, - bw_def_display_write_back420_chroma, - bw_def_portrait, - bw_def_hsr_mtn_4, - bw_def_hsr_mtn_h_taps, - bw_def_ceiling__h_taps_div_4___meq_hsr, - bw_def_invalid_linear_or_stereo_mode, - bw_def_invalid_rotation_or_bpp_or_stereo, - bw_def_vsr_mtn_v_taps, - bw_def_vsr_mtn_4, - bw_def_auto, - bw_def_manual, - bw_def_exceeded_allowed_maximum_sclk, - bw_def_exceeded_allowed_page_close_open, - bw_def_exceeded_allowed_outstanding_pte_req_queue_size, - bw_def_exceeded_allowed_maximum_bw, - bw_def_landscape, - - //Panning and bezel - bw_def_any_lines, - - //Underlay mode - bw_def_underlay_only, - bw_def_blended, - bw_def_blend, - - //Stereo mode - bw_def_mono, - bw_def_side_by_side, - bw_def_top_bottom, - - //Underlay surface type - bw_def_420, - bw_def_422, - bw_def_444, - - //Tiling mode - bw_def_linear, - bw_def_tiled, - bw_def_array_linear_general, - bw_def_array_linear_aligned, - bw_def_rotated_micro_tiling, - bw_def_display_micro_tiling, - - //Memory type - bw_def_gddr5, - bw_def_hbm, - - //Voltage - bw_def_high_no_nbp_state_change, - bw_def_0_72, - bw_def_0_8, - bw_def_0_9, - - bw_def_notok = -1, - bw_def_na = -1 -}; - -struct bw_calcs_dceip { - enum bw_calcs_version version; - bool large_cursor; - uint32_t cursor_max_outstanding_group_num; - bool dmif_pipe_en_fbc_chunk_tracker; - struct bw_fixed dmif_request_buffer_size; - uint32_t lines_interleaved_into_lb; - uint32_t low_power_tiling_mode; - uint32_t chunk_width; - uint32_t number_of_graphics_pipes; - uint32_t number_of_underlay_pipes; - bool display_write_back_supported; - bool argb_compression_support; - struct bw_fixed underlay_vscaler_efficiency6_bit_per_component; - struct bw_fixed underlay_vscaler_efficiency8_bit_per_component; - struct bw_fixed underlay_vscaler_efficiency10_bit_per_component; - struct bw_fixed underlay_vscaler_efficiency12_bit_per_component; - struct bw_fixed graphics_vscaler_efficiency6_bit_per_component; - struct bw_fixed graphics_vscaler_efficiency8_bit_per_component; - struct bw_fixed graphics_vscaler_efficiency10_bit_per_component; - struct bw_fixed graphics_vscaler_efficiency12_bit_per_component; - struct bw_fixed alpha_vscaler_efficiency; - uint32_t max_dmif_buffer_allocated; - uint32_t graphics_dmif_size; - uint32_t underlay_luma_dmif_size; - uint32_t underlay_chroma_dmif_size; - bool pre_downscaler_enabled; - bool underlay_downscale_prefetch_enabled; - struct bw_fixed lb_write_pixels_per_dispclk; - struct bw_fixed lb_size_per_component444; - bool graphics_lb_nodownscaling_multi_line_prefetching; - struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor; - struct bw_fixed underlay420_luma_lb_size_per_component; - struct bw_fixed underlay420_chroma_lb_size_per_component; - struct bw_fixed underlay422_lb_size_per_component; - struct bw_fixed cursor_chunk_width; - struct bw_fixed cursor_dcp_buffer_lines; - struct bw_fixed underlay_maximum_width_efficient_for_tiling; - struct bw_fixed underlay_maximum_height_efficient_for_tiling; - struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display; - struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation; - struct bw_fixed minimum_outstanding_pte_request_limit; - struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw; - bool limit_excessive_outstanding_dmif_requests; - struct bw_fixed linear_mode_line_request_alternation_slice; - uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; - uint32_t display_write_back420_luma_mcifwr_buffer_size; - uint32_t display_write_back420_chroma_mcifwr_buffer_size; - struct bw_fixed request_efficiency; - struct bw_fixed dispclk_per_request; - struct bw_fixed dispclk_ramping_factor; - struct bw_fixed display_pipe_throughput_factor; - uint32_t scatter_gather_pte_request_rows_in_tiling_mode; - struct bw_fixed mcifwr_all_surfaces_burst_time; -}; - -struct bw_calcs_vbios { - enum bw_defines memory_type; - uint32_t dram_channel_width_in_bits; - uint32_t number_of_dram_channels; - uint32_t number_of_dram_banks; - struct bw_fixed low_yclk; /*m_hz*/ - struct bw_fixed mid_yclk; /*m_hz*/ - struct bw_fixed high_yclk; /*m_hz*/ - struct bw_fixed low_sclk; /*m_hz*/ - struct bw_fixed mid1_sclk; /*m_hz*/ - struct bw_fixed mid2_sclk; /*m_hz*/ - struct bw_fixed mid3_sclk; /*m_hz*/ - struct bw_fixed mid4_sclk; /*m_hz*/ - struct bw_fixed mid5_sclk; /*m_hz*/ - struct bw_fixed mid6_sclk; /*m_hz*/ - struct bw_fixed high_sclk; /*m_hz*/ - struct bw_fixed low_voltage_max_dispclk; /*m_hz*/ - struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/ - struct bw_fixed high_voltage_max_dispclk; /*m_hz*/ - struct bw_fixed low_voltage_max_phyclk; - struct bw_fixed mid_voltage_max_phyclk; - struct bw_fixed high_voltage_max_phyclk; - struct bw_fixed data_return_bus_width; - struct bw_fixed trc; - struct bw_fixed dmifmc_urgent_latency; - struct bw_fixed stutter_self_refresh_exit_latency; - struct bw_fixed stutter_self_refresh_entry_latency; - struct bw_fixed nbp_state_change_latency; - struct bw_fixed mcifwrmc_urgent_latency; - bool scatter_gather_enable; - struct bw_fixed down_spread_percentage; - uint32_t cursor_width; - uint32_t average_compression_rate; - uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; - struct bw_fixed blackout_duration; - struct bw_fixed maximum_blackout_recovery_time; -}; - -/******************************************************************************* - * Temporary data structure(s). - ******************************************************************************/ -#define maximum_number_of_surfaces 12 -/*Units : MHz, us */ - -struct bw_calcs_data { - /* data for all displays */ - uint32_t number_of_displays; - enum bw_defines underlay_surface_type; - enum bw_defines panning_and_bezel_adjustment; - enum bw_defines graphics_tiling_mode; - uint32_t graphics_lb_bpc; - uint32_t underlay_lb_bpc; - enum bw_defines underlay_tiling_mode; - enum bw_defines d0_underlay_mode; - bool d1_display_write_back_dwb_enable; - enum bw_defines d1_underlay_mode; - - bool cpup_state_change_enable; - bool cpuc_state_change_enable; - bool nbp_state_change_enable; - bool stutter_mode_enable; - uint32_t y_clk_level; - uint32_t sclk_level; - uint32_t number_of_underlay_surfaces; - uint32_t number_of_dram_wrchannels; - uint32_t chunk_request_delay; - uint32_t number_of_dram_channels; - enum bw_defines underlay_micro_tile_mode; - enum bw_defines graphics_micro_tile_mode; - struct bw_fixed max_phyclk; - struct bw_fixed dram_efficiency; - struct bw_fixed src_width_after_surface_type; - struct bw_fixed src_height_after_surface_type; - struct bw_fixed hsr_after_surface_type; - struct bw_fixed vsr_after_surface_type; - struct bw_fixed src_width_after_rotation; - struct bw_fixed src_height_after_rotation; - struct bw_fixed hsr_after_rotation; - struct bw_fixed vsr_after_rotation; - struct bw_fixed source_height_pixels; - struct bw_fixed hsr_after_stereo; - struct bw_fixed vsr_after_stereo; - struct bw_fixed source_width_in_lb; - struct bw_fixed lb_line_pitch; - struct bw_fixed underlay_maximum_source_efficient_for_tiling; - struct bw_fixed num_lines_at_frame_start; - struct bw_fixed min_dmif_size_in_time; - struct bw_fixed min_mcifwr_size_in_time; - struct bw_fixed total_requests_for_dmif_size; - struct bw_fixed peak_pte_request_to_eviction_ratio_limiting; - struct bw_fixed useful_pte_per_pte_request; - struct bw_fixed scatter_gather_pte_request_rows; - struct bw_fixed scatter_gather_row_height; - struct bw_fixed scatter_gather_pte_requests_in_vblank; - struct bw_fixed inefficient_linear_pitch_in_bytes; - struct bw_fixed cursor_total_data; - struct bw_fixed cursor_total_request_groups; - struct bw_fixed scatter_gather_total_pte_requests; - struct bw_fixed scatter_gather_total_pte_request_groups; - struct bw_fixed tile_width_in_pixels; - struct bw_fixed dmif_total_number_of_data_request_page_close_open; - struct bw_fixed mcifwr_total_number_of_data_request_page_close_open; - struct bw_fixed bytes_per_page_close_open; - struct bw_fixed mcifwr_total_page_close_open_time; - struct bw_fixed total_requests_for_adjusted_dmif_size; - struct bw_fixed total_dmifmc_urgent_trips; - struct bw_fixed total_dmifmc_urgent_latency; - struct bw_fixed total_display_reads_required_data; - struct bw_fixed total_display_reads_required_dram_access_data; - struct bw_fixed total_display_writes_required_data; - struct bw_fixed total_display_writes_required_dram_access_data; - struct bw_fixed display_reads_required_data; - struct bw_fixed display_reads_required_dram_access_data; - struct bw_fixed dmif_total_page_close_open_time; - struct bw_fixed min_cursor_memory_interface_buffer_size_in_time; - struct bw_fixed min_read_buffer_size_in_time; - struct bw_fixed display_reads_time_for_data_transfer; - struct bw_fixed display_writes_time_for_data_transfer; - struct bw_fixed dmif_required_dram_bandwidth; - struct bw_fixed mcifwr_required_dram_bandwidth; - struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open; - struct bw_fixed required_mcifmcwr_urgent_latency; - struct bw_fixed required_dram_bandwidth_gbyte_per_second; - struct bw_fixed dram_bandwidth; - struct bw_fixed dmif_required_sclk; - struct bw_fixed mcifwr_required_sclk; - struct bw_fixed required_sclk; - struct bw_fixed downspread_factor; - struct bw_fixed v_scaler_efficiency; - struct bw_fixed scaler_limits_factor; - struct bw_fixed display_pipe_pixel_throughput; - struct bw_fixed total_dispclk_required_with_ramping; - struct bw_fixed total_dispclk_required_without_ramping; - struct bw_fixed total_read_request_bandwidth; - struct bw_fixed total_write_request_bandwidth; - struct bw_fixed dispclk_required_for_total_read_request_bandwidth; - struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth; - struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth; - struct bw_fixed dispclk; - struct bw_fixed blackout_recovery_time; - struct bw_fixed min_pixels_per_data_fifo_entry; - struct bw_fixed sclk_deep_sleep; - struct bw_fixed chunk_request_time; - struct bw_fixed cursor_request_time; - struct bw_fixed line_source_pixels_transfer_time; - struct bw_fixed dmifdram_access_efficiency; - struct bw_fixed mcifwrdram_access_efficiency; - struct bw_fixed total_average_bandwidth_no_compression; - struct bw_fixed total_average_bandwidth; - struct bw_fixed total_stutter_cycle_duration; - struct bw_fixed stutter_burst_time; - struct bw_fixed time_in_self_refresh; - struct bw_fixed stutter_efficiency; - struct bw_fixed worst_number_of_trips_to_memory; - struct bw_fixed immediate_flip_time; - struct bw_fixed latency_for_non_dmif_clients; - struct bw_fixed latency_for_non_mcifwr_clients; - struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk; - struct bw_fixed nbp_state_dram_speed_change_margin; - struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency; - struct bw_fixed dram_speed_change_margin; - struct bw_fixed min_vblank_dram_speed_change_margin; - struct bw_fixed min_stutter_refresh_duration; - uint32_t total_stutter_dmif_buffer_size; - uint32_t total_bytes_requested; - uint32_t min_stutter_dmif_buffer_size; - uint32_t num_stutter_bursts; - struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported; - struct bw_fixed nbp_state_dram_speed_change_latency_supported; - bool fbc_en[maximum_number_of_surfaces]; - bool lpt_en[maximum_number_of_surfaces]; - bool displays_match_flag[maximum_number_of_surfaces]; - bool use_alpha[maximum_number_of_surfaces]; - bool orthogonal_rotation[maximum_number_of_surfaces]; - bool enable[maximum_number_of_surfaces]; - bool access_one_channel_only[maximum_number_of_surfaces]; - bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; - bool interlace_mode[maximum_number_of_surfaces]; - bool display_pstate_change_enable[maximum_number_of_surfaces]; - bool line_buffer_prefetch[maximum_number_of_surfaces]; - uint32_t bytes_per_pixel[maximum_number_of_surfaces]; - uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; - uint32_t lb_bpc[maximum_number_of_surfaces]; - uint32_t output_bpphdmi[maximum_number_of_surfaces]; - uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; - uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; - uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; - enum bw_defines stereo_mode[maximum_number_of_surfaces]; - struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; - struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; - struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces]; - struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces]; - struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; - struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces]; - struct bw_fixed h_total[maximum_number_of_surfaces]; - struct bw_fixed v_total[maximum_number_of_surfaces]; - struct bw_fixed pixel_rate[maximum_number_of_surfaces]; - struct bw_fixed src_width[maximum_number_of_surfaces]; - struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; - struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; - struct bw_fixed src_height[maximum_number_of_surfaces]; - struct bw_fixed scale_ratio[maximum_number_of_surfaces]; - struct bw_fixed h_taps[maximum_number_of_surfaces]; - struct bw_fixed v_taps[maximum_number_of_surfaces]; - struct bw_fixed h_scale_ratio[maximum_number_of_surfaces]; - struct bw_fixed v_scale_ratio[maximum_number_of_surfaces]; - struct bw_fixed rotation_angle[maximum_number_of_surfaces]; - struct bw_fixed compression_rate[maximum_number_of_surfaces]; - struct bw_fixed hsr[maximum_number_of_surfaces]; - struct bw_fixed vsr[maximum_number_of_surfaces]; - struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; - struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; - struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; - struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; - struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; - struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; - struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; - struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; - struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; - struct bw_fixed lb_partitions[maximum_number_of_surfaces]; - struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; - struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; - struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; - struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; - struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; - struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; - struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; - struct bw_fixed v_filter_init[maximum_number_of_surfaces]; - struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; - struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; - struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; - struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; - struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; - struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; - struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; - struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; - struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; - struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; - struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; - struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; - struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; - struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; - struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; - struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; - struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; - struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; - struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; - struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; - struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; - struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; - struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; - struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; - struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; - struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; - struct bw_fixed active_time[maximum_number_of_surfaces]; - struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; - struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; - struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces]; - uint32_t num_displays_with_margin[3][8]; - struct bw_fixed dmif_burst_time[3][8]; - struct bw_fixed mcifwr_burst_time[3][8]; - struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8]; - struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8]; - struct bw_fixed min_dram_speed_change_margin[3][8]; - struct bw_fixed dispclk_required_for_dram_speed_change[3][8]; - struct bw_fixed blackout_duration_margin[3][8]; - struct bw_fixed dispclk_required_for_blackout_duration[3][8]; - struct bw_fixed dispclk_required_for_blackout_recovery[3][8]; - struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; -}; - -/******************************************************************************* - * Output data structures. - ******************************************************************************/ -struct bw_watermarks { - uint32_t a_mark; - uint32_t b_mark; - uint32_t c_mark; - uint32_t d_mark; -}; - -struct bw_calcs_output { - bool cpuc_state_change_enable; - bool cpup_state_change_enable; - bool stutter_mode_enable; - bool nbp_state_change_enable; - bool all_displays_in_sync; - struct bw_watermarks urgent_wm_ns[6]; - struct bw_watermarks stutter_exit_wm_ns[6]; - struct bw_watermarks nbp_state_change_wm_ns[6]; - uint32_t required_sclk; - uint32_t required_sclk_deep_sleep; - uint32_t required_yclk; - uint32_t dispclk_khz; - int blackout_recovery_time_us; -}; - -/** - * Initialize structures with data which will NOT change at runtime. - */ -void bw_calcs_init( - struct bw_calcs_dceip *bw_dceip, - struct bw_calcs_vbios *bw_vbios, - struct hw_asic_id asic_id); - -/** - * Return: - * true - Display(s) configuration supported. - * In this case 'calcs_output' contains data for HW programming - * false - Display(s) configuration not supported (not enough bandwidth). - */ -bool bw_calcs( - struct dc_context *ctx, - const struct bw_calcs_dceip *dceip, - const struct bw_calcs_vbios *vbios, - const struct pipe_ctx *pipe, - int pipe_count, - struct bw_calcs_output *calcs_output); - -#endif /* __BANDWIDTH_CALCS_H__ */ - diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 7f3c6da1ebd7..405608318ccc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -27,7 +27,7 @@ #define _CORE_TYPES_H_ #include "dc.h" -#include "bandwidth_calcs.h" +#include "dce_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h new file mode 100644 index 000000000000..580dee95e57a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -0,0 +1,506 @@ +/* + * Copyright 2015-2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * Bandwidth and Watermark calculations interface. + * (Refer to "DCEx_mode_support.xlsm" from Perforce.) + */ +#ifndef __DCE_CALCS_H__ +#define __DCE_CALCS_H__ + +#include "bw_fixed.h" + +struct pipe_ctx; +struct core_dc; +struct validate_context; + +enum bw_calcs_version { + BW_CALCS_VERSION_INVALID, + BW_CALCS_VERSION_CARRIZO, + BW_CALCS_VERSION_POLARIS10, + BW_CALCS_VERSION_POLARIS11, + BW_CALCS_VERSION_STONEY, + BW_CALCS_VERSION_VEGA10 +}; + +/******************************************************************************* + * There are three types of input into Calculations: + * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP + * 2. board-level values - these are generally coming from VBIOS parser + * 3. mode/configuration values - depending Mode, Scaling number of Displays etc. + ******************************************************************************/ + +enum bw_defines { + //Common + bw_def_no = 0, + bw_def_none = 0, + bw_def_yes = 1, + bw_def_ok = 1, + bw_def_high = 2, + bw_def_mid = 1, + bw_def_low = 0, + + //Internal + bw_defs_start = 255, + bw_def_underlay422, + bw_def_underlay420_luma, + bw_def_underlay420_chroma, + bw_def_underlay444, + bw_def_graphics, + bw_def_display_write_back420_luma, + bw_def_display_write_back420_chroma, + bw_def_portrait, + bw_def_hsr_mtn_4, + bw_def_hsr_mtn_h_taps, + bw_def_ceiling__h_taps_div_4___meq_hsr, + bw_def_invalid_linear_or_stereo_mode, + bw_def_invalid_rotation_or_bpp_or_stereo, + bw_def_vsr_mtn_v_taps, + bw_def_vsr_mtn_4, + bw_def_auto, + bw_def_manual, + bw_def_exceeded_allowed_maximum_sclk, + bw_def_exceeded_allowed_page_close_open, + bw_def_exceeded_allowed_outstanding_pte_req_queue_size, + bw_def_exceeded_allowed_maximum_bw, + bw_def_landscape, + + //Panning and bezel + bw_def_any_lines, + + //Underlay mode + bw_def_underlay_only, + bw_def_blended, + bw_def_blend, + + //Stereo mode + bw_def_mono, + bw_def_side_by_side, + bw_def_top_bottom, + + //Underlay surface type + bw_def_420, + bw_def_422, + bw_def_444, + + //Tiling mode + bw_def_linear, + bw_def_tiled, + bw_def_array_linear_general, + bw_def_array_linear_aligned, + bw_def_rotated_micro_tiling, + bw_def_display_micro_tiling, + + //Memory type + bw_def_gddr5, + bw_def_hbm, + + //Voltage + bw_def_high_no_nbp_state_change, + bw_def_0_72, + bw_def_0_8, + bw_def_0_9, + + bw_def_notok = -1, + bw_def_na = -1 +}; + +struct bw_calcs_dceip { + enum bw_calcs_version version; + bool large_cursor; + uint32_t cursor_max_outstanding_group_num; + bool dmif_pipe_en_fbc_chunk_tracker; + struct bw_fixed dmif_request_buffer_size; + uint32_t lines_interleaved_into_lb; + uint32_t low_power_tiling_mode; + uint32_t chunk_width; + uint32_t number_of_graphics_pipes; + uint32_t number_of_underlay_pipes; + bool display_write_back_supported; + bool argb_compression_support; + struct bw_fixed underlay_vscaler_efficiency6_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency8_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency10_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency12_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency6_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency8_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency10_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency12_bit_per_component; + struct bw_fixed alpha_vscaler_efficiency; + uint32_t max_dmif_buffer_allocated; + uint32_t graphics_dmif_size; + uint32_t underlay_luma_dmif_size; + uint32_t underlay_chroma_dmif_size; + bool pre_downscaler_enabled; + bool underlay_downscale_prefetch_enabled; + struct bw_fixed lb_write_pixels_per_dispclk; + struct bw_fixed lb_size_per_component444; + bool graphics_lb_nodownscaling_multi_line_prefetching; + struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor; + struct bw_fixed underlay420_luma_lb_size_per_component; + struct bw_fixed underlay420_chroma_lb_size_per_component; + struct bw_fixed underlay422_lb_size_per_component; + struct bw_fixed cursor_chunk_width; + struct bw_fixed cursor_dcp_buffer_lines; + struct bw_fixed underlay_maximum_width_efficient_for_tiling; + struct bw_fixed underlay_maximum_height_efficient_for_tiling; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation; + struct bw_fixed minimum_outstanding_pte_request_limit; + struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw; + bool limit_excessive_outstanding_dmif_requests; + struct bw_fixed linear_mode_line_request_alternation_slice; + uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; + uint32_t display_write_back420_luma_mcifwr_buffer_size; + uint32_t display_write_back420_chroma_mcifwr_buffer_size; + struct bw_fixed request_efficiency; + struct bw_fixed dispclk_per_request; + struct bw_fixed dispclk_ramping_factor; + struct bw_fixed display_pipe_throughput_factor; + uint32_t scatter_gather_pte_request_rows_in_tiling_mode; + struct bw_fixed mcifwr_all_surfaces_burst_time; +}; + +struct bw_calcs_vbios { + enum bw_defines memory_type; + uint32_t dram_channel_width_in_bits; + uint32_t number_of_dram_channels; + uint32_t number_of_dram_banks; + struct bw_fixed low_yclk; /*m_hz*/ + struct bw_fixed mid_yclk; /*m_hz*/ + struct bw_fixed high_yclk; /*m_hz*/ + struct bw_fixed low_sclk; /*m_hz*/ + struct bw_fixed mid1_sclk; /*m_hz*/ + struct bw_fixed mid2_sclk; /*m_hz*/ + struct bw_fixed mid3_sclk; /*m_hz*/ + struct bw_fixed mid4_sclk; /*m_hz*/ + struct bw_fixed mid5_sclk; /*m_hz*/ + struct bw_fixed mid6_sclk; /*m_hz*/ + struct bw_fixed high_sclk; /*m_hz*/ + struct bw_fixed low_voltage_max_dispclk; /*m_hz*/ + struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/ + struct bw_fixed high_voltage_max_dispclk; /*m_hz*/ + struct bw_fixed low_voltage_max_phyclk; + struct bw_fixed mid_voltage_max_phyclk; + struct bw_fixed high_voltage_max_phyclk; + struct bw_fixed data_return_bus_width; + struct bw_fixed trc; + struct bw_fixed dmifmc_urgent_latency; + struct bw_fixed stutter_self_refresh_exit_latency; + struct bw_fixed stutter_self_refresh_entry_latency; + struct bw_fixed nbp_state_change_latency; + struct bw_fixed mcifwrmc_urgent_latency; + bool scatter_gather_enable; + struct bw_fixed down_spread_percentage; + uint32_t cursor_width; + uint32_t average_compression_rate; + uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; + struct bw_fixed blackout_duration; + struct bw_fixed maximum_blackout_recovery_time; +}; + +/******************************************************************************* + * Temporary data structure(s). + ******************************************************************************/ +#define maximum_number_of_surfaces 12 +/*Units : MHz, us */ + +struct bw_calcs_data { + /* data for all displays */ + uint32_t number_of_displays; + enum bw_defines underlay_surface_type; + enum bw_defines panning_and_bezel_adjustment; + enum bw_defines graphics_tiling_mode; + uint32_t graphics_lb_bpc; + uint32_t underlay_lb_bpc; + enum bw_defines underlay_tiling_mode; + enum bw_defines d0_underlay_mode; + bool d1_display_write_back_dwb_enable; + enum bw_defines d1_underlay_mode; + + bool cpup_state_change_enable; + bool cpuc_state_change_enable; + bool nbp_state_change_enable; + bool stutter_mode_enable; + uint32_t y_clk_level; + uint32_t sclk_level; + uint32_t number_of_underlay_surfaces; + uint32_t number_of_dram_wrchannels; + uint32_t chunk_request_delay; + uint32_t number_of_dram_channels; + enum bw_defines underlay_micro_tile_mode; + enum bw_defines graphics_micro_tile_mode; + struct bw_fixed max_phyclk; + struct bw_fixed dram_efficiency; + struct bw_fixed src_width_after_surface_type; + struct bw_fixed src_height_after_surface_type; + struct bw_fixed hsr_after_surface_type; + struct bw_fixed vsr_after_surface_type; + struct bw_fixed src_width_after_rotation; + struct bw_fixed src_height_after_rotation; + struct bw_fixed hsr_after_rotation; + struct bw_fixed vsr_after_rotation; + struct bw_fixed source_height_pixels; + struct bw_fixed hsr_after_stereo; + struct bw_fixed vsr_after_stereo; + struct bw_fixed source_width_in_lb; + struct bw_fixed lb_line_pitch; + struct bw_fixed underlay_maximum_source_efficient_for_tiling; + struct bw_fixed num_lines_at_frame_start; + struct bw_fixed min_dmif_size_in_time; + struct bw_fixed min_mcifwr_size_in_time; + struct bw_fixed total_requests_for_dmif_size; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting; + struct bw_fixed useful_pte_per_pte_request; + struct bw_fixed scatter_gather_pte_request_rows; + struct bw_fixed scatter_gather_row_height; + struct bw_fixed scatter_gather_pte_requests_in_vblank; + struct bw_fixed inefficient_linear_pitch_in_bytes; + struct bw_fixed cursor_total_data; + struct bw_fixed cursor_total_request_groups; + struct bw_fixed scatter_gather_total_pte_requests; + struct bw_fixed scatter_gather_total_pte_request_groups; + struct bw_fixed tile_width_in_pixels; + struct bw_fixed dmif_total_number_of_data_request_page_close_open; + struct bw_fixed mcifwr_total_number_of_data_request_page_close_open; + struct bw_fixed bytes_per_page_close_open; + struct bw_fixed mcifwr_total_page_close_open_time; + struct bw_fixed total_requests_for_adjusted_dmif_size; + struct bw_fixed total_dmifmc_urgent_trips; + struct bw_fixed total_dmifmc_urgent_latency; + struct bw_fixed total_display_reads_required_data; + struct bw_fixed total_display_reads_required_dram_access_data; + struct bw_fixed total_display_writes_required_data; + struct bw_fixed total_display_writes_required_dram_access_data; + struct bw_fixed display_reads_required_data; + struct bw_fixed display_reads_required_dram_access_data; + struct bw_fixed dmif_total_page_close_open_time; + struct bw_fixed min_cursor_memory_interface_buffer_size_in_time; + struct bw_fixed min_read_buffer_size_in_time; + struct bw_fixed display_reads_time_for_data_transfer; + struct bw_fixed display_writes_time_for_data_transfer; + struct bw_fixed dmif_required_dram_bandwidth; + struct bw_fixed mcifwr_required_dram_bandwidth; + struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open; + struct bw_fixed required_mcifmcwr_urgent_latency; + struct bw_fixed required_dram_bandwidth_gbyte_per_second; + struct bw_fixed dram_bandwidth; + struct bw_fixed dmif_required_sclk; + struct bw_fixed mcifwr_required_sclk; + struct bw_fixed required_sclk; + struct bw_fixed downspread_factor; + struct bw_fixed v_scaler_efficiency; + struct bw_fixed scaler_limits_factor; + struct bw_fixed display_pipe_pixel_throughput; + struct bw_fixed total_dispclk_required_with_ramping; + struct bw_fixed total_dispclk_required_without_ramping; + struct bw_fixed total_read_request_bandwidth; + struct bw_fixed total_write_request_bandwidth; + struct bw_fixed dispclk_required_for_total_read_request_bandwidth; + struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth; + struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth; + struct bw_fixed dispclk; + struct bw_fixed blackout_recovery_time; + struct bw_fixed min_pixels_per_data_fifo_entry; + struct bw_fixed sclk_deep_sleep; + struct bw_fixed chunk_request_time; + struct bw_fixed cursor_request_time; + struct bw_fixed line_source_pixels_transfer_time; + struct bw_fixed dmifdram_access_efficiency; + struct bw_fixed mcifwrdram_access_efficiency; + struct bw_fixed total_average_bandwidth_no_compression; + struct bw_fixed total_average_bandwidth; + struct bw_fixed total_stutter_cycle_duration; + struct bw_fixed stutter_burst_time; + struct bw_fixed time_in_self_refresh; + struct bw_fixed stutter_efficiency; + struct bw_fixed worst_number_of_trips_to_memory; + struct bw_fixed immediate_flip_time; + struct bw_fixed latency_for_non_dmif_clients; + struct bw_fixed latency_for_non_mcifwr_clients; + struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk; + struct bw_fixed nbp_state_dram_speed_change_margin; + struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency; + struct bw_fixed dram_speed_change_margin; + struct bw_fixed min_vblank_dram_speed_change_margin; + struct bw_fixed min_stutter_refresh_duration; + uint32_t total_stutter_dmif_buffer_size; + uint32_t total_bytes_requested; + uint32_t min_stutter_dmif_buffer_size; + uint32_t num_stutter_bursts; + struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported; + struct bw_fixed nbp_state_dram_speed_change_latency_supported; + bool fbc_en[maximum_number_of_surfaces]; + bool lpt_en[maximum_number_of_surfaces]; + bool displays_match_flag[maximum_number_of_surfaces]; + bool use_alpha[maximum_number_of_surfaces]; + bool orthogonal_rotation[maximum_number_of_surfaces]; + bool enable[maximum_number_of_surfaces]; + bool access_one_channel_only[maximum_number_of_surfaces]; + bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; + bool interlace_mode[maximum_number_of_surfaces]; + bool display_pstate_change_enable[maximum_number_of_surfaces]; + bool line_buffer_prefetch[maximum_number_of_surfaces]; + uint32_t bytes_per_pixel[maximum_number_of_surfaces]; + uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; + uint32_t lb_bpc[maximum_number_of_surfaces]; + uint32_t output_bpphdmi[maximum_number_of_surfaces]; + uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; + uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; + uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; + enum bw_defines stereo_mode[maximum_number_of_surfaces]; + struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; + struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; + struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces]; + struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; + struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces]; + struct bw_fixed h_total[maximum_number_of_surfaces]; + struct bw_fixed v_total[maximum_number_of_surfaces]; + struct bw_fixed pixel_rate[maximum_number_of_surfaces]; + struct bw_fixed src_width[maximum_number_of_surfaces]; + struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; + struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; + struct bw_fixed src_height[maximum_number_of_surfaces]; + struct bw_fixed scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed h_taps[maximum_number_of_surfaces]; + struct bw_fixed v_taps[maximum_number_of_surfaces]; + struct bw_fixed h_scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed v_scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed rotation_angle[maximum_number_of_surfaces]; + struct bw_fixed compression_rate[maximum_number_of_surfaces]; + struct bw_fixed hsr[maximum_number_of_surfaces]; + struct bw_fixed vsr[maximum_number_of_surfaces]; + struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; + struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; + struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; + struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; + struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; + struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; + struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; + struct bw_fixed lb_partitions[maximum_number_of_surfaces]; + struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; + struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; + struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; + struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; + struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; + struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; + struct bw_fixed v_filter_init[maximum_number_of_surfaces]; + struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; + struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; + struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; + struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; + struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; + struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; + struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; + struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; + struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; + struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; + struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; + struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; + struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; + struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; + struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed active_time[maximum_number_of_surfaces]; + struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; + struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces]; + uint32_t num_displays_with_margin[3][8]; + struct bw_fixed dmif_burst_time[3][8]; + struct bw_fixed mcifwr_burst_time[3][8]; + struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8]; + struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8]; + struct bw_fixed min_dram_speed_change_margin[3][8]; + struct bw_fixed dispclk_required_for_dram_speed_change[3][8]; + struct bw_fixed blackout_duration_margin[3][8]; + struct bw_fixed dispclk_required_for_blackout_duration[3][8]; + struct bw_fixed dispclk_required_for_blackout_recovery[3][8]; + struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; +}; + +/******************************************************************************* + * Output data structures. + ******************************************************************************/ +struct bw_watermarks { + uint32_t a_mark; + uint32_t b_mark; + uint32_t c_mark; + uint32_t d_mark; +}; + +struct bw_calcs_output { + bool cpuc_state_change_enable; + bool cpup_state_change_enable; + bool stutter_mode_enable; + bool nbp_state_change_enable; + bool all_displays_in_sync; + struct bw_watermarks urgent_wm_ns[6]; + struct bw_watermarks stutter_exit_wm_ns[6]; + struct bw_watermarks nbp_state_change_wm_ns[6]; + uint32_t required_sclk; + uint32_t required_sclk_deep_sleep; + uint32_t required_yclk; + uint32_t dispclk_khz; + int blackout_recovery_time_us; +}; + +/** + * Initialize structures with data which will NOT change at runtime. + */ +void bw_calcs_init( + struct bw_calcs_dceip *bw_dceip, + struct bw_calcs_vbios *bw_vbios, + struct hw_asic_id asic_id); + +/** + * Return: + * true - Display(s) configuration supported. + * In this case 'calcs_output' contains data for HW programming + * false - Display(s) configuration not supported (not enough bandwidth). + */ +bool bw_calcs( + struct dc_context *ctx, + const struct bw_calcs_dceip *dceip, + const struct bw_calcs_vbios *vbios, + const struct pipe_ctx *pipe, + int pipe_count, + struct bw_calcs_output *calcs_output); + +#endif /* __BANDWIDTH_CALCS_H__ */ + diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 7ec4027700d8..179f5ad70f48 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -27,7 +27,7 @@ #include "dc.h" #include "include/grph_object_id.h" -#include "inc/bandwidth_calcs.h" +#include "inc/dce_calcs.h" #include "dce/dce_mem_input.h" /* temporary */ -- cgit v1.2.3-59-g8ed1b From 667e1498a9d0e43849fa84c1c6874184b33aee5f Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 23 Mar 2017 15:27:15 -0400 Subject: drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as VBLANK trigger. VBLANK interrupt is driven bu line buffer vcounter which is ahead of CRTC vcounter. Use an interrupt that fires at the actual CRTC vblank start boundry. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- .../display/dc/dce110/dce110_timing_generator.c | 46 ++++++++++++++- .../display/dc/dce110/dce110_timing_generator.h | 3 + .../display/dc/dce120/dce120_timing_generator.c | 32 +++++++++- .../amd/display/dc/dce80/dce80_timing_generator.c | 1 + .../drm/amd/display/dc/inc/hw/timing_generator.h | 2 + .../amd/display/dc/irq/dce110/irq_service_dce110.c | 68 +++++++++++++++------- .../amd/display/dc/irq/dce110/irq_service_dce110.h | 5 ++ .../amd/display/dc/irq/dce120/irq_service_dce120.c | 11 ++-- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 22 ++++--- 9 files changed, 152 insertions(+), 38 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index f4b8576a0546..006412be7a02 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1869,6 +1869,48 @@ void dce110_tg_set_colors(struct timing_generator *tg, dce110_tg_set_overscan_color(tg, overscan_color); } +/* Gets first line of blank region of the display timing for CRTC + * and programms is as a trigger to fire vertical interrupt + */ +bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t vbl = 0; + uint32_t val = 0; + uint32_t position, vbl_start; + + tg->funcs->get_scanoutpos( + tg, + &vbl, + &position); + + if (vbl == 0) + return false; + + vbl_start = + get_reg_field_value( + vbl, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + + set_reg_field_value( + val, + vbl_start, + CRTC_VERTICAL_INTERRUPT0_POSITION, + CRTC_VERTICAL_INTERRUPT0_LINE_START); + + /* Set interaval width for interrupt to fire to 1 scanline */ + set_reg_field_value( + val, + vbl_start + width, + CRTC_VERTICAL_INTERRUPT0_POSITION, + CRTC_VERTICAL_INTERRUPT0_LINE_END); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERTICAL_INTERRUPT0_POSITION), val); + + return true; +} + static const struct timing_generator_funcs dce110_tg_funcs = { .validate_timing = dce110_tg_validate_timing, .program_timing = dce110_tg_program_timing, @@ -1901,8 +1943,8 @@ static const struct timing_generator_funcs dce110_tg_funcs = { dce110_timing_generator_set_drr, .set_static_screen_control = dce110_timing_generator_set_static_screen_control, - .set_test_pattern = dce110_timing_generator_set_test_pattern - + .set_test_pattern = dce110_timing_generator_set_test_pattern, + .arm_vert_intr = dce110_arm_vert_intr, }; bool dce110_timing_generator_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 378509b8e56c..ca387b40fc67 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -271,4 +271,7 @@ void dce110_tg_set_colors(struct timing_generator *tg, const struct tg_color *blank_color, const struct tg_color *overscan_color); +bool dce110_arm_vert_intr( + struct timing_generator *tg, uint8_t width); + #endif /* __DC_TIMING_GENERATOR_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index d7e787b591a0..95cb1768aeb5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -1039,6 +1039,35 @@ void dce120_timing_generator_set_test_pattern( } } +static bool dce120_arm_vert_intr( + struct timing_generator *tg, + uint8_t width) +{ + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + uint32_t vbl, position, vbl_start; + + tg->funcs->get_scanoutpos( + tg, + &vbl, + &position); + + if (vbl == 0) + return false; + + vbl_start = + get_reg_field_value( + vbl, + CRTC0_CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + + CRTC_REG_SET_2( + CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION, + CRTC_VERTICAL_INTERRUPT0_LINE_START, vbl_start, + CRTC_VERTICAL_INTERRUPT0_LINE_END, vbl_start + width); + + return true; +} + static struct timing_generator_funcs dce120_tg_funcs = { .validate_timing = dce120_tg_validate_timing, .program_timing = dce120_tg_program_timing, @@ -1068,7 +1097,8 @@ static struct timing_generator_funcs dce120_tg_funcs = { .enable_advanced_request = dce120_timing_generator_enable_advanced_request, .set_drr = dce120_timing_generator_set_drr, .set_static_screen_control = dce120_timing_generator_set_static_screen_control, - .set_test_pattern = dce120_timing_generator_set_test_pattern + .set_test_pattern = dce120_timing_generator_set_test_pattern, + .arm_vert_intr = dce120_arm_vert_intr, }; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c index eeccabd65a7a..1198f2fbf9c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c @@ -145,6 +145,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = { .set_static_screen_control = dce110_timing_generator_set_static_screen_control, .set_test_pattern = dce110_timing_generator_set_test_pattern, + .arm_vert_intr = dce110_arm_vert_intr, /* DCE8.0 overrides */ .enable_advanced_request = diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 62c19358254b..51902a4f8798 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -156,6 +156,8 @@ struct timing_generator_funcs { enum controller_dp_test_pattern test_pattern, enum dc_color_depth color_depth); + bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); + }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 4c7c85d45518..52361d1472fa 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -31,14 +31,10 @@ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" + #include "ivsrcid/ivsrcid_vislands30.h" -#define VISLANDS30_IV_SRCID_D1_VBLANK 1 -#define VISLANDS30_IV_SRCID_D2_VBLANK 2 -#define VISLANDS30_IV_SRCID_D3_VBLANK 3 -#define VISLANDS30_IV_SRCID_D4_VBLANK 4 -#define VISLANDS30_IV_SRCID_D5_VBLANK 5 -#define VISLANDS30_IV_SRCID_D6_VBLANK 6 +#include "core_dc.h" static bool hpd_ack( struct irq_service *irq_service, @@ -83,7 +79,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = { }; static const struct irq_source_info_funcs vblank_irq_info_funcs = { - .set = NULL, + .set = dce110_vblank_set, .ack = NULL }; @@ -148,18 +144,19 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { #define vblank_int_entry(reg_num)\ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ - .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\ + .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ .enable_mask =\ - LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ .enable_value = {\ - LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\ - ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\ - .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ + ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\ + .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ .ack_mask =\ - LB_VBLANK_STATUS__VBLANK_ACK_MASK,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ .ack_value =\ - LB_VBLANK_STATUS__VBLANK_ACK_MASK,\ - .funcs = &vblank_irq_info_funcs\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ + .funcs = &vblank_irq_info_funcs,\ + .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ } #define dummy_irq_entry() \ @@ -202,6 +199,35 @@ bool dal_irq_service_dummy_ack( return false; } + +bool dce110_vblank_set( + struct irq_service *irq_service, + const struct irq_source_info *info, + bool enable) +{ + struct dc_context *dc_ctx = irq_service->ctx; + struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc); + enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source( + irq_service->ctx->dc, + info->src_id, + info->ext_id); + uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; + + struct timing_generator *tg = + core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].tg; + + if (enable) { + if (!tg->funcs->arm_vert_intr(tg, 2)) { + DC_ERROR("Failed to get VBLANK!\n"); + return false; + } + } + + dal_irq_service_set_generic(irq_service, info, enable); + return true; + +} + static const struct irq_source_info_funcs dummy_irq_info_funcs = { .set = dal_irq_service_dummy_set, .ack = dal_irq_service_dummy_ack @@ -302,17 +328,17 @@ enum dc_irq_source to_dal_irq_source_dce110( uint32_t ext_id) { switch (src_id) { - case VISLANDS30_IV_SRCID_D1_VBLANK: + case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0: return DC_IRQ_SOURCE_VBLANK1; - case VISLANDS30_IV_SRCID_D2_VBLANK: + case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0: return DC_IRQ_SOURCE_VBLANK2; - case VISLANDS30_IV_SRCID_D3_VBLANK: + case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0: return DC_IRQ_SOURCE_VBLANK3; - case VISLANDS30_IV_SRCID_D4_VBLANK: + case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0: return DC_IRQ_SOURCE_VBLANK4; - case VISLANDS30_IV_SRCID_D5_VBLANK: + case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0: return DC_IRQ_SOURCE_VBLANK5; - case VISLANDS30_IV_SRCID_D6_VBLANK: + case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0: return DC_IRQ_SOURCE_VBLANK6; case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT: return DC_IRQ_SOURCE_VUPDATE1; diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h index a84f360c6515..9237646c0959 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h @@ -45,4 +45,9 @@ bool dal_irq_service_dummy_ack( struct irq_service *irq_service, const struct irq_source_info *info); +bool dce110_vblank_set( + struct irq_service *irq_service, + const struct irq_source_info *info, + bool enable); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 5a263b2efa51..3871633ac635 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -79,7 +79,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = { }; static const struct irq_source_info_funcs vblank_irq_info_funcs = { - .set = NULL, + .set = dce110_vblank_set, .ack = NULL }; @@ -144,10 +144,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { #define vblank_int_entry(reg_num)\ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ - IRQ_REG_ENTRY(LB, reg_num,\ - LB_INTERRUPT_MASK, VBLANK_INTERRUPT_MASK,\ - LB_VBLANK_STATUS, VBLANK_ACK),\ - .funcs = &vblank_irq_info_funcs\ + IRQ_REG_ENTRY(CRTC, reg_num,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vblank_irq_info_funcs,\ + .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ } #define dummy_irq_entry() \ diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index dd09d2b6d4a7..7e8cb22f280f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -35,6 +35,9 @@ #include "ivsrcid/ivsrcid_vislands30.h" +#include "dc_types.h" +#include "inc/core_dc.h" + static bool hpd_ack( struct irq_service *irq_service, const struct irq_source_info *info) @@ -78,7 +81,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = { }; static const struct irq_source_info_funcs vblank_irq_info_funcs = { - .set = NULL, + .set = dce110_vblank_set, .ack = NULL }; @@ -145,18 +148,19 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { #define vblank_int_entry(reg_num)\ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ - .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\ + .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ .enable_mask =\ - LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ .enable_value = {\ - LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\ - ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\ - .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ + ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\ + .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ .ack_mask =\ - LB_VBLANK_STATUS__VBLANK_ACK_MASK,\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ .ack_value =\ - LB_VBLANK_STATUS__VBLANK_ACK_MASK,\ - .funcs = &vblank_irq_info_funcs\ + CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ + .funcs = &vblank_irq_info_funcs,\ + .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ } #define dummy_irq_entry() \ -- cgit v1.2.3-59-g8ed1b From d4e13b0db124345be93bc2ff39ecb48409da2c9b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:24:01 -0400 Subject: drm/amd/display: decouple per-crtc-plane model Current design has per-crtc-plane model. As a result, for asic's that support underlay, are unable to expose it to user space for modesetting. To enable this, the drm driver intialisation now runs for number of surfaces instead of stream/crtc. This patch plumbs surface capabilities to drm framework so that it can be effectively used by user space. Tests: (On Chromium OS for Stoney Only) * 'modetest -p' now shows additional plane with YUV capabilities in case of CZ and ST. * 'plane_test' fails with below error: [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0 as ther is no support for YUYV * Checked multimonitor display works fine Signed-off-by: Shirish S Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 +++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 67 ++++++++++++++----- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 76 +++++++++++++++------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 5 +- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../drm/amd/display/dc/dce100/dce100_resource.c | 2 + .../drm/amd/display/dc/dce110/dce110_resource.c | 2 + .../drm/amd/display/dc/dce112/dce112_resource.c | 2 + .../drm/amd/display/dc/dce120/dce120_resource.c | 2 + .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 + 10 files changed, 127 insertions(+), 40 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index e5d2ce48cb1e..362d9559f065 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -60,6 +60,7 @@ struct amdgpu_hpd; #define AMDGPU_MAX_HPD_PINS 6 #define AMDGPU_MAX_CRTCS 6 +#define AMDGPU_MAX_PLANES 6 #define AMDGPU_MAX_AFMT_BLOCKS 9 enum amdgpu_rmx_type { @@ -327,6 +328,7 @@ struct amdgpu_mode_info { struct card_info *atom_card_info; bool mode_config_initialized; struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; + struct amdgpu_plane *planes[AMDGPU_MAX_PLANES]; struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; /* DVI-I properties */ struct drm_property *coherent_mode_property; @@ -356,6 +358,7 @@ struct amdgpu_mode_info { int num_dig; /* number of dig blocks */ int disp_priority; const struct amdgpu_display_funcs *funcs; + enum drm_plane_type *plane_type; }; #define AMDGPU_MAX_BL_LEVEL 0xFF @@ -436,6 +439,11 @@ struct amdgpu_crtc { struct drm_pending_vblank_event *event; }; +struct amdgpu_plane { + struct drm_plane base; + enum drm_plane_type plane_type; +}; + struct amdgpu_encoder_atom_dig { bool linkb; /* atom dig */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b08ec453b773..d76448d04423 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -49,6 +49,28 @@ #include "modules/inc/mod_freesync.h" +static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, +}; + +static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ +}; + +static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ +}; + /* * dm_vblank_get_counter * @@ -1051,30 +1073,34 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) uint32_t i; struct amdgpu_connector *aconnector; struct amdgpu_encoder *aencoder; - struct amdgpu_crtc *acrtc; + struct amdgpu_mode_info *mode_info = &adev->mode_info; uint32_t link_cnt; link_cnt = dm->dc->caps.max_links; - if (amdgpu_dm_mode_config_init(dm->adev)) { DRM_ERROR("DM: Failed to initialize mode config\n"); - return -1; + goto fail; } - for (i = 0; i < dm->dc->caps.max_streams; i++) { - acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); - if (!acrtc) - goto fail; + for (i = 0; i < dm->dc->caps.max_surfaces; i++) { + mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), + GFP_KERNEL); + if (!mode_info->planes[i]) { + DRM_ERROR("KMS: Failed to allocate surface\n"); + goto fail_free_planes; + } + mode_info->planes[i]->plane_type = mode_info->plane_type[i]; + if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) { + DRM_ERROR("KMS: Failed to initialize plane\n"); + goto fail_free_planes; + } + } - if (amdgpu_dm_crtc_init( - dm, - acrtc, - i)) { + for (i = 0; i < dm->dc->caps.max_streams; i++) + if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { DRM_ERROR("KMS: Failed to initialize crtc\n"); - kfree(acrtc); - goto fail; + goto fail_free_planes; } - } dm->display_indexes_num = dm->dc->caps.max_streams; @@ -1125,12 +1151,12 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_VEGA10: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - return -1; + goto fail_free_encoder; } break; default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); - return -1; + goto fail_free_encoder; } drm_mode_config_reset(dm->ddev); @@ -1140,6 +1166,9 @@ fail_free_encoder: kfree(aencoder); fail_free_connector: kfree(aconnector); +fail_free_planes: + for (i = 0; i < dm->dc->caps.max_surfaces; i++) + kfree(mode_info->planes[i]); fail: return -1; } @@ -1361,33 +1390,39 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; + adev->mode_info.plane_type = dm_surfaces_type_carizzo; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; + adev->mode_info.plane_type = dm_surfaces_type_stoney; break; case CHIP_POLARIS11: case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_VEGA10: adev->mode_info.num_crtc = 6; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index ee9239ab734c..1751f138c36a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1446,6 +1446,8 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { }; static const struct drm_plane_funcs dm_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, .reset = drm_atomic_helper_plane_reset, .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, .atomic_destroy_state = drm_atomic_helper_plane_destroy_state @@ -1577,38 +1579,67 @@ static uint32_t rgb_formats[] = { DRM_FORMAT_ABGR2101010, }; -int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct amdgpu_crtc *acrtc, - uint32_t crtc_index) +static uint32_t yuv_formats[] = { + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, +}; + +int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs) { - int res = -ENOMEM; + int res = -EPERM; - struct drm_plane *primary_plane = - kzalloc(sizeof(*primary_plane), GFP_KERNEL); + switch (aplane->plane_type) { + case DRM_PLANE_TYPE_PRIMARY: + aplane->base.format_default = true; - if (!primary_plane) - goto fail_plane; + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + rgb_formats, + ARRAY_SIZE(rgb_formats), + NULL, aplane->plane_type, NULL); + break; + case DRM_PLANE_TYPE_OVERLAY: + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + yuv_formats, + ARRAY_SIZE(yuv_formats), + NULL, aplane->plane_type, NULL); + break; + case DRM_PLANE_TYPE_CURSOR: + DRM_ERROR("KMS: Cursor plane not implemented."); + break; + } - primary_plane->format_default = true; + drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); - res = drm_universal_plane_init( - dm->adev->ddev, - primary_plane, - 0, - &dm_plane_funcs, - rgb_formats, - ARRAY_SIZE(rgb_formats), - NULL, - DRM_PLANE_TYPE_PRIMARY, NULL); + return res; +} - primary_plane->crtc = &acrtc->base; +int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t crtc_index) +{ + struct amdgpu_crtc *acrtc; + int res = -ENOMEM; - drm_plane_helper_add(primary_plane, &dm_plane_helper_funcs); + acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); + if (!acrtc) + goto fail; res = drm_crtc_init_with_planes( dm->ddev, &acrtc->base, - primary_plane, + plane, NULL, &amdgpu_dm_crtc_funcs, NULL); @@ -1628,8 +1659,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, return 0; fail: - kfree(primary_plane); -fail_plane: + kfree(acrtc); acrtc->crtc_id = -1; return res; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 1bbeb87dc9d0..ab6d51dbbf4b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -34,8 +34,11 @@ struct dc_validation_set; struct dc_surface; /*TODO Jodan Hersen use the one in amdgpu_dm*/ +int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs); int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct amdgpu_crtc *amdgpu_crtc, + struct drm_plane *plane, uint32_t link_index); int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, struct amdgpu_connector *amdgpu_connector, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 0731045f6084..9dd8b2ad4c59 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,6 +45,7 @@ struct dc_caps { uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; + uint32_t max_surfaces; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index b6f77f88be9c..d1685df09815 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -1035,6 +1035,8 @@ static bool construct( } } + dc->public.caps.max_surfaces = pool->base.pipe_count; + if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) goto res_create_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index e3002031c40d..065a2986b666 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1455,6 +1455,8 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; + dc->public.caps.max_surfaces = pool->base.pipe_count; + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 32aa1b5bf1f9..ece3ec72363d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1409,6 +1409,8 @@ static bool construct( &res_create_funcs)) goto res_create_fail; + dc->public.caps.max_surfaces = pool->base.pipe_count; + /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) goto res_create_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index efa58889058b..f677a77ca6e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -1060,6 +1060,8 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; + dc->public.caps.max_surfaces = pool->base.pipe_count; + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index a3e8182885b2..752e0e7579b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -1043,6 +1043,8 @@ static bool construct( } } + dc->public.caps.max_surfaces = pool->base.pipe_count; + if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) goto res_create_fail; -- cgit v1.2.3-59-g8ed1b From 934d292316b5d3933d7fe6811c5d7a696c33910c Mon Sep 17 00:00:00 2001 From: Reza Amini Date: Fri, 17 Mar 2017 15:24:09 -0400 Subject: drm/amd/display: remove surface validation against stream rect Surface information is by default copied from old context in dc_commit_stream. Thus unchange streams will not be affected. For new streams, we shouldn't validate the new mode against the surface configuration of old_context. Signed-off-by: Reza Amini Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 5 ----- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 5 ----- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 5 ----- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 5 ----- 4 files changed, 20 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index d1685df09815..7fae8537e18a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -788,11 +788,6 @@ static bool dce100_validate_surface_sets( if (set[i].surface_count > 1) return false; - if (set[i].surfaces[0]->clip_rect.width - < set[i].stream->src.width - || set[i].surfaces[0]->clip_rect.height - < set[i].stream->src.height) - return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 065a2986b666..b4ab438e1c97 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1007,11 +1007,6 @@ static bool dce110_validate_surface_sets( if (set[i].surface_count > 2) return false; - if (set[i].surfaces[0]->clip_rect.width - > set[i].stream->src.width - || set[i].surfaces[0]->clip_rect.height - > set[i].stream->src.height) - return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index ece3ec72363d..0a1ad2808129 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -972,11 +972,6 @@ static bool dce112_validate_surface_sets( if (set[i].surface_count > 1) return false; - if (set[i].surfaces[0]->clip_rect.width - > set[i].stream->src.width - || set[i].surfaces[0]->clip_rect.height - > set[i].stream->src.height) - return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 752e0e7579b9..ab8cee3e734e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -804,11 +804,6 @@ static bool dce80_validate_surface_sets( if (set[i].surface_count > 1) return false; - if (set[i].surfaces[0]->clip_rect.width - > set[i].stream->src.width - || set[i].surfaces[0]->clip_rect.height - > set[i].stream->src.height) - return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; -- cgit v1.2.3-59-g8ed1b From 28f72454320d2084cc082c8509135bdfd4012c10 Mon Sep 17 00:00:00 2001 From: Jordan Lazare Date: Thu, 30 Mar 2017 13:08:34 -0400 Subject: drm/amd/display: Fill in vrefresh and min_vblank_time for dce8/dce10 PPLib is now calling into DC to get vrefresh and min_vblank_time, but since full bandwidth calcs are missing for those generations, the pplib structures were never being filled. This change fills the currently required fields to prevent screen corruption. Signed-off-by: Jordan Lazare Acked-by: Harry Wentland Reviewed-by: Jordan Lazare Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 21 +++++++++++++++++++++ .../drm/amd/display/dc/dce100/dce100_hw_sequencer.h | 5 +++++ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 8 ++++---- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 8 ++++++++ .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 2 ++ 5 files changed, 40 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index bd8e19f1038b..f11044e0245c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -104,6 +104,26 @@ static bool dce100_enable_display_power_gating( return false; } +void dce100_pplib_apply_display_requirements( + struct core_dc *dc, + struct validate_context *context) +{ + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + + pp_display_cfg->avail_mclk_switch_time_us = + dce110_get_min_vblank_time_us(context); + + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( + struct dm_pp_display_configuration)) != 0) + dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); + + dc->prev_display_config = *pp_display_cfg; +} + + + static void set_displaymarks( const struct core_dc *dc, struct validate_context *context) { @@ -116,6 +136,7 @@ static void set_bandwidth( bool decrease_allowed) { dc->hwss.set_displaymarks(dc, context); + dce100_pplib_apply_display_requirements(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index cf497ea605c8..f51d04a66a49 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -29,8 +29,13 @@ #include "core_types.h" struct core_dc; +struct validate_context; bool dce100_hw_sequencer_construct(struct core_dc *dc); +void dce100_pplib_apply_display_requirements( + struct core_dc *dc, + struct validate_context *context); + #endif /* __DC_HWSS_DCE100_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2a3a39e31717..839c34409c63 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2097,7 +2097,7 @@ static void init_hw(struct core_dc *dc) } } -static void fill_display_configs( +void dce110_fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg) { @@ -2146,7 +2146,7 @@ static void fill_display_configs( pp_display_cfg->display_count = num_cfgs; } -static uint32_t get_min_vblank_time_us(const struct validate_context *context) +uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) { uint8_t j; uint32_t min_vertical_blank_time = -1; @@ -2224,13 +2224,13 @@ static void pplib_apply_display_requirements( = context->bw_results.required_sclk_deep_sleep; pp_display_cfg->avail_mclk_switch_time_us = - get_min_vblank_time_us(context); + dce110_get_min_vblank_time_us(context); /* TODO: dce11.2*/ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; pp_display_cfg->disp_clk_khz = context->dispclk_khz; - fill_display_configs(context, pp_display_cfg); + dce110_fill_display_configs(context, pp_display_cfg); /* TODO: is this still applicable?*/ if (pp_display_cfg->display_count == 1) { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index a6b4d0d2429f..52462c17b2e9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -30,6 +30,8 @@ #define GAMMA_HW_POINTS_NUM 256 struct core_dc; +struct validate_context; +struct dm_pp_display_configuration; bool dce110_hw_sequencer_construct(struct core_dc *dc); @@ -58,5 +60,11 @@ void dce110_power_down(struct core_dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); +void dce110_fill_display_configs( + const struct validate_context *context, + struct dm_pp_display_configuration *pp_display_cfg); + +uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context); + #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index 85a54d963f8d..9d4e7d8b836e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -31,6 +31,7 @@ #include "dce/dce_hwseq.h" #include "dce110/dce110_hw_sequencer.h" +#include "dce100/dce100_hw_sequencer.h" /* include DCE8 register header files */ #include "dce/dce_8_0_d.h" @@ -118,6 +119,7 @@ static void set_bandwidth( bool decrease_allowed) { dc->hwss.set_displaymarks(dc, context); + dce100_pplib_apply_display_requirements(dc, context); } -- cgit v1.2.3-59-g8ed1b From 632550d71fcf78d495cfd1d321427e634b662f23 Mon Sep 17 00:00:00 2001 From: Zeyu Fan Date: Mon, 3 Apr 2017 11:54:11 -0400 Subject: drm/amd/display: Fix hotspot programming during set cursor position. - Remove x,y hotspot from dc_cursor_attributes. Only program it through setPosition. Signed-off-by: Zeyu Fan Acked-by: Harry Wentland Reviewed-by: Zeyu Fan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 5 ----- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 ------- drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 11 ++++------- drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 15 ++++----------- 4 files changed, 8 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 4b0fc6b56969..58fda20f6b97 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -90,8 +90,6 @@ static void dm_set_cursor( attributes.address.low_part = lower_32_bits(gpu_addr); attributes.width = width; attributes.height = height; - attributes.x_hot = 0; - attributes.y_hot = 0; attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; attributes.rotation_angle = 0; attributes.attribute_flags.value = 0; @@ -118,7 +116,6 @@ static void dm_set_cursor( position.x = x; position.y = y; - position.hot_spot_enable = true; position.x_hotspot = xorigin; position.y_hotspot = yorigin; @@ -260,7 +257,6 @@ static int dm_crtc_cursor_set( position.enable = false; position.x = 0; position.y = 0; - position.hot_spot_enable = false; if (amdgpu_crtc->stream) { /*set cursor visible false*/ @@ -344,7 +340,6 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, position.x = x; position.y = y; - position.hot_spot_enable = true; position.x_hotspot = xorigin; position.y_hotspot = yorigin; diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 568b7f0569f8..b785dd7b3a97 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -395,11 +395,6 @@ struct dc_cursor_position { */ bool enable; - /* - * This parameter indicates whether cursor hot spot should be - * programmed - */ - bool hot_spot_enable; }; struct dc_cursor_mi_param { @@ -464,8 +459,6 @@ struct dc_cursor_attributes { /* Width and height should correspond to cursor surface width x heigh */ uint32_t width; uint32_t height; - uint32_t x_hot; - uint32_t y_hot; enum dc_cursor_color_format color_format; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c index 1cab12ba8447..5b230b17fc5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c @@ -86,11 +86,10 @@ void dce110_ipp_cursor_set_position( program_position(ipp110, position->x, position->y); - if (position->hot_spot_enable) - program_hotspot( - ipp110, - position->x_hotspot, - position->y_hotspot); + program_hotspot( + ipp110, + position->x_hotspot, + position->y_hotspot); /* unlock cursor registers */ lock(ipp110, false); @@ -111,8 +110,6 @@ bool dce110_ipp_cursor_set_attributes( attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); - /* Program hot spot coordinates */ - program_hotspot(ipp110, attributes->x_hot, attributes->y_hot); /* * Program cursor size -- NOTE: HW spec specifies that HW register diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c index d520b5d7aa81..15671fd2cb9c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c @@ -151,11 +151,10 @@ void dce120_ipp_cursor_set_position( CURSOR_X_POSITION, position->x, CURSOR_Y_POSITION, position->y); - if (position->hot_spot_enable) - DCP_REG_SET_2( - DCP0_CUR_HOT_SPOT, - CURSOR_HOT_SPOT_X, position->x_hotspot, - CURSOR_HOT_SPOT_Y, position->y_hotspot); + DCP_REG_SET_2( + DCP0_CUR_HOT_SPOT, + CURSOR_HOT_SPOT_X, position->x_hotspot, + CURSOR_HOT_SPOT_Y, position->y_hotspot); /* unlock cursor registers */ lock(ipp110, false); @@ -176,12 +175,6 @@ bool dce120_ipp_cursor_set_attributes( attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); - /* Program hot spot coordinates */ - DCP_REG_SET_2( - DCP0_CUR_HOT_SPOT, - CURSOR_HOT_SPOT_X, attributes->x_hot, - CURSOR_HOT_SPOT_Y, attributes->y_hot); - /* * Program cursor size -- NOTE: HW spec specifies that HW register * stores size as (height - 1, width - 1) -- cgit v1.2.3-59-g8ed1b From 313bf4ff0180107b687dbd10dde8fd021247cd37 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 6 Apr 2017 16:21:58 -0400 Subject: drm/amd/display: Add same check as reset pipes for programing backend regs. Signed-off-by: Yongqiang Sun Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 839c34409c63..7430be502efd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1689,6 +1689,10 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->stream == pipe_ctx_old->stream) continue; + if (pipe_ctx->stream && pipe_ctx_old->stream + && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + continue; + if (pipe_ctx->top_pipe) continue; -- cgit v1.2.3-59-g8ed1b From 1ce71fcd5dddf4a3198a96e422122edc210847e9 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Tue, 11 Apr 2017 22:24:44 -0400 Subject: drm/amd/display: use full surface update when stream is NULL Signed-off-by: Charlene Liu Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 70dc02cf4dbb..6576137ee189 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1155,7 +1155,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; - if (stream_status->surface_count != surface_count) + if (stream_status == NULL || stream_status->surface_count != surface_count) return UPDATE_TYPE_FULL; if (stream_update) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7430be502efd..1401331080c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1599,11 +1599,11 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); if (context->dispclk_khz - > dc->current_context->dispclk_khz) + > dc->current_context->dispclk_khz) { context->res_ctx.pool->display_clock->funcs->set_clock( context->res_ctx.pool->display_clock, context->dispclk_khz * 115 / 100); - + } /* program audio wall clock. use HDMI as clock source if HDMI * audio active. Otherwise, use DP as clock source * first, loop to find any HDMI audio, if not, loop find DP audio -- cgit v1.2.3-59-g8ed1b From 81c509633aa93442d58b895f773892b3e8d936cf Mon Sep 17 00:00:00 2001 From: Sylvia Tsai Date: Tue, 11 Apr 2017 15:15:28 -0400 Subject: drm/amd/display: Parse scanline registers They could differ between ASIC generations Signed-off-by: Sylvia Tsai Signed-off-by: Harry Wentland Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 21 ++++++--- drivers/gpu/drm/amd/display/dc/dc.h | 7 ++- .../display/dc/dce110/dce110_timing_generator.c | 54 ++++++++++------------ .../display/dc/dce110/dce110_timing_generator.h | 8 ++-- .../display/dc/dce120/dce120_timing_generator.c | 42 ++++++++--------- .../drm/amd/display/dc/inc/hw/timing_generator.h | 8 ++-- 7 files changed, 89 insertions(+), 66 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 93f10bc772c4..84995a48ec61 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -103,6 +103,8 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, u32 *vbl, u32 *position) { + uint32_t v_blank_start, v_blank_end, h_position, v_position; + if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) return -EINVAL; else { @@ -113,7 +115,18 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, return 0; } - return dc_stream_get_scanoutpos(acrtc->stream, vbl, position); + /* + * TODO rework base driver to use values directly. + * for now parse it back into reg-format + */ + dc_stream_get_scanoutpos(acrtc->stream, + &v_blank_start, + &v_blank_end, + &h_position, + &v_position); + + *position = (v_position) || (h_position << 16); + *vbl = (v_blank_start) || (v_blank_end << 16); } return 0; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index bf209f7bbf98..3dbd6c0885d8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -282,12 +282,14 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) return 0; } -uint32_t dc_stream_get_scanoutpos( - const struct dc_stream *dc_stream, - uint32_t *vbl, - uint32_t *position) +bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position) { uint8_t i; + bool ret = false; struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = @@ -299,10 +301,17 @@ uint32_t dc_stream_get_scanoutpos( if (res_ctx->pipe_ctx[i].stream != stream) continue; - return tg->funcs->get_scanoutpos(tg, vbl, position); + tg->funcs->get_scanoutpos(tg, + v_blank_start, + v_blank_end, + h_position, + v_position); + + ret = true; + break; } - return 0; + return ret; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 97af8f63eec3..7d548b4d0299 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -484,8 +484,11 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -uint32_t dc_stream_get_scanoutpos( - const struct dc_stream *stream, uint32_t *vbl, uint32_t *position); +bool dc_stream_get_scanoutpos(const struct dc_stream *stream, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); /* * Structure to store surface/stream associations for validation diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 006412be7a02..7070aaf9e433 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -574,29 +574,26 @@ void dce110_timing_generator_get_crtc_positions( * @param [out] vpos, hpos ***************************************************************************** */ -uint32_t dce110_timing_generator_get_crtc_scanoutpos( +void dce110_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position) + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - /* TODO 1: Update the implementation once caller is updated - * WARNING!! This function is returning the whole register value - * because the caller is expecting it instead of proper vertical and - * horizontal position. This should be a temporary implementation - * until the caller is updated. */ - /* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */ - - *vbl = dm_read_reg(tg->ctx, + uint32_t v_blank_start_end = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_V_BLANK_START_END)); - *position = dm_read_reg(tg->ctx, - CRTC_REG(mmCRTC_STATUS_POSITION)); + *v_blank_start = get_reg_field_value(v_blank_start_end, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + *v_blank_end = get_reg_field_value(v_blank_start_end, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_END); - /* @TODO: return value should indicate if current - * crtc is inside vblank*/ - return 0; + dce110_timing_generator_get_crtc_positions(tg, h_position, v_position); } /* TODO: is it safe to assume that mask/shift of Primary and Underlay @@ -1875,34 +1872,31 @@ void dce110_tg_set_colors(struct timing_generator *tg, bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - uint32_t vbl = 0; + uint32_t v_blank_start = 0; + uint32_t v_blank_end = 0; uint32_t val = 0; - uint32_t position, vbl_start; + uint32_t h_position, v_position; tg->funcs->get_scanoutpos( tg, - &vbl, - &position); + &v_blank_start, + &v_blank_end, + &h_position, + &v_position); - if (vbl == 0) + if (v_blank_start == 0 || v_blank_end == 0) return false; - vbl_start = - get_reg_field_value( - vbl, - CRTC_V_BLANK_START_END, - CRTC_V_BLANK_START); - set_reg_field_value( val, - vbl_start, + v_blank_start, CRTC_VERTICAL_INTERRUPT0_POSITION, CRTC_VERTICAL_INTERRUPT0_LINE_START); - /* Set interaval width for interrupt to fire to 1 scanline */ + /* Set interval width for interrupt to fire to 1 scanline */ set_reg_field_value( val, - vbl_start + width, + v_blank_start + width, CRTC_VERTICAL_INTERRUPT0_POSITION, CRTC_VERTICAL_INTERRUPT0_LINE_END); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index ca387b40fc67..f14a4d91cd8e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -230,10 +230,12 @@ void dce110_timing_generator_set_static_screen_control( struct timing_generator *tg, uint32_t value); -uint32_t dce110_timing_generator_get_crtc_scanoutpos( +void dce110_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position); + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); void dce110_timing_generator_enable_advanced_request( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 95cb1768aeb5..1318df7ed47e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -576,24 +576,28 @@ void dce120_timing_generator_set_drr( } } -uint32_t dce120_timing_generator_get_crtc_scanoutpos( +void dce120_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position) + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - *vbl = dm_read_reg_soc15( + uint32_t v_blank_start_end = dm_read_reg_soc15( tg->ctx, mmCRTC0_CRTC_V_BLANK_START_END, tg110->offsets.crtc); - *position = dm_read_reg_soc15( - tg->ctx, - mmCRTC0_CRTC_STATUS_POSITION, - tg110->offsets.crtc); + *v_blank_start = get_reg_field_value(v_blank_start_end, + CRTC0_CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + *v_blank_end = get_reg_field_value(v_blank_start_end, + CRTC0_CRTC_V_BLANK_START_END, + CRTC_V_BLANK_END); - return 0; + dce120_timing_generator_get_crtc_positions(tg, h_position, v_position); } void dce120_timing_generator_enable_advanced_request( @@ -1044,26 +1048,22 @@ static bool dce120_arm_vert_intr( uint8_t width) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - uint32_t vbl, position, vbl_start; + uint32_t v_blank_start, v_blank_end, h_position, v_position; tg->funcs->get_scanoutpos( tg, - &vbl, - &position); + &v_blank_start, + &v_blank_end, + &h_position, + &v_position); - if (vbl == 0) + if (v_blank_start == 0 || v_blank_end == 0) return false; - vbl_start = - get_reg_field_value( - vbl, - CRTC0_CRTC_V_BLANK_START_END, - CRTC_V_BLANK_START); - CRTC_REG_SET_2( CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION, - CRTC_VERTICAL_INTERRUPT0_LINE_START, vbl_start, - CRTC_VERTICAL_INTERRUPT0_LINE_END, vbl_start + width); + CRTC_VERTICAL_INTERRUPT0_LINE_START, v_blank_start, + CRTC_VERTICAL_INTERRUPT0_LINE_END, v_blank_start + width); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 51902a4f8798..b3deaf2d8173 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -120,10 +120,12 @@ struct timing_generator_funcs { int32_t *h_position, int32_t *v_position); uint32_t (*get_frame_count)(struct timing_generator *tg); - uint32_t (*get_scanoutpos)( + void (*get_scanoutpos)( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position); + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); void (*set_early_control)(struct timing_generator *tg, uint32_t early_cntl); void (*wait_for_state)(struct timing_generator *tg, -- cgit v1.2.3-59-g8ed1b From ab3c179893fd44953008d1b1442973ecb1bb5c7e Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Fri, 31 Mar 2017 15:25:04 -0500 Subject: drm/amd/display: Add support for programming stereo sync Signed-off-by: Vitaly Prosyak Acked-by: Harry Wentland Reviewed-by: Charlene Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 11 ++++++++--- drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h | 14 ++++++++++++-- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 +++++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 +++++ drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 5 +++++ 6 files changed, 49 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index 03ce9ba50b64..e5045d21a05c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -174,7 +174,8 @@ enum dce110_opp_reg_type { OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ - OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ @@ -182,7 +183,8 @@ enum dce110_opp_reg_type { OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ - OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ @@ -195,7 +197,8 @@ enum dce110_opp_reg_type { OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ - OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ @@ -244,6 +247,7 @@ enum dce110_opp_reg_type { OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ @@ -308,6 +312,7 @@ enum dce110_opp_reg_type { type FMT_RGB_RANDOM_ENABLE; \ type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ + type FMT_STEREOSYNC_OVERRIDE; \ type FMT_RAND_R_SEED; \ type FMT_RAND_G_SEED; \ type FMT_RAND_B_SEED; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index f3e1a293351f..9713def6e481 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -1286,6 +1286,17 @@ void dce110_se_hdmi_audio_disable( dce110_se_enable_audio_clock(enc, false); } + +static void setup_stereo_sync( + struct stream_encoder *enc, + int tg_inst, bool enable) +{ + struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); + REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); + REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); +} + + static const struct stream_encoder_funcs dce110_str_enc_funcs = { .dp_set_stream_attribute = dce110_stream_encoder_dp_set_stream_attribute, @@ -1316,6 +1327,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = { .hdmi_audio_setup = dce110_se_hdmi_audio_setup, .hdmi_audio_disable = dce110_se_hdmi_audio_disable, + .setup_stereo_sync = setup_stereo_sync, }; bool dce110_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index c2f4050fc6dc..850e12a8db61 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -151,6 +151,8 @@ SE_SF(DP_VID_N, DP_VID_N, mask_sh),\ SE_SF(DP_VID_M, DP_VID_M, mask_sh),\ SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\ + SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ + SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ @@ -265,7 +267,9 @@ SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) + SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh) #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) @@ -281,7 +285,9 @@ SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ - SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) + SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ + SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh) #define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ @@ -416,6 +422,8 @@ struct dce_stream_encoder_shift { uint8_t AFMT_AUDIO_CLOCK_EN; uint8_t TMDS_PIXEL_ENCODING; uint8_t TMDS_COLOR_FORMAT; + uint8_t DIG_STEREOSYNC_SELECT; + uint8_t DIG_STEREOSYNC_GATE_EN; uint8_t DP_DB_DISABLE; uint8_t DP_MSA_MISC0; uint8_t DP_MSA_HTOTAL; @@ -543,6 +551,8 @@ struct dce_stream_encoder_mask { uint32_t AFMT_AUDIO_SAMPLE_SEND; uint32_t AFMT_AUDIO_CLOCK_EN; uint32_t TMDS_PIXEL_ENCODING; + uint32_t DIG_STEREOSYNC_SELECT; + uint32_t DIG_STEREOSYNC_GATE_EN; uint32_t TMDS_COLOR_FORMAT; uint32_t DP_DB_DISABLE; uint32_t DP_MSA_MISC0; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1401331080c5..6bf03d680314 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1056,6 +1056,13 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->sink->link->link_enc, pipe_ctx->stream->signal); + if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) + pipe_ctx->stream_enc->funcs->setup_stereo_sync( + pipe_ctx->stream_enc, + pipe_ctx->tg->inst, + stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); + + /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ pipe_ctx->opp->funcs->opp_program_fmt( pipe_ctx->opp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index e01b831a7e7f..521bd21eb5df 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -316,6 +316,11 @@ struct opp_funcs { struct hw_adjustment_range *range); void (*opp_destroy)(struct output_pixel_processor **opp); + + void (*opp_set_stereo_polarity)( + struct output_pixel_processor *opp, + bool enable, + bool rightEyePolarity); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 674bebfe3bd2..9fb27bd360ac 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -118,6 +118,11 @@ struct stream_encoder_funcs { void (*hdmi_audio_disable) ( struct stream_encoder *enc); + + void (*setup_stereo_sync) ( + struct stream_encoder *enc, + int tg_inst, + bool enable); }; #endif /* STREAM_ENCODER_H_ */ -- cgit v1.2.3-59-g8ed1b From 2180e7cca4d5b93b9f150a83d83e27b7fb82a72f Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 17 Apr 2017 11:39:19 -0400 Subject: drm/amd/display: update dce8 & 10 bw programming Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Jordan Lazare Signed-off-by: Alex Deucher --- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 28 +++++++++++----------- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 7 +++--- .../drm/amd/display/dc/dce100/dce100_resource.c | 1 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +-- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 19 +-------------- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ---- 6 files changed, 21 insertions(+), 41 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index f11044e0245c..dd6f0b1bd8ae 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -28,6 +28,8 @@ #include "core_types.h" #include "hw_sequencer.h" #include "dce100_hw_sequencer.h" +#include "resource.h" + #include "dce110/dce110_hw_sequencer.h" /* include DCE10 register header files */ @@ -104,7 +106,7 @@ static bool dce100_enable_display_power_gating( return false; } -void dce100_pplib_apply_display_requirements( +static void dce100_pplib_apply_display_requirements( struct core_dc *dc, struct validate_context *context) { @@ -112,6 +114,8 @@ void dce100_pplib_apply_display_requirements( pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); + pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk + / MEMORY_TYPE_MULTIPLIER; dce110_fill_display_configs(context, pp_display_cfg); @@ -122,20 +126,18 @@ void dce100_pplib_apply_display_requirements( dc->prev_display_config = *pp_display_cfg; } - - -static void set_displaymarks( - const struct core_dc *dc, struct validate_context *context) -{ - /* Do nothing until we have proper bandwitdth calcs */ -} - -static void set_bandwidth( +void dce100_set_bandwidth( struct core_dc *dc, struct validate_context *context, bool decrease_allowed) { - dc->hwss.set_displaymarks(dc, context); + if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { + context->res_ctx.pool->display_clock->funcs->set_clock( + context->res_ctx.pool->display_clock, + context->dispclk_khz * 115 / 100); + dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; + dc->current_context->dispclk_khz = context->dispclk_khz; + } dce100_pplib_apply_display_requirements(dc, context); } @@ -146,10 +148,8 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc) { dce110_hw_sequencer_construct(dc); - /* TODO: dce80 is empty implementation at the moment*/ dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; - dc->hwss.set_displaymarks = set_displaymarks; - dc->hwss.set_bandwidth = set_bandwidth; + dc->hwss.set_bandwidth = dce100_set_bandwidth; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index f51d04a66a49..24433f0e770b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -33,9 +33,10 @@ struct validate_context; bool dce100_hw_sequencer_construct(struct core_dc *dc); -void dce100_pplib_apply_display_requirements( - struct core_dc *dc, - struct validate_context *context); +void dce100_set_bandwidth( + struct core_dc *dc, + struct validate_context *context, + bool decrease_allowed); #endif /* __DC_HWSS_DCE100_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 7fae8537e18a..9b365597cec5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -771,6 +771,7 @@ bool dce100_validate_bandwidth( { /* TODO implement when needed but for now hardcode max value*/ context->dispclk_khz = 681000; + context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6bf03d680314..2fbf6ddcf3be 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2266,7 +2266,7 @@ static void dce110_set_bandwidth( struct validate_context *context, bool decrease_allowed) { - dc->hwss.set_displaymarks(dc, context); + dce110_set_displaymarks(dc, context); if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { context->res_ctx.pool->display_clock->funcs->set_clock( @@ -2468,7 +2468,6 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_display_power_gating = dce110_enable_display_power_gating, .power_down_front_end = dce110_power_down_fe, .pipe_control_lock = dce_pipe_control_lock, - .set_displaymarks = dce110_set_displaymarks, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, .set_static_screen_control = set_static_screen_control, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index 9d4e7d8b836e..4cba80ff6ca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -107,30 +107,13 @@ static bool dce80_enable_display_power_gating( return false; } -static void set_displaymarks( - const struct core_dc *dc, struct validate_context *context) -{ - /* Do nothing until we have proper bandwitdth calcs */ -} - -static void set_bandwidth( - struct core_dc *dc, - struct validate_context *context, - bool decrease_allowed) -{ - dc->hwss.set_displaymarks(dc, context); - dce100_pplib_apply_display_requirements(dc, context); -} - - bool dce80_hw_sequencer_construct(struct core_dc *dc) { dce110_hw_sequencer_construct(dc); dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating; dc->hwss.pipe_control_lock = dce_pipe_control_lock; - dc->hwss.set_displaymarks = set_displaymarks; - dc->hwss.set_bandwidth = set_bandwidth; + dc->hwss.set_bandwidth = dce100_set_bandwidth; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 077dc7573c52..9bfaaad09bea 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -123,10 +123,6 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe, bool lock); - void (*set_displaymarks)( - const struct core_dc *dc, - struct validate_context *context); - void (*set_bandwidth)( struct core_dc *dc, struct validate_context *context, -- cgit v1.2.3-59-g8ed1b From 974db151d48b6793fc2b708d1c3f9ceee735fc5a Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 18 Apr 2017 16:51:39 -0400 Subject: drm/amd/display: remove unnecessary allocation for regamma_params inside opp Signed-off-by: Dmytro Laktyushkin Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 10 +--------- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 4 ---- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 2 +- 4 files changed, 5 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 121ccbb1ad2d..f716a9e8784e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -987,10 +987,6 @@ bool dce110_opp_construct(struct dce110_opp *opp110, opp110->base.inst = inst; - opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params)); - if (opp110->base.regamma_params == NULL) - return false; - opp110->regs = regs; opp110->opp_shift = opp_shift; opp110->opp_mask = opp_mask; @@ -1000,12 +996,8 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp) { - if (*opp) { - if ((*opp)->regamma_params) - dm_free((*opp)->regamma_params); - (*opp)->regamma_params = NULL; + if (*opp) dm_free(FROM_DCE11_OPP(*opp)); - } *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2fbf6ddcf3be..6b249f5bf1da 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -637,7 +637,7 @@ static bool dce110_set_output_transfer_func( struct output_pixel_processor *opp = pipe_ctx->opp; opp->funcs->opp_power_on_regamma_lut(opp, true); - opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; + opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->public.out_transfer_func && stream->public.out_transfer_func->type == @@ -646,8 +646,8 @@ static bool dce110_set_output_transfer_func( TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->public.out_transfer_func, opp->regamma_params)) { - opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params); + stream->public.out_transfer_func, &opp->regamma_params)) { + opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 95b3d2eb8428..6f8b414cabbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -56,10 +56,6 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110, opp110->base.ctx = ctx; - opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params)); - if (opp110->base.regamma_params == NULL) - return false; - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 521bd21eb5df..92c99c3b9002 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -203,7 +203,7 @@ enum opp_regamma { struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; - struct pwl_params *regamma_params; + struct pwl_params regamma_params; const struct opp_funcs *funcs; }; -- cgit v1.2.3-59-g8ed1b From d4e745e3dbf43ad14759615d0236f6378db1ad4a Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 18 Apr 2017 15:35:27 -0400 Subject: drm/amd/display: set correct v_total_min and v_total_max for dce. Signed-off-by: Yongqiang Sun Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 7070aaf9e433..69ae3a83d2fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -393,12 +393,12 @@ void dce110_timing_generator_set_drr( params->vertical_total_min > 0) { set_reg_field_value(v_total_max, - params->vertical_total_max - 1, + params->vertical_total_max, CRTC_V_TOTAL_MAX, CRTC_V_TOTAL_MAX); set_reg_field_value(v_total_min, - params->vertical_total_min - 1, + params->vertical_total_min, CRTC_V_TOTAL_MIN, CRTC_V_TOTAL_MIN); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 1318df7ed47e..6e3e7b6bc58c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -540,10 +540,10 @@ void dce120_timing_generator_set_drr( CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL_MIN, - CRTC_V_TOTAL_MIN, params->vertical_total_min - 1); + CRTC_V_TOTAL_MIN, params->vertical_total_min); CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL_MAX, - CRTC_V_TOTAL_MAX, params->vertical_total_max - 1); + CRTC_V_TOTAL_MAX, params->vertical_total_max); CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 6, FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1, FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1, -- cgit v1.2.3-59-g8ed1b From 6c626ffb1bfa2705e71376fe20bcdc6b89aace85 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 21 Apr 2017 11:00:43 -0400 Subject: drm/amd/display: Make sure v_total_min and max not less than v_total. Signed-off-by: Yongqiang Sun Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 4 ++-- .../gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 4 ++-- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 12 ++++++++++++ 3 files changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 69ae3a83d2fe..7070aaf9e433 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -393,12 +393,12 @@ void dce110_timing_generator_set_drr( params->vertical_total_min > 0) { set_reg_field_value(v_total_max, - params->vertical_total_max, + params->vertical_total_max - 1, CRTC_V_TOTAL_MAX, CRTC_V_TOTAL_MAX); set_reg_field_value(v_total_min, - params->vertical_total_min, + params->vertical_total_min - 1, CRTC_V_TOTAL_MIN, CRTC_V_TOTAL_MIN); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 6e3e7b6bc58c..1318df7ed47e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -540,10 +540,10 @@ void dce120_timing_generator_set_drr( CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL_MIN, - CRTC_V_TOTAL_MIN, params->vertical_total_min); + CRTC_V_TOTAL_MIN, params->vertical_total_min - 1); CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL_MAX, - CRTC_V_TOTAL_MAX, params->vertical_total_max); + CRTC_V_TOTAL_MAX, params->vertical_total_max - 1); CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 6, FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1, FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 94566c0a0e62..5c6de723da5d 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -347,6 +347,7 @@ static void calc_vmin_vmax(struct core_freesync *core_freesync, { unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0; unsigned int index = map_index_from_stream(core_freesync, stream); + uint32_t vtotal = stream->timing.v_total; min_frame_duration_in_ns = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), @@ -362,6 +363,17 @@ static void calc_vmin_vmax(struct core_freesync *core_freesync, *vmin = div64_u64(div64_u64(((unsigned long long)( min_frame_duration_in_ns) * stream->timing.pix_clk_khz), stream->timing.h_total), 1000000); + + /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ + if (*vmin < vtotal) { + ASSERT(false); + *vmin = vtotal; + } + + if (*vmax < vtotal) { + ASSERT(false); + *vmax = vtotal; + } } static void calc_v_total_from_duration(const struct dc_stream *stream, -- cgit v1.2.3-59-g8ed1b From beb16b6a0f921f66472e4946a4955f07942fa9d8 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 21 Apr 2017 09:34:09 -0400 Subject: drm/amd/display: improve cursor programming reliability This change will cache cursor attributes and reprogram them when enabling cursor after power gating if the attributes were not yet reprogrammed Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 55 ++++++++++------------ drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 2 +- .../drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 4 +- drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 2 +- .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 4 +- 7 files changed, 32 insertions(+), 41 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 3dbd6c0885d8..23627b14c16c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -182,7 +182,6 @@ bool dc_stream_set_cursor_attributes( struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - bool ret = false; if (NULL == dc_stream) { dm_error("DC: dc_stream is NULL!\n"); @@ -200,28 +199,26 @@ bool dc_stream_set_cursor_attributes( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if ((pipe_ctx->stream == stream) && - (pipe_ctx->ipp != NULL)) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; + if (pipe_ctx->stream != stream || !pipe_ctx->ipp) + continue; + if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + continue; - if (ipp->funcs->ipp_cursor_set_attributes( - ipp, attributes)) - ret = true; - } + pipe_ctx->ipp->funcs->ipp_cursor_set_attributes( + pipe_ctx->ipp, attributes); } - return ret; + return true; } bool dc_stream_set_cursor_position( const struct dc_stream *dc_stream, - struct dc_cursor_position *position) + const struct dc_cursor_position *position) { int i; struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - bool ret = false; if (NULL == dc_stream) { dm_error("DC: dc_stream is NULL!\n"); @@ -239,27 +236,27 @@ bool dc_stream_set_cursor_position( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct dc_cursor_position pos_cpy = *position; + struct dc_cursor_mi_param param = { + .pixel_clk_khz = dc_stream->timing.pix_clk_khz, + .ref_clk_khz = res_ctx->pool->ref_clock_inKhz, + .viewport_x_start = pipe_ctx->scl_data.viewport.x, + .viewport_width = pipe_ctx->scl_data.viewport.width, + .h_scale_ratio = pipe_ctx->scl_data.ratios.horz + }; + + if (pipe_ctx->stream != stream || + !pipe_ctx->ipp || !pipe_ctx->surface) + continue; - if (pipe_ctx->stream == stream && - pipe_ctx->ipp && pipe_ctx->surface) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_cursor_mi_param param = { - .pixel_clk_khz = dc_stream->timing.pix_clk_khz, - .ref_clk_khz = res_ctx->pool->ref_clock_inKhz, - .viewport_x_start = pipe_ctx->scl_data.viewport.x, - .viewport_width = pipe_ctx->scl_data.viewport.width, - .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, - }; - - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) - position->enable = false; - - ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m); - ret = true; - } + if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + pos_cpy.enable = false; + + ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); } - return ret; + return true; } uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d35fa01024f8..5629e3ca6336 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -764,7 +764,7 @@ bool dc_stream_set_cursor_attributes( bool dc_stream_set_cursor_position( const struct dc_stream *stream, - struct dc_cursor_position *position); + const struct dc_cursor_position *position); /* Newer interfaces */ struct dc_cursor { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h index a374ef2c9d0b..434fe2f5a9d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h @@ -54,7 +54,7 @@ void dce110_ipp_cursor_set_position( const struct dc_cursor_position *position, const struct dc_cursor_mi_param *param); -bool dce110_ipp_cursor_set_attributes( +void dce110_ipp_cursor_set_attributes( struct input_pixel_processor *ipp, const struct dc_cursor_attributes *attributes); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c index 5b230b17fc5c..f712916563b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c @@ -95,7 +95,7 @@ void dce110_ipp_cursor_set_position( lock(ipp110, false); } -bool dce110_ipp_cursor_set_attributes( +void dce110_ipp_cursor_set_attributes( struct input_pixel_processor *ipp, const struct dc_cursor_attributes *attributes) { @@ -122,8 +122,6 @@ bool dce110_ipp_cursor_set_attributes( /* Unlock Cursor registers. */ lock(ipp110, false); - - return true; } static void enable( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h index 4b326bcb4600..7f645fde7064 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h @@ -42,7 +42,7 @@ void dce120_ipp_cursor_set_position( const struct dc_cursor_position *position, const struct dc_cursor_mi_param *param); -bool dce120_ipp_cursor_set_attributes( +void dce120_ipp_cursor_set_attributes( struct input_pixel_processor *ipp, const struct dc_cursor_attributes *attributes); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c index 15671fd2cb9c..dc81d320f6e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c @@ -160,7 +160,7 @@ void dce120_ipp_cursor_set_position( lock(ipp110, false); } -bool dce120_ipp_cursor_set_attributes( +void dce120_ipp_cursor_set_attributes( struct input_pixel_processor *ipp, const struct dc_cursor_attributes *attributes) { @@ -189,7 +189,5 @@ bool dce120_ipp_cursor_set_attributes( /* Unlock Cursor registers. */ lock(ipp110, false); - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 0457bc7a44d4..7928e230eefb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -37,8 +37,6 @@ struct input_pixel_processor { struct dc_context *ctx; unsigned int inst; const struct ipp_funcs *funcs; - - unsigned int cusor_width; }; enum ipp_prescale_mode { @@ -88,7 +86,7 @@ struct ipp_funcs { const struct dc_cursor_position *position, const struct dc_cursor_mi_param *param); - bool (*ipp_cursor_set_attributes)( + void (*ipp_cursor_set_attributes)( struct input_pixel_processor *ipp, const struct dc_cursor_attributes *attributes); -- cgit v1.2.3-59-g8ed1b From 94267b3df7ee00f21fa0ff7d618ca7e0574db5ed Mon Sep 17 00:00:00 2001 From: Sylvia Tsai Date: Fri, 21 Apr 2017 15:29:55 -0400 Subject: drm/amd/display: PSR Refactor - Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by: Sylvia Tsai Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 74 +++++++++------------- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++---- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 53 +--------------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 17 +++-- drivers/gpu/drm/amd/display/dc/dc_types.h | 24 +++---- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 +++++- .../display/dc/dce110/dce110_timing_generator.c | 16 ----- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 14 +++- 11 files changed, 93 insertions(+), 150 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1dd9c736aedc..93c936d92f5a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -199,6 +199,32 @@ static bool set_gamut_remap(struct dc *dc, return ret; } +static void set_static_screen_events(struct dc *dc, + const struct dc_stream **stream, + int num_streams, + const struct dc_static_screen_events *events) +{ + struct core_dc *core_dc = DC_TO_CORE(dc); + int i = 0; + int j = 0; + struct pipe_ctx *pipes_affected[MAX_PIPES]; + int num_pipes_affected = 0; + + for (i = 0; i < num_streams; i++) { + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]); + + for (j = 0; j < MAX_PIPES; j++) { + if (core_dc->current_context->res_ctx.pipe_ctx[j].stream + == core_stream) { + pipes_affected[num_pipes_affected++] = + &core_dc->current_context->res_ctx.pipe_ctx[j]; + } + } + } + + core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); +} + /* This function is not expected to fail, proper implementation of * validation will prevent this from ever being called for unsupported * configurations. @@ -240,45 +266,6 @@ static void stream_update_scaling( } } -static bool set_psr_enable(struct dc *dc, bool enable) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - int i; - - for (i = 0; i < core_dc->link_count; i++) - dc_link_set_psr_enable(&core_dc->links[i]->public, - enable); - - return true; -} - - -static bool setup_psr(struct dc *dc, const struct dc_stream *stream) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - struct pipe_ctx *pipes; - int i; - unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; - - for (i = 0; i < core_dc->link_count; i++) { - if (core_stream->sink->link == core_dc->links[i]) - dc_link_setup_psr(&core_dc->links[i]->public, - stream); - } - - for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream && i != underlay_idx) { - pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; - core_dc->hwss.set_static_screen_control(&pipes, 1, - 0x182); - } - } - - return true; -} - static void set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link) @@ -359,15 +346,12 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) stream_adjust_vmin_vmax; } + core_dc->public.stream_funcs.set_static_screen_events = + set_static_screen_events; + core_dc->public.stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->public.stream_funcs.set_psr_enable = - set_psr_enable; - - core_dc->public.stream_funcs.setup_psr = - setup_psr; - core_dc->public.link_funcs.set_drive_settings = set_drive_settings; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 426f7f8187a6..6f78403e2d64 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1430,14 +1430,14 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) struct core_dc *core_dc = DC_TO_CORE(ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; - if (dmcu != NULL && dc_link->psr_caps.psr_version > 0) + if (dmcu != NULL && link->psr_enabled) dmcu->funcs->set_psr_enable(dmcu, enable); return true; } bool dc_link_setup_psr(const struct dc_link *dc_link, - const struct dc_stream *stream) + const struct dc_stream *stream, struct psr_config *psr_config) { struct core_link *link = DC_LINK_TO_CORE(dc_link); struct dc_context *ctx = link->ctx; @@ -1449,10 +1449,8 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, psr_context.controllerId = CONTROLLER_ID_UNDEFINED; - if (dc_link != NULL && - dmcu != NULL && - dc_link->psr_caps.psr_version > 0) { + dmcu != NULL) { /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; @@ -1461,10 +1459,10 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, psr_configuration.bits.ENABLE = 1; psr_configuration.bits.CRC_VERIFICATION = 1; psr_configuration.bits.FRAME_CAPTURE_INDICATION = - dc_link->psr_caps.psr_frame_capture_indication_req; + psr_config->psr_frame_capture_indication_req; /* Check for PSR v2*/ - if (dc_link->psr_caps.psr_version == 0x2) { + if (psr_config->psr_version == 0x2) { /* For PSR v2 selective update. * Indicates whether sink should start capturing * immediately following active scan line, @@ -1512,14 +1510,13 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, stream->timing.v_total), stream->timing.h_total); - psr_context.psrSupportedDisplayConfig = - (dc_link->psr_caps.psr_version > 0) ? true : false; + psr_context.psrSupportedDisplayConfig = true; psr_context.psrExitLinkTrainingRequired = - dc_link->psr_caps.psr_exit_link_training_required; + psr_config->psr_exit_link_training_required; psr_context.sdpTransmitLineNumDeadline = - dc_link->psr_caps.psr_sdp_transmit_line_num_deadline; + psr_config->psr_sdp_transmit_line_num_deadline; psr_context.psrFrameCaptureIndicationReq = - dc_link->psr_caps.psr_frame_capture_indication_req; + psr_config->psr_frame_capture_indication_req; psr_context.skipPsrWaitForPllLock = 0; /* only = 1 in KV */ @@ -1550,6 +1547,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, */ psr_context.frame_delay = 0; + link->psr_enabled = true; dmcu->funcs->setup_psr(dmcu, link, &psr_context); return true; } else diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 17286465e850..f883fdb820c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1478,7 +1478,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) { union dpcd_psr_configuration psr_configuration; - if (link->public.psr_caps.psr_version == 0) + if (!link->psr_enabled) return false; dm_helpers_dp_read_dpcd( @@ -2060,36 +2060,6 @@ static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data, link->wa_flags.dp_keep_receiver_powered = false; } -static void retrieve_psr_link_cap(struct core_link *link, - enum edp_revision edp_revision) -{ - if (edp_revision >= EDP_REVISION_13) { - core_link_read_dpcd(link, - DP_PSR_SUPPORT, - (uint8_t *)(&link->public.psr_caps), - sizeof(link->public.psr_caps)); - if (link->public.psr_caps.psr_version != 0) { - unsigned char psr_capability = 0; - - core_link_read_dpcd(link, - DP_PSR_CAPS, - &psr_capability, - sizeof(psr_capability)); - /* Bit 0 determines whether fast link training is - * required on PSR exit. If set to 0, link training - * is required. If set to 1, sink must lock within - * five Idle Patterns after Main Link is turned on. - */ - link->public.psr_caps.psr_exit_link_training_required - = !(psr_capability & 0x1); - - psr_capability = (psr_capability >> 1) & 0x7; - link->public.psr_caps.psr_rfb_setup_time = - 55 * (6 - psr_capability); - } - } -} - static void retrieve_link_cap(struct core_link *link) { uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1]; @@ -2157,38 +2127,17 @@ static void retrieve_link_cap(struct core_link *link) link->dpcd_caps.panel_mode_edp = edp_config_cap.bits.ALT_SCRAMBLER_RESET; - link->edp_revision = EDP_REVISION_11; - link->public.test_pattern_enabled = false; link->public.compliance_test_state.raw = 0; - link->public.psr_caps.psr_exit_link_training_required = false; - link->public.psr_caps.psr_frame_capture_indication_req = false; - link->public.psr_caps.psr_rfb_setup_time = 0; - link->public.psr_caps.psr_sdp_transmit_line_num_deadline = 0; - link->public.psr_caps.psr_version = 0; - /* read sink count */ core_link_read_dpcd(link, DP_SINK_COUNT, &link->dpcd_caps.sink_count.raw, sizeof(link->dpcd_caps.sink_count.raw)); - /* Display control registers starting at DPCD 700h are only valid and - * enabled if this eDP config cap bit is set. */ - if (edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE) { - /* Read the Panel's eDP revision at DPCD 700h. */ - core_link_read_dpcd(link, - DP_EDP_DPCD_REV, - (uint8_t *)(&link->edp_revision), - sizeof(link->edp_revision)); - } - /* Connectivity log: detection */ CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); - - /* TODO: Confirm if need retrieve_psr_link_cap */ - retrieve_psr_link_cap(link, link->edp_revision); } void detect_dp_sink_caps(struct core_link *link) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2e12a0ba5ddf..cdb98d5f7caa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2015,7 +2015,7 @@ static void set_vsc_info_packet( unsigned int vscPacketRevision = 0; unsigned int i; - if (stream->sink->link->public.psr_caps.psr_version != 0) { + if (stream->sink->link->psr_enabled) { vscPacketRevision = 2; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a2a9e4ed393c..d12aa726164e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -82,6 +82,12 @@ struct dc_surface_dcc_cap { }; }; +struct dc_static_screen_events { + bool cursor_update; + bool surface_update; + bool overlay_update; +}; + /* Forward declaration*/ struct dc; struct dc_surface; @@ -102,10 +108,14 @@ struct dc_stream_funcs { const struct dc_stream *dc_stream, const struct rect *src, const struct rect *dst); + bool (*set_gamut_remap)(struct dc *dc, const struct dc_stream **stream, int num_streams); - bool (*set_psr_enable)(struct dc *dc, bool enable); - bool (*setup_psr)(struct dc *dc, const struct dc_stream *stream); + + void (*set_static_screen_events)(struct dc *dc, + const struct dc_stream **stream, + int num_streams, + const struct dc_static_screen_events *events); }; struct link_training_settings; @@ -604,7 +614,6 @@ struct dc_link { uint8_t ddc_hw_inst; uint8_t link_enc_hw_inst; - struct psr_caps psr_caps; bool test_pattern_enabled; union compliance_test_state compliance_test_state; @@ -657,7 +666,7 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_setup_psr(const struct dc_link *dc_link, - const struct dc_stream *stream); + const struct dc_stream *stream, struct psr_config *psr_config); /* Request DC to detect if there is a Panel connected. * boot - If this call is during initial boot. diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2ba02b50bc18..d2f3b9fd7a30 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -484,6 +484,15 @@ struct freesync_context { unsigned int nominal_refresh_in_micro_hz; }; +struct psr_config { + unsigned char psr_version; + unsigned int psr_rfb_setup_time; + bool psr_exit_link_training_required; + + bool psr_frame_capture_indication_req; + unsigned int psr_sdp_transmit_line_num_deadline; +}; + struct colorspace_transform { struct fixed31_32 matrix[12]; bool enable_remap; @@ -494,21 +503,6 @@ struct csc_transform { bool enable_adjustment; }; -struct psr_caps { - /* These parameters are from PSR capabilities reported by Sink DPCD */ - unsigned char psr_version; - unsigned int psr_rfb_setup_time; - bool psr_exit_link_training_required; - - /* These parameters are calculated in Driver, - * based on display timing and Sink capabilities. - * If VBLANK region is too small and Sink takes a long time - * to set up RFB, it may take an extra frame to enter PSR state. - */ - bool psr_frame_capture_indication_req; - unsigned int psr_sdp_transmit_line_num_deadline; -}; - enum i2c_mot_mode { I2C_MOT_UNDEF, I2C_MOT_TRUE, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6b249f5bf1da..6a93c96b9b26 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1005,6 +1005,10 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( pipe_ctx->tg, &stream->public.timing, true); + + pipe_ctx->tg->funcs->set_static_screen_control( + pipe_ctx->tg, + 0x182); } if (!pipe_ctx_old->stream) { @@ -1015,6 +1019,8 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( } } + + return DC_OK; } @@ -1114,6 +1120,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->public.timing.pix_clk_khz, context->stream_count); + pipe_ctx->stream->sink->link->psr_enabled = false; + return DC_OK; } @@ -1355,9 +1363,17 @@ static void set_drr(struct pipe_ctx **pipe_ctx, } static void set_static_screen_control(struct pipe_ctx **pipe_ctx, - int num_pipes, int value) + int num_pipes, const struct dc_static_screen_events *events) { unsigned int i; + unsigned int value = 0; + + if (events->overlay_update) + value |= 0x100; + if (events->surface_update) + value |= 0x80; + if (events->cursor_update) + value |= 0x2; for (i = 0; i < num_pipes; i++) pipe_ctx[i]->tg->funcs-> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 7070aaf9e433..23760727f000 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -371,7 +371,6 @@ void dce110_timing_generator_set_drr( uint32_t v_total_min = 0; uint32_t v_total_max = 0; uint32_t v_total_cntl = 0; - uint32_t static_screen_cntl = 0; struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t addr = 0; @@ -385,9 +384,6 @@ void dce110_timing_generator_set_drr( addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL); v_total_cntl = dm_read_reg(tg->ctx, addr); - addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); - static_screen_cntl = dm_read_reg(tg->ctx, addr); - if (params != NULL && params->vertical_total_max > 0 && params->vertical_total_min > 0) { @@ -430,20 +426,11 @@ void dce110_timing_generator_set_drr( 0, CRTC_V_TOTAL_CONTROL, CRTC_SET_V_TOTAL_MIN_MASK); - - set_reg_field_value(static_screen_cntl, - 0x180, - CRTC_STATIC_SCREEN_CONTROL, - CRTC_STATIC_SCREEN_EVENT_MASK); } else { set_reg_field_value(v_total_cntl, 0, CRTC_V_TOTAL_CONTROL, CRTC_SET_V_TOTAL_MIN_MASK); - set_reg_field_value(static_screen_cntl, - 0, - CRTC_STATIC_SCREEN_CONTROL, - CRTC_STATIC_SCREEN_EVENT_MASK); set_reg_field_value(v_total_min, 0, CRTC_V_TOTAL_MIN, @@ -478,9 +465,6 @@ void dce110_timing_generator_set_drr( addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL); dm_write_reg(tg->ctx, addr, v_total_cntl); - - addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); - dm_write_reg(tg->ctx, addr, static_screen_cntl); } void dce110_timing_generator_set_static_screen_control( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 405608318ccc..2b43e18c65f5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -156,6 +156,7 @@ struct core_link { unsigned int dpcd_sink_count; enum edp_revision edp_revision; + bool psr_enabled; /* MST record stream using this link */ struct link_flags { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 9bfaaad09bea..b42e4a0ef18a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -132,7 +132,7 @@ struct hw_sequencer_funcs { int vmin, int vmax); void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, - int num_pipes, int value); + int num_pipes, const struct dc_static_screen_events *events); enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 5c6de723da5d..78b4f28d862c 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -264,10 +264,10 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, enable_for_video = false; } - temp = core_stream->public.timing.pix_clk_khz; + temp = stream->timing.pix_clk_khz; temp *= 1000ULL * 1000ULL * 1000ULL; - temp = div_u64(temp, core_stream->public.timing.h_total); - temp = div_u64(temp, core_stream->public.timing.v_total); + temp = div_u64(temp, stream->timing.h_total); + temp = div_u64(temp, stream->timing.v_total); nom_refresh_rate_micro_hz = (unsigned int) temp; @@ -657,6 +657,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, unsigned int min_frame_duration_in_ns, vmax, vmin = 0; struct freesync_state *state; struct core_freesync *core_freesync = NULL; + struct dc_static_screen_events triggers = {0}; if (mod_freesync == NULL) return; @@ -749,6 +750,13 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, core_freesync->dc, streams, num_streams, v_total, v_total); + + triggers.overlay_update = true; + triggers.surface_update = true; + + core_freesync->dc->stream_funcs.set_static_screen_events( + core_freesync->dc, streams, num_streams, + &triggers); } } -- cgit v1.2.3-59-g8ed1b From 86b6a203b966ea54e3225b49e53769cf4c116905 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 24 Apr 2017 15:20:24 -0400 Subject: drm/amd/display: dce120 to dce ipp refactor Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 252 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h | 226 ++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 2 +- .../drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 4 +- drivers/gpu/drm/amd/display/dc/dce120/Makefile | 1 - drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 ----- drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 ----- .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 193 ---------------- .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 -------------- .../drm/amd/display/dc/dce120/dce120_resource.c | 69 +++--- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 3 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 5 +- 14 files changed, 521 insertions(+), 525 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 05562553b656..8abec0bed379 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -7,7 +7,7 @@ DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ -dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o +dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c new file mode 100644 index 000000000000..d6bf6067a309 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -0,0 +1,252 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce_ipp.h" +#include "reg_helper.h" +#include "dm_services.h" + +#define REG(reg) \ + (ipp_dce->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name + +#define CTX \ + ipp_dce->base.ctx + +static void dce_ipp_cursor_set_position( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position, + const struct dc_cursor_mi_param *param) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + + /* lock cursor registers */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); + + /* Flag passed in structure differentiates cursor enable/disable. */ + /* Update if it differs from cached state. */ + REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); + + REG_SET_2(CUR_POSITION, 0, + CURSOR_X_POSITION, position->x, + CURSOR_Y_POSITION, position->y); + + REG_SET_2(CUR_HOT_SPOT, 0, + CURSOR_HOT_SPOT_X, position->x_hotspot, + CURSOR_HOT_SPOT_Y, position->y_hotspot); + + /* unlock cursor registers */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); +} + +static void dce_ipp_cursor_set_attributes( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + int mode; + + /* Lock cursor registers */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); + + /* Program cursor control */ + switch (attributes->color_format) { + case CURSOR_MODE_MONO: + mode = 0; + break; + case CURSOR_MODE_COLOR_1BIT_AND: + mode = 1; + break; + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: + mode = 2; + break; + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: + mode = 3; + break; + default: + BREAK_TO_DEBUGGER(); /* unsupported */ + mode = 0; + } + + REG_UPDATE_3(CUR_CONTROL, + CURSOR_MODE, mode, + CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, + CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); + + if (attributes->color_format == CURSOR_MODE_MONO) { + REG_SET_3(CUR_COLOR1, 0, + CUR_COLOR1_BLUE, 0, + CUR_COLOR1_GREEN, 0, + CUR_COLOR1_RED, 0); + + REG_SET_3(CUR_COLOR2, 0, + CUR_COLOR2_BLUE, 0xff, + CUR_COLOR2_GREEN, 0xff, + CUR_COLOR2_RED, 0xff); + } + + /* + * Program cursor size -- NOTE: HW spec specifies that HW register + * stores size as (height - 1, width - 1) + */ + REG_SET_2(CUR_SIZE, 0, + CURSOR_WIDTH, attributes->width-1, + CURSOR_HEIGHT, attributes->height-1); + + /* Program cursor surface address */ + /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor + * surface base address in byte. It is 4K byte aligned. + * The correct way to program cursor surface address is to first write + * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS + */ + REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, + CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part); + + REG_SET(CUR_SURFACE_ADDRESS, 0, + CURSOR_SURFACE_ADDRESS, attributes->address.low_part); + + /* Unlock Cursor registers. */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); +} + +static void dce_ipp_program_prescale( + struct input_pixel_processor *ipp, + struct ipp_prescale_params *params) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + + /* set to bypass mode first before change */ + REG_UPDATE(PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS, + 1); + + REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, + GRPH_PRESCALE_SCALE_R, params->scale, + GRPH_PRESCALE_BIAS_R, params->bias); + + REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, + GRPH_PRESCALE_SCALE_G, params->scale, + GRPH_PRESCALE_BIAS_G, params->bias); + + REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, + GRPH_PRESCALE_SCALE_B, params->scale, + GRPH_PRESCALE_BIAS_B, params->bias); + + if (params->mode != IPP_PRESCALE_MODE_BYPASS) { + REG_UPDATE(PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS, 0); + + /* If prescale is in use, then legacy lut should be bypassed */ + REG_UPDATE(INPUT_GAMMA_CONTROL, + GRPH_INPUT_GAMMA_MODE, 1); + } +} + +static void dce_ipp_program_input_lut( + struct input_pixel_processor *ipp, + const struct dc_gamma *gamma) +{ + int i; + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + + /* power on LUT memory */ + REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); + + /* enable all */ + REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); + + /* 256 entry mode */ + REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); + + /* LUT-256, unsigned, integer, new u0.12 format */ + REG_SET_3(DC_LUT_CONTROL, 0, + DC_LUT_DATA_R_FORMAT, 3, + DC_LUT_DATA_G_FORMAT, 3, + DC_LUT_DATA_B_FORMAT, 3); + + /* start from index 0 */ + REG_SET(DC_LUT_RW_INDEX, 0, + DC_LUT_RW_INDEX, 0); + + for (i = 0; i < INPUT_LUT_ENTRIES; i++) { + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->red[i]); + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->green[i]); + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->blue[i]); + } + + /* power off LUT memory */ + REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); + + /* bypass prescale, enable legacy LUT */ + REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); + REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); +} + +static void dce_ipp_set_degamma( + struct input_pixel_processor *ipp, + enum ipp_degamma_mode mode) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; + + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || + mode == IPP_DEGAMMA_MODE_HW_sRGB); + + REG_SET_3(DEGAMMA_CONTROL, 0, + GRPH_DEGAMMA_MODE, degamma_type, + CURSOR_DEGAMMA_MODE, degamma_type, + CURSOR2_DEGAMMA_MODE, degamma_type); +} + +static const struct ipp_funcs dce_ipp_funcs = { + .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, + .ipp_cursor_set_position = dce_ipp_cursor_set_position, + .ipp_program_prescale = dce_ipp_program_prescale, + .ipp_program_input_lut = dce_ipp_program_input_lut, + .ipp_set_degamma = dce_ipp_set_degamma +}; + +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +void dce_ipp_construct( + struct dce_ipp *ipp_dce, + struct dc_context *ctx, + int inst, + const struct dce_ipp_registers *regs, + const struct dce_ipp_shift *ipp_shift, + const struct dce_ipp_mask *ipp_mask) +{ + ipp_dce->base.ctx = ctx; + ipp_dce->base.inst = inst; + ipp_dce->base.funcs = &dce_ipp_funcs; + + ipp_dce->regs = regs; + ipp_dce->ipp_shift = ipp_shift; + ipp_dce->ipp_mask = ipp_mask; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h new file mode 100644 index 000000000000..23f25b1b0e64 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h @@ -0,0 +1,226 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCE_DCE_IPP_H_ +#define _DCE_DCE_IPP_H_ + +#include "ipp.h" + +#define TO_DCE_IPP(ipp)\ + container_of(ipp, struct dce_ipp, base) + +#define IPP_COMMON_REG_LIST_DCE_BASE(id) \ + SRI(CUR_UPDATE, DCP, id), \ + SRI(CUR_CONTROL, DCP, id), \ + SRI(CUR_POSITION, DCP, id), \ + SRI(CUR_HOT_SPOT, DCP, id), \ + SRI(CUR_COLOR1, DCP, id), \ + SRI(CUR_COLOR2, DCP, id), \ + SRI(CUR_SIZE, DCP, id), \ + SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \ + SRI(CUR_SURFACE_ADDRESS, DCP, id), \ + SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ + SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \ + SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ + SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ + SRI(INPUT_GAMMA_CONTROL, DCP, id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ + SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ + SRI(DC_LUT_RW_MODE, DCP, id), \ + SRI(DC_LUT_CONTROL, DCP, id), \ + SRI(DC_LUT_RW_INDEX, DCP, id), \ + SRI(DC_LUT_SEQ_COLOR, DCP, id), \ + SRI(DEGAMMA_CONTROL, DCP, id) + +#define IPP_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ + IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ + IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ + IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ + IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ + IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ + IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ + IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ + IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ + IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ + IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ + IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \ + IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ + IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ + IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ + IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ + IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ + IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ + IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ + IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ + IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ + IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ + IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ + IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) + +#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ + IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ + IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ + IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ + IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \ + IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ + IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ + IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ + IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ + IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ + IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ + IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ + IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ + IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ + IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ + IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ + IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) + +#define IPP_REG_FIELD_LIST(type) \ + type CURSOR_UPDATE_LOCK; \ + type CURSOR_EN; \ + type CURSOR_X_POSITION; \ + type CURSOR_Y_POSITION; \ + type CURSOR_HOT_SPOT_X; \ + type CURSOR_HOT_SPOT_Y; \ + type CURSOR_MODE; \ + type CURSOR_2X_MAGNIFY; \ + type CUR_INV_TRANS_CLAMP; \ + type CUR_COLOR1_BLUE; \ + type CUR_COLOR1_GREEN; \ + type CUR_COLOR1_RED; \ + type CUR_COLOR2_BLUE; \ + type CUR_COLOR2_GREEN; \ + type CUR_COLOR2_RED; \ + type CURSOR_WIDTH; \ + type CURSOR_HEIGHT; \ + type CURSOR_SURFACE_ADDRESS_HIGH; \ + type CURSOR_SURFACE_ADDRESS; \ + type GRPH_PRESCALE_BYPASS; \ + type GRPH_PRESCALE_SCALE_R; \ + type GRPH_PRESCALE_BIAS_R; \ + type GRPH_PRESCALE_SCALE_G; \ + type GRPH_PRESCALE_BIAS_G; \ + type GRPH_PRESCALE_SCALE_B; \ + type GRPH_PRESCALE_BIAS_B; \ + type GRPH_INPUT_GAMMA_MODE; \ + type DCP_LUT_MEM_PWR_DIS; \ + type DC_LUT_WRITE_EN_MASK; \ + type DC_LUT_RW_MODE; \ + type DC_LUT_DATA_R_FORMAT; \ + type DC_LUT_DATA_G_FORMAT; \ + type DC_LUT_DATA_B_FORMAT; \ + type DC_LUT_RW_INDEX; \ + type DC_LUT_SEQ_COLOR; \ + type GRPH_DEGAMMA_MODE; \ + type CURSOR_DEGAMMA_MODE; \ + type CURSOR2_DEGAMMA_MODE + +struct dce_ipp_shift { + IPP_REG_FIELD_LIST(uint8_t); +}; + +struct dce_ipp_mask { + IPP_REG_FIELD_LIST(uint32_t); +}; + +struct dce_ipp_registers { + uint32_t CUR_UPDATE; + uint32_t CUR_CONTROL; + uint32_t CUR_POSITION; + uint32_t CUR_HOT_SPOT; + uint32_t CUR_COLOR1; + uint32_t CUR_COLOR2; + uint32_t CUR_SIZE; + uint32_t CUR_SURFACE_ADDRESS_HIGH; + uint32_t CUR_SURFACE_ADDRESS; + uint32_t PRESCALE_GRPH_CONTROL; + uint32_t PRESCALE_VALUES_GRPH_R; + uint32_t PRESCALE_VALUES_GRPH_G; + uint32_t PRESCALE_VALUES_GRPH_B; + uint32_t INPUT_GAMMA_CONTROL; + uint32_t DCFE_MEM_PWR_CTRL; + uint32_t DC_LUT_WRITE_EN_MASK; + uint32_t DC_LUT_RW_MODE; + uint32_t DC_LUT_CONTROL; + uint32_t DC_LUT_RW_INDEX; + uint32_t DC_LUT_SEQ_COLOR; + uint32_t DEGAMMA_CONTROL; +}; + +struct dce_ipp { + struct input_pixel_processor base; + const struct dce_ipp_registers *regs; + const struct dce_ipp_shift *ipp_shift; + const struct dce_ipp_mask *ipp_mask; +}; + +void dce_ipp_construct(struct dce_ipp *ipp_dce, + struct dc_context *ctx, + int inst, + const struct dce_ipp_registers *regs, + const struct dce_ipp_shift *ipp_shift, + const struct dce_ipp_mask *ipp_mask); + +#endif /* _DCE_DCE_IPP_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index da2a02434665..ca6c621151b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -369,7 +369,7 @@ struct dce_transform { bool prescaler_on; }; -bool dce_transform_construct(struct dce_transform *xfm110, +bool dce_transform_construct(struct dce_transform *xfm_dce, struct dc_context *ctx, uint32_t inst, const struct dce_transform_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h index 434fe2f5a9d7..8684e6a0ef4b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h @@ -59,7 +59,7 @@ void dce110_ipp_cursor_set_attributes( const struct dc_cursor_attributes *attributes); /* DEGAMMA RELATED */ -bool dce110_ipp_set_degamma( +void dce110_ipp_set_degamma( struct input_pixel_processor *ipp, enum ipp_degamma_mode mode); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c index f05cc9e981f3..0bcd8a68d5e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c @@ -66,7 +66,7 @@ -bool dce110_ipp_set_degamma( +void dce110_ipp_set_degamma( struct input_pixel_processor *ipp, enum ipp_degamma_mode mode) { @@ -82,8 +82,6 @@ bool dce110_ipp_set_degamma( GRPH_DEGAMMA_MODE, degamma_type, CURSOR_DEGAMMA_MODE, degamma_type, CURSOR2_DEGAMMA_MODE, degamma_type); - - return true; } void dce110_ipp_program_prescale( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile index 3c6b3fa98ddc..826c12ee368c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -4,7 +4,6 @@ DCE120 = dce120_resource.o dce120_timing_generator.o \ -dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \ dce120_mem_input.o dce120_hw_sequencer.o AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c deleted file mode 100644 index f4505690e01a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#include "dce120_ipp.h" - -static const struct ipp_funcs funcs = { - .ipp_cursor_set_attributes = dce120_ipp_cursor_set_attributes, - .ipp_cursor_set_position = dce120_ipp_cursor_set_position, - .ipp_program_prescale = dce120_ipp_program_prescale, - .ipp_program_input_lut = dce120_ipp_program_input_lut, - .ipp_set_degamma = dce120_ipp_set_degamma, -}; - -bool dce120_ipp_construct( - struct dce110_ipp *ipp, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) -{ - if (!dce110_ipp_construct(ipp, ctx, inst, offset)) { - ASSERT_CRITICAL(false); - return false; - } - - ipp->base.funcs = &funcs; - - return true; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h deleted file mode 100644 index 7f645fde7064..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_IPP_DCE120_H__ -#define __DC_IPP_DCE120_H__ - -#include "ipp.h" -#include "../dce110/dce110_ipp.h" - - -bool dce120_ipp_construct( - struct dce110_ipp *ipp, - struct dc_context *ctx, - enum controller_id id, - const struct dce110_ipp_reg_offsets *offset); - -/* CURSOR RELATED */ -void dce120_ipp_cursor_set_position( - struct input_pixel_processor *ipp, - const struct dc_cursor_position *position, - const struct dc_cursor_mi_param *param); - -void dce120_ipp_cursor_set_attributes( - struct input_pixel_processor *ipp, - const struct dc_cursor_attributes *attributes); - -/* DEGAMMA RELATED */ -bool dce120_ipp_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode); - -void dce120_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params); - -void dce120_ipp_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma); - -#endif /*__DC_IPP_DCE120_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c deleted file mode 100644 index dc81d320f6e5..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#include "../dce110/dce110_ipp.h" - - -#define DCP_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_UPDATE(reg, field, val) \ - DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define DCP_REG_SET(reg, field, val) \ - DCP_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ - DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -/* TODO: DAL3 does not implement cursor memory control - * MCIF_MEM_CONTROL, DMIF_CURSOR_MEM_CONTROL - */ -static void lock( - struct dce110_ipp *ipp110, bool lock) -{ - DCP_REG_UPDATE(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, lock); -} - -static bool program_control( - struct dce110_ipp *ipp110, - enum dc_cursor_color_format color_format, - bool enable_magnification, - bool inverse_transparent_clamping) -{ - uint32_t mode = 0; - - switch (color_format) { - case CURSOR_MODE_MONO: - mode = 0; - break; - case CURSOR_MODE_COLOR_1BIT_AND: - mode = 1; - break; - case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: - mode = 2; - break; - case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: - mode = 3; - break; - default: - return false; - } - - DCP_REG_UPDATE_3( - DCP0_CUR_CONTROL, - CURSOR_MODE, mode, - CURSOR_2X_MAGNIFY, enable_magnification, - CUR_INV_TRANS_CLAMP, inverse_transparent_clamping); - - if (color_format == CURSOR_MODE_MONO) { - DCP_REG_SET_3( - DCP0_CUR_COLOR1, - CUR_COLOR1_BLUE, 0, - CUR_COLOR1_GREEN, 0, - CUR_COLOR1_RED, 0); - - DCP_REG_SET_3( - DCP0_CUR_COLOR2, - CUR_COLOR2_BLUE, 0xff, - CUR_COLOR2_GREEN, 0xff, - CUR_COLOR2_RED, 0xff); - } - return true; -} - -static void program_address( - struct dce110_ipp *ipp110, - PHYSICAL_ADDRESS_LOC address) -{ - /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor - * surface base address in byte. It is 4K byte aligned. - * The correct way to program cursor surface address is to first write - * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS - */ - - DCP_REG_SET( - DCP0_CUR_SURFACE_ADDRESS_HIGH, - CURSOR_SURFACE_ADDRESS_HIGH, address.high_part); - - DCP_REG_SET( - DCP0_CUR_SURFACE_ADDRESS, - CURSOR_SURFACE_ADDRESS, address.low_part); -} - -void dce120_ipp_cursor_set_position( - struct input_pixel_processor *ipp, - const struct dc_cursor_position *position, - const struct dc_cursor_mi_param *param) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* lock cursor registers */ - lock(ipp110, true); - - /* Flag passed in structure differentiates cursor enable/disable. */ - /* Update if it differs from cached state. */ - DCP_REG_UPDATE(DCP0_CUR_CONTROL, CURSOR_EN, position->enable); - - DCP_REG_SET_2( - DCP0_CUR_POSITION, - CURSOR_X_POSITION, position->x, - CURSOR_Y_POSITION, position->y); - - DCP_REG_SET_2( - DCP0_CUR_HOT_SPOT, - CURSOR_HOT_SPOT_X, position->x_hotspot, - CURSOR_HOT_SPOT_Y, position->y_hotspot); - - /* unlock cursor registers */ - lock(ipp110, false); -} - -void dce120_ipp_cursor_set_attributes( - struct input_pixel_processor *ipp, - const struct dc_cursor_attributes *attributes) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - /* Lock cursor registers */ - lock(ipp110, true); - - /* Program cursor control */ - program_control( - ipp110, - attributes->color_format, - attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, - attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); - - /* - * Program cursor size -- NOTE: HW spec specifies that HW register - * stores size as (height - 1, width - 1) - */ - DCP_REG_SET_2( - DCP0_CUR_SIZE, - CURSOR_WIDTH, attributes->width-1, - CURSOR_HEIGHT, attributes->height-1); - - /* Program cursor surface address */ - program_address(ipp110, attributes->address); - - /* Unlock Cursor registers. */ - lock(ipp110, false); -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c deleted file mode 100644 index 7aa5a49c01e2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" -#include "include/fixed31_32.h" -#include "basics/conversion.h" - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#include "../dce110/dce110_ipp.h" - -#define DCP_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_UPDATE(reg, field, val) \ - DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define DCP_REG_SET(reg, field, val) \ - DCP_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ - DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - - -bool dce120_ipp_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; - - ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || - mode == IPP_DEGAMMA_MODE_HW_sRGB); - - DCP_REG_SET_3( - DCP0_DEGAMMA_CONTROL, - GRPH_DEGAMMA_MODE, degamma_type, - CURSOR_DEGAMMA_MODE, degamma_type, - CURSOR2_DEGAMMA_MODE, degamma_type); - - return true; -} - -void dce120_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* set to bypass mode first before change */ - DCP_REG_UPDATE( - DCP0_PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, - 1); - - DCP_REG_SET_2( - DCP0_PRESCALE_VALUES_GRPH_R, - GRPH_PRESCALE_SCALE_R, params->scale, - GRPH_PRESCALE_BIAS_R, params->bias); - - DCP_REG_SET_2( - DCP0_PRESCALE_VALUES_GRPH_G, - GRPH_PRESCALE_SCALE_G, params->scale, - GRPH_PRESCALE_BIAS_G, params->bias); - - DCP_REG_SET_2( - DCP0_PRESCALE_VALUES_GRPH_B, - GRPH_PRESCALE_SCALE_B, params->scale, - GRPH_PRESCALE_BIAS_B, params->bias); - - if (params->mode != IPP_PRESCALE_MODE_BYPASS) { - DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, 0); - - /* If prescale is in use, then legacy lut should be bypassed */ - DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE, 1); - } -} - -static void dce120_helper_select_lut(struct dce110_ipp *ipp110) -{ - /* enable all */ - DCP_REG_SET( - DCP0_DC_LUT_WRITE_EN_MASK, - DC_LUT_WRITE_EN_MASK, - 0x7); - - /* 256 entry mode */ - DCP_REG_UPDATE(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); - - /* LUT-256, unsigned, integer, new u0.12 format */ - DCP_REG_SET_3( - DCP0_DC_LUT_CONTROL, - DC_LUT_DATA_R_FORMAT, 3, - DC_LUT_DATA_G_FORMAT, 3, - DC_LUT_DATA_B_FORMAT, 3); - - /* start from index 0 */ - DCP_REG_SET( - DCP0_DC_LUT_RW_INDEX, - DC_LUT_RW_INDEX, - 0); -} - -void dce120_ipp_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma) -{ - int i; - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* power on LUT memory */ - DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1); - - dce120_helper_select_lut(ipp110); - - for (i = 0; i < INPUT_LUT_ENTRIES; i++) { - DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]); - DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]); - DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]); - } - - /* power off LUT memory */ - DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0); - - /* bypass prescale, enable legacy LUT */ - DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); - DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index f677a77ca6e0..207d07b29e81 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -40,7 +40,7 @@ #include "dce/dce_opp.h" #include "dce/dce_clock_source.h" #include "dce/dce_clocks.h" -#include "dce120_ipp.h" +#include "dce/dce_ipp.h" #include "dce110/dce110_mem_input.h" #include "dce120/dce120_mem_input.h" @@ -174,6 +174,28 @@ static const struct dce_abm_mask abm_mask = { ABM_MASK_SH_LIST_DCE110(_MASK) }; +#define ipp_regs(id)\ +[id] = {\ + IPP_COMMON_REG_LIST_DCE_BASE(id)\ +} + +static const struct dce_ipp_registers ipp_regs[] = { + ipp_regs(0), + ipp_regs(1), + ipp_regs(2), + ipp_regs(3), + ipp_regs(4), + ipp_regs(5) +}; + +static const struct dce_ipp_shift ipp_shift = { + IPP_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) +}; + +static const struct dce_ipp_mask ipp_mask = { + IPP_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -354,27 +376,6 @@ struct output_pixel_processor *dce120_opp_create( return NULL; } -static const struct dce110_ipp_reg_offsets dce120_ipp_reg_offsets[] = { - { - .dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL), - } -}; - static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = { { .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), @@ -498,7 +499,7 @@ static struct timing_generator *dce120_timing_generator_create( static void dce120_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCE110_IPP(*ipp)); + dm_free(TO_DCE_IPP(*ipp)); *ipp = NULL; } @@ -622,21 +623,18 @@ struct link_encoder *dce120_link_encoder_create( } static struct input_pixel_processor *dce120_ipp_create( - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) + struct dc_context *ctx, uint32_t inst) { - struct dce110_ipp *ipp = dm_alloc(sizeof(struct dce110_ipp)); + struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - if (!ipp) + if (!ipp) { + BREAK_TO_DEBUGGER(); return NULL; + } - if (dce120_ipp_construct(ipp, ctx, inst, offset)) - return &ipp->base; - - BREAK_TO_DEBUGGER(); - dm_free(ipp); - return NULL; + dce_ipp_construct(ipp, ctx, inst, + &ipp_regs[inst], &ipp_shift, &ipp_mask); + return &ipp->base; } static struct stream_encoder *dce120_stream_encoder_create( @@ -1025,8 +1023,7 @@ static bool construct( goto controller_create_fail; } - pool->base.ipps[i] = dce120_ipp_create(ctx, i, - &dce120_ipp_reg_offsets[i]); + pool->base.ipps[i] = dce120_ipp_create(ctx, i); if (pool->base.ipps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index dfe590198a33..907e0a9a8474 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -26,6 +26,9 @@ #ifndef __DAL_HW_SHARED_H__ #define __DAL_HW_SHARED_H__ +#include "os_types.h" +#include "fixed31_32.h" + /****************************************************************************** * Data types shared between different Virtual HW blocks ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 7928e230eefb..2f3dc2e7f17a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,6 +27,7 @@ #define __DAL_IPP_H__ #include "hw_shared.h" +#include "dc_hw_types.h" #define MAXTRIX_COEFFICIENTS_NUMBER 12 #define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4) @@ -113,7 +114,7 @@ struct ipp_funcs { const struct dc_gamma *gamma); /*** DEGAMMA RELATED ***/ - bool (*ipp_set_degamma)( + void (*ipp_set_degamma)( struct input_pixel_processor *ipp, enum ipp_degamma_mode mode); -- cgit v1.2.3-59-g8ed1b From e6303950ea7221e49cabb240383fa4e2bd035b0c Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 24 Apr 2017 16:30:58 -0400 Subject: drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 12 +- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h | 24 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 73 +++--- drivers/gpu/drm/amd/display/dc/dce110/Makefile | 4 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c | 63 ------ drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 74 ------ .../drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 249 --------------------- .../drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 159 ------------- .../drm/amd/display/dc/dce110/dce110_resource.c | 70 +++--- .../drm/amd/display/dc/dce112/dce112_resource.c | 81 +++---- .../drm/amd/display/dc/dce120/dce120_resource.c | 14 +- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c | 65 ------ drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h | 45 ---- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 84 ++++--- 15 files changed, 171 insertions(+), 848 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index d6bf6067a309..9e8f0a3593a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -174,7 +174,8 @@ static void dce_ipp_program_input_lut( struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); /* power on LUT memory */ - REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); + if (REG(DCFE_MEM_PWR_CTRL)) + REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); /* enable all */ REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); @@ -199,7 +200,8 @@ static void dce_ipp_program_input_lut( } /* power off LUT memory */ - REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); + if (REG(DCFE_MEM_PWR_CTRL)) + REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); /* bypass prescale, enable legacy LUT */ REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); @@ -250,3 +252,9 @@ void dce_ipp_construct( ipp_dce->ipp_shift = ipp_shift; ipp_dce->ipp_mask = ipp_mask; } + +void dce_ipp_destroy(struct input_pixel_processor **ipp) +{ + dm_free(TO_DCE_IPP(*ipp)); + *ipp = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h index 23f25b1b0e64..ca04e97d44c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h @@ -23,8 +23,8 @@ * */ -#ifndef _DCE_DCE_IPP_H_ -#define _DCE_DCE_IPP_H_ +#ifndef _DCE_IPP_H_ +#define _DCE_IPP_H_ #include "ipp.h" @@ -46,7 +46,6 @@ SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ SRI(INPUT_GAMMA_CONTROL, DCP, id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ SRI(DC_LUT_RW_MODE, DCP, id), \ SRI(DC_LUT_CONTROL, DCP, id), \ @@ -54,6 +53,14 @@ SRI(DC_LUT_SEQ_COLOR, DCP, id), \ SRI(DEGAMMA_CONTROL, DCP, id) +#define IPP_DCE100_REG_LIST_DCE_BASE(id) \ + IPP_COMMON_REG_LIST_DCE_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, CRTC, id) + +#define IPP_DCE110_REG_LIST_DCE_BASE(id) \ + IPP_COMMON_REG_LIST_DCE_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id) + #define IPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -85,7 +92,6 @@ IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ - IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ @@ -97,7 +103,11 @@ IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) -#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ +#define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh) + +#define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \ IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ @@ -223,4 +233,6 @@ void dce_ipp_construct(struct dce_ipp *ipp_dce, const struct dce_ipp_shift *ipp_shift, const struct dce_ipp_mask *ipp_mask); -#endif /* _DCE_DCE_IPP_H_ */ +void dce_ipp_destroy(struct input_pixel_processor **ipp); + +#endif /* _DCE_IPP_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 9b365597cec5..f65b785220e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -37,7 +37,7 @@ #include "dce/dce_stream_encoder.h" #include "dce110/dce110_mem_input.h" #include "dce110/dce110_mem_input_v.h" -#include "dce110/dce110_ipp.h" +#include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce/dce_opp.h" #include "dce/dce_clocks.h" @@ -168,30 +168,6 @@ static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = { } }; - -static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = { -{ - .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), -} -}; - - - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -213,6 +189,28 @@ static const struct dce_disp_clk_mask disp_clk_mask = { CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) }; +#define ipp_regs(id)\ +[id] = {\ + IPP_DCE100_REG_LIST_DCE_BASE(id)\ +} + +static const struct dce_ipp_registers ipp_regs[] = { + ipp_regs(0), + ipp_regs(1), + ipp_regs(2), + ipp_regs(3), + ipp_regs(4), + ipp_regs(5) +}; + +static const struct dce_ipp_shift ipp_shift = { + IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_ipp_mask ipp_mask = { + IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE100(id)\ @@ -563,22 +561,18 @@ static struct transform *dce100_transform_create( } static struct input_pixel_processor *dce100_ipp_create( - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offsets) + struct dc_context *ctx, uint32_t inst) { - struct dce110_ipp *ipp = - dm_alloc(sizeof(struct dce110_ipp)); + struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - if (!ipp) + if (!ipp) { + BREAK_TO_DEBUGGER(); return NULL; + } - if (dce110_ipp_construct(ipp, ctx, inst, offsets)) - return &ipp->base; - - BREAK_TO_DEBUGGER(); - dm_free(ipp); - return NULL; + dce_ipp_construct(ipp, ctx, inst, + &ipp_regs[inst], &ipp_shift, &ipp_mask); + return &ipp->base; } static const struct encoder_feature_support link_enc_feature = { @@ -674,7 +668,7 @@ static void destruct(struct dce110_resource_pool *pool) dce100_transform_destroy(&pool->base.transforms[i]); if (pool->base.ipps[i] != NULL) - dce110_ipp_destroy(&pool->base.ipps[i]); + dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); @@ -1005,8 +999,7 @@ static bool construct( goto res_create_fail; } - pool->base.ipps[i] = dce100_ipp_create(ctx, i, - &dce100_ipp_reg_offsets[i]); + pool->base.ipps[i] = dce100_ipp_create(ctx, i); if (pool->base.ipps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index 9c42afcac325..c54bf0330701 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -2,9 +2,7 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. -DCE110 = dce110_ipp.o dce110_ipp_cursor.o \ -dce110_ipp_gamma.o \ -dce110_timing_generator.o \ +DCE110 = dce110_timing_generator.o \ dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \ dce110_resource.o \ dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c deleted file mode 100644 index 86fa7657a756..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "dce110_ipp.h" - -static const struct ipp_funcs funcs = { - .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, - .ipp_cursor_set_position = dce110_ipp_cursor_set_position, - .ipp_program_prescale = dce110_ipp_program_prescale, - .ipp_program_input_lut = dce110_ipp_program_input_lut, - .ipp_set_degamma = dce110_ipp_set_degamma, -}; - -bool dce110_ipp_construct( - struct dce110_ipp* ipp, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) -{ - ipp->base.ctx = ctx; - - ipp->base.inst = inst; - - ipp->offsets = *offset; - - ipp->base.funcs = &funcs; - - return true; -} - -void dce110_ipp_destroy(struct input_pixel_processor **ipp) -{ - dm_free(TO_DCE110_IPP(*ipp)); - *ipp = NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h deleted file mode 100644 index 8684e6a0ef4b..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_IPP_DCE110_H__ -#define __DC_IPP_DCE110_H__ - -#include "ipp.h" - -#define TO_DCE110_IPP(input_pixel_processor)\ - container_of(input_pixel_processor, struct dce110_ipp, base) - -struct dce110_ipp_reg_offsets { - uint32_t dcp_offset; -}; - -struct dce110_ipp { - struct input_pixel_processor base; - struct dce110_ipp_reg_offsets offsets; -}; - -bool dce110_ipp_construct( - struct dce110_ipp* ipp, - struct dc_context *ctx, - enum controller_id id, - const struct dce110_ipp_reg_offsets *offset); - -void dce110_ipp_destroy(struct input_pixel_processor **ipp); - -/* CURSOR RELATED */ -void dce110_ipp_cursor_set_position( - struct input_pixel_processor *ipp, - const struct dc_cursor_position *position, - const struct dc_cursor_mi_param *param); - -void dce110_ipp_cursor_set_attributes( - struct input_pixel_processor *ipp, - const struct dc_cursor_attributes *attributes); - -/* DEGAMMA RELATED */ -void dce110_ipp_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode); - -void dce110_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params); - -void dce110_ipp_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma); - -#endif /*__DC_IPP_DCE110_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c deleted file mode 100644 index f712916563b9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "dce110_ipp.h" - -#define CURSOR_COLOR_BLACK 0x00000000 -#define CURSOR_COLOR_WHITE 0xFFFFFFFF - -#define DCP_REG(reg)\ - (reg + ipp110->offsets.dcp_offset) - -static void enable( - struct dce110_ipp *ipp110, - bool enable); - -static void lock( - struct dce110_ipp *ipp110, - bool enable); - -static void program_position( - struct dce110_ipp *ipp110, - uint32_t x, - uint32_t y); - -static bool program_control( - struct dce110_ipp *ipp110, - enum dc_cursor_color_format color_format, - bool enable_magnification, - bool inverse_transparent_clamping); - -static void program_hotspot( - struct dce110_ipp *ipp110, - uint32_t x, - uint32_t y); - -static void program_size( - struct dce110_ipp *ipp110, - uint32_t width, - uint32_t height); - -static void program_address( - struct dce110_ipp *ipp110, - PHYSICAL_ADDRESS_LOC address); - -void dce110_ipp_cursor_set_position( - struct input_pixel_processor *ipp, - const struct dc_cursor_position *position, - const struct dc_cursor_mi_param *param) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* lock cursor registers */ - lock(ipp110, true); - - /* Flag passed in structure differentiates cursor enable/disable. */ - /* Update if it differs from cached state. */ - enable(ipp110, position->enable); - - program_position(ipp110, position->x, position->y); - - program_hotspot( - ipp110, - position->x_hotspot, - position->y_hotspot); - - /* unlock cursor registers */ - lock(ipp110, false); -} - -void dce110_ipp_cursor_set_attributes( - struct input_pixel_processor *ipp, - const struct dc_cursor_attributes *attributes) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - /* Lock cursor registers */ - lock(ipp110, true); - - /* Program cursor control */ - program_control( - ipp110, - attributes->color_format, - attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, - attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); - - - /* - * Program cursor size -- NOTE: HW spec specifies that HW register - * stores size as (height - 1, width - 1) - */ - program_size(ipp110, attributes->width-1, attributes->height-1); - - /* Program cursor surface address */ - program_address(ipp110, attributes->address); - - /* Unlock Cursor registers. */ - lock(ipp110, false); -} - -static void enable( - struct dce110_ipp *ipp110, bool enable) -{ - uint32_t value = 0; - uint32_t addr = DCP_REG(mmCUR_CONTROL); - - value = dm_read_reg(ipp110->base.ctx, addr); - set_reg_field_value(value, enable, CUR_CONTROL, CURSOR_EN); - dm_write_reg(ipp110->base.ctx, addr, value); -} - -static void lock( - struct dce110_ipp *ipp110, bool lock) -{ - uint32_t value = 0; - uint32_t addr = DCP_REG(mmCUR_UPDATE); - - value = dm_read_reg(ipp110->base.ctx, addr); - set_reg_field_value(value, lock, CUR_UPDATE, CURSOR_UPDATE_LOCK); - dm_write_reg(ipp110->base.ctx, addr, value); -} - -static void program_position( - struct dce110_ipp *ipp110, - uint32_t x, - uint32_t y) -{ - uint32_t value = 0; - uint32_t addr = DCP_REG(mmCUR_POSITION); - - value = dm_read_reg(ipp110->base.ctx, addr); - set_reg_field_value(value, x, CUR_POSITION, CURSOR_X_POSITION); - set_reg_field_value(value, y, CUR_POSITION, CURSOR_Y_POSITION); - dm_write_reg(ipp110->base.ctx, addr, value); -} - -static bool program_control( - struct dce110_ipp *ipp110, - enum dc_cursor_color_format color_format, - bool enable_magnification, - bool inverse_transparent_clamping) -{ - uint32_t value = 0; - uint32_t addr = DCP_REG(mmCUR_CONTROL); - uint32_t mode = 0; - - switch (color_format) { - case CURSOR_MODE_MONO: - mode = 0; - break; - case CURSOR_MODE_COLOR_1BIT_AND: - mode = 1; - break; - case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: - mode = 2; - break; - case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: - mode = 3; - break; - default: - return false; - } - - set_reg_field_value(value, mode, CUR_CONTROL, CURSOR_MODE); - set_reg_field_value(value, enable_magnification, - CUR_CONTROL, CURSOR_2X_MAGNIFY); - set_reg_field_value(value, inverse_transparent_clamping, - CUR_CONTROL, CUR_INV_TRANS_CLAMP); - dm_write_reg(ipp110->base.ctx, addr, value); - - if (color_format == CURSOR_MODE_MONO) { - addr = DCP_REG(mmCUR_COLOR1); - dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_BLACK); - addr = DCP_REG(mmCUR_COLOR2); - dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_WHITE); - } - return true; -} - -static void program_hotspot( - struct dce110_ipp *ipp110, - uint32_t x, - uint32_t y) -{ - uint32_t value = 0; - uint32_t addr = DCP_REG(mmCUR_HOT_SPOT); - - value = dm_read_reg(ipp110->base.ctx, addr); - set_reg_field_value(value, x, CUR_HOT_SPOT, CURSOR_HOT_SPOT_X); - set_reg_field_value(value, y, CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y); - dm_write_reg(ipp110->base.ctx, addr, value); -} - -static void program_size( - struct dce110_ipp *ipp110, - uint32_t width, - uint32_t height) -{ - uint32_t value = 0; - uint32_t addr = DCP_REG(mmCUR_SIZE); - - value = dm_read_reg(ipp110->base.ctx, addr); - set_reg_field_value(value, width, CUR_SIZE, CURSOR_WIDTH); - set_reg_field_value(value, height, CUR_SIZE, CURSOR_HEIGHT); - dm_write_reg(ipp110->base.ctx, addr, value); -} - -static void program_address( - struct dce110_ipp *ipp110, - PHYSICAL_ADDRESS_LOC address) -{ - uint32_t addr = DCP_REG(mmCUR_SURFACE_ADDRESS_HIGH); - /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor - * surface base address in byte. It is 4K byte aligned. - * The correct way to program cursor surface address is to first write - * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS */ - - dm_write_reg(ipp110->base.ctx, addr, address.high_part); - - addr = DCP_REG(mmCUR_SURFACE_ADDRESS); - dm_write_reg(ipp110->base.ctx, addr, address.low_part); -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c deleted file mode 100644 index 0bcd8a68d5e5..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" -#include "include/fixed31_32.h" -#include "basics/conversion.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "dce110_ipp.h" - -#define DCP_REG(reg)\ - (mm##reg + ipp110->offsets.dcp_offset) - -#define DCP_REG_SET_N(reg_name, n, ...) \ - generic_reg_update_ex(ipp110->base.ctx, \ - DCP_REG(reg_name), \ - 0, n, __VA_ARGS__) - -#define DCP_REG_SET(reg, field1, val1) \ - DCP_REG_SET_N(reg, 1, FD(reg##__##field1), val1) - -#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ - DCP_REG_SET_N(reg, 2, \ - FD(reg##__##field1), val1, \ - FD(reg##__##field2), val2) - -#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_SET_N(reg, 3, \ - FD(reg##__##field1), val1, \ - FD(reg##__##field2), val2, \ - FD(reg##__##field3), val3) - -#define DCP_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_ex(ipp110->base.ctx, \ - DCP_REG(reg_name), \ - dm_read_reg(ipp110->base.ctx, DCP_REG(reg_name)), \ - n, __VA_ARGS__) - -#define DCP_REG_UPDATE(reg, field, val) \ - DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - - - -void dce110_ipp_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; - - ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || - mode == IPP_DEGAMMA_MODE_HW_sRGB); - - DCP_REG_SET_3( - DEGAMMA_CONTROL, - GRPH_DEGAMMA_MODE, degamma_type, - CURSOR_DEGAMMA_MODE, degamma_type, - CURSOR2_DEGAMMA_MODE, degamma_type); -} - -void dce110_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* set to bypass mode first before change */ - DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, 1); - - DCP_REG_SET_2(PRESCALE_VALUES_GRPH_R, - GRPH_PRESCALE_SCALE_R, params->scale, - GRPH_PRESCALE_BIAS_R, params->bias); - - DCP_REG_SET_2(PRESCALE_VALUES_GRPH_G, - GRPH_PRESCALE_SCALE_G, params->scale, - GRPH_PRESCALE_BIAS_G, params->bias); - - DCP_REG_SET_2(PRESCALE_VALUES_GRPH_B, - GRPH_PRESCALE_SCALE_B, params->scale, - GRPH_PRESCALE_BIAS_B, params->bias); - - if (params->mode != IPP_PRESCALE_MODE_BYPASS) { - /* If prescale is in use, then legacy lut should be bypassed */ - DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 0); - DCP_REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 1); - } -} - -static void dce110_helper_select_lut(struct dce110_ipp *ipp110) -{ - /* enable all */ - DCP_REG_SET(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, 0x7); - - /* 256 entry mode */ - DCP_REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); - - /* LUT-256, unsigned, integer, new u0.12 format */ - DCP_REG_SET_3(DC_LUT_CONTROL, - DC_LUT_DATA_R_FORMAT, 3, - DC_LUT_DATA_G_FORMAT, 3, - DC_LUT_DATA_B_FORMAT, 3); - - /* start from index 0 */ - DCP_REG_SET(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, 0); -} - -void dce110_ipp_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma) -{ - int i; - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - dce110_helper_select_lut(ipp110); - - /* power on LUT memory and give it time to settle */ - DCP_REG_SET(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1); - udelay(10); - - for (i = 0; i < INPUT_LUT_ENTRIES; i++) { - DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]); - DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]); - DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]); - } - - /* power off LUT memory */ - DCP_REG_SET(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0); - - /* bypass prescale, enable legacy LUT */ - DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); - DCP_REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index b4ab438e1c97..8dec9a5602a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -40,7 +40,7 @@ #include "dce/dce_stream_encoder.h" #include "dce110/dce110_mem_input.h" #include "dce110/dce110_mem_input_v.h" -#include "dce110/dce110_ipp.h" +#include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce110/dce110_transform_v.h" #include "dce/dce_opp.h" @@ -157,31 +157,6 @@ static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = { } }; - -static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = { -{ - .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), -} -}; - - - - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -226,6 +201,25 @@ static const struct dce_abm_mask abm_mask = { ABM_MASK_SH_LIST_DCE110(_MASK) }; +#define ipp_regs(id)\ +[id] = {\ + IPP_DCE110_REG_LIST_DCE_BASE(id)\ +} + +static const struct dce_ipp_registers ipp_regs[] = { + ipp_regs(0), + ipp_regs(1), + ipp_regs(2) +}; + +static const struct dce_ipp_shift ipp_shift = { + IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_ipp_mask ipp_mask = { + IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -578,22 +572,18 @@ static struct transform *dce110_transform_create( } static struct input_pixel_processor *dce110_ipp_create( - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offsets) + struct dc_context *ctx, uint32_t inst) { - struct dce110_ipp *ipp = - dm_alloc(sizeof(struct dce110_ipp)); + struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - if (!ipp) + if (!ipp) { + BREAK_TO_DEBUGGER(); return NULL; + } - if (dce110_ipp_construct(ipp, ctx, inst, offsets)) - return &ipp->base; - - BREAK_TO_DEBUGGER(); - dm_free(ipp); - return NULL; + dce_ipp_construct(ipp, ctx, inst, + &ipp_regs[inst], &ipp_shift, &ipp_mask); + return &ipp->base; } static const struct encoder_feature_support link_enc_feature = { @@ -705,7 +695,7 @@ static void destruct(struct dce110_resource_pool *pool) dce110_transform_destroy(&pool->base.transforms[i]); if (pool->base.ipps[i] != NULL) - dce110_ipp_destroy(&pool->base.ipps[i]); + dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); @@ -1414,7 +1404,7 @@ static bool construct( goto res_create_fail; } - pool->base.ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]); + pool->base.ipps[i] = dce110_ipp_create(ctx, i); if (pool->base.ipps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 0a1ad2808129..4bf75afd5721 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -40,7 +40,7 @@ #include "dce/dce_stream_encoder.h" #include "dce/dce_audio.h" #include "dce/dce_opp.h" -#include "dce110/dce110_ipp.h" +#include "dce/dce_ipp.h" #include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" @@ -177,28 +177,6 @@ static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets[] = { } }; -static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { -{ - .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), -} -}; - - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -244,6 +222,28 @@ static const struct dce_abm_mask abm_mask = { ABM_MASK_SH_LIST_DCE110(_MASK) }; +#define ipp_regs(id)\ +[id] = {\ + IPP_DCE110_REG_LIST_DCE_BASE(id)\ +} + +static const struct dce_ipp_registers ipp_regs[] = { + ipp_regs(0), + ipp_regs(1), + ipp_regs(2), + ipp_regs(3), + ipp_regs(4), + ipp_regs(5) +}; + +static const struct dce_ipp_shift ipp_shift = { + IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_ipp_mask ipp_mask = { + IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -627,29 +627,19 @@ struct link_encoder *dce112_link_encoder_create( return NULL; } -struct input_pixel_processor *dce112_ipp_create( - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) +static struct input_pixel_processor *dce112_ipp_create( + struct dc_context *ctx, uint32_t inst) { - struct dce110_ipp *ipp = - dm_alloc(sizeof(struct dce110_ipp)); + struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - if (!ipp) + if (!ipp) { + BREAK_TO_DEBUGGER(); return NULL; + } - if (dce110_ipp_construct(ipp, ctx, inst, offset)) - return &ipp->base; - - BREAK_TO_DEBUGGER(); - dm_free(ipp); - return NULL; -} - -void dce112_ipp_destroy(struct input_pixel_processor **ipp) -{ - dm_free(TO_DCE110_IPP(*ipp)); - *ipp = NULL; + dce_ipp_construct(ipp, ctx, inst, + &ipp_regs[inst], &ipp_shift, &ipp_mask); + return &ipp->base; } struct output_pixel_processor *dce112_opp_create( @@ -712,7 +702,7 @@ static void destruct(struct dce110_resource_pool *pool) dce112_transform_destroy(&pool->base.transforms[i]); if (pool->base.ipps[i] != NULL) - dce112_ipp_destroy(&pool->base.ipps[i]); + dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); @@ -1370,10 +1360,7 @@ static bool construct( goto res_create_fail; } - pool->base.ipps[i] = dce112_ipp_create( - ctx, - i, - &ipp_reg_offsets[i]); + pool->base.ipps[i] = dce112_ipp_create(ctx, i); if (pool->base.ipps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 207d07b29e81..b6bdd1d52922 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -176,7 +176,7 @@ static const struct dce_abm_mask abm_mask = { #define ipp_regs(id)\ [id] = {\ - IPP_COMMON_REG_LIST_DCE_BASE(id)\ + IPP_DCE110_REG_LIST_DCE_BASE(id)\ } static const struct dce_ipp_registers ipp_regs[] = { @@ -189,11 +189,11 @@ static const struct dce_ipp_registers ipp_regs[] = { }; static const struct dce_ipp_shift ipp_shift = { - IPP_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) + IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) }; static const struct dce_ipp_mask ipp_mask = { - IPP_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) + IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) }; #define transform_regs(id)\ @@ -497,12 +497,6 @@ static struct timing_generator *dce120_timing_generator_create( return NULL; } -static void dce120_ipp_destroy(struct input_pixel_processor **ipp) -{ - dm_free(TO_DCE_IPP(*ipp)); - *ipp = NULL; -} - static void dce120_transform_destroy(struct transform **xfm) { dm_free(TO_DCE_TRANSFORM(*xfm)); @@ -521,7 +515,7 @@ static void destruct(struct dce110_resource_pool *pool) dce120_transform_destroy(&pool->base.transforms[i]); if (pool->base.ipps[i] != NULL) - dce120_ipp_destroy(&pool->base.ipps[i]); + dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index 8d2c3dbfced1..1d54d5fa0fd2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -2,7 +2,7 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. -DCE80 = dce80_ipp.o dce80_timing_generator.o \ +DCE80 = dce80_timing_generator.o \ dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \ dce80_resource.o diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c deleted file mode 100644 index c195acb6e1a6..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "dce80_ipp.h" - -#include "dce110/dce110_ipp.h" - -static const struct ipp_funcs funcs = { - .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, - .ipp_cursor_set_position = dce110_ipp_cursor_set_position, - .ipp_program_prescale = dce110_ipp_program_prescale, - .ipp_program_input_lut = dce110_ipp_program_input_lut, - .ipp_set_degamma = dce110_ipp_set_degamma, -}; - -bool dce80_ipp_construct( - struct dce110_ipp *ipp, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) -{ - ipp->base.ctx = ctx; - - ipp->base.inst = inst; - - ipp->offsets = *offset; - - ipp->base.funcs = &funcs; - - return true; -} - -void dce80_ipp_destroy(struct input_pixel_processor **ipp) -{ - dm_free(TO_DCE80_IPP(*ipp)); - *ipp = NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h deleted file mode 100644 index 06e8598d395f..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_IPP_DCE80_H__ -#define __DC_IPP_DCE80_H__ - -#include "ipp.h" - -#define TO_DCE80_IPP(input_pixel_processor)\ - container_of(input_pixel_processor, struct dce110_ipp, base) - -struct dce110_ipp; -struct dce110_ipp_reg_offsets; - -bool dce80_ipp_construct( - struct dce110_ipp *ipp, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset); - -void dce80_ipp_destroy(struct input_pixel_processor **ipp); - -#endif /*__DC_IPP_DCE80_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index ab8cee3e734e..d49092986d54 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -41,10 +41,9 @@ #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" #include "dce80/dce80_mem_input.h" -#include "dce80/dce80_ipp.h" +#include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce/dce_opp.h" -#include "dce110/dce110_ipp.h" #include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" @@ -187,27 +186,6 @@ static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = { } }; -static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { -{ - .dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL), -}, -{ - .dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL), -} -}; - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -229,6 +207,28 @@ static const struct dce_disp_clk_mask disp_clk_mask = { CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) }; +#define ipp_regs(id)\ +[id] = {\ + IPP_COMMON_REG_LIST_DCE_BASE(id)\ +} + +static const struct dce_ipp_registers ipp_regs[] = { + ipp_regs(0), + ipp_regs(1), + ipp_regs(2), + ipp_regs(3), + ipp_regs(4), + ipp_regs(5) +}; + +static const struct dce_ipp_shift ipp_shift = { + IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) +}; + +static const struct dce_ipp_mask ipp_mask = { + IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE_BASE(id)\ @@ -592,25 +592,6 @@ static struct transform *dce80_transform_create( return NULL; } -static struct input_pixel_processor *dce80_ipp_create( - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) -{ - struct dce110_ipp *ipp = - dm_alloc(sizeof(struct dce110_ipp)); - - if (!ipp) - return NULL; - - if (dce80_ipp_construct(ipp, ctx, inst, offset)) - return &ipp->base; - - BREAK_TO_DEBUGGER(); - dm_free(ipp); - return NULL; -} - static const struct encoder_feature_support link_enc_feature = { .max_hdmi_deep_color = COLOR_DEPTH_121212, .max_hdmi_pixel_clock = 297000, @@ -673,6 +654,21 @@ void dce80_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } +static struct input_pixel_processor *dce80_ipp_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + + if (!ipp) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_ipp_construct(ipp, ctx, inst, + &ipp_regs[inst], &ipp_shift, &ipp_mask); + return &ipp->base; +} + static void destruct(struct dce110_resource_pool *pool) { unsigned int i; @@ -685,7 +681,7 @@ static void destruct(struct dce110_resource_pool *pool) dce80_transform_destroy(&pool->base.transforms[i]); if (pool->base.ipps[i] != NULL) - dce80_ipp_destroy(&pool->base.ipps[i]); + dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); @@ -1016,7 +1012,7 @@ static bool construct( goto res_create_fail; } - pool->base.ipps[i] = dce80_ipp_create(ctx, i, &ipp_reg_offsets[i]); + pool->base.ipps[i] = dce80_ipp_create(ctx, i); if (pool->base.ipps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create input pixel processor!\n"); -- cgit v1.2.3-59-g8ed1b From 72ada5f76939ed00c07c584be7691a29d3c2c3da Mon Sep 17 00:00:00 2001 From: Eric Cook Date: Tue, 18 Apr 2017 15:24:50 -0400 Subject: drm/amd/display: FreeSync Auto Sweep Support Implement core support to allow for FreeSync Auto Sweep to work Signed-off-by: Eric Cook Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 28 +++ drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 5 +- drivers/gpu/drm/amd/display/dc/dc.h | 6 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++ .../display/dc/dce110/dce110_timing_generator.c | 61 +++--- .../display/dc/dce110/dce110_timing_generator.h | 9 +- .../display/dc/dce110/dce110_timing_generator_v.c | 23 +-- .../display/dc/dce120/dce120_timing_generator.c | 73 ++++++- .../amd/display/dc/dce80/dce80_timing_generator.c | 2 +- .../drm/amd/display/dc/inc/hw/timing_generator.h | 10 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 + .../drm/amd/display/modules/freesync/freesync.c | 227 ++++++++++++++++----- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 20 ++ 13 files changed, 357 insertions(+), 123 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 93c936d92f5a..2e74faef68e7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -175,6 +175,31 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, return ret; } +static bool stream_get_crtc_position(struct dc *dc, + const struct dc_stream **stream, int num_streams, + unsigned int *v_pos, unsigned int *nom_v_pos) +{ + /* TODO: Support multiple streams */ + struct core_dc *core_dc = DC_TO_CORE(dc); + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + int i = 0; + bool ret = false; + struct crtc_position position; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe = + &core_dc->current_context->res_ctx.pipe_ctx[i]; + + if (pipe->stream == core_stream && pipe->stream_enc) { + core_dc->hwss.get_position(&pipe, 1, &position); + + *v_pos = position.vertical_count; + *nom_v_pos = position.nominal_vcount; + ret = true; + } + } + return ret; +} static bool set_gamut_remap(struct dc *dc, const struct dc_stream **stream, int num_streams) @@ -349,6 +374,9 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) core_dc->public.stream_funcs.set_static_screen_events = set_static_screen_events; + core_dc->public.stream_funcs.get_crtc_position = + stream_get_crtc_position; + core_dc->public.stream_funcs.set_gamut_remap = set_gamut_remap; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index fb48b8909e7f..ee840e75ee1f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -287,6 +287,7 @@ void context_timing_trace( struct core_dc *core_dc = DC_TO_CORE(dc); struct dal_logger *logger = core_dc->ctx->logger; int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; + struct crtc_position position; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -294,7 +295,9 @@ void context_timing_trace( if (pipe_ctx->stream == NULL) continue; - pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos[i], &v_pos[i]); + pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &position); + h_pos[i] = position.horizontal_count; + v_pos[i] = position.vertical_count; } for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d12aa726164e..647c095e0ae9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -103,6 +103,12 @@ struct dc_stream_funcs { int num_streams, int vmin, int vmax); + bool (*get_crtc_position)(struct dc *dc, + const struct dc_stream **stream, + int num_streams, + unsigned int *v_pos, + unsigned int *nom_v_pos); + void (*stream_update_scaling)(const struct dc *dc, const struct dc_stream *dc_stream, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6a93c96b9b26..0e69aceb0bad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1362,6 +1362,18 @@ static void set_drr(struct pipe_ctx **pipe_ctx, } } +static void get_position(struct pipe_ctx **pipe_ctx, + int num_pipes, + struct crtc_position *position) +{ + int i = 0; + + /* TODO: handle pipes > 1 + */ + for (i = 0; i < num_pipes; i++) + pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position); +} + static void set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_events *events) { @@ -2486,6 +2498,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .pipe_control_lock = dce_pipe_control_lock, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, + .get_position = get_position, .set_static_screen_control = set_static_screen_control, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 23760727f000..ec599276ed2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -518,34 +518,38 @@ uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg) /** ***************************************************************************** - * Function: dce110_get_crtc_positions + * Function: dce110_timing_generator_get_position * * @brief * Returns CRTC vertical/horizontal counters * - * @param [out] v_position, h_position + * @param [out] position ***************************************************************************** */ - -void dce110_timing_generator_get_crtc_positions( - struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position) +void dce110_timing_generator_get_position(struct timing_generator *tg, + struct crtc_position *position) { uint32_t value; struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION)); - *h_position = get_reg_field_value( + position->horizontal_count = get_reg_field_value( value, CRTC_STATUS_POSITION, CRTC_HORZ_COUNT); - *v_position = get_reg_field_value( + position->vertical_count = get_reg_field_value( value, CRTC_STATUS_POSITION, CRTC_VERT_COUNT); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_NOM_VERT_POSITION)); + + position->nominal_vcount = get_reg_field_value( + value, + CRTC_NOM_VERT_POSITION, + CRTC_VERT_COUNT_NOM); } /** @@ -566,18 +570,23 @@ void dce110_timing_generator_get_crtc_scanoutpos( uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + struct crtc_position position; - uint32_t v_blank_start_end = dm_read_reg(tg->ctx, + uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_V_BLANK_START_END)); - *v_blank_start = get_reg_field_value(v_blank_start_end, + *v_blank_start = get_reg_field_value(value, CRTC_V_BLANK_START_END, CRTC_V_BLANK_START); - *v_blank_end = get_reg_field_value(v_blank_start_end, + *v_blank_end = get_reg_field_value(value, CRTC_V_BLANK_START_END, CRTC_V_BLANK_END); - dce110_timing_generator_get_crtc_positions(tg, h_position, v_position); + dce110_timing_generator_get_position( + tg, &position); + + *h_position = position.horizontal_count; + *v_position = position.vertical_count; } /* TODO: is it safe to assume that mask/shift of Primary and Underlay @@ -1344,15 +1353,13 @@ void dce110_timing_generator_tear_down_global_swap_lock( */ bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg) { - uint32_t h1 = 0; - uint32_t h2 = 0; - uint32_t v1 = 0; - uint32_t v2 = 0; + struct crtc_position position1, position2; - tg->funcs->get_position(tg, &h1, &v1); - tg->funcs->get_position(tg, &h2, &v2); + tg->funcs->get_position(tg, &position1); + tg->funcs->get_position(tg, &position2); - if (h1 == h2 && v1 == v2) + if (position1.horizontal_count == position2.horizontal_count && + position1.vertical_count == position2.vertical_count) return false; else return true; @@ -1750,18 +1757,6 @@ void dce110_tg_set_overscan_color(struct timing_generator *tg, dm_write_reg(ctx, addr, value); } -void dce110_tg_get_position(struct timing_generator *tg, - struct crtc_position *position) -{ - int32_t h_position; - int32_t v_position; - - dce110_timing_generator_get_crtc_positions(tg, &h_position, &v_position); - - position->horizontal_count = (uint32_t)h_position; - position->vertical_count = (uint32_t)v_position; -} - void dce110_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, bool use_vbios) @@ -1895,7 +1890,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = { .enable_crtc = dce110_timing_generator_enable_crtc, .disable_crtc = dce110_timing_generator_disable_crtc, .is_counter_moving = dce110_timing_generator_is_counter_moving, - .get_position = dce110_timing_generator_get_crtc_positions, + .get_position = dce110_timing_generator_get_position, .get_frame_count = dce110_timing_generator_get_vblank_counter, .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, .set_early_control = dce110_timing_generator_set_early_control, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index f14a4d91cd8e..a5d63c626ada 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -151,11 +151,9 @@ void dce110_timing_generator_set_early_control( uint32_t dce110_timing_generator_get_vblank_counter( struct timing_generator *tg); -/* Get current H and V position */ -void dce110_timing_generator_get_crtc_positions( +void dce110_timing_generator_get_position( struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position); + struct crtc_position *position); /* return true if TG counter is moving. false if TG is stopped */ bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg); @@ -251,9 +249,6 @@ void dce110_tg_program_blank_color(struct timing_generator *tg, void dce110_tg_set_overscan_color(struct timing_generator *tg, const struct tg_color *overscan_color); -void dce110_tg_get_position(struct timing_generator *tg, - struct crtc_position *position); - void dce110_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, bool use_vbios); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index c95b69446ced..759c55bb4d15 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -570,24 +570,11 @@ static void dce110_timing_generator_v_set_early_control( dm_write_reg(tg->ctx, address, regval); } -static void dce110_timing_generator_v_get_crtc_positions( - struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position) +static void dce110_timing_generator_get_underlay_position(struct timing_generator *tg, + struct crtc_position *position) { - uint32_t value; - - value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); - - *h_position = get_reg_field_value( - value, - CRTCV_STATUS_POSITION, - CRTC_HORZ_COUNT); - - *v_position = get_reg_field_value( - value, - CRTCV_STATUS_POSITION, - CRTC_VERT_COUNT); + //Should never hit this case + ASSERT(false); } static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg) @@ -665,7 +652,7 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = { .enable_crtc = dce110_timing_generator_v_enable_crtc, .disable_crtc = dce110_timing_generator_v_disable_crtc, .is_counter_moving = dce110_timing_generator_v_is_counter_moving, - .get_position = dce110_timing_generator_v_get_crtc_positions, + .get_position = dce110_timing_generator_get_underlay_position, .get_frame_count = dce110_timing_generator_v_get_vblank_counter, .set_early_control = dce110_timing_generator_v_set_early_control, .wait_for_state = dce110_timing_generator_v_wait_for_state, diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 1318df7ed47e..245356e72b36 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -180,10 +180,9 @@ uint32_t dce120_timing_generator_get_vblank_counter( } /* Get current H and V position */ -void dce120_timing_generator_get_crtc_positions( +void dce120_timing_generator_get_crtc_position( struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position) + struct crtc_position *position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t value = dm_read_reg_soc15( @@ -191,11 +190,19 @@ void dce120_timing_generator_get_crtc_positions( mmCRTC0_CRTC_STATUS_POSITION, tg110->offsets.crtc); - *h_position = get_reg_field_value( - value, CRTC0_CRTC_STATUS_POSITION, CRTC_HORZ_COUNT); + position->horizontal_count = get_reg_field_value(value, + CRTC0_CRTC_STATUS_POSITION, CRTC_HORZ_COUNT); - *v_position = get_reg_field_value( - value, CRTC0_CRTC_STATUS_POSITION, CRTC_VERT_COUNT); + position->vertical_count = get_reg_field_value(value, + CRTC0_CRTC_STATUS_POSITION, CRTC_VERT_COUNT); + + value = dm_read_reg_soc15( + tg->ctx, + mmCRTC0_CRTC_NOM_VERT_POSITION, + tg110->offsets.crtc); + + position->nominal_vcount = get_reg_field_value(value, + CRTC0_CRTC_NOM_VERT_POSITION, CRTC_VERT_COUNT_NOM); } /* wait until TG is in beginning of vertical blank region */ @@ -576,6 +583,49 @@ void dce120_timing_generator_set_drr( } } +/** + ***************************************************************************** + * Function: dce120_timing_generator_get_position + * + * @brief + * Returns CRTC vertical/horizontal counters + * + * @param [out] position + ***************************************************************************** + */ +void dce120_timing_generator_get_position(struct timing_generator *tg, + struct crtc_position *position) +{ + uint32_t value; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + value = dm_read_reg_soc15( + tg->ctx, + mmCRTC0_CRTC_STATUS_POSITION, + tg110->offsets.crtc); + + position->horizontal_count = get_reg_field_value( + value, + CRTC0_CRTC_STATUS_POSITION, + CRTC_HORZ_COUNT); + + position->vertical_count = get_reg_field_value( + value, + CRTC0_CRTC_STATUS_POSITION, + CRTC_VERT_COUNT); + + value = dm_read_reg_soc15( + tg->ctx, + mmCRTC0_CRTC_NOM_VERT_POSITION, + tg110->offsets.crtc); + + position->nominal_vcount = get_reg_field_value( + value, + CRTC0_CRTC_NOM_VERT_POSITION, + CRTC_VERT_COUNT_NOM); +} + + void dce120_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, uint32_t *v_blank_start, @@ -584,6 +634,7 @@ void dce120_timing_generator_get_crtc_scanoutpos( uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + struct crtc_position position; uint32_t v_blank_start_end = dm_read_reg_soc15( tg->ctx, @@ -597,7 +648,11 @@ void dce120_timing_generator_get_crtc_scanoutpos( CRTC0_CRTC_V_BLANK_START_END, CRTC_V_BLANK_END); - dce120_timing_generator_get_crtc_positions(tg, h_position, v_position); + dce120_timing_generator_get_crtc_position( + tg, &position); + + *h_position = position.horizontal_count; + *v_position = position.vertical_count; } void dce120_timing_generator_enable_advanced_request( @@ -1076,7 +1131,7 @@ static struct timing_generator_funcs dce120_tg_funcs = { /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = dce110_timing_generator_is_counter_moving, /* never be called */ - .get_position = dce120_timing_generator_get_crtc_positions, + .get_position = dce120_timing_generator_get_crtc_position, .get_frame_count = dce120_timing_generator_get_vblank_counter, .get_scanoutpos = dce120_timing_generator_get_crtc_scanoutpos, .set_early_control = dce120_timing_generator_set_early_control, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c index 1198f2fbf9c7..179a6d604838 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c @@ -121,7 +121,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = { .enable_crtc = dce110_timing_generator_enable_crtc, .disable_crtc = dce110_timing_generator_disable_crtc, .is_counter_moving = dce110_timing_generator_is_counter_moving, - .get_position = dce110_timing_generator_get_crtc_positions, + .get_position = dce110_timing_generator_get_position, .get_frame_count = dce110_timing_generator_get_vblank_counter, .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, .set_early_control = dce110_timing_generator_set_early_control, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 235cfe8d1ad4..2c4a9d02b3c1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -30,9 +30,9 @@ struct dc_bios; /* Contains CRTC vertical/horizontal pixel counters */ struct crtc_position { - uint32_t vertical_count; - uint32_t horizontal_count; - uint32_t nominal_vcount; + int32_t vertical_count; + int32_t horizontal_count; + int32_t nominal_vcount; }; struct dcp_gsl_params { @@ -105,8 +105,8 @@ struct timing_generator_funcs { bool (*disable_crtc)(struct timing_generator *tg); bool (*is_counter_moving)(struct timing_generator *tg); void (*get_position)(struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position); + struct crtc_position *position); + uint32_t (*get_frame_count)(struct timing_generator *tg); void (*get_scanoutpos)( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b42e4a0ef18a..afdb8605a30f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -131,6 +131,9 @@ struct hw_sequencer_funcs { void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, int vmin, int vmax); + void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, + struct crtc_position *position); + void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_events *events); diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 78b4f28d862c..f6223e6b3536 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -76,6 +76,16 @@ struct fixed_refresh { bool program_fixed_refresh; }; +struct freesync_range { + unsigned int min_refresh; + unsigned int max_frame_duration; + unsigned int vmax; + + unsigned int max_refresh; + unsigned int min_frame_duration; + unsigned int vmin; +}; + struct freesync_state { bool fullscreen; bool static_screen; @@ -89,6 +99,7 @@ struct freesync_state { struct gradual_static_ramp static_ramp; struct below_the_range btr; struct fixed_refresh fixed_refresh; + struct freesync_range freesync_range; }; struct freesync_entity { @@ -342,8 +353,11 @@ static void update_stream(struct core_freesync *core_freesync, } } -static void calc_vmin_vmax(struct core_freesync *core_freesync, - const struct dc_stream *stream, int *vmin, int *vmax) +static void calc_freesync_range(struct core_freesync *core_freesync, + const struct dc_stream *stream, + struct freesync_state *state, + unsigned int min_refresh_in_uhz, + unsigned int max_refresh_in_uhz) { unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0; unsigned int index = map_index_from_stream(core_freesync, stream); @@ -351,29 +365,50 @@ static void calc_vmin_vmax(struct core_freesync *core_freesync, min_frame_duration_in_ns = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), - core_freesync->map[index].state. - nominal_refresh_rate_in_micro_hz))); + max_refresh_in_uhz))); max_frame_duration_in_ns = ((unsigned int) (div64_u64( - (1000000000ULL * 1000000), - core_freesync->map[index].caps->min_refresh_in_micro_hz))); + (1000000000ULL * 1000000), + min_refresh_in_uhz))); + + state->freesync_range.min_refresh = min_refresh_in_uhz; + state->freesync_range.max_refresh = max_refresh_in_uhz; - *vmax = div64_u64(div64_u64(((unsigned long long)( - max_frame_duration_in_ns) * stream->timing.pix_clk_khz), - stream->timing.h_total), 1000000); - *vmin = div64_u64(div64_u64(((unsigned long long)( - min_frame_duration_in_ns) * stream->timing.pix_clk_khz), - stream->timing.h_total), 1000000); + state->freesync_range.max_frame_duration = max_frame_duration_in_ns; + state->freesync_range.min_frame_duration = min_frame_duration_in_ns; + + state->freesync_range.vmax = div64_u64(div64_u64(((unsigned long long)( + max_frame_duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); + state->freesync_range.vmin = div64_u64(div64_u64(((unsigned long long)( + min_frame_duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ - if (*vmin < vtotal) { + if (state->freesync_range.vmin < vtotal) { ASSERT(false); - *vmin = vtotal; + state->freesync_range.vmin = vtotal; } - if (*vmax < vtotal) { + if (state->freesync_range.vmax < vtotal) { ASSERT(false); - *vmax = vtotal; + state->freesync_range.vmax = vtotal; } + + /* Determine whether BTR can be supported */ + if (max_frame_duration_in_ns >= + 2 * min_frame_duration_in_ns) + core_freesync->map[index].caps->btr_supported = true; + else + core_freesync->map[index].caps->btr_supported = false; + + /* Cache the time variables */ + state->time.max_render_time_in_us = + max_frame_duration_in_ns / 1000; + state->time.min_render_time_in_us = + min_frame_duration_in_ns / 1000; + state->btr.mid_point_in_us = + (max_frame_duration_in_ns + + min_frame_duration_in_ns) / 2000; } static void calc_v_total_from_duration(const struct dc_stream *stream, @@ -518,9 +553,8 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, state->fixed_refresh.fixed_refresh_active == false) { /* Enable freesync */ - calc_vmin_vmax(core_freesync, - streams[stream_idx], - &v_total_min, &v_total_max); + v_total_min = state->freesync_range.vmin; + v_total_max = state->freesync_range.vmax; /* Update the freesync context for the stream */ update_stream_freesync_context(core_freesync, @@ -696,7 +730,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, (1000000000ULL * 1000000), state->nominal_refresh_rate_in_micro_hz))); - calc_vmin_vmax(core_freesync, *streams, &vmin, &vmax); + vmin = state->freesync_range.vmin; inserted_frame_v_total = vmin; @@ -941,11 +975,120 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, return true; } +bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *streams, + unsigned int min_refresh, + unsigned int max_refresh) +{ + unsigned int index = 0; + struct core_freesync *core_freesync; + struct freesync_state *state; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, streams); + state = &core_freesync->map[index].state; + + if (min_refresh == 0 || max_refresh == 0) { + /* Restore defaults */ + calc_freesync_range(core_freesync, streams, state, + core_freesync->map[index].caps-> + min_refresh_in_micro_hz, + state->nominal_refresh_rate_in_micro_hz); + } else { + calc_freesync_range(core_freesync, streams, + state, + min_refresh, + max_refresh); + + /* Program vtotal min/max */ + core_freesync->dc->stream_funcs.adjust_vmin_vmax( + core_freesync->dc, &streams, 1, + state->freesync_range.vmin, + state->freesync_range.vmax); + } + + return true; +} + +bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *min_refresh, + unsigned int *max_refresh) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + *min_refresh = + core_freesync->map[index].state.freesync_range.min_refresh; + *max_refresh = + core_freesync->map[index].state.freesync_range.max_refresh; + + return true; +} + +bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *vmin, + unsigned int *vmax) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + *vmin = + core_freesync->map[index].state.freesync_range.vmin; + *vmax = + core_freesync->map[index].state.freesync_range.vmax; + + return true; +} + +bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *nom_v_pos, + unsigned int *v_pos) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + struct crtc_position position; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + if (core_freesync->dc->stream_funcs.get_crtc_position( + core_freesync->dc, &stream, 1, + &position.vertical_count, &position.nominal_vcount)) { + + *nom_v_pos = position.vertical_count; + *v_pos = position.nominal_vcount; + + return true; + } + + return false; +} + void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams) { unsigned int stream_index, map_index; - unsigned min_frame_duration_in_ns, max_frame_duration_in_ns; struct freesync_state *state; struct core_freesync *core_freesync = NULL; @@ -965,37 +1108,23 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, unsigned long long temp; temp = streams[stream_index]->timing.pix_clk_khz; temp *= 1000ULL * 1000ULL * 1000ULL; - temp = div_u64(temp, streams[stream_index]->timing.h_total); - temp = div_u64(temp, streams[stream_index]->timing.v_total); - state->nominal_refresh_rate_in_micro_hz = (unsigned int) temp; + temp = div_u64(temp, + streams[stream_index]->timing.h_total); + temp = div_u64(temp, + streams[stream_index]->timing.v_total); + state->nominal_refresh_rate_in_micro_hz = + (unsigned int) temp; /* Update the stream */ update_stream(core_freesync, streams[stream_index]); - /* Determine whether BTR can be supported */ - min_frame_duration_in_ns = ((unsigned int) (div64_u64( - (1000000000ULL * 1000000), - state->nominal_refresh_rate_in_micro_hz))); - - max_frame_duration_in_ns = ((unsigned int) (div64_u64( - (1000000000ULL * 1000000), - core_freesync->map[map_index].caps->min_refresh_in_micro_hz))); - - if (max_frame_duration_in_ns >= - 2 * min_frame_duration_in_ns) - core_freesync->map[map_index].caps->btr_supported = true; - else - core_freesync->map[map_index].caps->btr_supported = false; - - /* Cache the time variables */ - state->time.max_render_time_in_us = - max_frame_duration_in_ns / 1000; - state->time.min_render_time_in_us = - min_frame_duration_in_ns / 1000; - state->btr.mid_point_in_us = - (max_frame_duration_in_ns + - min_frame_duration_in_ns) / 2000; - + /* Calculate vmin/vmax and refresh rate for + * current mode + */ + calc_freesync_range(core_freesync, *streams, state, + core_freesync->map[stream_index].caps-> + min_refresh_in_micro_hz, + state->nominal_refresh_rate_in_micro_hz); } } @@ -1178,7 +1307,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, /* Fixed Refresh set to "active" so engage (fix to max) */ } else { - calc_vmin_vmax(core_freesync, stream, &vmin, &vmax); + vmin = state->freesync_range.vmin; vmax = vmin; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 783ff2ef3bee..3947cc412ad7 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -129,6 +129,26 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_user_enable *user_enable); +bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *streams, + unsigned int min_refresh, + unsigned int max_refresh); + +bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *min_refresh, + unsigned int *max_refresh); + +bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *vmin, + unsigned int *vmax); + +bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *nom_v_pos, + unsigned int *v_pos); + void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams); -- cgit v1.2.3-59-g8ed1b From a2b8659db9b435853cb0dc78d225a492e7ee69d0 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Sat, 22 Apr 2017 14:17:51 -0400 Subject: drm/amd/display: decouple resource_pool from resource_context to avoid null access in case res_ctx is used to access res_pool before it's fully constructed also make it clear which function has dependency on resource_pool Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ++- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 143 ++++++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 3 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 42 +++--- .../drm/amd/display/dc/dce110/dce110_resource.c | 25 ++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 35 +++-- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 15 ++- 13 files changed, 161 insertions(+), 147 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 2e74faef68e7..37986632f025 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -736,7 +736,7 @@ static void program_timing_sync( { int i, j; int group_index = 0; - int pipe_count = ctx->res_ctx.pool->pipe_count; + int pipe_count = core_dc->res_pool->pipe_count; struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; for (i = 0; i < pipe_count; i++) { @@ -939,7 +939,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) post_surface_trace(dc); - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) + for (i = 0; i < core_dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL) { context->res_ctx.pipe_ctx[i].pipe_idx = i; core_dc->hwss.power_down_front_end( @@ -1015,7 +1015,7 @@ static bool is_surface_in_context( { int j; - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { + for (j = 0; j < MAX_PIPES; j++) { const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (surface == &pipe_ctx->surface->public) { @@ -1245,7 +1245,8 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, dc_stream, context)) { + new_surfaces, surface_count, dc_stream, + context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; } @@ -1304,7 +1305,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* not sure if we still need this */ if (update_type == UPDATE_TYPE_FULL) { - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { + for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (pipe_ctx->surface != surface) @@ -1365,7 +1366,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (i = 0; i < surface_count; i++) { struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { + for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (pipe_ctx->surface != surface) @@ -1389,7 +1390,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, context_timing_trace(dc, &context->res_ctx); } - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { + for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; struct pipe_ctx *cur_pipe_ctx; bool is_new_pipe_surface = true; @@ -1427,7 +1428,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, } /* Unlock pipes */ - for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { + for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; for (j = 0; j < surface_count; j++) { @@ -1571,8 +1572,6 @@ void dc_set_power_state( memset(core_dc->current_context, 0, sizeof(*core_dc->current_context)); - core_dc->current_context->res_ctx.pool = core_dc->res_pool; - break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index f883fdb820c8..4b9d3f12406f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2245,7 +2245,7 @@ static void set_crtc_test_pattern(struct core_link *link, case DP_TEST_PATTERN_VIDEO_MODE: { /* restore bitdepth reduction */ - link->dc->current_context->res_ctx.pool->funcs-> + link->dc->res_pool->funcs-> build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms); pipe_ctx->stream->bit_depth_params = params; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index cdb98d5f7caa..43e5758719ca 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -233,11 +233,12 @@ bool resource_construct( void resource_unreference_clock_source( struct resource_context *res_ctx, + const struct resource_pool *pool, struct clock_source **clock_source) { int i; - for (i = 0; i < res_ctx->pool->clk_src_count; i++) { - if (res_ctx->pool->clock_sources[i] != *clock_source) + for (i = 0; i < pool->clk_src_count; i++) { + if (pool->clock_sources[i] != *clock_source) continue; res_ctx->clock_source_ref_count[i]--; @@ -248,7 +249,7 @@ void resource_unreference_clock_source( break; } - if (res_ctx->pool->dp_clock_source == *clock_source) { + if (pool->dp_clock_source == *clock_source) { res_ctx->dp_clock_source_ref_count--; if (res_ctx->dp_clock_source_ref_count == 0) @@ -259,18 +260,19 @@ void resource_unreference_clock_source( void resource_reference_clock_source( struct resource_context *res_ctx, + const struct resource_pool *pool, struct clock_source *clock_source) { int i; - for (i = 0; i < res_ctx->pool->clk_src_count; i++) { - if (res_ctx->pool->clock_sources[i] != clock_source) + for (i = 0; i < pool->clk_src_count; i++) { + if (pool->clock_sources[i] != clock_source) continue; res_ctx->clock_source_ref_count[i]++; break; } - if (res_ctx->pool->dp_clock_source == clock_source) + if (pool->dp_clock_source == clock_source) res_ctx->dp_clock_source_ref_count++; } @@ -861,12 +863,13 @@ enum dc_status resource_build_scaling_params_for_context( static void detach_surfaces_for_stream( struct validate_context *context, + const struct resource_pool *pool, const struct dc_stream *dc_stream) { int i; struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < pool->pipe_count; i++) { struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; if (cur_pipe->stream == stream) { cur_pipe->surface = NULL; @@ -876,7 +879,9 @@ static void detach_surfaces_for_stream( } } -struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx) +struct pipe_ctx *find_idle_secondary_pipe( + struct resource_context *res_ctx, + const struct resource_pool *pool) { int i; struct pipe_ctx *secondary_pipe = NULL; @@ -886,7 +891,7 @@ struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx) * assignment more consistent */ - for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) { + for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[i]; secondary_pipe->pipe_idx = i; @@ -903,7 +908,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( const struct core_stream *stream) { int i; - for (i = 0; i < res_ctx->pool->pipe_count; i++) { + for (i = 0; i < MAX_PIPES; i++) { if (res_ctx->pipe_ctx[i].stream == stream && res_ctx->pipe_ctx[i].stream_enc) { return &res_ctx->pipe_ctx[i]; @@ -919,6 +924,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( */ static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, + const struct resource_pool *pool, const struct dc_stream *dc_stream) { int i; @@ -938,7 +944,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( return head_pipe; /* Re-use pipe already acquired for this stream if available*/ - for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) { + for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && !res_ctx->pipe_ctx[i].surface) { return &res_ctx->pipe_ctx[i]; @@ -950,10 +956,10 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( * to acquire an idle one to satisfy the request */ - if(!res_ctx->pool->funcs->acquire_idle_pipe_for_layer) + if (!pool->funcs->acquire_idle_pipe_for_layer) return NULL; - return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(context, stream); + return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream); } @@ -964,7 +970,7 @@ static void release_free_pipes_for_stream( int i; struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); - for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) { + for (i = MAX_PIPES - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && !res_ctx->pipe_ctx[i].surface) { res_ctx->pipe_ctx[i].stream = NULL; @@ -976,7 +982,8 @@ bool resource_attach_surfaces_to_context( const struct dc_surface * const *surfaces, int surface_count, const struct dc_stream *dc_stream, - struct validate_context *context) + struct validate_context *context, + const struct resource_pool *pool) { int i; struct pipe_ctx *tail_pipe; @@ -1003,7 +1010,7 @@ bool resource_attach_surfaces_to_context( for (i = 0; i < surface_count; i++) dc_surface_retain(surfaces[i]); - detach_surfaces_for_stream(context, dc_stream); + detach_surfaces_for_stream(context, pool, dc_stream); /* release existing surfaces*/ for (i = 0; i < stream_status->surface_count; i++) @@ -1020,7 +1027,8 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); - struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(context, dc_stream); + struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( + context, pool, dc_stream); if (!free_pipe) { stream_status->surfaces[i] = NULL; @@ -1101,7 +1109,8 @@ bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, const struct validate_context *old_context, - struct validate_context *context) + struct validate_context *context, + const struct resource_pool *pool) { int i, j; @@ -1114,7 +1123,7 @@ bool resource_validate_attach_surfaces( old_context->stream_status[j].surfaces, old_context->stream_status[j].surface_count, &context->streams[i]->public, - context)) + context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; } @@ -1123,7 +1132,7 @@ bool resource_validate_attach_surfaces( set[i].surfaces, set[i].surface_count, &context->streams[i]->public, - context)) + context, pool)) return false; } @@ -1136,12 +1145,13 @@ bool resource_validate_attach_surfaces( static void set_stream_engine_in_use( struct resource_context *res_ctx, + const struct resource_pool *pool, struct stream_encoder *stream_enc) { int i; - for (i = 0; i < res_ctx->pool->stream_enc_count; i++) { - if (res_ctx->pool->stream_enc[i] == stream_enc) + for (i = 0; i < pool->stream_enc_count; i++) { + if (pool->stream_enc[i] == stream_enc) res_ctx->is_stream_enc_acquired[i] = true; } } @@ -1149,32 +1159,33 @@ static void set_stream_engine_in_use( /* TODO: release audio object */ static void set_audio_in_use( struct resource_context *res_ctx, + const struct resource_pool *pool, struct audio *audio) { int i; - for (i = 0; i < res_ctx->pool->audio_count; i++) { - if (res_ctx->pool->audios[i] == audio) { + for (i = 0; i < pool->audio_count; i++) { + if (pool->audios[i] == audio) res_ctx->is_audio_acquired[i] = true; - } } } static int acquire_first_free_pipe( struct resource_context *res_ctx, + const struct resource_pool *pool, struct core_stream *stream) { int i; - for (i = 0; i < res_ctx->pool->pipe_count; i++) { + for (i = 0; i < pool->pipe_count; i++) { if (!res_ctx->pipe_ctx[i].stream) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - pipe_ctx->tg = res_ctx->pool->timing_generators[i]; - pipe_ctx->mi = res_ctx->pool->mis[i]; - pipe_ctx->ipp = res_ctx->pool->ipps[i]; - pipe_ctx->xfm = res_ctx->pool->transforms[i]; - pipe_ctx->opp = res_ctx->pool->opps[i]; - pipe_ctx->dis_clk = res_ctx->pool->display_clock; + pipe_ctx->tg = pool->timing_generators[i]; + pipe_ctx->mi = pool->mis[i]; + pipe_ctx->ipp = pool->ipps[i]; + pipe_ctx->xfm = pool->transforms[i]; + pipe_ctx->opp = pool->opps[i]; + pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; pipe_ctx->stream = stream; @@ -1186,21 +1197,22 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, + const struct resource_pool *pool, struct core_stream *stream) { int i; int j = -1; struct core_link *link = stream->sink->link; - for (i = 0; i < res_ctx->pool->stream_enc_count; i++) { + for (i = 0; i < pool->stream_enc_count; i++) { if (!res_ctx->is_stream_enc_acquired[i] && - res_ctx->pool->stream_enc[i]) { + pool->stream_enc[i]) { /* Store first available for MST second display * in daisy chain use case */ j = i; - if (res_ctx->pool->stream_enc[i]->id == + if (pool->stream_enc[i]->id == link->link_enc->preferred_engine) - return res_ctx->pool->stream_enc[i]; + return pool->stream_enc[i]; } } @@ -1218,17 +1230,19 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link( */ if (j >= 0 && dc_is_dp_signal(stream->signal)) - return res_ctx->pool->stream_enc[j]; + return pool->stream_enc[j]; return NULL; } -static struct audio *find_first_free_audio(struct resource_context *res_ctx) +static struct audio *find_first_free_audio( + struct resource_context *res_ctx, + const struct resource_pool *pool) { int i; - for (i = 0; i < res_ctx->pool->audio_count; i++) { + for (i = 0; i < pool->audio_count; i++) { if (res_ctx->is_audio_acquired[i] == false) { - return res_ctx->pool->audios[i]; + return pool->audios[i]; } } @@ -1358,6 +1372,7 @@ enum dc_status resource_map_pool_resources( const struct core_dc *dc, struct validate_context *context) { + const struct resource_pool *pool = dc->res_pool; int i, j; calculate_phy_pix_clks(dc, context); @@ -1370,12 +1385,12 @@ enum dc_status resource_map_pool_resources( stream->bit_depth_params = dc->current_context->streams[i]->bit_depth_params; stream->clamping = dc->current_context->streams[i]->clamping; - continue; + continue; + } } - } /* mark resources used for stream that is already active */ - for (j = 0; j < MAX_PIPES; j++) { + for (j = 0; j < pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; const struct pipe_ctx *old_pipe_ctx = @@ -1395,7 +1410,7 @@ enum dc_status resource_map_pool_resources( continue; set_stream_engine_in_use( - &context->res_ctx, + &context->res_ctx, pool, pipe_ctx->stream_enc); /* Switch to dp clock source only if there is @@ -1404,15 +1419,14 @@ enum dc_status resource_map_pool_resources( */ if (dc_is_dp_signal(pipe_ctx->stream->signal) && !find_pll_sharable_stream(stream, context)) - pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; + pipe_ctx->clock_source = pool->dp_clock_source; resource_reference_clock_source( - &context->res_ctx, + &context->res_ctx, pool, pipe_ctx->clock_source); - set_audio_in_use(&context->res_ctx, - pipe_ctx->audio); + set_audio_in_use(&context->res_ctx, pool, + pipe_ctx->audio); } } @@ -1424,22 +1438,22 @@ enum dc_status resource_map_pool_resources( if (resource_is_stream_unchanged(dc->current_context, stream)) continue; /* acquire new resources */ - pipe_idx = acquire_first_free_pipe(&context->res_ctx, stream); + pipe_idx = acquire_first_free_pipe( + &context->res_ctx, pool, stream); if (pipe_idx < 0) return DC_NO_CONTROLLER_RESOURCE; - pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_ctx->stream_enc = find_first_free_match_stream_enc_for_link( - &context->res_ctx, stream); + &context->res_ctx, pool, stream); if (!pipe_ctx->stream_enc) return DC_NO_STREAM_ENG_RESOURCE; set_stream_engine_in_use( - &context->res_ctx, + &context->res_ctx, pool, pipe_ctx->stream_enc); /* TODO: Add check if ASIC support and EDID audio */ @@ -1447,7 +1461,7 @@ enum dc_status resource_map_pool_resources( dc_is_audio_capable_signal(pipe_ctx->stream->signal) && stream->public.audio_info.mode_count) { pipe_ctx->audio = find_first_free_audio( - &context->res_ctx); + &context->res_ctx, pool); /* * Audio assigned in order first come first get. @@ -1456,7 +1470,7 @@ enum dc_status resource_map_pool_resources( */ if (pipe_ctx->audio) set_audio_in_use( - &context->res_ctx, + &context->res_ctx, pool, pipe_ctx->audio); } @@ -2077,7 +2091,7 @@ void dc_resource_validate_ctx_copy_construct( *dst_ctx = *src_ctx; - for (i = 0; i < dst_ctx->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; if (cur_pipe->top_pipe) @@ -2097,13 +2111,14 @@ void dc_resource_validate_ctx_copy_construct( } struct clock_source *dc_resource_find_first_free_pll( - struct resource_context *res_ctx) + struct resource_context *res_ctx, + const struct resource_pool *pool) { int i; - for (i = 0; i < res_ctx->pool->clk_src_count; ++i) { + for (i = 0; i < pool->clk_src_count; ++i) { if (res_ctx->clock_source_ref_count[i] == 0) - return res_ctx->pool->clock_sources[i]; + return pool->clock_sources[i]; } return NULL; @@ -2151,6 +2166,7 @@ enum dc_status resource_map_clock_resources( struct validate_context *context) { int i, j; + const struct resource_pool *pool = dc->res_pool; /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { @@ -2168,8 +2184,7 @@ enum dc_status resource_map_clock_resources( if (dc_is_dp_signal(pipe_ctx->stream->signal) || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; + pipe_ctx->clock_source = pool->dp_clock_source; else { pipe_ctx->clock_source = NULL; @@ -2180,14 +2195,16 @@ enum dc_status resource_map_clock_resources( if (pipe_ctx->clock_source == NULL) pipe_ctx->clock_source = - dc_resource_find_first_free_pll(&context->res_ctx); + dc_resource_find_first_free_pll( + &context->res_ctx, + pool); } if (pipe_ctx->clock_source == NULL) return DC_NO_CLOCK_SOURCE_RESOURCE; resource_reference_clock_source( - &context->res_ctx, + &context->res_ctx, pool, pipe_ctx->clock_source); /* only one cs per stream regardless of mpo */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 23627b14c16c..99b6a1695f26 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -240,7 +240,7 @@ bool dc_stream_set_cursor_position( struct dc_cursor_position pos_cpy = *position; struct dc_cursor_mi_param param = { .pixel_clk_khz = dc_stream->timing.pix_clk_khz, - .ref_clk_khz = res_ctx->pool->ref_clock_inKhz, + .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz, .viewport_x_start = pipe_ctx->scl_data.viewport.x, .viewport_width = pipe_ctx->scl_data.viewport.width, .h_scale_ratio = pipe_ctx->scl_data.ratios.horz diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 943895faee49..aa6ac9596235 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -138,8 +138,7 @@ const struct dc_surface_status *dc_surface_get_status( if (core_dc->current_context == NULL) return NULL; - for (i = 0; i < core_dc->current_context->res_ctx.pool->pipe_count; - i++) { + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index dd6f0b1bd8ae..30c197f378dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -132,8 +132,8 @@ void dce100_set_bandwidth( bool decrease_allowed) { if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { - context->res_ctx.pool->display_clock->funcs->set_clock( - context->res_ctx.pool->display_clock, + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, context->dispclk_khz * 115 / 100); dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; dc->current_context->dispclk_khz = context->dispclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index f65b785220e2..f0700706d7c9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -804,8 +804,6 @@ enum dc_status dce100_validate_with_context( if (!dce100_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - context->res_ctx.pool = dc->res_pool; - for (i = 0; i < set_count; i++) { context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); dc_stream_retain(&context->streams[i]->public); @@ -817,8 +815,8 @@ enum dc_status dce100_validate_with_context( if (result == DC_OK) result = resource_map_clock_resources(dc, context); - if (!resource_validate_attach_surfaces( - set, set_count, dc->current_context, context)) { + if (!resource_validate_attach_surfaces(set, set_count, + dc->current_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -843,8 +841,6 @@ enum dc_status dce100_validate_guaranteed( { enum dc_status result = DC_ERROR_UNEXPECTED; - context->res_ctx.pool = dc->res_pool; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); dc_stream_retain(&context->streams[0]->public); context->stream_count++; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 0e69aceb0bad..dc4c16416370 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1260,10 +1260,12 @@ void dce110_set_displaymarks( } } -static void set_safe_displaymarks(struct resource_context *res_ctx) +static void set_safe_displaymarks( + struct resource_context *res_ctx, + const struct resource_pool *pool) { int i; - int underlay_idx = res_ctx->pool->underlay_pipe_index; + int underlay_idx = pool->underlay_pipe_index; struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; struct bw_watermarks nbp_marks = { @@ -1308,9 +1310,11 @@ static void switch_dp_clock_sources( if (clk_src && clk_src != pipe_ctx->clock_source) { resource_unreference_clock_source( - res_ctx, &pipe_ctx->clock_source); + res_ctx, dc->res_pool, + &pipe_ctx->clock_source); pipe_ctx->clock_source = clk_src; - resource_reference_clock_source(res_ctx, clk_src); + resource_reference_clock_source( + res_ctx, dc->res_pool, clk_src); dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); } @@ -1336,8 +1340,8 @@ static void reset_single_pipe_hw_ctx( pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); pipe_ctx->mi->funcs->free_mem_input( pipe_ctx->mi, context->stream_count); - resource_unreference_clock_source( - &context->res_ctx, &pipe_ctx->clock_source); + resource_unreference_clock_source(&context->res_ctx, dc->res_pool, + &pipe_ctx->clock_source); dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); @@ -1530,7 +1534,7 @@ static enum dc_status apply_ctx_to_hw_fpga( enum dc_status status = DC_ERROR_UNEXPECTED; int i; - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -1561,7 +1565,7 @@ static void reset_hw_ctx_wrap( /* Reset old context */ /* look up the targets that have been removed since last commit */ - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -1609,7 +1613,7 @@ enum dc_status dce110_apply_ctx_to_hw( dcb->funcs->set_scratch_critical_state(dcb, true); /* below is for real asic only */ - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -1629,14 +1633,14 @@ enum dc_status dce110_apply_ctx_to_hw( PIPE_GATING_CONTROL_DISABLE); } - set_safe_displaymarks(&context->res_ctx); + set_safe_displaymarks(&context->res_ctx, dc->res_pool); /*TODO: when pplib works*/ apply_min_clocks(dc, context, &clocks_state, true); if (context->dispclk_khz > dc->current_context->dispclk_khz) { - context->res_ctx.pool->display_clock->funcs->set_clock( - context->res_ctx.pool->display_clock, + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, context->dispclk_khz * 115 / 100); } /* program audio wall clock. use HDMI as clock source if HDMI @@ -1658,7 +1662,7 @@ enum dc_status dce110_apply_ctx_to_hw( * find first available pipe with audio, setup audio wall DTO per topology * instead of per pipe. */ - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -1685,8 +1689,8 @@ enum dc_status dce110_apply_ctx_to_hw( } /* no HDMI audio is found, try DP audio */ - if (i == context->res_ctx.pool->pipe_count) { - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + if (i == dc->res_pool->pipe_count) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -1713,7 +1717,7 @@ enum dc_status dce110_apply_ctx_to_hw( } } - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -2297,8 +2301,8 @@ static void dce110_set_bandwidth( dce110_set_displaymarks(dc, context); if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { - context->res_ctx.pool->display_clock->funcs->set_clock( - context->res_ctx.pool->display_clock, + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, context->dispclk_khz * 115 / 100); dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; dc->current_context->dispclk_khz = context->dispclk_khz; @@ -2446,7 +2450,7 @@ static void dce110_apply_ctx_for_surface( if (!surface) return; - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->surface != surface) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 8dec9a5602a9..122f2d03afc0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -866,7 +866,7 @@ static enum dc_status validate_mapped_resource( continue; if (!is_surface_pixel_format_supported(pipe_ctx, - context->res_ctx.pool->underlay_pipe_index)) + dc->res_pool->underlay_pipe_index)) return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; if (!pipe_ctx->tg->funcs->validate_timing( @@ -918,7 +918,7 @@ bool dce110_validate_bandwidth( &dc->bw_dceip, &dc->bw_vbios, context->res_ctx.pipe_ctx, - context->res_ctx.pool->pipe_count, + dc->res_pool->pipe_count, &context->bw_results)) result = true; context->dispclk_khz = context->bw_results.dispclk_khz; @@ -1030,8 +1030,6 @@ enum dc_status dce110_validate_with_context( if (!dce110_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - context->res_ctx.pool = dc->res_pool; - for (i = 0; i < set_count; i++) { context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); dc_stream_retain(&context->streams[i]->public); @@ -1043,8 +1041,8 @@ enum dc_status dce110_validate_with_context( if (result == DC_OK) result = resource_map_clock_resources(dc, context); - if (!resource_validate_attach_surfaces( - set, set_count, dc->current_context, context)) { + if (!resource_validate_attach_surfaces(set, set_count, + dc->current_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -1069,8 +1067,6 @@ enum dc_status dce110_validate_guaranteed( { enum dc_status result = DC_ERROR_UNEXPECTED; - context->res_ctx.pool = dc->res_pool; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); dc_stream_retain(&context->streams[0]->public); context->stream_count++; @@ -1098,22 +1094,23 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, + const struct resource_pool *pool, struct core_stream *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; - unsigned int underlay_idx = res_ctx->pool->underlay_pipe_index; + unsigned int underlay_idx = pool->underlay_pipe_index; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; if (res_ctx->pipe_ctx[underlay_idx].stream) return NULL; - pipe_ctx->tg = res_ctx->pool->timing_generators[underlay_idx]; - pipe_ctx->mi = res_ctx->pool->mis[underlay_idx]; + pipe_ctx->tg = pool->timing_generators[underlay_idx]; + pipe_ctx->mi = pool->mis[underlay_idx]; /*pipe_ctx->ipp = res_ctx->pool->ipps[underlay_idx];*/ - pipe_ctx->xfm = res_ctx->pool->transforms[underlay_idx]; - pipe_ctx->opp = res_ctx->pool->opps[underlay_idx]; - pipe_ctx->dis_clk = res_ctx->pool->display_clock; + pipe_ctx->xfm = pool->transforms[underlay_idx]; + pipe_ctx->opp = pool->opps[underlay_idx]; + pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = underlay_idx; pipe_ctx->stream = stream; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 4bf75afd5721..4de51a86c9ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -749,22 +749,24 @@ static void destruct(struct dce110_resource_pool *pool) } } -static struct clock_source *find_matching_pll(struct resource_context *res_ctx, +static struct clock_source *find_matching_pll( + struct resource_context *res_ctx, + const struct resource_pool *pool, const struct core_stream *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: - return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL0]; + return pool->clock_sources[DCE112_CLK_SRC_PLL0]; case TRANSMITTER_UNIPHY_B: - return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL1]; + return pool->clock_sources[DCE112_CLK_SRC_PLL1]; case TRANSMITTER_UNIPHY_C: - return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL2]; + return pool->clock_sources[DCE112_CLK_SRC_PLL2]; case TRANSMITTER_UNIPHY_D: - return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL3]; + return pool->clock_sources[DCE112_CLK_SRC_PLL3]; case TRANSMITTER_UNIPHY_E: - return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL4]; + return pool->clock_sources[DCE112_CLK_SRC_PLL4]; case TRANSMITTER_UNIPHY_F: - return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL5]; + return pool->clock_sources[DCE112_CLK_SRC_PLL5]; default: return NULL; }; @@ -842,7 +844,7 @@ bool dce112_validate_bandwidth( &dc->bw_dceip, &dc->bw_vbios, context->res_ctx.pipe_ctx, - context->res_ctx.pool->pipe_count, + dc->res_pool->pipe_count, &context->bw_results)) result = true; context->dispclk_khz = context->bw_results.dispclk_khz; @@ -928,17 +930,18 @@ enum dc_status resource_map_phy_clock_resources( if (dc_is_dp_signal(pipe_ctx->stream->signal) || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; + dc->res_pool->dp_clock_source; else - pipe_ctx->clock_source = - find_matching_pll(&context->res_ctx, - stream); + pipe_ctx->clock_source = find_matching_pll( + &context->res_ctx, dc->res_pool, + stream); if (pipe_ctx->clock_source == NULL) return DC_NO_CLOCK_SOURCE_RESOURCE; resource_reference_clock_source( &context->res_ctx, + dc->res_pool, pipe_ctx->clock_source); /* only one cs per stream regardless of mpo */ @@ -983,8 +986,6 @@ enum dc_status dce112_validate_with_context( if (!dce112_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - context->res_ctx.pool = dc->res_pool; - for (i = 0; i < set_count; i++) { context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); dc_stream_retain(&context->streams[i]->public); @@ -996,8 +997,8 @@ enum dc_status dce112_validate_with_context( if (result == DC_OK) result = resource_map_phy_clock_resources(dc, context); - if (!resource_validate_attach_surfaces( - set, set_count, dc->current_context, context)) { + if (!resource_validate_attach_surfaces(set, set_count, + dc->current_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -1022,8 +1023,6 @@ enum dc_status dce112_validate_guaranteed( { enum dc_status result = DC_ERROR_UNEXPECTED; - context->res_ctx.pool = dc->res_pool; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); dc_stream_retain(&context->streams[0]->public); context->stream_count++; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index d49092986d54..0aa128e5ed84 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -821,8 +821,6 @@ enum dc_status dce80_validate_with_context( if (!dce80_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - context->res_ctx.pool = dc->res_pool; - for (i = 0; i < set_count; i++) { context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); dc_stream_retain(&context->streams[i]->public); @@ -834,8 +832,8 @@ enum dc_status dce80_validate_with_context( if (result == DC_OK) result = resource_map_clock_resources(dc, context); - if (!resource_validate_attach_surfaces( - set, set_count, dc->current_context, context)) { + if (!resource_validate_attach_surfaces(set, set_count, + dc->current_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -859,8 +857,6 @@ enum dc_status dce80_validate_guaranteed( { enum dc_status result = DC_ERROR_UNEXPECTED; - context->res_ctx.pool = dc->res_pool; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); dc_stream_retain(&context->streams[0]->public); context->stream_count++; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 2b43e18c65f5..f3fe850ffa13 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -212,6 +212,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, + const struct resource_pool *pool, struct core_stream *stream); void (*build_bit_depth_reduction_params)( @@ -293,7 +294,6 @@ struct pipe_ctx { }; struct resource_context { - const struct resource_pool *pool; struct pipe_ctx pipe_ctx[MAX_PIPES]; bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index b1987cab9751..89d34bed131b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -92,10 +92,12 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx); void resource_unreference_clock_source( struct resource_context *res_ctx, + const struct resource_pool *pool, struct clock_source **clock_source); void resource_reference_clock_source( struct resource_context *res_ctx, + const struct resource_pool *pool, struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( @@ -107,7 +109,8 @@ struct clock_source *resource_find_used_clk_src_for_sharing( struct pipe_ctx *pipe_ctx); struct clock_source *dc_resource_find_first_free_pll( - struct resource_context *res_ctx); + struct resource_context *res_ctx, + const struct resource_pool *pool); struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, @@ -117,9 +120,12 @@ bool resource_attach_surfaces_to_context( const struct dc_surface *const *surfaces, int surface_count, const struct dc_stream *dc_stream, - struct validate_context *context); + struct validate_context *context, + const struct resource_pool *pool); -struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx); +struct pipe_ctx *find_idle_secondary_pipe( + struct resource_context *res_ctx, + const struct resource_pool *pool); bool resource_is_stream_unchanged( const struct validate_context *old_context, const struct core_stream *stream); @@ -131,7 +137,8 @@ bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, const struct validate_context *old_context, - struct validate_context *context); + struct validate_context *context, + const struct resource_pool *pool); void validate_guaranteed_copy_streams( struct validate_context *context, -- cgit v1.2.3-59-g8ed1b From 529cad0f945c9e60569e902062d2f2741e4fd71a Mon Sep 17 00:00:00 2001 From: Ding Wang Date: Tue, 25 Apr 2017 10:03:27 -0400 Subject: drm/amd/display: Add function to set dither option Signed-off-by: Ding Wang Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 41 ++++++++ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 110 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 3 + .../drm/amd/display/dc/dce110/dce110_resource.c | 48 +-------- .../drm/amd/display/dc/dce110/dce110_resource.h | 4 - .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 - drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 + 9 files changed, 160 insertions(+), 58 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 37986632f025..738acf0cc7db 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -363,6 +363,44 @@ static void set_test_pattern( cust_pattern_size); } +void set_dither_option(const struct dc_stream *dc_stream, + enum dc_dither_option option) +{ + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct bit_depth_reduction_params params; + struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link); + struct pipe_ctx *pipes = + core_link->dc->current_context->res_ctx.pipe_ctx; + + memset(¶ms, 0, sizeof(params)); + if (!stream) + return; + if (option > DITHER_OPTION_MAX) + return; + if (option == DITHER_OPTION_DEFAULT) { + switch (stream->public.timing.display_color_depth) { + case COLOR_DEPTH_666: + stream->public.dither_option = DITHER_OPTION_SPATIAL6; + break; + case COLOR_DEPTH_888: + stream->public.dither_option = DITHER_OPTION_SPATIAL8; + break; + case COLOR_DEPTH_101010: + stream->public.dither_option = DITHER_OPTION_SPATIAL10; + break; + default: + option = DITHER_OPTION_DISABLE; + } + } else { + stream->public.dither_option = option; + } + resource_build_bit_depth_reduction_params(stream, + ¶ms); + stream->bit_depth_params = params; + pipes->opp->funcs-> + opp_program_bit_depth_reduction(pipes->opp, ¶ms); +} + static void allocate_dc_stream_funcs(struct core_dc *core_dc) { core_dc->public.stream_funcs.stream_update_scaling = stream_update_scaling; @@ -380,6 +418,9 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) core_dc->public.stream_funcs.set_gamut_remap = set_gamut_remap; + core_dc->public.stream_funcs.set_dither_option = + set_dither_option; + core_dc->public.link_funcs.set_drive_settings = set_drive_settings; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 4b9d3f12406f..a0d192774a22 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -11,6 +11,7 @@ #include "dpcd_defs.h" #include "core_dc.h" +#include "resource.h" /* maximum pre emphasis level allowed for each voltage swing level*/ static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = { @@ -2245,8 +2246,7 @@ static void set_crtc_test_pattern(struct core_link *link, case DP_TEST_PATTERN_VIDEO_MODE: { /* restore bitdepth reduction */ - link->dc->res_pool->funcs-> - build_bit_depth_reduction_params(pipe_ctx->stream, + resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms); pipe_ctx->stream->bit_depth_params = params; pipe_ctx->opp->funcs-> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 43e5758719ca..2de86f8364a3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2246,3 +2246,113 @@ bool pipe_need_reprogram( return false; } + +void resource_build_bit_depth_reduction_params(const struct core_stream *stream, + struct bit_depth_reduction_params *fmt_bit_depth) +{ + enum dc_dither_option option = stream->public.dither_option; + enum dc_pixel_encoding pixel_encoding = + stream->public.timing.pixel_encoding; + + memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); + + if (option == DITHER_OPTION_DISABLE) + return; + + if (option == DITHER_OPTION_TRUN6) { + fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; + fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; + } else if (option == DITHER_OPTION_TRUN8 || + option == DITHER_OPTION_TRUN8_SPATIAL6 || + option == DITHER_OPTION_TRUN8_FM6) { + fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; + fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; + } else if (option == DITHER_OPTION_TRUN10 || + option == DITHER_OPTION_TRUN10_SPATIAL6 || + option == DITHER_OPTION_TRUN10_SPATIAL8 || + option == DITHER_OPTION_TRUN10_FM8 || + option == DITHER_OPTION_TRUN10_FM6 || + option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { + fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; + fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; + } + + /* special case - Formatter can only reduce by 4 bits at most. + * When reducing from 12 to 6 bits, + * HW recommends we use trunc with round mode + * (if we did nothing, trunc to 10 bits would be used) + * note that any 12->10 bit reduction is ignored prior to DCE8, + * as the input was 10 bits. + */ + if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || + option == DITHER_OPTION_SPATIAL6 || + option == DITHER_OPTION_FM6) { + fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; + fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; + fmt_bit_depth->flags.TRUNCATE_MODE = 1; + } + + /* spatial dither + * note that spatial modes 1-3 are never used + */ + if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || + option == DITHER_OPTION_SPATIAL6 || + option == DITHER_OPTION_TRUN10_SPATIAL6 || + option == DITHER_OPTION_TRUN8_SPATIAL6) { + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; + fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; + fmt_bit_depth->flags.RGB_RANDOM = + (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; + } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || + option == DITHER_OPTION_SPATIAL8 || + option == DITHER_OPTION_SPATIAL8_FM6 || + option == DITHER_OPTION_TRUN10_SPATIAL8 || + option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; + fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; + fmt_bit_depth->flags.RGB_RANDOM = + (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; + } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || + option == DITHER_OPTION_SPATIAL10 || + option == DITHER_OPTION_SPATIAL10_FM8 || + option == DITHER_OPTION_SPATIAL10_FM6) { + fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; + fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; + fmt_bit_depth->flags.RGB_RANDOM = + (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; + } + + if (option == DITHER_OPTION_SPATIAL6 || + option == DITHER_OPTION_SPATIAL8 || + option == DITHER_OPTION_SPATIAL10) { + fmt_bit_depth->flags.FRAME_RANDOM = 0; + } else { + fmt_bit_depth->flags.FRAME_RANDOM = 1; + } + + ////////////////////// + //// temporal dither + ////////////////////// + if (option == DITHER_OPTION_FM6 || + option == DITHER_OPTION_SPATIAL8_FM6 || + option == DITHER_OPTION_SPATIAL10_FM6 || + option == DITHER_OPTION_TRUN10_FM6 || + option == DITHER_OPTION_TRUN8_FM6 || + option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { + fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; + fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; + } else if (option == DITHER_OPTION_FM8 || + option == DITHER_OPTION_SPATIAL10_FM8 || + option == DITHER_OPTION_TRUN10_FM8) { + fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; + fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; + } else if (option == DITHER_OPTION_FM10) { + fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; + fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; + } + + fmt_bit_depth->pixel_encoding = pixel_encoding; +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index dd8902d28ee1..87675f032949 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -122,6 +122,9 @@ struct dc_stream_funcs { const struct dc_stream **stream, int num_streams, const struct dc_static_screen_events *events); + + void (*set_dither_option)(const struct dc_stream *stream, + enum dc_dither_option option); }; struct link_training_settings; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 122f2d03afc0..5b2b41efa5f0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -775,50 +775,6 @@ static void get_pixel_clock_parameters( } } -void dce110_resource_build_bit_depth_reduction_params( - const struct core_stream *stream, - struct bit_depth_reduction_params *fmt_bit_depth) -{ - memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); - - /*TODO: Need to un-hardcode, refer to function with same name - * in dal2 hw_sequencer*/ - - fmt_bit_depth->flags.TRUNCATE_ENABLED = 0; - fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 0; - fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 0; - - /* Diagnostics need consistent CRC of the image, that means - * dithering should not be enabled for Diagnostics. */ - if (IS_DIAG_DC(stream->ctx->dce_environment) == false) { - switch (stream->public.timing.display_color_depth) { - case COLOR_DEPTH_666: - fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; - fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; - break; - case COLOR_DEPTH_888: - fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; - fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; - break; - case COLOR_DEPTH_101010: - fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; - fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; - break; - default: - break; - } - fmt_bit_depth->flags.RGB_RANDOM = 1; - fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; - fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; - fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; - - fmt_bit_depth->pixel_encoding = - stream->public.timing.pixel_encoding; - } - - return; -} - enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); @@ -826,7 +782,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) pipe_ctx->clock_source, &pipe_ctx->pix_clk_params, &pipe_ctx->pll_settings); - dce110_resource_build_bit_depth_reduction_params(pipe_ctx->stream, + resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; @@ -1171,8 +1127,6 @@ static const struct resource_funcs dce110_res_pool_funcs = { .validate_guaranteed = dce110_validate_guaranteed, .validate_bandwidth = dce110_validate_bandwidth, .acquire_idle_pipe_for_layer = dce110_acquire_underlay, - .build_bit_depth_reduction_params = - dce110_resource_build_bit_depth_reduction_params }; static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h index 0c357fdfa8bc..8e2e85dd30b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -40,10 +40,6 @@ struct dce110_resource_pool { enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); -void dce110_resource_build_bit_depth_reduction_params( - const struct core_stream *stream, - struct bit_depth_reduction_params *fmt_bit_depth); - struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, struct core_dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 4de51a86c9ea..18c1b89a52be 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1062,7 +1062,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .link_enc_create = dce112_link_encoder_create, .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, - .validate_bandwidth = dce112_validate_bandwidth + .validate_bandwidth = dce112_validate_bandwidth, }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index f3fe850ffa13..9e5e0ba5b10b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -214,10 +214,6 @@ struct resource_funcs { struct validate_context *context, const struct resource_pool *pool, struct core_stream *stream); - - void (*build_bit_depth_reduction_params)( - const struct core_stream *stream, - struct bit_depth_reduction_params *fmt_bit_depth); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 89d34bed131b..4e07b9fea669 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -160,5 +160,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); +void resource_build_bit_depth_reduction_params(const struct core_stream *stream, + struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ -- cgit v1.2.3-59-g8ed1b From ff5ef99248662ef98a64c11c5370ecd9fbbf57a6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:27:42 -0400 Subject: drm/amdgpu/display: Enable DCN in DC Enable DCN in DC. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 7 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 115 ++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +- drivers/gpu/drm/amd/display/dc/Makefile | 5 + .../amd/display/dc/bios/command_table_helper2.c | 5 + drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 ++ drivers/gpu/drm/amd/display/dc/dc.h | 18 ++ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 ++++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 ++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 ++ .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +++++++++++++++++++++ .../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 ++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +++ drivers/gpu/drm/amd/display/dc/dm_services.h | 4 + drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 + drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 + drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +- drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 + drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 + drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 + drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 ++ .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +++++++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + .../drm/amd/display/dc/inc/hw/timing_generator.h | 16 ++ drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 + drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 + drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 + drivers/gpu/drm/amd/display/include/dal_types.h | 5 +- 39 files changed, 1250 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 47c8e2940a91..5c3bb3581842 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,6 +17,13 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. +config DRM_AMD_DC_DCN1_0 + bool "DCN 1.0 Raven family" + depends on DRM_AMD_DC + help + Choose this option if you want to have + RV family for display engine + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 74e32246ff30..4ec86ed5622f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -49,6 +49,16 @@ #include "modules/inc/mod_freesync.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "ivsrcid/irqsrcs_dcn_1_0.h" + +#include "raven1/DCN/dcn_1_0_offset.h" +#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "vega10/soc15ip.h" + +#include "soc15_common.h" +#endif + static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -930,7 +940,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int i; unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; - if (adev->asic_type == CHIP_VEGA10) + if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_RAVEN) client_id = AMDGPU_IH_CLIENTID_DCE; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; @@ -1003,6 +1014,92 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) return 0; } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +/* Register IRQ sources and initialize IRQ callbacks */ +static int dcn10_register_irq_handlers(struct amdgpu_device *adev) +{ + struct dc *dc = adev->dm.dc; + struct common_irq_params *c_irq_params; + struct dc_interrupt_params int_params = {0}; + int r; + int i; + + int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; + int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; + + /* Actions of amdgpu_irq_add_id(): + * 1. Register a set() function with base driver. + * Base driver will call set() function to enable/disable an + * interrupt in DC hardware. + * 2. Register amdgpu_dm_irq_handler(). + * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts + * coming from DC hardware. + * amdgpu_dm_irq_handler() will re-direct the interrupt to DC + * for acknowledging and handling. + * */ + + /* Use VSTARTUP interrupt */ + for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; + i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; + i++) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq); + + if (r) { + DRM_ERROR("Failed to add crtc irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_crtc_high_irq, c_irq_params); + } + + /* Use GRPH_PFLIP interrupt */ + for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; + i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; + i++) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq); + if (r) { + DRM_ERROR("Failed to add page flip irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_pflip_high_irq, c_irq_params); + + } + + /* HPD */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, + &adev->hpd_irq); + if (r) { + DRM_ERROR("Failed to add hpd irq id!\n"); + return r; + } + + register_hpd_handlers(adev); + + return 0; +} +#endif + static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) { int r; @@ -1172,6 +1269,14 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail_free_encoder; } break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + if (dcn10_register_irq_handlers(dm->adev)) { + DRM_ERROR("DM: Failed to initialize IRQ\n"); + goto fail_free_encoder; + } + break; +#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); goto fail_free_encoder; @@ -1447,6 +1552,14 @@ static int dm_early_init(void *handle) adev->mode_info.num_dig = 6; adev->mode_info.plane_type = dm_surfaces_type_default; break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 4; + adev->mode_info.num_dig = 4; + adev->mode_info.plane_type = dm_surfaces_type_default; + break; +#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 0f09e8b903d3..bca6769e7481 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -562,7 +562,8 @@ static void fill_plane_attributes_from_fb( surface->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - if (adev->asic_type == CHIP_VEGA10) { + if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ surface->tiling_info.gfx9.num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 1a79762425ea..4f83e3011743 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -4,7 +4,12 @@ DC_LIBS = basics bios calcs dce gpio i2caux irq virtual +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +DC_LIBS += dcn10 dml +endif + DC_LIBS += dce120 + DC_LIBS += dce112 DC_LIBS += dce110 DC_LIBS += dce100 diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 1cc3df1d5698..84b1f515aa47 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -53,6 +53,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCE_VERSION_11_2: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + *h = dal_cmd_tbl_helper_dce112_get_table2(); + return true; +#endif case DCE_VERSION_12_0: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 63a0edbc32e7..a095472bf4b5 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -3,8 +3,16 @@ # It calculates Bandwidth and Watermarks values for HW programming # +CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4 +CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4 +CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4 + BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o +endif + AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS)) AMD_DISPLAY_FILES += $(AMD_DAL_BW_CALCS) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2de86f8364a3..ae8b221c85aa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -39,6 +39,9 @@ #include "dce100/dce100_resource.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/dcn10_resource.h" +#endif #include "dce120/dce120_resource.h" enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) @@ -69,6 +72,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) case FAMILY_AI: dc_version = DCE_VERSION_12_0; break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case FAMILY_RV: + dc_version = DCN_VERSION_1_0; + break; +#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -105,6 +113,13 @@ struct resource_pool *dc_create_resource_pool( res_pool = dce120_create_resource_pool( num_virtual_links, dc); break; + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + res_pool = dcn10_create_resource_pool( + num_virtual_links, dc); + break; +#endif default: break; } @@ -1188,6 +1203,10 @@ static int acquire_first_free_pipe( pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + pipe_ctx->mpc_idx = -1; +#endif + pipe_ctx->stream = stream; return i; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 87675f032949..d74bbdce1090 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -94,7 +94,13 @@ struct dc_surface; struct validate_context; struct dc_cap_funcs { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + bool (*get_dcc_compression_cap)(const struct dc *dc, + const struct dc_dcc_surface_param *input, + struct dc_surface_dcc_cap *output); +#else int i; +#endif }; struct dc_stream_funcs { @@ -164,6 +170,18 @@ struct dc_debug { bool disable_stutter; bool disable_dcc; bool disable_dfs_bypass; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + bool disable_dpp_power_gate; + bool disable_hubp_power_gate; + bool disable_pplib_wm_range; + bool use_dml_wm; + bool use_max_voltage; + int sr_exit_time_ns; + int sr_enter_plus_exit_time_ns; + int urgent_latency_ns; + int percent_of_ideal_drambw; + int dram_clock_change_latency_ns; +#endif bool disable_pplib_clock_request; bool disable_clock_gate; bool disable_dmcu; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 56087b36bdeb..e0abd2d49370 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -54,6 +54,22 @@ SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ SR(BIOS_SCRATCH_2) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define ABM_DCN10_REG_LIST(id)\ + ABM_COMMON_REG_LIST_DCE_BASE(), \ + SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ + SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ + SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ + SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_USER_LEVEL, ABM, id), \ + SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ + SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + NBIO_SR(BIOS_SCRATCH_2) +#endif + #define ABM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -105,6 +121,39 @@ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ + ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) +#endif + #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ type ABM1_HG_VMAX_SEL; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index bd4524ef3a37..142b3a01c204 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -586,6 +586,9 @@ static uint32_t dce110_get_pix_clk_dividers( break; case DCE_VERSION_11_2: case DCE_VERSION_12_0: +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: +#endif dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -815,6 +818,31 @@ static bool dce110_program_pix_clk( struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); struct bp_pixel_clock_parameters bp_pc_params = {0}; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { + unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; + unsigned dp_dto_ref_kHz = 600000; + /* DPREF clock from FPGA TODO: Does FPGA have this value? */ + unsigned clock_kHz = pll_settings->actual_pix_clk; + + /* For faster simulation, if mode pixe clock less than 290MHz, + * pixel clock can be hard coded to 290Mhz. For 4K mode, pixel clock + * is greater than 500Mhz, need real pixel clock + * clock_kHz = 290000; + */ + /* TODO: un-hardcode when we can set display clock properly*/ + /*clock_kHz = pix_clk_params->requested_pix_clk;*/ + clock_kHz = 290000; + + /* Set DTO values: phase = target clock, modulo = reference clock */ + REG_WRITE(PHASE[inst], clock_kHz); + REG_WRITE(MODULO[inst], dp_dto_ref_kHz); + + /* Enable DTO */ + REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); + return true; + } +#endif /* First disable SS * ATOMBIOS will enable by default SS on PLL for DP, * do not disable it here @@ -870,6 +898,9 @@ static bool dce110_program_pix_clk( break; case DCE_VERSION_11_2: case DCE_VERSION_12_0: +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: +#endif if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 28984c79fc46..e8bc98b3b622 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -55,6 +55,27 @@ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ + SRII(PHASE, DP_DTO, 1),\ + SRII(PHASE, DP_DTO, 2),\ + SRII(PHASE, DP_DTO, 3),\ + SRII(MODULO, DP_DTO, 0),\ + SRII(MODULO, DP_DTO, 1),\ + SRII(MODULO, DP_DTO, 2),\ + SRII(MODULO, DP_DTO, 3),\ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1), \ + SRII(PIXEL_RATE_CNTL, OTG, 2), \ + SRII(PIXEL_RATE_CNTL, OTG, 3) + +#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ + CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) +#endif + #define CS_REG_FIELD_LIST(type) \ type PLL_REF_DIV_SRC; \ type DCCG_DEEP_COLOR_CNTL1; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 81cb138cdc38..6e56d8308d66 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -29,6 +29,10 @@ #include "fixed32_32.h" #include "bios_parser_interface.h" #include "dc.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn_calcs.h" +#include "core_dc.h" +#endif #define TO_DCE_CLOCKS(clocks)\ container_of(clocks, struct dce_disp_clk, base) @@ -400,6 +404,10 @@ static void dce112_set_clock( bp->funcs->set_dce_clock(bp, &dce_clk_params); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + dce_psr_wait_loop(clk_dce, requested_clk_khz); +#endif + } static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce) @@ -596,6 +604,13 @@ static bool dce_apply_clock_voltage_request( } } if (send_request) { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + /*use dcfclk request voltage*/ + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock_voltage_req.clocks_in_khz = + dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value); +#endif dm_pp_apply_clock_for_voltage_request( clk->ctx, &clock_voltage_req); } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h index 29ff470086e5..103e905291a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -45,6 +45,15 @@ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define CLK_DCN10_REG_LIST()\ + SR(DPREFCLK_CNTL), \ + SR(DENTIST_DISPCLK_CNTL), \ + SR(MASTER_COMM_DATA_REG1), \ + SR(MASTER_COMM_CMD_REG), \ + SR(MASTER_COMM_CNTL_REG) +#endif + #define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index da7f86b61de4..c58328cd787b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -252,12 +252,234 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu, REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +bool dcn10_dmcu_load_iram(struct dmcu *dmcu, + unsigned int start_offset, + const char *src, + unsigned int bytes) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int count = 0; + + REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1); + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_WR_ADDR_AUTO_INC, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); + + for (count = 0; count < bytes; count++) + REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_WR_ADDR_AUTO_INC, 0); + + return true; +} + +static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + + uint32_t psrStateOffset = 0xf0; + + /* Enable write access to IRAM */ + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ + REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); + + /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ + *psr_state = REG_READ(DMCU_IRAM_RD_DATA); + + /* Disable write access to IRAM after finished using IRAM + * in order to allow dynamic sleep state + */ + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); +} + +static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + + unsigned int retryCount; + uint32_t psr_state = 0; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + dmcu_wait_reg_ready_interval, + dmcu_max_retry_on_wait_reg_ready); + + /* setDMCUParam_Cmd */ + if (enable) + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + PSR_ENABLE); + else + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + PSR_EXIT); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Below loops 1000 x 500us = 500 ms. + * Exit PSR may need to wait 1-2 frames to power up. Timeout after at + * least a few frames. Should never hit the max retry assert below. + */ + for (retryCount = 0; retryCount <= 1000; retryCount++) { + dcn10_get_dmcu_psr_state(dmcu, &psr_state); + if (enable) { + if (psr_state != 0) + break; + } else { + if (psr_state == 0) + break; + } + dm_delay_in_microseconds(dmcu->ctx, 500); + } + + /* assert if max retry hit */ + ASSERT(retryCount <= 1000); +} + +static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, + struct core_link *link, + struct psr_context *psr_context) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + + union dce_dmcu_psr_config_data_reg1 masterCmdData1; + union dce_dmcu_psr_config_data_reg2 masterCmdData2; + union dce_dmcu_psr_config_data_reg3 masterCmdData3; + + link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, + psr_context->psrExitLinkTrainingRequired); + + /* Enable static screen interrupts for PSR supported display */ + /* Disable the interrupt coming from other displays. */ + REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN1_INT_TO_UC_EN, 0, + STATIC_SCREEN2_INT_TO_UC_EN, 0, + STATIC_SCREEN3_INT_TO_UC_EN, 0, + STATIC_SCREEN4_INT_TO_UC_EN, 0); + + switch (psr_context->controllerId) { + /* Driver uses case 1 for unconfigured */ + case 1: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN1_INT_TO_UC_EN, 1); + break; + case 2: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN2_INT_TO_UC_EN, 1); + break; + case 3: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN3_INT_TO_UC_EN, 1); + break; + case 4: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN4_INT_TO_UC_EN, 1); + break; + case 5: + /* CZ/NL only has 4 CRTC!! + * really valid. + * There is no interrupt enable mask for these instances. + */ + break; + case 6: + /* CZ/NL only has 4 CRTC!! + * These are here because they are defined in HW regspec, + * but not really valid. There is no interrupt enable mask + * for these instances. + */ + break; + default: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN1_INT_TO_UC_EN, 1); + break; + } + + link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, + psr_context->sdpTransmitLineNumDeadline); + + if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) + REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + dmcu_wait_reg_ready_interval, + dmcu_max_retry_on_wait_reg_ready); + + /* setDMCUParam_PSRHostConfigData */ + masterCmdData1.u32All = 0; + masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; + masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; + masterCmdData1.bits.rfb_update_auto_en = + psr_context->rfb_update_auto_en; + masterCmdData1.bits.dp_port_num = psr_context->transmitterId; + masterCmdData1.bits.dcp_sel = psr_context->controllerId; + masterCmdData1.bits.phy_type = psr_context->phyType; + masterCmdData1.bits.frame_cap_ind = + psr_context->psrFrameCaptureIndicationReq; + masterCmdData1.bits.aux_chan = psr_context->channel; + masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), + masterCmdData1.u32All); + + masterCmdData2.u32All = 0; + masterCmdData2.bits.dig_fe = psr_context->engineId; + masterCmdData2.bits.dig_be = psr_context->transmitterId; + masterCmdData2.bits.skip_wait_for_pll_lock = + psr_context->skipPsrWaitForPllLock; + masterCmdData2.bits.frame_delay = psr_context->frame_delay; + masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; + masterCmdData2.bits.num_of_controllers = + psr_context->numberOfControllers; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), + masterCmdData2.u32All); + + masterCmdData3.u32All = 0; + masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), + masterCmdData3.u32All); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, + MASTER_COMM_CMD_REG_BYTE0, PSR_SET); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} + +#endif + static const struct dmcu_funcs dce_funcs = { .load_iram = dce_dmcu_load_iram, .set_psr_enable = dce_dmcu_set_psr_enable, .setup_psr = dce_dmcu_setup_psr, }; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +static const struct dmcu_funcs dcn10_funcs = { + .load_iram = dcn10_dmcu_load_iram, + .set_psr_enable = dcn10_dmcu_set_psr_enable, + .setup_psr = dcn10_dmcu_setup_psr, +}; +#endif + static void dce_dmcu_construct( struct dce_dmcu *dmcu_dce, struct dc_context *ctx, @@ -296,6 +518,29 @@ struct dmcu *dce_dmcu_create( return &dmcu_dce->base; } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct dmcu *dcn10_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask) +{ + struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + + if (dmcu_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_dmcu_construct( + dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); + + dmcu_dce->base.funcs = &dcn10_funcs; + + return &dmcu_dce->base; +} +#endif + void dce_dmcu_destroy(struct dmcu **dmcu) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h index 7dc25386c2bf..584682ba1f77 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h @@ -48,6 +48,12 @@ DMCU_COMMON_REG_LIST_DCE_BASE(), \ SR(DCI_MEM_PWR_STATUS) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define DMCU_DCN10_REG_LIST()\ + DMCU_COMMON_REG_LIST_DCE_BASE(), \ + SR(DMU_MEM_PWR_CNTL) +#endif + #define DMCU_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -76,6 +82,13 @@ DMCU_SF(DCI_MEM_PWR_STATUS, \ DMCU_IRAM_MEM_PWR_STATE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ + DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + DMCU_SF(DMU_MEM_PWR_CNTL, \ + DMCU_IRAM_MEM_PWR_STATE, mask_sh) +#endif + #define DMCU_REG_FIELD_LIST(type) \ type DMCU_IRAM_MEM_PWR_STATE; \ type IRAM_HOST_ACCESS_EN; \ @@ -190,6 +203,14 @@ struct dmcu *dce_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct dmcu *dcn10_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask); +#endif + void dce_dmcu_destroy(struct dmcu **dmcu); #endif /* _DCE_ABM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index c66585188ecd..dd13f47b6446 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -121,6 +121,12 @@ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ HWSEQ_PHYPLL_REG_LIST(CRTC) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define HWSEQ_DCN1_REG_LIST()\ + HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ + HWSEQ_PHYPLL_REG_LIST(OTG) +#endif + struct dce_hwseq_registers { uint32_t DCFE_CLOCK_CONTROL[6]; uint32_t DCFEV_CLOCK_CONTROL; @@ -129,6 +135,9 @@ struct dce_hwseq_registers { uint32_t BLND_CONTROL[6]; uint32_t BLNDV_CONTROL; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* DCE + DCN */ +#endif uint32_t CRTC_H_BLANK_START_END[6]; uint32_t PIXEL_RATE_CNTL[6]; uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; @@ -192,6 +201,12 @@ struct dce_hwseq_registers { HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_) +#endif + #define HWSEQ_REG_FIED_LIST(type) \ type DCFE_CLOCK_ENABLE; \ type DCFEV_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 4e0b5d965355..8b04996d5b89 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -78,6 +78,10 @@ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SR(DCI_MEM_PWR_STATUS) +#define LE_DCE80_REG_LIST(id)\ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + LE_COMMON_REG_LIST_BASE(id) + #define LE_DCE100_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ @@ -97,9 +101,15 @@ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ SR(DCI_MEM_PWR_STATUS) -#define LE_DCE80_REG_LIST(id)\ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define LE_DCN10_REG_LIST(id)\ + LE_COMMON_REG_LIST_BASE(id), \ + SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ + SR(DMU_MEM_PWR_CNTL) +#endif + struct dce110_link_enc_aux_registers { uint32_t AUX_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 9713def6e481..a065e4ae6cba 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -147,6 +147,46 @@ static void dce110_update_generic_info_packet( AFMT_GENERIC0_UPDATE, (packet_index == 0), AFMT_GENERIC2_UPDATE, (packet_index == 2)); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(AFMT_VBI_PACKET_CONTROL1)) { + switch (packet_index) { + case 0: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC0_FRAME_UPDATE, 1); + break; + case 1: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC1_FRAME_UPDATE, 1); + break; + case 2: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC2_FRAME_UPDATE, 1); + break; + case 3: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC3_FRAME_UPDATE, 1); + break; + case 4: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC4_FRAME_UPDATE, 1); + break; + case 5: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC5_FRAME_UPDATE, 1); + break; + case 6: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC6_FRAME_UPDATE, 1); + break; + case 7: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC7_FRAME_UPDATE, 1); + break; + default: + break; + } + } +#endif } static void dce110_update_hdmi_info_packet( @@ -202,6 +242,36 @@ static void dce110_update_hdmi_info_packet( HDMI_GENERIC1_SEND, send, HDMI_GENERIC1_LINE, line); break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case 4: + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, + HDMI_GENERIC0_CONT, cont, + HDMI_GENERIC0_SEND, send, + HDMI_GENERIC0_LINE, line); + break; + case 5: + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, + HDMI_GENERIC1_CONT, cont, + HDMI_GENERIC1_SEND, send, + HDMI_GENERIC1_LINE, line); + break; + case 6: + if (REG(HDMI_GENERIC_PACKET_CONTROL3)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, + HDMI_GENERIC0_CONT, cont, + HDMI_GENERIC0_SEND, send, + HDMI_GENERIC0_LINE, line); + break; + case 7: + if (REG(HDMI_GENERIC_PACKET_CONTROL3)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, + HDMI_GENERIC1_CONT, cont, + HDMI_GENERIC1_SEND, send, + HDMI_GENERIC1_LINE, line); + break; +#endif default: /* invalid HW packet index */ dm_logger_write( @@ -218,9 +288,24 @@ static void dce110_stream_encoder_dp_set_stream_attribute( struct dc_crtc_timing *crtc_timing, enum dc_color_space output_color_space) { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + uint32_t h_active_start; + uint32_t v_active_start; + uint32_t misc0 = 0; + uint32_t misc1 = 0; + uint32_t h_blank; + uint32_t h_back_porch; + uint8_t synchronous_clock = 0; /* asynchronous mode */ + uint8_t colorimetry_bpc; +#endif struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_DB_CNTL)) + REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1); +#endif + /* set pixel encoding */ switch (crtc_timing->pixel_encoding) { case PIXEL_ENCODING_YCBCR422: @@ -249,6 +334,10 @@ static void dce110_stream_encoder_dp_set_stream_attribute( if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->DP_VID_N_MUL) + REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); +#endif break; default: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, @@ -256,6 +345,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute( break; } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_MSA_MISC)) + misc1 = REG_READ(DP_MSA_MISC); +#endif + /* set color depth */ switch (crtc_timing->display_color_depth) { @@ -289,6 +383,128 @@ static void dce110_stream_encoder_dp_set_stream_attribute( DP_DYN_RANGE, 0, DP_YCBCR_RANGE, 0); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + switch (crtc_timing->display_color_depth) { + case COLOR_DEPTH_666: + colorimetry_bpc = 0; + break; + case COLOR_DEPTH_888: + colorimetry_bpc = 1; + break; + case COLOR_DEPTH_101010: + colorimetry_bpc = 2; + break; + case COLOR_DEPTH_121212: + colorimetry_bpc = 3; + break; + default: + colorimetry_bpc = 0; + break; + } + + misc0 = misc0 | synchronous_clock; + misc0 = colorimetry_bpc << 5; + + if (REG(DP_MSA_TIMING_PARAM1)) { + switch (output_color_space) { + case COLOR_SPACE_SRGB: + misc0 = misc0 | 0x0;; + misc1 = misc1 & ~0x80; /* bit7 = 0*/ + break; + case COLOR_SPACE_SRGB_LIMITED: + misc0 = misc0 | 0x8; /* bit3=1 */ + misc1 = misc1 & ~0x80; /* bit7 = 0*/ + break; + case COLOR_SPACE_YCBCR601: + misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ + misc1 = misc1 & ~0x80; /* bit7 = 0*/; + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) + misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ + else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) + misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ + break; + case COLOR_SPACE_YCBCR709: + misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ + misc1 = misc1 & ~0x80; /* bit7 = 0*/ + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) + misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ + else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) + misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_ADOBERGB: + case COLOR_SPACE_UNKNOWN: + case COLOR_SPACE_YCBCR601_LIMITED: + case COLOR_SPACE_YCBCR709_LIMITED: + /* do nothing */ + break; + } + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_MSA_COLORIMETRY)) + REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); + + if (REG(DP_MSA_MISC)) + REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ + + /* dcn new register + * dc_crtc_timing is vesa dmt struct. data from edid + */ + if (REG(DP_MSA_TIMING_PARAM1)) + REG_SET_2(DP_MSA_TIMING_PARAM1, 0, + DP_MSA_HTOTAL, crtc_timing->h_total, + DP_MSA_VTOTAL, crtc_timing->v_total); +#endif + + /* calcuate from vesa timing parameters + * h_active_start related to leading edge of sync + */ + + h_blank = crtc_timing->h_total - crtc_timing->h_border_left - + crtc_timing->h_addressable - crtc_timing->h_border_right; + + h_back_porch = h_blank - crtc_timing->h_front_porch - + crtc_timing->h_sync_width; + + /* start at begining of left border */ + h_active_start = crtc_timing->h_sync_width + h_back_porch; + + + v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - + crtc_timing->v_addressable - crtc_timing->v_border_bottom - + crtc_timing->v_front_porch; + + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* start at begining of left border */ + if (REG(DP_MSA_TIMING_PARAM2)) + REG_SET_2(DP_MSA_TIMING_PARAM2, 0, + DP_MSA_HSTART, h_active_start, + DP_MSA_VSTART, v_active_start); + + if (REG(DP_MSA_TIMING_PARAM3)) + REG_SET_4(DP_MSA_TIMING_PARAM3, 0, + DP_MSA_HSYNCWIDTH, + crtc_timing->h_sync_width, + DP_MSA_HSYNCPOLARITY, + !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, + DP_MSA_VSYNCWIDTH, + crtc_timing->v_sync_width, + DP_MSA_VSYNCPOLARITY, + !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); + + /* HWDITH include border or overscan */ + if (REG(DP_MSA_TIMING_PARAM4)) + REG_SET_2(DP_MSA_TIMING_PARAM4, 0, + DP_MSA_HWIDTH, crtc_timing->h_border_left + + crtc_timing->h_addressable + crtc_timing->h_border_right, + DP_MSA_VHEIGHT, crtc_timing->v_border_top + + crtc_timing->v_addressable + crtc_timing->v_border_bottom); +#endif + } +#endif } static void dce110_stream_encoder_set_stream_attribute_helper( @@ -533,6 +749,19 @@ static void dce110_stream_encoder_update_hdmi_info_packets( dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->HDMI_DB_DISABLE) { + /* for bring up, disable dp double TODO */ + if (REG(HDMI_DB_CONTROL)) + REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); + + dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); + dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); + dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); + dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); + dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); + } +#endif } static void dce110_stream_encoder_stop_hdmi_info_packets( @@ -558,6 +787,26 @@ static void dce110_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC1_LINE, 0, HDMI_GENERIC1_SEND, 0); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* stop generic packets 2 & 3 on HDMI */ + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, + HDMI_GENERIC0_CONT, 0, + HDMI_GENERIC0_LINE, 0, + HDMI_GENERIC0_SEND, 0, + HDMI_GENERIC1_CONT, 0, + HDMI_GENERIC1_LINE, 0, + HDMI_GENERIC1_SEND, 0); + + if (REG(HDMI_GENERIC_PACKET_CONTROL3)) + REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, + HDMI_GENERIC0_CONT, 0, + HDMI_GENERIC0_LINE, 0, + HDMI_GENERIC0_SEND, 0, + HDMI_GENERIC1_CONT, 0, + HDMI_GENERIC1_LINE, 0, + HDMI_GENERIC1_SEND, 0); +#endif } static void dce110_stream_encoder_update_dp_info_packets( @@ -621,6 +870,21 @@ static void dce110_stream_encoder_stop_dp_info_packets( DP_SEC_STREAM_ENABLE, 0); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->DP_SEC_GSP7_ENABLE) { + REG_SET_10(DP_SEC_CNTL, 0, + DP_SEC_GSP0_ENABLE, 0, + DP_SEC_GSP1_ENABLE, 0, + DP_SEC_GSP2_ENABLE, 0, + DP_SEC_GSP3_ENABLE, 0, + DP_SEC_GSP4_ENABLE, 0, + DP_SEC_GSP5_ENABLE, 0, + DP_SEC_GSP6_ENABLE, 0, + DP_SEC_GSP7_ENABLE, 0, + DP_SEC_MPG_ENABLE, 0, + DP_SEC_STREAM_ENABLE, 0); + } +#endif /* this register shared with audio info frame. * therefore we need to keep master enabled * if at least one of the fields is not 0 */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index 850e12a8db61..0b548cb3af14 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -97,6 +97,23 @@ SE_COMMON_REG_LIST_DCE_BASE(id), \ SRI(AFMT_CNTL, DIG, id) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define SE_DCN_REG_LIST(id)\ + SE_COMMON_REG_LIST_BASE(id),\ + SRI(AFMT_CNTL, DIG, id),\ + SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\ + SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ + SRI(DP_DB_CNTL, DP, id), \ + SRI(DP_MSA_MISC, DP, id), \ + SRI(DP_MSA_COLORIMETRY, DP, id), \ + SRI(DP_MSA_TIMING_PARAM1, DP, id), \ + SRI(DP_MSA_TIMING_PARAM2, DP, id), \ + SRI(DP_MSA_TIMING_PARAM3, DP, id), \ + SRI(DP_MSA_TIMING_PARAM4, DP, id), \ + SRI(HDMI_DB_CONTROL, DIG, id) +#endif + #define SE_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -311,6 +328,48 @@ SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ + SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ + SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh) +#endif + struct dce_stream_encoder_shift { uint8_t AFMT_GENERIC_INDEX; uint8_t AFMT_GENERIC0_UPDATE; @@ -625,6 +684,16 @@ struct dce110_stream_enc_registers { uint32_t HDMI_ACR_48_0; uint32_t HDMI_ACR_48_1; uint32_t TMDS_CNTL; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + uint32_t DP_DB_CNTL; + uint32_t DP_MSA_MISC; + uint32_t DP_MSA_COLORIMETRY; + uint32_t DP_MSA_TIMING_PARAM1; + uint32_t DP_MSA_TIMING_PARAM2; + uint32_t DP_MSA_TIMING_PARAM3; + uint32_t DP_MSA_TIMING_PARAM4; + uint32_t HDMI_DB_CONTROL; +#endif }; struct dce110_stream_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index dc4c16416370..c89df8acb458 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -947,6 +947,12 @@ static void program_scaler(const struct core_dc *dc, { struct tg_color color = {0}; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* TOFPGA */ + if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL) + return; +#endif + if (dc->public.debug.surface_visual_confirm) get_surface_visual_confirm_color(pipe_ctx, &color); else @@ -1113,6 +1119,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( program_scaler(dc, pipe_ctx); /* mst support - use total stream count */ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (pipe_ctx->mi->funcs->allocate_mem_input != NULL) +#endif pipe_ctx->mi->funcs->allocate_mem_input( pipe_ctx->mi, stream->public.timing.h_total, @@ -1637,6 +1646,26 @@ enum dc_status dce110_apply_ctx_to_hw( /*TODO: when pplib works*/ apply_min_clocks(dc, context, &clocks_state, true); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (context->fclk_khz + > dc->current_context->fclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; + clock.clocks_in_khz = context->fclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->fclk_khz = clock.clocks_in_khz; + } + if (context->dcfclk_khz + > dc->current_context->dcfclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock.clocks_in_khz = context->dcfclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->dcfclk_khz = clock.clocks_in_khz; + } +#endif if (context->dispclk_khz > dc->current_context->dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index cf6ecfcadd5e..fb61e333aefd 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -75,6 +75,10 @@ BREAK_TO_DEBUGGER(); \ } while (0) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include +#endif + #define dm_alloc(size) kzalloc(size, GFP_KERNEL) #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) #define dm_free(ptr) kfree(ptr) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 408141c6776e..b28304531d8a 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -69,6 +69,7 @@ enum dm_pp_clock_type { DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */ DM_PP_CLOCK_TYPE_MEMORY_CLK, DM_PP_CLOCK_TYPE_DCFCLK, + DM_PP_CLOCK_TYPE_DCEFCLK, DM_PP_CLOCK_TYPE_SOCCLK, DM_PP_CLOCK_TYPE_PIXELCLK, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 5e831aff4830..70d01a9e9676 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -37,6 +37,17 @@ AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) +############################################################################### +# DCN 1x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o + +AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) + +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10) +endif + ############################################################################### # Diagnostics on FPGA ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 29ba83d2c211..8a8b619a60a8 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -43,8 +43,10 @@ #include "dce80/hw_factory_dce80.h" #include "dce110/hw_factory_dce110.h" - #include "dce120/hw_factory_dce120.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/hw_factory_dcn10.h" +#endif #include "diagnostics/hw_factory_diag.h" @@ -77,6 +79,11 @@ bool dal_hw_factory_init( case DCE_VERSION_12_0: dal_hw_factory_dce120_init(factory); return true; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + dal_hw_factory_dcn10_init(factory); + return true; +#endif default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 872edda54536..36c082bda4ae 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -43,6 +43,10 @@ #include "dce80/hw_translate_dce80.h" #include "dce110/hw_translate_dce110.h" #include "dce120/hw_translate_dce120.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/hw_translate_dcn10.h" +#endif + #include "diagnostics/hw_translate_diag.h" /* @@ -71,6 +75,11 @@ bool dal_hw_translate_init( case DCE_VERSION_12_0: dal_hw_translate_dce120_init(translate); return true; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + dal_hw_translate_dcn10_init(translate); + return true; +#endif default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index a636768d06d5..55603400acd9 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -47,6 +47,17 @@ AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) +############################################################################### +# DCN 1.0 family +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +I2CAUX_DCN1 = i2caux_dcn10.o + +AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1)) + +AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCN1) +endif + ############################################################################### # DCE 120 family ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index 0743265e933c..983645b1be78 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -59,6 +59,10 @@ #include "dce120/i2caux_dce120.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/i2caux_dcn10.h" +#endif + #include "diagnostics/i2caux_diag.h" /* @@ -84,6 +88,10 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce100_create(ctx); case DCE_VERSION_12_0: return dal_i2caux_dce120_create(ctx); + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + return dal_i2caux_dcn10_create(ctx); + #endif default: BREAK_TO_DEBUGGER(); return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index f9363f642f92..392cff2cd558 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -30,6 +30,11 @@ struct core_dc { /* Inputs into BW and WM calculations. */ struct bw_calcs_dceip bw_dceip; struct bw_calcs_vbios bw_vbios; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box dcn_soc; + struct dcn_ip_params dcn_ip; + struct display_mode_lib dml; +#endif /* HW functions */ struct hw_sequencer_funcs hwss; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 9e5e0ba5b10b..c1273d6142c4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -28,8 +28,11 @@ #include "dc.h" #include "dce_calcs.h" +#include "dcn_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" +#include "mem_input.h" +#include "mpc.h" struct core_stream; @@ -254,6 +257,7 @@ struct resource_pool { struct abm *abm; struct dmcu *dmcu; + struct mpc *mpc; const struct resource_funcs *funcs; const struct resource_caps *res_cap; @@ -287,10 +291,20 @@ struct pipe_ctx { struct pipe_ctx *top_pipe; struct pipe_ctx *bottom_pipe; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + uint8_t mpc_idx; + struct _vcs_dpi_display_dlg_regs_st dlg_regs; + struct _vcs_dpi_display_ttu_regs_st ttu_regs; + struct _vcs_dpi_display_rq_regs_st rq_regs; + struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; +#endif }; struct resource_context { struct pipe_ctx pipe_ctx[MAX_PIPES]; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct mpc_tree_cfg mpc_tree[MAX_PIPES]; +#endif bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; @@ -309,6 +323,18 @@ struct validate_context { /* Note: these are big structures, do *not* put on stack! */ struct dm_pp_display_configuration pp_display_cfg; int dispclk_khz; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + int dppclk_khz; + bool dppclk_div; + int dcfclk_khz; + int dcfclk_deep_sleep_khz; + int socclk_khz; + int fclk_khz; + int dram_ccm_us; + int min_active_dram_ccm_us; + struct dcn_watermark_set watermarks; + struct dcn_bw_internal_vars dcn_bw_vars; +#endif }; #endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index 97f26b55535f..240ab11d1d30 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -37,6 +37,13 @@ struct clocks_value { bool dispclk_notify_pplib_done; bool pixelclk_notify_pplib_done; bool phyclk_notigy_pplib_done; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + int dcfclock_in_khz; + int dppclk_in_khz; + int mclk_in_khz; + int phyclk_in_khz; + int common_vdd_level; +#endif }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 2d472d8ef555..0f952e5b3ae8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -122,6 +122,7 @@ struct ipp_funcs { struct input_pixel_processor *ipp, const struct pwl_params *params); + void (*ipp_destroy)(struct input_pixel_processor **ipp); }; #endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 179f5ad70f48..0880ce98c90c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -31,6 +31,30 @@ #include "dce/dce_mem_input.h" /* temporary */ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dml/display_mode_structs.h" + +struct cstate_pstate_watermarks_st { + uint32_t cstate_exit_ns; + uint32_t cstate_enter_plus_exit_ns; + uint32_t pstate_change_ns; +}; + +struct dcn_watermarks { + uint32_t pte_meta_urgent_ns; + uint32_t urgent_ns; + struct cstate_pstate_watermarks_st cstate_pstate; +}; + +struct dcn_watermark_set { + struct dcn_watermarks a; + struct dcn_watermarks b; + struct dcn_watermarks c; + struct dcn_watermarks d; +}; + +#endif + struct stutter_modes { bool enhanced; bool quad_dmif_buffer; @@ -52,6 +76,23 @@ struct mem_input { }; struct mem_input_funcs { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + void (*program_watermarks)( + struct mem_input *mem_input, + struct dcn_watermark_set *watermarks, + unsigned int refclk_period_ns); + + void (*mem_input_setup)( + struct mem_input *mem_input, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*disable_request)(struct mem_input *mem_input); + +#endif + void (*mem_input_program_display_marks)( struct mem_input *mem_input, struct bw_watermarks nbp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h new file mode 100644 index 000000000000..2e86ebe5eeda --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -0,0 +1,110 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MPC_H__ +#define __DC_MPC_H__ + +/* define the maximum number of pipes + * MAX_NUM_PIPPES = MAX_PIPES defined in core_type.h + */ +enum { + MAX_NUM_PIPPES = 6 +}; + +enum blend_mode { + DIGI_BYPASS = 0, /* digital bypass */ + TOP_PASSTHRU, /* top layer pass through */ + TOP_BLND /* top layer blend */ +}; + +/* This structure define the mpc tree configuration + * num_pipes - number of pipes of the tree + * opp_id - instance id of OPP to drive MPC + * dpp- array of DPP index + * mpcc - array of MPCC index + * mode - the most bottom layer MPCC mode control. + * All other layers need to be program to 3 + * + * The connection will be: + * mpcc[num_pipes-1]->mpcc[num_pipes-2]->...->mpcc[1]->mpcc[0]->OPP[opp_id] + * dpp[0]->mpcc[0] + * dpp[1]->mpcc[1] + * ... + * dpp[num_pipes-1]->mpcc[num_pipes-1] + * mpcc[0] is the most top layer of MPC tree, + * mpcc[num_pipes-1] is the most bottom layer. + */ + +struct mpc_tree_cfg { + uint8_t num_pipes; + uint8_t opp_id; + /* dpp pipes for blend */ + uint8_t dpp[MAX_NUM_PIPPES]; + /* mpcc insatnces for blend */ + uint8_t mpcc[MAX_NUM_PIPPES]; + enum blend_mode mode; +}; + +struct mpcc_blnd_cfg { + /* 0- perpixel alpha, 1- perpixel alpha combined with global gain, + * 2- global alpha + */ + uint8_t alpha_mode; + uint8_t global_gain; + uint8_t global_alpha; + bool overlap_only; + bool pre_multiplied_alpha; +}; + +struct mpcc_sm_cfg { + bool enable; + /* 0-single plane, 2-row subsampling, 4-column subsampling, + * 6-checkboard subsampling + */ + uint8_t sm_mode; + bool frame_alt; /* 0- disable, 1- enable */ + bool field_alt; /* 0- disable, 1- enable */ + /* 0-no force, 2-force frame polarity from top, + * 3-force frame polarity from bottom + */ + uint8_t force_next_frame_porlarity; + /* 0-no force, 2-force field polarity from top, + * 3-force field polarity from bottom + */ + uint8_t force_next_field_polarity; +}; + +struct mpcc_vupdate_lock_cfg { + bool cfg_lock; + bool adr_lock; + bool adr_cfg_lock; + bool cur0_lock; + bool cur1_lock; +}; + +struct mpc { + struct dc_context *ctx; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 92c99c3b9002..64d43257db96 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -27,6 +27,7 @@ #define __DAL_OPP_H__ #include "hw_shared.h" +#include "dc_hw_types.h" #include "transform.h" struct fixed31_32; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 00cdaaae455c..9f130affb31c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -91,10 +91,22 @@ enum crtc_state { CRTC_STATE_VBLANK = 0, CRTC_STATE_VACTIVE }; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct _dlg_otg_param { + int vstartup_start; + int vupdate_offset; + int vupdate_width; + int vready_offset; + enum signal_type signal; +}; +#endif struct timing_generator { const struct timing_generator_funcs *funcs; struct dc_bios *bp; struct dc_context *ctx; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct _dlg_otg_param dlg_otg_param; +#endif int inst; }; @@ -155,6 +167,10 @@ struct timing_generator_funcs { bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + void (*program_global_sync)(struct timing_generator *tg); + void (*enable_optc_clock)(struct timing_generator *tg, bool enable); +#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 222f36e3074f..c7e93f7223bd 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -36,3 +36,13 @@ AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) +############################################################################### +# DCN 1x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +IRQ_DCN1 = irq_service_dcn10.o + +AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1) +endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index 5255c14254df..0a1fae4ef83a 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -35,6 +35,11 @@ #include "dce120/irq_service_dce120.h" + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/irq_service_dcn10.h" +#endif + #include "reg_helper.h" #include "irq_service.h" diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 6dab058f8f3c..3d2ed5c83734 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -109,6 +109,19 @@ #define ASIC_REV_IS_STONEY(rev) \ ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +/* DCN1_0 */ +#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ +#define RAVEN_A0 0x01 +#define RAVEN_UNKNOWN 0xFF + +#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) +#endif + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define FAMILY_RV 142 /* DCN 1*/ +#endif + /* * ASIC chip ID */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index 0cefde14aa02..50a2a3ebf36d 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -39,7 +39,10 @@ enum dce_version { DCE_VERSION_11_0, DCE_VERSION_11_2, DCE_VERSION_12_0, - DCE_VERSION_MAX, +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + DCN_VERSION_1_0, +#endif + DCN_VERSION_MAX }; #endif /* __DAL_TYPES_H__ */ -- cgit v1.2.3-59-g8ed1b From 9037d802a97812cb8d614b48f817a5532cf1558c Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 2 May 2017 17:29:48 -0400 Subject: drm/amd/display: refactor bw related variable structure in val_ctx Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 18 ++--- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 79 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc.c | 20 +----- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 12 ++-- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 ++- .../drm/amd/display/dc/dce100/dce100_resource.c | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 65 +++++++++--------- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 12 ++-- .../drm/amd/display/dc/dce110/dce110_mem_input.h | 6 +- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 30 ++++---- .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 6 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 63 +++++++++-------- .../drm/amd/display/dc/dce112/dce112_resource.c | 63 +++++++++-------- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 38 +++++------ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 58 ++++++++++++---- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 29 +------- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 20 ++++-- 20 files changed, 270 insertions(+), 278 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 627b7582394a..87666987429e 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2557,7 +2557,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, */ static bool is_display_configuration_supported( const struct bw_calcs_vbios *vbios, - const struct bw_calcs_output *calcs_output) + const struct dce_bw_output *calcs_output) { uint32_t int_max_clk; @@ -2568,7 +2568,7 @@ static bool is_display_configuration_supported( int_max_clk = bw_fixed_to_int(vbios->high_sclk); int_max_clk *= 1000; /* MHz to kHz */ - if (calcs_output->required_sclk > int_max_clk) + if (calcs_output->sclk_khz > int_max_clk) return false; return true; @@ -2790,7 +2790,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_vbios *vbios, const struct pipe_ctx pipe[], int pipe_count, - struct bw_calcs_output *calcs_output) + struct dce_bw_output *calcs_output) { struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data)); @@ -2831,20 +2831,20 @@ bool bw_calcs(struct dc_context *ctx, bw_int_to_fixed(1000))); calcs_output->blackout_recovery_time_us = bw_fixed_to_int(data->blackout_recovery_time); - calcs_output->required_sclk = + calcs_output->sclk_khz = bw_fixed_to_int(bw_mul(data->required_sclk, bw_int_to_fixed(1000))); - calcs_output->required_sclk_deep_sleep = + calcs_output->sclk_deep_sleep_khz = bw_fixed_to_int(bw_mul(data->sclk_deep_sleep, bw_int_to_fixed(1000))); if (yclk_lvl == 0) - calcs_output->required_yclk = bw_fixed_to_int( + calcs_output->yclk_khz = bw_fixed_to_int( bw_mul(low_yclk, bw_int_to_fixed(1000))); else if (yclk_lvl == 1) - calcs_output->required_yclk = bw_fixed_to_int( + calcs_output->yclk_khz = bw_fixed_to_int( bw_mul(mid_yclk, bw_int_to_fixed(1000))); else - calcs_output->required_yclk = bw_fixed_to_int( + calcs_output->yclk_khz = bw_fixed_to_int( bw_mul(high_yclk, bw_int_to_fixed(1000))); /* units: nanosecond, 16bit storage. */ @@ -3245,7 +3245,7 @@ bool bw_calcs(struct dc_context *ctx, calcs_output->cpup_state_change_enable = true; calcs_output->stutter_mode_enable = true; calcs_output->dispclk_khz = 0; - calcs_output->required_sclk = 0; + calcs_output->sclk_khz = 0; } dm_free(data); diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 22d98ef69a77..1b9edfda2b98 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -470,17 +470,17 @@ static void dcn_dml_wm_override( a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count); a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent); - context->watermarks.a.cstate_pstate.cstate_exit_ns = + context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = a.cpstate.cstate_exit_us * 1000; - context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = + context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = a.cpstate.cstate_enter_plus_exit_us * 1000; - context->watermarks.a.cstate_pstate.pstate_change_ns = + context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = a.cpstate.pstate_change_us * 1000; - context->watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000; - context->watermarks.a.urgent_ns = a.urgent * 1000; - context->watermarks.b = context->watermarks.a; - context->watermarks.c = context->watermarks.a; - context->watermarks.d = context->watermarks.a; + context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000; + context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000; + context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a; + context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a; + context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { @@ -543,28 +543,28 @@ static void calc_wm_sets_and_perf_params( v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8; dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); - context->watermarks.b.cstate_pstate.cstate_exit_ns = + context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = v->stutter_exit_watermark * 1000; - context->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = + context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = v->stutter_enter_plus_exit_watermark * 1000; - context->watermarks.b.cstate_pstate.pstate_change_ns = + context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = v->dram_clock_change_watermark * 1000; - context->watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; - context->watermarks.b.urgent_ns = v->urgent_watermark * 1000; + context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; + context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000; v->dcfclk_per_state[1] = v->dcfclkv_nom0p8; v->dcfclk_per_state[0] = v->dcfclkv_nom0p8; v->dcfclk = v->dcfclkv_nom0p8; dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); - context->watermarks.c.cstate_pstate.cstate_exit_ns = + context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = v->stutter_exit_watermark * 1000; - context->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = + context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = v->stutter_enter_plus_exit_watermark * 1000; - context->watermarks.c.cstate_pstate.pstate_change_ns = + context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = v->dram_clock_change_watermark * 1000; - context->watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; - context->watermarks.c.urgent_ns = v->urgent_watermark * 1000; + context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; + context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000; } if (v->voltage_level < 3) { @@ -578,14 +578,14 @@ static void calc_wm_sets_and_perf_params( v->dcfclk = v->dcfclkv_max0p9; dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); - context->watermarks.d.cstate_pstate.cstate_exit_ns = + context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = v->stutter_exit_watermark * 1000; - context->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = + context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = v->stutter_enter_plus_exit_watermark * 1000; - context->watermarks.d.cstate_pstate.pstate_change_ns = + context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = v->dram_clock_change_watermark * 1000; - context->watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; - context->watermarks.d.urgent_ns = v->urgent_watermark * 1000; + context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; + context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000; } v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8; @@ -598,20 +598,20 @@ static void calc_wm_sets_and_perf_params( v->dcfclk = v->dcfclk_per_state[v->voltage_level]; dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); - context->watermarks.a.cstate_pstate.cstate_exit_ns = + context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = v->stutter_exit_watermark * 1000; - context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = + context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = v->stutter_enter_plus_exit_watermark * 1000; - context->watermarks.a.cstate_pstate.pstate_change_ns = + context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = v->dram_clock_change_watermark * 1000; - context->watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; - context->watermarks.a.urgent_ns = v->urgent_watermark * 1000; + context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; + context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; if (v->voltage_level >= 2) { - context->watermarks.b = context->watermarks.a; - context->watermarks.c = context->watermarks.a; + context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a; + context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a; } if (v->voltage_level >= 3) - context->watermarks.d = context->watermarks.a; + context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; } static bool dcn_bw_apply_registry_override(struct core_dc *dc) @@ -916,17 +916,16 @@ bool dcn_validate_bandwidth( display_pipe_configuration(v); calc_wm_sets_and_perf_params(context, v); - context->fclk_khz = (int)(bw_consumed * 1000000 / + context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / (ddr4_dram_factor_single_Channel * v->number_of_channels)); - context->dram_ccm_us = (int)(v->dram_clock_change_margin); - context->min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin); - context->dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); - context->dcfclk_khz = (int)(v->dcfclk * 1000); - context->dispclk_khz = (int)(v->dispclk * 1000); + context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin); + context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin); + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); + context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000); + context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000); if (dc->public.debug.max_disp_clk == true) - context->dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000); - context->dppclk_khz = (int)(v->dppclk * 1000); - context->dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; + context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000); + context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d063a252ccd9..b30d4bc7b040 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -970,13 +970,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; struct core_dc *core_dc = DC_TO_CORE(dc); - struct validate_context *context = dm_alloc(sizeof(struct validate_context)); - - if (!context) { - dm_error("%s: failed to create validate ctx\n", __func__); - return false; - } - dc_resource_validate_ctx_copy_construct(core_dc->current_context, context); + struct validate_context *context = core_dc->current_context; post_surface_trace(dc); @@ -986,21 +980,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) core_dc->hwss.power_down_front_end( core_dc, &context->res_ctx.pipe_ctx[i]); } - if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { - BREAK_TO_DEBUGGER(); - dc_resource_validate_ctx_destruct(context); - dm_free(context); - return false; - } core_dc->hwss.set_bandwidth(core_dc, context, true); - if (core_dc->current_context) { - dc_resource_validate_ctx_destruct(core_dc->current_context); - dm_free(core_dc->current_context); - } - core_dc->current_context = context; - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 884f453d91b0..9da539db287c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -218,9 +218,9 @@ static void program_stutter_watermark(struct mem_input *mi, } void dce_mem_input_program_display_marks(struct mem_input *mi, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns) { uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index 6af533bdf98c..be37f52e9ba1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -25,6 +25,10 @@ #ifndef __DCE_MEM_INPUT_H__ #define __DCE_MEM_INPUT_H__ +#include "dc_hw_types.h" +struct dce_watermarks; +struct mem_input; + #define MI_DCE_BASE_REG_LIST(id)\ SRI(GRPH_ENABLE, DCP, id),\ SRI(GRPH_CONTROL, DCP, id),\ @@ -262,8 +266,6 @@ struct dce_mem_input_wa { uint8_t single_head_rdreq_dmif_limit; }; -struct mem_input; - void dce_mem_input_program_pte_vm(struct mem_input *mi, enum surface_pixel_format format, union dc_tiling_info *tiling_info, @@ -288,9 +290,9 @@ void dce_mem_input_free_dmif(struct mem_input *mi, uint32_t total_stream_num); void dce_mem_input_program_display_marks(struct mem_input *mi, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns); #endif /*__DCE_MEM_INPUT_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index 30c197f378dc..843f50a08e21 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -114,7 +114,7 @@ static void dce100_pplib_apply_display_requirements( pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); - pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk + pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz / MEMORY_TYPE_MULTIPLIER; dce110_fill_display_configs(context, pp_display_cfg); @@ -131,12 +131,11 @@ void dce100_set_bandwidth( struct validate_context *context, bool decrease_allowed) { - if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, - context->dispclk_khz * 115 / 100); - dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; - dc->current_context->dispclk_khz = context->dispclk_khz; + context->bw.dce.dispclk_khz * 115 / 100); + dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } dce100_pplib_apply_display_requirements(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index f0700706d7c9..254f9e4d0fc8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -764,8 +764,8 @@ bool dce100_validate_bandwidth( struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ - context->dispclk_khz = 681000; - context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; + context->bw.dce.dispclk_khz = 681000; + context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c89df8acb458..41aeceba5ae5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1252,17 +1252,17 @@ void dce110_set_displaymarks( dc->bw_vbios.blackout_duration, pipe_ctx->stream); pipe_ctx->mi->funcs->mem_input_program_display_marks( pipe_ctx->mi, - context->bw_results.nbp_state_change_wm_ns[num_pipes], - context->bw_results.stutter_exit_wm_ns[num_pipes], - context->bw_results.urgent_wm_ns[num_pipes], + context->bw.dce.nbp_state_change_wm_ns[num_pipes], + context->bw.dce.stutter_exit_wm_ns[num_pipes], + context->bw.dce.urgent_wm_ns[num_pipes], total_dest_line_time_ns); if (i == underlay_idx) { num_pipes++; pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( pipe_ctx->mi, - context->bw_results.nbp_state_change_wm_ns[num_pipes], - context->bw_results.stutter_exit_wm_ns[num_pipes], - context->bw_results.urgent_wm_ns[num_pipes], + context->bw.dce.nbp_state_change_wm_ns[num_pipes], + context->bw.dce.stutter_exit_wm_ns[num_pipes], + context->bw.dce.urgent_wm_ns[num_pipes], total_dest_line_time_ns); } num_pipes++; @@ -1275,9 +1275,9 @@ static void set_safe_displaymarks( { int i; int underlay_idx = pool->underlay_pipe_index; - struct bw_watermarks max_marks = { + struct dce_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; - struct bw_watermarks nbp_marks = { + struct dce_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; for (i = 0; i < MAX_PIPES; i++) { @@ -1502,7 +1502,7 @@ static void apply_min_clocks( /* get the required state based on state dependent clocks: * display clock and pixel clock */ - req_clocks.display_clk_khz = context->dispclk_khz; + req_clocks.display_clk_khz = context->bw.dce.dispclk_khz; req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( dc, context, true); @@ -1647,30 +1647,30 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (context->fclk_khz - > dc->current_context->fclk_khz) { + if (context->bw.dcn.calc_clk.fclk_khz + > dc->current_context->bw.dcn.calc_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; - clock.clocks_in_khz = context->fclk_khz; + clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->fclk_khz = clock.clocks_in_khz; + dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz; } - if (context->dcfclk_khz - > dc->current_context->dcfclk_khz) { + if (context->bw.dcn.calc_clk.dcfclk_khz + > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock.clocks_in_khz = context->dcfclk_khz; + clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->dcfclk_khz = clock.clocks_in_khz; + dc->current_context->bw.dcn.calc_clk.dcfclk_khz = clock.clocks_in_khz; } #endif - if (context->dispclk_khz - > dc->current_context->dispclk_khz) { + if (context->bw.dce.dispclk_khz + > dc->current_context->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, - context->dispclk_khz * 115 / 100); + context->bw.dce.dispclk_khz * 115 / 100); } /* program audio wall clock. use HDMI as clock source if HDMI * audio active. Otherwise, use DP as clock source @@ -2275,32 +2275,32 @@ static void pplib_apply_display_requirements( struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; pp_display_cfg->all_displays_in_sync = - context->bw_results.all_displays_in_sync; + context->bw.dce.all_displays_in_sync; pp_display_cfg->nb_pstate_switch_disable = - context->bw_results.nbp_state_change_enable == false; + context->bw.dce.nbp_state_change_enable == false; pp_display_cfg->cpu_cc6_disable = - context->bw_results.cpuc_state_change_enable == false; + context->bw.dce.cpuc_state_change_enable == false; pp_display_cfg->cpu_pstate_disable = - context->bw_results.cpup_state_change_enable == false; + context->bw.dce.cpup_state_change_enable == false; pp_display_cfg->cpu_pstate_separation_time = - context->bw_results.blackout_recovery_time_us; + context->bw.dce.blackout_recovery_time_us; - pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk + pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz / MEMORY_TYPE_MULTIPLIER; pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( dc, - context->bw_results.required_sclk); + context->bw.dce.sclk_khz); pp_display_cfg->min_engine_clock_deep_sleep_khz - = context->bw_results.required_sclk_deep_sleep; + = context->bw.dce.sclk_deep_sleep_khz; pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); /* TODO: dce11.2*/ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - pp_display_cfg->disp_clk_khz = context->dispclk_khz; + pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; dce110_fill_display_configs(context, pp_display_cfg); @@ -2329,12 +2329,11 @@ static void dce110_set_bandwidth( { dce110_set_displaymarks(dc, context); - if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, - context->dispclk_khz * 115 / 100); - dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; - dc->current_context->dispclk_khz = context->dispclk_khz; + context->bw.dce.dispclk_khz * 115 / 100); + dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } pplib_apply_display_requirements(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index a20feaedfca4..45e1a8d15d9b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -166,7 +166,7 @@ bool dce110_mem_input_program_surface_flip_and_addr( static void program_urgency_watermark( const struct dc_context *ctx, const uint32_t offset, - struct bw_watermarks marks_low, + struct dce_watermarks marks_low, uint32_t total_dest_line_time_ns) { /* register value */ @@ -224,7 +224,7 @@ static void program_urgency_watermark( static void program_stutter_watermark( const struct dc_context *ctx, const uint32_t offset, - struct bw_watermarks marks) + struct dce_watermarks marks) { /* register value */ uint32_t stutter_cntl = 0; @@ -289,7 +289,7 @@ static void program_stutter_watermark( static void program_nbp_watermark( const struct dc_context *ctx, const uint32_t offset, - struct bw_watermarks marks) + struct dce_watermarks marks) { uint32_t value; uint32_t addr; @@ -372,9 +372,9 @@ static void program_nbp_watermark( void dce110_mem_input_program_display_marks( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns) { struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h index 4aec18c94c49..5f10f266f096 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h @@ -55,9 +55,9 @@ bool dce110_mem_input_construct( */ void dce110_mem_input_program_display_marks( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 9c32b5bbdff5..02739d3efa97 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -679,7 +679,7 @@ static void program_urgency_watermark( const struct dc_context *ctx, const uint32_t urgency_addr, const uint32_t wm_addr, - struct bw_watermarks marks_low, + struct dce_watermarks marks_low, uint32_t total_dest_line_time_ns) { /* register value */ @@ -734,7 +734,7 @@ static void program_urgency_watermark( static void program_urgency_watermark_l( const struct dc_context *ctx, - struct bw_watermarks marks_low, + struct dce_watermarks marks_low, uint32_t total_dest_line_time_ns) { program_urgency_watermark( @@ -747,7 +747,7 @@ static void program_urgency_watermark_l( static void program_urgency_watermark_c( const struct dc_context *ctx, - struct bw_watermarks marks_low, + struct dce_watermarks marks_low, uint32_t total_dest_line_time_ns) { program_urgency_watermark( @@ -762,7 +762,7 @@ static void program_stutter_watermark( const struct dc_context *ctx, const uint32_t stutter_addr, const uint32_t wm_addr, - struct bw_watermarks marks) + struct dce_watermarks marks) { /* register value */ uint32_t stutter_cntl = 0; @@ -822,7 +822,7 @@ static void program_stutter_watermark( static void program_stutter_watermark_l( const struct dc_context *ctx, - struct bw_watermarks marks) + struct dce_watermarks marks) { program_stutter_watermark(ctx, mmDPGV0_PIPE_STUTTER_CONTROL, @@ -832,7 +832,7 @@ static void program_stutter_watermark_l( static void program_stutter_watermark_c( const struct dc_context *ctx, - struct bw_watermarks marks) + struct dce_watermarks marks) { program_stutter_watermark(ctx, mmDPGV1_PIPE_STUTTER_CONTROL, @@ -844,7 +844,7 @@ static void program_nbp_watermark( const struct dc_context *ctx, const uint32_t wm_mask_ctrl_addr, const uint32_t nbp_pstate_ctrl_addr, - struct bw_watermarks marks) + struct dce_watermarks marks) { uint32_t value; @@ -926,7 +926,7 @@ static void program_nbp_watermark( static void program_nbp_watermark_l( const struct dc_context *ctx, - struct bw_watermarks marks) + struct dce_watermarks marks) { program_nbp_watermark(ctx, mmDPGV0_WATERMARK_MASK_CONTROL, @@ -936,7 +936,7 @@ static void program_nbp_watermark_l( static void program_nbp_watermark_c( const struct dc_context *ctx, - struct bw_watermarks marks) + struct dce_watermarks marks) { program_nbp_watermark(ctx, mmDPGV1_WATERMARK_MASK_CONTROL, @@ -946,9 +946,9 @@ static void program_nbp_watermark_c( void dce110_mem_input_v_program_display_marks( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns) { program_urgency_watermark_l( @@ -968,9 +968,9 @@ void dce110_mem_input_v_program_display_marks( void dce110_mem_input_program_chroma_display_marks( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns) { program_urgency_watermark_c( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h index 44cf066279c0..b2667eefa3d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h @@ -38,9 +38,9 @@ bool dce110_mem_input_v_construct( */ void dce110_mem_input_v_program_display_marks( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 5b2b41efa5f0..041d11968566 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -875,9 +875,8 @@ bool dce110_validate_bandwidth( &dc->bw_vbios, context->res_ctx.pipe_ctx, dc->res_pool->pipe_count, - &context->bw_results)) + &context->bw.dce)) result = true; - context->dispclk_khz = context->bw_results.dispclk_khz; if (!result) dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, @@ -887,8 +886,8 @@ bool dce110_validate_bandwidth( context->streams[0]->public.timing.v_addressable, context->streams[0]->public.timing.pix_clk_khz); - if (memcmp(&dc->current_context->bw_results, - &context->bw_results, sizeof(context->bw_results))) { + if (memcmp(&dc->current_context->bw.dce, + &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( dc->ctx->logger, @@ -898,43 +897,43 @@ bool dce110_validate_bandwidth( "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" "stutMark_b: %d stutMark_a: %d\n", __func__, - context->bw_results.nbp_state_change_wm_ns[0].b_mark, - context->bw_results.nbp_state_change_wm_ns[0].a_mark, - context->bw_results.urgent_wm_ns[0].b_mark, - context->bw_results.urgent_wm_ns[0].a_mark, - context->bw_results.stutter_exit_wm_ns[0].b_mark, - context->bw_results.stutter_exit_wm_ns[0].a_mark); + context->bw.dce.nbp_state_change_wm_ns[0].b_mark, + context->bw.dce.nbp_state_change_wm_ns[0].a_mark, + context->bw.dce.urgent_wm_ns[0].b_mark, + context->bw.dce.urgent_wm_ns[0].a_mark, + context->bw.dce.stutter_exit_wm_ns[0].b_mark, + context->bw.dce.stutter_exit_wm_ns[0].a_mark); dm_logger_append(&log_entry, "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" "stutMark_b: %d stutMark_a: %d\n", - context->bw_results.nbp_state_change_wm_ns[1].b_mark, - context->bw_results.nbp_state_change_wm_ns[1].a_mark, - context->bw_results.urgent_wm_ns[1].b_mark, - context->bw_results.urgent_wm_ns[1].a_mark, - context->bw_results.stutter_exit_wm_ns[1].b_mark, - context->bw_results.stutter_exit_wm_ns[1].a_mark); + context->bw.dce.nbp_state_change_wm_ns[1].b_mark, + context->bw.dce.nbp_state_change_wm_ns[1].a_mark, + context->bw.dce.urgent_wm_ns[1].b_mark, + context->bw.dce.urgent_wm_ns[1].a_mark, + context->bw.dce.stutter_exit_wm_ns[1].b_mark, + context->bw.dce.stutter_exit_wm_ns[1].a_mark); dm_logger_append(&log_entry, "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", - context->bw_results.nbp_state_change_wm_ns[2].b_mark, - context->bw_results.nbp_state_change_wm_ns[2].a_mark, - context->bw_results.urgent_wm_ns[2].b_mark, - context->bw_results.urgent_wm_ns[2].a_mark, - context->bw_results.stutter_exit_wm_ns[2].b_mark, - context->bw_results.stutter_exit_wm_ns[2].a_mark, - context->bw_results.stutter_mode_enable); + context->bw.dce.nbp_state_change_wm_ns[2].b_mark, + context->bw.dce.nbp_state_change_wm_ns[2].a_mark, + context->bw.dce.urgent_wm_ns[2].b_mark, + context->bw.dce.urgent_wm_ns[2].a_mark, + context->bw.dce.stutter_exit_wm_ns[2].b_mark, + context->bw.dce.stutter_exit_wm_ns[2].a_mark, + context->bw.dce.stutter_mode_enable); dm_logger_append(&log_entry, "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", - context->bw_results.cpuc_state_change_enable, - context->bw_results.cpup_state_change_enable, - context->bw_results.nbp_state_change_enable, - context->bw_results.all_displays_in_sync, - context->bw_results.dispclk_khz, - context->bw_results.required_sclk, - context->bw_results.required_sclk_deep_sleep, - context->bw_results.required_yclk, - context->bw_results.blackout_recovery_time_us); + context->bw.dce.cpuc_state_change_enable, + context->bw.dce.cpup_state_change_enable, + context->bw.dce.nbp_state_change_enable, + context->bw.dce.all_displays_in_sync, + context->bw.dce.dispclk_khz, + context->bw.dce.sclk_khz, + context->bw.dce.sclk_deep_sleep_khz, + context->bw.dce.yclk_khz, + context->bw.dce.blackout_recovery_time_us); dm_logger_close(&log_entry); } return result; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 18c1b89a52be..0ed2616dd5cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -845,17 +845,16 @@ bool dce112_validate_bandwidth( &dc->bw_vbios, context->res_ctx.pipe_ctx, dc->res_pool->pipe_count, - &context->bw_results)) + &context->bw.dce)) result = true; - context->dispclk_khz = context->bw_results.dispclk_khz; if (!result) dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: Bandwidth validation failed!", __func__); - if (memcmp(&dc->current_context->bw_results, - &context->bw_results, sizeof(context->bw_results))) { + if (memcmp(&dc->current_context->bw.dce, + &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( dc->ctx->logger, @@ -865,43 +864,43 @@ bool dce112_validate_bandwidth( "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" "stutMark_b: %d stutMark_a: %d\n", __func__, - context->bw_results.nbp_state_change_wm_ns[0].b_mark, - context->bw_results.nbp_state_change_wm_ns[0].a_mark, - context->bw_results.urgent_wm_ns[0].b_mark, - context->bw_results.urgent_wm_ns[0].a_mark, - context->bw_results.stutter_exit_wm_ns[0].b_mark, - context->bw_results.stutter_exit_wm_ns[0].a_mark); + context->bw.dce.nbp_state_change_wm_ns[0].b_mark, + context->bw.dce.nbp_state_change_wm_ns[0].a_mark, + context->bw.dce.urgent_wm_ns[0].b_mark, + context->bw.dce.urgent_wm_ns[0].a_mark, + context->bw.dce.stutter_exit_wm_ns[0].b_mark, + context->bw.dce.stutter_exit_wm_ns[0].a_mark); dm_logger_append(&log_entry, "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" "stutMark_b: %d stutMark_a: %d\n", - context->bw_results.nbp_state_change_wm_ns[1].b_mark, - context->bw_results.nbp_state_change_wm_ns[1].a_mark, - context->bw_results.urgent_wm_ns[1].b_mark, - context->bw_results.urgent_wm_ns[1].a_mark, - context->bw_results.stutter_exit_wm_ns[1].b_mark, - context->bw_results.stutter_exit_wm_ns[1].a_mark); + context->bw.dce.nbp_state_change_wm_ns[1].b_mark, + context->bw.dce.nbp_state_change_wm_ns[1].a_mark, + context->bw.dce.urgent_wm_ns[1].b_mark, + context->bw.dce.urgent_wm_ns[1].a_mark, + context->bw.dce.stutter_exit_wm_ns[1].b_mark, + context->bw.dce.stutter_exit_wm_ns[1].a_mark); dm_logger_append(&log_entry, "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", - context->bw_results.nbp_state_change_wm_ns[2].b_mark, - context->bw_results.nbp_state_change_wm_ns[2].a_mark, - context->bw_results.urgent_wm_ns[2].b_mark, - context->bw_results.urgent_wm_ns[2].a_mark, - context->bw_results.stutter_exit_wm_ns[2].b_mark, - context->bw_results.stutter_exit_wm_ns[2].a_mark, - context->bw_results.stutter_mode_enable); + context->bw.dce.nbp_state_change_wm_ns[2].b_mark, + context->bw.dce.nbp_state_change_wm_ns[2].a_mark, + context->bw.dce.urgent_wm_ns[2].b_mark, + context->bw.dce.urgent_wm_ns[2].a_mark, + context->bw.dce.stutter_exit_wm_ns[2].b_mark, + context->bw.dce.stutter_exit_wm_ns[2].a_mark, + context->bw.dce.stutter_mode_enable); dm_logger_append(&log_entry, "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", - context->bw_results.cpuc_state_change_enable, - context->bw_results.cpup_state_change_enable, - context->bw_results.nbp_state_change_enable, - context->bw_results.all_displays_in_sync, - context->bw_results.dispclk_khz, - context->bw_results.required_sclk, - context->bw_results.required_sclk_deep_sleep, - context->bw_results.required_yclk, - context->bw_results.blackout_recovery_time_us); + context->bw.dce.cpuc_state_change_enable, + context->bw.dce.cpup_state_change_enable, + context->bw.dce.nbp_state_change_enable, + context->bw.dce.all_displays_in_sync, + context->bw.dce.dispclk_khz, + context->bw.dce.sclk_khz, + context->bw.dce.sclk_deep_sleep_khz, + context->bw.dce.yclk_khz, + context->bw.dce.blackout_recovery_time_us); dm_logger_close(&log_entry); } return result; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 0aa128e5ed84..5735914a8737 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -781,8 +781,8 @@ bool dce80_validate_bandwidth( struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ - context->dispclk_khz = 681000; - context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; + context->bw.dce.dispclk_khz = 681000; + context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 41a6fa507982..a62c4e72f21a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1428,7 +1428,7 @@ static void dcn10_power_on_fe( enable_dcfclk(dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->pix_clk_params.requested_pix_clk, - context->dppclk_div); + context->bw.dcn.calc_clk.dppclk_div); if (dc_surface) { dm_logger_write(dc->ctx->logger, LOG_DC, @@ -1530,7 +1530,7 @@ static void update_dchubp_dpp( dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->pix_clk_params.requested_pix_clk, - context->dppclk_div); + context->bw.dcn.calc_clk.dppclk_div); select_vtg(dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->tg->inst); @@ -1649,7 +1649,7 @@ static void program_all_pipe_in_tree( if (pipe_ctx->top_pipe == NULL) { /* watermark is for all pipes */ pipe_ctx->mi->funcs->program_watermarks( - pipe_ctx->mi, &context->watermarks, ref_clk_mhz); + pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz); lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst); } @@ -1679,16 +1679,16 @@ static void dcn10_pplib_apply_display_requirements( pp_display_cfg->all_displays_in_sync = false;/*todo*/ pp_display_cfg->nb_pstate_switch_disable = false; - pp_display_cfg->min_engine_clock_khz = context->dcfclk_khz; - pp_display_cfg->min_memory_clock_khz = context->fclk_khz; - pp_display_cfg->min_engine_clock_deep_sleep_khz = context->dcfclk_deep_sleep_khz; - pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->dcfclk_deep_sleep_khz; + pp_display_cfg->min_engine_clock_khz = context->bw.dcn.calc_clk.dcfclk_khz; + pp_display_cfg->min_memory_clock_khz = context->bw.dcn.calc_clk.fclk_khz; + pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; + pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; pp_display_cfg->avail_mclk_switch_time_us = - context->dram_ccm_us > 0 ? context->dram_ccm_us : 0; + context->bw.dcn.calc_clk.dram_ccm_us > 0 ? context->bw.dcn.calc_clk.dram_ccm_us : 0; pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = - context->min_active_dram_ccm_us > 0 ? context->min_active_dram_ccm_us : 0; - pp_display_cfg->min_dcfclock_khz = context->dcfclk_khz; - pp_display_cfg->disp_clk_khz = context->dispclk_khz; + context->bw.dcn.calc_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.calc_clk.min_active_dram_ccm_us : 0; + pp_display_cfg->min_dcfclock_khz = context->bw.dcn.calc_clk.dcfclk_khz; + pp_display_cfg->disp_clk_khz = context->bw.dcn.calc_clk.dispclk_khz; dce110_fill_display_configs(context, pp_display_cfg); if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( @@ -1755,22 +1755,22 @@ static void dcn10_set_bandwidth( if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) return; - if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { + if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz > dc->current_context->bw.dcn.calc_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, - context->dispclk_khz); - dc->current_context->dispclk_khz = context->dispclk_khz; + context->bw.dcn.calc_clk.dispclk_khz); + dc->current_context->bw.dcn.calc_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; } - if (decrease_allowed || context->dcfclk_khz > dc->current_context->dcfclk_khz) { + if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) { clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock.clocks_in_khz = context->dcfclk_khz; + clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); } - if (decrease_allowed || context->fclk_khz > dc->current_context->fclk_khz) { + if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.calc_clk.fclk_khz) { clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; - clock.clocks_in_khz = context->fclk_khz; + clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->fclk_khz = clock.clocks_in_khz ; + dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz; } dcn10_pplib_apply_display_requirements(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index bf89608b30e4..50b24456d495 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -820,9 +820,9 @@ static void program_watermarks( static void mem_input_program_display_marks( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns) { /* only for dce diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 919c6632ee3e..46bd0318e6be 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -31,8 +31,8 @@ #include "dcn_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mem_input.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mpc.h" #endif @@ -312,7 +312,48 @@ struct resource_context { bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; uint8_t dp_clock_source_ref_count; - }; +}; + +struct dce_bw_output { + bool cpuc_state_change_enable; + bool cpup_state_change_enable; + bool stutter_mode_enable; + bool nbp_state_change_enable; + bool all_displays_in_sync; + struct dce_watermarks urgent_wm_ns[MAX_PIPES]; + struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; + struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; + int sclk_khz; + int sclk_deep_sleep_khz; + int yclk_khz; + int dispclk_khz; + int blackout_recovery_time_us; +}; + +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 +struct dcn_bw_clocks { + int dispclk_khz; + bool dppclk_div; + int dcfclk_khz; + int dcfclk_deep_sleep_khz; + int fclk_khz; + int dram_ccm_us; + int min_active_dram_ccm_us; +}; + +struct dcn_bw_output { + struct dcn_bw_clocks cur_clk; + struct dcn_bw_clocks calc_clk; + struct dcn_watermark_set watermarks; +}; +#endif + +union bw_context { +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_bw_output dcn; +#endif + struct dce_bw_output dce; +}; struct validate_context { struct core_stream *streams[MAX_PIPES]; @@ -322,20 +363,11 @@ struct validate_context { struct resource_context res_ctx; /* The output from BW and WM calculations. */ - struct bw_calcs_output bw_results; + union bw_context bw; + /* Note: these are big structures, do *not* put on stack! */ struct dm_pp_display_configuration pp_display_cfg; - int dispclk_khz; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - int dppclk_khz; - bool dppclk_div; - int dcfclk_khz; - int dcfclk_deep_sleep_khz; - int socclk_khz; - int fclk_khz; - int dram_ccm_us; - int min_active_dram_ccm_us; - struct dcn_watermark_set watermarks; struct dcn_bw_internal_vars dcn_bw_vars; #endif }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 580dee95e57a..36c48f7d3f56 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -35,6 +35,7 @@ struct pipe_ctx; struct core_dc; struct validate_context; +struct dce_bw_output; enum bw_calcs_version { BW_CALCS_VERSION_INVALID, @@ -454,32 +455,6 @@ struct bw_calcs_data { struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; }; -/******************************************************************************* - * Output data structures. - ******************************************************************************/ -struct bw_watermarks { - uint32_t a_mark; - uint32_t b_mark; - uint32_t c_mark; - uint32_t d_mark; -}; - -struct bw_calcs_output { - bool cpuc_state_change_enable; - bool cpup_state_change_enable; - bool stutter_mode_enable; - bool nbp_state_change_enable; - bool all_displays_in_sync; - struct bw_watermarks urgent_wm_ns[6]; - struct bw_watermarks stutter_exit_wm_ns[6]; - struct bw_watermarks nbp_state_change_wm_ns[6]; - uint32_t required_sclk; - uint32_t required_sclk_deep_sleep; - uint32_t required_yclk; - uint32_t dispclk_khz; - int blackout_recovery_time_us; -}; - /** * Initialize structures with data which will NOT change at runtime. */ @@ -500,7 +475,7 @@ bool bw_calcs( const struct bw_calcs_vbios *vbios, const struct pipe_ctx *pipe, int pipe_count, - struct bw_calcs_output *calcs_output); + struct dce_bw_output *calcs_output); #endif /* __BANDWIDTH_CALCS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 0880ce98c90c..c4aea24d4574 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -27,7 +27,6 @@ #include "dc.h" #include "include/grph_object_id.h" -#include "inc/dce_calcs.h" #include "dce/dce_mem_input.h" /* temporary */ @@ -55,6 +54,13 @@ struct dcn_watermark_set { #endif +struct dce_watermarks { + int a_mark; + int b_mark; + int c_mark; + int d_mark; +}; + struct stutter_modes { bool enhanced; bool quad_dmif_buffer; @@ -95,16 +101,16 @@ struct mem_input_funcs { void (*mem_input_program_display_marks)( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns); void (*mem_input_program_chroma_display_marks)( struct mem_input *mem_input, - struct bw_watermarks nbp, - struct bw_watermarks stutter, - struct bw_watermarks urgent, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, uint32_t total_dest_line_time_ns); void (*allocate_mem_input)( -- cgit v1.2.3-59-g8ed1b From c66a54dc4a8403ab269568b3f964b0efd4052932 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 3 May 2017 11:40:40 -0400 Subject: drm/amd/display: switch to using calc_clk and cur_clk for dcn bw setting Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 50 +++++++++++------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 59 +++++++++++++++++----- 2 files changed, 79 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 41aeceba5ae5..150c8a4e7b61 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1647,24 +1647,38 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.calc_clk.fclk_khz) { - struct dm_pp_clock_for_voltage_req clock; - - clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; - clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; - dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz; - } - if (context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) { - struct dm_pp_clock_for_voltage_req clock; - - clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; - dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.calc_clk.dcfclk_khz = clock.clocks_in_khz; - } + if (resource_parse_asic_id(dc->ctx->asic_id) == DCN_VERSION_1_0) { + if (context->bw.dcn.calc_clk.fclk_khz + > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; + clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + } + if (context->bw.dcn.calc_clk.dcfclk_khz + > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + } + if (context->bw.dcn.calc_clk.dispclk_khz + > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dcn.calc_clk.dispclk_khz); + dc->current_context->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; + context->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; + } + } else #endif if (context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index a62c4e72f21a..f5638ad6e9fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1429,6 +1429,9 @@ static void dcn10_power_on_fe( pipe_ctx->pipe_idx, pipe_ctx->pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); + dc->current_context->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; if (dc_surface) { dm_logger_write(dc->ctx->logger, LOG_DC, @@ -1531,6 +1534,9 @@ static void update_dchubp_dpp( pipe_ctx->pipe_idx, pipe_ctx->pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); + dc->current_context->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; select_vtg(dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->tg->inst); @@ -1679,16 +1685,16 @@ static void dcn10_pplib_apply_display_requirements( pp_display_cfg->all_displays_in_sync = false;/*todo*/ pp_display_cfg->nb_pstate_switch_disable = false; - pp_display_cfg->min_engine_clock_khz = context->bw.dcn.calc_clk.dcfclk_khz; - pp_display_cfg->min_memory_clock_khz = context->bw.dcn.calc_clk.fclk_khz; - pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; - pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; + pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz; + pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz; + pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz; + pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz; pp_display_cfg->avail_mclk_switch_time_us = - context->bw.dcn.calc_clk.dram_ccm_us > 0 ? context->bw.dcn.calc_clk.dram_ccm_us : 0; + context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0; pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = - context->bw.dcn.calc_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.calc_clk.min_active_dram_ccm_us : 0; - pp_display_cfg->min_dcfclock_khz = context->bw.dcn.calc_clk.dcfclk_khz; - pp_display_cfg->disp_clk_khz = context->bw.dcn.calc_clk.dispclk_khz; + context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0; + pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz; + pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz; dce110_fill_display_configs(context, pp_display_cfg); if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( @@ -1755,22 +1761,51 @@ static void dcn10_set_bandwidth( if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) return; - if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz > dc->current_context->bw.dcn.calc_clk.dispclk_khz) { + if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz + > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.calc_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; + dc->current_context->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; } - if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) { + if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz + > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; } - if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.calc_clk.fclk_khz) { + if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz + > dc->current_context->bw.dcn.cur_clk.fclk_khz) { clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + } + if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz + > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { + dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; + context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz = + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; + } + /* Decrease in freq is increase in period so opposite comparison for dram_ccm */ + if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us + < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) { + dc->current_context->bw.dcn.calc_clk.dram_ccm_us = + context->bw.dcn.calc_clk.dram_ccm_us; + context->bw.dcn.cur_clk.dram_ccm_us = + context->bw.dcn.calc_clk.dram_ccm_us; + } + if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us + < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) { + dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us = + context->bw.dcn.calc_clk.min_active_dram_ccm_us; + context->bw.dcn.cur_clk.min_active_dram_ccm_us = + context->bw.dcn.calc_clk.min_active_dram_ccm_us; } dcn10_pplib_apply_display_requirements(dc, context); } -- cgit v1.2.3-59-g8ed1b From f46661dd42f3648b92eca73ba2c48f5d9a418b1b Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Tue, 9 May 2017 14:45:54 -0400 Subject: drm/amd/display: Move output transfer function to stream updates Signed-off-by: Amy Zhang Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 46 ++++++++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 14 +++---- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 - 5 files changed, 37 insertions(+), 29 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3c2554381a25..1e6952bde25b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -201,11 +201,10 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, - const struct dc_stream **stream, int num_streams) +static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -1182,7 +1181,6 @@ static enum surface_update_type det_surface_update( overall_type = type; if (u->in_transfer_func || - u->out_transfer_func || u->hdr_static_metadata) { if (overall_type < UPDATE_TYPE_MED) overall_type = UPDATE_TYPE_MED; @@ -1279,8 +1277,28 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* update current stream with the new updates */ if (stream_update) { - stream->public.src = stream_update->src; - stream->public.dst = stream_update->dst; + if ((stream_update->src.height != 0) && + (stream_update->src.width != 0)) + stream->public.src = stream_update->src; + + if ((stream_update->dst.height != 0) && + (stream_update->dst.width != 0)) + stream->public.dst = stream_update->dst; + + if (stream_update->out_transfer_func && + stream_update->out_transfer_func != + dc_stream->out_transfer_func) { + if (stream_update->out_transfer_func->type != + TF_TYPE_UNKNOWN) { + if (dc_stream->out_transfer_func != NULL) + dc_transfer_func_release + (dc_stream->out_transfer_func); + dc_transfer_func_retain(stream_update-> + out_transfer_func); + stream->public.out_transfer_func = + stream_update->out_transfer_func; + } + } } /* save update parameters into surface */ @@ -1361,13 +1379,6 @@ void dc_update_surfaces_and_stream(struct dc *dc, srf_updates[i].in_transfer_func; } - if (srf_updates[i].out_transfer_func && - srf_updates[i].out_transfer_func != dc_stream->out_transfer_func) { - if (dc_stream->out_transfer_func != NULL) - dc_transfer_func_release(dc_stream->out_transfer_func); - dc_transfer_func_retain(srf_updates[i].out_transfer_func); - stream->public.out_transfer_func = srf_updates[i].out_transfer_func; - } if (srf_updates[i].hdr_static_metadata) surface->public.hdr_static_ctx = *(srf_updates[i].hdr_static_metadata); @@ -1436,11 +1447,12 @@ void dc_update_surfaces_and_stream(struct dc *dc, pipe_ctx, pipe_ctx->surface); if (is_new_pipe_surface || - srf_updates[i].out_transfer_func) + (stream_update != NULL && + stream_update->out_transfer_func != + NULL)) { core_dc->hwss.set_output_transfer_func( - pipe_ctx, - pipe_ctx->surface, - pipe_ctx->stream); + pipe_ctx, pipe_ctx->stream); + } if (srf_updates[i].hdr_static_metadata) { resource_build_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c7e503a91f45..7dd145b6e927 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -122,7 +122,7 @@ struct dc_stream_funcs { const struct rect *dst); bool (*set_gamut_remap)(struct dc *dc, - const struct dc_stream **stream, int num_streams); + const struct dc_stream *stream); void (*set_static_screen_events)(struct dc *dc, const struct dc_stream **stream, @@ -265,7 +265,8 @@ struct dc_hdr_static_metadata { enum dc_transfer_func_type { TF_TYPE_PREDEFINED, TF_TYPE_DISTRIBUTED_POINTS, - TF_TYPE_BYPASS + TF_TYPE_BYPASS, + TF_TYPE_UNKNOWN }; struct dc_transfer_func_distributed_points { @@ -349,11 +350,8 @@ struct dc_surface_update { */ /* gamma TO BE REMOVED */ struct dc_gamma *gamma; - struct dc_hdr_static_metadata *hdr_static_metadata; struct dc_transfer_func *in_transfer_func; - struct dc_transfer_func *out_transfer_func; - - + struct dc_hdr_static_metadata *hdr_static_metadata; }; /* * This structure is filled in by dc_surface_get_status and contains @@ -473,11 +471,9 @@ struct dc_stream { }; struct dc_stream_update { - struct rect src; - struct rect dst; - + struct dc_transfer_func *out_transfer_func; }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 150c8a4e7b61..8a663003017c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -631,7 +631,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_surface *surface, /* Surface - To be removed */ const struct core_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index f5638ad6e9fc..6cb3924225da 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1301,11 +1301,13 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_surface *surface, const struct core_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; + if (opp == NULL) + return false; + opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->public.out_transfer_func && diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index afdb8605a30f..b53e1206dfb3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -80,7 +80,6 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct core_surface *surface, const struct core_stream *stream); void (*power_down)(struct core_dc *dc); -- cgit v1.2.3-59-g8ed1b From 4b28b76bfe14430a91de74a5cf9215f3c108acf9 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 11 May 2017 17:15:14 -0400 Subject: drm/amd/display: fix mpo blanking out on one of planes being set not visible Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 3 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++--- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++++++++++++++++++---- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 20 +++-------- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 8 ++--- 7 files changed, 51 insertions(+), 37 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 9da539db287c..0552fc5f7ecc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -403,8 +403,7 @@ void dce_mem_input_program_surface_config(struct mem_input *mi, union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - bool visible) + bool horizontal_mirror) { REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index be37f52e9ba1..4977f5f6e7e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -277,8 +277,7 @@ void dce_mem_input_program_surface_config(struct mem_input *mi, union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - bool visible); + bool horizontal_mirror); void dce_mem_input_allocate_dmif(struct mem_input *mi, uint32_t h_total, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 8a663003017c..20ad1cb263db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1986,8 +1986,9 @@ static void set_plane_config( &surface->public.plane_size, surface->public.rotation, NULL, - false, - pipe_ctx->surface->public.visible); + false); + if (mi->funcs->set_blank) + mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( @@ -2432,8 +2433,9 @@ static void dce110_program_front_end_for_pipe( &surface->public.plane_size, surface->public.rotation, NULL, - false, - pipe_ctx->surface->public.visible); + false); + if (mi->funcs->set_blank) + mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 02739d3efa97..78dd3ae3af5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -664,8 +664,7 @@ void dce110_mem_input_v_program_surface_config( union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizotal_mirror, - bool visible) + bool horizotal_mirror) { struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 6cb3924225da..28b47bed72cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -848,7 +848,7 @@ static void reset_front_end_for_pipe( unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst); - pipe_ctx->mi->funcs->disable_request(pipe_ctx->mi); + pipe_ctx->mi->funcs->set_blank(pipe_ctx->mi, true); wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx); @@ -1513,6 +1513,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); } +static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) +{ + if (pipe_ctx->surface->public.visible) + return true; + if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) + return true; + return false; +} + +static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) +{ + if (pipe_ctx->surface->public.visible) + return true; + if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) + return true; + return false; +} + +static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) +{ + if (pipe_ctx->surface->public.visible) + return true; + if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) + return true; + if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) + return true; + return false; +} + static void update_dchubp_dpp( struct core_dc *dc, struct pipe_ctx *pipe_ctx, @@ -1633,12 +1662,9 @@ static void update_dchubp_dpp( &size, surface->public.rotation, &surface->public.dcc, - surface->public.horizontal_mirror, - surface->public.visible); - - /* Only support one plane for now. */ - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !surface->public.visible); + surface->public.horizontal_mirror); + mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx)); } static void program_all_pipe_in_tree( @@ -1669,10 +1695,13 @@ static void program_all_pipe_in_tree( pipe_ctx->tg->funcs->program_global_sync( pipe_ctx->tg); + pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx)); update_dchubp_dpp(dc, pipe_ctx, context); + + /* Only support one plane for now. */ } if (pipe_ctx->bottom_pipe != NULL) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 50b24456d495..587ded13140b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -38,8 +38,9 @@ #define FN(reg_name, field_name) \ mi->mi_shift->field_name, mi->mi_mask->field_name -static void set_blank(struct dcn10_mem_input *mi, bool blank) +static void dcn_mi_set_blank(struct mem_input *mem_input, bool blank) { + struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); uint32_t blank_en = blank ? 1 : 0; REG_UPDATE_2(DCHUBP_CNTL, @@ -47,15 +48,6 @@ static void set_blank(struct dcn10_mem_input *mi, bool blank) HUBP_TTU_DISABLE, blank_en); } - -static void disable_request(struct mem_input *mem_input) -{ - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); - - /* To disable the requestors, set blank_en to 1 */ - set_blank(mi, true); -} - static void vready_workaround(struct mem_input *mem_input, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) { @@ -402,8 +394,7 @@ static void mem_input_program_surface_config( union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - bool visible) + bool horizontal_mirror) { struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); @@ -412,8 +403,6 @@ static void mem_input_program_surface_config( program_size_and_rotation( mi, rotation, format, plane_size, dcc, horizontal_mirror); program_pixel_format(mi, format); - - set_blank(mi, !visible); } static void program_requestor( @@ -573,7 +562,6 @@ static void mem_input_setup( /* otg is locked when this func is called. Register are double buffered. * disable the requestors is not needed */ - /* disable_request(mem_input); */ program_requestor(mem_input, rq_regs); program_deadline(mem_input, dlg_attr, ttu_attr); vready_workaround(mem_input, pipe_dest); @@ -1065,7 +1053,6 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { .mem_input_program_display_marks = mem_input_program_display_marks, .allocate_mem_input = NULL, .free_mem_input = NULL, - .disable_request = disable_request, .mem_input_program_surface_flip_and_addr = mem_input_program_surface_flip_and_addr, .mem_input_program_surface_config = @@ -1075,6 +1062,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { .program_watermarks = program_watermarks, .mem_input_update_dchub = mem_input_update_dchub, .mem_input_program_pte_vm = dcn_mem_input_program_pte_vm, + .set_blank = dcn_mi_set_blank, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index c4aea24d4574..79fbc60e21c9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -94,9 +94,6 @@ struct mem_input_funcs { struct _vcs_dpi_display_ttu_regs_st *ttu_regs, struct _vcs_dpi_display_rq_regs_st *rq_regs, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); - - void (*disable_request)(struct mem_input *mem_input); - #endif void (*mem_input_program_display_marks)( @@ -142,13 +139,14 @@ struct mem_input_funcs { union plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - bool visible); + bool horizontal_mirror); bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); void (*mem_input_update_dchub)(struct mem_input *mem_input, struct dchub_init_data *dh_data); + + void (*set_blank)(struct mem_input *mi, bool blank); }; #endif -- cgit v1.2.3-59-g8ed1b From c34892144d38eddb4499ac425c24455b1e34dd61 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 15 May 2017 08:31:51 -0400 Subject: drm/amd/display: dce 8 - 12 mem_input refactor to new style Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 306 +++++++++++++-- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 115 ++++-- .../drm/amd/display/dc/dce100/dce100_resource.c | 78 +--- drivers/gpu/drm/amd/display/dc/dce110/Makefile | 3 +- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 437 --------------------- .../drm/amd/display/dc/dce110/dce110_mem_input.h | 121 ------ .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 155 +++----- .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 66 +--- .../drm/amd/display/dc/dce110/dce110_resource.c | 58 +-- drivers/gpu/drm/amd/display/dc/dce112/Makefile | 2 +- .../drm/amd/display/dc/dce112/dce112_mem_input.c | 54 --- .../drm/amd/display/dc/dce112/dce112_mem_input.h | 38 -- .../drm/amd/display/dc/dce112/dce112_resource.c | 77 +--- drivers/gpu/drm/amd/display/dc/dce120/Makefile | 2 +- .../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 ---------------- .../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 -- .../drm/amd/display/dc/dce120/dce120_resource.c | 75 +--- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 3 +- .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 83 ---- .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.h | 36 -- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 78 +--- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 8 - 22 files changed, 476 insertions(+), 1696 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 0552fc5f7ecc..718688c41f7b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -23,18 +23,18 @@ * */ -#include "mem_input.h" +#include "dce_mem_input.h" #include "reg_helper.h" #include "basics/conversion.h" #define CTX \ - mi->ctx + dce_mi->base.ctx #define REG(reg)\ - mi->regs->reg + dce_mi->regs->reg #undef FN #define FN(reg_name, field_name) \ - mi->shifts->field_name, mi->masks->field_name + dce_mi->shifts->field_name, dce_mi->masks->field_name struct pte_setting { unsigned int bpp; @@ -130,11 +130,13 @@ static bool is_vert_scan(enum dc_rotation_angle rotation) } } -void dce_mem_input_program_pte_vm(struct mem_input *mi, +static void dce_mi_program_pte_vm( + struct mem_input *mi, enum surface_pixel_format format, union dc_tiling_info *tiling_info, enum dc_rotation_angle rotation) { + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format); enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp]; @@ -158,7 +160,8 @@ void dce_mem_input_program_pte_vm(struct mem_input *mi, DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff); } -static void program_urgency_watermark(struct mem_input *mi, +static void program_urgency_watermark( + struct dce_mem_input *dce_mi, uint32_t wm_select, uint32_t urgency_low_wm, uint32_t urgency_high_wm) @@ -171,7 +174,8 @@ static void program_urgency_watermark(struct mem_input *mi, URGENCY_HIGH_WATERMARK, urgency_high_wm); } -static void program_nbp_watermark(struct mem_input *mi, +static void program_nbp_watermark( + struct dce_mem_input *dce_mi, uint32_t wm_select, uint32_t nbp_wm) { @@ -202,7 +206,8 @@ static void program_nbp_watermark(struct mem_input *mi, } } -static void program_stutter_watermark(struct mem_input *mi, +static void program_stutter_watermark( + struct dce_mem_input *dce_mi, uint32_t wm_select, uint32_t stutter_mark) { @@ -217,41 +222,67 @@ static void program_stutter_watermark(struct mem_input *mi, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); } -void dce_mem_input_program_display_marks(struct mem_input *mi, +static void dce_mi_program_display_marks( + struct mem_input *mi, struct dce_watermarks nbp, struct dce_watermarks stutter, struct dce_watermarks urgent, uint32_t total_dest_line_time_ns) { + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; - program_urgency_watermark(mi, 0, /* set a */ + program_urgency_watermark(dce_mi, 2, /* set a */ urgent.a_mark, total_dest_line_time_ns); - program_urgency_watermark(mi, 1, /* set b */ + program_urgency_watermark(dce_mi, 1, /* set d */ + urgent.d_mark, total_dest_line_time_ns); + + REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE, stutter_en, + STUTTER_IGNORE_FBC, 1); + program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */ + program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */ + + program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */ + program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */ +} + +static void dce120_mi_program_display_marks(struct mem_input *mi, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns) +{ + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); + uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; + + program_urgency_watermark(dce_mi, 0, /* set a */ + urgent.a_mark, total_dest_line_time_ns); + program_urgency_watermark(dce_mi, 1, /* set b */ urgent.b_mark, total_dest_line_time_ns); - program_urgency_watermark(mi, 2, /* set c */ + program_urgency_watermark(dce_mi, 2, /* set c */ urgent.c_mark, total_dest_line_time_ns); - program_urgency_watermark(mi, 3, /* set d */ + program_urgency_watermark(dce_mi, 3, /* set d */ urgent.d_mark, total_dest_line_time_ns); REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, stutter_en, STUTTER_IGNORE_FBC, 1); - program_nbp_watermark(mi, 0, nbp.a_mark); /* set a */ - program_nbp_watermark(mi, 1, nbp.b_mark); /* set b */ - program_nbp_watermark(mi, 2, nbp.c_mark); /* set c */ - program_nbp_watermark(mi, 3, nbp.d_mark); /* set d */ - - program_stutter_watermark(mi, 0, stutter.a_mark); /* set a */ - program_stutter_watermark(mi, 1, stutter.b_mark); /* set b */ - program_stutter_watermark(mi, 2, stutter.c_mark); /* set c */ - program_stutter_watermark(mi, 3, stutter.d_mark); /* set d */ + program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */ + program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */ + program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */ + program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */ + + program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */ + program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */ + program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */ + program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */ } -static void program_tiling(struct mem_input *mi, - const union dc_tiling_info *info) +static void program_tiling( + struct dce_mem_input *dce_mi, const union dc_tiling_info *info) { - if (mi->masks->GRPH_SW_MODE) { /* GFX9 */ + if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ REG_UPDATE_6(GRPH_CONTROL, GRPH_SW_MODE, info->gfx9.swizzle, GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), @@ -265,7 +296,7 @@ static void program_tiling(struct mem_input *mi, */ } - if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ + if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, GRPH_BANK_WIDTH, info->gfx8.bank_width, @@ -285,7 +316,7 @@ static void program_tiling(struct mem_input *mi, static void program_size_and_rotation( - struct mem_input *mi, + struct dce_mem_input *dce_mi, enum dc_rotation_angle rotation, const union plane_size *plane_size) { @@ -326,7 +357,7 @@ static void program_size_and_rotation( } static void program_grph_pixel_format( - struct mem_input *mi, + struct dce_mem_input *dce_mi, enum surface_pixel_format format) { uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */ @@ -397,7 +428,8 @@ static void program_grph_pixel_format( GRPH_PRESCALE_B_SIGN, sign); } -void dce_mem_input_program_surface_config(struct mem_input *mi, +static void dce_mi_program_surface_config( + struct mem_input *mi, enum surface_pixel_format format, union dc_tiling_info *tiling_info, union plane_size *plane_size, @@ -405,14 +437,15 @@ void dce_mem_input_program_surface_config(struct mem_input *mi, struct dc_plane_dcc_param *dcc, bool horizontal_mirror) { + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1); - program_tiling(mi, tiling_info); - program_size_and_rotation(mi, rotation, plane_size); + program_tiling(dce_mi, tiling_info); + program_size_and_rotation(dce_mi, rotation, plane_size); if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN && format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) - program_grph_pixel_format(mi, format); + program_grph_pixel_format(dce_mi, format); } static uint32_t get_dmif_switch_time_us( @@ -461,12 +494,14 @@ static uint32_t get_dmif_switch_time_us( return frame_time; } -void dce_mem_input_allocate_dmif(struct mem_input *mi, +static void dce_mi_allocate_dmif( + struct mem_input *mi, uint32_t h_total, uint32_t v_total, uint32_t pix_clk_khz, uint32_t total_stream_num) { + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); const uint32_t retry_delay = 10; uint32_t retry_count = get_dmif_switch_time_us( h_total, @@ -497,18 +532,20 @@ void dce_mem_input_allocate_dmif(struct mem_input *mi, PIXEL_DURATION, pix_dur); } - if (mi->wa.single_head_rdreq_dmif_limit) { + if (dce_mi->wa.single_head_rdreq_dmif_limit) { uint32_t eanble = (total_stream_num > 1) ? 0 : - mi->wa.single_head_rdreq_dmif_limit; + dce_mi->wa.single_head_rdreq_dmif_limit; REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT, ENABLE, eanble); } } -void dce_mem_input_free_dmif(struct mem_input *mi, +static void dce_mi_free_dmif( + struct mem_input *mi, uint32_t total_stream_num) { + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); uint32_t buffers_allocated; uint32_t dmif_buffer_control; @@ -525,11 +562,204 @@ void dce_mem_input_free_dmif(struct mem_input *mi, DMIF_BUFFERS_ALLOCATION_COMPLETED, 1, 10, 3500); - if (mi->wa.single_head_rdreq_dmif_limit) { + if (dce_mi->wa.single_head_rdreq_dmif_limit) { uint32_t eanble = (total_stream_num > 1) ? 0 : - mi->wa.single_head_rdreq_dmif_limit; + dce_mi->wa.single_head_rdreq_dmif_limit; REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT, ENABLE, eanble); } } + + +static void program_sec_addr( + struct dce_mem_input *dce_mi, + PHYSICAL_ADDRESS_LOC address) +{ + /*high register MUST be programmed first*/ + REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0, + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, + address.high_part); + + REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, + GRPH_SECONDARY_SURFACE_ADDRESS, address.low_part >> 8, + GRPH_SECONDARY_DFQ_ENABLE, 0); +} + +static void program_pri_addr( + struct dce_mem_input *dce_mi, + PHYSICAL_ADDRESS_LOC address) +{ + /*high register MUST be programmed first*/ + REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, + address.high_part); + + REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0, + GRPH_PRIMARY_SURFACE_ADDRESS, + address.low_part >> 8); +} + + +static bool dce_mi_is_flip_pending(struct mem_input *mem_input) +{ + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input); + uint32_t update_pending; + + REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending); + if (update_pending) + return true; + + mem_input->current_address = mem_input->request_address; + return false; +} + +static bool dce_mi_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate) +{ + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input); + + /* TODO: Figure out if two modes are needed: + * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1 + * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1 + */ + REG_UPDATE(GRPH_UPDATE, + GRPH_UPDATE_LOCK, 1); + + if (flip_immediate) { + REG_UPDATE_2(GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1); + } else { + REG_UPDATE_2(GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); + } + + switch (address->type) { + case PLN_ADDR_TYPE_GRAPHICS: + if (address->grph.addr.quad_part == 0) + break; + program_pri_addr(dce_mi, address->grph.addr); + break; + case PLN_ADDR_TYPE_GRPH_STEREO: + if (address->grph_stereo.left_addr.quad_part == 0 + || address->grph_stereo.right_addr.quad_part == 0) + break; + program_pri_addr(dce_mi, address->grph_stereo.left_addr); + program_sec_addr(dce_mi, address->grph_stereo.right_addr); + break; + default: + /* not supported */ + BREAK_TO_DEBUGGER(); + break; + } + + mem_input->request_address = *address; + + if (flip_immediate) + mem_input->current_address = *address; + + REG_UPDATE(GRPH_UPDATE, + GRPH_UPDATE_LOCK, 0); + + return true; +} + +static void dce_mi_update_dchub(struct mem_input *mi, + struct dchub_init_data *dh_data) +{ + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); + /* TODO: port code from dal2 */ + switch (dh_data->fb_mode) { + case FRAME_BUFFER_MODE_ZFB_ONLY: + /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ + REG_UPDATE_2(DCHUB_FB_LOCATION, + FB_TOP, 0, + FB_BASE, 0x0FFFF); + + REG_UPDATE(DCHUB_AGP_BASE, + AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUB_AGP_BOT, + AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUB_AGP_TOP, + AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUB_AGP_BASE, + AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUB_AGP_BOT, + AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUB_AGP_TOP, + AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_LOCAL_ONLY: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUB_AGP_BASE, + AGP_BASE, 0); + + REG_UPDATE(DCHUB_AGP_BOT, + AGP_BOT, 0x03FFFF); + + REG_UPDATE(DCHUB_AGP_TOP, + AGP_TOP, 0); + break; + default: + break; + } + + dh_data->dchub_initialzied = true; + dh_data->dchub_info_valid = false; +} + +static struct mem_input_funcs dce_mi_funcs = { + .mem_input_program_display_marks = dce_mi_program_display_marks, + .allocate_mem_input = dce_mi_allocate_dmif, + .free_mem_input = dce_mi_free_dmif, + .mem_input_program_surface_flip_and_addr = + dce_mi_program_surface_flip_and_addr, + .mem_input_program_pte_vm = dce_mi_program_pte_vm, + .mem_input_program_surface_config = + dce_mi_program_surface_config, + .mem_input_is_flip_pending = dce_mi_is_flip_pending, + .mem_input_update_dchub = dce_mi_update_dchub +}; + + +void dce_mem_input_construct( + struct dce_mem_input *dce_mi, + struct dc_context *ctx, + int inst, + const struct dce_mem_input_registers *regs, + const struct dce_mem_input_shift *mi_shift, + const struct dce_mem_input_mask *mi_mask) +{ + dce_mi->base.ctx = ctx; + + dce_mi->base.inst = inst; + dce_mi->base.funcs = &dce_mi_funcs; + + dce_mi->regs = regs; + dce_mi->shifts = mi_shift; + dce_mi->masks = mi_mask; + +} + +void dce112_mem_input_construct( + struct dce_mem_input *dce_mi, + struct dc_context *ctx, + int inst, + const struct dce_mem_input_registers *regs, + const struct dce_mem_input_shift *mi_shift, + const struct dce_mem_input_mask *mi_mask) +{ + dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask); + dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index 4977f5f6e7e2..55481f5adcdf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -26,8 +26,10 @@ #define __DCE_MEM_INPUT_H__ #include "dc_hw_types.h" -struct dce_watermarks; -struct mem_input; +#include "mem_input.h" + +#define TO_DCE_MEM_INPUT(mem_input)\ + container_of(mem_input, struct dce_mem_input, base) #define MI_DCE_BASE_REG_LIST(id)\ SRI(GRPH_ENABLE, DCP, id),\ @@ -40,6 +42,12 @@ struct mem_input; SRI(HW_ROTATION, DCP, id),\ SRI(GRPH_SWAP_CNTL, DCP, id),\ SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ + SRI(GRPH_UPDATE, DCP, id),\ + SRI(GRPH_FLIP_CONTROL, DCP, id),\ + SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\ + SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\ + SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\ + SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\ SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\ SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\ SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\ @@ -67,7 +75,11 @@ struct mem_input; MI_DCE_PTE_REG_LIST(id),\ SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ - SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id) + SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\ + SR(DCHUB_FB_LOCATION),\ + SR(DCHUB_AGP_BASE),\ + SR(DCHUB_AGP_BOT),\ + SR(DCHUB_AGP_TOP) struct dce_mem_input_registers { /* DCP */ @@ -84,6 +96,12 @@ struct dce_mem_input_registers { uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; uint32_t DVMM_PTE_CONTROL; uint32_t DVMM_PTE_ARB_CONTROL; + uint32_t GRPH_UPDATE; + uint32_t GRPH_FLIP_CONTROL; + uint32_t GRPH_PRIMARY_SURFACE_ADDRESS; + uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + uint32_t GRPH_SECONDARY_SURFACE_ADDRESS; + uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; /* DMIF_PG */ uint32_t DPG_PIPE_ARBITRATION_CONTROL1; uint32_t DPG_WATERMARK_MASK_CONTROL; @@ -96,6 +114,11 @@ struct dce_mem_input_registers { uint32_t DMIF_BUFFER_CONTROL; /* MC_HUB */ uint32_t MC_HUB_RDREQ_DMIF_LIMIT; + /*DCHUB*/ + uint32_t DCHUB_FB_LOCATION; + uint32_t DCHUB_AGP_BASE; + uint32_t DCHUB_AGP_BOT; + uint32_t DCHUB_AGP_TOP; }; /* Set_Filed_for_Block */ @@ -129,9 +152,16 @@ struct dce_mem_input_registers { SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ - SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh) + SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\ + SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\ + SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\ + SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\ + SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh) #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, mask_sh),\ SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh) #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\ @@ -189,13 +219,22 @@ struct dce_mem_input_registers { SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) +#define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ + SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ + SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ + SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ + SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ + SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) + #define MI_DCE12_MASK_SH_LIST(mask_sh)\ MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ + SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\ MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ - MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_) + MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh) #define MI_REG_FIELD_LIST(type) \ type GRPH_ENABLE; \ @@ -232,6 +271,15 @@ struct dce_mem_input_registers { type GRPH_SE_ENABLE; \ type GRPH_NUM_SHADER_ENGINES; \ type GRPH_NUM_PIPES; \ + type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \ + type GRPH_SECONDARY_SURFACE_ADDRESS; \ + type GRPH_SECONDARY_DFQ_ENABLE; \ + type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \ + type GRPH_PRIMARY_SURFACE_ADDRESS; \ + type GRPH_SURFACE_UPDATE_PENDING; \ + type GRPH_SURFACE_UPDATE_IMMEDIATE_EN; \ + type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \ + type GRPH_UPDATE_LOCK; \ type PIXEL_DURATION; \ type URGENCY_WATERMARK_MASK; \ type PSTATE_CHANGE_WATERMARK_MASK; \ @@ -253,6 +301,11 @@ struct dce_mem_input_registers { type DMIF_BUFFERS_ALLOCATED; \ type DMIF_BUFFERS_ALLOCATION_COMPLETED; \ type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\ + type FB_BASE; \ + type FB_TOP; \ + type AGP_BASE; \ + type AGP_TOP; \ + type AGP_BOT; \ struct dce_mem_input_shift { MI_REG_FIELD_LIST(uint8_t) @@ -266,32 +319,30 @@ struct dce_mem_input_wa { uint8_t single_head_rdreq_dmif_limit; }; -void dce_mem_input_program_pte_vm(struct mem_input *mi, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - enum dc_rotation_angle rotation); - -void dce_mem_input_program_surface_config(struct mem_input *mi, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - union plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror); - -void dce_mem_input_allocate_dmif(struct mem_input *mi, - uint32_t h_total, - uint32_t v_total, - uint32_t pix_clk_khz, - uint32_t total_stream_num); - -void dce_mem_input_free_dmif(struct mem_input *mi, - uint32_t total_stream_num); - -void dce_mem_input_program_display_marks(struct mem_input *mi, - struct dce_watermarks nbp, - struct dce_watermarks stutter, - struct dce_watermarks urgent, - uint32_t total_dest_line_time_ns); +struct dce_mem_input { + struct mem_input base; + + const struct dce_mem_input_registers *regs; + const struct dce_mem_input_shift *shifts; + const struct dce_mem_input_mask *masks; + + struct dce_mem_input_wa wa; +}; + +void dce_mem_input_construct( + struct dce_mem_input *dce_mi, + struct dc_context *ctx, + int inst, + const struct dce_mem_input_registers *regs, + const struct dce_mem_input_shift *mi_shift, + const struct dce_mem_input_mask *mi_mask); + +void dce112_mem_input_construct( + struct dce_mem_input *dce_mi, + struct dc_context *ctx, + int inst, + const struct dce_mem_input_registers *regs, + const struct dce_mem_input_shift *mi_shift, + const struct dce_mem_input_mask *mi_mask); #endif /*__DCE_MEM_INPUT_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 254f9e4d0fc8..8f1fe95dd76c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -35,8 +35,8 @@ #include "irq/dce110/irq_service_dce110.h" #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" -#include "dce110/dce110_mem_input.h" -#include "dce110/dce110_mem_input_v.h" + +#include "dce/dce_mem_input.h" #include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce/dce_opp.h" @@ -123,51 +123,6 @@ static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { } }; -static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = { - { - .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - } -}; - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -510,28 +465,18 @@ static const struct dce_mem_input_mask mi_masks = { static struct mem_input *dce100_mem_input_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offset) + uint32_t inst) { - struct dce110_mem_input *mem_input110 = - dm_alloc(sizeof(struct dce110_mem_input)); + struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); - if (!mem_input110) + if (!dce_mi) { + BREAK_TO_DEBUGGER(); return NULL; - - if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) { - struct mem_input *mi = &mem_input110->base; - - mi->regs = &mi_regs[inst]; - mi->shifts = &mi_shifts; - mi->masks = &mi_masks; - mi->wa.single_head_rdreq_dmif_limit = 2; - return mi; } - BREAK_TO_DEBUGGER(); - dm_free(mem_input110); - return NULL; + dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); + dce_mi->wa.single_head_rdreq_dmif_limit = 2; + return &dce_mi->base; } static void dce100_transform_destroy(struct transform **xfm) @@ -671,7 +616,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -986,8 +931,7 @@ static bool construct( goto res_create_fail; } - pool->base.mis[i] = dce100_mem_input_create(ctx, i, - &dce100_mi_reg_offsets[i]); + pool->base.mis[i] = dce100_mem_input_create(ctx, i); if (pool->base.mis[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index c54bf0330701..98d956e2f218 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -3,8 +3,7 @@ # It provides the control and status of HW CRTC block. DCE110 = dce110_timing_generator.o \ -dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \ -dce110_resource.o \ +dce110_compressor.o dce110_hw_sequencer.o dce110_resource.o \ dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \ dce110_mem_input_v.o dce110_opp_v.o dce110_transform_v.o diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c deleted file mode 100644 index 45e1a8d15d9b..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#include "dm_services.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" -/* TODO: this needs to be looked at, used by Stella's workaround*/ -#include "gmc/gmc_8_2_d.h" -#include "gmc/gmc_8_2_sh_mask.h" - -#include "include/logger_interface.h" - -#include "dce110_mem_input.h" - -#define DCP_REG(reg) (reg + mem_input110->offsets.dcp) -#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif) -#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe) - -static void program_sec_addr( - struct dce110_mem_input *mem_input110, - PHYSICAL_ADDRESS_LOC address) -{ - uint32_t value = 0; - uint32_t temp; - - /*high register MUST be programmed first*/ - temp = address.high_part & - GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK; - set_reg_field_value(value, temp, - GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, - GRPH_SECONDARY_SURFACE_ADDRESS_HIGH); - dm_write_reg(mem_input110->base.ctx, - DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH), value); - - value = 0; - temp = address.low_part >> - GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT; - set_reg_field_value(value, temp, - GRPH_SECONDARY_SURFACE_ADDRESS, - GRPH_SECONDARY_SURFACE_ADDRESS); - dm_write_reg(mem_input110->base.ctx, - DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS), value); -} - -static void program_pri_addr( - struct dce110_mem_input *mem_input110, - PHYSICAL_ADDRESS_LOC address) -{ - uint32_t value = 0; - uint32_t temp; - - /*high register MUST be programmed first*/ - temp = address.high_part & - GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK; - set_reg_field_value(value, temp, - GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, - GRPH_PRIMARY_SURFACE_ADDRESS_HIGH); - dm_write_reg(mem_input110->base.ctx, - DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH), value); - - value = 0; - temp = address.low_part >> - GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT; - set_reg_field_value(value, temp, - GRPH_PRIMARY_SURFACE_ADDRESS, - GRPH_PRIMARY_SURFACE_ADDRESS); - dm_write_reg(mem_input110->base.ctx, - DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS), value); -} - -bool dce110_mem_input_is_flip_pending(struct mem_input *mem_input) -{ - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); - uint32_t value; - - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); - - if (get_reg_field_value(value, GRPH_UPDATE, - GRPH_SURFACE_UPDATE_PENDING)) - return true; - - mem_input->current_address = mem_input->request_address; - return false; -} - -bool dce110_mem_input_program_surface_flip_and_addr( - struct mem_input *mem_input, - const struct dc_plane_address *address, - bool flip_immediate) -{ - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); - - uint32_t value = 0; - uint32_t value_old = 0; - uint32_t lock_value = 0; - - lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); - set_reg_field_value(lock_value, 1, GRPH_UPDATE, GRPH_UPDATE_LOCK); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value); - - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL)); - value_old = value; - if (flip_immediate) { - set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); - set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); - } else { - set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN); - set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN); - } - if (value != value_old) { - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value); - } - - switch (address->type) { - case PLN_ADDR_TYPE_GRAPHICS: - if (address->grph.addr.quad_part == 0) - break; - program_pri_addr(mem_input110, address->grph.addr); - break; - case PLN_ADDR_TYPE_GRPH_STEREO: - if (address->grph_stereo.left_addr.quad_part == 0 - || address->grph_stereo.right_addr.quad_part == 0) - break; - program_pri_addr(mem_input110, address->grph_stereo.left_addr); - program_sec_addr(mem_input110, address->grph_stereo.right_addr); - break; - default: - /* not supported */ - BREAK_TO_DEBUGGER(); - break; - } - - mem_input->request_address = *address; - if (flip_immediate) - mem_input->current_address = *address; - - lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE)); - set_reg_field_value(lock_value, 0, GRPH_UPDATE, GRPH_UPDATE_LOCK); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value); - - return true; -} - -static void program_urgency_watermark( - const struct dc_context *ctx, - const uint32_t offset, - struct dce_watermarks marks_low, - uint32_t total_dest_line_time_ns) -{ - /* register value */ - uint32_t urgency_cntl = 0; - uint32_t wm_mask_cntl = 0; - - uint32_t urgency_addr = offset + mmDPG_PIPE_URGENCY_CONTROL; - uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL; - - /*Write mask to enable reading/writing of watermark set A*/ - wm_mask_cntl = dm_read_reg(ctx, wm_addr); - set_reg_field_value(wm_mask_cntl, - 1, - DPG_WATERMARK_MASK_CONTROL, - URGENCY_WATERMARK_MASK); - dm_write_reg(ctx, wm_addr, wm_mask_cntl); - - urgency_cntl = dm_read_reg(ctx, urgency_addr); - - set_reg_field_value( - urgency_cntl, - marks_low.d_mark, - DPG_PIPE_URGENCY_CONTROL, - URGENCY_LOW_WATERMARK); - - set_reg_field_value( - urgency_cntl, - total_dest_line_time_ns, - DPG_PIPE_URGENCY_CONTROL, - URGENCY_HIGH_WATERMARK); - dm_write_reg(ctx, urgency_addr, urgency_cntl); - - /*Write mask to enable reading/writing of watermark set B*/ - wm_mask_cntl = dm_read_reg(ctx, wm_addr); - set_reg_field_value(wm_mask_cntl, - 2, - DPG_WATERMARK_MASK_CONTROL, - URGENCY_WATERMARK_MASK); - dm_write_reg(ctx, wm_addr, wm_mask_cntl); - - urgency_cntl = dm_read_reg(ctx, urgency_addr); - - set_reg_field_value(urgency_cntl, - marks_low.a_mark, - DPG_PIPE_URGENCY_CONTROL, - URGENCY_LOW_WATERMARK); - - set_reg_field_value(urgency_cntl, - total_dest_line_time_ns, - DPG_PIPE_URGENCY_CONTROL, - URGENCY_HIGH_WATERMARK); - dm_write_reg(ctx, urgency_addr, urgency_cntl); -} - -static void program_stutter_watermark( - const struct dc_context *ctx, - const uint32_t offset, - struct dce_watermarks marks) -{ - /* register value */ - uint32_t stutter_cntl = 0; - uint32_t wm_mask_cntl = 0; - - uint32_t stutter_addr = offset + mmDPG_PIPE_STUTTER_CONTROL; - uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL; - - /*Write mask to enable reading/writing of watermark set A*/ - - wm_mask_cntl = dm_read_reg(ctx, wm_addr); - set_reg_field_value(wm_mask_cntl, - 1, - DPG_WATERMARK_MASK_CONTROL, - STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK); - dm_write_reg(ctx, wm_addr, wm_mask_cntl); - - stutter_cntl = dm_read_reg(ctx, stutter_addr); - - if (ctx->dc->debug.disable_stutter) { - set_reg_field_value(stutter_cntl, - 0, - DPG_PIPE_STUTTER_CONTROL, - STUTTER_ENABLE); - } else { - set_reg_field_value(stutter_cntl, - 1, - DPG_PIPE_STUTTER_CONTROL, - STUTTER_ENABLE); - } - - set_reg_field_value(stutter_cntl, - 1, - DPG_PIPE_STUTTER_CONTROL, - STUTTER_IGNORE_FBC); - - /*Write watermark set A*/ - set_reg_field_value(stutter_cntl, - marks.d_mark, - DPG_PIPE_STUTTER_CONTROL, - STUTTER_EXIT_SELF_REFRESH_WATERMARK); - dm_write_reg(ctx, stutter_addr, stutter_cntl); - - /*Write mask to enable reading/writing of watermark set B*/ - wm_mask_cntl = dm_read_reg(ctx, wm_addr); - set_reg_field_value(wm_mask_cntl, - 2, - DPG_WATERMARK_MASK_CONTROL, - STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK); - dm_write_reg(ctx, wm_addr, wm_mask_cntl); - - stutter_cntl = dm_read_reg(ctx, stutter_addr); - - /*Write watermark set B*/ - set_reg_field_value(stutter_cntl, - marks.a_mark, - DPG_PIPE_STUTTER_CONTROL, - STUTTER_EXIT_SELF_REFRESH_WATERMARK); - dm_write_reg(ctx, stutter_addr, stutter_cntl); -} - -static void program_nbp_watermark( - const struct dc_context *ctx, - const uint32_t offset, - struct dce_watermarks marks) -{ - uint32_t value; - uint32_t addr; - /* Write mask to enable reading/writing of watermark set A */ - addr = offset + mmDPG_WATERMARK_MASK_CONTROL; - value = dm_read_reg(ctx, addr); - set_reg_field_value( - value, - 1, - DPG_WATERMARK_MASK_CONTROL, - NB_PSTATE_CHANGE_WATERMARK_MASK); - dm_write_reg(ctx, addr, value); - - addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL; - value = dm_read_reg(ctx, addr); - set_reg_field_value( - value, - 1, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_ENABLE); - set_reg_field_value( - value, - 1, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_URGENT_DURING_REQUEST); - set_reg_field_value( - value, - 1, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST); - dm_write_reg(ctx, addr, value); - - /* Write watermark set A */ - value = dm_read_reg(ctx, addr); - set_reg_field_value( - value, - marks.d_mark, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_WATERMARK); - dm_write_reg(ctx, addr, value); - - /* Write mask to enable reading/writing of watermark set B */ - addr = offset + mmDPG_WATERMARK_MASK_CONTROL; - value = dm_read_reg(ctx, addr); - set_reg_field_value( - value, - 2, - DPG_WATERMARK_MASK_CONTROL, - NB_PSTATE_CHANGE_WATERMARK_MASK); - dm_write_reg(ctx, addr, value); - - addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL; - value = dm_read_reg(ctx, addr); - set_reg_field_value( - value, - 1, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_ENABLE); - set_reg_field_value( - value, - 1, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_URGENT_DURING_REQUEST); - set_reg_field_value( - value, - 1, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST); - dm_write_reg(ctx, addr, value); - - /* Write watermark set B */ - value = dm_read_reg(ctx, addr); - set_reg_field_value( - value, - marks.a_mark, - DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_WATERMARK); - dm_write_reg(ctx, addr, value); -} - -void dce110_mem_input_program_display_marks( - struct mem_input *mem_input, - struct dce_watermarks nbp, - struct dce_watermarks stutter, - struct dce_watermarks urgent, - uint32_t total_dest_line_time_ns) -{ - struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input); - - program_urgency_watermark( - mem_input->ctx, - bm_dce110->offsets.dmif, - urgent, - total_dest_line_time_ns); - - program_nbp_watermark( - mem_input->ctx, - bm_dce110->offsets.dmif, - nbp); - - program_stutter_watermark( - mem_input->ctx, - bm_dce110->offsets.dmif, - stutter); -} - -static struct mem_input_funcs dce110_mem_input_funcs = { - .mem_input_program_display_marks = - dce110_mem_input_program_display_marks, - .allocate_mem_input = dce_mem_input_allocate_dmif, - .free_mem_input = dce_mem_input_free_dmif, - .mem_input_program_surface_flip_and_addr = - dce110_mem_input_program_surface_flip_and_addr, - .mem_input_program_pte_vm = - dce_mem_input_program_pte_vm, - .mem_input_program_surface_config = - dce_mem_input_program_surface_config, - .mem_input_is_flip_pending = - dce110_mem_input_is_flip_pending, - .mem_input_update_dchub = NULL -}; -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -bool dce110_mem_input_construct( - struct dce110_mem_input *mem_input110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets) -{ - /* supported stutter method - * STUTTER_MODE_ENHANCED - * STUTTER_MODE_QUAD_DMIF_BUFFER - * STUTTER_MODE_WATERMARK_NBP_STATE - */ - mem_input110->base.funcs = &dce110_mem_input_funcs; - mem_input110->base.ctx = ctx; - - mem_input110->base.inst = inst; - - mem_input110->offsets = *offsets; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h deleted file mode 100644 index 5f10f266f096..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h +++ /dev/null @@ -1,121 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MEM_INPUT_DCE110_H__ -#define __DC_MEM_INPUT_DCE110_H__ - -#include "mem_input.h" - -#define TO_DCE110_MEM_INPUT(mi)\ - container_of(mi, struct dce110_mem_input, base) - -struct dce110_mem_input_reg_offsets { - uint32_t dcp; - uint32_t dmif; - uint32_t pipe; -}; - -struct dce110_mem_input { - struct mem_input base; - struct dce110_mem_input_reg_offsets offsets; -}; - -bool dce110_mem_input_construct( - struct dce110_mem_input *mem_input110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets); - -/* - * dce110_mem_input_program_display_marks - * - * This function will program nbp stutter and urgency watermarks to minimum - * allowable values - */ -void dce110_mem_input_program_display_marks( - struct mem_input *mem_input, - struct dce_watermarks nbp, - struct dce_watermarks stutter, - struct dce_watermarks urgent, - uint32_t total_dest_line_time_ns); - -/* - * dce110_allocate_mem_input - * - * This function will allocate a dmif buffer and program required - * pixel duration for pipe - */ -void dce110_allocate_mem_input( - struct mem_input *mem_input, - uint32_t h_total,/* for current stream */ - uint32_t v_total,/* for current stream */ - uint32_t pix_clk_khz,/* for current stream */ - uint32_t total_stream_num); - -/* - * dce110_free_mem_input - * - * This function will deallocate a dmif buffer from pipe - */ -void dce110_free_mem_input( - struct mem_input *mem_input, - uint32_t total_stream_num); - -/* - * dce110_mem_input_program_surface_flip_and_addr - * - * This function programs hsync/vsync mode and surface address - */ -bool dce110_mem_input_program_surface_flip_and_addr( - struct mem_input *mem_input, - const struct dc_plane_address *address, - bool flip_immediate); - -/* - * dce110_mem_input_program_surface_config - * - * This function will program surface tiling, size, rotation and pixel format - * to corresponding dcp registers. - */ -bool dce110_mem_input_program_surface_config( - struct mem_input *mem_input, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - union plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - bool visible); - -/* - * dce110_mem_input_is_flip_pending - * - * This function will wait until the surface update-pending bit is cleared. - * This is necessary when a flip immediate call is requested as we shouldn't - * return until the flip has actually occurred. - */ -bool dce110_mem_input_is_flip_pending( - struct mem_input *mem_input); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 78dd3ae3af5f..9777a4d961d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -33,29 +33,17 @@ #include "include/logger_interface.h" #include "inc/dce_calcs.h" -#include "dce110_mem_input.h" - -#define DCP_REG(reg) (reg + mem_input110->offsets.dcp) -/*#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)*/ -/*#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)*/ - -static const struct dce110_mem_input_reg_offsets dce110_mi_v_reg_offsets[] = { - { - .dcp = 0, - .dmif = 0, - .pipe = 0, - } -}; +#include "dce/dce_mem_input.h" static void set_flip_control( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, bool immediate) { uint32_t value = 0; value = dm_read_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_FLIP_CONTROL)); + mmUNP_FLIP_CONTROL); set_reg_field_value(value, 1, UNP_FLIP_CONTROL, @@ -63,13 +51,13 @@ static void set_flip_control( dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_FLIP_CONTROL), + mmUNP_FLIP_CONTROL, value); } /* chroma part */ static void program_pri_addr_c( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, PHYSICAL_ADDRESS_LOC address) { uint32_t value = 0; @@ -84,7 +72,7 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MAS dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C), + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C, value); temp = 0; @@ -98,13 +86,13 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MAS dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C), + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C, value); } /* luma part */ static void program_pri_addr_l( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, PHYSICAL_ADDRESS_LOC address) { uint32_t value = 0; @@ -120,7 +108,7 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MAS dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L), + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L, value); temp = 0; @@ -134,12 +122,12 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MAS dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L), + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L, value); } static void program_addr( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, const struct dc_plane_address *addr) { switch (addr->type) { @@ -162,19 +150,19 @@ static void program_addr( } } -static void enable(struct dce110_mem_input *mem_input110) +static void enable(struct dce_mem_input *mem_input110) { uint32_t value = 0; - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_ENABLE)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE); set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE); dm_write_reg(mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_ENABLE), + mmUNP_GRPH_ENABLE, value); } static void program_tiling( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, const union dc_tiling_info *info, const enum surface_pixel_format pixel_format) { @@ -239,7 +227,7 @@ static void program_tiling( } static void program_size_and_rotation( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, enum dc_rotation_angle rotation, const union plane_size *plane_size) { @@ -277,7 +265,7 @@ static void program_size_and_rotation( dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_PITCH_L), + mmUNP_GRPH_PITCH_L, value); value = 0; @@ -285,7 +273,7 @@ static void program_size_and_rotation( UNP_GRPH_PITCH_C, GRPH_PITCH_C); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_PITCH_C), + mmUNP_GRPH_PITCH_C, value); value = 0; @@ -293,7 +281,7 @@ static void program_size_and_rotation( UNP_GRPH_X_START_L, GRPH_X_START_L); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_X_START_L), + mmUNP_GRPH_X_START_L, value); value = 0; @@ -301,7 +289,7 @@ static void program_size_and_rotation( UNP_GRPH_X_START_C, GRPH_X_START_C); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_X_START_C), + mmUNP_GRPH_X_START_C, value); value = 0; @@ -309,7 +297,7 @@ static void program_size_and_rotation( UNP_GRPH_Y_START_L, GRPH_Y_START_L); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_Y_START_L), + mmUNP_GRPH_Y_START_L, value); value = 0; @@ -317,7 +305,7 @@ static void program_size_and_rotation( UNP_GRPH_Y_START_C, GRPH_Y_START_C); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_Y_START_C), + mmUNP_GRPH_Y_START_C, value); value = 0; @@ -326,7 +314,7 @@ static void program_size_and_rotation( UNP_GRPH_X_END_L, GRPH_X_END_L); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_X_END_L), + mmUNP_GRPH_X_END_L, value); value = 0; @@ -335,7 +323,7 @@ static void program_size_and_rotation( UNP_GRPH_X_END_C, GRPH_X_END_C); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_X_END_C), + mmUNP_GRPH_X_END_C, value); value = 0; @@ -344,7 +332,7 @@ static void program_size_and_rotation( UNP_GRPH_Y_END_L, GRPH_Y_END_L); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_Y_END_L), + mmUNP_GRPH_Y_END_L, value); value = 0; @@ -353,7 +341,7 @@ static void program_size_and_rotation( UNP_GRPH_Y_END_C, GRPH_Y_END_C); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_Y_END_C), + mmUNP_GRPH_Y_END_C, value); value = 0; @@ -378,12 +366,12 @@ static void program_size_and_rotation( dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_HW_ROTATION), + mmUNP_HW_ROTATION, value); } static void program_pixel_format( - struct dce110_mem_input *mem_input110, + struct dce_mem_input *mem_input110, enum surface_pixel_format format) { if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { @@ -393,7 +381,7 @@ static void program_pixel_format( value = dm_read_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_CONTROL)); + mmUNP_GRPH_CONTROL); switch (format) { case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: @@ -440,12 +428,12 @@ static void program_pixel_format( dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_CONTROL), + mmUNP_GRPH_CONTROL, value); value = dm_read_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_CONTROL_EXP)); + mmUNP_GRPH_CONTROL_EXP); /* VIDEO FORMAT 0 */ set_reg_field_value( @@ -455,7 +443,7 @@ static void program_pixel_format( VIDEO_FORMAT); dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_CONTROL_EXP), + mmUNP_GRPH_CONTROL_EXP, value); } else { @@ -465,7 +453,7 @@ static void program_pixel_format( value = dm_read_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_CONTROL_EXP)); + mmUNP_GRPH_CONTROL_EXP); switch (format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: @@ -487,17 +475,17 @@ static void program_pixel_format( dm_write_reg( mem_input110->base.ctx, - DCP_REG(mmUNP_GRPH_CONTROL_EXP), + mmUNP_GRPH_CONTROL_EXP, value); } } -bool dce110_mem_input_v_is_surface_pending(struct mem_input *mem_input) +bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input) { - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input); uint32_t value; - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_UPDATE)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE); if (get_reg_field_value(value, UNP_GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING)) @@ -507,12 +495,12 @@ bool dce110_mem_input_v_is_surface_pending(struct mem_input *mem_input) return false; } -bool dce110_mem_input_v_program_surface_flip_and_addr( +bool dce_mem_input_v_program_surface_flip_and_addr( struct mem_input *mem_input, const struct dc_plane_address *address, bool flip_immediate) { - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input); set_flip_control(mem_input110, flip_immediate); program_addr(mem_input110, @@ -584,13 +572,13 @@ static const unsigned int *get_dvmm_hw_setting( } } -void dce110_mem_input_v_program_pte_vm( +void dce_mem_input_v_program_pte_vm( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, enum dc_rotation_angle rotation) { - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input); const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); @@ -628,36 +616,36 @@ void dce110_mem_input_v_program_pte_vm( break; } - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT); /* TODO: un-hardcode requestlimit */ set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L); set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT), value); + dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value); - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL); set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH); set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT); set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL), value); + dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value); - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL); set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK); set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL), value); + dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value); - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL_C)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C); set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C); set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C); set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL_C), value); + dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value); - value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C)); + value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C); set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C); set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C); - dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C), value); + dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value); } -void dce110_mem_input_v_program_surface_config( +void dce_mem_input_v_program_surface_config( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, @@ -666,7 +654,7 @@ void dce110_mem_input_v_program_surface_config( struct dc_plane_dcc_param *dcc, bool horizotal_mirror) { - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); + struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input); enable(mem_input110); program_tiling(mem_input110, tiling_info, format); @@ -943,7 +931,7 @@ static void program_nbp_watermark_c( marks); } -void dce110_mem_input_v_program_display_marks( +void dce_mem_input_v_program_display_marks( struct mem_input *mem_input, struct dce_watermarks nbp, struct dce_watermarks stutter, @@ -965,7 +953,7 @@ void dce110_mem_input_v_program_display_marks( } -void dce110_mem_input_program_chroma_display_marks( +void dce_mem_input_program_chroma_display_marks( struct mem_input *mem_input, struct dce_watermarks nbp, struct dce_watermarks stutter, @@ -1036,42 +1024,29 @@ void dce110_free_mem_input_v( static struct mem_input_funcs dce110_mem_input_v_funcs = { .mem_input_program_display_marks = - dce110_mem_input_v_program_display_marks, + dce_mem_input_v_program_display_marks, .mem_input_program_chroma_display_marks = - dce110_mem_input_program_chroma_display_marks, + dce_mem_input_program_chroma_display_marks, .allocate_mem_input = dce110_allocate_mem_input_v, .free_mem_input = dce110_free_mem_input_v, .mem_input_program_surface_flip_and_addr = - dce110_mem_input_v_program_surface_flip_and_addr, + dce_mem_input_v_program_surface_flip_and_addr, .mem_input_program_pte_vm = - dce110_mem_input_v_program_pte_vm, + dce_mem_input_v_program_pte_vm, .mem_input_program_surface_config = - dce110_mem_input_v_program_surface_config, + dce_mem_input_v_program_surface_config, .mem_input_is_flip_pending = - dce110_mem_input_v_is_surface_pending + dce_mem_input_v_is_surface_pending }; /*****************************************/ /* Constructor, Destructor */ /*****************************************/ -bool dce110_mem_input_v_construct( - struct dce110_mem_input *mem_input110, +void dce110_mem_input_v_construct( + struct dce_mem_input *dce_mi, struct dc_context *ctx) { - mem_input110->base.funcs = &dce110_mem_input_v_funcs; - mem_input110->base.ctx = ctx; - - mem_input110->base.inst = 0; - - mem_input110->offsets = dce110_mi_v_reg_offsets[0]; - - return true; + dce_mi->base.funcs = &dce110_mem_input_v_funcs; + dce_mi->base.ctx = ctx; } -#if 0 -void dce110_mem_input_v_destroy(struct mem_input **mem_input) -{ - dm_free(TO_DCE110_MEM_INPUT(*mem_input)); - *mem_input = NULL; -} -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h index b2667eefa3d0..f01d4a607fea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h @@ -26,70 +26,10 @@ #define __DC_MEM_INPUT_V_DCE110_H__ #include "mem_input.h" -#include "dce110_mem_input.h" +#include "dce/dce_mem_input.h" -bool dce110_mem_input_v_construct( - struct dce110_mem_input *mem_input110, +void dce110_mem_input_v_construct( + struct dce_mem_input *dce_mi, struct dc_context *ctx); -/* - * This function will program nbp stutter and urgency watermarks to minimum - * allowable values - */ -void dce110_mem_input_v_program_display_marks( - struct mem_input *mem_input, - struct dce_watermarks nbp, - struct dce_watermarks stutter, - struct dce_watermarks urgent, - uint32_t total_dest_line_time_ns); - -/* - * This function will allocate a dmif buffer and program required - * pixel duration for pipe - */ -void dce110_allocate_mem_v_input( - struct mem_input *mem_input, - uint32_t h_total,/* for current stream */ - uint32_t v_total,/* for current stream */ - uint32_t pix_clk_khz,/* for current stream */ - uint32_t total_stream_num); - -/* - * This function will deallocate a dmif buffer from pipe - */ -void dce110_free_mem_v_input( - struct mem_input *mem_input, - uint32_t total_stream_num); - -/* - * This function programs hsync/vsync mode and surface address - */ -bool dce110_mem_input_v_program_surface_flip_and_addr( - struct mem_input *mem_input, - const struct dc_plane_address *address, - bool flip_immediate); - -/* - * dce110_mem_input_v_program_scatter_gather - * - * This function will program scatter gather registers. - */ -bool dce110_mem_input_v_program_pte_vm( - struct mem_input *mem_input, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - enum dc_rotation_angle rotation); - -/* - * This function will program surface tiling, size, rotation and pixel format - * to corresponding dcp registers. - */ -bool dce110_mem_input_v_program_surface_config( - struct mem_input *mem_input, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - union plane_size *plane_size, - enum dc_rotation_angle rotation, - bool visible); - #endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 041d11968566..3ed5b9445535 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -38,7 +38,7 @@ #include "dce110/dce110_timing_generator_v.h" #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" -#include "dce110/dce110_mem_input.h" +#include "dce/dce_mem_input.h" #include "dce110/dce110_mem_input_v.h" #include "dce/dce_ipp.h" #include "dce/dce_transform.h" @@ -133,30 +133,6 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { } }; -static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = { - { - .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - } -}; - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -520,30 +496,21 @@ static const struct dce_mem_input_mask mi_masks = { .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK }; + static struct mem_input *dce110_mem_input_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offset) + uint32_t inst) { - struct dce110_mem_input *mem_input110 = - dm_alloc(sizeof(struct dce110_mem_input)); + struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); - if (!mem_input110) + if (!dce_mi) { + BREAK_TO_DEBUGGER(); return NULL; - - if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) { - struct mem_input *mi = &mem_input110->base; - - mi->regs = &mi_regs[inst]; - mi->shifts = &mi_shifts; - mi->masks = &mi_masks; - mi->wa.single_head_rdreq_dmif_limit = 3; - return mi; } - BREAK_TO_DEBUGGER(); - dm_free(mem_input110); - return NULL; + dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); + dce_mi->wa.single_head_rdreq_dmif_limit = 3; + return &dce_mi->base; } static void dce110_transform_destroy(struct transform **xfm) @@ -698,7 +665,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -1132,7 +1099,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) { struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); - struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); + struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); if ((dce110_tgv == NULL) || @@ -1345,8 +1312,7 @@ static bool construct( goto res_create_fail; } - pool->base.mis[i] = dce110_mem_input_create(ctx, i, - &dce110_mi_reg_offsets[i]); + pool->base.mis[i] = dce110_mem_input_create(ctx, i); if (pool->base.mis[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile index 2d536fbc60c4..265ac4310d85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile @@ -3,7 +3,7 @@ # It provides the control and status of HW CRTC block. DCE112 = dce112_compressor.o dce112_hw_sequencer.o \ -dce112_resource.o dce112_mem_input.o +dce112_resource.o AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112)) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c deleted file mode 100644 index c29007dafe21..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#include "dm_services.h" -#include "dce112_mem_input.h" - - -#include "dce/dce_11_2_d.h" -#include "dce/dce_11_2_sh_mask.h" - - -#define DCP_REG(reg) (reg + mem_input110->offsets.dcp) -#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif) -#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe) - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -bool dce112_mem_input_construct( - struct dce110_mem_input *mem_input110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets) -{ - if (!dce110_mem_input_construct(mem_input110, ctx, inst, offsets)) - return false; - - mem_input110->base.funcs->mem_input_program_display_marks = - dce_mem_input_program_display_marks; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h deleted file mode 100644 index de2aaf0f9a8e..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MEM_INPUT_DCE112_H__ -#define __DC_MEM_INPUT_DCE112_H__ - -#include "mem_input.h" -#include "dce110/dce110_mem_input.h" - -bool dce112_mem_input_construct( - struct dce110_mem_input *mem_input110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets); - - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 0ed2616dd5cd..f405d6eecaa5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -32,9 +32,10 @@ #include "include/irq_service_interface.h" #include "dce110/dce110_resource.h" #include "dce110/dce110_timing_generator.h" -#include "dce112/dce112_mem_input.h" #include "irq/dce110/irq_service_dce110.h" + +#include "dce/dce_mem_input.h" #include "dce/dce_transform.h" #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" @@ -132,51 +133,6 @@ static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { } }; -static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets[] = { - { - .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - } -}; - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -541,27 +497,17 @@ static const struct dce_mem_input_mask mi_masks = { static struct mem_input *dce112_mem_input_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offset) + uint32_t inst) { - struct dce110_mem_input *mem_input110 = - dm_alloc(sizeof(struct dce110_mem_input)); + struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); - if (!mem_input110) + if (!dce_mi) { + BREAK_TO_DEBUGGER(); return NULL; - - if (dce112_mem_input_construct(mem_input110, ctx, inst, offset)) { - struct mem_input *mi = &mem_input110->base; - - mi->regs = &mi_regs[inst]; - mi->shifts = &mi_shifts; - mi->masks = &mi_masks; - return mi; } - BREAK_TO_DEBUGGER(); - dm_free(mem_input110); - return NULL; + dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); + return &dce_mi->base; } static void dce112_transform_destroy(struct transform **xfm) @@ -705,7 +651,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -1347,10 +1293,7 @@ static bool construct( goto res_create_fail; } - pool->base.mis[i] = dce112_mem_input_create( - ctx, - i, - &dce112_mi_reg_offsets[i]); + pool->base.mis[i] = dce112_mem_input_create(ctx, i); if (pool->base.mis[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile index 826c12ee368c..1779b963525c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -4,7 +4,7 @@ DCE120 = dce120_resource.o dce120_timing_generator.o \ -dce120_mem_input.o dce120_hw_sequencer.o +dce120_hw_sequencer.o AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c deleted file mode 100644 index c0677211bd93..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#include "dm_services.h" -#include "dce120_mem_input.h" - - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#define GENERAL_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(mem_input110->base.ctx, 0, reg_name, n, __VA_ARGS__) - -#define GENERAL_REG_UPDATE(reg, field, val) \ - GENERAL_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define GENERAL_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - GENERAL_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - - - -#define DCP_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(mem_input110->base.ctx, mem_input110->offsets.dcp, reg_name, n, __VA_ARGS__) - -#define DCP_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(mem_input110->base.ctx, mem_input110->offsets.dcp, reg_name, n, __VA_ARGS__) - -#define DCP_REG_UPDATE(reg, field, val) \ - DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define DCP_REG_SET(reg, field, val) \ - DCP_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ - DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - - - -#define DMIF_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(mem_input110->base.ctx, mem_input110->offsets.dmif, reg_name, n, __VA_ARGS__) - -#define DMIF_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(mem_input110->base.ctx, mem_input110->offsets.dmif, reg_name, n, __VA_ARGS__) - -#define DMIF_REG_UPDATE(reg, field, val) \ - DMIF_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define DMIF_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - DMIF_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DMIF_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - DMIF_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define DMIF_REG_SET(reg, field, val) \ - DMIF_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define DMIF_REG_SET_2(reg, field1, val1, field2, val2) \ - DMIF_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DMIF_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DMIF_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - - - -#define PIPE_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(mem_input110->base.ctx, mem_input110->offsets.pipe, reg_name, n, __VA_ARGS__) - -#define PIPE_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(mem_input110->base.ctx, mem_input110->offsets.pipe, reg_name, n, __VA_ARGS__) - -#define PIPE_REG_UPDATE(reg, field, val) \ - PIPE_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define PIPE_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - PIPE_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define PIPE_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - PIPE_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define PIPE_REG_SET(reg, field, val) \ - PIPE_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define PIPE_REG_SET_2(reg, field1, val1, field2, val2) \ - PIPE_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define PIPE_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - PIPE_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - - - -static void program_sec_addr( - struct dce110_mem_input *mem_input110, - PHYSICAL_ADDRESS_LOC address) -{ - uint32_t temp; - - /*high register MUST be programmed first*/ - temp = address.high_part & - DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK; - - DCP_REG_SET( - DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, - GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, - temp); - - temp = address.low_part >> - DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT; - - DCP_REG_SET_2( - DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, - GRPH_SECONDARY_SURFACE_ADDRESS, temp, - GRPH_SECONDARY_DFQ_ENABLE, 0); -} - -static void program_pri_addr( - struct dce110_mem_input *mem_input110, - PHYSICAL_ADDRESS_LOC address) -{ - uint32_t temp; - - /*high register MUST be programmed first*/ - temp = address.high_part & - DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK; - - DCP_REG_SET( - DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, - GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, - temp); - - temp = address.low_part >> - DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT; - - DCP_REG_SET( - DCP0_GRPH_PRIMARY_SURFACE_ADDRESS, - GRPH_PRIMARY_SURFACE_ADDRESS, - temp); -} - - -static bool mem_input_is_flip_pending(struct mem_input *mem_input) -{ - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); - uint32_t value; - - value = dm_read_reg_soc15(mem_input110->base.ctx, - mmDCP0_GRPH_UPDATE, mem_input110->offsets.dcp); - - if (get_reg_field_value(value, DCP0_GRPH_UPDATE, - GRPH_SURFACE_UPDATE_PENDING)) - return true; - - mem_input->current_address = mem_input->request_address; - return false; -} - -static bool mem_input_program_surface_flip_and_addr( - struct mem_input *mem_input, - const struct dc_plane_address *address, - bool flip_immediate) -{ - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input); - - /* TODO: Figure out if two modes are needed: - * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1 - * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1 - */ - DCP_REG_UPDATE(DCP0_GRPH_UPDATE, - GRPH_UPDATE_LOCK, 1); - - if (flip_immediate) { - DCP_REG_UPDATE_2( - DCP0_GRPH_FLIP_CONTROL, - GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0, - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1); - } else { - DCP_REG_UPDATE_2( - DCP0_GRPH_FLIP_CONTROL, - GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0, - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); - } - - switch (address->type) { - case PLN_ADDR_TYPE_GRAPHICS: - if (address->grph.addr.quad_part == 0) - break; - program_pri_addr(mem_input110, address->grph.addr); - break; - case PLN_ADDR_TYPE_GRPH_STEREO: - if (address->grph_stereo.left_addr.quad_part == 0 - || address->grph_stereo.right_addr.quad_part == 0) - break; - program_pri_addr(mem_input110, address->grph_stereo.left_addr); - program_sec_addr(mem_input110, address->grph_stereo.right_addr); - break; - default: - /* not supported */ - BREAK_TO_DEBUGGER(); - break; - } - - mem_input->request_address = *address; - - if (flip_immediate) - mem_input->current_address = *address; - - DCP_REG_UPDATE(DCP0_GRPH_UPDATE, - GRPH_UPDATE_LOCK, 0); - - return true; -} - -static void mem_input_update_dchub(struct mem_input *mi, - struct dchub_init_data *dh_data) -{ - struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mi); - /* TODO: port code from dal2 */ - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - GENERAL_REG_UPDATE_2( - DCHUB_FB_LOCATION, - FB_TOP, 0, - FB_BASE, 0x0FFFF); - - GENERAL_REG_UPDATE( - DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - GENERAL_REG_UPDATE( - DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - GENERAL_REG_UPDATE( - DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - GENERAL_REG_UPDATE( - DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - GENERAL_REG_UPDATE( - DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - GENERAL_REG_UPDATE( - DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - GENERAL_REG_UPDATE( - DCHUB_AGP_BASE, - AGP_BASE, 0); - - GENERAL_REG_UPDATE( - DCHUB_AGP_BOT, - AGP_BOT, 0x03FFFF); - - GENERAL_REG_UPDATE( - DCHUB_AGP_TOP, - AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - -static struct mem_input_funcs dce120_mem_input_funcs = { - .mem_input_program_display_marks = dce_mem_input_program_display_marks, - .allocate_mem_input = dce_mem_input_allocate_dmif, - .free_mem_input = dce_mem_input_free_dmif, - .mem_input_program_surface_flip_and_addr = - mem_input_program_surface_flip_and_addr, - .mem_input_program_pte_vm = dce_mem_input_program_pte_vm, - .mem_input_program_surface_config = - dce_mem_input_program_surface_config, - .mem_input_is_flip_pending = mem_input_is_flip_pending, - .mem_input_update_dchub = mem_input_update_dchub -}; - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -bool dce120_mem_input_construct( - struct dce110_mem_input *mem_input110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets) -{ - /* supported stutter method - * STUTTER_MODE_ENHANCED - * STUTTER_MODE_QUAD_DMIF_BUFFER - * STUTTER_MODE_WATERMARK_NBP_STATE - */ - - if (!dce110_mem_input_construct(mem_input110, ctx, inst, offsets)) - return false; - - mem_input110->base.funcs = &dce120_mem_input_funcs; - mem_input110->offsets = *offsets; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h deleted file mode 100644 index 379fd72155b9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MEM_INPUT_DCE120_H__ -#define __DC_MEM_INPUT_DCE120_H__ - -#include "mem_input.h" -#include "dce110/dce110_mem_input.h" - -bool dce120_mem_input_construct( - struct dce110_mem_input *mem_input110, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b13abb025e1b..1276dabfb208 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -41,8 +41,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_clocks.h" #include "dce/dce_ipp.h" -#include "dce110/dce110_mem_input.h" -#include "dce120/dce120_mem_input.h" +#include "dce/dce_mem_input.h" #include "dce110/dce110_hw_sequencer.h" #include "dce120/dce120_hw_sequencer.h" @@ -376,51 +375,6 @@ struct output_pixel_processor *dce120_opp_create( return NULL; } -static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = { - { - .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - } -}; - static const struct bios_registers bios_regs = { .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) }; @@ -518,7 +472,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -708,27 +662,17 @@ static const struct dce_mem_input_mask mi_masks = { static struct mem_input *dce120_mem_input_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offset) + uint32_t inst) { - struct dce110_mem_input *mem_input110 = - dm_alloc(sizeof(struct dce110_mem_input)); + struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); - if (!mem_input110) + if (!dce_mi) { + BREAK_TO_DEBUGGER(); return NULL; - - if (dce120_mem_input_construct(mem_input110, ctx, inst, offset)) { - struct mem_input *mi = &mem_input110->base; - - mi->regs = &mi_regs[inst]; - mi->shifts = &mi_shifts; - mi->masks = &mi_masks; - return mi; } - BREAK_TO_DEBUGGER(); - dm_free(mem_input110); - return NULL; + dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); + return &dce_mi->base; } static struct transform *dce120_transform_create( @@ -1007,8 +951,7 @@ static bool construct( goto controller_create_fail; } - pool->base.mis[i] = dce120_mem_input_create(ctx, - i, &dce120_mi_reg_offsets[i]); + pool->base.mis[i] = dce120_mem_input_create(ctx, i); if (pool->base.mis[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index 1d54d5fa0fd2..c1105895e5fa 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -2,8 +2,7 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. -DCE80 = dce80_timing_generator.o \ - dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \ +DCE80 = dce80_timing_generator.o dce80_compressor.o dce80_hw_sequencer.o \ dce80_resource.o AMD_DAL_DCE80 = $(addprefix $(AMDDALPATH)/dc/dce80/,$(DCE80)) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c deleted file mode 100644 index 933e3d819f27..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#include "dm_services.h" - -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" -/* TODO: this needs to be looked at, used by Stella's workaround*/ -#include "gmc/gmc_7_1_d.h" -#include "gmc/gmc_7_1_sh_mask.h" - -#include "include/logger_interface.h" -#include "inc/dce_calcs.h" - -#include "../dce110/dce110_mem_input.h" -#include "dce80_mem_input.h" - -#define MAX_WATERMARK 0xFFFF -#define SAFE_NBP_MARK 0x7FFF - -#define DCP_REG(reg) (reg + mem_input80->offsets.dcp) -#define DMIF_REG(reg) (reg + mem_input80->offsets.dmif) -#define PIPE_REG(reg) (reg + mem_input80->offsets.pipe) - -static struct mem_input_funcs dce80_mem_input_funcs = { - .mem_input_program_display_marks = - dce110_mem_input_program_display_marks, - .allocate_mem_input = dce_mem_input_allocate_dmif, - .free_mem_input = dce_mem_input_free_dmif, - .mem_input_program_surface_flip_and_addr = - dce110_mem_input_program_surface_flip_and_addr, - .mem_input_program_surface_config = - dce_mem_input_program_surface_config, - .mem_input_is_flip_pending = - dce110_mem_input_is_flip_pending, - .mem_input_update_dchub = NULL -}; - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -bool dce80_mem_input_construct( - struct dce110_mem_input *mem_input80, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets) -{ - /* supported stutter method - * STUTTER_MODE_ENHANCED - * STUTTER_MODE_QUAD_DMIF_BUFFER - */ - mem_input80->base.funcs = &dce80_mem_input_funcs; - mem_input80->base.ctx = ctx; - - mem_input80->base.inst = inst; - - mem_input80->offsets = *offsets; - - return true; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h deleted file mode 100644 index 357b9e2e9f1e..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MEM_INPUT_DCE80_H__ -#define __DC_MEM_INPUT_DCE80_H__ - -#include "mem_input.h" - -bool dce80_mem_input_construct( - struct dce110_mem_input *mem_input80, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5735914a8737..095e437ce112 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -35,12 +35,12 @@ #include "include/irq_service_interface.h" #include "irq/dce80/irq_service_dce80.h" #include "dce110/dce110_timing_generator.h" -#include "dce110/dce110_mem_input.h" #include "dce110/dce110_resource.h" #include "dce80/dce80_timing_generator.h" +#include "dce/dce_mem_input.h" #include "dce/dce_link_encoder.h" #include "dce/dce_stream_encoder.h" -#include "dce80/dce80_mem_input.h" +#include "dce/dce_mem_input.h" #include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce/dce_opp.h" @@ -141,51 +141,6 @@ static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { } }; -static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = { - { - .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), - .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL - - mmDPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - } -}; - /* set register offset */ #define SR(reg_name)\ .reg_name = mm ## reg_name @@ -541,28 +496,18 @@ static const struct dce_mem_input_mask mi_masks = { static struct mem_input *dce80_mem_input_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offsets) + uint32_t inst) { - struct dce110_mem_input *mem_input80 = - dm_alloc(sizeof(struct dce110_mem_input)); + struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); - if (!mem_input80) + if (!dce_mi) { + BREAK_TO_DEBUGGER(); return NULL; - - if (dce80_mem_input_construct(mem_input80, ctx, inst, offsets)) { - struct mem_input *mi = &mem_input80->base; - - mi->regs = &mi_regs[inst]; - mi->shifts = &mi_shifts; - mi->masks = &mi_masks; - mi->wa.single_head_rdreq_dmif_limit = 2; - return mi; } - BREAK_TO_DEBUGGER(); - dm_free(mem_input80); - return NULL; + dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); + dce_mi->wa.single_head_rdreq_dmif_limit = 2; + return &dce_mi->base; } static void dce80_transform_destroy(struct transform **xfm) @@ -684,7 +629,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -1000,8 +945,7 @@ static bool construct( goto res_create_fail; } - pool->base.mis[i] = dce80_mem_input_create(ctx, i, - &dce80_mi_reg_offsets[i]); + pool->base.mis[i] = dce80_mem_input_create(ctx, i); if (pool->base.mis[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create memory input!\n"); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 79fbc60e21c9..bd0dfeb2afa2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -28,8 +28,6 @@ #include "dc.h" #include "include/grph_object_id.h" -#include "dce/dce_mem_input.h" /* temporary */ - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "dml/display_mode_structs.h" @@ -51,7 +49,6 @@ struct dcn_watermark_set { struct dcn_watermarks c; struct dcn_watermarks d; }; - #endif struct dce_watermarks { @@ -74,11 +71,6 @@ struct mem_input { struct dc_plane_address current_address; uint32_t inst; struct stutter_modes stutter_mode; - - const struct dce_mem_input_registers *regs; - const struct dce_mem_input_shift *shifts; - const struct dce_mem_input_mask *masks; - struct dce_mem_input_wa wa; }; struct mem_input_funcs { -- cgit v1.2.3-59-g8ed1b From 430ef426bc43b59a7444c08d664e24a7cf89710e Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 17 May 2017 16:05:40 -0400 Subject: drm/amd/display: make dc_get_validate_context re-entrant Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 44 ++-------------------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 30 +++++++-------- .../drm/amd/display/dc/dce100/dce100_resource.c | 22 ++++++----- .../drm/amd/display/dc/dce110/dce110_resource.c | 22 ++++++----- .../drm/amd/display/dc/dce112/dce112_resource.c | 27 +++++++------ .../drm/amd/display/dc/dce112/dce112_resource.h | 3 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 22 ++++++----- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 24 ++++++------ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 9 +++-- 10 files changed, 92 insertions(+), 114 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b5ba822df55e..0aafcc088284 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -653,40 +653,6 @@ void dc_destroy(struct dc **dc) *dc = NULL; } -static bool is_validation_required( - const struct core_dc *dc, - const struct dc_validation_set set[], - int set_count) -{ - const struct validate_context *context = dc->current_context; - int i, j; - - if (context->stream_count != set_count) - return true; - - for (i = 0; i < set_count; i++) { - - if (set[i].surface_count != context->stream_status[i].surface_count) - return true; - if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) - return true; - - for (j = 0; j < set[i].surface_count; j++) { - struct dc_surface temp_surf = { 0 }; - - temp_surf = *context->stream_status[i].surfaces[j]; - temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; - temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; - temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; - - if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0) - return true; - } - } - - return false; -} - struct validate_context *dc_get_validate_context( const struct dc *dc, const struct dc_validation_set set[], @@ -700,13 +666,8 @@ struct validate_context *dc_get_validate_context( if(context == NULL) goto context_alloc_fail; - if (!is_validation_required(core_dc, set, set_count)) { - dc_resource_validate_ctx_copy_construct(core_dc->current_context, context); - return context; - } - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, set_count, context); + core_dc, set, set_count, context, NULL); context_alloc_fail: if (result != DC_OK) { @@ -903,7 +864,8 @@ bool dc_commit_streams( if (context == NULL) goto context_alloc_fail; - result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, stream_count, context); + result = core_dc->res_pool->funcs->validate_with_context( + core_dc, set, stream_count, context, core_dc->current_context); if (result != DC_OK){ dm_logger_write(core_dc->ctx->logger, LOG_ERROR, "%s: Context validation failed! dc_status:%d\n", diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7ca03d1ad163..ec5045734378 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1148,7 +1148,7 @@ bool resource_validate_attach_surfaces( int i, j; for (i = 0; i < set_count; i++) { - for (j = 0; j < old_context->stream_count; j++) + for (j = 0; old_context && j < old_context->stream_count; j++) if (is_stream_unchanged( old_context->streams[j], context->streams[i])) { @@ -1387,9 +1387,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks( - const struct core_dc *dc, - struct validate_context *context) +static void calculate_phy_pix_clks(struct validate_context *context) { int i; @@ -1410,21 +1408,22 @@ static void calculate_phy_pix_clks( enum dc_status resource_map_pool_resources( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { const struct resource_pool *pool = dc->res_pool; int i, j; - calculate_phy_pix_clks(dc, context); + calculate_phy_pix_clks(context); - for (i = 0; i < context->stream_count; i++) { + for (i = 0; old_context && i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - if (!resource_is_stream_unchanged(dc->current_context, stream)) { - if (stream != NULL && dc->current_context->streams[i] != NULL) { + if (!resource_is_stream_unchanged(old_context, stream)) { + if (stream != NULL && old_context->streams[i] != NULL) { stream->bit_depth_params = - dc->current_context->streams[i]->bit_depth_params; - stream->clamping = dc->current_context->streams[i]->clamping; + old_context->streams[i]->bit_depth_params; + stream->clamping = old_context->streams[i]->clamping; continue; } } @@ -1434,7 +1433,7 @@ enum dc_status resource_map_pool_resources( struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; const struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[j]; + &old_context->res_ctx.pipe_ctx[j]; if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) continue; @@ -1475,7 +1474,7 @@ enum dc_status resource_map_pool_resources( struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; /* acquire new resources */ pipe_idx = acquire_first_free_pipe( @@ -2203,7 +2202,8 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) enum dc_status resource_map_clock_resources( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { int i, j; const struct resource_pool *pool = dc->res_pool; @@ -2212,7 +2212,7 @@ enum dc_status resource_map_clock_resources( for (i = 0; i < context->stream_count; i++) { const struct core_stream *stream = context->streams[i]; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; for (j = 0; j < MAX_PIPES; j++) { diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 8f1fe95dd76c..716f664f40ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -653,7 +653,8 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status validate_mapped_resource( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { enum dc_status status = DC_OK; uint8_t i, j; @@ -662,7 +663,7 @@ static enum dc_status validate_mapped_resource( struct core_stream *stream = context->streams[i]; struct core_link *link = stream->sink->link; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; for (j = 0; j < MAX_PIPES; j++) { @@ -740,7 +741,8 @@ enum dc_status dce100_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { struct dc_context *dc_ctx = dc->ctx; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -755,19 +757,19 @@ enum dc_status dce100_validate_with_context( context->stream_count++; } - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, old_context); if (result == DC_OK) - result = resource_map_clock_resources(dc, context); + result = resource_map_clock_resources(dc, context, old_context); if (!resource_validate_attach_surfaces(set, set_count, - dc->current_context, context, dc->res_pool)) { + old_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -790,13 +792,13 @@ enum dc_status dce100_validate_guaranteed( dc_stream_retain(&context->streams[0]->public); context->stream_count++; - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, NULL); if (result == DC_OK) - result = resource_map_clock_resources(dc, context); + result = resource_map_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 3ed5b9445535..45759b9f15e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -769,7 +769,8 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne static enum dc_status validate_mapped_resource( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { enum dc_status status = DC_OK; uint8_t i, j; @@ -778,7 +779,7 @@ static enum dc_status validate_mapped_resource( struct core_stream *stream = context->streams[i]; struct core_link *link = stream->sink->link; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; for (j = 0; j < MAX_PIPES; j++) { @@ -943,7 +944,8 @@ enum dc_status dce110_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { struct dc_context *dc_ctx = dc->ctx; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -958,19 +960,19 @@ enum dc_status dce110_validate_with_context( context->stream_count++; } - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, old_context); if (result == DC_OK) - result = resource_map_clock_resources(dc, context); + result = resource_map_clock_resources(dc, context, old_context); if (!resource_validate_attach_surfaces(set, set_count, - dc->current_context, context, dc->res_pool)) { + old_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -993,13 +995,13 @@ enum dc_status dce110_validate_guaranteed( dc_stream_retain(&context->streams[0]->public); context->stream_count++; - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, NULL); if (result == DC_OK) - result = resource_map_clock_resources(dc, context); + result = resource_map_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index f405d6eecaa5..80f067343a91 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -722,7 +722,8 @@ static struct clock_source *find_matching_pll( static enum dc_status validate_mapped_resource( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { enum dc_status status = DC_OK; uint8_t i, j; @@ -731,7 +732,7 @@ static enum dc_status validate_mapped_resource( struct core_stream *stream = context->streams[i]; struct core_link *link = stream->sink->link; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; for (j = 0; j < MAX_PIPES; j++) { @@ -854,7 +855,8 @@ bool dce112_validate_bandwidth( enum dc_status resource_map_phy_clock_resources( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { uint8_t i, j; @@ -862,7 +864,7 @@ enum dc_status resource_map_phy_clock_resources( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; for (j = 0; j < MAX_PIPES; j++) { @@ -922,7 +924,8 @@ enum dc_status dce112_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { struct dc_context *dc_ctx = dc->ctx; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -937,19 +940,19 @@ enum dc_status dce112_validate_with_context( context->stream_count++; } - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, old_context); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context); + result = resource_map_phy_clock_resources(dc, context, old_context); if (!resource_validate_attach_surfaces(set, set_count, - dc->current_context, context, dc->res_pool)) { + old_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -972,13 +975,13 @@ enum dc_status dce112_validate_guaranteed( dc_stream_retain(&context->streams[0]->public); context->stream_count++; - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, NULL); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context); + result = resource_map_phy_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index dc842aace766..c6c0bbac5335 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -39,7 +39,8 @@ enum dc_status dce112_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context); + struct validate_context *context, + struct validate_context *old_context); enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 095e437ce112..5861b3fdf7d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -669,7 +669,8 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status validate_mapped_resource( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { enum dc_status status = DC_OK; uint8_t i, j; @@ -678,7 +679,7 @@ static enum dc_status validate_mapped_resource( struct core_stream *stream = context->streams[i]; struct core_link *link = stream->sink->link; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; for (j = 0; j < MAX_PIPES; j++) { @@ -757,7 +758,8 @@ enum dc_status dce80_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { struct dc_context *dc_ctx = dc->ctx; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -772,19 +774,19 @@ enum dc_status dce80_validate_with_context( context->stream_count++; } - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, old_context); if (result == DC_OK) - result = resource_map_clock_resources(dc, context); + result = resource_map_clock_resources(dc, context, old_context); if (!resource_validate_attach_surfaces(set, set_count, - dc->current_context, context, dc->res_pool)) { + old_context, context, dc->res_pool)) { DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -806,13 +808,13 @@ enum dc_status dce80_validate_guaranteed( dc_stream_retain(&context->streams[0]->public); context->stream_count++; - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, NULL); if (result == DC_OK) - result = resource_map_clock_resources(dc, context); + result = resource_map_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 7fdc5860857b..94cd7a9b0b19 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -853,7 +853,8 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) static enum dc_status validate_mapped_resource( const struct core_dc *dc, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { enum dc_status status = DC_OK; uint8_t i, j; @@ -862,8 +863,8 @@ static enum dc_status validate_mapped_resource( struct core_stream *stream = context->streams[i]; struct core_link *link = stream->sink->link; - if (resource_is_stream_unchanged(dc->current_context, stream)) { - if (stream != NULL && dc->current_context->streams[i] != NULL) { + if (old_context && resource_is_stream_unchanged(old_context, stream)) { + if (stream != NULL && old_context->streams[i] != NULL) { /* todo: shouldn't have to copy missing parameter here */ resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); @@ -920,7 +921,8 @@ enum dc_status dcn10_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct validate_context *context, + struct validate_context *old_context) { enum dc_status result = DC_OK; int i; @@ -934,20 +936,20 @@ enum dc_status dcn10_validate_with_context( context->stream_count++; } - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, old_context); if (result != DC_OK) return result; - result = resource_map_phy_clock_resources(dc, context); + result = resource_map_phy_clock_resources(dc, context, old_context); if (result != DC_OK) return result; - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, old_context); if (result != DC_OK) return result; if (!resource_validate_attach_surfaces(set, set_count, - dc->current_context, context, dc->res_pool)) + old_context, context, dc->res_pool)) return DC_FAIL_ATTACH_SURFACES; result = resource_build_scaling_params_for_context(dc, context); @@ -971,13 +973,13 @@ enum dc_status dcn10_validate_guaranteed( dc_stream_retain(&context->streams[0]->public); context->stream_count++; - result = resource_map_pool_resources(dc, context); + result = resource_map_pool_resources(dc, context, NULL); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context); + result = resource_map_phy_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context); + result = validate_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 46bd0318e6be..d8a378dabb43 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -203,7 +203,8 @@ struct resource_funcs { const struct core_dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context); + struct validate_context *context, + struct validate_context *old_context); enum dc_status (*validate_guaranteed)( const struct core_dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 4e07b9fea669..7cac24d4ae86 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -80,7 +80,8 @@ void dc_destroy_resource_pool(struct core_dc *dc); enum dc_status resource_map_pool_resources( const struct core_dc *dc, - struct validate_context *context); + struct validate_context *context, + struct validate_context *old_context); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); @@ -150,11 +151,13 @@ void resource_validate_ctx_update_pointer_after_copy( enum dc_status resource_map_clock_resources( const struct core_dc *dc, - struct validate_context *context); + struct validate_context *context, + struct validate_context *old_context); enum dc_status resource_map_phy_clock_resources( const struct core_dc *dc, - struct validate_context *context); + struct validate_context *context, + struct validate_context *old_context); bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, -- cgit v1.2.3-59-g8ed1b From 98489c026edc48d9c783f783cc82f2e8811e0ee4 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 16 May 2017 13:52:28 -0400 Subject: drm/amd/display: Refactor use_lut() from dce110 to dce use_lut() checks if the input surface's pixel format is compatible with a 256 entry LUT. This function can be used across different versions and not just dce11. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 ++ .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 ++--------------- 3 files changed, 16 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 34c18712970c..cc3178acfc54 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -191,3 +191,15 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, clk_src->id, tg_inst); } } + +/* Only use LUT for 8 bit formats */ +bool dce_use_lut(const struct core_surface *surface) +{ + switch (surface->public.format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + return true; + default: + return false; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index dd13f47b6446..112f9c85c142 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -256,4 +256,6 @@ void dce_clock_gating_power_up(struct dce_hwseq *hws, void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); + +bool dce_use_lut(const struct core_surface *surface); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 20ad1cb263db..65c691569eb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -28,10 +28,10 @@ #include "core_types.h" #include "core_status.h" #include "resource.h" -#include "hw_sequencer.h" #include "dm_helpers.h" #include "dce110_hw_sequencer.h" #include "dce110_timing_generator.h" +#include "dce/dce_hwseq.h" #include "bios/bios_parser_helper.h" #include "timing_generator.h" @@ -233,19 +233,6 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } - -/* Only use LUT for 8 bit formats */ -static bool use_lut(const struct core_surface *surface) -{ - switch (surface->public.format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - return true; - default: - return false; - } -} - static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct core_surface *surface) @@ -264,7 +251,7 @@ static bool dce110_set_input_transfer_func( build_prescale_params(&prescale_params, surface); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - if (surface->public.gamma_correction && use_lut(surface)) + if (surface->public.gamma_correction && dce_use_lut(surface)) ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); if (tf == NULL) { -- cgit v1.2.3-59-g8ed1b From c1473558e617d886276e4a8b3c139b681d90d67c Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 19 May 2017 17:40:50 -0400 Subject: drm/amd/display: program scaler not called. Scaler code in case of UPDATE_TYPE_MED was not called since new pipe context and current context are the same. Signed-off-by: Andrey Grodzovsky Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 23 ++++++++++++++++++++-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 6 ++---- 2 files changed, 23 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b428c7c6559b..4900e8073c69 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1011,12 +1011,23 @@ bool dc_commit_surfaces_to_stream( struct dc_plane_info plane_info[MAX_SURFACES]; struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; + bool ret; + struct dc_stream_update *stream_update = + dm_alloc(sizeof(struct dc_stream_update)); + + if (!stream_update) { + BREAK_TO_DEBUGGER(); + return false; + } memset(updates, 0, sizeof(updates)); memset(flip_addr, 0, sizeof(flip_addr)); memset(plane_info, 0, sizeof(plane_info)); memset(scaling_info, 0, sizeof(scaling_info)); + stream_update->src = dc_stream->src; + stream_update->dst = dc_stream->dst; + for (i = 0; i < new_surface_count; i++) { updates[i].surface = new_surfaces[i]; updates[i].gamma = @@ -1041,9 +1052,17 @@ bool dc_commit_surfaces_to_stream( updates[i].plane_info = &plane_info[i]; updates[i].scaling_info = &scaling_info[i]; } - dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream); - return dc_post_update_surfaces_to_stream(dc); + dc_update_surfaces_and_stream( + dc, + updates, + new_surface_count, + dc_stream, stream_update); + + ret = dc_post_update_surfaces_to_stream(dc); + + dm_free(stream_update); + return ret; } static bool is_surface_in_context( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 65c691569eb7..7dd4b02b5938 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2408,10 +2408,8 @@ static void dce110_program_front_end_for_pipe( pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; - if (old_pipe && memcmp(&old_pipe->scl_data, - &pipe_ctx->scl_data, - sizeof(struct scaler_data)) != 0) - program_scaler(dc, pipe_ctx); + + program_scaler(dc, pipe_ctx); mi->funcs->mem_input_program_surface_config( mi, -- cgit v1.2.3-59-g8ed1b From 0a1c73ec8e4834d72441ae77f436869fd5179d8f Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 25 May 2017 14:40:21 +0530 Subject: drm/amd/display: re-order the luma chroma addres updation The DCE engine triggers scan as soon as the luma address is updated, since it is updated before chroma address the chroma data is not scanned out properly or in order. This patch fixes this by re-ordering the same. BUG: SWDEV-119421 TEST: (On Chromium OS for Stoney Only) * Executed below tests to see YUV(underlay) & RGB planes on eDP plane_test --format XR24 --size 500x100 -p --format NV12 --size 500x500 * Chroma data is scanned properly. Signed-off-by: Shirish S Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 9777a4d961d5..a06c6024deb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -137,12 +137,12 @@ static void program_addr( addr->grph.addr); break; case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: - program_pri_addr_l( - mem_input110, - addr->video_progressive.luma_addr); program_pri_addr_c( mem_input110, addr->video_progressive.chroma_addr); + program_pri_addr_l( + mem_input110, + addr->video_progressive.luma_addr); break; default: /* not supported */ -- cgit v1.2.3-59-g8ed1b From 1bf56e62cc4fbff6d701b798da05a91f78aa12e9 Mon Sep 17 00:00:00 2001 From: Zeyu Fan Date: Fri, 2 Jun 2017 17:25:49 -0400 Subject: drm/amd/display: Call program_gamut explicitly instead of entire set_plane This fixes on boot crush on Vega, Polaris with Dal3. Signed-off-by: Zeyu Fan Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 42 ++++++++++++++++++++++ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++ 4 files changed, 47 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f5102b644942..657e10bae93f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -213,8 +213,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) == core_stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; - core_dc->hwss.set_plane_config(core_dc, pipes, - &core_dc->current_context->res_ctx); + core_dc->hwss.program_gamut_remap(pipes); ret = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7dd4b02b5938..616533e25534 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1894,6 +1894,47 @@ static void program_surface_visibility(const struct core_dc *dc, } +static void program_gamut_remap(struct pipe_ctx *pipe_ctx) +{ + struct xfm_grph_csc_adjustment adjust; + memset(&adjust, 0, sizeof(adjust)); + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; + + + if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; + adjust.temperature_matrix[0] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[0]; + adjust.temperature_matrix[1] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[1]; + adjust.temperature_matrix[2] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[2]; + adjust.temperature_matrix[3] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[4]; + adjust.temperature_matrix[4] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[5]; + adjust.temperature_matrix[5] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[6]; + adjust.temperature_matrix[6] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[8]; + adjust.temperature_matrix[7] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[9]; + adjust.temperature_matrix[8] = + pipe_ctx->stream-> + public.gamut_remap_matrix.matrix[10]; + } + + pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); +} + /** * TODO REMOVE, USE UPDATE INSTEAD */ @@ -2509,6 +2550,7 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) } static const struct hw_sequencer_funcs dce110_funcs = { + .program_gamut_remap = program_gamut_remap, .init_hw = init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, .apply_ctx_for_surface = dce110_apply_ctx_for_surface, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 447f6bf4644c..107f82df3053 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1899,6 +1899,7 @@ static void set_plane_config( } static const struct hw_sequencer_funcs dcn10_funcs = { + .program_gamut_remap = program_gamut_remap, .init_hw = init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b53e1206dfb3..6f8733ec9b16 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -67,6 +67,9 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx); + void (*program_gamut_remap)( + struct pipe_ctx *pipe_ctx); + void (*update_plane_addr)( const struct core_dc *dc, struct pipe_ctx *pipe_ctx); -- cgit v1.2.3-59-g8ed1b From aed8b319180f18402ed90929f85e2b3e5b81e71d Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 8 Jun 2017 11:55:06 +0530 Subject: drm/amd/display: remove get_position() of underlay get_position() returns CRTC vertical/horizontal counters, hence it is not applicable for underlay which is plane and not attached to one crtc. This patch hence removes the callback from dce110_tg_v_funcs and hence fixes a bug in dc_debug.c where in get_position() for underlay pipe is called un-conditionally. Witout this patch get_position() is called in case one has to update underlay plane's data, since callback implmented with an ASSERT(), the old_surface_count and new_surface_count mismatches; causing only one plane update which is not right and also assert makes the rendering slow. Signed-off-by: Shirish S Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 9 +++++++-- .../gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c | 9 +-------- 2 files changed, 8 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index ad556e9b0754..9a5df3a848b5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -297,11 +297,16 @@ void context_timing_trace( struct dal_logger *logger = core_dc->ctx->logger; int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; struct crtc_position position; + unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - - if (pipe_ctx->stream == NULL) + /* get_position() returns CRTC vertical/horizontal counter + * hence not applicable for underlay pipe + */ + if (pipe_ctx->stream == NULL + || pipe_ctx->pipe_idx == underlay_idx) continue; pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &position); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 759c55bb4d15..93ca6ae48cb9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -570,13 +570,6 @@ static void dce110_timing_generator_v_set_early_control( dm_write_reg(tg->ctx, address, regval); } -static void dce110_timing_generator_get_underlay_position(struct timing_generator *tg, - struct crtc_position *position) -{ - //Should never hit this case - ASSERT(false); -} - static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg) { uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT; @@ -652,7 +645,7 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = { .enable_crtc = dce110_timing_generator_v_enable_crtc, .disable_crtc = dce110_timing_generator_v_disable_crtc, .is_counter_moving = dce110_timing_generator_v_is_counter_moving, - .get_position = dce110_timing_generator_get_underlay_position, + .get_position = NULL, /* Not to be implemented for underlay*/ .get_frame_count = dce110_timing_generator_v_get_vblank_counter, .set_early_control = dce110_timing_generator_v_set_early_control, .wait_for_state = dce110_timing_generator_v_wait_for_state, -- cgit v1.2.3-59-g8ed1b From 7f5c22d1652327b64375e88b184b0df502c7bdc7 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Thu, 8 Jun 2017 15:55:02 -0500 Subject: drm/amd/display: RV stereo support HDMI frame pack and DP frame alternate in band Signed-off-by: Vitaly Prosyak Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 25 ++++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 6 ++ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 69 +++++++++++++++++++++- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 -- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 2 - 7 files changed, 105 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 66f0595a4c20..2b62efce73c5 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -972,9 +972,7 @@ bool dcn_validate_bandwidth( if (pipe->surface) { struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; - if (v->dpp_per_plane[input_idx] == 2 || - (pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM || - pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE)) { + if (v->dpp_per_plane[input_idx] == 2) { if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { /* update previously split pipe */ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 47870a640f37..e518aeddfa58 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -832,6 +832,30 @@ static bool streams_changed( return false; } +bool dc_enable_stereo( + struct dc *dc, + struct validate_context *context, + const struct dc_stream *streams[], + uint8_t stream_count) +{ + bool ret = true; + int i, j; + struct pipe_ctx *pipe; + struct core_dc *core_dc = DC_TO_CORE(dc); + for (i = 0; i < MAX_PIPES; i++) { + if (context != NULL) + pipe = &context->res_ctx.pipe_ctx[i]; + else + pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; + for (j = 0 ; pipe && j < stream_count; j++) { + if (streams[j] && streams[j] == &pipe->stream->public && + core_dc->hwss.setup_stereo) + core_dc->hwss.setup_stereo(pipe, core_dc); + } + } + return ret; +} + bool dc_commit_streams( struct dc *dc, const struct dc_stream *streams[], @@ -903,6 +927,7 @@ bool dc_commit_streams( DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]); core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); + dc_enable_stereo(dc, context, streams, stream_count); } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index c51ec617eff7..90eb839f5414 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -440,8 +440,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; - if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || - stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) { + if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || + stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pri_split = false; sec_split = false; } @@ -568,8 +568,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip /* Handle h & vsplit */ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { - if (stream->public.timing.timing_3d_format == - TIMING_3D_FORMAT_TOP_AND_BOTTOM) { + if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; /* Floor primary pipe, ceil 2ndary pipe */ @@ -581,8 +580,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip } } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { - if (stream->public.timing.timing_3d_format == - TIMING_3D_FORMAT_TOP_AND_BOTTOM) + if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else pipe_ctx->scl_data.recout.width /= 2; @@ -626,7 +624,7 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) surf_src.height, surface->dst_rect.height); - if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE) + if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.ratios.vert.value *= 2; @@ -1772,6 +1770,8 @@ static void set_vendor_info_packet( enum dc_timing_3d_format format; format = stream->public.timing.timing_3d_format; + if (stream->public.view_format == VIEW_3D_FORMAT_NONE) + format = TIMING_3D_FORMAT_NONE; /* Can be different depending on packet content */ length = 5; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 616533e25534..ac99d283bf0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2057,6 +2057,11 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; surface->status.current_address = pipe_ctx->mi->current_address; + if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && + pipe_ctx->tg->funcs->is_stereo_left_eye) { + surface->status.is_right_eye =\ + !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); + } } void dce110_power_down(struct core_dc *dc) @@ -2576,6 +2581,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_static_screen_control = set_static_screen_control, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, + .setup_stereo = NULL }; bool dce110_hw_sequencer_construct(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index f41230013309..edcd7369cf9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -896,8 +896,9 @@ static void reset_hw_ctx_wrap( reset_hw_ctx(dc, context, reset_back_end_for_pipe); } -static bool patch_address_for_sbs_tb_stereo( - struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) + +static bool patch_address_for_sbs_tb_stereo(struct pipe_ctx *pipe_ctx, + PHYSICAL_ADDRESS_LOC *addr) { struct core_surface *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && @@ -912,6 +913,7 @@ static bool patch_address_for_sbs_tb_stereo( surface->public.address.grph_stereo.right_addr; return true; } + return false; } @@ -2061,6 +2063,66 @@ static void set_plane_config( program_gamut_remap(pipe_ctx); } +static void dcn10_config_stereo_parameters(struct core_stream *stream,\ + struct crtc_stereo_flags *flags) +{ + enum view_3d_format view_format = stream->public.view_format; + enum dc_timing_3d_format timing_3d_format =\ + stream->public.timing.timing_3d_format; + bool non_stereo_timing = false; + + if (timing_3d_format == TIMING_3D_FORMAT_NONE || + timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || + timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) + non_stereo_timing = true; + + if (non_stereo_timing == false && + view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) { + + flags->PROGRAM_STEREO = 1; + flags->PROGRAM_POLARITY = 1; + if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA || + timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA || + timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) { + enum display_dongle_type dongle = \ + stream->sink->link->public.ddc->dongle_type; + if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER || + dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER || + dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER) + flags->DISABLE_STEREO_DP_SYNC = 1; + } + flags->RIGHT_EYE_POLARITY =\ + stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) + flags->FRAME_PACKED = 1; + } + + return; +} + +static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, + struct core_dc *dc) +{ + struct crtc_stereo_flags flags = { 0 }; + struct core_stream *stream = pipe_ctx->stream; + + dcn10_config_stereo_parameters(stream, &flags); + + pipe_ctx->opp->funcs->opp_set_stereo_polarity( + pipe_ctx->opp, + flags.PROGRAM_STEREO == 1 ? true:false, + stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); + + pipe_ctx->tg->funcs->program_stereo( + pipe_ctx->tg, + &stream->public.timing, + &flags); + + + + return; +} + static const struct hw_sequencer_funcs dcn10_funcs = { .program_gamut_remap = program_gamut_remap, .init_hw = init_hw, @@ -2088,7 +2150,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg, .set_drr = set_drr, .get_position = get_position, - .set_static_screen_control = set_static_screen_control + .set_static_screen_control = set_static_screen_control, + .setup_stereo = dcn10_setup_stereo }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index a2276803c0d0..77fc251d45ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -821,10 +821,6 @@ static void get_pixel_clock_parameters( if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) pixel_clk_params->requested_pix_clk /= 2; - if (stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING || - stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_SW_FRAME_PACKING || - stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA) - pixel_clk_params->requested_pix_clk *= 2; } static void build_clamping_params(struct core_stream *stream) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index bc3934d75b46..83efbec77357 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -271,8 +271,6 @@ static void tg_program_timing_generator( REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, h_div_2); - dcn10_disable_stereo( tg); - } /** tg_program_blanking -- cgit v1.2.3-59-g8ed1b From c8210d5ae37b3c0e5dc2a91095dd1147c524977d Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 9 Jun 2017 10:12:36 -0400 Subject: drm/amd/display: Don't call DCN clk code for Vega Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++++++---- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 84b0860190d7..4e3f4e5e46a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -614,11 +614,13 @@ static bool dce_apply_clock_voltage_request( } if (send_request) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); - /*use dcfclk request voltage*/ - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock_voltage_req.clocks_in_khz = + if (clk->ctx->dce_version == DCN_VERSION_1_0) { + struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + /*use dcfclk request voltage*/ + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value); + } #endif dm_pp_apply_clock_for_voltage_request( clk->ctx, &clock_voltage_req); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ac99d283bf0a..7c509811efa6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1633,7 +1633,7 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (resource_parse_asic_id(dc->ctx->asic_id) == DCN_VERSION_1_0) { + if (dc->ctx->dce_version == DCN_VERSION_1_0) { if (context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.cur_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; -- cgit v1.2.3-59-g8ed1b From 7950f0f9815a2dc2e3e1cc2d341d486ac2ae8bae Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 13 Jun 2017 17:08:22 -0400 Subject: drm/amd/display: fix dc_post_update_surfaces_to_stream Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 35 ++++++++-------------- drivers/gpu/drm/amd/display/dc/dc.h | 9 +----- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 11 ++----- 3 files changed, 17 insertions(+), 38 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a8f34a92cee2..909d38522361 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -953,15 +953,6 @@ context_alloc_fail: return (result == DC_OK); } -bool dc_pre_update_surfaces_to_stream( - struct dc *dc, - const struct dc_surface *const *new_surfaces, - uint8_t new_surface_count, - const struct dc_stream *dc_stream) -{ - return true; -} - bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; @@ -971,14 +962,19 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) post_surface_trace(dc); for (i = 0; i < core_dc->res_pool->pipe_count; i++) - if (context->res_ctx.pipe_ctx[i].stream == NULL) { + if (context->res_ctx.pipe_ctx[i].stream == NULL + || context->res_ctx.pipe_ctx[i].surface == NULL) { context->res_ctx.pipe_ctx[i].pipe_idx = i; core_dc->hwss.power_down_front_end( core_dc, &context->res_ctx.pipe_ctx[i]); } + /* 3rd param should be true, temp w/a for RV*/ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0); +#else core_dc->hwss.set_bandwidth(core_dc, context, true); - +#endif return true; } @@ -1262,17 +1258,12 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (stream_update->out_transfer_func && stream_update->out_transfer_func != - dc_stream->out_transfer_func) { - if (stream_update->out_transfer_func->type != - TF_TYPE_UNKNOWN) { - if (dc_stream->out_transfer_func != NULL) - dc_transfer_func_release - (dc_stream->out_transfer_func); - dc_transfer_func_retain(stream_update-> - out_transfer_func); - stream->public.out_transfer_func = - stream_update->out_transfer_func; - } + dc_stream->out_transfer_func) { + if (dc_stream->out_transfer_func != NULL) + dc_transfer_func_release(dc_stream->out_transfer_func); + dc_transfer_func_retain(stream_update->out_transfer_func); + stream->public.out_transfer_func = + stream_update->out_transfer_func; } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 36b3b123d3c7..52c36007382f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -262,8 +262,7 @@ struct dc_hdr_static_metadata { enum dc_transfer_func_type { TF_TYPE_PREDEFINED, TF_TYPE_DISTRIBUTED_POINTS, - TF_TYPE_BYPASS, - TF_TYPE_UNKNOWN + TF_TYPE_BYPASS }; struct dc_transfer_func_distributed_points { @@ -411,12 +410,6 @@ bool dc_commit_surfaces_to_stream( uint8_t surface_count, const struct dc_stream *stream); -bool dc_pre_update_surfaces_to_stream( - struct dc *dc, - const struct dc_surface *const *new_surfaces, - uint8_t new_surface_count, - const struct dc_stream *stream); - bool dc_post_update_surfaces_to_stream( struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7c509811efa6..a83d260cda45 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2538,17 +2538,12 @@ static void dce110_apply_ctx_for_surface( static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) { - int i; - - for (i = 0; i < dc->res_pool->pipe_count; i++) - if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe) - break; - - if (i == dc->res_pool->pipe_count) + /* Do not power down fe when stream is active on dce*/ + if (pipe->stream) return; dc->hwss.enable_display_power_gating( - dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); + dc, pipe->pipe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); if (pipe->xfm) pipe->xfm->funcs->transform_reset(pipe->xfm); memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); -- cgit v1.2.3-59-g8ed1b From 866294f80582e252913c72b5e0f1792f6133424d Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 21 Jun 2017 16:48:06 -0400 Subject: drm/amd/display: Don't program scaler if we have no surface If we don't have a surface in dc_commit_streams scl_data won't get populated in resource_build_scaling_params_for_context. In this case we shouldn't attempt to program the scaler. Signed-off-by: Harry Wentland Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index a83d260cda45..0bab85b27a85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1099,10 +1099,12 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; /* program_scaler and allocate_mem_input are not new asic */ - if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, - &pipe_ctx->scl_data, - sizeof(struct scaler_data)) != 0) + if ((!pipe_ctx_old || + memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, + sizeof(struct scaler_data)) != 0) && + pipe_ctx->surface) { program_scaler(dc, pipe_ctx); + } /* mst support - use total stream count */ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- cgit v1.2.3-59-g8ed1b From 7f524a0d838d8d9334003b956b73729f27a1315a Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 23 Jun 2017 13:35:53 -0400 Subject: drm/amd/display: remove unneeded FBC hw programming code - Removed uneeded FBC code. - Initial placeholder for FBC implementation on stoney/carrizo Signed-off-by: Bhawanpreet Lakha Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_compressor.c | 534 ++++----------------- .../drm/amd/display/dc/dce110/dce110_compressor.h | 3 + drivers/gpu/drm/amd/display/dc/inc/compressor.h | 46 +- 3 files changed, 137 insertions(+), 446 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 518150a414e2..5fe83045d1a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -94,199 +94,8 @@ enum fbc_idle_force { FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000, }; -static uint32_t lpt_size_alignment(struct dce110_compressor *cp110) -{ - /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */ - return cp110->base.raw_size * cp110->base.banks_num * - cp110->base.dram_channels_num; -} - -static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110, - uint32_t lpt_control) -{ - /*LPT MC Config */ - if (cp110->base.options.bits.LPT_MC_CONFIG == 1) { - /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS): - * 00 - 1 CHANNEL - * 01 - 2 CHANNELS - * 02 - 4 OR 6 CHANNELS - * (Only for discrete GPU, N/A for CZ) - * 03 - 8 OR 12 CHANNELS - * (Only for discrete GPU, N/A for CZ) */ - switch (cp110->base.dram_channels_num) { - case 2: - set_reg_field_value( - lpt_control, - 1, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_NUM_PIPES); - break; - case 1: - set_reg_field_value( - lpt_control, - 0, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_NUM_PIPES); - break; - default: - dm_logger_write( - cp110->base.ctx->logger, LOG_WARNING, - "%s: Invalid LPT NUM_PIPES!!!", - __func__); - break; - } - - /* The mapping for LPT NUM_BANKS is in - * GRPH_CONTROL.GRPH_NUM_BANKS register field - * Specifies the number of memory banks for tiling - * purposes. Only applies to 2D and 3D tiling modes. - * POSSIBLE VALUES: - * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK - * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK - * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK - * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */ - switch (cp110->base.banks_num) { - case 16: - set_reg_field_value( - lpt_control, - 3, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_NUM_BANKS); - break; - case 8: - set_reg_field_value( - lpt_control, - 2, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_NUM_BANKS); - break; - case 4: - set_reg_field_value( - lpt_control, - 1, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_NUM_BANKS); - break; - case 2: - set_reg_field_value( - lpt_control, - 0, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_NUM_BANKS); - break; - default: - dm_logger_write( - cp110->base.ctx->logger, LOG_WARNING, - "%s: Invalid LPT NUM_BANKS!!!", - __func__); - break; - } - - /* The mapping is in DMIF_ADDR_CALC. - * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for - * Carrizo specifies the memory interleave per pipe. - * It effectively specifies the location of pipe bits in - * the memory address. - * POSSIBLE VALUES: - * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte - * interleave - * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte - * interleave - */ - switch (cp110->base.channel_interleave_size) { - case 256: /*256B */ - set_reg_field_value( - lpt_control, - 0, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); - break; - case 512: /*512B */ - set_reg_field_value( - lpt_control, - 1, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); - break; - default: - dm_logger_write( - cp110->base.ctx->logger, LOG_WARNING, - "%s: Invalid LPT INTERLEAVE_SIZE!!!", - __func__); - break; - } - /* The mapping for LOW_POWER_TILING_ROW_SIZE is in - * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field - * for Carrizo. Specifies the size of dram row in bytes. - * This should match up with NOOFCOLS field in - * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns). - * This register DMIF_ADDR_CALC is not used by the - * hardware as it is only used for addrlib assertions. - * POSSIBLE VALUES: - * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row - * boundary - * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row - * boundary - * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row - * boundary */ - switch (cp110->base.raw_size) { - case 4096: /*4 KB */ - set_reg_field_value( - lpt_control, - 2, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ROW_SIZE); - break; - case 2048: - set_reg_field_value( - lpt_control, - 1, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ROW_SIZE); - break; - case 1024: - set_reg_field_value( - lpt_control, - 0, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ROW_SIZE); - break; - default: - dm_logger_write( - cp110->base.ctx->logger, LOG_WARNING, - "%s: Invalid LPT ROW_SIZE!!!", - __func__); - break; - } - } else { - dm_logger_write( - cp110->base.ctx->logger, LOG_WARNING, - "%s: LPT MC Configuration is not provided", - __func__); - } - - return lpt_control; -} - -static bool is_source_bigger_than_epanel_size( - struct dce110_compressor *cp110, - uint32_t source_view_width, - uint32_t source_view_height) -{ - if (cp110->base.embedded_panel_h_size != 0 && - cp110->base.embedded_panel_v_size != 0 && - ((source_view_width * source_view_height) > - (cp110->base.embedded_panel_h_size * - cp110->base.embedded_panel_v_size))) - return true; - - return false; -} - -static uint32_t align_to_chunks_number_per_line( - struct dce110_compressor *cp110, - uint32_t pixels) +static uint32_t align_to_chunks_number_per_line(uint32_t pixels) { return 256 * ((pixels + 255) / 256); } @@ -372,25 +181,11 @@ void dce110_compressor_enable_fbc( struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); if (compressor->options.bits.FBC_SUPPORT && - (compressor->options.bits.DUMMY_BACKEND == 0) && - (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) && - (!is_source_bigger_than_epanel_size( - cp110, - params->source_view_width, - params->source_view_height))) { + (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) { uint32_t addr; uint32_t value; - /* Before enabling FBC first need to enable LPT if applicable - * LPT state should always be changed (enable/disable) while FBC - * is disabled */ - if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) && - (params->source_view_width * - params->source_view_height <= - dce11_one_lpt_channel_max_resolution)) { - dce110_compressor_enable_lpt(compressor); - } addr = mmFBC_CNTL; value = dm_read_reg(compressor->ctx, addr); @@ -432,11 +227,6 @@ void dce110_compressor_disable_fbc(struct compressor *compressor) compressor->attached_inst = 0; compressor->is_enabled = false; - /* Whenever disabling FBC make sure LPT is disabled if LPT - * supported */ - if (compressor->options.bits.LPT_SUPPORT) - dce110_compressor_disable_lpt(compressor); - wait_for_fbc_state_changed(cp110, false); } } @@ -469,17 +259,6 @@ bool dce110_compressor_is_fbc_enabled_in_hw( return false; } -bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *compressor) -{ - /* Check the hardware register */ - uint32_t value = dm_read_reg(compressor->ctx, - mmLOW_POWER_TILING_CONTROL); - - return get_reg_field_value( - value, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ENABLE); -} void dce110_compressor_program_compressed_surface_address_and_pitch( struct compressor *compressor, @@ -499,17 +278,6 @@ void dce110_compressor_program_compressed_surface_address_and_pitch( dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0); - if (compressor->options.bits.LPT_SUPPORT) { - uint32_t lpt_alignment = lpt_size_alignment(cp110); - - if (lpt_alignment != 0) { - compressed_surf_address_low_part = - ((compressed_surf_address_low_part - + (lpt_alignment - 1)) / lpt_alignment) - * lpt_alignment; - } - } - /* Write address, HIGH has to be first. */ dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), @@ -518,9 +286,7 @@ void dce110_compressor_program_compressed_surface_address_and_pitch( DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), compressed_surf_address_low_part); - fbc_pitch = align_to_chunks_number_per_line( - cp110, - params->source_view_width); + fbc_pitch = align_to_chunks_number_per_line(params->source_view_width); if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) fbc_pitch = fbc_pitch / 8; @@ -543,197 +309,6 @@ void dce110_compressor_program_compressed_surface_address_and_pitch( } -void dce110_compressor_disable_lpt(struct compressor *compressor) -{ - struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); - uint32_t value; - uint32_t addr; - uint32_t inx; - - /* Disable all pipes LPT Stutter */ - for (inx = 0; inx < 3; inx++) { - value = - dm_read_reg( - compressor->ctx, - DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); - set_reg_field_value( - value, - 0, - DPG_PIPE_STUTTER_CONTROL_NONLPTCH, - STUTTER_ENABLE_NONLPTCH); - dm_write_reg( - compressor->ctx, - DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), - value); - } - /* Disable Underlay pipe LPT Stutter */ - addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; - value = dm_read_reg(compressor->ctx, addr); - set_reg_field_value( - value, - 0, - DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, - STUTTER_ENABLE_NONLPTCH); - dm_write_reg(compressor->ctx, addr, value); - - /* Disable LPT */ - addr = mmLOW_POWER_TILING_CONTROL; - value = dm_read_reg(compressor->ctx, addr); - set_reg_field_value( - value, - 0, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ENABLE); - dm_write_reg(compressor->ctx, addr, value); - - /* Clear selection of Channel(s) containing Compressed Surface */ - addr = mmGMCON_LPT_TARGET; - value = dm_read_reg(compressor->ctx, addr); - set_reg_field_value( - value, - 0xFFFFFFFF, - GMCON_LPT_TARGET, - STCTRL_LPT_TARGET); - dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value); -} - -void dce110_compressor_enable_lpt(struct compressor *compressor) -{ - struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); - uint32_t value; - uint32_t addr; - uint32_t value_control; - uint32_t channels; - - /* Enable LPT Stutter from Display pipe */ - value = dm_read_reg(compressor->ctx, - DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); - set_reg_field_value( - value, - 1, - DPG_PIPE_STUTTER_CONTROL_NONLPTCH, - STUTTER_ENABLE_NONLPTCH); - dm_write_reg(compressor->ctx, - DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value); - - /* Enable Underlay pipe LPT Stutter */ - addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; - value = dm_read_reg(compressor->ctx, addr); - set_reg_field_value( - value, - 1, - DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, - STUTTER_ENABLE_NONLPTCH); - dm_write_reg(compressor->ctx, addr, value); - - /* Selection of Channel(s) containing Compressed Surface: 0xfffffff - * will disable LPT. - * STCTRL_LPT_TARGETn corresponds to channel n. */ - addr = mmLOW_POWER_TILING_CONTROL; - value_control = dm_read_reg(compressor->ctx, addr); - channels = get_reg_field_value(value_control, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_MODE); - - addr = mmGMCON_LPT_TARGET; - value = dm_read_reg(compressor->ctx, addr); - set_reg_field_value( - value, - channels + 1, /* not mentioned in programming guide, - but follow DCE8.1 */ - GMCON_LPT_TARGET, - STCTRL_LPT_TARGET); - dm_write_reg(compressor->ctx, addr, value); - - /* Enable LPT */ - addr = mmLOW_POWER_TILING_CONTROL; - value = dm_read_reg(compressor->ctx, addr); - set_reg_field_value( - value, - 1, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ENABLE); - dm_write_reg(compressor->ctx, addr, value); -} - -void dce110_compressor_program_lpt_control( - struct compressor *compressor, - struct compr_addr_and_pitch_params *params) -{ - struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); - uint32_t rows_per_channel; - uint32_t lpt_alignment; - uint32_t source_view_width; - uint32_t source_view_height; - uint32_t lpt_control = 0; - - if (!compressor->options.bits.LPT_SUPPORT) - return; - - lpt_control = dm_read_reg(compressor->ctx, - mmLOW_POWER_TILING_CONTROL); - - /* POSSIBLE VALUES for Low Power Tiling Mode: - * 00 - Use channel 0 - * 01 - Use Channel 0 and 1 - * 02 - Use Channel 0,1,2,3 - * 03 - reserved */ - switch (compressor->lpt_channels_num) { - /* case 2: - * Use Channel 0 & 1 / Not used for DCE 11 */ - case 1: - /*Use Channel 0 for LPT for DCE 11 */ - set_reg_field_value( - lpt_control, - 0, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_MODE); - break; - default: - dm_logger_write( - compressor->ctx->logger, LOG_WARNING, - "%s: Invalid selected DRAM channels for LPT!!!", - __func__); - break; - } - - lpt_control = lpt_memory_control_config(cp110, lpt_control); - - /* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on - * FBC compressed surface pitch. - * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height * - * Surface Pitch) / (Row Size * Number of Channels * - * Number of Banks)). */ - rows_per_channel = 0; - lpt_alignment = lpt_size_alignment(cp110); - source_view_width = - align_to_chunks_number_per_line( - cp110, - params->source_view_width); - source_view_height = (params->source_view_height + 1) & (~0x1); - - if (lpt_alignment != 0) { - rows_per_channel = source_view_width * source_view_height * 4; - rows_per_channel = - (rows_per_channel % lpt_alignment) ? - (rows_per_channel / lpt_alignment + 1) : - rows_per_channel / lpt_alignment; - } - - set_reg_field_value( - lpt_control, - rows_per_channel, - LOW_POWER_TILING_CONTROL, - LOW_POWER_TILING_ROWS_PER_CHAN); - - dm_write_reg(compressor->ctx, - mmLOW_POWER_TILING_CONTROL, lpt_control); -} - -/* - * DCE 11 Frame Buffer Compression Implementation - */ - void dce110_compressor_set_fbc_invalidation_triggers( struct compressor *compressor, uint32_t fbc_trigger) @@ -792,21 +367,20 @@ void dce110_compressor_set_fbc_invalidation_triggers( } bool dce110_compressor_construct(struct dce110_compressor *compressor, - struct dc_context *ctx) + struct dc_context *ctx) { - struct dc_bios *bp = ctx->dc_bios; - struct embedded_panel_info panel_info; compressor->base.options.bits.FBC_SUPPORT = true; - compressor->base.options.bits.LPT_SUPPORT = true; - /* For DCE 11 always use one DRAM channel for LPT */ + + /* for dce 11 always use one dram channel for lpt */ compressor->base.lpt_channels_num = 1; compressor->base.options.bits.DUMMY_BACKEND = false; - /* Check if this system has more than 1 DRAM channel; if only 1 then LPT - * should not be supported */ - if (compressor->base.memory_bus_width == 64) - compressor->base.options.bits.LPT_SUPPORT = false; + /* + * check if this system has more than 1 dram channel; if only 1 then lpt + * should not be supported + */ + compressor->base.options.bits.CLK_GATING_DISABLED = false; @@ -826,13 +400,6 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, compressor->base.attached_inst = 0; compressor->base.is_enabled = false; - if (BP_RESULT_OK == - bp->funcs->get_embedded_panel_info(bp, &panel_info)) { - compressor->base.embedded_panel_h_size = - panel_info.lcd_timing.horizontal_addressable; - compressor->base.embedded_panel_v_size = - panel_info.lcd_timing.vertical_addressable; - } return true; } @@ -857,3 +424,82 @@ void dce110_compressor_destroy(struct compressor **compressor) dm_free(TO_DCE110_COMPRESSOR(*compressor)); *compressor = NULL; } + +bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info, + struct fbc_requested_compressed_size size) +{ + bool result = false; + + unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y; + + get_max_support_fbc_buffersize(&max_x, &max_y); + + if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) { + /* + * For DCE11 here use Max HW supported size: HW Support up to 3840x2400 resolution + * or 18000 chunks. + */ + size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4; /* (For FBC when LPT not supported). */ + size.preferred_size_alignment = size.min_size_alignment = 0x100; /* For FBC when LPT not supported */ + size.bits.preferred_must_be_framebuffer_pool = 1; + size.bits.min_must_be_framebuffer_pool = 1; + + result = true; + } + /* + * Maybe to add registry key support with optional size here to override above + * for debugging purposes + */ + + return result; +} + + +void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y) +{ + *max_x = FBC_MAX_X; + *max_y = FBC_MAX_Y; + + /* if (m_smallLocalFrameBufferMemory == 1) + * { + * *max_x = FBC_MAX_X_SG; + * *max_y = FBC_MAX_Y_SG; + * } + */ +} + + +unsigned int controller_id_to_index(enum controller_id controller_id) +{ + unsigned int index = 0; + + switch (controller_id) { + case CONTROLLER_ID_D0: + index = 0; + break; + case CONTROLLER_ID_D1: + index = 1; + break; + case CONTROLLER_ID_D2: + index = 2; + break; + case CONTROLLER_ID_D3: + index = 3; + break; + default: + break; + } + return index; +} + + +static const struct compressor_funcs dce110_compressor_funcs = { + .power_up_fbc = dce110_compressor_power_up_fbc, + .enable_fbc = dce110_compressor_enable_fbc, + .disable_fbc = dce110_compressor_disable_fbc, + .set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers, + .surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch, + .is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw +}; + + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h index 22af5be51581..ff21c86df828 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h @@ -75,4 +75,7 @@ void dce110_compressor_program_lpt_control(struct compressor *cp, bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp); +void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y); + #endif + diff --git a/drivers/gpu/drm/amd/display/dc/inc/compressor.h b/drivers/gpu/drm/amd/display/dc/inc/compressor.h index af292596b101..5fdc2fc10231 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/compressor.h +++ b/drivers/gpu/drm/amd/display/dc/inc/compressor.h @@ -45,6 +45,7 @@ union fbc_physical_address { }; struct compr_addr_and_pitch_params { + enum controller_id controller_id; uint32_t inst; uint32_t source_view_width; uint32_t source_view_height; @@ -52,14 +53,32 @@ struct compr_addr_and_pitch_params { enum fbc_hw_max_resolution_supported { FBC_MAX_X = 3840, - FBC_MAX_Y = 2400 + FBC_MAX_Y = 2400, + FBC_MAX_X_SG = 1920, + FBC_MAX_Y_SG = 1080, }; +struct compressor; + +struct compressor_funcs { + + void (*power_up_fbc)(struct compressor *cp); + void (*enable_fbc)(struct compressor *cp, uint32_t paths_num, + struct compr_addr_and_pitch_params *params); + void (*disable_fbc)(struct compressor *cp); + void (*set_fbc_invalidation_triggers)(struct compressor *cp, + uint32_t fbc_trigger); + void (*surface_address_and_pitch)( + struct compressor *cp, + struct compr_addr_and_pitch_params *params); + bool (*is_fbc_enabled_in_hw)(struct compressor *cp, + uint32_t *fbc_mapped_crtc_id); +}; struct compressor { struct dc_context *ctx; uint32_t attached_inst; bool is_enabled; - + const struct compressor_funcs funcs; union { uint32_t raw; struct { @@ -90,4 +109,27 @@ struct compressor { enum fbc_compress_ratio min_compress_ratio; }; +struct fbc_input_info { + bool dynamic_fbc_buffer_alloc; + unsigned int source_view_width; + unsigned int source_view_height; + unsigned int num_of_active_targets; +}; + + +struct fbc_requested_compressed_size { + unsigned int preferred_size; + unsigned int preferred_size_alignment; + unsigned int min_size; + unsigned int min_size_alignment; + union { + struct { + /* Above preferedSize must be allocated in FB pool */ + unsigned int preferred_must_be_framebuffer_pool : 1; + /* Above minSize must be allocated in FB pool */ + unsigned int min_must_be_framebuffer_pool : 1; + } bits; + unsigned int flags; + }; +}; #endif -- cgit v1.2.3-59-g8ed1b From cfe4645e17f8dbe680c35c439d000313f2648482 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 14 Jun 2017 18:58:04 -0400 Subject: drm/amd/display: fix dcn pipe reset sequence This change fixes dcn10 front end reset sequence. Previously we would reset front end during flip which led to issues in certain MPO and 4k/5k scenarios. We would also never properly power gate our front end. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 19 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 22 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 + drivers/gpu/drm/amd/display/dc/dc.h | 3 - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 17 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 226 ++++++++++----------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 17 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 4 +- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 6 +- .../amd/display/dc/dcn10/dcn10_timing_generator.h | 4 + drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- 13 files changed, 155 insertions(+), 175 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 3711176bd070..a6f27ceaf4af 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2380,7 +2380,7 @@ static void amdgpu_dm_do_flip( surface_updates->flip_addr = &addr; - dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, acrtc->stream); + dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc->stream, NULL); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 3ec702fecfd1..00961bc37200 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -511,12 +511,14 @@ static void split_stream_across_pipes( struct pipe_ctx *primary_pipe, struct pipe_ctx *secondary_pipe) { + int pipe_idx = secondary_pipe->pipe_idx; + if (!primary_pipe->surface) return; - secondary_pipe->stream = primary_pipe->stream; - secondary_pipe->tg = primary_pipe->tg; + *secondary_pipe = *primary_pipe; + secondary_pipe->pipe_idx = pipe_idx; secondary_pipe->mpcc = pool->mpcc[secondary_pipe->pipe_idx]; secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx]; secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx]; @@ -528,8 +530,6 @@ static void split_stream_across_pipes( } primary_pipe->bottom_pipe = secondary_pipe; secondary_pipe->top_pipe = primary_pipe; - secondary_pipe->surface = primary_pipe->surface; - secondary_pipe->pipe_dlg_param = primary_pipe->pipe_dlg_param; resource_build_scaling_params(primary_pipe); resource_build_scaling_params(secondary_pipe); @@ -1011,10 +1011,13 @@ bool dcn_validate_bandwidth( dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe); } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { /* merge previously split pipe */ - if (pipe->bottom_pipe->bottom_pipe) - pipe->bottom_pipe->bottom_pipe->top_pipe = pipe; - memset(pipe->bottom_pipe, 0, sizeof(*pipe->bottom_pipe)); - pipe->bottom_pipe = pipe->bottom_pipe->bottom_pipe; + pipe->bottom_pipe = hsplit_pipe->bottom_pipe; + if (hsplit_pipe->bottom_pipe) + hsplit_pipe->bottom_pipe->top_pipe = pipe; + hsplit_pipe->surface = NULL; + hsplit_pipe->stream = NULL; + hsplit_pipe->top_pipe = NULL; + hsplit_pipe->bottom_pipe = NULL; resource_build_scaling_params(pipe); } /* for now important to do this after pipe split for building e2e params */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 18fde5081742..2f481ef55490 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -963,11 +963,8 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) for (i = 0; i < core_dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].surface == NULL) { - context->res_ctx.pipe_ctx[i].pipe_idx = i; - core_dc->hwss.power_down_front_end( - core_dc, &context->res_ctx.pipe_ctx[i]); - } + || context->res_ctx.pipe_ctx[i].surface == NULL) + core_dc->hwss.power_down_front_end(core_dc, i); /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -989,7 +986,6 @@ bool dc_commit_surfaces_to_stream( struct dc_plane_info plane_info[MAX_SURFACES]; struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; - bool ret; struct dc_stream_update *stream_update = dm_alloc(sizeof(struct dc_stream_update)); @@ -1038,10 +1034,10 @@ bool dc_commit_surfaces_to_stream( new_surface_count, dc_stream, stream_update); - ret = dc_post_update_surfaces_to_stream(dc); + dc_post_update_surfaces_to_stream(dc); dm_free(stream_update); - return ret; + return true; } static bool is_surface_in_context( @@ -1217,14 +1213,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream( return overall_type; } -void dc_update_surfaces_for_stream(struct dc *dc, - struct dc_surface_update *surface_updates, int surface_count, - const struct dc_stream *dc_stream) -{ - dc_update_surfaces_and_stream(dc, surface_updates, surface_count, - dc_stream, NULL); -} - enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, @@ -1401,7 +1389,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, } } - if (!surface_count) /* reset */ + if (surface_count == 0) core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); /* Lock pipes for provided surfaces, or all active if full update*/ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index f0183d5f0d0d..fb033b69e2bf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1096,6 +1096,10 @@ bool resource_attach_surfaces_to_context( free_pipe->surface = surface; if (tail_pipe) { + free_pipe->tg = tail_pipe->tg; + free_pipe->stream_enc = tail_pipe->stream_enc; + free_pipe->audio = tail_pipe->audio; + free_pipe->clock_source = tail_pipe->clock_source; free_pipe->top_pipe = tail_pipe; tail_pipe->bottom_pipe = free_pipe; } @@ -2300,6 +2304,9 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx) { + if (!pipe_ctx_old->stream) + return false; + if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) return true; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index cb70b6d8be10..18f6858e4992 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -415,9 +415,6 @@ bool dc_commit_surfaces_to_stream( bool dc_post_update_surfaces_to_stream( struct dc *dc); -void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, - int surface_count, const struct dc_stream *stream); - /* Surface update type is used by dc_update_surfaces_and_stream * The update type is determined at the very beginning of the function based * on parameters passed in and decides how much programming (or updating) is diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 0bab85b27a85..fd1cb7fe45bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1185,8 +1185,7 @@ static void disable_vga_and_power_gate_all_controllers( enable_display_pipe_clock_gating(ctx, true); - dc->hwss.power_down_front_end( - dc, &dc->current_context->res_ctx.pipe_ctx[i]); + dc->hwss.power_down_front_end(dc, i); } } @@ -1340,7 +1339,7 @@ static void reset_single_pipe_hw_ctx( resource_unreference_clock_source(&context->res_ctx, dc->res_pool, &pipe_ctx->clock_source); - dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); + dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx->pipe_idx); pipe_ctx->stream = NULL; } @@ -2538,17 +2537,17 @@ static void dce110_apply_ctx_for_surface( } } -static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) +static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ - if (pipe->stream) + if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) return; dc->hwss.enable_display_power_gating( - dc, pipe->pipe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); - if (pipe->xfm) - pipe->xfm->funcs->transform_reset(pipe->xfm); - memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); + dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); + + dc->res_pool->transforms[fe_idx]->funcs->transform_reset( + dc->res_pool->transforms[fe_idx]); } static const struct hw_sequencer_funcs dce110_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index edcd7369cf9d..d0bddfd64c67 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -116,18 +116,6 @@ static const struct dcn10_hwseq_reg_offsets reg_offsets[] = { HWSEQ_REG_SET_N(reg, 1, FD(reg##__##field), val) /* TODO should be moved to OTG */ -static void lock_otg_master_update( - struct dc_context *ctx, - uint8_t inst) -{ - uint32_t inst_offset = reg_offsets[inst].otg; - - HWSEQ_REG_UPDATE(OTG0_OTG_GLOBAL_CONTROL0, - OTG_MASTER_UPDATE_LOCK_SEL, inst); - - HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK, - OTG_MASTER_UPDATE_LOCK, 1); -} static bool unlock_master_tg_and_wait( struct dc_context *ctx, @@ -148,19 +136,6 @@ static bool unlock_master_tg_and_wait( return true; } -/* TODO: should be moved to OTG ? */ -static void unlock_otg_master( - struct dc_context *ctx, - uint8_t inst) -{ - uint32_t inst_offset = reg_offsets[inst].otg; - - /* unlock master locker */ - HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK, - OTG_MASTER_UPDATE_LOCK, 0); -} - - static void wait_no_outstanding_request( struct dc_context *ctx, uint8_t plane_id) @@ -489,8 +464,7 @@ static void hubp_pg_control( static void power_on_plane( struct dc_context *ctx, - uint8_t plane_id, - uint8_t inst) + int plane_id) { uint32_t inst_offset = 0; @@ -500,6 +474,8 @@ static void power_on_plane( hubp_pg_control(ctx, plane_id, true); HWSEQ_REG_SET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, 0); + dm_logger_write(ctx->logger, LOG_DC, + "Un-gated front end for pipe %d\n", plane_id); } /* fully check bios enabledisplaypowergating table. dal only need dce init @@ -596,13 +572,13 @@ static void init_hw(struct core_dc *dc) dc->res_pool->mpcc[i]; struct mpcc_cfg mpcc_cfg; - lock_otg_master_update(dc->ctx, tg->inst); + tg->funcs->lock(tg); mpcc_cfg.opp_id = 0xf; mpcc_cfg.top_dpp_id = 0xf; mpcc_cfg.bot_mpcc_id = 0xf; mpcc_cfg.top_of_tree = true; mpcc->funcs->set(mpcc, &mpcc_cfg); - unlock_otg_master(dc->ctx, tg->inst); + tg->funcs->unlock(tg); tg->funcs->disable_vga(tg); /* Blank controller using driver code instead of @@ -822,56 +798,85 @@ static void reset_back_end_for_pipe( return; pipe_ctx->stream = NULL; + dm_logger_write(dc->ctx->logger, LOG_DC, + "Reset back end for pipe %d, tg:%d\n", + pipe_ctx->pipe_idx, pipe_ctx->tg->inst); } -static void reset_front_end_for_pipe( +static void reset_front_end( struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) + int fe_idx) { struct mpcc_cfg mpcc_cfg; + struct mem_input *mi = dc->res_pool->mis[fe_idx]; + struct transform *xfm = dc->res_pool->transforms[fe_idx]; + struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx]; + struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id]; - if (!pipe_ctx->surface) + /*Already reset*/ + if (mpcc->opp_id == 0xf) return; - pipe_ctx->mi->funcs->dcc_control(pipe_ctx->mi, false, false); - - lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst); + mi->funcs->dcc_control(mi, false, false); + tg->funcs->lock(tg); mpcc_cfg.opp_id = 0xf; mpcc_cfg.top_dpp_id = 0xf; mpcc_cfg.bot_mpcc_id = 0xf; - mpcc_cfg.top_of_tree = !pipe_ctx->top_pipe; - pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); - - pipe_ctx->top_pipe = NULL; - pipe_ctx->bottom_pipe = NULL; + mpcc_cfg.top_of_tree = tg->inst == mpcc->inst; + mpcc->funcs->set(mpcc, &mpcc_cfg); - unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst); + unlock_master_tg_and_wait(dc->ctx, tg->inst); + mpcc->funcs->wait_for_idle(mpcc); + mi->funcs->set_blank(mi, true); + wait_no_outstanding_request(dc->ctx, fe_idx); + disable_clocks(dc->ctx, fe_idx); - pipe_ctx->mi->funcs->set_blank(pipe_ctx->mi, true); + xfm->funcs->transform_reset(xfm); - wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx); + dm_logger_write(dc->ctx->logger, LOG_DC, + "Reset front end %d\n", + fe_idx); +} - disable_clocks(dc->ctx, pipe_ctx->pipe_idx); +static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) +{ + struct dc_context *ctx = dc->ctx; + uint32_t inst_offset = 0; - pipe_ctx->xfm->funcs->transform_reset(pipe_ctx->xfm); + reset_front_end(dc, fe_idx); + HWSEQ_REG_SET(DC_IP_REQUEST_CNTL, + IP_REQUEST_EN, 1); + dpp_pg_control(ctx, fe_idx, false); + hubp_pg_control(ctx, fe_idx, false); + HWSEQ_REG_SET(DC_IP_REQUEST_CNTL, + IP_REQUEST_EN, 0); dm_logger_write(dc->ctx->logger, LOG_DC, - "Reset front end for pipe %d\n", - pipe_ctx->pipe_idx); - - pipe_ctx->surface = NULL; + "Power gated front end %d\n", fe_idx); } -static void reset_hw_ctx(struct core_dc *dc, - struct validate_context *context, - void (*reset)(struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context)) +static void reset_hw_ctx_wrap( + struct core_dc *dc, + struct validate_context *context) { int i; + /* Reset Front End*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + /*if (!pipe_ctx_old->stream) + continue;*/ + + if (!pipe_ctx->stream || !pipe_ctx->surface) + dcn10_power_down_fe(dc, i); + else if (pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + reset_front_end(dc, i); + } + /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; @@ -882,23 +887,13 @@ static void reset_hw_ctx(struct core_dc *dc, if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - reset(dc, pipe_ctx_old, dc->current_context); + reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context); } } -static void reset_hw_ctx_wrap( - struct core_dc *dc, - struct validate_context *context) -{ - /* Reset Front End*/ - reset_hw_ctx(dc, context, reset_front_end_for_pipe); - /* Reset Back End*/ - reset_hw_ctx(dc, context, reset_back_end_for_pipe); -} - -static bool patch_address_for_sbs_tb_stereo(struct pipe_ctx *pipe_ctx, - PHYSICAL_ADDRESS_LOC *addr) +static bool patch_address_for_sbs_tb_stereo( + struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { struct core_surface *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && @@ -936,8 +931,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct core_surface *surface) + struct pipe_ctx *pipe_ctx, const struct core_surface *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct core_transfer_func *tf = NULL; @@ -950,8 +944,8 @@ static bool dcn10_set_input_transfer_func( tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); if (surface->public.gamma_correction && dce_use_lut(surface)) - ipp->funcs->ipp_program_input_lut(ipp, - surface->public.gamma_correction); + ipp->funcs->ipp_program_input_lut(ipp, + surface->public.gamma_correction); if (tf == NULL) ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); @@ -1333,8 +1327,6 @@ static void dcn10_pipe_control_lock( struct pipe_ctx *pipe, bool lock) { - struct dce_hwseq *hws = hws = dc->hwseq; - /* use TG master update lock to lock everything on the TG * therefore only top pipe need to lock */ @@ -1342,9 +1334,9 @@ static void dcn10_pipe_control_lock( return; if (lock) - dcn10_lock(pipe->tg); + pipe->tg->funcs->lock(pipe->tg); else - dcn10_unlock(pipe->tg); + pipe->tg->funcs->unlock(pipe->tg); } static bool wait_for_reset_trigger_to_occur( @@ -1543,7 +1535,7 @@ static void dcn10_power_on_fe( struct dc_surface *dc_surface = &pipe_ctx->surface->public; power_on_plane(dc->ctx, - pipe_ctx->pipe_idx, pipe_ctx->tg->inst); + pipe_ctx->pipe_idx); /* enable DCFCLK current DCHUB */ enable_dcfclk(dc->ctx, @@ -1694,7 +1686,6 @@ static void update_dchubp_dpp( struct default_adjustment ocsc = {0}; struct tg_color black_color = {0}; struct mpcc_cfg mpcc_cfg; - struct pipe_ctx *top_pipe; bool per_pixel_alpha = surface->public.per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ @@ -1734,14 +1725,13 @@ static void update_dchubp_dpp( IPP_OUTPUT_FORMAT_12_BIT_FIX); pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha; - for (top_pipe = pipe_ctx; top_pipe != NULL; top_pipe = top_pipe->top_pipe) - mpcc_cfg.opp_id = top_pipe->opp->inst; mpcc_cfg.top_dpp_id = pipe_ctx->pipe_idx; if (pipe_ctx->bottom_pipe) mpcc_cfg.bot_mpcc_id = pipe_ctx->bottom_pipe->mpcc->inst; else mpcc_cfg.bot_mpcc_id = 0xf; - mpcc_cfg.top_of_tree = !pipe_ctx->top_pipe; + mpcc_cfg.opp_id = pipe_ctx->tg->inst; + mpcc_cfg.top_of_tree = pipe_ctx->pipe_idx == pipe_ctx->tg->inst; mpcc_cfg.per_pixel_alpha = per_pixel_alpha; /* DCN1.0 has output CM before MPC which seems to screw with * pre-multiplied alpha. @@ -1749,8 +1739,6 @@ static void update_dchubp_dpp( mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace( pipe_ctx->stream->public.output_color_space) && per_pixel_alpha; - if (!dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].surface) - pipe_ctx->mpcc->funcs->wait_for_idle(pipe_ctx->mpcc); pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); color_space_to_black_color( @@ -1796,7 +1784,7 @@ static void program_all_pipe_in_tree( /* watermark is for all pipes */ pipe_ctx->mi->funcs->program_watermarks( pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz); - lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst); + pipe_ctx->tg->funcs->lock(pipe_ctx->tg); pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; @@ -1852,13 +1840,41 @@ static void dcn10_apply_ctx_for_surface( { int i; + /* reset unused mpcc */ + /*for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = + &dc->current_context->res_ctx.pipe_ctx[i]; + + if ((!pipe_ctx->surface && old_pipe_ctx->surface) + || (!pipe_ctx->stream && old_pipe_ctx->stream)) { + struct mpcc_cfg mpcc_cfg; + + mpcc_cfg.opp_id = 0xf; + mpcc_cfg.top_dpp_id = 0xf; + mpcc_cfg.bot_mpcc_id = 0xf; + mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe; + old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg); + + old_pipe_ctx->top_pipe = NULL; + old_pipe_ctx->bottom_pipe = NULL; + old_pipe_ctx->surface = NULL; + + dm_logger_write(dc->ctx->logger, LOG_DC, + "Reset mpcc for pipe %d\n", + old_pipe_ctx->pipe_idx); + } + }*/ + + if (!surface) + return; + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (!pipe_ctx->surface || pipe_ctx->surface != surface) + if (pipe_ctx->surface != surface) continue; - /* looking for top pipe to program */ if (!pipe_ctx->top_pipe) program_all_pipe_in_tree(dc, pipe_ctx, context); @@ -1910,27 +1926,6 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns, context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (!pipe_ctx->surface || pipe_ctx->top_pipe) - continue; - - /* unlock master update lock */ - unlock_otg_master(dc->ctx, pipe_ctx->tg->inst); - } - - /* reset unused pipe */ - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; - - if ((!pipe_ctx->surface && old_pipe_ctx->surface) - || (!pipe_ctx->stream && old_pipe_ctx->stream)) - reset_front_end_for_pipe(dc, old_pipe_ctx, dc->current_context); - } } static void dcn10_set_bandwidth( @@ -1992,23 +1987,6 @@ static void dcn10_set_bandwidth( dcn10_pplib_apply_display_requirements(dc, context); } -static void dcn10_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) -{ - struct dc_context *ctx = dc->ctx; - uint32_t inst_offset = 0; - - HWSEQ_REG_SET(DC_IP_REQUEST_CNTL, - IP_REQUEST_EN, 1); - dpp_pg_control(ctx, pipe->pipe_idx, false); - hubp_pg_control(ctx, pipe->pipe_idx, false); - HWSEQ_REG_SET(DC_IP_REQUEST_CNTL, - IP_REQUEST_EN, 0); - - if (pipe->xfm) - pipe->xfm->funcs->transform_reset(pipe->xfm); - memset(&pipe->scl_data, 0, sizeof(pipe->scl_data)); -} - static void set_drr(struct pipe_ctx **pipe_ctx, int num_pipes, int vmin, int vmax) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index b1c590d4f454..7af04bce3599 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -65,17 +65,17 @@ void dcn10_mpcc_set_bg_color( static void set_output_mux(struct dcn10_mpcc *mpcc10, int opp_id, int mpcc_id) { - ASSERT(mpcc10->opp_id == 0xf || opp_id == mpcc10->opp_id); - mpcc10->opp_id = opp_id; + ASSERT(mpcc10->base.opp_id == 0xf || opp_id == mpcc10->base.opp_id); + mpcc10->base.opp_id = opp_id; REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1); REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id); } static void reset_output_mux(struct dcn10_mpcc *mpcc10) { - REG_SET(MUX[mpcc10->opp_id], 0, MPC_OUT_MUX, 0xf); - REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->opp_id], OPP_PIPE_CLOCK_EN, 0); - mpcc10->opp_id = 0xf; + REG_SET(MUX[mpcc10->base.opp_id], 0, MPC_OUT_MUX, 0xf); + REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->base.opp_id], OPP_PIPE_CLOCK_EN, 0); + mpcc10->base.opp_id = 0xf; } static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) @@ -104,16 +104,17 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) if (cfg->top_of_tree) { if (cfg->opp_id != 0xf) set_output_mux(mpcc10, cfg->opp_id, mpcc->inst); - else + else if (mpcc->opp_id != 0xf) reset_output_mux(mpcc10); } + mpcc10->base.opp_id = cfg->opp_id; } static void dcn10_mpcc_wait_idle(struct mpcc *mpcc) { struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc); - REG_WAIT(MPCC_STATUS, MPCC_IDLE, 1, 1000, 1000); + REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000); } @@ -139,5 +140,5 @@ void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10, mpcc10->mpcc_shift = mpcc_shift; mpcc10->mpcc_mask = mpcc_mask; - mpcc10->opp_id = inst; + mpcc10->base.opp_id = inst; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index 0f9f1b97d238..fff267455a3d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -68,6 +68,7 @@ struct dcn_mpcc_registers { SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ @@ -83,6 +84,7 @@ struct dcn_mpcc_registers { type MPCC_ALPHA_MULTIPLIED_MODE;\ type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\ type MPCC_IDLE;\ + type MPCC_BUSY;\ type MPCC_OPP_ID;\ type MPCC_BG_G_Y;\ type MPCC_BG_R_CR;\ @@ -103,8 +105,6 @@ struct dcn10_mpcc { const struct dcn_mpcc_registers *mpcc_regs; const struct dcn_mpcc_shift *mpcc_shift; const struct dcn_mpcc_mask *mpcc_mask; - - int opp_id; }; void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 58fb29ff5677..802ace2e5212 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -575,6 +575,8 @@ void dcn10_lock(struct timing_generator *tg) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + REG_SET(OTG_GLOBAL_CONTROL0, 0, + OTG_MASTER_UPDATE_LOCK_SEL, tg->inst); REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); } @@ -587,9 +589,9 @@ void dcn10_unlock(struct timing_generator *tg) OTG_MASTER_UPDATE_LOCK, 0); /* why are we waiting here? */ - REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, + /*REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, 0, - 20000, 200000); + 20000, 200000);*/ } static void dcn10_get_position(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index c880fa587790..3b2a20a4b957 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -37,6 +37,7 @@ SRI(OTG_VREADY_PARAM, OTG, inst),\ SRI(OTG_BLANK_CONTROL, OTG, inst),\ SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ SRI(OTG_H_TOTAL, OTG, inst),\ SRI(OTG_H_BLANK_START_END, OTG, inst),\ @@ -83,6 +84,7 @@ struct dcn_tg_registers { uint32_t OTG_VREADY_PARAM; uint32_t OTG_BLANK_CONTROL; uint32_t OTG_MASTER_UPDATE_LOCK; + uint32_t OTG_GLOBAL_CONTROL0; uint32_t OTG_DOUBLE_BUFFER_CONTROL; uint32_t OTG_H_TOTAL; uint32_t OTG_H_BLANK_START_END; @@ -134,6 +136,7 @@ struct dcn_tg_registers { SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ @@ -224,6 +227,7 @@ struct dcn_tg_registers { type OTG_CURRENT_BLANK_STATE;\ type OTG_MASTER_UPDATE_LOCK;\ type OTG_UPDATE_PENDING;\ + type OTG_MASTER_UPDATE_LOCK_SEL;\ type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ type OTG_H_TOTAL;\ type OTG_H_BLANK_START;\ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 51bc8ef5ef79..55c9c305a259 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -40,6 +40,7 @@ struct mpcc { const struct mpcc_funcs *funcs; struct dc_context *ctx; int inst; + int opp_id; }; struct mpcc_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 52884815c67b..642ae5e4ee1c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -105,7 +105,7 @@ struct hw_sequencer_funcs { struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct core_dc *dc, struct pipe_ctx *pipe); + void (*power_down_front_end)(struct core_dc *dc, int fe_idx); void (*power_on_front_end)(struct core_dc *dc, struct pipe_ctx *pipe, -- cgit v1.2.3-59-g8ed1b From 1663ae1c4288da81b9f1668d204aa8ed55ebf849 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 27 Jun 2017 16:34:27 -0400 Subject: drm/amd/display: Connect DC resource to FBC compressor - Connected DC resource to FBC compressor, - Initial Implementation of FBC for Stoney/Carrizo - Code is currently guarded with "ENABLE_FBC" compile time flag Signed-off-by: Bhawanpreet Lakha Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ++++++ .../drm/amd/display/dc/dce110/dce110_compressor.c | 78 +++++++++++----------- .../drm/amd/display/dc/dce110/dce110_compressor.h | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 15 +++++ .../drm/amd/display/dc/dce110/dce110_resource.c | 10 +++ drivers/gpu/drm/amd/display/dc/inc/compressor.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 6 ++ 7 files changed, 94 insertions(+), 42 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 2f481ef55490..51e4cb30f858 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -843,6 +843,11 @@ bool dc_enable_stereo( int i, j; struct pipe_ctx *pipe; struct core_dc *core_dc = DC_TO_CORE(dc); + +#ifdef ENABLE_FBC + struct compressor *fbc_compressor = core_dc->fbc_compressor; +#endif + for (i = 0; i < MAX_PIPES; i++) { if (context != NULL) pipe = &context->res_ctx.pipe_ctx[i]; @@ -854,6 +859,14 @@ bool dc_enable_stereo( core_dc->hwss.setup_stereo(pipe, core_dc); } } + +#ifdef ENABLE_FBC + if (fbc_compressor != NULL && + fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor, + &pipe->tg->inst)) + fbc_compressor->funcs->disable_fbc(fbc_compressor); + +#endif return ret; } @@ -1232,6 +1245,12 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (!stream_status) return; /* Cannot commit surface to stream that is not committed */ +#ifdef ENABLE_FBC + if (srf_updates->flip_addr) { + if (srf_updates->flip_addr->address.grph.addr.low_part == 0) + ASSERT(0); + } +#endif context = core_dc->current_context; /* update current stream with the new updates */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 5fe83045d1a6..1e59f4e31a6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -175,7 +175,6 @@ void dce110_compressor_power_up_fbc(struct compressor *compressor) void dce110_compressor_enable_fbc( struct compressor *compressor, - uint32_t paths_num, struct compr_addr_and_pitch_params *params) { struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); @@ -366,43 +365,6 @@ void dce110_compressor_set_fbc_invalidation_triggers( dm_write_reg(compressor->ctx, addr, value); } -bool dce110_compressor_construct(struct dce110_compressor *compressor, - struct dc_context *ctx) -{ - - compressor->base.options.bits.FBC_SUPPORT = true; - - /* for dce 11 always use one dram channel for lpt */ - compressor->base.lpt_channels_num = 1; - compressor->base.options.bits.DUMMY_BACKEND = false; - - /* - * check if this system has more than 1 dram channel; if only 1 then lpt - * should not be supported - */ - - - compressor->base.options.bits.CLK_GATING_DISABLED = false; - - compressor->base.ctx = ctx; - compressor->base.embedded_panel_h_size = 0; - compressor->base.embedded_panel_v_size = 0; - compressor->base.memory_bus_width = ctx->asic_id.vram_width; - compressor->base.allocated_size = 0; - compressor->base.preferred_requested_size = 0; - compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; - compressor->base.banks_num = 0; - compressor->base.raw_size = 0; - compressor->base.channel_interleave_size = 0; - compressor->base.dram_channels_num = 0; - compressor->base.lpt_channels_num = 0; - compressor->base.attached_inst = 0; - compressor->base.is_enabled = false; - - return true; -} - struct compressor *dce110_compressor_create(struct dc_context *ctx) { struct dce110_compressor *cp110 = @@ -503,3 +465,43 @@ static const struct compressor_funcs dce110_compressor_funcs = { }; +bool dce110_compressor_construct(struct dce110_compressor *compressor, + struct dc_context *ctx) +{ + + compressor->base.options.bits.FBC_SUPPORT = true; + + /* for dce 11 always use one dram channel for lpt */ + compressor->base.lpt_channels_num = 1; + compressor->base.options.bits.DUMMY_BACKEND = false; + + /* + * check if this system has more than 1 dram channel; if only 1 then lpt + * should not be supported + */ + + + compressor->base.options.bits.CLK_GATING_DISABLED = false; + + compressor->base.ctx = ctx; + compressor->base.embedded_panel_h_size = 0; + compressor->base.embedded_panel_v_size = 0; + compressor->base.memory_bus_width = ctx->asic_id.vram_width; + compressor->base.allocated_size = 0; + compressor->base.preferred_requested_size = 0; + compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; + compressor->base.options.raw = 0; + compressor->base.banks_num = 0; + compressor->base.raw_size = 0; + compressor->base.channel_interleave_size = 0; + compressor->base.dram_channels_num = 0; + compressor->base.lpt_channels_num = 0; + compressor->base.attached_inst = 0; + compressor->base.is_enabled = false; +#ifdef ENABLE_FBC + compressor->base.funcs = &dce110_compressor_funcs; + +#endif + return true; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h index ff21c86df828..460cb77b8d75 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h @@ -50,7 +50,7 @@ void dce110_compressor_destroy(struct compressor **cp); /* FBC RELATED */ void dce110_compressor_power_up_fbc(struct compressor *cp); -void dce110_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num, +void dce110_compressor_enable_fbc(struct compressor *cp, struct compr_addr_and_pitch_params *params); void dce110_compressor_disable_fbc(struct compressor *cp); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index fd1cb7fe45bc..72d5f753949d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -33,6 +33,10 @@ #include "dce110_timing_generator.h" #include "dce/dce_hwseq.h" +#ifdef ENABLE_FBC +#include "dce110_compressor.h" +#endif + #include "bios/bios_parser_helper.h" #include "timing_generator.h" #include "mem_input.h" @@ -1166,6 +1170,10 @@ static void power_down_all_hw_blocks(struct core_dc *dc) power_down_controllers(dc); power_down_clock_sources(dc); + +#ifdef ENABLE_FBC + dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); +#endif } static void disable_vga_and_power_gate_all_controllers( @@ -1630,6 +1638,10 @@ enum dc_status dce110_apply_ctx_to_hw( } set_safe_displaymarks(&context->res_ctx, dc->res_pool); + +#ifdef ENABLE_FBC + dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); +#endif /*TODO: when pplib works*/ apply_min_clocks(dc, context, &clocks_state, true); @@ -2215,6 +2227,9 @@ static void init_hw(struct core_dc *dc) abm->funcs->init_backlight(abm); abm->funcs->abm_init(abm); } +#ifdef ENABLE_FBC + dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); +#endif } void dce110_fill_display_configs( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 45759b9f15e5..8b7bc1cc2b7b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -52,6 +52,10 @@ #include "dce/dce_abm.h" #include "dce/dce_dmcu.h" +#ifdef ENABLE_FBC +#include "dce110/dce110_compressor.h" +#endif + #include "reg_helper.h" #include "dce/dce_11_0_d.h" @@ -1347,6 +1351,12 @@ static bool construct( } } +#ifdef ENABLE_FBC + dc->fbc_compressor = dce110_compressor_create(ctx); + + + +#endif if (!underlay_create(ctx, &pool->base)) goto res_create_fail; diff --git a/drivers/gpu/drm/amd/display/dc/inc/compressor.h b/drivers/gpu/drm/amd/display/dc/inc/compressor.h index 5fdc2fc10231..24cca18f3c8f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/compressor.h +++ b/drivers/gpu/drm/amd/display/dc/inc/compressor.h @@ -45,7 +45,7 @@ union fbc_physical_address { }; struct compr_addr_and_pitch_params { - enum controller_id controller_id; + /* enum controller_id controller_id; */ uint32_t inst; uint32_t source_view_width; uint32_t source_view_height; @@ -63,7 +63,7 @@ struct compressor; struct compressor_funcs { void (*power_up_fbc)(struct compressor *cp); - void (*enable_fbc)(struct compressor *cp, uint32_t paths_num, + void (*enable_fbc)(struct compressor *cp, struct compr_addr_and_pitch_params *params); void (*disable_fbc)(struct compressor *cp); void (*set_fbc_invalidation_triggers)(struct compressor *cp, @@ -78,7 +78,7 @@ struct compressor { struct dc_context *ctx; uint32_t attached_inst; bool is_enabled; - const struct compressor_funcs funcs; + const struct compressor_funcs *funcs; union { uint32_t raw; struct { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index 392cff2cd558..785236a44aee 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -10,6 +10,7 @@ #include "core_types.h" #include "hw_sequencer.h" +#include "compressor.h" #define DC_TO_CORE(dc)\ container_of(dc, struct core_dc, public) @@ -44,6 +45,11 @@ struct core_dc { * to compare to see if display config changed */ struct dm_pp_display_configuration prev_display_config; + + /* FBC compressor */ +#ifdef ENABLE_FBC + struct compressor *fbc_compressor; +#endif }; #endif /* __CORE_DC_H__ */ -- cgit v1.2.3-59-g8ed1b From c3aa1d67295c8fc87364dfe8920c9e30775fd124 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 30 Jun 2017 15:19:55 -0400 Subject: drm/amd/display: Set static screen register for stoney/carrizo -Set CRTC_STATIC_SCREEN_EVENT for stoney/carrizo for FBC implementation -Code is currently guarded with "ENABLE_FBC" compile time flag Signed-off-by: Bhawanpreet Lakha Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 72d5f753949d..8778af76f4e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1395,6 +1395,10 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, if (events->cursor_update) value |= 0x2; +#ifdef ENABLE_FBC + value |= 0x84; +#endif + for (i = 0; i < num_pipes; i++) pipe_ctx[i]->tg->funcs-> set_static_screen_control(pipe_ctx[i]->tg, value); -- cgit v1.2.3-59-g8ed1b From 97416d4cbb9efab2eea7740fa4ce86b317da06c5 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 26 Jun 2017 16:25:10 -0400 Subject: drm/amd/display: set drr during program timing. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_timing_generator.c | 21 +++++++++++++++++++++ .../amd/display/dc/dce120/dce120_timing_generator.c | 19 ++++++++++++++++--- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 8 ++++++++ 3 files changed, 45 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index ec599276ed2e..7f93d6d83cfd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -629,6 +629,27 @@ void dce110_timing_generator_program_blanking( CRTC_V_TOTAL); dm_write_reg(ctx, addr, value); + /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and + * V_TOTAL_MIN are equal to V_TOTAL. + */ + addr = CRTC_REG(mmCRTC_V_TOTAL_MAX); + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->v_total - 1, + CRTC_V_TOTAL_MAX, + CRTC_V_TOTAL_MAX); + dm_write_reg(ctx, addr, value); + + addr = CRTC_REG(mmCRTC_V_TOTAL_MIN); + value = dm_read_reg(ctx, addr); + set_reg_field_value( + value, + timing->v_total - 1, + CRTC_V_TOTAL_MIN, + CRTC_V_TOTAL_MIN); + dm_write_reg(ctx, addr, value); + addr = CRTC_REG(mmCRTC_H_BLANK_START_END); value = dm_read_reg(ctx, addr); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 03b21e9a1156..58a070debd58 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -441,15 +441,28 @@ void dce120_timing_generator_program_blanking( struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); CRTC_REG_UPDATE( - CRTC0_CRTC_H_TOTAL, - CRTC_H_TOTAL, - timing->h_total - 1); + CRTC0_CRTC_H_TOTAL, + CRTC_H_TOTAL, + timing->h_total - 1); CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL, CRTC_V_TOTAL, timing->v_total - 1); + /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and + * V_TOTAL_MIN are equal to V_TOTAL. + */ + CRTC_REG_UPDATE( + CRTC0_CRTC_V_TOTAL_MAX, + CRTC_V_TOTAL_MAX, + timing->v_total - 1); + + CRTC_REG_UPDATE( + CRTC0_CRTC_V_TOTAL_MIN, + CRTC_V_TOTAL_MIN, + timing->v_total - 1); + tmp1 = timing->h_total - (h_sync_start + timing->h_border_left); tmp2 = tmp1 + timing->h_addressable + diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 5927478b9044..e1899f5fb083 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -177,6 +177,14 @@ static void tgn10_program_timing( REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, v_total); + /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and + * OTG_V_TOTAL_MIN are equal to V_TOTAL. + */ + REG_SET(OTG_V_TOTAL_MAX, 0, + OTG_V_TOTAL_MAX, v_total); + REG_SET(OTG_V_TOTAL_MIN, 0, + OTG_V_TOTAL_MIN, v_total); + /* v_sync_start = 0, v_sync_end = v_sync_width */ v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor; -- cgit v1.2.3-59-g8ed1b From 87449a90c2545eaed5757153770346563378463b Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Thu, 6 Jul 2017 14:27:49 -0400 Subject: drm/amd/display: Fix MPO visual confirm 1. Need to blend non-active area to show visual confirm borders 2. Set number of Visual Confirm lines based on pipe instance 3. Set Different colors representing surface format of bottom most plan Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 6 --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 16 ++++---- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 8 ++-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +++- .../drm/amd/display/dc/dce110/dce110_transform_v.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 45 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 ++- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 13 ++++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 1 + 10 files changed, 77 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 6cd1e93b5084..7b1f2493cbc9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -59,12 +59,6 @@ void color_space_to_black_color( enum dc_color_space colorspace, struct tg_color *black_color) { - if (dc->public.debug.surface_visual_confirm) { - *black_color = - black_color_format[BLACK_COLOR_FORMAT_DEBUG]; - return; - } - switch (colorspace) { case COLOR_SPACE_YCBCR601: case COLOR_SPACE_YCBCR709: diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ddf032214dc3..5a5ed37474bf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -399,11 +399,11 @@ static enum pixel_format convert_pixel_format_to_dalsurface( break; case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - dal_pixel_format = PIXEL_FORMAT_420BPP12; + dal_pixel_format = PIXEL_FORMAT_420BPP8; break; case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - dal_pixel_format = PIXEL_FORMAT_420BPP15; + dal_pixel_format = PIXEL_FORMAT_420BPP10; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: default: @@ -433,8 +433,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; - int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 - || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; + int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 + || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; bool pri_split = pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && @@ -637,8 +637,8 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz; pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert; - if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12 - || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) { + if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8 + || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) { pipe_ctx->scl_data.ratios.horz_c.value /= 2; pipe_ctx->scl_data.ratios.vert_c.value /= 2; } @@ -648,8 +648,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r { struct scaler_data *data = &pipe_ctx->scl_data; struct rect src = pipe_ctx->surface->public.src_rect; - int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 - || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; + int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 + || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 94fb93066784..05f030ee8cf0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -214,15 +214,15 @@ enum pixel_format { PIXEL_FORMAT_ARGB2101010_XRBIAS, PIXEL_FORMAT_FP16, /*video*/ - PIXEL_FORMAT_420BPP12, - PIXEL_FORMAT_420BPP15, + PIXEL_FORMAT_420BPP8, + PIXEL_FORMAT_420BPP10, /*end of pixel format definition*/ PIXEL_FORMAT_INVALID, PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, - PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12, - PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP15, + PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, + PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, PIXEL_FORMAT_UNKNOWN }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 8778af76f4e0..d3c84dc36b80 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -916,11 +916,15 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, /* set boarder color to blue */ color->color_b_cb = color_value; break; - case PIXEL_FORMAT_420BPP12: - case PIXEL_FORMAT_420BPP15: + case PIXEL_FORMAT_420BPP8: /* set boarder color to green */ color->color_g_y = color_value; break; + case PIXEL_FORMAT_420BPP10: + /* set boarder color to yellow */ + color->color_g_y = color_value; + color->color_r_cr = color_value; + break; case PIXEL_FORMAT_FP16: /* set boarder color to white */ color->color_r_cr = color_value; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index 28963996693c..8548248d4b19 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -59,7 +59,7 @@ static void calculate_viewport( chroma_viewport->height = luma_viewport->height; chroma_viewport->width = luma_viewport->width; - if (scl_data->format == PIXEL_FORMAT_420BPP12) { + if (scl_data->format == PIXEL_FORMAT_420BPP8) { luma_viewport->height += luma_viewport->height % 2; luma_viewport->width += luma_viewport->width % 2; /*for 420 video chroma is 1/4 the area of luma, scaled @@ -184,7 +184,7 @@ static bool setup_scaling_configuration( set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C); set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C); is_scaling_needed = true; - } else if (data->format != PIXEL_FORMAT_420BPP12) { + } else if (data->format != PIXEL_FORMAT_420BPP8) { set_reg_field_value( value, get_reg_field_value(value, SCLV_MODE, SCL_MODE), diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fb326316b08b..5e275239341d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1390,6 +1390,42 @@ static bool is_rgb_cspace(enum dc_color_space output_color_space) } } +static void dcn10_get_surface_visual_confirm_color( + const struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + + switch (pipe_ctx->scl_data.format) { + case PIXEL_FORMAT_ARGB8888: + /* set boarder color to red */ + color->color_r_cr = color_value; + break; + + case PIXEL_FORMAT_ARGB2101010: + /* set boarder color to blue */ + color->color_b_cb = color_value; + break; + case PIXEL_FORMAT_420BPP8: + /* set boarder color to green */ + color->color_g_y = color_value; + break; + case PIXEL_FORMAT_420BPP10: + /* set boarder color to yellow */ + color->color_g_y = color_value; + color->color_r_cr = color_value; + break; + case PIXEL_FORMAT_FP16: + /* set boarder color to white */ + color->color_r_cr = color_value; + color->color_b_cb = color_value; + color->color_g_y = color_value; + break; + default: + break; + } +} + static void update_dchubp_dpp( struct core_dc *dc, struct pipe_ctx *pipe_ctx, @@ -1462,8 +1498,13 @@ static void update_dchubp_dpp( && per_pixel_alpha; pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); - color_space_to_black_color( - dc, pipe_ctx->stream->public.output_color_space, &black_color); + if (dc->public.debug.surface_visual_confirm) { + dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color); + } else { + color_space_to_black_color( + dc, pipe_ctx->stream->public.output_color_space, + &black_color); + } pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color); pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 7af04bce3599..1c9d5e96ab55 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -25,6 +25,7 @@ #include "reg_helper.h" #include "dcn10_mpc.h" +#include "dc.h" #define REG(reg)\ mpcc10->mpcc_regs->reg @@ -85,6 +86,8 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; int mpcc_mode = cfg->bot_mpcc_id != 0xf ? MODE_BLEND : MODE_TOP_ONLY; + bool blend_active_only = cfg->top_of_tree && + !mpcc->ctx->dc->debug.surface_visual_confirm; REG_SET(MPCC_OPP_ID, 0, MPCC_OPP_ID, cfg->opp_id); @@ -99,7 +102,7 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) MPCC_MODE, mpcc_mode, MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha, - MPCC_BLND_ACTIVE_OVERLAP_ONLY, cfg->top_of_tree); + MPCC_BLND_ACTIVE_OVERLAP_ONLY, blend_active_only); if (cfg->top_of_tree) { if (cfg->opp_id != 0xf) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 66b5d3027336..75ad37e81738 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -465,7 +465,7 @@ static struct transform *dcn10_transform_create( if (!transform) return NULL; - if (dcn10_transform_construct(transform, ctx, + if (dcn10_transform_construct(transform, ctx, inst, &tf_regs[inst], &tf_shift, &tf_mask)) return &transform->base; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c index 92322b75d868..398af229f2a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c @@ -171,8 +171,8 @@ static enum dscl_mode_sel get_dscl_mode( && data->format <= PIXEL_FORMAT_VIDEO_END) ycbcr = true; - if (data->format == PIXEL_FORMAT_420BPP12 || - data->format == PIXEL_FORMAT_420BPP15) + if (data->format == PIXEL_FORMAT_420BPP8 || + data->format == PIXEL_FORMAT_420BPP10) format420 = true; if (data->ratios.horz.value == one @@ -579,8 +579,8 @@ static enum lb_memory_config find_lb_memory_config(const struct scaler_data *scl && is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) return LB_MEMORY_CONFIG_2; - if (scl_data->format == PIXEL_FORMAT_420BPP12 - || scl_data->format == PIXEL_FORMAT_420BPP15) { + if (scl_data->format == PIXEL_FORMAT_420BPP8 + || scl_data->format == PIXEL_FORMAT_420BPP10) { calc_lb_num_partitions( scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c); @@ -675,7 +675,8 @@ static void transform_set_recout( RECOUT_WIDTH, recout->width, /* Number of RECOUT vertical lines */ RECOUT_HEIGHT, recout->height - - xfm->base.ctx->dc->debug.surface_visual_confirm * 2); + - xfm->base.ctx->dc->debug.surface_visual_confirm * 4 * + (xfm->base.inst + 1)); } static void transform_set_manual_ratio_init( @@ -1038,12 +1039,14 @@ static struct transform_funcs dcn10_transform_funcs = { bool dcn10_transform_construct( struct dcn10_transform *xfm, struct dc_context *ctx, + uint32_t inst, const struct dcn_transform_registers *tf_regs, const struct dcn_transform_shift *tf_shift, const struct dcn_transform_mask *tf_mask) { xfm->base.ctx = ctx; + xfm->base.inst = inst; xfm->base.funcs = &dcn10_transform_funcs; xfm->tf_regs = tf_regs; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h index cd312bd7055b..880a554886b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h @@ -413,6 +413,7 @@ struct dcn10_transform { bool dcn10_transform_construct(struct dcn10_transform *xfm110, struct dc_context *ctx, + uint32_t inst, const struct dcn_transform_registers *tf_regs, const struct dcn_transform_shift *tf_shift, const struct dcn_transform_mask *tf_mask); -- cgit v1.2.3-59-g8ed1b From 7b0c470fcb44b7dbe63db5b5fb52b6123ebe335f Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Mon, 10 Jul 2017 14:04:21 -0400 Subject: drm/amd/display: Flattening to dc_transfer_func Flattening dc transfer functions in the following manner: transfer_func > core_transfer_func > dc_transfer_func References to deleted structs are updated as needed. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 19 ++++--------------- drivers/gpu/drm/amd/display/dc/dc.h | 10 ++++++---- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++++----- .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++++----- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 -------- 5 files changed, 20 insertions(+), 37 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index aa6ac9596235..d44ddfb85748 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -45,18 +45,11 @@ struct gamma { int ref_count; }; -struct transfer_func { - struct core_transfer_func protected; - int ref_count; -}; - #define DC_SURFACE_TO_SURFACE(dc_surface) container_of(dc_surface, struct surface, protected.public) #define CORE_SURFACE_TO_SURFACE(core_surface) container_of(core_surface, struct surface, protected) #define DC_GAMMA_TO_GAMMA(dc_gamma) \ container_of(dc_gamma, struct gamma, protected.public) -#define DC_TRANSFER_FUNC_TO_TRANSFER_FUNC(dc_tf) \ - container_of(dc_tf, struct transfer_func, protected.public) #define CORE_GAMMA_TO_GAMMA(core_gamma) \ container_of(core_gamma, struct gamma, protected) @@ -208,18 +201,14 @@ alloc_fail: return NULL; } -void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf) +void dc_transfer_func_retain(struct dc_transfer_func *tf) { - struct transfer_func *tf = DC_TRANSFER_FUNC_TO_TRANSFER_FUNC(dc_tf); - ASSERT(tf->ref_count > 0); ++tf->ref_count; } -void dc_transfer_func_release(const struct dc_transfer_func *dc_tf) +void dc_transfer_func_release(struct dc_transfer_func *tf) { - struct transfer_func *tf = DC_TRANSFER_FUNC_TO_TRANSFER_FUNC(dc_tf); - ASSERT(tf->ref_count > 0); --tf->ref_count; @@ -229,14 +218,14 @@ void dc_transfer_func_release(const struct dc_transfer_func *dc_tf) struct dc_transfer_func *dc_create_transfer_func() { - struct transfer_func *tf = dm_alloc(sizeof(*tf)); + struct dc_transfer_func *tf = dm_alloc(sizeof(*tf)); if (tf == NULL) goto alloc_fail; ++tf->ref_count; - return &tf->protected.public; + return tf; alloc_fail: return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 42c1aa8d68af..1fad03cdeb9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -293,6 +293,8 @@ struct dc_transfer_func { struct dc_transfer_func_distributed_points tf_pts; enum dc_transfer_func_type type; enum dc_transfer_func_predefined tf; + struct dc_context *ctx; + int ref_count; }; struct dc_surface { @@ -310,7 +312,7 @@ struct dc_surface { struct dc_hdr_static_metadata hdr_static_ctx; const struct dc_gamma *gamma_correction; - const struct dc_transfer_func *in_transfer_func; + struct dc_transfer_func *in_transfer_func; enum dc_color_space color_space; enum surface_pixel_format format; @@ -384,8 +386,8 @@ void dc_gamma_retain(const struct dc_gamma *dc_gamma); void dc_gamma_release(const struct dc_gamma **dc_gamma); struct dc_gamma *dc_create_gamma(void); -void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf); -void dc_transfer_func_release(const struct dc_transfer_func *dc_tf); +void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); +void dc_transfer_func_release(struct dc_transfer_func *dc_tf); struct dc_transfer_func *dc_create_transfer_func(void); /* @@ -465,7 +467,7 @@ struct dc_stream { struct freesync_context freesync_ctx; - const struct dc_transfer_func *out_transfer_func; + struct dc_transfer_func *out_transfer_func; struct colorspace_transform gamut_remap_matrix; struct csc_transform csc_color_matrix; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d3c84dc36b80..5d64611eb6a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -242,7 +242,7 @@ static bool dce110_set_input_transfer_func( const struct core_surface *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; - const struct core_transfer_func *tf = NULL; + const struct dc_transfer_func *tf = NULL; struct ipp_prescale_params prescale_params = { 0 }; bool result = true; @@ -250,7 +250,7 @@ static bool dce110_set_input_transfer_func( return false; if (surface->public.in_transfer_func) - tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); + tf = surface->public.in_transfer_func; build_prescale_params(&prescale_params, surface); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); @@ -262,8 +262,8 @@ static bool dce110_set_input_transfer_func( /* Default case if no input transfer function specified */ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); - } else if (tf->public.type == TF_TYPE_PREDEFINED) { - switch (tf->public.tf) { + } else if (tf->type == TF_TYPE_PREDEFINED) { + switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); @@ -283,7 +283,7 @@ static bool dce110_set_input_transfer_func( result = false; break; } - } else if (tf->public.type == TF_TYPE_BYPASS) { + } else if (tf->type == TF_TYPE_BYPASS) { ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); } else { /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 4c39bf052d08..ac0d62c10da2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -602,14 +602,14 @@ static bool dcn10_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct core_surface *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; - const struct core_transfer_func *tf = NULL; + const struct dc_transfer_func *tf = NULL; bool result = true; if (ipp == NULL) return false; if (surface->public.in_transfer_func) - tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); + tf = surface->public.in_transfer_func; if (surface->public.gamma_correction && dce_use_lut(surface)) ipp->funcs->ipp_program_input_lut(ipp, @@ -617,8 +617,8 @@ static bool dcn10_set_input_transfer_func( if (tf == NULL) ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); - else if (tf->public.type == TF_TYPE_PREDEFINED) { - switch (tf->public.tf) { + else if (tf->type == TF_TYPE_PREDEFINED) { + switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); @@ -638,7 +638,7 @@ static bool dcn10_set_input_transfer_func( result = false; break; } - } else if (tf->public.type == TF_TYPE_BYPASS) { + } else if (tf->type == TF_TYPE_BYPASS) { ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); } else { /*TF_TYPE_DISTRIBUTED_POINTS*/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 030841889803..3e9a0ccca3b4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -49,9 +49,6 @@ struct core_stream; #define DC_GAMMA_TO_CORE(dc_gamma) \ container_of(dc_gamma, struct core_gamma, public) -#define DC_TRANSFER_FUNC_TO_CORE(dc_transfer_func) \ - container_of(dc_transfer_func, struct core_transfer_func, public) - struct core_surface { struct dc_surface public; struct dc_surface_status status; @@ -63,11 +60,6 @@ struct core_gamma { struct dc_context *ctx; }; -struct core_transfer_func { - struct dc_transfer_func public; - struct dc_context *ctx; -}; - void enable_surface_flip_reporting(struct dc_surface *dc_surface, uint32_t controller_id); -- cgit v1.2.3-59-g8ed1b From 15e173352eeae76286e0d018f9eec6b55726caa4 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 17 Jul 2017 16:04:02 -0400 Subject: drm/amd/display: fix aviInfoFrame bar Info and add set_avMute Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 ++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 37 ++++++++++++++++++---- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 13 +++++++- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++++++-- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 1 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 3 ++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 ++ .../display/dc/virtual/virtual_stream_encoder.c | 4 +++ 10 files changed, 77 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fed38fbab452..036d22f878b8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1911,3 +1911,13 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal); } +void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) +{ + struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + + if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) + return; + + core_dc->hwss.set_avmute(pipe_ctx, enable); +} + diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9d0128e95767..63056e8c6d78 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1607,6 +1607,8 @@ static void set_avi_info_frame( uint8_t *check_sum = NULL; uint8_t byte_index = 0; union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; + unsigned int vic = pipe_ctx->stream->public.timing.vic; + enum dc_timing_3d_format format; color_space = pipe_ctx->stream->public.output_color_space; if (color_space == COLOR_SPACE_UNKNOWN) @@ -1661,8 +1663,7 @@ static void set_avi_info_frame( /* C0, C1 : Colorimetry */ if (color_space == COLOR_SPACE_YCBCR709 || - color_space == COLOR_SPACE_YCBCR709_LIMITED || - color_space == COLOR_SPACE_2020_YCBCR) + color_space == COLOR_SPACE_YCBCR709_LIMITED) hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709; else if (color_space == COLOR_SPACE_YCBCR601 || color_space == COLOR_SPACE_YCBCR601_LIMITED) @@ -1722,9 +1723,29 @@ static void set_avi_info_frame( hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; } - - hdmi_info->bits.VIC0_VIC7 = - stream->public.timing.vic; + ///VIC + format = stream->public.timing.timing_3d_format; + /*todo, add 3DStereo support*/ + if (format != TIMING_3D_FORMAT_NONE) { + // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled + switch (pipe_ctx->stream->public.timing.hdmi_vic) { + case 1: + vic = 95; + break; + case 2: + vic = 94; + break; + case 3: + vic = 93; + break; + case 4: + vic = 98; + break; + default: + break; + } + } + hdmi_info->bits.VIC0_VIC7 = vic; /* pixel repetition * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel @@ -1737,7 +1758,7 @@ static void set_avi_info_frame( * barLeft: Pixel Number of End of Left Bar. * barRight: Pixel Number of Start of Right Bar. */ hdmi_info->bits.bar_top = stream->public.timing.v_border_top; - hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top + hdmi_info->bits.bar_bottom = (stream->public.timing.v_total - stream->public.timing.v_border_bottom + 1); hdmi_info->bits.bar_left = stream->public.timing.h_border_left; hdmi_info->bits.bar_right = (stream->public.timing.h_total @@ -1776,6 +1797,10 @@ static void set_vendor_info_packet( uint8_t checksum = 0; uint32_t i = 0; enum dc_timing_3d_format format; + // Can be different depending on packet content /*todo*/ + // unsigned int length = pPathMode->dolbyVision ? 24 : 5; + + info_packet->valid = false; format = stream->public.timing.timing_3d_format; if (stream->public.view_format == VIEW_3D_FORMAT_NONE) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index daab81bd1773..532c6e638943 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -1003,6 +1003,16 @@ static void dce110_stream_encoder_dp_unblank( REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); } +static void dce110_stream_encoder_set_avmute( + struct stream_encoder *enc, + bool enable) +{ + struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); + unsigned int value = enable ? 1 : 0; + + REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); +} + #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 @@ -1582,7 +1592,6 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = { dce110_stream_encoder_dp_blank, .dp_unblank = dce110_stream_encoder_dp_unblank, - .audio_mute_control = dce110_se_audio_mute_control, .dp_audio_setup = dce110_se_dp_audio_setup, @@ -1592,6 +1601,8 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = { .hdmi_audio_setup = dce110_se_hdmi_audio_setup, .hdmi_audio_disable = dce110_se_hdmi_audio_disable, .setup_stereo_sync = setup_stereo_sync, + .set_avmute = dce110_stream_encoder_set_avmute, + }; bool dce110_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5d64611eb6a6..b691ef956d45 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -801,6 +801,13 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); } + +void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) +{ + if (pipe_ctx != NULL && pipe_ctx->stream_enc != NULL) + pipe_ctx->stream_enc->funcs->set_avmute(pipe_ctx->stream_enc, enable); +} + static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) { switch (crtc_id) { @@ -1095,10 +1102,11 @@ static enum dc_status apply_single_controller_ctx_to_hw( (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? true : false); + resource_build_info_frame(pipe_ctx); + if (!pipe_ctx_old->stream) { core_link_enable_stream(pipe_ctx); - resource_build_info_frame(pipe_ctx); dce110_update_info_frame(pipe_ctx); if (dc_is_dp_signal(pipe_ctx->stream->signal)) dce110_unblank_stream(pipe_ctx, @@ -2600,7 +2608,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_static_screen_control = set_static_screen_control, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, - .setup_stereo = NULL + .setup_stereo = NULL, + .set_avmute = dce110_set_avmute, }; bool dce110_hw_sequencer_construct(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 52462c17b2e9..89782ca1917f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -54,6 +54,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); +void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); void dce110_enable_accelerated_mode(struct core_dc *dc); void dce110_power_down(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index cadc940e7c0e..8284837898d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1867,7 +1867,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .set_drr = set_drr, .get_position = get_position, .set_static_screen_control = set_static_screen_control, - .setup_stereo = dcn10_setup_stereo + .setup_stereo = dcn10_setup_stereo, + .set_avmute = dce110_set_avmute, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d216522a9989..d75368030917 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -179,6 +179,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx); void core_link_disable_stream(struct pipe_ctx *pipe_ctx); +void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); /********** DAL Core*********************/ #include "display_clock.h" #include "transform.h" diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 9fb27bd360ac..6ff90a0fef24 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -123,6 +123,9 @@ struct stream_encoder_funcs { struct stream_encoder *enc, int tg_inst, bool enable); + + void (*set_avmute)( + struct stream_encoder *enc, bool enable); }; #endif /* STREAM_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 97dbd259f66c..d94e8e446ce5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -152,6 +152,8 @@ struct hw_sequencer_funcs { void (*setup_stereo)( struct pipe_ctx *pipe_ctx, struct core_dc *dc); + + void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 8de21d9a8079..7fe6085e6e37 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -53,6 +53,9 @@ static void virtual_stream_encoder_update_hdmi_info_packets( static void virtual_stream_encoder_stop_hdmi_info_packets( struct stream_encoder *enc) {} +static void virtual_stream_encoder_set_avmute( + struct stream_encoder *enc, + bool enable) {} static void virtual_stream_encoder_update_dp_info_packets( struct stream_encoder *enc, const struct encoder_info_frame *info_frame) {} @@ -94,6 +97,7 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { virtual_stream_encoder_dp_unblank, .audio_mute_control = virtual_audio_mute_control, + .set_avmute = virtual_stream_encoder_set_avmute, }; bool virtual_stream_encoder_construct( -- cgit v1.2.3-59-g8ed1b From 72f0281d34b464121f9f6b75a2d7a2502055ec79 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Wed, 19 Jul 2017 16:59:14 -0400 Subject: drm/amd/display: fix index and union overwrite in compressor Fixing 2 bugs in compressor: - array out of bounds due to incorrect index - compressor options always 0 due to union overwrite Signed-off-by: Roman Li Reviewed-by: Bhawanpreet Lakha Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 1e59f4e31a6a..9759d8e790a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -198,7 +198,7 @@ void dce110_compressor_enable_fbc( /* Keep track of enum controller_id FBC is attached to */ compressor->is_enabled = true; compressor->attached_inst = params->inst; - cp110->offsets = reg_offsets[params->inst - 1]; + cp110->offsets = reg_offsets[params->inst]; /*Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); @@ -469,6 +469,7 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, struct dc_context *ctx) { + compressor->base.options.raw = 0; compressor->base.options.bits.FBC_SUPPORT = true; /* for dce 11 always use one dram channel for lpt */ @@ -490,7 +491,6 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, compressor->base.allocated_size = 0; compressor->base.preferred_requested_size = 0; compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; compressor->base.banks_num = 0; compressor->base.raw_size = 0; compressor->base.channel_interleave_size = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c index 22a5aba073ca..75af2125344b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c @@ -404,7 +404,7 @@ void dce112_compressor_enable_fbc( /* Keep track of enum controller_id FBC is attached to */ compressor->is_enabled = true; compressor->attached_inst = params->inst; - cp110->offsets = reg_offsets[params->inst - 1]; + cp110->offsets = reg_offsets[params->inst]; /*Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); @@ -797,6 +797,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, struct dc_bios *bp = ctx->dc_bios; struct embedded_panel_info panel_info; + compressor->base.options.raw = 0; compressor->base.options.bits.FBC_SUPPORT = true; compressor->base.options.bits.LPT_SUPPORT = true; /* For DCE 11 always use one DRAM channel for LPT */ @@ -817,7 +818,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, compressor->base.allocated_size = 0; compressor->base.preferred_requested_size = 0; compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; compressor->base.banks_num = 0; compressor->base.raw_size = 0; compressor->base.channel_interleave_size = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c index eeedb7c4fe53..77626d7624c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c @@ -407,7 +407,7 @@ void dce80_compressor_enable_fbc( /* Keep track of enum controller_id FBC is attached to */ compressor->is_enabled = true; compressor->attached_inst = params->inst; - cp80->offsets = reg_offsets[params->inst - 1]; + cp80->offsets = reg_offsets[params->inst]; /*Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); @@ -777,6 +777,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, struct dc_bios *bp = ctx->dc_bios; struct embedded_panel_info panel_info; + compressor->base.options.raw = 0; compressor->base.options.bits.FBC_SUPPORT = true; compressor->base.options.bits.LPT_SUPPORT = true; /* For DCE 11 always use one DRAM channel for LPT */ @@ -797,7 +798,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, compressor->base.allocated_size = 0; compressor->base.preferred_requested_size = 0; compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; compressor->base.banks_num = 0; compressor->base.raw_size = 0; compressor->base.channel_interleave_size = 0; -- cgit v1.2.3-59-g8ed1b From 516666318fe1f427ab81e2ebe45d116a9667c3b5 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 21 Jul 2017 17:35:16 -0400 Subject: drm/amd/display: support for updated register headers on DCN Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12 +++++++- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++++++-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 17 +++++++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 19 +++++++++--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 15 ++++++++- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 36 ++++++++++++---------- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 +++ 8 files changed, 88 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 0479554bc231..80ee1ac32fee 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -227,6 +227,15 @@ struct dce_hwseq_registers { uint32_t DISPCLK_FREQ_CHANGE_CNTL; uint32_t RBBMIF_TIMEOUT_DIS; uint32_t RBBMIF_TIMEOUT_DIS_2; + uint32_t DENTIST_DISPCLK_CNTL; + uint32_t DCHUBBUB_CRC_CTRL; + uint32_t DPP_TOP0_DPP_CRC_CTRL; + uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; + uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; + uint32_t MPC_CRC_CTRL; + uint32_t MPC_CRC_RESULT_GB; + uint32_t MPC_CRC_RESULT_C; + uint32_t MPC_CRC_RESULT_AR; #endif }; /* set field name */ @@ -388,7 +397,8 @@ struct dce_hwseq_registers { type DOMAIN6_PGFSM_PWR_STATUS; \ type DOMAIN7_PGFSM_PWR_STATUS; \ type DCFCLK_GATE_DIS; \ - type DCHUBBUB_GLOBAL_TIMER_REFDIV; + type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ + type DENTIST_DPPCLK_WDIVIDER; #endif struct dce_hwseq_shift { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index b691ef956d45..baafe6609d24 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -256,7 +256,7 @@ static bool dce110_set_input_transfer_func( ipp->funcs->ipp_program_prescale(ipp, &prescale_params); if (surface->public.gamma_correction && dce_use_lut(surface)) - ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); + ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); if (tf == NULL) { /* Default case if no input transfer function specified */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 6db78d9f8e3b..ce7da8864507 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -550,7 +550,9 @@ static void reset_front_end( if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); - REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000); + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], + VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000); mpcc->funcs->wait_for_idle(mpcc); @@ -1295,6 +1297,7 @@ static void dcn10_power_on_fe( /* make sure OPP_PIPE_CLOCK_EN = 1 */ REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst], OPP_PIPE_CLOCK_EN, 1); + /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ if (dc_surface) { dm_logger_write(dc->ctx->logger, LOG_DC, @@ -1984,9 +1987,16 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) static void dcn10_log_hw_state(struct core_dc *dc) { struct dc_context *dc_ctx = dc->ctx; + struct dce_hwseq *hws = dc->hwseq; DTN_INFO("%s: Hello World", __func__); + if (REG(MPC_CRC_RESULT_GB)) + DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", + REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); + if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) + DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", + REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); /* todo: add meaningful register reads and print out HW state * */ @@ -2065,7 +2075,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .set_static_screen_control = set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dce110_set_avmute, - .log_hw_state = dcn10_log_hw_state, + .log_hw_state = dcn10_log_hw_state }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 53dd9a9593f0..ee12f671d8ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -472,11 +472,18 @@ static bool ippn10_cursor_program_control( bool pixel_data_invert, enum dc_cursor_color_format color_format) { - REG_SET_2(CURSOR_SETTINS, 0, - /* no shift of the cursor HDL schedule */ - CURSOR0_DST_Y_OFFSET, 0, - /* used to shift the cursor chunk request deadline */ - CURSOR0_CHUNK_HDL_ADJUST, 3); + if (REG(CURSOR_SETTINS)) + REG_SET_2(CURSOR_SETTINS, 0, + /* no shift of the cursor HDL schedule */ + CURSOR0_DST_Y_OFFSET, 0, + /* used to shift the cursor chunk request deadline */ + CURSOR0_CHUNK_HDL_ADJUST, 3); + else + REG_SET_2(CURSOR_SETTINGS, 0, + /* no shift of the cursor HDL schedule */ + CURSOR0_DST_Y_OFFSET, 0, + /* used to shift the cursor chunk request deadline */ + CURSOR0_CHUNK_HDL_ADJUST, 3); REG_UPDATE_2(CURSOR0_CONTROL, CUR0_MODE, color_format, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 8054794dd96d..1f86295d6db6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -460,9 +460,14 @@ static void min10_program_deadline( REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); - REG_SET_2(PREFETCH_SETTINS, 0, - DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, dlg_attr->vratio_prefetch); + if (REG(PREFETCH_SETTINS)) + REG_SET_2(PREFETCH_SETTINS, 0, + DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, + VRATIO_PREFETCH, dlg_attr->vratio_prefetch); + else + REG_SET_2(PREFETCH_SETTINGS, 0, + DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, + VRATIO_PREFETCH, dlg_attr->vratio_prefetch); REG_SET_2(VBLANK_PARAMETERS_0, 0, DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, @@ -498,8 +503,12 @@ static void min10_program_deadline( REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); - REG_SET(PREFETCH_SETTINS_C, 0, - VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); + if (REG(PREFETCH_SETTINS_C)) + REG_SET(PREFETCH_SETTINS_C, 0, + VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); + else + REG_SET(PREFETCH_SETTINGS_C, 0, + VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); REG_SET(VBLANK_PARAMETERS_2, 0, REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index de0b631736bb..d9d66a4afb19 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -123,7 +123,6 @@ SRI(CM_MEM_PWR_CTRL, CM, id), \ SRI(CM_RGAM_LUT_DATA, CM, id) - #define OPP_MASK_SH_LIST_DCN(mask_sh) \ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ @@ -357,6 +356,16 @@ OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh) #define OPP_DCN10_REG_FIELD_LIST(type) \ + type DPG_EN; \ + type DPG_MODE; \ + type DPG_VRES; \ + type DPG_HRES; \ + type DPG_COLOUR0_R_CR; \ + type DPG_COLOUR1_R_CR; \ + type DPG_COLOUR0_B_CB; \ + type DPG_COLOUR1_B_CB; \ + type DPG_COLOUR0_G_Y; \ + type DPG_COLOUR1_G_Y; \ type CM_OCSC_C11; \ type CM_OCSC_C12; \ type CM_OCSC_C13; \ @@ -594,6 +603,10 @@ struct dcn10_opp_mask { }; struct dcn10_opp_registers { + uint32_t DPG_CONTROL; + uint32_t DPG_COLOUR_B_CB; + uint32_t DPG_COLOUR_G_Y; + uint32_t DPG_COLOUR_R_CR; uint32_t CM_OCSC_C11_C12; uint32_t CM_OCSC_C13_C14; uint32_t CM_OCSC_C21_C22; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 12d7f3570cfa..b2e796d87dac 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -345,17 +345,18 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); if (enable) { - REG_UPDATE(OPTC_INPUT_CLOCK_CONTROL, - OPTC_INPUT_CLK_EN, 1); + REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, + OPTC_INPUT_CLK_EN, 1, + OPTC_INPUT_CLK_GATE_DIS, 1); REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, 1, 2000, 500); /* Enable clock */ - REG_UPDATE(OTG_CLOCK_CONTROL, - OTG_CLOCK_EN, 1); - + REG_UPDATE_2(OTG_CLOCK_CONTROL, + OTG_CLOCK_EN, 1, + OTG_CLOCK_GATE_DIS, 1); REG_WAIT(OTG_CLOCK_CONTROL, OTG_CLOCK_ON, 1, 2000, 500); @@ -364,17 +365,19 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) OTG_CLOCK_GATE_DIS, 0, OTG_CLOCK_EN, 0); - REG_WAIT(OTG_CLOCK_CONTROL, - OTG_CLOCK_ON, 0, - 2000, 500); + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_CLOCK_ON, 0, + 2000, 500); REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, 0, OPTC_INPUT_CLK_EN, 0); - REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, - OPTC_INPUT_CLK_ON, 0, - 2000, 500); + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, + OPTC_INPUT_CLK_ON, 0, + 2000, 500); } } @@ -574,9 +577,10 @@ static void tgn10_lock(struct timing_generator *tg) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); - REG_WAIT(OTG_MASTER_UPDATE_LOCK, - UPDATE_LOCK_STATUS, 1, - 1, 100); + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_MASTER_UPDATE_LOCK, + UPDATE_LOCK_STATUS, 1, + 1, 100); } static void tgn10_unlock(struct timing_generator *tg) @@ -587,9 +591,9 @@ static void tgn10_unlock(struct timing_generator *tg) OTG_MASTER_UPDATE_LOCK, 0); /* why are we waiting here? */ - /*REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, + REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, 0, - 20000, 200000);*/ + 20000, 200000); } static void tgn10_get_position(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index a101f4b5e0c7..4b0c28eef352 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -324,6 +324,10 @@ struct opp_funcs { struct output_pixel_processor *opp, bool enable, bool rightEyePolarity); + + void (*opp_set_test_pattern)( + struct output_pixel_processor *opp, + bool enable); }; #endif -- cgit v1.2.3-59-g8ed1b From 0a87425a37b4c1f06d75949ea39e60455a2b0a4f Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Wed, 12 Jul 2017 22:35:52 -0400 Subject: drm/amd/display: move VGA to HWSS from TG Signed-off-by: Tony Cheng Reviewed-by: Zeyu Fan Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 11 ++++++- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++++- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 38 ---------------------- 4 files changed, 23 insertions(+), 41 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 80ee1ac32fee..7feb1ca9b8c0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -170,7 +170,12 @@ SR(DIO_MEM_PWR_CTRL), \ SR(DCCG_GATE_DISABLE_CNTL), \ SR(DCCG_GATE_DISABLE_CNTL2), \ - SR(DCFCLK_CNTL) + SR(DCFCLK_CNTL),\ + SR(DCFCLK_CNTL), \ + SR(D1VGA_CONTROL), \ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL) #endif #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -236,6 +241,10 @@ struct dce_hwseq_registers { uint32_t MPC_CRC_RESULT_GB; uint32_t MPC_CRC_RESULT_C; uint32_t MPC_CRC_RESULT_AR; + uint32_t D1VGA_CONTROL; + uint32_t D2VGA_CONTROL; + uint32_t D3VGA_CONTROL; + uint32_t D4VGA_CONTROL; #endif }; /* set field name */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index baafe6609d24..72e099953a05 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1198,7 +1198,8 @@ static void disable_vga_and_power_gate_all_controllers( for (i = 0; i < dc->res_pool->pipe_count; i++) { tg = dc->res_pool->timing_generators[i]; - tg->funcs->disable_vga(tg); + if (tg->funcs->disable_vga) + tg->funcs->disable_vga(tg); /* Enable CLOCK gating for each pipe BEFORE controller * powergating. */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ce7da8864507..64f2fd0d539e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -163,6 +163,15 @@ static void enable_power_gating_plane( REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); } +static void disable_vga( + struct dce_hwseq *hws) +{ + REG_WRITE(D1VGA_CONTROL, 0); + REG_WRITE(D2VGA_CONTROL, 0); + REG_WRITE(D3VGA_CONTROL, 0); + REG_WRITE(D4VGA_CONTROL, 0); +} + static void dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, @@ -312,6 +321,8 @@ static void dcn10_init_hw(struct core_dc *dc) bios_golden_init(dc); + disable_vga(dc->hwseq); + for (i = 0; i < dc->link_count; i++) { /* Power up AND update implementation according to the * required signal (which may be different from the @@ -335,7 +346,6 @@ static void dcn10_init_hw(struct core_dc *dc) mpcc_cfg.top_of_tree = true; mpcc->funcs->set(mpcc, &mpcc_cfg); - tg->funcs->disable_vga(tg); /* Blank controller using driver code instead of * command table. */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index b2e796d87dac..0ef5d8f0625c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -447,43 +447,6 @@ static void tgn10_program_blank_color( OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); } -/** - * dcn10_dcn10_timing_generator_disable_vga - * Turn OFF VGA Mode and Timing - DxVGA_CONTROL - * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors; - */ -/* TODO FPGA FPGA setup is done by Diag which does not enable VGA mode. - * VGA is disable by ASIC default. This function is not needed for - * FPGA story. - * usage: - * init_hw within dc.c - * disable_vga_and_power_gate_all_controllers within dce110_hw_sequencer.c - * We may move init_hw into DC specific so that we can remove - * .disable_vga from upper layer stack - */ -static void tgn10_disable_vga( - struct timing_generator *tg) -{ - struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); - - switch (tgn10->base.inst) { - case 0: - REG_WRITE(D1VGA_CONTROL, 0); - break; - case 1: - REG_WRITE(D2VGA_CONTROL, 0); - break; - case 2: - REG_WRITE(D2VGA_CONTROL, 0); - break; - case 3: - REG_WRITE(D4VGA_CONTROL, 0); - break; - default: - break; - } -} - static bool tgn10_validate_timing( struct timing_generator *tg, const struct dc_crtc_timing *timing) @@ -1144,7 +1107,6 @@ static struct timing_generator_funcs dcn10_tg_funcs = { .set_blank = tgn10_set_blank, .is_blanked = tgn10_is_blanked, .set_blank_color = tgn10_program_blank_color, - .disable_vga = tgn10_disable_vga, .did_triggered_reset_occur = tgn10_did_triggered_reset_occur, .enable_reset_trigger = tgn10_enable_reset_trigger, .disable_reset_trigger = tgn10_disable_reset_trigger, -- cgit v1.2.3-59-g8ed1b From b6762f0c16a43c3d2867fb652f8efa429f70c83d Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Mon, 24 Jul 2017 11:18:29 -0400 Subject: drm/amd/display: add missing func for dce11o to avoid crash Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 72e099953a05..6ab9712ed808 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2582,6 +2582,11 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) dc->res_pool->transforms[fe_idx]); } +static void dce110_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) +{ + /* do nothing*/ +} + static const struct hw_sequencer_funcs dce110_funcs = { .program_gamut_remap = program_gamut_remap, .init_hw = init_hw, @@ -2611,6 +2616,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, .setup_stereo = NULL, .set_avmute = dce110_set_avmute, + .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect }; bool dce110_hw_sequencer_construct(struct core_dc *dc) -- cgit v1.2.3-59-g8ed1b From 08b1688620426ad3e09fc7a98aabc28dda30cde6 Mon Sep 17 00:00:00 2001 From: Zeyu Fan Date: Sun, 23 Jul 2017 18:30:15 -0400 Subject: drm/amd/display: Move DCHUBBUB block from MemInput to HW sequencer. Signed-off-by: Zeyu Fan Reviewed-by: Zeyu Fan Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 122 ++++++++- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 54 +--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1 + .../amd/display/dc/dce120/dce120_hw_sequencer.c | 64 +++++ .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 304 ++++++++++++++++++++- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 303 -------------------- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 76 +----- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 7 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 + 11 files changed, 492 insertions(+), 451 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9ef671735125..e89a2e5c8902 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2042,10 +2042,10 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) return false; } - if (mi->funcs->mem_input_update_dchub) - mi->funcs->mem_input_update_dchub(mi, dh_data); + if (core_dc->hwss.update_dchub) + core_dc->hwss.update_dchub(core_dc->hwseq, dh_data); else - ASSERT(mi->funcs->mem_input_update_dchub); + ASSERT(core_dc->hwss.update_dchub); return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 7feb1ca9b8c0..d62fc526783f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -116,6 +116,15 @@ .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ .BLND_CONTROL[3] = mmBLNDV_CONTROL +#define HWSEQ_DCE120_REG_LIST() \ + HWSEQ_DCE10_REG_LIST(), \ + HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ + HWSEQ_PHYPLL_REG_LIST(CRTC), \ + SR(DCHUB_FB_LOCATION),\ + SR(DCHUB_AGP_BASE),\ + SR(DCHUB_AGP_BOT),\ + SR(DCHUB_AGP_TOP) + #define HWSEQ_DCE112_REG_LIST() \ HWSEQ_DCE10_REG_LIST(), \ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ @@ -146,8 +155,31 @@ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \ SR(REFCLK_CNTL), \ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ + SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ + SR(DCHUBBUB_ARB_SAT_LEVEL),\ + SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ - SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \ SR(DCHUBBUB_TEST_DEBUG_INDEX), \ SR(DCHUBBUB_TEST_DEBUG_DATA), \ SR(DC_IP_REQUEST_CNTL), \ @@ -180,7 +212,13 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #define HWSEQ_DCN1_REG_LIST()\ - HWSEQ_DCN_REG_LIST() + HWSEQ_DCN_REG_LIST(), \ + SR(DCHUBBUB_SDPIF_FB_TOP),\ + SR(DCHUBBUB_SDPIF_FB_BASE),\ + SR(DCHUBBUB_SDPIF_FB_OFFSET),\ + SR(DCHUBBUB_SDPIF_AGP_BASE),\ + SR(DCHUBBUB_SDPIF_AGP_BOT),\ + SR(DCHUBBUB_SDPIF_AGP_TOP) #endif @@ -194,6 +232,11 @@ struct dce_hwseq_registers { uint32_t CRTC_H_BLANK_START_END[6]; uint32_t PIXEL_RATE_CNTL[6]; uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; + /*DCHUB*/ + uint32_t DCHUB_FB_LOCATION; + uint32_t DCHUB_AGP_BASE; + uint32_t DCHUB_AGP_BOT; + uint32_t DCHUB_AGP_TOP; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) uint32_t OTG_GLOBAL_SYNC_STATUS[4]; @@ -202,10 +245,39 @@ struct dce_hwseq_registers { uint32_t DPP_CONTROL[4]; uint32_t OPP_PIPE_CONTROL[4]; uint32_t REFCLK_CNTL; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; + uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; + uint32_t DCHUBBUB_ARB_SAT_LEVEL; + uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; uint32_t DCHUBBUB_TEST_DEBUG_INDEX; uint32_t DCHUBBUB_TEST_DEBUG_DATA; + uint32_t DCHUBBUB_SDPIF_FB_TOP; + uint32_t DCHUBBUB_SDPIF_FB_BASE; + uint32_t DCHUBBUB_SDPIF_FB_OFFSET; + uint32_t DCHUBBUB_SDPIF_AGP_BASE; + uint32_t DCHUBBUB_SDPIF_AGP_BOT; + uint32_t DCHUBBUB_SDPIF_AGP_TOP; uint32_t DC_IP_REQUEST_CNTL; uint32_t DOMAIN0_PG_CONFIG; uint32_t DOMAIN1_PG_CONFIG; @@ -300,11 +372,19 @@ struct dce_hwseq_registers { HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ + SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ + SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ + SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ + SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ + SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) + #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ - HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ + HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ @@ -342,6 +422,12 @@ struct dce_hwseq_registers { HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh) #endif @@ -349,6 +435,12 @@ struct dce_hwseq_registers { #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ + HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ + HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ + HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ + HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ + HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ + HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh) #endif @@ -370,7 +462,6 @@ struct dce_hwseq_registers { type PHYPLL_PIXEL_RATE_SOURCE; \ type PIXEL_RATE_PLL_SOURCE; \ -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #define HWSEQ_DCN_REG_FIELD_LIST(type) \ type VUPDATE_NO_LOCK_EVENT_CLEAR; \ type VUPDATE_NO_LOCK_EVENT_OCCURRED; \ @@ -378,7 +469,25 @@ struct dce_hwseq_registers { type HUBP_CLOCK_ENABLE; \ type DPP_CLOCK_ENABLE; \ type DPPCLK_RATE_CONTROL; \ + type SDPIF_FB_TOP;\ + type SDPIF_FB_BASE;\ + type SDPIF_FB_OFFSET;\ + type SDPIF_AGP_BASE;\ + type SDPIF_AGP_BOT;\ + type SDPIF_AGP_TOP;\ + type FB_TOP;\ + type FB_BASE;\ + type FB_OFFSET;\ + type AGP_BASE;\ + type AGP_BOT;\ + type AGP_TOP;\ type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ + type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ + type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ + type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ + type DCHUBBUB_ARB_SAT_LEVEL;\ + type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ type OPP_PIPE_CLOCK_EN;\ type IP_REQUEST_EN; \ type DOMAIN0_POWER_FORCEON; \ @@ -408,20 +517,15 @@ struct dce_hwseq_registers { type DCFCLK_GATE_DIS; \ type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ type DENTIST_DPPCLK_WDIVIDER; -#endif struct dce_hwseq_shift { HWSEQ_REG_FIELD_LIST(uint8_t) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) HWSEQ_DCN_REG_FIELD_LIST(uint8_t) -#endif }; struct dce_hwseq_mask { HWSEQ_REG_FIELD_LIST(uint32_t) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) HWSEQ_DCN_REG_FIELD_LIST(uint32_t) -#endif }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 157f4e1680e3..627669749740 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -656,57 +656,6 @@ static bool dce_mi_program_surface_flip_and_addr( return true; } -static void dce_mi_update_dchub(struct mem_input *mi, - struct dchub_init_data *dh_data) -{ - struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); - /* TODO: port code from dal2 */ - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - REG_UPDATE_2(DCHUB_FB_LOCATION, - FB_TOP, 0, - FB_BASE, 0x0FFFF); - - REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, 0); - - REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, 0x03FFFF); - - REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - static struct mem_input_funcs dce_mi_funcs = { .mem_input_program_display_marks = dce_mi_program_display_marks, .allocate_mem_input = dce_mi_allocate_dmif, @@ -716,8 +665,7 @@ static struct mem_input_funcs dce_mi_funcs = { .mem_input_program_pte_vm = dce_mi_program_pte_vm, .mem_input_program_surface_config = dce_mi_program_surface_config, - .mem_input_is_flip_pending = dce_mi_is_flip_pending, - .mem_input_update_dchub = dce_mi_update_dchub + .mem_input_is_flip_pending = dce_mi_is_flip_pending }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6ab9712ed808..efba8d7964eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -49,6 +49,7 @@ #include "abm.h" #include "audio.h" #include "dce/dce_hwseq.h" +#include "reg_helper.h" /* include DCE11 register header files */ #include "dce/dce_11_0_d.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index f5ffd8f6ed3b..91301b412aa0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -28,6 +28,7 @@ #include "core_dc.h" #include "core_types.h" #include "dce120_hw_sequencer.h" +#include "dce/dce_hwseq.h" #include "dce110/dce110_hw_sequencer.h" @@ -37,6 +38,15 @@ #include "vega10/soc15ip.h" #include "reg_helper.h" +#define CTX \ + hws->ctx +#define REG(reg)\ + hws->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + struct dce120_hw_seq_reg_offsets { uint32_t crtc; }; @@ -184,6 +194,59 @@ static bool dce120_enable_display_power_gating( return false; } +static void dce120_update_dchub( + struct dce_hwseq *hws, + struct dchub_init_data *dh_data) +{ + /* TODO: port code from dal2 */ + switch (dh_data->fb_mode) { + case FRAME_BUFFER_MODE_ZFB_ONLY: + /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ + REG_UPDATE_2(DCHUB_FB_LOCATION, + FB_TOP, 0, + FB_BASE, 0x0FFFF); + + REG_UPDATE(DCHUB_AGP_BASE, + AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUB_AGP_BOT, + AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUB_AGP_TOP, + AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUB_AGP_BASE, + AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUB_AGP_BOT, + AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUB_AGP_TOP, + AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_LOCAL_ONLY: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUB_AGP_BASE, + AGP_BASE, 0); + + REG_UPDATE(DCHUB_AGP_BOT, + AGP_BOT, 0x03FFFF); + + REG_UPDATE(DCHUB_AGP_TOP, + AGP_TOP, 0); + break; + default: + break; + } + + dh_data->dchub_initialzied = true; + dh_data->dchub_info_valid = false; +} + + + bool dce120_hw_sequencer_construct(struct core_dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and @@ -191,6 +254,7 @@ bool dce120_hw_sequencer_construct(struct core_dc *dc) */ dce110_hw_sequencer_construct(dc); dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating; + dc->hwss.update_dchub = dce120_update_dchub; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 82481247a812..f829b6e58bcb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -598,7 +598,7 @@ static struct stream_encoder *dce120_stream_encoder_create( mm ## block ## id ## _ ## reg_name static const struct dce_hwseq_registers hwseq_reg = { - HWSEQ_DCE112_REG_LIST() + HWSEQ_DCE120_REG_LIST() }; static const struct dce_hwseq_shift hwseq_shift = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d61b63df16b8..b7940876c761 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -218,6 +218,306 @@ static void dpp_pg_control( } } +static uint32_t convert_and_clamp( + uint32_t wm_ns, + uint32_t refclk_mhz, + uint32_t clamp_value) +{ + uint32_t ret_val = 0; + ret_val = wm_ns * refclk_mhz; + ret_val /= 1000; + + if (ret_val > clamp_value) + ret_val = clamp_value; + + return ret_val; +} + +static void program_watermarks( + struct dce_hwseq *hws, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz) +{ + uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0; + /* + * Need to clamp to max of the register values (i.e. no wrap) + * for dcn1, all wm registers are 21-bit wide + */ + uint32_t prog_wm_value; + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); + + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.urgent_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.pte_meta_urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); + + + /* clock state B */ + prog_wm_value = convert_and_clamp( + watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.pte_meta_urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_ENTER_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); + + /* clock state C */ + prog_wm_value = convert_and_clamp( + watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.pte_meta_urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_ENTER_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); + + /* clock state D */ + prog_wm_value = convert_and_clamp( + watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.urgent_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp( + watermarks->d.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.pte_meta_urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_ENTER_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "SR_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); + dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0); + REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); + + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); + +#if 0 + REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); +#endif +} + + +static void dcn10_update_dchub( + struct dce_hwseq *hws, + struct dchub_init_data *dh_data) +{ + /* TODO: port code from dal2 */ + switch (dh_data->fb_mode) { + case FRAME_BUFFER_MODE_ZFB_ONLY: + /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ + REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, + SDPIF_FB_TOP, 0); + + REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, + SDPIF_FB_BASE, 0x0FFFF); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_LOCAL_ONLY: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, 0); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, 0X03FFFF); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, 0); + break; + default: + break; + } + + dh_data->dchub_initialzied = true; + dh_data->dchub_info_valid = false; +} + static void hubp_pg_control( struct dce_hwseq *hws, unsigned int hubp_inst, @@ -1615,8 +1915,7 @@ static void program_all_pipe_in_tree( * this OTG. this is done only one time. */ /* watermark is for all pipes */ - pipe_ctx->mi->funcs->program_watermarks( - pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz); + program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); if (dc->public.debug.sanity_checks) { /* pstate stuck check after watermark update */ @@ -2078,6 +2377,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, + .update_dchub = dcn10_update_dchub, .update_pending_status = dcn10_update_pending_status, .set_input_transfer_func = dcn10_set_input_transfer_func, .set_output_transfer_func = dcn10_set_output_transfer_func, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 1f86295d6db6..c56a69b5a4d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -574,250 +574,6 @@ static void min10_setup( min10_vready_workaround(mem_input, pipe_dest); } -static uint32_t convert_and_clamp( - uint32_t wm_ns, - uint32_t refclk_mhz, - uint32_t clamp_value) -{ - uint32_t ret_val = 0; - ret_val = wm_ns * refclk_mhz; - ret_val /= 1000; - - if (ret_val > clamp_value) - ret_val = clamp_value; - - return ret_val; -} - -static void min10_program_watermarks( - struct mem_input *mem_input, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz) -{ - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); - uint32_t force_en = mem_input->ctx->dc->debug.disable_stutter ? 1 : 0; - /* - * Need to clamp to max of the register values (i.e. no wrap) - * for dcn1, all wm registers are 21-bit wide - */ - uint32_t prog_wm_value; - - /* Repeat for water mark set A, B, C and D. */ - /* clock state A */ - prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); - - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.urgent_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.pte_meta_urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); - - - /* clock state B */ - prog_wm_value = convert_and_clamp( - watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.pte_meta_urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_ENTER_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); - - /* clock state C */ - prog_wm_value = convert_and_clamp( - watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.pte_meta_urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_ENTER_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); - - /* clock state D */ - prog_wm_value = convert_and_clamp( - watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.urgent_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp( - watermarks->d.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.pte_meta_urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_ENTER_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "SR_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS, - "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0); - REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); - - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); - -#if 0 - REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); -#endif -} - static void min10_program_display_marks( struct mem_input *mem_input, struct dce_watermarks nbp, @@ -855,63 +611,6 @@ static bool min10_is_flip_pending(struct mem_input *mem_input) return false; } -static void min10_update_dchub( - struct mem_input *mem_input, - struct dchub_init_data *dh_data) -{ - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); - /* TODO: port code from dal2 */ - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, - SDPIF_FB_TOP, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, - SDPIF_FB_BASE, 0x0FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, 0X03FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - struct vm_system_aperture_param { PHYSICAL_ADDRESS_LOC sys_default; PHYSICAL_ADDRESS_LOC sys_low; @@ -1114,8 +813,6 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { min10_program_surface_config, .mem_input_is_flip_pending = min10_is_flip_pending, .mem_input_setup = min10_setup, - .program_watermarks = min10_program_watermarks, - .mem_input_update_dchub = min10_update_dchub, .mem_input_program_pte_vm = min10_program_pte_vm, .set_blank = min10_set_blank, .dcc_control = min10_dcc_control, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h index 0f4d247c4237..9130f5e0ab03 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h @@ -98,30 +98,6 @@ SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ - SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ - SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ - SR(DCHUBBUB_ARB_SAT_LEVEL),\ - SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ /* todo: get these from GVM instead of reading registers ourselves */\ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ @@ -154,12 +130,8 @@ SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ - SR(DCHUBBUB_SDPIF_FB_TOP),\ SR(DCHUBBUB_SDPIF_FB_BASE),\ - SR(DCHUBBUB_SDPIF_FB_OFFSET),\ - SR(DCHUBBUB_SDPIF_AGP_BASE),\ - SR(DCHUBBUB_SDPIF_AGP_BOT),\ - SR(DCHUBBUB_SDPIF_AGP_TOP) + SR(DCHUBBUB_SDPIF_FB_OFFSET) struct dcn_mi_registers { uint32_t DCHUBP_CNTL; @@ -248,42 +220,14 @@ struct dcn_mi_registers { uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; - uint32_t DCHUBBUB_SDPIF_FB_TOP; uint32_t DCHUBBUB_SDPIF_FB_BASE; uint32_t DCHUBBUB_SDPIF_FB_OFFSET; - uint32_t DCHUBBUB_SDPIF_AGP_BASE; - uint32_t DCHUBBUB_SDPIF_AGP_BOT; - uint32_t DCHUBBUB_SDPIF_AGP_TOP; uint32_t DCN_VM_FB_LOCATION_TOP; uint32_t DCN_VM_FB_LOCATION_BASE; uint32_t DCN_VM_FB_OFFSET; uint32_t DCN_VM_AGP_BASE; uint32_t DCN_VM_AGP_BOT; uint32_t DCN_VM_AGP_TOP; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; - uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; - uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; - uint32_t DCHUBBUB_ARB_SAT_LEVEL; - uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; /* GC registers. read only. temporary hack */ uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; @@ -418,13 +362,7 @@ struct dcn_mi_registers { MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\ - MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\ - MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh) + MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) #define MI_MASK_SH_LIST_DCN10(mask_sh)\ MI_MASK_SH_LIST_DCN(mask_sh),\ @@ -443,12 +381,8 @@ struct dcn_mi_registers { MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh),\ MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ @@ -611,12 +545,6 @@ struct dcn_mi_registers { type AGP_BASE;\ type AGP_BOT;\ type AGP_TOP;\ - type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ - type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ - type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ - type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ - type DCHUBBUB_ARB_SAT_LEVEL;\ - type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ /* todo: get these from GVM instead of reading registers ourselves */\ type PAGE_DIRECTORY_ENTRY_HI32;\ type PAGE_DIRECTORY_ENTRY_LO32;\ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 1b7d151a66f8..fd3ce742af2c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -75,11 +75,6 @@ struct mem_input { struct mem_input_funcs { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - void (*program_watermarks)( - struct mem_input *mem_input, - struct dcn_watermark_set *watermarks, - unsigned int refclk_period_ns); - void (*mem_input_setup)( struct mem_input *mem_input, struct _vcs_dpi_display_dlg_regs_st *dlg_regs, @@ -143,7 +138,7 @@ struct mem_input_funcs { bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); void (*mem_input_update_dchub)(struct mem_input *mem_input, - struct dchub_init_data *dh_data); + struct dchub_init_data *dh_data); void (*set_blank)(struct mem_input *mi, bool blank); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 22aca5a375ae..d865df802c88 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -79,6 +79,10 @@ struct hw_sequencer_funcs { const struct core_dc *dc, struct pipe_ctx *pipe_ctx); + void (*update_dchub)( + struct dce_hwseq *hws, + struct dchub_init_data *dh_data); + void (*update_pending_status)( struct pipe_ctx *pipe_ctx); -- cgit v1.2.3-59-g8ed1b From e12cfcb1d447cc937d1abc6f4aab8bbe5f88542e Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 20 Jul 2017 11:43:32 -0400 Subject: drm/amd/display: Roll core_surface into dc_surface Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 8 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 16 ++-- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 26 +++--- drivers/gpu/drm/amd/display/dc/core/dc.c | 73 +++++++-------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 42 ++++----- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 44 ++++----- drivers/gpu/drm/amd/display/dc/dc.h | 45 +++++---- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 102 ++++++++++----------- .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 76 +++++++-------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 16 +--- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- 16 files changed, 226 insertions(+), 240 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 44d85b77e252..b247904206ba 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2345,7 +2345,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; const struct dc_stream *dc_stream_attach; - const struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -2624,7 +2624,7 @@ void amdgpu_dm_atomic_commit_tail( struct dm_connector_state *con_old_state = to_dm_connector_state(old_conn_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); - const struct dc_stream_status *status = NULL; + struct dc_stream_status *status = NULL; /* Skip any modesets/resets */ if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) @@ -2649,7 +2649,7 @@ void amdgpu_dm_atomic_commit_tail( /*TODO How it works with MPO ?*/ if (!dc_commit_surfaces_to_stream( dm->dc, - (const struct dc_surface **)status->surfaces, + status->surfaces, status->surface_count, new_acrtc_state->stream)) dm_error("%s: Failed to update stream scaling!\n", __func__); @@ -2793,7 +2793,7 @@ static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream *stream, - const struct dc_surface *surface) + struct dc_surface *surface) { uint32_t i = 0, j = 0; diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 87666987429e..5ef44ff4bcf8 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2597,12 +2597,12 @@ static void populate_initial_data( ASSERT(pipe[i].surface); if (num_displays == 0) { - if (!pipe[i].surface->public.visible) + if (!pipe[i].surface->visible) data->d0_underlay_mode = bw_def_underlay_only; else data->d0_underlay_mode = bw_def_blend; } else { - if (!pipe[i].surface->public.visible) + if (!pipe[i].surface->visible) data->d1_underlay_mode = bw_def_underlay_only; else data->d1_underlay_mode = bw_def_blend; @@ -2620,7 +2620,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->public.rotation) { + switch (pipe[i].surface->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2636,7 +2636,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->public.format) { + switch (pipe[i].surface->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: case SURFACE_PIXEL_FORMAT_GRPH_RGB565: @@ -2670,14 +2670,14 @@ static void populate_initial_data( data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.height); data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.width); data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed( - pipe[i].bottom_pipe->surface->public.plane_size.grph.surface_pitch); + pipe[i].bottom_pipe->surface->plane_size.grph.surface_pitch); data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.h_taps); data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.v_taps); data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.horz.value); data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.vert.value); - switch (pipe[i].bottom_pipe->surface->public.rotation) { + switch (pipe[i].bottom_pipe->surface->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0); break; @@ -2718,7 +2718,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->public.rotation) { + switch (pipe[i].surface->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2734,7 +2734,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->public.format) { + switch (pipe[i].surface->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 17b28280236f..1651b7548d40 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -238,11 +238,11 @@ static void pipe_ctx_to_e2e_pipe_params ( else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface) input->src.is_hsplit = true; - input->src.dcc = pipe->surface->public.dcc.enable; + input->src.dcc = pipe->surface->dcc.enable; input->src.dcc_rate = 1; - input->src.meta_pitch = pipe->surface->public.dcc.grph.meta_pitch; + input->src.meta_pitch = pipe->surface->dcc.grph.meta_pitch; input->src.source_scan = dm_horz; - input->src.sw_mode = pipe->surface->public.tiling_info.gfx9.swizzle; + input->src.sw_mode = pipe->surface->tiling_info.gfx9.swizzle; input->src.viewport_width = pipe->scl_data.viewport.width; input->src.viewport_height = pipe->scl_data.viewport.height; @@ -251,7 +251,7 @@ static void pipe_ctx_to_e2e_pipe_params ( input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ input->src.cur0_bpp = 32; - switch (pipe->surface->public.tiling_info.gfx9.swizzle) { + switch (pipe->surface->tiling_info.gfx9.swizzle) { /* for 4/8/16 high tiles */ case DC_SW_LINEAR: input->src.is_display_sw = 1; @@ -299,7 +299,7 @@ static void pipe_ctx_to_e2e_pipe_params ( break; } - switch (pipe->surface->public.rotation) { + switch (pipe->surface->rotation) { case ROTATION_ANGLE_0: case ROTATION_ANGLE_180: input->src.source_scan = dm_horz; @@ -314,7 +314,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } /* TODO: Fix pixel format mappings */ - switch (pipe->surface->public.format) { + switch (pipe->surface->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: input->src.source_format = dm_420_8; @@ -455,7 +455,7 @@ static void dcn_bw_calc_rq_dlg_ttu( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->public.flip_immediate); + pipe->surface->flip_immediate); } static void dcn_dml_wm_override( @@ -527,7 +527,7 @@ static void dcn_dml_wm_override( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->public.flip_immediate); + pipe->surface->flip_immediate); in_idx++; } dm_free(input); @@ -883,7 +883,7 @@ bool dcn_validate_bandwidth( v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width; v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height; if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) { - if (pipe->surface->public.rotation % 2 == 0) { + if (pipe->surface->rotation % 2 == 0) { int viewport_end = pipe->scl_data.viewport.width + pipe->scl_data.viewport.x; int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width @@ -912,17 +912,17 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->scl_data.recout.width; } - v->dcc_enable[input_idx] = pipe->surface->public.dcc.enable ? dcn_bw_yes : dcn_bw_no; + v->dcc_enable[input_idx] = pipe->surface->dcc.enable ? dcn_bw_yes : dcn_bw_no; v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( - pipe->surface->public.format); + pipe->surface->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( - pipe->surface->public.tiling_info.gfx9.swizzle); + pipe->surface->tiling_info.gfx9.swizzle); v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth); v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps; v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps; v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c; v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c; - v->source_scan[input_idx] = (pipe->surface->public.rotation % 2) ? dcn_bw_vert : dcn_bw_hor; + v->source_scan[input_idx] = (pipe->surface->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e89a2e5c8902..569310ab116d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -946,8 +946,8 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c const struct core_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { - struct core_surface *surface = - DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]); + const struct dc_surface *surface = + context->stream_status[i].surfaces[j]; core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); @@ -1098,7 +1098,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) bool dc_commit_surfaces_to_stream( struct dc *dc, - const struct dc_surface **new_surfaces, + struct dc_surface **new_surfaces, uint8_t new_surface_count, const struct dc_stream *dc_stream) { @@ -1189,7 +1189,7 @@ static bool is_surface_in_context( for (j = 0; j < MAX_PIPES; j++) { const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (surface == &pipe_ctx->surface->public) { + if (surface == pipe_ctx->surface) { return true; } } @@ -1422,7 +1422,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - const struct dc_surface *new_surfaces[MAX_SURFACES] = {0}; + struct dc_surface *new_surfaces[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) new_surfaces[i] = srf_updates[i].surface; @@ -1448,46 +1448,45 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* save update parameters into surface */ for (i = 0; i < surface_count; i++) { - struct core_surface *surface = - DC_SURFACE_TO_CORE(srf_updates[i].surface); + struct dc_surface *surface = srf_updates[i].surface; if (srf_updates[i].flip_addr) { - surface->public.address = srf_updates[i].flip_addr->address; - surface->public.flip_immediate = + surface->address = srf_updates[i].flip_addr->address; + surface->flip_immediate = srf_updates[i].flip_addr->flip_immediate; } if (srf_updates[i].scaling_info) { - surface->public.scaling_quality = + surface->scaling_quality = srf_updates[i].scaling_info->scaling_quality; - surface->public.dst_rect = + surface->dst_rect = srf_updates[i].scaling_info->dst_rect; - surface->public.src_rect = + surface->src_rect = srf_updates[i].scaling_info->src_rect; - surface->public.clip_rect = + surface->clip_rect = srf_updates[i].scaling_info->clip_rect; } if (srf_updates[i].plane_info) { - surface->public.color_space = + surface->color_space = srf_updates[i].plane_info->color_space; - surface->public.format = + surface->format = srf_updates[i].plane_info->format; - surface->public.plane_size = + surface->plane_size = srf_updates[i].plane_info->plane_size; - surface->public.rotation = + surface->rotation = srf_updates[i].plane_info->rotation; - surface->public.horizontal_mirror = + surface->horizontal_mirror = srf_updates[i].plane_info->horizontal_mirror; - surface->public.stereo_format = + surface->stereo_format = srf_updates[i].plane_info->stereo_format; - surface->public.tiling_info = + surface->tiling_info = srf_updates[i].plane_info->tiling_info; - surface->public.visible = + surface->visible = srf_updates[i].plane_info->visible; - surface->public.per_pixel_alpha = + surface->per_pixel_alpha = srf_updates[i].plane_info->per_pixel_alpha; - surface->public.dcc = + surface->dcc = srf_updates[i].plane_info->dcc; } @@ -1503,31 +1502,31 @@ void dc_update_surfaces_and_stream(struct dc *dc, } if (srf_updates[i].gamma && - srf_updates[i].gamma != surface->public.gamma_correction) { - if (surface->public.gamma_correction != NULL) - dc_gamma_release(&surface->public. + srf_updates[i].gamma != surface->gamma_correction) { + if (surface->gamma_correction != NULL) + dc_gamma_release(&surface-> gamma_correction); dc_gamma_retain(srf_updates[i].gamma); - surface->public.gamma_correction = + surface->gamma_correction = srf_updates[i].gamma; } if (srf_updates[i].in_transfer_func && - srf_updates[i].in_transfer_func != surface->public.in_transfer_func) { - if (surface->public.in_transfer_func != NULL) + srf_updates[i].in_transfer_func != surface->in_transfer_func) { + if (surface->in_transfer_func != NULL) dc_transfer_func_release( - surface->public. + surface-> in_transfer_func); dc_transfer_func_retain( srf_updates[i].in_transfer_func); - surface->public.in_transfer_func = + surface->in_transfer_func = srf_updates[i].in_transfer_func; } if (srf_updates[i].hdr_static_metadata) - surface->public.hdr_static_ctx = + surface->hdr_static_ctx = *(srf_updates[i].hdr_static_metadata); } @@ -1543,12 +1542,10 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (update_type > UPDATE_TYPE_FAST) { for (i = 0; i < surface_count; i++) { - struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->surface != srf_updates[i].surface) continue; core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe_ctx); @@ -1561,7 +1558,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); + struct dc_surface *surface = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1613,7 +1610,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); + struct dc_surface *surface = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( @@ -1654,7 +1651,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < surface_count; j++) { if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != &pipe_ctx->surface->public) + srf_updates[j].surface != pipe_ctx->surface) continue; if (!pipe_ctx->surface || pipe_ctx->top_pipe) continue; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 5acc5cdcda16..303c95432d5b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -428,7 +428,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = &pipe_ctx->surface->public; + const struct dc_surface *surface = pipe_ctx->surface; const struct dc_stream *stream = &pipe_ctx->stream->public; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; @@ -446,8 +446,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) sec_split = false; } - if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) + if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); /* The actual clip is an intersection between stream @@ -527,14 +527,14 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_surface *surface = &pipe_ctx->surface->public; + const struct dc_surface *surface = pipe_ctx->surface; struct core_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; - if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) + if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.recout.x = stream->public.dst.x; @@ -605,7 +605,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = &pipe_ctx->surface->public; + const struct dc_surface *surface = pipe_ctx->surface; struct core_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->public.src.width; @@ -613,8 +613,8 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) const int out_w = stream->public.dst.width; const int out_h = stream->public.dst.height; - if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) + if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction( @@ -647,13 +647,13 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { struct scaler_data *data = &pipe_ctx->scl_data; - struct rect src = pipe_ctx->surface->public.src_rect; + struct rect src = pipe_ctx->surface->src_rect; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&src); rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); @@ -803,8 +803,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); - if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -812,7 +812,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = &pipe_ctx->surface->public; + const struct dc_surface *surface = pipe_ctx->surface; struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; struct view recout_skip = { 0 }; bool res = false; @@ -822,7 +822,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * Inits require viewport, taps, ratios and recout of split pipe */ pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( - pipe_ctx->surface->public.format); + pipe_ctx->surface->format); calculate_scaling_ratios(pipe_ctx); @@ -1029,7 +1029,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - const struct dc_surface * const *surfaces, + struct dc_surface * const *surfaces, int surface_count, const struct dc_stream *dc_stream, struct validate_context *context, @@ -1077,7 +1077,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); + struct dc_surface *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, dc_stream); @@ -1358,7 +1358,7 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct core_surface *surface = to_pipe_ctx->surface; + struct dc_surface *surface = to_pipe_ctx->surface; struct core_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; @@ -2072,7 +2072,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct core_surface *surface, + struct dc_surface *surface, struct core_stream *stream) { uint16_t i = 0; @@ -2083,7 +2083,7 @@ static void set_hdr_static_info_packet( if (!surface) return; - hdr_metadata = surface->public.hdr_static_ctx; + hdr_metadata = surface->hdr_static_ctx; if (!hdr_metadata.hdr_supported) return; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index ead7b63caab7..73712fd6f64a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -157,7 +157,7 @@ alloc_fail: return NULL; } -const struct dc_stream_status *dc_stream_get_status( +struct dc_stream_status *dc_stream_get_status( const struct dc_stream *dc_stream) { uint8_t i; @@ -252,7 +252,7 @@ bool dc_stream_set_cursor_position( !pipe_ctx->ipp || !pipe_ctx->surface) continue; - if (pipe_ctx->surface->public.address.type + if (pipe_ctx->surface->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) pos_cpy.enable = false; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 3784358d35ef..9a21ea71f4b3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -47,33 +47,32 @@ struct gamma { /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct core_surface *surface) +static bool construct(struct dc_context *ctx, struct dc_surface *surface) { surface->ctx = ctx; - memset(&surface->public.hdr_static_ctx, + memset(&surface->hdr_static_ctx, 0, sizeof(struct dc_hdr_static_metadata)); return true; } -static void destruct(struct core_surface *surface) +static void destruct(struct dc_surface *surface) { - if (surface->public.gamma_correction != NULL) { - dc_gamma_release(&surface->public.gamma_correction); + if (surface->gamma_correction != NULL) { + dc_gamma_release(&surface->gamma_correction); } - if (surface->public.in_transfer_func != NULL) { + if (surface->in_transfer_func != NULL) { dc_transfer_func_release( - surface->public.in_transfer_func); - surface->public.in_transfer_func = NULL; + surface->in_transfer_func); + surface->in_transfer_func = NULL; } } /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_surface *dc_surface, +void enable_surface_flip_reporting(struct dc_surface *surface, uint32_t controller_id) { - struct core_surface *surface = DC_SURFACE_TO_CORE(dc_surface); surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } @@ -82,7 +81,7 @@ struct dc_surface *dc_create_surface(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_surface *surface = dm_alloc(sizeof(*surface)); + struct dc_surface *surface = dm_alloc(sizeof(*surface)); if (NULL == surface) goto alloc_fail; @@ -92,7 +91,7 @@ struct dc_surface *dc_create_surface(const struct dc *dc) ++surface->ref_count; - return &surface->public; + return surface; construct_fail: dm_free(surface); @@ -104,20 +103,19 @@ alloc_fail: const struct dc_surface_status *dc_surface_get_status( const struct dc_surface *dc_surface) { - struct dc_surface_status *surface_status; - struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface); + const struct dc_surface_status *surface_status; struct core_dc *core_dc; int i; if (!dc_surface || - !core_surface->ctx || - !core_surface->ctx->dc) { + !dc_surface->ctx || + !dc_surface->ctx->dc) { ASSERT(0); return NULL; /* remove this if above assert never hit */ } - surface_status = &core_surface->status; - core_dc = DC_TO_CORE(core_surface->ctx->dc); + surface_status = &dc_surface->status; + core_dc = DC_TO_CORE(dc_surface->ctx->dc); if (core_dc->current_context == NULL) return NULL; @@ -126,7 +124,7 @@ const struct dc_surface_status *dc_surface_get_status( struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != core_surface) + if (pipe_ctx->surface != dc_surface) continue; core_dc->hwss.update_pending_status(pipe_ctx); @@ -135,18 +133,14 @@ const struct dc_surface_status *dc_surface_get_status( return surface_status; } -void dc_surface_retain(const struct dc_surface *dc_surface) +void dc_surface_retain(struct dc_surface *surface) { - struct core_surface *surface = DC_SURFACE_TO_CORE(dc_surface); - ASSERT(surface->ref_count > 0); ++surface->ref_count; } -void dc_surface_release(const struct dc_surface *dc_surface) +void dc_surface_release(struct dc_surface *surface) { - struct core_surface *surface = DC_SURFACE_TO_CORE(dc_surface); - ASSERT(surface->ref_count > 0); --surface->ref_count; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ee04c3562081..b14bad10db97 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -299,6 +299,18 @@ struct dc_transfer_func { int ref_count; }; +/* + * This structure is filled in by dc_surface_get_status and contains + * the last requested address and the currently active address so the called + * can determine if there are any outstanding flips + */ +struct dc_surface_status { + struct dc_plane_address requested_address; + struct dc_plane_address current_address; + bool is_flip_pending; + bool is_right_eye; +}; + struct dc_surface { struct dc_plane_address address; @@ -325,6 +337,14 @@ struct dc_surface { bool visible; bool flip_immediate; bool horizontal_mirror; + + /* private to DC core */ + struct dc_surface_status status; + struct dc_context *ctx; + + /* private to dc_surface.c */ + enum dc_irq_source irq_source; + int ref_count; }; struct dc_plane_info { @@ -348,7 +368,7 @@ struct dc_scaling_info { }; struct dc_surface_update { - const struct dc_surface *surface; + struct dc_surface *surface; /* isr safe update parameters. null means no updates */ struct dc_flip_addrs *flip_addr; @@ -362,17 +382,6 @@ struct dc_surface_update { struct dc_transfer_func *in_transfer_func; struct dc_hdr_static_metadata *hdr_static_metadata; }; -/* - * This structure is filled in by dc_surface_get_status and contains - * the last requested address and the currently active address so the called - * can determine if there are any outstanding flips - */ -struct dc_surface_status { - struct dc_plane_address requested_address; - struct dc_plane_address current_address; - bool is_flip_pending; - bool is_right_eye; -}; /* * Create a new surface with default parameters; @@ -381,8 +390,8 @@ struct dc_surface *dc_create_surface(const struct dc *dc); const struct dc_surface_status *dc_surface_get_status( const struct dc_surface *dc_surface); -void dc_surface_retain(const struct dc_surface *dc_surface); -void dc_surface_release(const struct dc_surface *dc_surface); +void dc_surface_retain(struct dc_surface *dc_surface); +void dc_surface_release(struct dc_surface *dc_surface); void dc_gamma_retain(const struct dc_gamma *dc_gamma); void dc_gamma_release(const struct dc_gamma **dc_gamma); @@ -416,7 +425,7 @@ struct dc_flip_addrs { bool dc_commit_surfaces_to_stream( struct dc *dc, - const struct dc_surface **dc_surfaces, + struct dc_surface **dc_surfaces, uint8_t surface_count, const struct dc_stream *stream); @@ -545,7 +554,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, */ struct dc_validation_set { const struct dc_stream *stream; - const struct dc_surface *surfaces[MAX_SURFACES]; + struct dc_surface *surfaces[MAX_SURFACES]; uint8_t surface_count; }; @@ -627,7 +636,7 @@ void dc_stream_release(const struct dc_stream *dc_stream); struct dc_stream_status { int primary_otg_inst; int surface_count; - const struct dc_surface *surfaces[MAX_SURFACE_NUM]; + struct dc_surface *surfaces[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -635,7 +644,7 @@ struct dc_stream_status { const struct dc_link *link; }; -const struct dc_stream_status *dc_stream_get_status( +struct dc_stream_status *dc_stream_get_status( const struct dc_stream *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index cc3178acfc54..a8c254f66c98 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -193,9 +193,9 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct core_surface *surface) +bool dce_use_lut(const struct dc_surface *surface) { - switch (surface->public.format) { + switch (surface->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index d62fc526783f..ade7507e99c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct core_surface *surface); +bool dce_use_lut(const struct dc_surface *surface); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index efba8d7964eb..cf6bf2098b7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,11 +215,11 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct core_surface *surface) + const struct dc_surface *surface) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; - switch (surface->public.format) { + switch (surface->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: prescale_params->scale = 0x2020; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_surface *surface) + const struct dc_surface *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -250,14 +250,14 @@ static bool dce110_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->public.in_transfer_func) - tf = surface->public.in_transfer_func; + if (surface->in_transfer_func) + tf = surface->in_transfer_func; build_prescale_params(&prescale_params, surface); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - if (surface->public.gamma_correction && dce_use_lut(surface)) - ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); + if (surface->gamma_correction && dce_use_lut(surface)) + ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction); if (tf == NULL) { /* Default case if no input transfer function specified */ @@ -1857,7 +1857,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) default_adjust.in_color_space = COLOR_SPACE_SRGB; else default_adjust.in_color_space = - pipe_ctx->surface->public.color_space; + pipe_ctx->surface->color_space; if (pipe_ctx->stream == NULL) default_adjust.out_color_space = COLOR_SPACE_SRGB; else @@ -1908,16 +1908,16 @@ static void program_surface_visibility(const struct core_dc *dc, /* For now we are supporting only two pipes */ ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); - if (pipe_ctx->bottom_pipe->surface->public.visible) { - if (pipe_ctx->surface->public.visible) + if (pipe_ctx->bottom_pipe->surface->visible) { + if (pipe_ctx->surface->visible) blender_mode = BLND_MODE_BLENDING; else blender_mode = BLND_MODE_OTHER_PIPE; - } else if (!pipe_ctx->surface->public.visible) + } else if (!pipe_ctx->surface->visible) blank_target = true; - } else if (!pipe_ctx->surface->public.visible) + } else if (!pipe_ctx->surface->visible) blank_target = true; dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); @@ -1975,7 +1975,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2040,42 +2040,42 @@ static void set_plane_config( mi->funcs->mem_input_program_surface_config( mi, - surface->public.format, - &surface->public.tiling_info, - &surface->public.plane_size, - surface->public.rotation, + surface->format, + &surface->tiling_info, + &surface->plane_size, + surface->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible); + mi->funcs->set_blank(mi, pipe_ctx->surface->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->public.format, - &surface->public.tiling_info, - surface->public.rotation); + surface->format, + &surface->tiling_info, + surface->rotation); } static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; if (surface == NULL) return; pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->public.address, - surface->public.flip_immediate); + &surface->address, + surface->flip_immediate); - surface->status.requested_address = surface->public.address; + surface->status.requested_address = surface->address; } void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2084,7 +2084,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); - if (surface->status.is_flip_pending && !surface->public.visible) + if (surface->status.is_flip_pending && !surface->visible) pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; surface->status.current_address = pipe_ctx->mi->current_address; @@ -2425,7 +2425,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2493,21 +2493,21 @@ static void dce110_program_front_end_for_pipe( mi->funcs->mem_input_program_surface_config( mi, - surface->public.format, - &surface->public.tiling_info, - &surface->public.plane_size, - surface->public.rotation, + surface->format, + &surface->tiling_info, + &surface->plane_size, + surface->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible); + mi->funcs->set_blank(mi, pipe_ctx->surface->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->public.format, - &surface->public.tiling_info, - surface->public.rotation); + surface->format, + &surface->tiling_info, + surface->rotation); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe:%d 0x%x: addr hi:0x%x, " @@ -2517,20 +2517,20 @@ static void dce110_program_front_end_for_pipe( "clip: %d, %d, %d, %d\n", pipe_ctx->pipe_idx, pipe_ctx->surface, - pipe_ctx->surface->public.address.grph.addr.high_part, - pipe_ctx->surface->public.address.grph.addr.low_part, - pipe_ctx->surface->public.src_rect.x, - pipe_ctx->surface->public.src_rect.y, - pipe_ctx->surface->public.src_rect.width, - pipe_ctx->surface->public.src_rect.height, - pipe_ctx->surface->public.dst_rect.x, - pipe_ctx->surface->public.dst_rect.y, - pipe_ctx->surface->public.dst_rect.width, - pipe_ctx->surface->public.dst_rect.height, - pipe_ctx->surface->public.clip_rect.x, - pipe_ctx->surface->public.clip_rect.y, - pipe_ctx->surface->public.clip_rect.width, - pipe_ctx->surface->public.clip_rect.height); + pipe_ctx->surface->address.grph.addr.high_part, + pipe_ctx->surface->address.grph.addr.low_part, + pipe_ctx->surface->src_rect.x, + pipe_ctx->surface->src_rect.y, + pipe_ctx->surface->src_rect.width, + pipe_ctx->surface->src_rect.height, + pipe_ctx->surface->dst_rect.x, + pipe_ctx->surface->dst_rect.y, + pipe_ctx->surface->dst_rect.width, + pipe_ctx->surface->dst_rect.height, + pipe_ctx->surface->clip_rect.x, + pipe_ctx->surface->clip_rect.y, + pipe_ctx->surface->clip_rect.width, + pipe_ctx->surface->clip_rect.height); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe %d: width, height, x, y\n" @@ -2549,7 +2549,7 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - struct core_surface *surface, + const struct dc_surface *surface, struct validate_context *context) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 8b7bc1cc2b7b..0fcb1cf4b4ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -766,7 +766,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne return true; if (!pipe_ctx->surface) return false; - if (pipe_ctx->surface->public.format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (pipe_ctx->surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index b7940876c761..4390023ca6dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -945,24 +945,24 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; - if (sec_split && surface->public.address.type == PLN_ADDR_TYPE_GRPH_STEREO && + if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && (pipe_ctx->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || pipe_ctx->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { - *addr = surface->public.address.grph_stereo.left_addr; - surface->public.address.grph_stereo.left_addr = - surface->public.address.grph_stereo.right_addr; + *addr = surface->address.grph_stereo.left_addr; + surface->address.grph_stereo.left_addr = + surface->address.grph_stereo.right_addr; return true; } else { if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE && - surface->public.address.type != PLN_ADDR_TYPE_GRPH_STEREO) { - surface->public.address.type = PLN_ADDR_TYPE_GRPH_STEREO; - surface->public.address.grph_stereo.right_addr = - surface->public.address.grph_stereo.left_addr; + surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { + surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; + surface->address.grph_stereo.right_addr = + surface->address.grph_stereo.left_addr; } } return false; @@ -972,22 +972,22 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; if (surface == NULL) return; addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->public.address, - surface->public.flip_immediate); - surface->status.requested_address = surface->public.address; + &surface->address, + surface->flip_immediate); + surface->status.requested_address = surface->address; if (addr_patched) - pipe_ctx->surface->public.address.grph_stereo.left_addr = addr; + pipe_ctx->surface->address.grph_stereo.left_addr = addr; } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct core_surface *surface) + struct pipe_ctx *pipe_ctx, const struct dc_surface *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -996,12 +996,12 @@ static bool dcn10_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->public.in_transfer_func) - tf = surface->public.in_transfer_func; + if (surface->in_transfer_func) + tf = surface->in_transfer_func; - if (surface->public.gamma_correction && dce_use_lut(surface)) + if (surface->gamma_correction && dce_use_lut(surface)) ipp->funcs->ipp_program_input_lut(ipp, - surface->public.gamma_correction); + surface->gamma_correction); if (tf == NULL) ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); @@ -1594,7 +1594,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_surface *dc_surface = &pipe_ctx->surface->public; + struct dc_surface *dc_surface = pipe_ctx->surface; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1710,7 +1710,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->public.visible) + if (pipe_ctx->surface->visible) return true; if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) return true; @@ -1719,7 +1719,7 @@ static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->public.visible) + if (pipe_ctx->surface->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1728,7 +1728,7 @@ static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->public.visible) + if (pipe_ctx->surface->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1803,12 +1803,12 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct core_surface *surface = pipe_ctx->surface; - union plane_size size = surface->public.plane_size; + struct dc_surface *surface = pipe_ctx->surface; + union plane_size size = surface->plane_size; struct default_adjustment ocsc = {0}; struct tg_color black_color = {0}; struct mpcc_cfg mpcc_cfg; - bool per_pixel_alpha = surface->public.per_pixel_alpha && pipe_ctx->bottom_pipe; + bool per_pixel_alpha = surface->per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ /* depends on DML calculation, DPP clock value may change dynamically */ @@ -1841,12 +1841,12 @@ static void update_dchubp_dpp( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->public.format, - &surface->public.tiling_info, - surface->public.rotation); + surface->format, + &surface->tiling_info, + surface->rotation); ipp->funcs->ipp_setup(ipp, - surface->public.format, + surface->format, 1, IPP_OUTPUT_FORMAT_12_BIT_FIX); @@ -1892,12 +1892,12 @@ static void update_dchubp_dpp( mi->funcs->mem_input_program_surface_config( mi, - surface->public.format, - &surface->public.tiling_info, + surface->format, + &surface->tiling_info, &size, - surface->public.rotation, - &surface->public.dcc, - surface->public.horizontal_mirror); + surface->rotation, + &surface->dcc, + surface->horizontal_mirror); mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx)); } @@ -1978,7 +1978,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - struct core_surface *surface, + const struct dc_surface *surface, struct validate_context *context) { int i, be_idx; @@ -2337,7 +2337,7 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct core_surface *surface = pipe_ctx->surface; + struct dc_surface *surface = pipe_ctx->surface; struct timing_generator *tg = pipe_ctx->tg; if (surface->ctx->dc->debug.sanity_checks) { @@ -2355,7 +2355,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) /* DCN we read INUSE address in MI, do we still need this wa? */ if (surface->status.is_flip_pending && - !surface->public.visible) { + !surface->visible) { pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index cc65cfdea66f..07a1aec5a28b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -40,23 +40,9 @@ struct core_stream; #define MAX_CLOCK_SOURCES 7 -/********* core_surface **********/ -#define DC_SURFACE_TO_CORE(dc_surface) \ - container_of(dc_surface, struct core_surface, public) - #define DC_GAMMA_TO_CORE(dc_gamma) \ container_of(dc_gamma, struct core_gamma, public) -struct core_surface { - struct dc_surface public; - struct dc_surface_status status; - struct dc_context *ctx; - - /* private to dc_surface.c */ - enum dc_irq_source irq_source; - int ref_count; -}; - struct core_gamma { struct dc_gamma public; struct dc_context *ctx; @@ -263,7 +249,7 @@ struct resource_pool { }; struct pipe_ctx { - struct core_surface *surface; + struct dc_surface *surface; struct core_stream *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index d865df802c88..2343beb4ef87 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - struct core_surface *surface, + const struct dc_surface *surface, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct core_surface *surface); + const struct dc_surface *surface); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 04e5fd1d8c89..ed94df16a2d3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( const struct core_stream *stream); bool resource_attach_surfaces_to_context( - const struct dc_surface *const *surfaces, + struct dc_surface *const *surfaces, int surface_count, const struct dc_stream *dc_stream, struct validate_context *context, -- cgit v1.2.3-59-g8ed1b From d0778ebfd58f5650de17531296ee5ecdde39ba68 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sat, 22 Jul 2017 20:05:20 -0400 Subject: drm/amd/display: Roll core_link into dc_link Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 4 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 100 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 229 +++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 264 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 40 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 9 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 112 ++++++--- drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 4 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 58 +---- drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 16 +- drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 22 +- .../gpu/drm/amd/display/include/logger_interface.h | 8 +- 29 files changed, 444 insertions(+), 484 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 2bb2fc2a6566..c558f700df35 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -563,7 +563,7 @@ struct amdgpu_connector { /* The 'old' sink - before an HPD. * The 'current' sink is in dc_link->sink. */ const struct dc_sink *dc_sink; - const struct dc_link *dc_link; + struct dc_link *dc_link; const struct dc_sink *dc_em_sink; const struct dc_stream *stream; void *con_priv; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index b247904206ba..4885403f5cec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1874,7 +1874,7 @@ void amdgpu_dm_connector_init_helper( struct amdgpu_display_manager *dm, struct amdgpu_connector *aconnector, int connector_type, - const struct dc_link *link, + struct dc_link *link, int link_index) { struct amdgpu_device *adev = dm->ddev->dev_private; @@ -1997,7 +1997,7 @@ int amdgpu_dm_connector_init( int res = 0; int connector_type; struct dc *dc = dm->dc; - const struct dc_link *link = dc_get_link_at_index(dc, link_index); + struct dc_link *link = dc_get_link_at_index(dc, link_index); struct amdgpu_i2c_adapter *i2c; ((struct dc_link *)link)->priv = aconnector; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 115d9081d964..c565787cd782 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -114,7 +114,7 @@ void amdgpu_dm_connector_init_helper( struct amdgpu_display_manager *dm, struct amdgpu_connector *aconnector, int connector_type, - const struct dc_link *link, + struct dc_link *link, int link_index); int amdgpu_dm_connector_mode_valid( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 569310ab116d..73740e2a5819 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -94,7 +94,7 @@ static bool create_links( for (i = 0; i < connectors_num; i++) { struct link_init_data link_init_params = {0}; - struct core_link *link; + struct dc_link *link; link_init_params.ctx = dc->ctx; /* next BIOS object table connector */ @@ -111,7 +111,7 @@ static bool create_links( } for (i = 0; i < num_virtual_links; i++) { - struct core_link *link = dm_alloc(sizeof(*link)); + struct dc_link *link = dm_alloc(sizeof(*link)); struct encoder_init_data enc_init = {0}; if (link == NULL) { @@ -121,7 +121,7 @@ static bool create_links( link->ctx = dc->ctx; link->dc = dc; - link->public.connector_signal = SIGNAL_TYPE_VIRTUAL; + link->connector_signal = SIGNAL_TYPE_VIRTUAL; link->link_id.type = OBJECT_TYPE_CONNECTOR; link->link_id.id = CONNECTOR_ID_VIRTUAL; link->link_id.enum_id = ENUM_ID_1; @@ -137,7 +137,7 @@ static bool create_links( enc_init.encoder.enum_id = ENUM_ID_1; virtual_link_encoder_construct(link->link_enc, &enc_init); - link->public.link_index = dc->link_count; + link->link_index = dc->link_count; dc->links[dc->link_count] = link; dc->link_count++; } @@ -278,14 +278,14 @@ static void set_drive_settings(struct dc *dc, int i; for (i = 0; i < core_dc->link_count; i++) { - if (&core_dc->links[i]->public == link) + if (core_dc->links[i] == link) break; } if (i >= core_dc->link_count) ASSERT_CRITICAL(false); - dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings); + dc_link_dp_set_drive_settings(core_dc->links[i], lt_settings); } static void perform_link_training(struct dc *dc, @@ -297,20 +297,17 @@ static void perform_link_training(struct dc *dc, for (i = 0; i < core_dc->link_count; i++) dc_link_dp_perform_link_training( - &core_dc->links[i]->public, + core_dc->links[i], link_setting, skip_video_pattern); } static void set_preferred_link_settings(struct dc *dc, struct dc_link_settings *link_setting, - const struct dc_link *link) + struct dc_link *link) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - - core_link->public.preferred_link_setting = - *link_setting; - dp_retrain_link_dp_test(core_link, link_setting, false); + link->preferred_link_setting = *link_setting; + dp_retrain_link_dp_test(link, link_setting, false); } static void enable_hpd(const struct dc_link *link) @@ -325,7 +322,7 @@ static void disable_hpd(const struct dc_link *link) static void set_test_pattern( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, @@ -345,9 +342,8 @@ void set_dither_option(const struct dc_stream *dc_stream, { struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct bit_depth_reduction_params params; - struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link); - struct pipe_ctx *pipes = - core_link->dc->current_context->res_ctx.pipe_ctx; + struct dc_link *link = stream->status.link; + struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; memset(¶ms, 0, sizeof(params)); if (!stream) @@ -1693,10 +1689,10 @@ struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) return NULL; } -const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) +struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) { struct core_dc *core_dc = DC_TO_CORE(dc); - return &core_dc->links[link_index]->public; + return core_dc->links[link_index]; } const struct graphics_object_id dc_get_link_id_at_index( @@ -1710,7 +1706,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index) { struct core_dc *core_dc = DC_TO_CORE(dc); - return core_dc->links[link_index]->public.irq_source_hpd; + return core_dc->links[link_index]->irq_source_hpd; } const struct audio **dc_get_audios(struct dc *dc) @@ -1796,9 +1792,9 @@ bool dc_read_aux_dpcd( { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( - link->public.ddc, + link->ddc, false, I2C_MOT_UNDEF, address, @@ -1815,10 +1811,10 @@ bool dc_write_aux_dpcd( uint32_t size) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( - link->public.ddc, + link->ddc, false, I2C_MOT_UNDEF, address, @@ -1837,9 +1833,9 @@ bool dc_read_aux_i2c( { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( - link->public.ddc, + link->ddc, true, mot, address, @@ -1857,10 +1853,10 @@ bool dc_write_aux_i2c( uint32_t size) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( - link->public.ddc, + link->ddc, true, mot, address, @@ -1880,10 +1876,10 @@ bool dc_query_ddc_data( struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; bool result = dal_ddc_service_query_ddc_data( - link->public.ddc, + link->ddc, address, write_buf, write_size, @@ -1900,8 +1896,8 @@ bool dc_submit_i2c( { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; - struct ddc_service *ddc = link->public.ddc; + struct dc_link *link = core_dc->links[link_index]; + struct ddc_service *ddc = link->ddc; return dal_i2caux_submit_i2c_command( ddc->ctx->i2caux, @@ -1909,10 +1905,8 @@ bool dc_submit_i2c( cmd); } -static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink) +static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { - struct dc_link *dc_link = &core_link->public; - if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { BREAK_TO_DEBUGGER(); return false; @@ -1927,14 +1921,13 @@ static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_s } struct dc_sink *dc_link_add_remote_sink( - const struct dc_link *link, + struct dc_link *link, const uint8_t *edid, int len, struct dc_sink_init_data *init_data) { struct dc_sink *dc_sink; enum dc_edid_status edid_status; - struct core_link *core_link = DC_LINK_TO_LINK(link); if (len > MAX_EDID_BUFFER_SIZE) { dm_error("Max EDID buffer size breached!\n"); @@ -1960,12 +1953,12 @@ struct dc_sink *dc_link_add_remote_sink( dc_sink->dc_edid.length = len; if (!link_add_remote_sink_helper( - core_link, + link, dc_sink)) goto fail_add_sink; edid_status = dm_helpers_parse_edid_caps( - core_link->ctx, + link->ctx, &dc_sink->dc_edid, &dc_sink->edid_caps); @@ -1980,43 +1973,38 @@ fail_add_sink: return NULL; } -void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink) +void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink) { - struct core_link *core_link = DC_LINK_TO_LINK(link); - struct dc_link *dc_link = &core_link->public; - - dc_link->local_sink = sink; + link->local_sink = sink; if (sink == NULL) { - dc_link->type = dc_connection_none; + link->type = dc_connection_none; } else { - dc_link->type = dc_connection_single; + link->type = dc_connection_single; } } -void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink) +void dc_link_remove_remote_sink(struct dc_link *link, const struct dc_sink *sink) { int i; - struct core_link *core_link = DC_LINK_TO_LINK(link); - struct dc_link *dc_link = &core_link->public; if (!link->sink_count) { BREAK_TO_DEBUGGER(); return; } - for (i = 0; i < dc_link->sink_count; i++) { - if (dc_link->remote_sinks[i] == sink) { + for (i = 0; i < link->sink_count; i++) { + if (link->remote_sinks[i] == sink) { dc_sink_release(sink); - dc_link->remote_sinks[i] = NULL; + link->remote_sinks[i] = NULL; /* shrink array to remove empty place */ - while (i < dc_link->sink_count - 1) { - dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1]; + while (i < link->sink_count - 1) { + link->remote_sinks[i] = link->remote_sinks[i+1]; i++; } - dc_link->remote_sinks[i] = NULL; - dc_link->sink_count--; + link->remote_sinks[i] = NULL; + link->sink_count--; return; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 036d22f878b8..428dbff8505b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -62,24 +62,24 @@ enum { /******************************************************************************* * Private functions ******************************************************************************/ -static void destruct(struct core_link *link) +static void destruct(struct dc_link *link) { int i; - if (link->public.ddc) - dal_ddc_service_destroy(&link->public.ddc); + if (link->ddc) + dal_ddc_service_destroy(&link->ddc); if(link->link_enc) link->link_enc->funcs->destroy(&link->link_enc); - if (link->public.local_sink) - dc_sink_release(link->public.local_sink); + if (link->local_sink) + dc_sink_release(link->local_sink); - for (i = 0; i < link->public.sink_count; ++i) - dc_sink_release(link->public.remote_sinks[i]); + for (i = 0; i < link->sink_count; ++i) + dc_sink_release(link->remote_sinks[i]); } -static struct gpio *get_hpd_gpio(const struct core_link *link) +static struct gpio *get_hpd_gpio(const struct dc_link *link) { enum bp_result bp_result; struct dc_bios *dcb = link->ctx->dc_bios; @@ -116,7 +116,7 @@ static struct gpio *get_hpd_gpio(const struct core_link *link) * true on success, false otherwise */ static bool program_hpd_filter( - const struct core_link *link) + const struct dc_link *link) { bool result = false; @@ -126,7 +126,7 @@ static bool program_hpd_filter( int delay_on_disconnect_in_ms = 0; /* Verify feature is supported */ - switch (link->public.connector_signal) { + switch (link->connector_signal) { case SIGNAL_TYPE_DVI_SINGLE_LINK: case SIGNAL_TYPE_DVI_DUAL_LINK: case SIGNAL_TYPE_HDMI_TYPE_A: @@ -181,7 +181,7 @@ static bool program_hpd_filter( return result; } -static bool detect_sink(struct core_link *link, enum dc_connection_type *type) +static bool detect_sink(struct dc_link *link, enum dc_connection_type *type) { uint32_t is_hpd_high = 0; struct gpio *hpd_pin; @@ -306,7 +306,7 @@ static enum signal_type get_basic_signal_type( * @brief * Check whether there is a dongle on DP connector */ -static bool is_dp_sink_present(struct core_link *link) +static bool is_dp_sink_present(struct dc_link *link) { enum gpio_result gpio_result; uint32_t clock_pin = 0; @@ -320,7 +320,7 @@ static bool is_dp_sink_present(struct core_link *link) ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || (connector_id == CONNECTOR_ID_EDP)); - ddc = dal_ddc_service_get_ddc_pin(link->public.ddc); + ddc = dal_ddc_service_get_ddc_pin(link->ddc); if (!ddc) { BREAK_TO_DEBUGGER(); @@ -356,7 +356,7 @@ static bool is_dp_sink_present(struct core_link *link) * @brief * Detect output sink type */ -static enum signal_type link_detect_sink(struct core_link *link) +static enum signal_type link_detect_sink(struct dc_link *link) { enum signal_type result = get_basic_signal_type( link->link_enc->id, link->link_id); @@ -446,18 +446,18 @@ static enum signal_type dp_passive_dongle_detection( audio_support); } -static void link_disconnect_sink(struct core_link *link) +static void link_disconnect_sink(struct dc_link *link) { - if (link->public.local_sink) { - dc_sink_release(link->public.local_sink); - link->public.local_sink = NULL; + if (link->local_sink) { + dc_sink_release(link->local_sink); + link->local_sink = NULL; } link->dpcd_sink_count = 0; } static void detect_dp( - struct core_link *link, + struct dc_link *link, struct display_sink_capability *sink_caps, bool *converter_disable_audio, struct audio_support *audio_support, @@ -473,7 +473,7 @@ static void detect_dp( /* DP active dongles */ if (is_dp_active_dongle(link)) { - link->public.type = dc_connection_active_dongle; + link->type = dc_connection_active_dongle; if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) { /* * active dongle unplug processing for short irq @@ -517,8 +517,8 @@ static void detect_dp( if (dm_helpers_dp_mst_start_top_mgr( link->ctx, - &link->public, boot)) { - link->public.type = dc_connection_mst_branch; + link, boot)) { + link->type = dc_connection_mst_branch; } else { /* MST not supported */ sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; @@ -526,15 +526,14 @@ static void detect_dp( } } else { /* DP passive dongles */ - sink_caps->signal = dp_passive_dongle_detection(link->public.ddc, + sink_caps->signal = dp_passive_dongle_detection(link->ddc, sink_caps, audio_support); } } -bool dc_link_detect(const struct dc_link *dc_link, bool boot) +bool dc_link_detect(struct dc_link *link, bool boot) { - struct core_link *link = DC_LINK_TO_LINK(dc_link); struct dc_sink_init_data sink_init_data = { 0 }; struct display_sink_capability sink_caps = { 0 }; uint8_t i; @@ -546,7 +545,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) struct core_sink *sink = NULL; enum dc_connection_type new_connection_type = dc_connection_none; - if (link->public.connector_signal == SIGNAL_TYPE_VIRTUAL) + if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) return false; if (false == detect_sink(link, &new_connection_type)) { @@ -554,17 +553,17 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) return false; } - if (link->public.connector_signal == SIGNAL_TYPE_EDP && - link->public.local_sink) + if (link->connector_signal == SIGNAL_TYPE_EDP && + link->local_sink) return true; link_disconnect_sink(link); if (new_connection_type != dc_connection_none) { - link->public.type = new_connection_type; + link->type = new_connection_type; /* From Disconnected-to-Connected. */ - switch (link->public.connector_signal) { + switch (link->connector_signal) { case SIGNAL_TYPE_HDMI_TYPE_A: { sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; if (aud_support->hdmi_audio_native) @@ -602,14 +601,14 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) aud_support, boot); /* Active dongle downstream unplug */ - if (link->public.type == dc_connection_active_dongle + if (link->type == dc_connection_active_dongle && link->dpcd_caps.sink_count. bits.SINK_COUNT == 0) return true; - if (link->public.type == dc_connection_mst_branch) { + if (link->type == dc_connection_mst_branch) { LINK_INFO("link=%d, mst branch is now Connected\n", - link->public.link_index); + link->link_index); return false; } @@ -618,7 +617,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) default: DC_ERROR("Invalid connector type! signal:%d\n", - link->public.connector_signal); + link->connector_signal); return false; } /* switch() */ @@ -629,13 +628,13 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) link->dpcd_sink_count = 1; dal_ddc_service_set_transaction_type( - link->public.ddc, + link->ddc, sink_caps.transaction_type); - link->public.aux_mode = dal_ddc_service_is_in_aux_transaction_mode( - link->public.ddc); + link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode( + link->ddc); - sink_init_data.link = &link->public; + sink_init_data.link = link; sink_init_data.sink_signal = sink_caps.signal; dc_sink = dc_sink_create(&sink_init_data); @@ -648,11 +647,11 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) dc_sink->converter_disable_audio = converter_disable_audio; sink = DC_SINK_TO_CORE(dc_sink); - link->public.local_sink = &sink->public; + link->local_sink = &sink->public; edid_status = dm_helpers_read_local_edid( link->ctx, - &link->public, + link, &sink->public); switch (edid_status) { @@ -719,21 +718,21 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) } else { /* From Connected-to-Disconnected. */ - if (link->public.type == dc_connection_mst_branch) { + if (link->type == dc_connection_mst_branch) { LINK_INFO("link=%d, mst branch is now Disconnected\n", - link->public.link_index); - dm_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public); + link->link_index); + dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); link->mst_stream_alloc_table.stream_count = 0; memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations)); } - link->public.type = dc_connection_none; + link->type = dc_connection_none; sink_caps.signal = SIGNAL_TYPE_NONE; } LINK_INFO("link=%d, dc_sink_in=%p is now %s\n", - link->public.link_index, &sink->public, + link->link_index, &sink->public, (sink_caps.signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected")); @@ -741,7 +740,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) } static enum hpd_source_id get_hpd_line( - struct core_link *link) + struct dc_link *link) { struct gpio *hpd; enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN; @@ -779,12 +778,12 @@ static enum hpd_source_id get_hpd_line( return hpd_id; } -static enum channel_id get_ddc_line(struct core_link *link) +static enum channel_id get_ddc_line(struct dc_link *link) { struct ddc *ddc; enum channel_id channel = CHANNEL_ID_UNKNOWN; - ddc = dal_ddc_service_get_ddc_pin(link->public.ddc); + ddc = dal_ddc_service_get_ddc_pin(link->ddc); if (ddc) { switch (dal_ddc_get_line(ddc)) { @@ -887,7 +886,7 @@ static enum transmitter translate_encoder_to_transmitter( } static bool construct( - struct core_link *link, + struct dc_link *link, const struct link_init_data *init_params) { uint8_t i; @@ -899,14 +898,14 @@ static bool construct( struct dc_bios *bios = init_params->dc->ctx->dc_bios; const struct dc_vbios_funcs *bp_funcs = bios->funcs; - link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID; - link->public.irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; link->link_status.dpcd_caps = &link->dpcd_caps; link->dc = init_params->dc; link->ctx = dc_ctx; - link->public.link_index = init_params->link_index; + link->link_index = init_params->link_index; link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); @@ -919,35 +918,35 @@ static bool construct( hpd_gpio = get_hpd_gpio(link); if (hpd_gpio != NULL) - link->public.irq_source_hpd = dal_irq_get_source(hpd_gpio); + link->irq_source_hpd = dal_irq_get_source(hpd_gpio); switch (link->link_id.id) { case CONNECTOR_ID_HDMI_TYPE_A: - link->public.connector_signal = SIGNAL_TYPE_HDMI_TYPE_A; + link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A; break; case CONNECTOR_ID_SINGLE_LINK_DVID: case CONNECTOR_ID_SINGLE_LINK_DVII: - link->public.connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; break; case CONNECTOR_ID_DUAL_LINK_DVID: case CONNECTOR_ID_DUAL_LINK_DVII: - link->public.connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; + link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; break; case CONNECTOR_ID_DISPLAY_PORT: - link->public.connector_signal = SIGNAL_TYPE_DISPLAY_PORT; + link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; if (hpd_gpio != NULL) - link->public.irq_source_hpd_rx = + link->irq_source_hpd_rx = dal_irq_get_rx_source(hpd_gpio); break; case CONNECTOR_ID_EDP: - link->public.connector_signal = SIGNAL_TYPE_EDP; + link->connector_signal = SIGNAL_TYPE_EDP; if (hpd_gpio != NULL) { - link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID; - link->public.irq_source_hpd_rx = + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + link->irq_source_hpd_rx = dal_irq_get_rx_source(hpd_gpio); } break; @@ -966,21 +965,21 @@ static bool construct( LINK_INFO("Connector[%d] description:" "signal %d\n", init_params->connector_index, - link->public.connector_signal); + link->connector_signal); ddc_service_init_data.ctx = link->ctx; ddc_service_init_data.id = link->link_id; ddc_service_init_data.link = link; - link->public.ddc = dal_ddc_service_create(&ddc_service_init_data); + link->ddc = dal_ddc_service_create(&ddc_service_init_data); - if (link->public.ddc == NULL) { + if (link->ddc == NULL) { DC_ERROR("Failed to create ddc_service!\n"); goto ddc_create_fail; } - link->public.ddc_hw_inst = + link->ddc_hw_inst = dal_ddc_get_line( - dal_ddc_service_get_ddc_pin(link->public.ddc)); + dal_ddc_service_get_ddc_pin(link->ddc)); enc_init_data.ctx = dc_ctx; bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder); @@ -988,7 +987,7 @@ static bool construct( enc_init_data.channel = get_ddc_line(link); enc_init_data.hpd_source = get_hpd_line(link); - link->public.hpd_src = enc_init_data.hpd_source; + link->hpd_src = enc_init_data.hpd_source; enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder); @@ -1000,7 +999,7 @@ static bool construct( goto link_enc_create_fail; } - link->public.link_enc_hw_inst = link->link_enc->transmitter; + link->link_enc_hw_inst = link->link_enc->transmitter; for (i = 0; i < 4; i++) { if (BP_RESULT_OK != @@ -1015,10 +1014,10 @@ static bool construct( if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id)) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT - && link->public.connector_signal != SIGNAL_TYPE_RGB) + && link->connector_signal != SIGNAL_TYPE_RGB) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD - && link->public.connector_signal == SIGNAL_TYPE_RGB) + && link->connector_signal == SIGNAL_TYPE_RGB) continue; break; } @@ -1052,7 +1051,7 @@ static bool construct( device_tag_fail: link->link_enc->funcs->destroy(&link->link_enc); link_enc_create_fail: - dal_ddc_service_destroy(&link->public.ddc); + dal_ddc_service_destroy(&link->ddc); ddc_create_fail: create_fail: @@ -1066,9 +1065,9 @@ create_fail: /******************************************************************************* * Public functions ******************************************************************************/ -struct core_link *link_create(const struct link_init_data *init_params) +struct dc_link *link_create(const struct link_init_data *init_params) { - struct core_link *link = + struct dc_link *link = dm_alloc(sizeof(*link)); if (NULL == link) @@ -1086,7 +1085,7 @@ alloc_fail: return NULL; } -void link_destroy(struct core_link **link) +void link_destroy(struct dc_link **link) { destruct(*link); dm_free(*link); @@ -1094,7 +1093,7 @@ void link_destroy(struct core_link **link) } static void dpcd_configure_panel_mode( - struct core_link *link, + struct dc_link *link, enum dp_panel_mode panel_mode) { union dpcd_edp_config edp_config_set; @@ -1139,7 +1138,7 @@ static void dpcd_configure_panel_mode( dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS, "Link: %d eDP panel mode supported: %d " "eDP panel mode enabled: %d \n", - link->public.link_index, + link->link_index, link->dpcd_caps.panel_mode_edp, panel_mode_edp); } @@ -1147,7 +1146,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, @@ -1165,7 +1164,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) struct core_stream *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; struct dc_link_settings link_settings = {0}; enum dp_panel_mode panel_mode; enum dc_link_rate max_link_rate = LINK_RATE_HIGH2; @@ -1224,7 +1223,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) &link_settings, skip_video_pattern, LINK_TRAINING_ATTEMPTS)) { - link->public.cur_link_settings = link_settings; + link->cur_link_settings = link_settings; status = DC_OK; } else @@ -1237,12 +1236,12 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) { - struct core_link *link = pipe_ctx->stream->sink->link; + struct dc_link *link = pipe_ctx->stream->sink->link; /* sink signal type after MST branch is MST. Multiple MST sinks * share one link. Link DP PHY is enable or training only once. */ - if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) + if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) return DC_OK; /* set the sink to MST mode before enabling the link */ @@ -1254,16 +1253,16 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) dal_ddc_service_write_scdc_data( - stream->sink->link->public.ddc, + stream->sink->link->ddc, stream->phy_pix_clk, stream->public.timing.flags.LTE_340MCSC_SCRAMBLE); - memset(&stream->sink->link->public.cur_link_settings, 0, + memset(&stream->sink->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); display_color_depth = stream->public.timing.display_color_depth; @@ -1279,7 +1278,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) stream->phy_pix_clk); if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) - dal_ddc_service_read_scdc_data(link->public.ddc); + dal_ddc_service_read_scdc_data(link->ddc); } /****************************enable_link***********************************/ @@ -1321,7 +1320,7 @@ static enum dc_status enable_link(struct pipe_ctx *pipe_ctx) return status; } -static void disable_link(struct core_link *link, enum signal_type signal) +static void disable_link(struct dc_link *link, enum signal_type signal) { /* * TODO: implement call for dp_set_hw_test_pattern @@ -1345,7 +1344,7 @@ static void disable_link(struct core_link *link, enum signal_type signal) enum dc_status dc_link_validate_mode_timing( const struct core_stream *stream, - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing) { uint32_t max_pix_clk = stream->sink->public.dongle_max_pix_clk; @@ -1353,7 +1352,7 @@ enum dc_status dc_link_validate_mode_timing( /* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle */ - if (link->public.remote_sinks[0]) + if (link->remote_sinks[0]) return DC_OK; if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk) @@ -1376,10 +1375,9 @@ enum dc_status dc_link_validate_mode_timing( } -bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, +bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct core_stream *core_stream = NULL; struct abm *abm = core_dc->res_pool->abm; @@ -1392,7 +1390,7 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, dm_logger_write(link->ctx->logger, LOG_BACKLIGHT, "New Backlight level: %d (0x%X)\n", level, level); - if (dc_is_embedded_signal(dc_link->connector_signal)) { + if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { core_stream = DC_STREAM_TO_CORE(stream); for (i = 0; i < MAX_PIPES; i++) { @@ -1419,9 +1417,8 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, } -bool dc_link_set_abm_disable(const struct dc_link *dc_link) +bool dc_link_set_abm_disable(const struct dc_link *link) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct abm *abm = core_dc->res_pool->abm; @@ -1434,11 +1431,9 @@ bool dc_link_set_abm_disable(const struct dc_link *dc_link) } -bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) +bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1447,11 +1442,9 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) return true; } -bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state) +bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1460,20 +1453,18 @@ bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state) return true; } -bool dc_link_setup_psr(const struct dc_link *dc_link, +bool dc_link_setup_psr(struct dc_link *link, const struct dc_stream *stream, struct psr_config *psr_config, struct psr_context *psr_context) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; - if (dc_link != NULL && + if (link != NULL && dmcu != NULL) { /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; @@ -1501,12 +1492,12 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, dm_helpers_dp_write_dpcd( link->ctx, - dc_link, + link, 368, &psr_configuration.raw, sizeof(psr_configuration.raw)); - psr_context->channel = link->public.ddc->ddc_pin->hw_info.ddc_channel; + psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; psr_context->transmitterId = link->link_enc->transmitter; psr_context->engineId = link->link_enc->preferred_engine; @@ -1584,23 +1575,21 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, } -const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link) +const struct dc_link_status *dc_link_get_status(const struct dc_link *link) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - return &link->link_status; } -void core_link_resume(struct core_link *link) +void core_link_resume(struct dc_link *link) { - if (link->public.connector_signal != SIGNAL_TYPE_VIRTUAL) + if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) program_hpd_filter(link); } static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream) { struct dc_link_settings *link_settings = - &stream->sink->link->public.cur_link_settings; + &stream->sink->link->cur_link_settings; uint32_t link_rate_in_mbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ; struct fixed31_32 mbps = dal_fixed31_32_from_int( @@ -1653,7 +1642,7 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) } static void update_mst_stream_alloc_table( - struct core_link *link, + struct dc_link *link, struct stream_encoder *stream_enc, const struct dp_mst_stream_allocation_table *proposed_table) { @@ -1668,7 +1657,7 @@ static void update_mst_stream_alloc_table( ASSERT(proposed_table->stream_count - link->mst_stream_alloc_table.stream_count < 2); - /* copy proposed_table to core_link, add stream encoder */ + /* copy proposed_table to link, add stream encoder */ for (i = 0; i < proposed_table->stream_count; i++) { for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { @@ -1707,7 +1696,7 @@ static void update_mst_stream_alloc_table( static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; @@ -1789,13 +1778,13 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0); uint8_t i; - bool mst_mode = (link->public.type == dc_connection_mst_branch); + bool mst_mode = (link->type == dc_connection_mst_branch); /* deallocate_mst_payload is called before disable link. When mode or * disable/enable monitor, new stream is created which is not in link @@ -1875,7 +1864,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) if (status != DC_OK) { dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_WARNING, "enabling link %u failed: %d\n", - pipe_ctx->stream->sink->link->public.link_index, + pipe_ctx->stream->sink->link->link_index, status); /* Abort stream enable *unless* the failure was due to diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index 2f5a89c5b063..d09e539397ea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -354,7 +354,7 @@ static uint32_t defer_delay_converter_wa( struct ddc_service *ddc, uint32_t defer_delay) { - struct core_link *link = ddc->link; + struct dc_link *link = ddc->link; if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 && !memcmp(link->dpcd_caps.branch_dev_name, @@ -423,7 +423,7 @@ static bool i2c_read( return dm_helpers_submit_i2c( ddc->ctx, - &ddc->link->public, + ddc->link, &command); } @@ -624,7 +624,7 @@ bool dal_ddc_service_query_ddc_data( ret = dm_helpers_submit_i2c( ddc->ctx, - &ddc->link->public, + ddc->link, &command); dal_ddc_i2c_payloads_destroy(&payloads); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index e90b3ebc8347..c7b400786121 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -34,7 +34,7 @@ enum { }; static void wait_for_training_aux_rd_interval( - struct core_link* link, + struct dc_link *link, uint32_t default_wait_in_micro_secs) { union training_aux_rd_interval training_rd_interval; @@ -63,7 +63,7 @@ static void wait_for_training_aux_rd_interval( } static void dpcd_set_training_pattern( - struct core_link* link, + struct dc_link *link, union dpcd_training_pattern dpcd_pattern) { core_link_write_dpcd( @@ -80,7 +80,7 @@ static void dpcd_set_training_pattern( } static void dpcd_set_link_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *lt_settings) { uint8_t rate = (uint8_t) @@ -123,7 +123,7 @@ static void dpcd_set_link_settings( static enum dpcd_training_patterns hw_training_pattern_to_dpcd_training_pattern( - struct core_link* link, + struct dc_link *link, enum hw_dp_training_pattern pattern) { enum dpcd_training_patterns dpcd_tr_pattern = @@ -155,7 +155,7 @@ static enum dpcd_training_patterns } static void dpcd_set_lt_pattern_and_lane_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *lt_settings, enum hw_dp_training_pattern pattern) { @@ -246,7 +246,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( dpcd_lt_buffer, size_in_bytes + sizeof(dpcd_pattern.raw) ); - link->public.cur_lane_setting = lt_settings->lane_settings[0]; + link->cur_lane_setting = lt_settings->lane_settings[0]; } static bool is_cr_done(enum dc_lane_count ln_count, @@ -419,7 +419,7 @@ static void find_max_drive_settings( } static void get_lane_status_and_drive_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *link_training_setting, union lane_status *ln_status, union lane_align_status_updated *ln_status_updated, @@ -500,7 +500,7 @@ static void get_lane_status_and_drive_settings( } static void dpcd_set_lane_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *link_training_setting) { union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}}; @@ -560,7 +560,7 @@ static void dpcd_set_lane_settings( dpcd_lane[0].bits.MAX_SWING_REACHED, dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); - link->public.cur_lane_setting = link_training_setting->lane_settings[0]; + link->cur_lane_setting = link_training_setting->lane_settings[0]; } @@ -580,19 +580,18 @@ static bool is_max_vs_reached( } void dc_link_dp_set_drive_settings( - const struct dc_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { - struct core_link *core_link = DC_LINK_TO_CORE(link); /* program ASIC PHY settings*/ - dp_set_hw_lane_settings(core_link, lt_settings); + dp_set_hw_lane_settings(link, lt_settings); /* Notify DP sink the PHY settings from source */ - dpcd_set_lane_settings(core_link, lt_settings); + dpcd_set_lane_settings(link, lt_settings); } static bool perform_post_lt_adj_req_sequence( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { enum dc_lane_count lane_count = @@ -656,7 +655,7 @@ static bool perform_post_lt_adj_req_sequence( update_drive_settings( lt_settings,req_settings); - dc_link_dp_set_drive_settings(&link->public, + dc_link_dp_set_drive_settings(link, lt_settings); break; } @@ -682,7 +681,7 @@ static bool perform_post_lt_adj_req_sequence( } -static enum hw_dp_training_pattern get_supported_tp(struct core_link *link) +static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link) { enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2; struct encoder_feature_support *features = &link->link_enc->features; @@ -706,7 +705,7 @@ static enum hw_dp_training_pattern get_supported_tp(struct core_link *link) } static enum link_training_result perform_channel_equalization_sequence( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { struct link_training_settings req_settings; @@ -768,7 +767,7 @@ static enum link_training_result perform_channel_equalization_sequence( } static bool perform_clock_recovery_sequence( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { uint32_t retries_cr; @@ -877,7 +876,7 @@ static bool perform_clock_recovery_sequence( } static inline bool perform_link_training_int( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings, bool status) { @@ -923,7 +922,6 @@ enum link_training_result dc_link_dp_perform_link_training( bool skip_video_pattern) { enum link_training_result status = LINK_TRAINING_SUCCESS; - struct core_link *core_link = DC_LINK_TO_CORE(link); char *link_rate = "Unknown"; struct link_training_settings lt_settings; @@ -945,19 +943,19 @@ enum link_training_result dc_link_dp_perform_link_training( lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; /* 1. set link rate, lane count and spread*/ - dpcd_set_link_settings(core_link, <_settings); + dpcd_set_link_settings(link, <_settings); /* 2. perform link training (set link training done * to false is done as well)*/ - if (!perform_clock_recovery_sequence(core_link, <_settings)) { + if (!perform_clock_recovery_sequence(link, <_settings)) { status = LINK_TRAINING_CR_FAIL; } else { - status = perform_channel_equalization_sequence(core_link, + status = perform_channel_equalization_sequence(link, <_settings); } if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) { - if (!perform_link_training_int(core_link, + if (!perform_link_training_int(link, <_settings, status == LINK_TRAINING_SUCCESS)) { /* the next link training setting in this case @@ -990,7 +988,7 @@ enum link_training_result dc_link_dp_perform_link_training( } /* Connectivity log: link training */ - CONN_MSG_LT(core_link, "%sx%d %s VS=%d, PE=%d", + CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d", link_rate, lt_settings.link_settings.lane_count, (status == LINK_TRAINING_SUCCESS) ? "pass" : @@ -1004,7 +1002,7 @@ enum link_training_result dc_link_dp_perform_link_training( bool perform_link_training_with_retries( - struct core_link *link, + struct dc_link *link, const struct dc_link_settings *link_setting, bool skip_video_pattern, int attempts) @@ -1015,7 +1013,7 @@ bool perform_link_training_with_retries( for (j = 0; j < attempts; ++j) { if (dc_link_dp_perform_link_training( - &link->public, + link, link_setting, skip_video_pattern) == LINK_TRAINING_SUCCESS) return true; @@ -1027,7 +1025,7 @@ bool perform_link_training_with_retries( return false; } -static struct dc_link_settings get_max_link_cap(struct core_link *link) +static struct dc_link_settings get_max_link_cap(struct dc_link *link) { /* Set Default link settings */ struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, @@ -1041,21 +1039,21 @@ static struct dc_link_settings get_max_link_cap(struct core_link *link) max_link_cap.link_rate = LINK_RATE_HIGH3; /* Lower link settings based on sink's link cap */ - if (link->public.reported_link_cap.lane_count < max_link_cap.lane_count) + if (link->reported_link_cap.lane_count < max_link_cap.lane_count) max_link_cap.lane_count = - link->public.reported_link_cap.lane_count; - if (link->public.reported_link_cap.link_rate < max_link_cap.link_rate) + link->reported_link_cap.lane_count; + if (link->reported_link_cap.link_rate < max_link_cap.link_rate) max_link_cap.link_rate = - link->public.reported_link_cap.link_rate; - if (link->public.reported_link_cap.link_spread < + link->reported_link_cap.link_rate; + if (link->reported_link_cap.link_spread < max_link_cap.link_spread) max_link_cap.link_spread = - link->public.reported_link_cap.link_spread; + link->reported_link_cap.link_spread; return max_link_cap; } bool dp_hbr_verify_link_cap( - struct core_link *link, + struct dc_link *link, struct dc_link_settings *known_limit_link_setting) { struct dc_link_settings max_link_cap = {0}; @@ -1080,7 +1078,7 @@ bool dp_hbr_verify_link_cap( * find the physical link capability */ /* disable PHY done possible by BIOS, will be done by driver itself */ - dp_disable_link_phy(link, link->public.connector_signal); + dp_disable_link_phy(link, link->connector_signal); dp_cs = link->dc->res_pool->dp_clock_source; @@ -1109,7 +1107,7 @@ bool dp_hbr_verify_link_cap( dp_enable_link_phy( link, - link->public.connector_signal, + link->connector_signal, dp_cs_id, cur); @@ -1117,7 +1115,7 @@ bool dp_hbr_verify_link_cap( success = true; else { status = dc_link_dp_perform_link_training( - &link->public, + link, cur, skip_video_pattern); if (status == LINK_TRAINING_SUCCESS) @@ -1125,13 +1123,13 @@ bool dp_hbr_verify_link_cap( } if (success) - link->public.verified_link_cap = *cur; + link->verified_link_cap = *cur; /* always disable the link before trying another * setting or before returning we'll enable it later * based on the actual mode we're driving */ - dp_disable_link_phy(link, link->public.connector_signal); + dp_disable_link_phy(link, link->connector_signal); } while (!success && decide_fallback_link_setting( initial_link_settings, cur, status)); @@ -1142,14 +1140,14 @@ bool dp_hbr_verify_link_cap( /* If all LT fails for all settings, * set verified = failed safe (1 lane low) */ - link->public.verified_link_cap.lane_count = LANE_COUNT_ONE; - link->public.verified_link_cap.link_rate = LINK_RATE_LOW; + link->verified_link_cap.lane_count = LANE_COUNT_ONE; + link->verified_link_cap.link_rate = LINK_RATE_LOW; - link->public.verified_link_cap.link_spread = + link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED; } - link->public.max_link_setting = link->public.verified_link_cap; + link->max_link_setting = link->verified_link_cap; return success; } @@ -1391,7 +1389,7 @@ static uint32_t bandwidth_in_kbps_from_link_settings( } bool dp_validate_mode_timing( - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing) { uint32_t req_bw; @@ -1406,12 +1404,12 @@ bool dp_validate_mode_timing( return true; /* We always use verified link settings */ - link_setting = &link->public.verified_link_cap; + link_setting = &link->verified_link_cap; /* TODO: DYNAMIC_VALIDATION needs to be implemented */ /*if (flags.DYNAMIC_VALIDATION == 1 && - link->public.verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) - link_setting = &link->public.verified_link_cap; + link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) + link_setting = &link->verified_link_cap; */ req_bw = bandwidth_in_kbps_from_timing(timing); @@ -1444,7 +1442,7 @@ void decide_link_settings(struct core_stream *stream, LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED}; struct dc_link_settings current_link_setting = initial_link_setting; - struct core_link* link; + struct dc_link *link; uint32_t req_bw; uint32_t link_bw; @@ -1456,11 +1454,11 @@ void decide_link_settings(struct core_stream *stream, /* if preferred is specified through AMDDP, use it, if it's enough * to drive the mode */ - if (link->public.preferred_link_setting.lane_count != + if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && - link->public.preferred_link_setting.link_rate != + link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) { - *link_setting = link->public.preferred_link_setting; + *link_setting = link->preferred_link_setting; return; } @@ -1469,7 +1467,7 @@ void decide_link_settings(struct core_stream *stream, * 2. could support the b/w requested by the timing */ while (current_link_setting.link_rate <= - link->public.max_link_setting.link_rate) { + link->max_link_setting.link_rate) { link_bw = bandwidth_in_kbps_from_link_settings( ¤t_link_setting); if (req_bw <= link_bw) { @@ -1478,7 +1476,7 @@ void decide_link_settings(struct core_stream *stream, } if (current_link_setting.lane_count < - link->public.max_link_setting.lane_count) { + link->max_link_setting.lane_count) { current_link_setting.lane_count = increase_lane_count( current_link_setting.lane_count); @@ -1492,16 +1490,15 @@ void decide_link_settings(struct core_stream *stream, } BREAK_TO_DEBUGGER(); - ASSERT(link->public.verified_link_cap.lane_count != - LANE_COUNT_UNKNOWN); + ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN); - *link_setting = link->public.verified_link_cap; + *link_setting = link->verified_link_cap; } /*************************Short Pulse IRQ***************************/ static bool hpd_rx_irq_check_link_loss_status( - struct core_link *link, + struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data) { uint8_t irq_reg_rx_power_state; @@ -1514,7 +1511,7 @@ static bool hpd_rx_irq_check_link_loss_status( sink_status_changed = false; return_code = false; - if (link->public.cur_link_settings.lane_count == 0) + if (link->cur_link_settings.lane_count == 0) return return_code; /*1. Check that we can handle interrupt: Not in FS DOS, * Not in "Display Timeout" state, Link is trained. @@ -1538,7 +1535,7 @@ static bool hpd_rx_irq_check_link_loss_status( /*parse lane status*/ for (lane = 0; - lane < link->public.cur_link_settings.lane_count; + lane < link->cur_link_settings.lane_count; lane++) { /* check status of lanes 0,1 @@ -1577,7 +1574,7 @@ static bool hpd_rx_irq_check_link_loss_status( } static enum dc_status read_hpd_rx_irq_data( - struct core_link *link, + struct dc_link *link, union hpd_irq_data *irq_data) { /* The HW reads 16 bytes from 200h on HPD, @@ -1593,7 +1590,7 @@ static enum dc_status read_hpd_rx_irq_data( sizeof(union hpd_irq_data)); } -static bool allow_hpd_rx_irq(const struct core_link *link) +static bool allow_hpd_rx_irq(const struct dc_link *link) { /* * Don't handle RX IRQ unless one of following is met: @@ -1602,15 +1599,15 @@ static bool allow_hpd_rx_irq(const struct core_link *link) * 3) We know we're dealing with an active dongle */ - if ((link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || - (link->public.type == dc_connection_mst_branch) || + if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || + (link->type == dc_connection_mst_branch) || is_dp_active_dongle(link)) return true; return false; } -static bool handle_hpd_irq_psr_sink(const struct core_link *link) +static bool handle_hpd_irq_psr_sink(const struct dc_link *link) { union dpcd_psr_configuration psr_configuration; @@ -1619,7 +1616,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) dm_helpers_dp_read_dpcd( link->ctx, - &link->public, + link, 368,/*DpcdAddress_PSR_Enable_Cfg*/ &psr_configuration.raw, sizeof(psr_configuration.raw)); @@ -1632,7 +1629,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) dm_helpers_dp_read_dpcd( link->ctx, - &link->public, + link, 0x2006, /*DpcdAddress_PSR_Error_Status*/ (unsigned char *) dpcdbuf, sizeof(dpcdbuf)); @@ -1647,14 +1644,14 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) /* Acknowledge and clear error bits */ dm_helpers_dp_write_dpcd( link->ctx, - &link->public, + link, 8198,/*DpcdAddress_PSR_Error_Status*/ &psr_error_status.raw, sizeof(psr_error_status.raw)); /* PSR error, disable and re-enable PSR */ - dc_link_set_psr_enable(&link->public, false); - dc_link_set_psr_enable(&link->public, true); + dc_link_set_psr_enable(link, false); + dc_link_set_psr_enable(link, true); return true; } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS == @@ -1670,7 +1667,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) return false; } -static void dp_test_send_link_training(struct core_link *link) +static void dp_test_send_link_training(struct dc_link *link) { struct dc_link_settings link_settings = {0}; @@ -1686,13 +1683,13 @@ static void dp_test_send_link_training(struct core_link *link) 1); /* Set preferred link settings */ - link->public.verified_link_cap.lane_count = link_settings.lane_count; - link->public.verified_link_cap.link_rate = link_settings.link_rate; + link->verified_link_cap.lane_count = link_settings.lane_count; + link->verified_link_cap.link_rate = link_settings.link_rate; dp_retrain_link_dp_test(link, &link_settings, false); } -static void dp_test_send_phy_test_pattern(struct core_link *link) +static void dp_test_send_phy_test_pattern(struct dc_link *link) { union phy_test_pattern dpcd_test_pattern; union lane_adjust dpcd_lane_adjustment[2]; @@ -1771,10 +1768,10 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) sizeof(test_80_bit_pattern)); /* prepare link training settings */ - link_settings.link = link->public.cur_link_settings; + link_settings.link = link->cur_link_settings; for (lane = 0; lane < - (unsigned int)(link->public.cur_link_settings.lane_count); + (unsigned int)(link->cur_link_settings.lane_count); lane++) { dpcd_lane_adjust.raw = get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane); @@ -1802,7 +1799,7 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) * forward request to DS */ dc_link_dp_set_test_pattern( - &link->public, + link, test_pattern, &link_training_settings, test_80_bit_pattern, @@ -1810,7 +1807,7 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1); } -static void dp_test_send_link_test_pattern(struct core_link *link) +static void dp_test_send_link_test_pattern(struct dc_link *link) { union link_test_pattern dpcd_test_pattern; union test_misc dpcd_test_params; @@ -1850,14 +1847,14 @@ static void dp_test_send_link_test_pattern(struct core_link *link) } dc_link_dp_set_test_pattern( - &link->public, + link, test_pattern, NULL, NULL, 0); } -static void handle_automated_test(struct core_link *link) +static void handle_automated_test(struct dc_link *link) { union test_request test_request; union test_response test_response; @@ -1904,9 +1901,8 @@ static void handle_automated_test(struct core_link *link) sizeof(test_response)); } -bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data *out_hpd_irq_dpcd_data) +bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data) { - struct core_link *link = DC_LINK_TO_LINK(dc_link); union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}}; union device_service_irq device_service_clear = { { 0 } }; enum dc_status result = DDC_RESULT_UNKNOWN; @@ -1917,7 +1913,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, "%s: Got short pulse HPD on link %d\n", - __func__, link->public.link_index); + __func__, link->link_index); /* All the "handle_hpd_irq_xxx()" methods @@ -1951,7 +1947,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data if (!allow_hpd_rx_irq(link)) { dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, "%s: skipping HPD handling on %d\n", - __func__, link->public.link_index); + __func__, link->link_index); return false; } @@ -1984,13 +1980,13 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data "Status: "); perform_link_training_with_retries(link, - &link->public.cur_link_settings, + &link->cur_link_settings, true, LINK_TRAINING_ATTEMPTS); status = false; } - if (link->public.type == dc_connection_active_dongle && + if (link->type == dc_connection_active_dongle && hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT != link->dpcd_sink_count) status = true; @@ -2010,7 +2006,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data } /*query dpcd for version and mst cap addresses*/ -bool is_mst_supported(struct core_link *link) +bool is_mst_supported(struct dc_link *link) { bool mst = false; enum dc_status st = DC_OK; @@ -2034,7 +2030,7 @@ bool is_mst_supported(struct core_link *link) } -bool is_dp_active_dongle(const struct core_link *link) +bool is_dp_active_dongle(const struct dc_link *link) { enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type; @@ -2044,14 +2040,14 @@ bool is_dp_active_dongle(const struct core_link *link) } static void get_active_converter_info( - uint8_t data, struct core_link *link) + uint8_t data, struct dc_link *link) { union dp_downstream_port_present ds_port = { .byte = data }; /* decode converter info*/ if (!ds_port.fields.PORT_PRESENT) { link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; - ddc_service_set_dongle_type(link->public.ddc, + ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); return; } @@ -2121,7 +2117,7 @@ static void get_active_converter_info( } } - ddc_service_set_dongle_type(link->public.ddc, link->dpcd_caps.dongle_type); + ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); { struct dp_device_vendor_id dp_id; @@ -2158,7 +2154,7 @@ static void get_active_converter_info( } } -static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data, +static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, int length) { int retry = 0; @@ -2199,7 +2195,7 @@ static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data, link->wa_flags.dp_keep_receiver_powered = false; } -static void retrieve_link_cap(struct core_link *link) +static void retrieve_link_cap(struct dc_link *link) { uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1]; @@ -2253,11 +2249,11 @@ static void retrieve_link_cap(struct core_link *link) link->dpcd_caps.max_down_spread.raw = dpcd_data[ DP_MAX_DOWNSPREAD - DP_DPCD_REV]; - link->public.reported_link_cap.lane_count = + link->reported_link_cap.lane_count = link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; - link->public.reported_link_cap.link_rate = dpcd_data[ + link->reported_link_cap.link_rate = dpcd_data[ DP_MAX_LINK_RATE - DP_DPCD_REV]; - link->public.reported_link_cap.link_spread = + link->reported_link_cap.link_spread = link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; @@ -2266,8 +2262,8 @@ static void retrieve_link_cap(struct core_link *link) link->dpcd_caps.panel_mode_edp = edp_config_cap.bits.ALT_SCRAMBLER_RESET; - link->public.test_pattern_enabled = false; - link->public.compliance_test_state.raw = 0; + link->test_pattern_enabled = false; + link->compliance_test_state.raw = 0; /* read sink count */ core_link_read_dpcd(link, @@ -2279,7 +2275,7 @@ static void retrieve_link_cap(struct core_link *link) CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); } -void detect_dp_sink_caps(struct core_link *link) +void detect_dp_sink_caps(struct dc_link *link) { retrieve_link_cap(link); @@ -2291,18 +2287,17 @@ void detect_dp_sink_caps(struct core_link *link) */ if (is_mst_supported(link)) { - link->public.verified_link_cap = link->public.reported_link_cap; + link->verified_link_cap = link->reported_link_cap; } else { dp_hbr_verify_link_cap(link, - &link->public.reported_link_cap); + &link->reported_link_cap); } /* TODO save sink caps in link->sink */ } void dc_link_dp_enable_hpd(const struct dc_link *link) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - struct link_encoder *encoder = core_link->link_enc; + struct link_encoder *encoder = link->link_enc; if (encoder != NULL && encoder->funcs->enable_hpd != NULL) encoder->funcs->enable_hpd(encoder); @@ -2310,8 +2305,7 @@ void dc_link_dp_enable_hpd(const struct dc_link *link) void dc_link_dp_disable_hpd(const struct dc_link *link) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - struct link_encoder *encoder = core_link->link_enc; + struct link_encoder *encoder = link->link_enc; if (encoder != NULL && encoder->funcs->enable_hpd != NULL) encoder->funcs->disable_hpd(encoder); @@ -2327,7 +2321,7 @@ static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern) return false; } -static void set_crtc_test_pattern(struct core_link *link, +static void set_crtc_test_pattern(struct dc_link *link, struct pipe_ctx *pipe_ctx, enum dp_test_pattern test_pattern) { @@ -2402,15 +2396,13 @@ static void set_crtc_test_pattern(struct core_link *link, } bool dc_link_dp_set_test_pattern( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, unsigned int cust_pattern_size) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - struct pipe_ctx *pipes = - core_link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; struct pipe_ctx pipe_ctx = pipes[0]; unsigned int lane; unsigned int i; @@ -2421,7 +2413,7 @@ bool dc_link_dp_set_test_pattern( memset(&training_pattern, 0, sizeof(training_pattern)); for (i = 0; i < MAX_PIPES; i++) { - if (pipes[i].stream->sink->link == core_link) { + if (pipes[i].stream->sink->link == link) { pipe_ctx = pipes[i]; break; } @@ -2431,24 +2423,24 @@ bool dc_link_dp_set_test_pattern( * is VideoMode Reset DP Phy Test Pattern if it is currently running * and request is VideoMode */ - if (core_link->public.test_pattern_enabled && test_pattern == + if (link->test_pattern_enabled && test_pattern == DP_TEST_PATTERN_VIDEO_MODE) { /* Set CRTC Test Pattern */ - set_crtc_test_pattern(core_link, &pipe_ctx, test_pattern); - dp_set_hw_test_pattern(core_link, test_pattern, + set_crtc_test_pattern(link, &pipe_ctx, test_pattern); + dp_set_hw_test_pattern(link, test_pattern, (uint8_t *)p_custom_pattern, (uint32_t)cust_pattern_size); /* Unblank Stream */ - core_link->dc->hwss.unblank_stream( + link->dc->hwss.unblank_stream( &pipe_ctx, - &core_link->public.verified_link_cap); + &link->verified_link_cap); /* TODO:m_pHwss->MuteAudioEndpoint * (pPathMode->pDisplayPath, false); */ /* Reset Test Pattern state */ - core_link->public.test_pattern_enabled = false; + link->test_pattern_enabled = false; return true; } @@ -2457,8 +2449,8 @@ bool dc_link_dp_set_test_pattern( if (is_dp_phy_pattern(test_pattern)) { /* Set DPCD Lane Settings before running test pattern */ if (p_link_settings != NULL) { - dp_set_hw_lane_settings(core_link, p_link_settings); - dpcd_set_lane_settings(core_link, p_link_settings); + dp_set_hw_lane_settings(link, p_link_settings); + dpcd_set_lane_settings(link, p_link_settings); } /* Blank stream if running test pattern */ @@ -2471,15 +2463,15 @@ bool dc_link_dp_set_test_pattern( pipes->stream_enc->funcs->dp_blank(pipe_ctx.stream_enc); } - dp_set_hw_test_pattern(core_link, test_pattern, + dp_set_hw_test_pattern(link, test_pattern, (uint8_t *)p_custom_pattern, (uint32_t)cust_pattern_size); if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { /* Set Test Pattern state */ - core_link->public.test_pattern_enabled = true; + link->test_pattern_enabled = true; if (p_link_settings != NULL) - dpcd_set_link_settings(core_link, + dpcd_set_link_settings(link, p_link_settings); } @@ -2516,7 +2508,7 @@ bool dc_link_dp_set_test_pattern( /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/) return false; - if (core_link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { + if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { /* tell receiver that we are sending qualification * pattern DP 1.2 or later - DP receiver's link quality * pattern is set using DPCD LINK_QUAL_LANEx_SET @@ -2526,12 +2518,12 @@ bool dc_link_dp_set_test_pattern( link_qual_pattern[lane] = (unsigned char)(pattern); - core_link_write_dpcd(core_link, + core_link_write_dpcd(link, DP_LINK_QUAL_LANE0_SET, link_qual_pattern, sizeof(link_qual_pattern)); - } else if (core_link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 || - core_link->dpcd_caps.dpcd_rev.raw == 0) { + } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 || + link->dpcd_caps.dpcd_rev.raw == 0) { /* tell receiver that we are sending qualification * pattern DP 1.1a or earlier - DP receiver's link * quality pattern is set using @@ -2539,27 +2531,25 @@ bool dc_link_dp_set_test_pattern( * register (0x102). We will use v_1.3 when we are * setting test pattern for DP 1.1. */ - core_link_read_dpcd(core_link, - DP_TRAINING_PATTERN_SET, - &training_pattern.raw, - sizeof(training_pattern)); + core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET, + &training_pattern.raw, + sizeof(training_pattern)); training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern; - core_link_write_dpcd(core_link, - DP_TRAINING_PATTERN_SET, - &training_pattern.raw, - sizeof(training_pattern)); + core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET, + &training_pattern.raw, + sizeof(training_pattern)); } } else { /* CRTC Patterns */ - set_crtc_test_pattern(core_link, &pipe_ctx, test_pattern); + set_crtc_test_pattern(link, &pipe_ctx, test_pattern); /* Set Test Pattern state */ - core_link->public.test_pattern_enabled = true; + link->test_pattern_enabled = true; } return true; } -void dp_enable_mst_on_sink(struct core_link *link, bool enable) +void dp_enable_mst_on_sink(struct dc_link *link, bool enable) { unsigned char mstmCntl; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 0092e70b9efd..aac2420caefa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -16,13 +16,13 @@ #include "dpcd_defs.h" enum dc_status core_link_read_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, uint8_t *data, uint32_t size) { if (!dm_helpers_dp_read_dpcd(link->ctx, - &link->public, + link, address, data, size)) return DC_ERROR_UNEXPECTED; @@ -30,20 +30,20 @@ enum dc_status core_link_read_dpcd( } enum dc_status core_link_write_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, const uint8_t *data, uint32_t size) { if (!dm_helpers_dp_write_dpcd(link->ctx, - &link->public, + link, address, data, size)) return DC_ERROR_UNEXPECTED; return DC_OK; } -void dp_receiver_power_ctrl(struct core_link *link, bool on) +void dp_receiver_power_ctrl(struct dc_link *link, bool on) { uint8_t state; @@ -54,7 +54,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on) } void dp_enable_link_phy( - struct core_link *link, + struct dc_link *link, enum signal_type signal, enum clock_source_id clock_source, const struct dc_link_settings *link_settings) @@ -107,7 +107,7 @@ void dp_enable_link_phy( dp_receiver_power_ctrl(link, true); } -void dp_disable_link_phy(struct core_link *link, enum signal_type signal) +void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) { if (!link->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(link, false); @@ -120,11 +120,11 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal) link->link_enc->funcs->disable_output(link->link_enc, signal); /* Clear current link setting.*/ - memset(&link->public.cur_link_settings, 0, - sizeof(link->public.cur_link_settings)); + memset(&link->cur_link_settings, 0, + sizeof(link->cur_link_settings)); } -void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal) +void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal) { /* MST disable link only when no stream use the link */ if (link->mst_stream_alloc_table.stream_count > 0) @@ -137,7 +137,7 @@ void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal) } bool dp_set_hw_training_pattern( - struct core_link *link, + struct dc_link *link, enum hw_dp_training_pattern pattern) { enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; @@ -165,7 +165,7 @@ bool dp_set_hw_training_pattern( } void dp_set_hw_lane_settings( - struct core_link *link, + struct dc_link *link, const struct link_training_settings *link_settings) { struct link_encoder *encoder = link->link_enc; @@ -174,13 +174,13 @@ void dp_set_hw_lane_settings( encoder->funcs->dp_set_lane_settings(encoder, link_settings); } -enum dp_panel_mode dp_get_panel_mode(struct core_link *link) +enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) { /* We need to explicitly check that connector * is not DP. Some Travis_VGA get reported * by video bios as DP. */ - if (link->public.connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { + if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { switch (link->dpcd_caps.branch_dev_id) { case DP_BRANCH_DEVICE_ID_2: @@ -215,7 +215,7 @@ enum dp_panel_mode dp_get_panel_mode(struct core_link *link) } void dp_set_hw_test_pattern( - struct core_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, uint8_t *custom_pattern, uint32_t custom_pattern_size) @@ -231,7 +231,7 @@ void dp_set_hw_test_pattern( encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param); } -void dp_retrain_link_dp_test(struct core_link *link, +void dp_retrain_link_dp_test(struct dc_link *link, struct dc_link_settings *link_setting, bool skip_video_pattern) { @@ -263,8 +263,8 @@ void dp_retrain_link_dp_test(struct core_link *link, SIGNAL_TYPE_DISPLAY_PORT); /* Clear current link setting. */ - memset(&link->public.cur_link_settings, 0, - sizeof(link->public.cur_link_settings)); + memset(&link->cur_link_settings, 0, + sizeof(link->cur_link_settings)); link->link_enc->funcs->enable_dp_output( link->link_enc, @@ -274,11 +274,11 @@ void dp_retrain_link_dp_test(struct core_link *link, dp_receiver_power_ctrl(link, true); dc_link_dp_perform_link_training( - &link->public, + link, link_setting, skip_video_pattern); - link->public.cur_link_settings = *link_setting; + link->cur_link_settings = *link_setting; link->dc->hwss.enable_stream(&pipes[i]); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 303c95432d5b..7a3d090f8465 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1269,7 +1269,7 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link( { int i; int j = -1; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; for (i = 0; i < pool->stream_enc_count; i++) { if (!res_ctx->is_stream_enc_acquired[i] && @@ -1322,9 +1322,7 @@ static void update_stream_signal(struct core_stream *stream) const struct dc_sink *dc_sink = stream->public.sink; if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) - stream->signal = - stream->sink->link-> - public.connector_signal; + stream->signal = stream->sink->link->connector_signal; else stream->signal = dc_sink->sink_signal; } else { @@ -1380,7 +1378,7 @@ static struct core_stream *find_pll_sharable_stream( if (resource_are_streams_timing_synchronizable( stream_needs_pll, stream_has_pll) && !dc_is_dp_signal(stream_has_pll->signal) - && stream_has_pll->sink->link->public.connector_signal + && stream_has_pll->sink->link->connector_signal != SIGNAL_TYPE_VIRTUAL) return stream_has_pll; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index da9955675fbf..7f0ba7267682 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -54,15 +54,14 @@ static void destruct(struct sink *sink) static bool construct(struct sink *sink, const struct dc_sink_init_data *init_params) { - struct core_link *core_link = DC_LINK_TO_LINK(init_params->link); + struct dc_link *link = init_params->link; - if (!core_link) { + if (!link) return false; - } sink->protected.public.sink_signal = init_params->sink_signal; - sink->protected.link = core_link; - sink->protected.ctx = core_link->ctx; + sink->protected.link = link; + sink->protected.ctx = link->ctx; sink->protected.public.dongle_max_pix_clk = init_params->dongle_max_pix_clk; sink->protected.public.converter_disable_audio = init_params->converter_disable_audio; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 73712fd6f64a..a329709de360 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -91,7 +91,7 @@ static bool construct(struct core_stream *stream, /* EDID CAP translation for HDMI 2.0 */ stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; - stream->status.link = &stream->sink->link->public; + stream->status.link = stream->sink->link; return true; } @@ -355,5 +355,5 @@ void dc_stream_log( dm_logger_write(dm_logger, log_type, "\tlink: %d\n", - core_stream->sink->link->public.link_index); + core_stream->sink->link->link_index); } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b14bad10db97..e15e8fb1eefe 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -31,6 +31,7 @@ #include "logger_types.h" #include "gpio_types.h" #include "link_service_types.h" +#include "grph_object_ctrl_defs.h" #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -141,11 +142,11 @@ struct dc_link_funcs { bool skip_video_pattern); void (*set_preferred_link_settings)(struct dc *dc, struct dc_link_settings *link_setting, - const struct dc_link *link); + struct dc_link *link); void (*enable_hpd)(const struct dc_link *link); void (*disable_hpd)(const struct dc_link *link); void (*set_test_pattern)( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, @@ -641,7 +642,7 @@ struct dc_stream_status { /* * link this stream passes through */ - const struct dc_link *link; + struct dc_link *link; }; struct dc_stream_status *dc_stream_get_status( @@ -662,6 +663,50 @@ void dc_release_validate_context(struct validate_context *context); * Link Interfaces ******************************************************************************/ +struct dpcd_caps { + union dpcd_rev dpcd_rev; + union max_lane_count max_ln_count; + union max_down_spread max_down_spread; + + /* dongle type (DP converter, CV smart dongle) */ + enum display_dongle_type dongle_type; + /* Dongle's downstream count. */ + union sink_count sink_count; + /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, + indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ + struct dc_dongle_caps dongle_caps; + + uint32_t sink_dev_id; + uint32_t branch_dev_id; + int8_t branch_dev_name[6]; + int8_t branch_hw_revision; + + bool allow_invalid_MSA_timing_param; + bool panel_mode_edp; +}; + +struct dc_link_status { + struct dpcd_caps *dpcd_caps; +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct link_mst_stream_allocation { + /* DIG front */ + const struct stream_encoder *stream_enc; + /* associate DRM payload table with DC stream encoder */ + uint8_t vcp_id; + /* number of slots required for the DP stream in transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct link_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; +}; + /* * A link contains one or more sinks and their connected status. * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. @@ -699,32 +744,31 @@ struct dc_link { struct ddc_service *ddc; bool aux_mode; -}; -struct dpcd_caps { - union dpcd_rev dpcd_rev; - union max_lane_count max_ln_count; - union max_down_spread max_down_spread; + /* Private to DC core */ - /* dongle type (DP converter, CV smart dongle) */ - enum display_dongle_type dongle_type; - /* Dongle's downstream count. */ - union sink_count sink_count; - /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, - indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ - struct dc_dongle_caps dongle_caps; + const struct core_dc *dc; - uint32_t sink_dev_id; - uint32_t branch_dev_id; - int8_t branch_dev_name[6]; - int8_t branch_hw_revision; + struct dc_context *ctx; - bool allow_invalid_MSA_timing_param; - bool panel_mode_edp; -}; + struct link_encoder *link_enc; + struct graphics_object_id link_id; + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + struct dpcd_caps dpcd_caps; + unsigned int dpcd_sink_count; + + enum edp_revision edp_revision; + bool psr_enabled; + + /* MST record stream using this link */ + struct link_flags { + bool dp_keep_receiver_powered; + } wa_flags; + struct link_mst_stream_allocation_table mst_stream_alloc_table; + + struct dc_link_status link_status; -struct dc_link_status { - struct dpcd_caps *dpcd_caps; }; const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); @@ -734,7 +778,7 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); * boot time. They cannot be created or destroyed. * Use dc_get_caps() to get number of links. */ -const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); +struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); /* Return id of physical connector represented by a dc_link at link_index.*/ const struct graphics_object_id dc_get_link_id_at_index( @@ -750,7 +794,7 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); -bool dc_link_setup_psr(const struct dc_link *dc_link, +bool dc_link_setup_psr(struct dc_link *dc_link, const struct dc_stream *stream, struct psr_config *psr_config, struct psr_context *psr_context); @@ -760,7 +804,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, * true otherwise. True meaning further action is required (status update * and OS notification). */ -bool dc_link_detect(const struct dc_link *dc_link, bool boot); +bool dc_link_detect(struct dc_link *dc_link, bool boot); /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). * Return: @@ -768,26 +812,26 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot); * detection. * false - no change in Downstream port status. No further action required * from DM. */ -bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, union hpd_irq_data *hpd_irq_dpcd_data); struct dc_sink_init_data; struct dc_sink *dc_link_add_remote_sink( - const struct dc_link *dc_link, + struct dc_link *dc_link, const uint8_t *edid, int len, struct dc_sink_init_data *init_data); void dc_link_remove_remote_sink( - const struct dc_link *link, + struct dc_link *link, const struct dc_sink *sink); /* Used by diagnostics for virtual link at the moment */ -void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink); +void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink); void dc_link_dp_set_drive_settings( - const struct dc_link *link, + struct dc_link *link, struct link_training_settings *lt_settings); enum link_training_result dc_link_dp_perform_link_training( @@ -800,7 +844,7 @@ void dc_link_dp_enable_hpd(const struct dc_link *link); void dc_link_dp_disable_hpd(const struct dc_link *link); bool dc_link_dp_set_test_pattern( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, @@ -844,7 +888,7 @@ const struct audio **dc_get_audios(struct dc *dc); struct dc_sink_init_data { enum signal_type sink_signal; - const struct dc_link *link; + struct dc_link *link; uint32_t dongle_max_pix_clk; bool converter_disable_audio; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h index b143fe88f49f..e1affeb5cc51 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h @@ -105,7 +105,7 @@ struct ddc_service { enum ddc_transaction_type transaction_type; enum display_dongle_type dongle_type; struct dc_context *ctx; - struct core_link *link; + struct dc_link *link; uint32_t address; uint32_t edid_buf_len; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 0fe3ee8e29d3..aaff946a6d0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -142,7 +142,7 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) } static void dce_dmcu_setup_psr(struct dmcu *dmcu, - struct core_link *link, + struct dc_link *link, struct psr_context *psr_context) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); @@ -382,7 +382,7 @@ static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) } static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, - struct core_link *link, + struct dc_link *link, struct psr_context *psr_context) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 5663d3dbd7d5..318673da189b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1020,7 +1020,7 @@ bool dce110_link_encoder_validate_output_with_stream( case SIGNAL_TYPE_DVI_DUAL_LINK: is_valid = dce110_link_encoder_validate_dvi_output( enc110, - stream->sink->link->public.connector_signal, + stream->sink->link->connector_signal, pipe_ctx->stream->signal, &stream->public.timing); break; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 716f664f40ce..6938158bed7f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -661,7 +661,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index cf6bf2098b7c..fe8084e290a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -700,10 +700,10 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) void dce110_enable_stream(struct pipe_ctx *pipe_ctx) { enum dc_lane_count lane_count = - pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; + pipe_ctx->stream->sink->link->cur_link_settings.lane_count; struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; - struct core_link *link = pipe_ctx->stream->sink->link; + struct dc_link *link = pipe_ctx->stream->sink->link; /* 1. update AVI info frame (HDMI, DP) * we always need to update info frame @@ -746,7 +746,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); @@ -1111,7 +1111,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( dce110_update_info_frame(pipe_ctx); if (dc_is_dp_signal(pipe_ctx->stream->signal)) dce110_unblank_stream(pipe_ctx, - &stream->sink->link->public.cur_link_settings); + &stream->sink->link->cur_link_settings); } pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; @@ -2220,7 +2220,7 @@ static void init_hw(struct core_dc *dc) /* Power up AND update implementation according to the * required signal (which may be different from the * default signal on connector). */ - struct core_link *link = dc->links[i]; + struct dc_link *link = dc->links[i]; link->link_enc->funcs->hw_init(link->link_enc); } @@ -2283,11 +2283,11 @@ void dce110_fill_display_configs( cfg->transmitter = stream->sink->link->link_enc->transmitter; cfg->link_settings.lane_count = - stream->sink->link->public.cur_link_settings.lane_count; + stream->sink->link->cur_link_settings.lane_count; cfg->link_settings.link_rate = - stream->sink->link->public.cur_link_settings.link_rate; + stream->sink->link->cur_link_settings.link_rate; cfg->link_settings.link_spread = - stream->sink->link->public.cur_link_settings.link_spread; + stream->sink->link->cur_link_settings.link_spread; cfg->sym_clock = stream->phy_pix_clk; /* Round v_refresh*/ cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 0fcb1cf4b4ce..015306a6ef88 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -781,7 +781,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 80f067343a91..ca1e13e2a3db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -730,7 +730,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5861b3fdf7d2..b2319dbf3be3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -677,7 +677,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 4390023ca6dc..c25a39214111 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -628,7 +628,7 @@ static void dcn10_init_hw(struct core_dc *dc) * required signal (which may be different from the * default signal on connector). */ - struct core_link *link = dc->links[i]; + struct dc_link *link = dc->links[i]; link->link_enc->funcs->hw_init(link->link_enc); } @@ -2259,7 +2259,7 @@ static void dcn10_config_stereo_parameters( timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA || timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) { enum display_dongle_type dongle = \ - stream->sink->link->public.ddc->dongle_type; + stream->sink->link->ddc->dongle_type; if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER || dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER || dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index eec0d5b22a9f..0110a431e289 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -845,7 +845,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index 785236a44aee..1ecb54603e17 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -20,7 +20,7 @@ struct core_dc { struct dc_context *ctx; uint8_t link_count; - struct core_link *links[MAX_PIPES * 2]; + struct dc_link *links[MAX_PIPES * 2]; struct validate_context *current_context; struct resource_pool *res_pool; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 07a1aec5a28b..6cdfeeba0faf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -92,13 +92,11 @@ struct core_sink { /** The 'protected' area - read/write access, for use only inside DC **/ /* not used for now */ - struct core_link *link; + struct dc_link *link; struct dc_context *ctx; }; /************ link *****************/ -#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public) - struct link_init_data { const struct core_dc *dc; struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ @@ -107,61 +105,15 @@ struct link_init_data { TODO: remove it when DC is complete. */ }; -/* DP MST stream allocation (payload bandwidth number) */ -struct link_mst_stream_allocation { - /* DIG front */ - const struct stream_encoder *stream_enc; - /* associate DRM payload table with DC stream encoder */ - uint8_t vcp_id; - /* number of slots required for the DP stream in transport packet */ - uint8_t slot_count; -}; - -/* DP MST stream allocation table */ -struct link_mst_stream_allocation_table { - /* number of DP video streams */ - int stream_count; - /* array of stream allocations */ - struct link_mst_stream_allocation - stream_allocations[MAX_CONTROLLER_NUM]; -}; - -struct core_link { - struct dc_link public; - const struct core_dc *dc; - - struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/ - - struct link_encoder *link_enc; - struct graphics_object_id link_id; - union ddi_channel_mapping ddi_channel_mapping; - struct connector_device_tag_info device_tag; - struct dpcd_caps dpcd_caps; - unsigned int dpcd_sink_count; - - enum edp_revision edp_revision; - bool psr_enabled; - - /* MST record stream using this link */ - struct link_flags { - bool dp_keep_receiver_powered; - } wa_flags; - struct link_mst_stream_allocation_table mst_stream_alloc_table; - - struct dc_link_status link_status; -}; - -#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public) - -struct core_link *link_create(const struct link_init_data *init_params); -void link_destroy(struct core_link **link); +struct dc_link *link_create(const struct link_init_data *init_params); +void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( const struct core_stream *stream, - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing); -void core_link_resume(struct core_link *link); +void core_link_resume(struct dc_link *link); void core_link_enable_stream(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h index 9c2f670c3dc3..af7ea5eaf185 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h @@ -84,7 +84,7 @@ void dal_ddc_aux_payloads_add( struct ddc_service_init_data { struct graphics_object_id id; struct dc_context *ctx; - struct core_link *link; + struct dc_link *link; }; struct ddc_service *dal_ddc_service_create( diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index b6ef1bfd267c..d9af028a39df 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -29,12 +29,12 @@ #define LINK_TRAINING_ATTEMPTS 4 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ -struct core_link; +struct dc_link; struct core_stream; struct dc_link_settings; bool dp_hbr_verify_link_cap( - struct core_link *link, + struct dc_link *link, struct dc_link_settings *known_limit_link_setting); bool decide_fallback_link_setting(struct dc_link_settings link_setting_init, @@ -46,7 +46,7 @@ struct dc_link_settings get_common_supported_link_settings ( struct dc_link_settings link_setting_b); bool dp_validate_mode_timing( - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing); void decide_link_settings( @@ -54,17 +54,17 @@ void decide_link_settings( struct dc_link_settings *link_setting); bool perform_link_training_with_retries( - struct core_link *link, + struct dc_link *link, const struct dc_link_settings *link_setting, bool skip_video_pattern, int attempts); -bool is_mst_supported(struct core_link *link); +bool is_mst_supported(struct dc_link *link); -void detect_dp_sink_caps(struct core_link *link); +void detect_dp_sink_caps(struct dc_link *link); -bool is_dp_active_dongle(const struct core_link *link); +bool is_dp_active_dongle(const struct dc_link *link); -void dp_enable_mst_on_sink(struct core_link *link, bool enable); +void dp_enable_mst_on_sink(struct dc_link *link, bool enable); #endif /* __DC_LINK_DP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index 6067f464d805..e34b25939a98 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -39,7 +39,7 @@ struct dmcu_funcs { unsigned int bytes); void (*set_psr_enable)(struct dmcu *dmcu, bool enable); void (*setup_psr)(struct dmcu *dmcu, - struct core_link *link, + struct dc_link *link, struct psr_context *psr_context); void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state); void (*set_psr_wait_loop)(struct dmcu *dmcu, diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h index 75d10e93b002..f7994cfc850d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h @@ -29,46 +29,46 @@ #include "inc/core_status.h" enum dc_status core_link_read_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, uint8_t *data, uint32_t size); enum dc_status core_link_write_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, const uint8_t *data, uint32_t size); void dp_enable_link_phy( - struct core_link *link, + struct dc_link *link, enum signal_type signal, enum clock_source_id clock_source, const struct dc_link_settings *link_settings); -void dp_receiver_power_ctrl(struct core_link *link, bool on); +void dp_receiver_power_ctrl(struct dc_link *link, bool on); -void dp_disable_link_phy(struct core_link *link, enum signal_type signal); +void dp_disable_link_phy(struct dc_link *link, enum signal_type signal); -void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal); +void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal); bool dp_set_hw_training_pattern( - struct core_link *link, + struct dc_link *link, enum hw_dp_training_pattern pattern); void dp_set_hw_lane_settings( - struct core_link *link, + struct dc_link *link, const struct link_training_settings *link_settings); void dp_set_hw_test_pattern( - struct core_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, uint8_t *custom_pattern, uint32_t custom_pattern_size); -enum dp_panel_mode dp_get_panel_mode(struct core_link *link); +enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); -void dp_retrain_link_dp_test(struct core_link *link, +void dp_retrain_link_dp_test(struct dc_link *link, struct dc_link_settings *link_setting, bool skip_video_pattern); diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 6e6fd4e8fc00..3adf3cfc7aba 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -140,19 +140,19 @@ void context_clock_trace( */ #define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \ - dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \ + dc_conn_log(link->ctx, link, hex_data, hex_len, \ LOG_EVENT_DETECTION, ##__VA_ARGS__) #define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \ - dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \ + dc_conn_log(link->ctx, link, hex_data, hex_len, \ LOG_EVENT_LINK_LOSS, ##__VA_ARGS__) #define CONN_MSG_LT(link, ...) \ - dc_conn_log(link->ctx, &link->public, NULL, 0, \ + dc_conn_log(link->ctx, link, NULL, 0, \ LOG_EVENT_LINK_TRAINING, ##__VA_ARGS__) #define CONN_MSG_MODE(link, ...) \ - dc_conn_log(link->ctx, &link->public, NULL, 0, \ + dc_conn_log(link->ctx, link, NULL, 0, \ LOG_EVENT_MODE_SET, ##__VA_ARGS__) #endif /* __DAL_LOGGER_INTERFACE_H__ */ -- cgit v1.2.3-59-g8ed1b From b73a22d3257f9ec237c46be12d74b58d5a925d8c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 24 Jul 2017 14:04:27 -0400 Subject: drm/amd/display: Roll core_sink into dc_sink Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 60 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 30 +++++------ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 19 ++++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 21 +------- 11 files changed, 72 insertions(+), 91 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index c558f700df35..8d939e3b3f15 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -562,9 +562,9 @@ struct amdgpu_connector { int num_modes; /* The 'old' sink - before an HPD. * The 'current' sink is in dc_link->sink. */ - const struct dc_sink *dc_sink; + struct dc_sink *dc_sink; struct dc_link *dc_link; - const struct dc_sink *dc_em_sink; + struct dc_sink *dc_em_sink; const struct dc_stream *stream; void *con_priv; bool dac_load_detect; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 26fbadba97dd..696a4112c8d9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -697,7 +697,7 @@ void amdgpu_dm_update_connector_after_detect( { struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; - const struct dc_sink *sink; + struct dc_sink *sink; /* MST handled by drm_mst framework */ if (aconnector->mst_mgr.mst_state == true) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 4885403f5cec..13708bcb83cd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1266,7 +1266,7 @@ int amdgpu_dm_connector_mode_valid( struct drm_display_mode *mode) { int result = MODE_ERROR; - const struct dc_sink *dc_sink; + struct dc_sink *dc_sink; struct amdgpu_device *adev = connector->dev->dev_private; struct dc_validation_set val_set = { 0 }; /* TODO: Unhardcode stream count */ @@ -1535,7 +1535,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, struct drm_display_mode *mode, struct dc_validation_set *val_set) { int result = MODE_ERROR; - const struct dc_sink *dc_sink = + struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ struct dc_stream *stream; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 73740e2a5819..30374ffaae0b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -939,7 +939,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c program_timing_sync(core_dc, context); for (i = 0; i < context->stream_count; i++) { - const struct core_sink *sink = context->streams[i]->sink; + const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { const struct dc_surface *surface = @@ -1984,7 +1984,7 @@ void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink) } } -void dc_link_remove_remote_sink(struct dc_link *link, const struct dc_sink *sink) +void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 428dbff8505b..e7062069d9a1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -541,8 +541,7 @@ bool dc_link_detect(struct dc_link *link, bool boot) struct audio_support *aud_support = &link->dc->res_pool->audio_support; enum dc_edid_status edid_status; struct dc_context *dc_ctx = link->ctx; - struct dc_sink *dc_sink; - struct core_sink *sink = NULL; + struct dc_sink *sink; enum dc_connection_type new_connection_type = dc_connection_none; if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) @@ -637,22 +636,21 @@ bool dc_link_detect(struct dc_link *link, bool boot) sink_init_data.link = link; sink_init_data.sink_signal = sink_caps.signal; - dc_sink = dc_sink_create(&sink_init_data); - if (!dc_sink) { + sink = dc_sink_create(&sink_init_data); + if (!sink) { DC_ERROR("Failed to create sink!\n"); return false; } - dc_sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; - dc_sink->converter_disable_audio = converter_disable_audio; + sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; + sink->converter_disable_audio = converter_disable_audio; - sink = DC_SINK_TO_CORE(dc_sink); - link->local_sink = &sink->public; + link->local_sink = sink; edid_status = dm_helpers_read_local_edid( link->ctx, link, - &sink->public); + sink); switch (edid_status) { case EDID_BAD_CHECKSUM: @@ -669,16 +667,16 @@ bool dc_link_detect(struct dc_link *link, bool boot) } /* HDMI-DVI Dongle */ - if (dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && - !dc_sink->edid_caps.edid_hdmi) - dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && + !sink->edid_caps.edid_hdmi) + sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; /* Connectivity log: detection */ - for (i = 0; i < sink->public.dc_edid.length / EDID_BLOCK_SIZE; i++) { + for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) { CONN_DATA_DETECT(link, - &sink->public.dc_edid.raw_edid[i * EDID_BLOCK_SIZE], + &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE], EDID_BLOCK_SIZE, - "%s: [Block %d] ", sink->public.edid_caps.display_name, i); + "%s: [Block %d] ", sink->edid_caps.display_name, i); } dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER, @@ -692,16 +690,16 @@ bool dc_link_detect(struct dc_link *link, bool boot) "speaker_flag = %d, " "audio_mode_count = %d\n", __func__, - sink->public.edid_caps.manufacturer_id, - sink->public.edid_caps.product_id, - sink->public.edid_caps.serial_number, - sink->public.edid_caps.manufacture_week, - sink->public.edid_caps.manufacture_year, - sink->public.edid_caps.display_name, - sink->public.edid_caps.speaker_flags, - sink->public.edid_caps.audio_mode_count); - - for (i = 0; i < sink->public.edid_caps.audio_mode_count; i++) { + sink->edid_caps.manufacturer_id, + sink->edid_caps.product_id, + sink->edid_caps.serial_number, + sink->edid_caps.manufacture_week, + sink->edid_caps.manufacture_year, + sink->edid_caps.display_name, + sink->edid_caps.speaker_flags, + sink->edid_caps.audio_mode_count); + + for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER, "%s: mode number = %d, " "format_code = %d, " @@ -710,10 +708,10 @@ bool dc_link_detect(struct dc_link *link, bool boot) "sample_size = %d\n", __func__, i, - sink->public.edid_caps.audio_modes[i].format_code, - sink->public.edid_caps.audio_modes[i].channel_count, - sink->public.edid_caps.audio_modes[i].sample_rate, - sink->public.edid_caps.audio_modes[i].sample_size); + sink->edid_caps.audio_modes[i].format_code, + sink->edid_caps.audio_modes[i].channel_count, + sink->edid_caps.audio_modes[i].sample_rate, + sink->edid_caps.audio_modes[i].sample_size); } } else { @@ -732,7 +730,7 @@ bool dc_link_detect(struct dc_link *link, bool boot) } LINK_INFO("link=%d, dc_sink_in=%p is now %s\n", - link->link_index, &sink->public, + link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected")); @@ -1347,7 +1345,7 @@ enum dc_status dc_link_validate_mode_timing( struct dc_link *link, const struct dc_crtc_timing *timing) { - uint32_t max_pix_clk = stream->sink->public.dongle_max_pix_clk; + uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk; /* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7a3d090f8465..7cb572ff3cba 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1528,7 +1528,7 @@ enum dc_status resource_map_pool_resources( pipe_ctx->stream_enc); /* TODO: Add check if ASIC support and EDID audio */ - if (!stream->sink->public.converter_disable_audio && + if (!stream->sink->converter_disable_audio && dc_is_audio_capable_signal(pipe_ctx->stream->signal) && stream->public.audio_info.mode_count) { pipe_ctx->audio = find_first_free_audio( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index 1f7985ad5dba..a83f1243a9d1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -31,15 +31,15 @@ * Private functions ******************************************************************************/ -static void destruct(struct core_sink *sink) +static void destruct(struct dc_sink *sink) { - if (sink->public.dc_container_id) { - dm_free(sink->public.dc_container_id); - sink->public.dc_container_id = NULL; + if (sink->dc_container_id) { + dm_free(sink->dc_container_id); + sink->dc_container_id = NULL; } } -static bool construct(struct core_sink *sink, const struct dc_sink_init_data *init_params) +static bool construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params) { struct dc_link *link = init_params->link; @@ -47,12 +47,12 @@ static bool construct(struct core_sink *sink, const struct dc_sink_init_data *in if (!link) return false; - sink->public.sink_signal = init_params->sink_signal; + sink->sink_signal = init_params->sink_signal; sink->link = link; sink->ctx = link->ctx; - sink->public.dongle_max_pix_clk = init_params->dongle_max_pix_clk; - sink->public.converter_disable_audio = init_params->converter_disable_audio; - sink->public.dc_container_id = NULL; + sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk; + sink->converter_disable_audio = init_params->converter_disable_audio; + sink->dc_container_id = NULL; return true; } @@ -61,18 +61,14 @@ static bool construct(struct core_sink *sink, const struct dc_sink_init_data *in * Public functions ******************************************************************************/ -void dc_sink_retain(const struct dc_sink *dc_sink) +void dc_sink_retain(struct dc_sink *sink) { - struct core_sink *sink = DC_SINK_TO_CORE(dc_sink); - ASSERT(sink->ref_count > 0); ++sink->ref_count; } -void dc_sink_release(const struct dc_sink *dc_sink) +void dc_sink_release(struct dc_sink *sink) { - struct core_sink *sink = DC_SINK_TO_CORE(dc_sink); - ASSERT(sink->ref_count > 0); --sink->ref_count; @@ -84,7 +80,7 @@ void dc_sink_release(const struct dc_sink *dc_sink) struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) { - struct core_sink *sink = dm_alloc(sizeof(*sink)); + struct dc_sink *sink = dm_alloc(sizeof(*sink)); if (NULL == sink) goto alloc_fail; @@ -94,7 +90,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) ++sink->ref_count; - return &sink->public; + return sink; construct_fail: dm_free(sink); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a329709de360..5b356ddf5614 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -46,11 +46,11 @@ struct stream { ******************************************************************************/ static bool construct(struct core_stream *stream, - const struct dc_sink *dc_sink_data) + struct dc_sink *dc_sink_data) { uint32_t i = 0; - stream->sink = DC_SINK_TO_CORE(dc_sink_data); + stream->sink = dc_sink_data; stream->ctx = stream->sink->ctx; stream->public.sink = dc_sink_data; @@ -97,7 +97,7 @@ static bool construct(struct core_stream *stream, static void destruct(struct core_stream *stream) { - dc_sink_release(&stream->sink->public); + dc_sink_release(stream->sink); if (stream->public.out_transfer_func != NULL) { dc_transfer_func_release( stream->public.out_transfer_func); @@ -130,9 +130,8 @@ void dc_stream_release(const struct dc_stream *public) } struct dc_stream *dc_create_stream_for_sink( - const struct dc_sink *dc_sink) + struct dc_sink *sink) { - struct core_sink *sink = DC_SINK_TO_CORE(dc_sink); struct stream *stream; if (sink == NULL) @@ -143,7 +142,7 @@ struct dc_stream *dc_create_stream_for_sink( if (NULL == stream) goto alloc_fail; - if (false == construct(&stream->protected, dc_sink)) + if (false == construct(&stream->protected, sink)) goto construct_fail; stream->ref_count++; @@ -350,8 +349,8 @@ void dc_stream_log( dm_logger_write(dm_logger, log_type, "\tsink name: %s, serial: %d\n", - core_stream->sink->public.edid_caps.display_name, - core_stream->sink->public.edid_caps.serial_number); + core_stream->sink->edid_caps.display_name, + core_stream->sink->edid_caps.serial_number); dm_logger_write(dm_logger, log_type, "\tlink: %d\n", diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e15e8fb1eefe..77bd54659a8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -629,7 +629,7 @@ bool dc_enable_stereo( /** * Create a new default stream for the requested sink */ -struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink); +struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); void dc_stream_retain(const struct dc_stream *dc_stream); void dc_stream_release(const struct dc_stream *dc_stream); @@ -712,9 +712,9 @@ struct link_mst_stream_allocation_table { * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. */ struct dc_link { - const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; + struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; unsigned int sink_count; - const struct dc_sink *local_sink; + struct dc_sink *local_sink; unsigned int link_index; enum dc_connection_type type; enum signal_type connector_signal; @@ -825,7 +825,7 @@ struct dc_sink *dc_link_add_remote_sink( void dc_link_remove_remote_sink( struct dc_link *link, - const struct dc_sink *sink); + struct dc_sink *sink); /* Used by diagnostics for virtual link at the moment */ void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink); @@ -879,10 +879,17 @@ struct dc_sink { void *priv; struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; bool converter_disable_audio; + + /* private to DC core */ + struct dc_link *link; + struct dc_context *ctx; + + /* private to dc_sink.c */ + int ref_count; }; -void dc_sink_retain(const struct dc_sink *sink); -void dc_sink_release(const struct dc_sink *sink); +void dc_sink_retain(struct dc_sink *sink); +void dc_sink_release(struct dc_sink *sink); const struct audio **dc_get_audios(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index fe8084e290a3..58701fdb7c94 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -657,7 +657,7 @@ static enum dc_status bios_parser_crtc_source_select( * encoder block * note: video bios clears all FMT setting here. */ struct bp_crtc_source_select crtc_source_select = {0}; - const struct core_sink *sink = pipe_ctx->stream->sink; + const struct dc_sink *sink = pipe_ctx->stream->sink; crtc_source_select.engine_id = pipe_ctx->stream_enc->id; crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index eed31a827a90..1d733c837854 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -68,7 +68,7 @@ struct core_stream { /* field internal to DC */ struct dc_context *ctx; - const struct core_sink *sink; + struct dc_sink *sink; /* used by DCP and FMT */ struct bit_depth_reduction_params bit_depth_params; @@ -80,25 +80,6 @@ struct core_stream { struct dc_stream_status status; }; -/************ core_sink *****************/ - -#define DC_SINK_TO_CORE(dc_sink) \ - container_of(dc_sink, struct core_sink, public) - -struct core_sink { - /** The public, read-only (for DM) area of sink. **/ - struct dc_sink public; - /** End-of-public area. **/ - - /** The 'protected' area - read/write access, for use only inside DC **/ - /* not used for now */ - struct dc_link *link; - struct dc_context *ctx; - - /* private to dc_sink.c */ - int ref_count; -}; - /************ link *****************/ struct link_init_data { const struct core_dc *dc; -- cgit v1.2.3-59-g8ed1b From 6be425f3dc16bac797f300136b976bce46229784 Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Mon, 24 Jul 2017 10:47:02 -0400 Subject: drm/amd/display: break up plane disable and disconnect in set mode Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 23 +++-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 102 ++++++++++++++++++--- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +- 4 files changed, 111 insertions(+), 23 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d3873ac45cf3..79218805754e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -932,7 +932,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c for (i = 0; i < core_dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; - core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe); + core_dc->hwss.wait_for_mpcc_disconnect(core_dc, core_dc->res_pool, pipe); } result = core_dc->hwss.apply_ctx_to_hw(core_dc, context); @@ -1364,6 +1364,16 @@ void dc_update_surfaces_and_stream(struct dc *dc, struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct dc_context *dc_ctx = core_dc->ctx; + /* Currently this function do not result in any HW programming + * when called with 0 surface. But proceeding will cause + * SW state to be updated in validate_context. So we might as + * well make it not do anything at all until the hw programming + * is implemented properly to handle 0 surface case. + * TODO: fix hw programming then remove this early return + */ + if (surface_count == 0) + return; + stream_status = dc_stream_get_status(dc_stream); ASSERT(stream_status); if (!stream_status) @@ -1535,15 +1545,10 @@ void dc_update_surfaces_and_stream(struct dc *dc, } if (update_type > UPDATE_TYPE_FAST) { - for (i = 0; i < surface_count; i++) { - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (pipe_ctx->surface != srf_updates[i].surface) - continue; + for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe_ctx); - } + core_dc->hwss.wait_for_mpcc_disconnect(core_dc, core_dc->res_pool, pipe_ctx); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 58701fdb7c94..aa4777a8ec36 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2583,7 +2583,10 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) dc->res_pool->transforms[fe_idx]); } -static void dce110_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) +static void dce110_wait_for_mpcc_disconnect( + struct core_dc *dc, + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx) { /* do nothing*/ } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3a0fcaad84c2..bbe3e8705405 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -831,21 +831,32 @@ static void plane_atomic_disconnect(struct core_dc *dc, if (opp_id == 0xf) return; + if (dc->public.debug.sanity_checks) + verify_allow_pstate_change_high(dc->hwseq); + mi->funcs->dcc_control(mi, false, false); + if (dc->public.debug.sanity_checks) + verify_allow_pstate_change_high(dc->hwseq); + mpcc_cfg.opp_id = 0xf; mpcc_cfg.top_dpp_id = 0xf; mpcc_cfg.bot_mpcc_id = 0xf; mpcc_cfg.top_of_tree = tg->inst == mpcc->inst; mpcc->funcs->set(mpcc, &mpcc_cfg); - /* Hack to preserve old opp_id for plane_atomic_disable - * to find the correct otg */ + /* + * Hack to preserve old opp_id for plane_atomic_disable + * to find the correct otg + */ mpcc->opp_id = opp_id_cached; /* todo:call remove pipe from tree */ /* flag mpcc idle pending */ + /*dm_logger_write(dc->ctx->logger, LOG_ERROR, + "[debug_mpo: plane_atomic_disconnect pending on mpcc %d]\n", + fe_idx);*/ xfm->funcs->transform_reset(xfm); } @@ -864,6 +875,10 @@ static void plane_atomic_disable(struct core_dc *dc, return; mpcc->funcs->wait_for_idle(mpcc); + dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[mpcc->inst] = false; + /*dm_logger_write(dc->ctx->logger, LOG_ERROR, + "[debug_mpo: atomic disable finished on mpcc %d]\n", + fe_idx);*/ mi->funcs->set_blank(mi, true); @@ -885,13 +900,27 @@ static void plane_atomic_disable(struct core_dc *dc, verify_allow_pstate_change_high(dc->hwseq); } -/* kill power to plane hw +/* + * kill power to plane hw * note: cannot power down until plane is disable -static void plane_atomic_power_down() + */ +static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) { + struct dce_hwseq *hws = dc->hwseq; + + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + dpp_pg_control(hws, fe_idx, false); + hubp_pg_control(hws, fe_idx, false); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + dm_logger_write(dc->ctx->logger, LOG_DC, + "Power gated front end %d\n", fe_idx); + if (dc->public.debug.sanity_checks) + verify_allow_pstate_change_high(dc->hwseq); } -*/ + static void reset_front_end( struct core_dc *dc, @@ -953,6 +982,37 @@ static void reset_hw_ctx_wrap( int i; /* Reset Front End*/ + /* Lock*/ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct timing_generator *tg = cur_pipe_ctx->tg; + + if (cur_pipe_ctx->stream) + tg->funcs->lock(tg); + } + /* Disconnect*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->stream || + !pipe_ctx->surface || + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + + plane_atomic_disconnect(dc, i); + } + } + /* Unlock*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct timing_generator *tg = cur_pipe_ctx->tg; + + if (cur_pipe_ctx->stream) + tg->funcs->unlock(tg); + } + + /* Disable and Powerdown*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.pipe_ctx[i]; @@ -961,11 +1021,16 @@ static void reset_hw_ctx_wrap( /*if (!pipe_ctx_old->stream) continue;*/ + if (pipe_ctx->stream && pipe_ctx->surface + && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + continue; + + plane_atomic_disable(dc, i); + if (!pipe_ctx->stream || !pipe_ctx->surface) - dcn10_power_down_fe(dc, i); - else if (pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - reset_front_end(dc, i); + plane_atomic_power_down(dc, i); } + /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = @@ -2079,6 +2144,10 @@ static void dcn10_apply_ctx_for_surface( old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg); old_pipe_ctx->top_pipe->opp->mpcc_disconnect_pending[old_pipe_ctx->mpcc->inst] = true; + /*dm_logger_write(dc->ctx->logger, LOG_ERROR, + "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", + old_pipe_ctx->mpcc->inst);*/ + if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); @@ -2351,18 +2420,27 @@ static void dcn10_log_hw_state(struct core_dc *dc) */ } -static void dcn10_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) +static void dcn10_wait_for_mpcc_disconnect( + struct core_dc *dc, + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx) { int i; - for (i = 0; i < MAX_PIPES; i++) { - if (!pipe_ctx->opp || !pipe_ctx->mpcc) - continue; + if (!pipe_ctx->opp || !pipe_ctx->mpcc) + return; + + for (i = 0; i < MAX_PIPES; i++) { if (pipe_ctx->opp->mpcc_disconnect_pending[i]) { pipe_ctx->mpcc->funcs->wait_for_idle(res_pool->mpcc[i]); pipe_ctx->opp->mpcc_disconnect_pending[i] = false; + res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true); + /*dm_logger_write(dc->ctx->logger, LOG_ERROR, + "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n", + i);*/ } } + } static bool dcn10_dummy_display_power_gating( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 2343beb4ef87..a3eec078dead 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -161,7 +161,9 @@ struct hw_sequencer_funcs { void (*log_hw_state)(struct core_dc *dc); - void (*wait_for_mpcc_disconnect)(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); + void (*wait_for_mpcc_disconnect)(struct core_dc *dc, + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( -- cgit v1.2.3-59-g8ed1b From 9345d9874c324b2f8cce79d4de11f27ae1ef80e9 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 21 Jul 2017 16:34:36 -0400 Subject: drm/amd/display: Move stream validations into seperate function. Stateless streams validations (not require resource population) moved into hook to be called directly from DM. Call dc_validate_stream be before validate_with_context for non Linux APIs Signed-off-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 24 +++++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 61 +++++++++++++++------- drivers/gpu/drm/amd/display/dc/dc.h | 2 + .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 7 ++- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 24 ++------- .../drm/amd/display/dc/dce110/dce110_resource.c | 23 ++------ .../drm/amd/display/dc/dce112/dce112_resource.c | 25 ++------- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 25 ++------- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 25 ++------- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- 12 files changed, 90 insertions(+), 132 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 79218805754e..9c2faf8e4b14 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -664,6 +664,20 @@ static bool is_validation_required( return false; } +static bool validate_streams ( + const struct dc *dc, + const struct dc_validation_set set[], + int set_count) +{ + int i; + + for (i = 0; i < set_count; i++) + if (!dc_validate_stream(dc, set[i].stream)) + return false; + + return true; +} + struct validate_context *dc_get_validate_context( const struct dc *dc, const struct dc_validation_set set[], @@ -673,6 +687,7 @@ struct validate_context *dc_get_validate_context( enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; + context = dm_alloc(sizeof(struct validate_context)); if (context == NULL) goto context_alloc_fail; @@ -711,6 +726,9 @@ bool dc_validate_resources( enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; + if (!validate_streams(dc, set, set_count)) + return false; + context = dm_alloc(sizeof(struct validate_context)); if (context == NULL) goto context_alloc_fail; @@ -742,6 +760,9 @@ bool dc_validate_guaranteed( enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; + if (!dc_validate_stream(dc, stream)) + return false; + context = dm_alloc(sizeof(struct validate_context)); if (context == NULL) goto context_alloc_fail; @@ -1044,6 +1065,9 @@ bool dc_commit_streams( } + if (!validate_streams(dc, set, stream_count)) + return false; + context = dm_alloc(sizeof(struct validate_context)); if (context == NULL) goto context_alloc_fail; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7cb572ff3cba..4403d8244407 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1416,23 +1416,17 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct validate_context *context) +static void calculate_phy_pix_clks(struct core_stream *stream) { - int i; - - for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; - - update_stream_signal(stream); - - /* update actual pixel clock on all streams */ - if (dc_is_hdmi_signal(stream->signal)) - stream->phy_pix_clk = get_norm_pix_clk( - &stream->public.timing); - else - stream->phy_pix_clk = - stream->public.timing.pix_clk_khz; - } + update_stream_signal(stream); + + /* update actual pixel clock on all streams */ + if (dc_is_hdmi_signal(stream->signal)) + stream->phy_pix_clk = get_norm_pix_clk( + &stream->public.timing); + else + stream->phy_pix_clk = + stream->public.timing.pix_clk_khz; } enum dc_status resource_map_pool_resources( @@ -1443,8 +1437,6 @@ enum dc_status resource_map_pool_resources( const struct resource_pool *pool = dc->res_pool; int i, j; - calculate_phy_pix_clks(context); - for (i = 0; old_context && i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; @@ -2516,3 +2508,36 @@ void resource_build_bit_depth_reduction_params(const struct core_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } + +bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream) +{ + struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc_context *dc_ctx = core_dc->ctx; + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); + struct dc_link *link = core_stream->sink->link; + struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; + enum dc_status res = DC_OK; + + calculate_phy_pix_clks(core_stream); + + if (!tg->funcs->validate_timing(tg, &core_stream->public.timing)) + res = DC_FAIL_CONTROLLER_VALIDATE; + + if (res == DC_OK) + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, core_stream)) + res = DC_FAIL_ENC_VALIDATE; + + /* TODO: validate audio ASIC caps, encoder */ + + if (res == DC_OK) + res = dc_link_validate_mode_timing(core_stream, + link, + &core_stream->public.timing); + + if (res != DC_OK) + DC_ERROR("Failed validation for stream %p, err:%d, !\n", + stream, res); + + return res == DC_OK; +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5523bb68f4e8..f250e87d39dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -559,6 +559,8 @@ struct dc_validation_set { uint8_t surface_count; }; +bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream); + /* * This function takes a set of resources and checks that they are cofunctional. * diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 318673da189b..aff0a440d4d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,19 +1009,18 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - struct pipe_ctx *pipe_ctx) + const struct core_stream *stream) { - struct core_stream *stream = pipe_ctx->stream; struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; - switch (pipe_ctx->stream->signal) { + switch (stream->signal) { case SIGNAL_TYPE_DVI_SINGLE_LINK: case SIGNAL_TYPE_DVI_DUAL_LINK: is_valid = dce110_link_encoder_validate_dvi_output( enc110, stream->sink->link->connector_signal, - pipe_ctx->stream->signal, + stream->signal, &stream->public.timing); break; case SIGNAL_TYPE_HDMI_TYPE_A: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index fd6ba7efc0f9..ded6c61304e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -199,7 +199,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - struct pipe_ctx *pipe_ctx); + const struct core_stream *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 6938158bed7f..3d25a90e49b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -651,7 +651,7 @@ static void destruct(struct dce110_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } -static enum dc_status validate_mapped_resource( +static enum dc_status build_mapped_resource( const struct core_dc *dc, struct validate_context *context, struct validate_context *old_context) @@ -661,7 +661,6 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -673,25 +672,8 @@ static enum dc_status validate_mapped_resource( if (context->res_ctx.pipe_ctx[j].stream != stream) continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; - - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; - - /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); - if (status != DC_OK) return status; @@ -769,7 +751,7 @@ enum dc_status dce100_validate_with_context( } if (result == DC_OK) - result = validate_mapped_resource(dc, context, old_context); + result = build_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -798,7 +780,7 @@ enum dc_status dce100_validate_guaranteed( result = resource_map_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 015306a6ef88..c773351e93af 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -771,7 +771,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne return true; } -static enum dc_status validate_mapped_resource( +static enum dc_status build_mapped_resource( const struct core_dc *dc, struct validate_context *context, struct validate_context *old_context) @@ -781,7 +781,6 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -797,29 +796,13 @@ static enum dc_status validate_mapped_resource( dc->res_pool->underlay_pipe_index)) return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); if (status != DC_OK) return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); - - if (status != DC_OK) - return status; - resource_build_info_frame(pipe_ctx); /* do not need to validate non root pipes */ @@ -976,7 +959,7 @@ enum dc_status dce110_validate_with_context( } if (result == DC_OK) - result = validate_mapped_resource(dc, context, old_context); + result = build_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -1005,7 +988,7 @@ enum dc_status dce110_validate_guaranteed( result = resource_map_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index ca1e13e2a3db..19cd99923b24 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -720,7 +720,7 @@ static struct clock_source *find_matching_pll( return 0; } -static enum dc_status validate_mapped_resource( +static enum dc_status build_mapped_resource( const struct core_dc *dc, struct validate_context *context, struct validate_context *old_context) @@ -730,7 +730,6 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -742,26 +741,8 @@ static enum dc_status validate_mapped_resource( if (context->res_ctx.pipe_ctx[j].stream != stream) continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; - - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; - - /* TODO: validate audio ASIC caps, encoder */ - - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); - if (status != DC_OK) return status; @@ -952,7 +933,7 @@ enum dc_status dce112_validate_with_context( } if (result == DC_OK) - result = validate_mapped_resource(dc, context, old_context); + result = build_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -981,7 +962,7 @@ enum dc_status dce112_validate_guaranteed( result = resource_map_phy_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index b2319dbf3be3..0123006e5360 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -667,7 +667,7 @@ static void destruct(struct dce110_resource_pool *pool) } } -static enum dc_status validate_mapped_resource( +static enum dc_status build_mapped_resource( const struct core_dc *dc, struct validate_context *context, struct validate_context *old_context) @@ -677,7 +677,6 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -689,26 +688,8 @@ static enum dc_status validate_mapped_resource( if (context->res_ctx.pipe_ctx[j].stream != stream) continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; - - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; - - /* TODO: validate audio ASIC caps, encoder */ - - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); - if (status != DC_OK) return status; @@ -786,7 +767,7 @@ enum dc_status dce80_validate_with_context( } if (result == DC_OK) - result = validate_mapped_resource(dc, context, old_context); + result = build_mapped_resource(dc, context, old_context); if (result == DC_OK) result = resource_build_scaling_params_for_context(dc, context); @@ -814,7 +795,7 @@ enum dc_status dce80_validate_guaranteed( result = resource_map_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 0110a431e289..b901ef9689a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -835,7 +835,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) return DC_OK; } -static enum dc_status validate_mapped_resource( +static enum dc_status build_mapped_resource( const struct core_dc *dc, struct validate_context *context, struct validate_context *old_context) @@ -845,7 +845,6 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -870,29 +869,11 @@ static enum dc_status validate_mapped_resource( if (context->res_ctx.pipe_ctx[j].stream != stream) continue; - - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; - status = build_pipe_hw_param(pipe_ctx); if (status != DC_OK) return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; - - /* TODO: validate audio ASIC caps, encoder */ - - status = dc_link_validate_mode_timing( - stream, link, &stream->public.timing); - - if (status != DC_OK) - return status; - - /* do not need to validate non root pipes */ break; } @@ -928,7 +909,7 @@ enum dc_status dcn10_validate_with_context( if (result != DC_OK) return result; - result = validate_mapped_resource(dc, context, old_context); + result = build_mapped_resource(dc, context, old_context); if (result != DC_OK) return result; @@ -963,7 +944,7 @@ enum dc_status dcn10_validate_guaranteed( result = resource_map_phy_clock_resources(dc, context, NULL); if (result == DC_OK) - result = validate_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, NULL); if (result == DC_OK) { validate_guaranteed_copy_streams( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index d330d38aff16..0ee738774f9f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -94,7 +94,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, struct pipe_ctx *pipe_ctx); + struct link_encoder *enc, const struct core_stream *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 12df49927f09..d312874d95b5 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - struct pipe_ctx *pipe_ctx) { return true; } + const struct core_stream *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} -- cgit v1.2.3-59-g8ed1b From 3639fa68122154b453eeaac840daadf3c7c56db4 Mon Sep 17 00:00:00 2001 From: Zeyu Fan Date: Tue, 25 Jul 2017 15:14:24 -0400 Subject: drm/amd/display: Clean up some DCN1 guards Signed-off-by: Zeyu Fan Reviewed-by: Charlene Liu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 +++--- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 1 + drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 1 + drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 5 +++-- 9 files changed, 15 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 84b1f515aa47..9084a32aab79 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -58,6 +58,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; #endif + case DCE_VERSION_12_0: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9c2faf8e4b14..bab07f8d4880 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1109,7 +1109,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0); + core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version < DCN_VERSION_1_0); #else core_dc->hwss.set_bandwidth(core_dc, context, true); #endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4403d8244407..dea2943392e4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -120,6 +120,8 @@ struct resource_pool *dc_create_resource_pool( num_virtual_links, dc); break; #endif + + default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 142b3a01c204..2205491c83e9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -589,6 +589,7 @@ static uint32_t dce110_get_pix_clk_dividers( #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case DCN_VERSION_1_0: #endif + dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -901,6 +902,7 @@ static bool dce110_program_pix_clk( #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case DCN_VERSION_1_0: #endif + if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index f30cd4dff554..37d074f595fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -614,7 +614,7 @@ static bool dce_apply_clock_voltage_request( } if (send_request) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (clk->ctx->dce_version == DCN_VERSION_1_0) { + if (clk->ctx->dce_version >= DCN_VERSION_1_0) { struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); /*use dcfclk request voltage*/ clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index aa4777a8ec36..119365960cd0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1104,11 +1104,11 @@ static enum dc_status apply_single_controller_ctx_to_hw( true : false); resource_build_info_frame(pipe_ctx); - + dce110_update_info_frame(pipe_ctx); if (!pipe_ctx_old->stream) { core_link_enable_stream(pipe_ctx); - dce110_update_info_frame(pipe_ctx); + if (dc_is_dp_signal(pipe_ctx->stream->signal)) dce110_unblank_stream(pipe_ctx, &stream->sink->link->cur_link_settings); @@ -1664,7 +1664,7 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (dc->ctx->dce_version == DCN_VERSION_1_0) { + if (dc->ctx->dce_version >= DCN_VERSION_1_0) { if (context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.cur_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 8a8b619a60a8..425f1c4fa891 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -84,6 +84,7 @@ bool dal_hw_factory_init( dal_hw_factory_dcn10_init(factory); return true; #endif + default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 36c082bda4ae..3b55d45b6775 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -80,6 +80,7 @@ bool dal_hw_translate_init( dal_hw_translate_dcn10_init(translate); return true; #endif + default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index 45e766ea79e3..10061cc4ba31 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -88,10 +88,11 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce100_create(ctx); case DCE_VERSION_12_0: return dal_i2caux_dce120_create(ctx); - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) case DCN_VERSION_1_0: return dal_i2caux_dcn10_create(ctx); - #endif +#endif + default: BREAK_TO_DEBUGGER(); return NULL; -- cgit v1.2.3-59-g8ed1b From 4fa086b9b6640818c053c79d4d7104790ba76cb7 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 25 Jul 2017 20:51:26 -0400 Subject: drm/amd/display: Roll core_stream into dc_stream Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 10 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 16 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 92 ++++---- drivers/gpu/drm/amd/display/dc/core/dc.c | 107 ++++----- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 41 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 259 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 118 +++++----- drivers/gpu/drm/amd/display/dc/dc.h | 71 +++--- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 12 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 176 +++++++------- .../drm/amd/display/dc/dce110/dce110_resource.c | 46 ++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 12 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 72 +++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 33 +-- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 14 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 60 +++-- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 28 +-- 31 files changed, 612 insertions(+), 649 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 696a4112c8d9..c802437f4858 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1401,7 +1401,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, num_streams = dc_get_current_stream_count(adev->dm.dc); for (i = 0; i < num_streams; i++) { - const struct dc_stream *stream; + struct dc_stream *stream; stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 0fcd9b373172..80d4e2670cc2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2196,7 +2196,7 @@ static bool is_scaling_state_different( static void remove_stream( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - const struct dc_stream *stream) + struct dc_stream *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -2351,7 +2351,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, uint32_t i; struct drm_plane *plane; struct drm_plane_state *old_plane_state; - const struct dc_stream *dc_stream_attach; + struct dc_stream *dc_stream_attach; struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); @@ -2487,7 +2487,7 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc *crtc, *pcrtc; struct drm_crtc_state *old_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - const struct dc_stream *new_stream; + struct dc_stream *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -2822,8 +2822,8 @@ static uint32_t add_val_sets_surface( static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *old_stream, - const struct dc_stream *new_stream, + struct dc_stream *old_stream, + struct dc_stream *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index c565787cd782..94de6a3736fc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -45,7 +45,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - const struct dc_stream *stream; + struct dc_stream *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 5ef44ff4bcf8..9a850227eeeb 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2610,9 +2610,9 @@ static void populate_initial_data( data->fbc_en[num_displays + 4] = false; data->lpt_en[num_displays + 4] = false; - data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total); - data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total); - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000); + data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); + data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); @@ -2707,9 +2707,9 @@ static void populate_initial_data( data->fbc_en[num_displays + 4] = false; data->lpt_en[num_displays + 4] = false; - data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total); - data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total); - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000); + data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); + data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); if (pipe[i].surface) { data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; @@ -2759,9 +2759,9 @@ static void populate_initial_data( break; } } else { - data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_addressable); + data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; - data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_addressable); + data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable); data->h_taps[num_displays + 4] = bw_int_to_fixed(1); data->v_taps[num_displays + 4] = bw_int_to_fixed(1); data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1); diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1651b7548d40..ef10a8b49379 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -365,7 +365,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } - input->dest.vactive = pipe->stream->public.timing.v_addressable; + input->dest.vactive = pipe->stream->timing.v_addressable; input->dest.recout_width = pipe->scl_data.recout.width; input->dest.recout_height = pipe->scl_data.recout.height; @@ -373,24 +373,24 @@ static void pipe_ctx_to_e2e_pipe_params ( input->dest.full_recout_width = pipe->scl_data.recout.width; input->dest.full_recout_height = pipe->scl_data.recout.height; - input->dest.htotal = pipe->stream->public.timing.h_total; - input->dest.hblank_start = input->dest.htotal - pipe->stream->public.timing.h_front_porch; + input->dest.htotal = pipe->stream->timing.h_total; + input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; input->dest.hblank_end = input->dest.hblank_start - - pipe->stream->public.timing.h_addressable - - pipe->stream->public.timing.h_border_left - - pipe->stream->public.timing.h_border_right; + - pipe->stream->timing.h_addressable + - pipe->stream->timing.h_border_left + - pipe->stream->timing.h_border_right; - input->dest.vtotal = pipe->stream->public.timing.v_total; - input->dest.vblank_start = input->dest.vtotal - pipe->stream->public.timing.v_front_porch; + input->dest.vtotal = pipe->stream->timing.v_total; + input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; input->dest.vblank_end = input->dest.vblank_start - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_border_bottom - - pipe->stream->public.timing.v_border_top; - - input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_front_porch; - input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0; + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_border_bottom + - pipe->stream->timing.v_border_top; + + input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_front_porch; + input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0; input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; @@ -851,14 +851,14 @@ bool dcn_validate_bandwidth( v->underscan_output[input_idx] = false; /* taken care of in recout already*/ v->interlace_output[input_idx] = false; - v->htotal[input_idx] = pipe->stream->public.timing.h_total; - v->vtotal[input_idx] = pipe->stream->public.timing.v_total; - v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_front_porch; - v->vactive[input_idx] = pipe->stream->public.timing.v_addressable; - v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f; - if (pipe->stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + v->htotal[input_idx] = pipe->stream->timing.h_total; + v->vtotal[input_idx] = pipe->stream->timing.v_total; + v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_front_porch; + v->vactive[input_idx] = pipe->stream->timing.v_addressable; + v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; + if (pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) v->pixel_clock[input_idx] /= 2; @@ -867,10 +867,10 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; v->lb_bit_per_pixel[input_idx] = 30; - v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable; - v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable; - v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable; - v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable; + v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; + v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; + v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable; + v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable; v->override_hta_ps[input_idx] = 1; v->override_vta_ps[input_idx] = 1; v->override_hta_pschroma[input_idx] = 1; @@ -995,22 +995,22 @@ bool dcn_validate_bandwidth( pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; - pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total; - pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total; - vesa_sync_start = pipe->stream->public.timing.v_addressable + - pipe->stream->public.timing.v_border_bottom + - pipe->stream->public.timing.v_front_porch; + pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; + pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; + vesa_sync_start = pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_bottom + + pipe->stream->timing.v_front_porch; - asic_blank_end = (pipe->stream->public.timing.v_total - + asic_blank_end = (pipe->stream->timing.v_total - vesa_sync_start - - pipe->stream->public.timing.v_border_top) - * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0); + pipe->stream->timing.v_border_top) + * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); asic_blank_start = asic_blank_end + - (pipe->stream->public.timing.v_border_top + - pipe->stream->public.timing.v_addressable + - pipe->stream->public.timing.v_border_bottom) - * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0); + (pipe->stream->timing.v_border_top + + pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_bottom) + * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe->pipe_dlg_param.vblank_end = asic_blank_end; @@ -1019,13 +1019,13 @@ bool dcn_validate_bandwidth( struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; if (v->dpp_per_plane[input_idx] == 2 || - ((pipe->stream->public.view_format == + ((pipe->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || - pipe->stream->public.view_format == + pipe->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) && - (pipe->stream->public.timing.timing_3d_format == + (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM || - pipe->stream->public.timing.timing_3d_format == + pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE))) { if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { /* update previously split pipe */ @@ -1034,8 +1034,8 @@ bool dcn_validate_bandwidth( hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; - hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total; - hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total; + hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; + hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; } else { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bab07f8d4880..df8c5ca6b22a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -149,19 +149,19 @@ failed_alloc: } static bool stream_adjust_vmin_vmax(struct dc *dc, - const struct dc_stream **stream, int num_streams, + struct dc_stream **streams, int num_streams, int vmin, int vmax) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct dc_stream *stream = streams[0]; int i = 0; bool ret = false; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == core_stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_enc) { core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); /* build and update the info frame */ @@ -175,12 +175,12 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, } static bool stream_get_crtc_position(struct dc *dc, - const struct dc_stream **stream, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct dc_stream *stream = streams[0]; int i = 0; bool ret = false; struct crtc_position position; @@ -189,7 +189,7 @@ static bool stream_get_crtc_position(struct dc *dc, struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == core_stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_enc) { core_dc->hwss.get_position(&pipe, 1, &position); *v_pos = position.vertical_count; @@ -203,15 +203,12 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { - + if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; core_dc->hwss.program_gamut_remap(pipes); ret = true; @@ -221,22 +218,21 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) return ret; } -static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream) +static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { + == stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; core_dc->hwss.program_csc_matrix(pipes, - core_stream->public.output_color_space, - core_stream->public.csc_color_matrix.matrix); + stream->output_color_space, + stream->csc_color_matrix.matrix); ret = true; } } @@ -245,7 +241,7 @@ static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream) } static void set_static_screen_events(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **streams, int num_streams, const struct dc_static_screen_events *events) { @@ -256,11 +252,11 @@ static void set_static_screen_events(struct dc *dc, int num_pipes_affected = 0; for (i = 0; i < num_streams; i++) { - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]); + struct dc_stream *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { if (core_dc->current_context->res_ctx.pipe_ctx[j].stream - == core_stream) { + == stream) { pipes_affected[num_pipes_affected++] = &core_dc->current_context->res_ctx.pipe_ctx[j]; } @@ -337,10 +333,9 @@ static void set_test_pattern( cust_pattern_size); } -void set_dither_option(const struct dc_stream *dc_stream, +void set_dither_option(struct dc_stream *stream, enum dc_dither_option option) { - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; @@ -351,21 +346,21 @@ void set_dither_option(const struct dc_stream *dc_stream, if (option > DITHER_OPTION_MAX) return; if (option == DITHER_OPTION_DEFAULT) { - switch (stream->public.timing.display_color_depth) { + switch (stream->timing.display_color_depth) { case COLOR_DEPTH_666: - stream->public.dither_option = DITHER_OPTION_SPATIAL6; + stream->dither_option = DITHER_OPTION_SPATIAL6; break; case COLOR_DEPTH_888: - stream->public.dither_option = DITHER_OPTION_SPATIAL8; + stream->dither_option = DITHER_OPTION_SPATIAL8; break; case COLOR_DEPTH_101010: - stream->public.dither_option = DITHER_OPTION_SPATIAL10; + stream->dither_option = DITHER_OPTION_SPATIAL10; break; default: option = DITHER_OPTION_DISABLE; } } else { - stream->public.dither_option = option; + stream->dither_option = option; } resource_build_bit_depth_reduction_params(stream, ¶ms); @@ -644,7 +639,7 @@ static bool is_validation_required( if (set[i].surface_count != context->stream_status[i].surface_count) return true; - if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) + if (!is_stream_unchanged(set[i].stream, context->streams[i])) return true; for (j = 0; j < set[i].surface_count; j++) { @@ -754,7 +749,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_stream *stream) + struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -869,7 +864,7 @@ static bool context_changed( return true; for (i = 0; i < dc->current_context->stream_count; i++) { - if (&dc->current_context->streams[i]->public != &context->streams[i]->public) + if (dc->current_context->streams[i] != context->streams[i]) return true; } @@ -878,7 +873,7 @@ static bool context_changed( static bool streams_changed( struct core_dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { uint8_t i; @@ -887,7 +882,7 @@ static bool streams_changed( return true; for (i = 0; i < dc->current_context->stream_count; i++) { - if (&dc->current_context->streams[i]->public != streams[i]) + if (dc->current_context->streams[i] != streams[i]) return true; } @@ -897,7 +892,7 @@ static bool streams_changed( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { bool ret = true; @@ -915,7 +910,7 @@ bool dc_enable_stereo( else pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { - if (streams[j] && streams[j] == &pipe->stream->public && + if (streams[j] && streams[j] == pipe->stream && core_dc->hwss.setup_stereo) core_dc->hwss.setup_stereo(pipe, core_dc); } @@ -943,10 +938,10 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; - const struct dc_stream *dc_streams[MAX_STREAMS] = {0}; + struct dc_stream *dc_streams[MAX_STREAMS] = {0}; for (i = 0; i < context->stream_count; i++) - dc_streams[i] = &context->streams[i]->public; + dc_streams[i] = context->streams[i]; if (!dcb->funcs->is_accelerated_mode(dcb)) core_dc->hwss.enable_accelerated_mode(core_dc); @@ -985,11 +980,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", - context->streams[i]->public.timing.h_addressable, - context->streams[i]->public.timing.v_addressable, - context->streams[i]->public.timing.h_total, - context->streams[i]->public.timing.v_total, - context->streams[i]->public.timing.pix_clk_khz); + context->streams[i]->timing.h_addressable, + context->streams[i]->timing.v_addressable, + context->streams[i]->timing.h_total, + context->streams[i]->timing.v_total, + context->streams[i]->timing.pix_clk_khz); } dc_enable_stereo(dc, context, dc_streams, context->stream_count); @@ -1016,7 +1011,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { - const struct dc_stream *stream = &context->streams[i]->public; + struct dc_stream *stream = context->streams[i]; dc_stream_log(stream, core_dc->ctx->logger, @@ -1031,7 +1026,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_commit_streams( struct dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1047,8 +1042,8 @@ bool dc_commit_streams( __func__, stream_count); for (i = 0; i < stream_count; i++) { - const struct dc_stream *stream = streams[i]; - const struct dc_stream_status *status = dc_stream_get_status(stream); + struct dc_stream *stream = streams[i]; + struct dc_stream_status *status = dc_stream_get_status(stream); int j; dc_stream_log(stream, @@ -1120,7 +1115,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_surface **new_surfaces, uint8_t new_surface_count, - const struct dc_stream *dc_stream) + struct dc_stream *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -1377,7 +1372,7 @@ enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct dc_stream_update *stream_update) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1385,7 +1380,6 @@ void dc_update_surfaces_and_stream(struct dc *dc, int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct dc_context *dc_ctx = core_dc->ctx; /* Currently this function do not result in any HW programming @@ -1398,7 +1392,8 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (surface_count == 0) return; - stream_status = dc_stream_get_status(dc_stream); + stream_status = dc_stream_get_status(stream); + ASSERT(stream_status); if (!stream_status) return; /* Cannot commit surface to stream that is not committed */ @@ -1415,19 +1410,19 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (stream_update) { if ((stream_update->src.height != 0) && (stream_update->src.width != 0)) - stream->public.src = stream_update->src; + stream->src = stream_update->src; if ((stream_update->dst.height != 0) && (stream_update->dst.width != 0)) - stream->public.dst = stream_update->dst; + stream->dst = stream_update->dst; if (stream_update->out_transfer_func && stream_update->out_transfer_func != - dc_stream->out_transfer_func) { - if (dc_stream->out_transfer_func != NULL) - dc_transfer_func_release(dc_stream->out_transfer_func); + stream->out_transfer_func) { + if (stream->out_transfer_func != NULL) + dc_transfer_func_release(stream->out_transfer_func); dc_transfer_func_retain(stream_update->out_transfer_func); - stream->public.out_transfer_func = + stream->out_transfer_func = stream_update->out_transfer_func; } } @@ -1469,7 +1464,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, dc_stream, + new_surfaces, surface_count, stream, context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; @@ -1617,7 +1612,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, core_dc, pipe_ctx->surface, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ - dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position); + dc_stream_set_cursor_position(pipe_ctx->stream, &position); if (is_new_pipe_surface) { core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); @@ -1712,7 +1707,7 @@ struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); if (i < core_dc->current_context->stream_count) - return &(core_dc->current_context->streams[i]->public); + return core_dc->current_context->streams[i]; return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 9a5df3a848b5..bf127a88e533 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -321,8 +321,8 @@ void context_timing_trace( TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", pipe_ctx->tg->inst, - pipe_ctx->stream->public.timing.h_total, - pipe_ctx->stream->public.timing.v_total, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, h_pos[i], v_pos[i]); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fd2ae181cff2..2487046457c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; @@ -1151,7 +1151,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) &downspread.raw, sizeof(downspread)); downspread.bits.IGNORE_MSA_TIMING_PARAM = - (stream->public.ignore_msa_timing_param) ? 1 : 0; + (stream->ignore_msa_timing_param) ? 1 : 0; core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, &downspread.raw, sizeof(downspread)); @@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; struct dc_link *link = stream->sink->link; @@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; @@ -1258,13 +1258,13 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) dal_ddc_service_write_scdc_data( stream->sink->link->ddc, stream->phy_pix_clk, - stream->public.timing.flags.LTE_340MCSC_SCRAMBLE); + stream->timing.flags.LTE_340MCSC_SCRAMBLE); memset(&stream->sink->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); - display_color_depth = stream->public.timing.display_color_depth; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + display_color_depth = stream->timing.display_color_depth; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) display_color_depth = COLOR_DEPTH_888; link->link_enc->funcs->enable_tmds_output( @@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) } enum dc_status dc_link_validate_mode_timing( - const struct core_stream *stream, + const struct dc_stream *stream, struct dc_link *link, const struct dc_crtc_timing *timing) { @@ -1377,7 +1377,6 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); - struct core_stream *core_stream = NULL; struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; @@ -1390,11 +1389,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { - core_stream = DC_STREAM_TO_CORE(stream); for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx. pipe_ctx[i].stream - == core_stream) + == stream) /* DMCU -1 for all controller id values, * therefore +1 here */ @@ -1457,7 +1455,6 @@ bool dc_link_setup_psr(struct dc_link *link, { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; @@ -1501,7 +1498,7 @@ bool dc_link_setup_psr(struct dc_link *link, for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { + == stream) { /* dmcu -1 for all controller id values, * therefore +1 here */ @@ -1590,7 +1587,7 @@ void core_link_resume(struct dc_link *link) program_hpd_filter(link); } -static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream) +static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream) { struct dc_link_settings *link_settings = &stream->sink->link->cur_link_settings; @@ -1699,7 +1696,7 @@ static void update_mst_stream_alloc_table( */ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1717,7 +1714,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) /* get calculate VC payload for stream: stream_alloc */ if (dm_helpers_dp_mst_write_payload_allocation_table( stream->ctx, - &stream->public, + stream, &proposed_table, true)) { update_mst_stream_alloc_table( @@ -1759,11 +1756,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) /* send down message */ dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, - &stream->public); + stream); dm_helpers_dp_mst_send_payload_allocation( stream->ctx, - &stream->public, + stream, true); /* slot X.Y for only current stream */ @@ -1781,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1806,7 +1803,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) if (mst_mode) { if (dm_helpers_dp_mst_write_payload_allocation_table( stream->ctx, - &stream->public, + stream, &proposed_table, false)) { @@ -1848,11 +1845,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) if (mst_mode) { dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, - &stream->public); + stream); dm_helpers_dp_mst_send_payload_allocation( stream->ctx, - &stream->public, + stream, false); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c7b400786121..d9754b5f2543 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1434,7 +1434,7 @@ bool dp_validate_mode_timing( return false; } -void decide_link_settings(struct core_stream *stream, +void decide_link_settings(struct dc_stream *stream, struct dc_link_settings *link_setting) { @@ -1446,8 +1446,7 @@ void decide_link_settings(struct core_stream *stream, uint32_t req_bw; uint32_t link_bw; - req_bw = bandwidth_in_kbps_from_timing( - &stream->public.timing); + req_bw = bandwidth_in_kbps_from_timing(&stream->timing); link = stream->sink->link; @@ -2327,7 +2326,7 @@ static void set_crtc_test_pattern(struct dc_link *link, { enum controller_dp_test_pattern controller_test_pattern; enum dc_color_depth color_depth = pipe_ctx-> - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; struct bit_depth_reduction_params params; memset(¶ms, 0, sizeof(params)); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 5bdcd5067116..76dc16916821 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -78,7 +78,7 @@ void dp_enable_link_phy( pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { pipes[i].clock_source = dp_cs; pipes[i].pix_clk_params.requested_pix_clk = - pipes[i].stream->public.timing.pix_clk_khz; + pipes[i].stream->timing.pix_clk_khz; pipes[i].clock_source->funcs->program_pix_clk( pipes[i].clock_source, &pipes[i].pix_clk_params, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index eeefc9c33633..ddbd3de63a8d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -294,25 +294,25 @@ void resource_reference_clock_source( } bool resource_are_streams_timing_synchronizable( - const struct core_stream *stream1, - const struct core_stream *stream2) + struct dc_stream *stream1, + struct dc_stream *stream2) { - if (stream1->public.timing.h_total != stream2->public.timing.h_total) + if (stream1->timing.h_total != stream2->timing.h_total) return false; - if (stream1->public.timing.v_total != stream2->public.timing.v_total) + if (stream1->timing.v_total != stream2->timing.v_total) return false; - if (stream1->public.timing.h_addressable - != stream2->public.timing.h_addressable) + if (stream1->timing.h_addressable + != stream2->timing.h_addressable) return false; - if (stream1->public.timing.v_addressable - != stream2->public.timing.v_addressable) + if (stream1->timing.v_addressable + != stream2->timing.v_addressable) return false; - if (stream1->public.timing.pix_clk_khz - != stream2->public.timing.pix_clk_khz) + if (stream1->timing.pix_clk_khz + != stream2->timing.pix_clk_khz) return false; if (stream1->phy_pix_clk != stream2->phy_pix_clk @@ -431,7 +431,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - const struct dc_stream *stream = &pipe_ctx->stream->public; + const struct dc_stream *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; @@ -530,7 +530,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { const struct dc_surface *surface = pipe_ctx->surface; - struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; @@ -539,38 +539,38 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->surface->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); - pipe_ctx->scl_data.recout.x = stream->public.dst.x; - if (stream->public.src.x < surf_clip.x) + pipe_ctx->scl_data.recout.x = stream->dst.x; + if (stream->src.x < surf_clip.x) pipe_ctx->scl_data.recout.x += (surf_clip.x - - stream->public.src.x) * stream->public.dst.width - / stream->public.src.width; + - stream->src.x) * stream->dst.width + / stream->src.width; pipe_ctx->scl_data.recout.width = surf_clip.width * - stream->public.dst.width / stream->public.src.width; + stream->dst.width / stream->src.width; if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x > - stream->public.dst.x + stream->public.dst.width) + stream->dst.x + stream->dst.width) pipe_ctx->scl_data.recout.width = - stream->public.dst.x + stream->public.dst.width + stream->dst.x + stream->dst.width - pipe_ctx->scl_data.recout.x; - pipe_ctx->scl_data.recout.y = stream->public.dst.y; - if (stream->public.src.y < surf_clip.y) + pipe_ctx->scl_data.recout.y = stream->dst.y; + if (stream->src.y < surf_clip.y) pipe_ctx->scl_data.recout.y += (surf_clip.y - - stream->public.src.y) * stream->public.dst.height - / stream->public.src.height; + - stream->src.y) * stream->dst.height + / stream->src.height; pipe_ctx->scl_data.recout.height = surf_clip.height * - stream->public.dst.height / stream->public.src.height; + stream->dst.height / stream->src.height; if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y > - stream->public.dst.y + stream->public.dst.height) + stream->dst.y + stream->dst.height) pipe_ctx->scl_data.recout.height = - stream->public.dst.y + stream->public.dst.height + stream->dst.y + stream->dst.height - pipe_ctx->scl_data.recout.y; /* Handle h & vsplit */ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { - if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { + if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; /* Floor primary pipe, ceil 2ndary pipe */ @@ -582,7 +582,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip } } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { - if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else pipe_ctx->scl_data.recout.width /= 2; @@ -592,14 +592,14 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) */ - recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x) - * stream->public.dst.width / stream->public.src.width - + recout_full_x = stream->dst.x + (surface->dst_rect.x - stream->src.x) + * stream->dst.width / stream->src.width - surf_src.x * surface->dst_rect.width / surf_src.width - * stream->public.dst.width / stream->public.src.width; - recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y) - * stream->public.dst.height / stream->public.src.height - + * stream->dst.width / stream->src.width; + recout_full_y = stream->dst.y + (surface->dst_rect.y - stream->src.y) + * stream->dst.height / stream->src.height - surf_src.y * surface->dst_rect.height / surf_src.height - * stream->public.dst.height / stream->public.src.height; + * stream->dst.height / stream->src.height; recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y; @@ -608,12 +608,12 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; - const int in_w = stream->public.src.width; - const int in_h = stream->public.src.height; - const int out_w = stream->public.dst.width; - const int out_h = stream->public.dst.height; + const int in_w = stream->src.width; + const int in_h = stream->src.height; + const int out_w = stream->dst.width; + const int out_h = stream->dst.height; if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || pipe_ctx->surface->rotation == ROTATION_ANGLE_270) @@ -626,9 +626,9 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) surf_src.height, surface->dst_rect.height); - if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) + if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; - else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.ratios.vert.value *= 2; pipe_ctx->scl_data.ratios.vert.value = div64_s64( @@ -815,7 +815,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -920,7 +920,7 @@ struct pipe_ctx *find_idle_secondary_pipe( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - const struct core_stream *stream) + struct dc_stream *stream) { int i; for (i = 0; i < MAX_PIPES; i++) { @@ -940,11 +940,10 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, const struct resource_pool *pool, - const struct dc_stream *dc_stream) + struct dc_stream *stream) { int i; struct resource_context *res_ctx = &context->res_ctx; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -980,10 +979,9 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( static void release_free_pipes_for_stream( struct resource_context *res_ctx, - const struct dc_stream *dc_stream) + struct dc_stream *stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = MAX_PIPES - 1; i >= 0; i--) { /* never release the topmost pipe*/ @@ -999,7 +997,7 @@ static void release_free_pipes_for_stream( static int acquire_first_split_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; @@ -1033,14 +1031,13 @@ static int acquire_first_split_pipe( bool resource_attach_surfaces_to_context( struct dc_surface * const *surfaces, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct validate_context *context, const struct resource_pool *pool) { int i; struct pipe_ctx *tail_pipe; struct dc_stream_status *stream_status = NULL; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); if (surface_count > MAX_SURFACE_NUM) { @@ -1050,7 +1047,7 @@ bool resource_attach_surfaces_to_context( } for (i = 0; i < context->stream_count; i++) - if (&context->streams[i]->public == dc_stream) { + if (context->streams[i] == stream) { stream_status = &context->stream_status[i]; break; } @@ -1081,7 +1078,7 @@ bool resource_attach_surfaces_to_context( for (i = 0; i < surface_count; i++) { struct dc_surface *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - context, pool, dc_stream); + context, pool, stream); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (!free_pipe) { @@ -1109,7 +1106,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = free_pipe; } - release_free_pipes_for_stream(&context->res_ctx, dc_stream); + release_free_pipes_for_stream(&context->res_ctx, stream); /* assign new surfaces*/ for (i = 0; i < surface_count; i++) @@ -1121,8 +1118,8 @@ bool resource_attach_surfaces_to_context( } -static bool is_timing_changed(const struct core_stream *cur_stream, - const struct core_stream *new_stream) +static bool is_timing_changed(struct dc_stream *cur_stream, + struct dc_stream *new_stream) { if (cur_stream == NULL) return true; @@ -1134,18 +1131,17 @@ static bool is_timing_changed(const struct core_stream *cur_stream, return true; /* If output color space is changed, need to reprogram info frames */ - if (cur_stream->public.output_color_space != - new_stream->public.output_color_space) + if (cur_stream->output_color_space != new_stream->output_color_space) return true; return memcmp( - &cur_stream->public.timing, - &new_stream->public.timing, + &cur_stream->timing, + &new_stream->timing, sizeof(struct dc_crtc_timing)) != 0; } static bool are_stream_backends_same( - const struct core_stream *stream_a, const struct core_stream *stream_b) + struct dc_stream *stream_a, struct dc_stream *stream_b) { if (stream_a == stream_b) return true; @@ -1160,7 +1156,7 @@ static bool are_stream_backends_same( } bool is_stream_unchanged( - const struct core_stream *old_stream, const struct core_stream *stream) + struct dc_stream *old_stream, struct dc_stream *stream) { if (!are_stream_backends_same(old_stream, stream)) @@ -1186,7 +1182,7 @@ bool resource_validate_attach_surfaces( if (!resource_attach_surfaces_to_context( old_context->stream_status[j].surfaces, old_context->stream_status[j].surface_count, - &context->streams[i]->public, + context->streams[i], context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; @@ -1195,7 +1191,7 @@ bool resource_validate_attach_surfaces( if (!resource_attach_surfaces_to_context( set[i].surfaces, set[i].surface_count, - &context->streams[i]->public, + context->streams[i], context, pool)) return false; @@ -1237,7 +1233,7 @@ static void set_audio_in_use( static int acquire_first_free_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; @@ -1267,7 +1263,7 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; int j = -1; @@ -1318,22 +1314,22 @@ static struct audio *find_first_free_audio( return 0; } -static void update_stream_signal(struct core_stream *stream) +static void update_stream_signal(struct dc_stream *stream) { - if (stream->public.output_signal == SIGNAL_TYPE_NONE) { - struct dc_sink *dc_sink = stream->public.sink; + if (stream->output_signal == SIGNAL_TYPE_NONE) { + struct dc_sink *dc_sink = stream->sink; if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) stream->signal = stream->sink->link->connector_signal; else stream->signal = dc_sink->sink_signal; } else { - stream->signal = stream->public.output_signal; + stream->signal = stream->output_signal; } if (dc_is_dvi_signal(stream->signal)) { - if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && - stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) + if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && + stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; else stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; @@ -1341,12 +1337,12 @@ static void update_stream_signal(struct core_stream *stream) } bool resource_is_stream_unchanged( - const struct validate_context *old_context, const struct core_stream *stream) + struct validate_context *old_context, struct dc_stream *stream) { int i; for (i = 0; i < old_context->stream_count; i++) { - const struct core_stream *old_stream = old_context->streams[i]; + struct dc_stream *old_stream = old_context->streams[i]; if (are_stream_backends_same(old_stream, stream)) return true; @@ -1359,7 +1355,7 @@ static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { struct dc_surface *surface = to_pipe_ctx->surface; - struct core_stream *stream = to_pipe_ctx->stream; + struct dc_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; @@ -1367,14 +1363,14 @@ static void copy_pipe_ctx( to_pipe_ctx->surface = surface; } -static struct core_stream *find_pll_sharable_stream( - const struct core_stream *stream_needs_pll, +static struct dc_stream *find_pll_sharable_stream( + struct dc_stream *stream_needs_pll, struct validate_context *context) { int i; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream_has_pll = context->streams[i]; + struct dc_stream *stream_has_pll = context->streams[i]; /* We are looking for non dp, non virtual stream */ if (resource_are_streams_timing_synchronizable( @@ -1418,17 +1414,17 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct core_stream *stream) +static void calculate_phy_pix_clks(struct dc_stream *stream) { update_stream_signal(stream); /* update actual pixel clock on all streams */ if (dc_is_hdmi_signal(stream->signal)) stream->phy_pix_clk = get_norm_pix_clk( - &stream->public.timing); + &stream->timing); else stream->phy_pix_clk = - stream->public.timing.pix_clk_khz; + stream->timing.pix_clk_khz; } enum dc_status resource_map_pool_resources( @@ -1440,7 +1436,7 @@ enum dc_status resource_map_pool_resources( int i, j; for (i = 0; old_context && i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -1493,7 +1489,7 @@ enum dc_status resource_map_pool_resources( } for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; @@ -1524,7 +1520,7 @@ enum dc_status resource_map_pool_resources( /* TODO: Add check if ASIC support and EDID audio */ if (!stream->sink->converter_disable_audio && dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->public.audio_info.mode_count) { + stream->audio_info.mode_count) { pipe_ctx->audio = find_first_free_audio( &context->res_ctx, pool); @@ -1560,7 +1556,7 @@ void validate_guaranteed_copy_streams( context->res_ctx.pipe_ctx[i].stream = context->res_ctx.pipe_ctx[0].stream; - dc_stream_retain(&context->streams[i]->public); + dc_stream_retain(context->streams[i]); context->stream_count++; } } @@ -1588,7 +1584,7 @@ static void set_avi_info_frame( struct encoder_info_packet *info_packet, struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; struct info_frame info_frame = { {0} }; uint32_t pixel_encoding = 0; @@ -1602,12 +1598,12 @@ static void set_avi_info_frame( uint8_t byte_index = 0; union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; union display_content_support support = {0}; - unsigned int vic = pipe_ctx->stream->public.timing.vic; + unsigned int vic = pipe_ctx->stream->timing.vic; enum dc_timing_3d_format format; - color_space = pipe_ctx->stream->public.output_color_space; + color_space = pipe_ctx->stream->output_color_space; if (color_space == COLOR_SPACE_UNKNOWN) - color_space = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_RGB)? + color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; /* Initialize header */ @@ -1622,7 +1618,7 @@ static void set_avi_info_frame( * according to HDMI 2.0 spec (Section 10.1) */ - switch (stream->public.timing.pixel_encoding) { + switch (stream->timing.pixel_encoding) { case PIXEL_ENCODING_YCBCR422: pixel_encoding = 1; break; @@ -1664,7 +1660,7 @@ static void set_avi_info_frame( color_space == COLOR_SPACE_YCBCR601_LIMITED) hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601; else { - if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) BREAK_TO_DEBUGGER(); hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA; } @@ -1679,7 +1675,7 @@ static void set_avi_info_frame( } /* TODO: un-hardcode aspect ratio */ - aspect = stream->public.timing.aspect_ratio; + aspect = stream->timing.aspect_ratio; switch (aspect) { case ASPECT_RATIO_4_3: @@ -1705,7 +1701,7 @@ static void set_avi_info_frame( itc = true; itc_value = 1; - support = stream->public.sink->edid_caps.content_support; + support = stream->sink->edid_caps.content_support; if (itc) { if (!support.bits.valid_content_type) { @@ -1744,8 +1740,8 @@ static void set_avi_info_frame( /* TODO : We should handle YCC quantization */ /* but we do not have matrix calculation */ - if (stream->public.sink->edid_caps.qs_bit == 1 && - stream->public.sink->edid_caps.qy_bit == 1) { + if (stream->sink->edid_caps.qs_bit == 1 && + stream->sink->edid_caps.qy_bit == 1) { if (color_space == COLOR_SPACE_SRGB || color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; @@ -1764,11 +1760,11 @@ static void set_avi_info_frame( } ///VIC - format = stream->public.timing.timing_3d_format; + format = stream->timing.timing_3d_format; /*todo, add 3DStereo support*/ if (format != TIMING_3D_FORMAT_NONE) { // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled - switch (pipe_ctx->stream->public.timing.hdmi_vic) { + switch (pipe_ctx->stream->timing.hdmi_vic) { case 1: vic = 95; break; @@ -1797,12 +1793,12 @@ static void set_avi_info_frame( * barBottom: Line Number of Start of Bottom Bar. * barLeft: Pixel Number of End of Left Bar. * barRight: Pixel Number of Start of Right Bar. */ - hdmi_info->bits.bar_top = stream->public.timing.v_border_top; - hdmi_info->bits.bar_bottom = (stream->public.timing.v_total - - stream->public.timing.v_border_bottom + 1); - hdmi_info->bits.bar_left = stream->public.timing.h_border_left; - hdmi_info->bits.bar_right = (stream->public.timing.h_total - - stream->public.timing.h_border_right + 1); + hdmi_info->bits.bar_top = stream->timing.v_border_top; + hdmi_info->bits.bar_bottom = (stream->timing.v_total + - stream->timing.v_border_bottom + 1); + hdmi_info->bits.bar_left = stream->timing.h_border_left; + hdmi_info->bits.bar_right = (stream->timing.h_total + - stream->timing.h_border_right + 1); /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0]; @@ -1830,7 +1826,7 @@ static void set_avi_info_frame( static void set_vendor_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { uint32_t length = 0; bool hdmi_vic_mode = false; @@ -1842,16 +1838,16 @@ static void set_vendor_info_packet( info_packet->valid = false; - format = stream->public.timing.timing_3d_format; - if (stream->public.view_format == VIEW_3D_FORMAT_NONE) + format = stream->timing.timing_3d_format; + if (stream->view_format == VIEW_3D_FORMAT_NONE) format = TIMING_3D_FORMAT_NONE; /* Can be different depending on packet content */ length = 5; - if (stream->public.timing.hdmi_vic != 0 - && stream->public.timing.h_total >= 3840 - && stream->public.timing.v_total >= 2160) + if (stream->timing.hdmi_vic != 0 + && stream->timing.h_total >= 3840 + && stream->timing.v_total >= 2160) hdmi_vic_mode = true; /* According to HDMI 1.4a CTS, VSIF should be sent @@ -1918,7 +1914,7 @@ static void set_vendor_info_packet( /*PB5: If PB4 is set to 0x1 (extended resolution format) * fill PB5 with the correct HDMI VIC code */ if (hdmi_vic_mode) - info_packet->sb[5] = stream->public.timing.hdmi_vic; + info_packet->sb[5] = stream->timing.hdmi_vic; /* Header */ info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */ @@ -1943,7 +1939,7 @@ static void set_vendor_info_packet( static void set_spd_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { /* SPD info packet for FreeSync */ @@ -1953,7 +1949,7 @@ static void set_spd_info_packet( /* Check if Freesync is supported. Return if false. If true, * set the corresponding bit in the info packet */ - if (stream->public.freesync_ctx.supported == false) + if (stream->freesync_ctx.supported == false) return; if (dc_is_hdmi_signal(stream->signal)) { @@ -2018,20 +2014,20 @@ static void set_spd_info_packet( /* PB6 = [Bits 7:3 = Reserved] */ info_packet->sb[6] = 0x00; - if (stream->public.freesync_ctx.supported == true) + if (stream->freesync_ctx.supported == true) /* PB6 = [Bit 0 = FreeSync Supported] */ info_packet->sb[6] |= 0x01; - if (stream->public.freesync_ctx.enabled == true) + if (stream->freesync_ctx.enabled == true) /* PB6 = [Bit 1 = FreeSync Enabled] */ info_packet->sb[6] |= 0x02; - if (stream->public.freesync_ctx.active == true) + if (stream->freesync_ctx.active == true) /* PB6 = [Bit 2 = FreeSync Active] */ info_packet->sb[6] |= 0x04; /* PB7 = FreeSync Minimum refresh rate (Hz) */ - info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx. + info_packet->sb[7] = (unsigned char) (stream->freesync_ctx. min_refresh_in_micro_hz / 1000000); /* PB8 = FreeSync Maximum refresh rate (Hz) @@ -2040,7 +2036,7 @@ static void set_spd_info_packet( * of the panel, because we should never go above the field * rate of the mode timing set. */ - info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx. + info_packet->sb[8] = (unsigned char) (stream->freesync_ctx. nominal_refresh_in_micro_hz / 1000000); /* PB9 - PB27 = Reserved */ @@ -2065,7 +2061,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, struct dc_surface *surface, - struct core_stream *stream) + struct dc_stream *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; @@ -2168,7 +2164,7 @@ static void set_hdr_static_info_packet( static void set_vsc_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { unsigned int vscPacketRevision = 0; unsigned int i; @@ -2218,7 +2214,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) context->stream_status[i].surfaces[j]); context->stream_status[i].surface_count = 0; - dc_stream_release(&context->streams[i]->public); + dc_stream_release(context->streams[i]); context->streams[i] = NULL; } } @@ -2248,7 +2244,7 @@ void dc_resource_validate_ctx_copy_construct( } for (i = 0; i < dst_ctx->stream_count; i++) { - dc_stream_retain(&dst_ctx->streams[i]->public); + dc_stream_retain(dst_ctx->streams[i]); for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) dc_surface_retain( dst_ctx->stream_status[i].surfaces[j]); @@ -2321,7 +2317,7 @@ enum dc_status resource_map_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - const struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -2401,12 +2397,12 @@ bool pipe_need_reprogram( return false; } -void resource_build_bit_depth_reduction_params(const struct core_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth) { - enum dc_dither_option option = stream->public.dither_option; + enum dc_dither_option option = stream->dither_option; enum dc_pixel_encoding pixel_encoding = - stream->public.timing.pixel_encoding; + stream->timing.pixel_encoding; memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); @@ -2511,31 +2507,30 @@ void resource_build_bit_depth_reduction_params(const struct core_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream) +bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_context *dc_ctx = core_dc->ctx; - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - struct dc_link *link = core_stream->sink->link; + struct dc_link *link = stream->sink->link; struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; enum dc_status res = DC_OK; - calculate_phy_pix_clks(core_stream); + calculate_phy_pix_clks(stream); - if (!tg->funcs->validate_timing(tg, &core_stream->public.timing)) + if (!tg->funcs->validate_timing(tg, &stream->timing)) res = DC_FAIL_CONTROLLER_VALIDATE; if (res == DC_OK) if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, core_stream)) + link->link_enc, stream)) res = DC_FAIL_ENC_VALIDATE; /* TODO: validate audio ASIC caps, encoder */ if (res == DC_OK) - res = dc_link_validate_mode_timing(core_stream, + res = dc_link_validate_mode_timing(stream, link, - &core_stream->public.timing); + &stream->timing); if (res != DC_OK) DC_ERROR("Failed validation for stream %p, err:%d, !\n", diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 5b356ddf5614..46ad1bc12f63 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -35,24 +35,24 @@ ******************************************************************************/ struct stream { - struct core_stream protected; + struct dc_stream protected; int ref_count; }; -#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected.public) +#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected) /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct core_stream *stream, +static bool construct(struct dc_stream *stream, struct dc_sink *dc_sink_data) { uint32_t i = 0; stream->sink = dc_sink_data; stream->ctx = stream->sink->ctx; - stream->public.sink = dc_sink_data; + stream->sink = dc_sink_data; dc_sink_retain(dc_sink_data); @@ -60,52 +60,52 @@ static bool construct(struct core_stream *stream, /* TODO - Remove this translation */ for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) { - stream->public.audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; - stream->public.audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; - stream->public.audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; - stream->public.audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; + stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; + stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; + stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; + stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; } - stream->public.audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; - stream->public.audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; - stream->public.audio_info.video_latency = dc_sink_data->edid_caps.video_latency; + stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; + stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; + stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; memmove( - stream->public.audio_info.display_name, + stream->audio_info.display_name, dc_sink_data->edid_caps.display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); - stream->public.audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; - stream->public.audio_info.product_id = dc_sink_data->edid_caps.product_id; - stream->public.audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; + stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; + stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; + stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; if (dc_sink_data->dc_container_id != NULL) { struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; - stream->public.audio_info.port_id[0] = dc_container_id->portId[0]; - stream->public.audio_info.port_id[1] = dc_container_id->portId[1]; + stream->audio_info.port_id[0] = dc_container_id->portId[0]; + stream->audio_info.port_id[1] = dc_container_id->portId[1]; } else { /* TODO - WindowDM has implemented, other DMs need Unhardcode port_id */ - stream->public.audio_info.port_id[0] = 0x5558859e; - stream->public.audio_info.port_id[1] = 0xd989449; + stream->audio_info.port_id[0] = 0x5558859e; + stream->audio_info.port_id[1] = 0xd989449; } /* EDID CAP translation for HDMI 2.0 */ - stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; stream->status.link = stream->sink->link; return true; } -static void destruct(struct core_stream *stream) +static void destruct(struct dc_stream *stream) { dc_sink_release(stream->sink); - if (stream->public.out_transfer_func != NULL) { + if (stream->out_transfer_func != NULL) { dc_transfer_func_release( - stream->public.out_transfer_func); - stream->public.out_transfer_func = NULL; + stream->out_transfer_func); + stream->out_transfer_func = NULL; } } -void dc_stream_retain(const struct dc_stream *dc_stream) +void dc_stream_retain(struct dc_stream *dc_stream) { struct stream *stream = DC_STREAM_TO_STREAM(dc_stream); @@ -113,17 +113,16 @@ void dc_stream_retain(const struct dc_stream *dc_stream) stream->ref_count++; } -void dc_stream_release(const struct dc_stream *public) +void dc_stream_release(struct dc_stream *public) { struct stream *stream = DC_STREAM_TO_STREAM(public); - struct core_stream *protected = DC_STREAM_TO_CORE(public); if (public != NULL) { ASSERT(stream->ref_count > 0); stream->ref_count--; if (stream->ref_count == 0) { - destruct(protected); + destruct(public); dm_free(stream); } } @@ -147,7 +146,7 @@ struct dc_stream *dc_create_stream_for_sink( stream->ref_count++; - return &stream->protected.public; + return &stream->protected; construct_fail: dm_free(stream); @@ -157,10 +156,9 @@ alloc_fail: } struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream) + struct dc_stream *stream) { uint8_t i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); for (i = 0; i < dc->current_context->stream_count; i++) { @@ -176,15 +174,14 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *dc_stream, + const struct dc_stream *stream, const struct dc_cursor_attributes *attributes) { int i; - struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - if (NULL == dc_stream) { + if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); return false; } @@ -193,7 +190,6 @@ bool dc_stream_set_cursor_attributes( return false; } - stream = DC_STREAM_TO_CORE(dc_stream); core_dc = DC_TO_CORE(stream->ctx->dc); res_ctx = &core_dc->current_context->res_ctx; @@ -213,15 +209,14 @@ bool dc_stream_set_cursor_attributes( } bool dc_stream_set_cursor_position( - const struct dc_stream *dc_stream, + struct dc_stream *stream, const struct dc_cursor_position *position) { int i; - struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - if (NULL == dc_stream) { + if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); return false; } @@ -231,7 +226,6 @@ bool dc_stream_set_cursor_position( return false; } - stream = DC_STREAM_TO_CORE(dc_stream); core_dc = DC_TO_CORE(stream->ctx->dc); res_ctx = &core_dc->current_context->res_ctx; @@ -240,7 +234,7 @@ bool dc_stream_set_cursor_position( struct input_pixel_processor *ipp = pipe_ctx->ipp; struct dc_cursor_position pos_cpy = *position; struct dc_cursor_mi_param param = { - .pixel_clk_khz = dc_stream->timing.pix_clk_khz, + .pixel_clk_khz = stream->timing.pix_clk_khz, .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz, .viewport_x_start = pipe_ctx->scl_data.viewport.x, .viewport_width = pipe_ctx->scl_data.viewport.width, @@ -264,10 +258,9 @@ bool dc_stream_set_cursor_position( return true; } -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) { uint8_t i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -284,7 +277,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) return 0; } -bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, +bool dc_stream_get_scanoutpos(const struct dc_stream *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -292,7 +285,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, { uint8_t i; bool ret = false; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -322,37 +314,35 @@ void dc_stream_log( struct dal_logger *dm_logger, enum dc_log_type log_type) { - const struct core_stream *core_stream = - DC_STREAM_TO_CORE(stream); dm_logger_write(dm_logger, log_type, "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", - core_stream, - core_stream->public.src.x, - core_stream->public.src.y, - core_stream->public.src.width, - core_stream->public.src.height, - core_stream->public.dst.x, - core_stream->public.dst.y, - core_stream->public.dst.width, - core_stream->public.dst.height, - core_stream->public.output_color_space); + stream, + stream->src.x, + stream->src.y, + stream->src.width, + stream->src.height, + stream->dst.x, + stream->dst.y, + stream->dst.width, + stream->dst.height, + stream->output_color_space); dm_logger_write(dm_logger, log_type, "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", - core_stream->public.timing.pix_clk_khz, - core_stream->public.timing.h_total, - core_stream->public.timing.v_total, - core_stream->public.timing.pixel_encoding, - core_stream->public.timing.display_color_depth); + stream->timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pixel_encoding, + stream->timing.display_color_depth); dm_logger_write(dm_logger, log_type, "\tsink name: %s, serial: %d\n", - core_stream->sink->edid_caps.display_name, - core_stream->sink->edid_caps.serial_number); + stream->sink->edid_caps.display_name, + stream->sink->edid_caps.serial_number); dm_logger_write(dm_logger, log_type, "\tlink: %d\n", - core_stream->sink->link->link_index); + stream->sink->link->link_index); } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f87f6c12494c..b20f7bfcdc1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -32,6 +32,7 @@ #include "gpio_types.h" #include "link_service_types.h" #include "grph_object_ctrl_defs.h" +#include #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -106,12 +107,12 @@ struct dc_cap_funcs { struct dc_stream_funcs { bool (*adjust_vmin_vmax)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, int vmin, int vmax); bool (*get_crtc_position)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos); @@ -120,14 +121,14 @@ struct dc_stream_funcs { const struct dc_stream *stream); bool (*program_csc_matrix)(struct dc *dc, - const struct dc_stream *stream); + struct dc_stream *stream); void (*set_static_screen_events)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, const struct dc_static_screen_events *events); - void (*set_dither_option)(const struct dc_stream *stream, + void (*set_dither_option)(struct dc_stream *stream, enum dc_dither_option option); }; @@ -428,7 +429,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_surface **dc_surfaces, uint8_t surface_count, - const struct dc_stream *stream); + struct dc_stream *stream); bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -468,6 +469,18 @@ enum surface_update_type { /******************************************************************************* * Stream Interfaces ******************************************************************************/ + +struct dc_stream_status { + int primary_otg_inst; + int surface_count; + struct dc_surface *surfaces[MAX_SURFACE_NUM]; + + /* + * link this stream passes through + */ + struct dc_link *link; +}; + struct dc_stream { struct dc_sink *sink; struct dc_crtc_timing timing; @@ -495,6 +508,21 @@ struct dc_stream { /* TODO: ABM info (DMCU) */ /* TODO: PSR info */ /* TODO: CEA VIC */ + + /* from core_stream struct */ + struct dc_context *ctx; + + /* used by DCP and FMT */ + struct bit_depth_reduction_params bit_depth_params; + struct clamping_and_pixel_encoding_params clamping; + + int phy_pix_clk; + enum signal_type signal; + + struct dc_stream_status status; + + /* from stream struct */ + int ref_count; }; struct dc_stream_update { @@ -521,7 +549,7 @@ struct dc_stream_update { void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct dc_stream_update *stream_update); /* @@ -554,12 +582,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, * Structure to store surface/stream associations for validation */ struct dc_validation_set { - const struct dc_stream *stream; + struct dc_stream *stream; struct dc_surface *surfaces[MAX_SURFACES]; uint8_t surface_count; }; -bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream); +bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); /* * This function takes a set of resources and checks that they are cofunctional. @@ -587,7 +615,7 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_stream *stream); + struct dc_stream *stream); void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, @@ -616,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_commit_streams( struct dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count); /* * Enable stereo when commit_streams is not required, @@ -625,7 +653,7 @@ bool dc_commit_streams( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count); /** @@ -633,22 +661,11 @@ bool dc_enable_stereo( */ struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); -void dc_stream_retain(const struct dc_stream *dc_stream); -void dc_stream_release(const struct dc_stream *dc_stream); - -struct dc_stream_status { - int primary_otg_inst; - int surface_count; - struct dc_surface *surfaces[MAX_SURFACE_NUM]; - - /* - * link this stream passes through - */ - struct dc_link *link; -}; +void dc_stream_retain(struct dc_stream *dc_stream); +void dc_stream_release(struct dc_stream *dc_stream); struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream); + struct dc_stream *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( struct dc *dc, @@ -915,7 +932,7 @@ bool dc_stream_set_cursor_attributes( const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( - const struct dc_stream *stream, + struct dc_stream *stream, const struct dc_cursor_position *position); /* Newer interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index aff0a440d4d3..24d0c48258ee 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream) + const struct dc_stream *stream) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; @@ -1021,22 +1021,22 @@ bool dce110_link_encoder_validate_output_with_stream( enc110, stream->sink->link->connector_signal, stream->signal, - &stream->public.timing); + &stream->timing); break; case SIGNAL_TYPE_HDMI_TYPE_A: is_valid = dce110_link_encoder_validate_hdmi_output( enc110, - &stream->public.timing, + &stream->timing, stream->phy_pix_clk); break; case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: is_valid = dce110_link_encoder_validate_dp_output( - enc110, &stream->public.timing); + enc110, &stream->timing); break; case SIGNAL_TYPE_EDP: is_valid = - (stream->public.timing. + (stream->timing. pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; break; case SIGNAL_TYPE_VIRTUAL: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index ded6c61304e6..a47b075f4869 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -199,7 +199,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream); + const struct dc_stream *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 3d25a90e49b4..cf98f2471023 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -734,8 +734,8 @@ enum dc_status dce100_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -765,13 +765,13 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 119365960cd0..15f6eeef343d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,21 +623,21 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream) + const struct dc_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; opp->funcs->opp_power_on_regamma_lut(opp, true); opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; - if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + if (stream->out_transfer_func && + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &opp->regamma_params)) { + stream->out_transfer_func, &opp->regamma_params)) { opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { @@ -702,7 +702,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) enum dc_lane_count lane_count = pipe_ctx->stream->sink->link->cur_link_settings.lane_count; - struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct dc_link *link = pipe_ctx->stream->sink->link; /* 1. update AVI info frame (HDMI, DP) @@ -745,7 +745,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { @@ -797,7 +797,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, /* only 3 items below are used by unblank */ params.pixel_clk_khz = - pipe_ctx->stream->public.timing.pix_clk_khz; + pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); } @@ -833,7 +833,7 @@ static void build_audio_output( const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { - const struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; audio_output->engine_id = pipe_ctx->stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -841,33 +841,33 @@ static void build_audio_output( /* audio_crtc_info */ audio_output->crtc_info.h_total = - stream->public.timing.h_total; + stream->timing.h_total; /* * Audio packets are sent during actual CRTC blank physical signal, we * need to specify actual active signal portion */ audio_output->crtc_info.h_active = - stream->public.timing.h_addressable - + stream->public.timing.h_border_left - + stream->public.timing.h_border_right; + stream->timing.h_addressable + + stream->timing.h_border_left + + stream->timing.h_border_right; audio_output->crtc_info.v_active = - stream->public.timing.v_addressable - + stream->public.timing.v_border_top - + stream->public.timing.v_border_bottom; + stream->timing.v_addressable + + stream->timing.v_border_top + + stream->timing.v_border_bottom; audio_output->crtc_info.pixel_repetition = 1; audio_output->crtc_info.interlaced = - stream->public.timing.flags.INTERLACE; + stream->timing.flags.INTERLACE; audio_output->crtc_info.refresh_rate = - (stream->public.timing.pix_clk_khz*1000)/ - (stream->public.timing.h_total*stream->public.timing.v_total); + (stream->timing.pix_clk_khz*1000)/ + (stream->timing.h_total*stream->timing.v_total); audio_output->crtc_info.color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; audio_output->crtc_info.requested_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk; @@ -878,7 +878,7 @@ static void build_audio_output( /*for HDMI, audio ACR is with deep color ratio factor*/ if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && audio_output->crtc_info.requested_pixel_clock == - stream->public.timing.pix_clk_khz) { + stream->timing.pix_clk_khz) { if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { audio_output->crtc_info.requested_pixel_clock = audio_output->crtc_info.requested_pixel_clock/2; @@ -959,7 +959,7 @@ static void program_scaler(const struct core_dc *dc, get_surface_visual_confirm_color(pipe_ctx, &color); else color_space_to_black_color(dc, - pipe_ctx->stream->public.output_color_space, + pipe_ctx->stream->output_color_space, &color); pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( @@ -981,7 +981,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -990,7 +990,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( /* program blank color */ color_space_to_black_color(dc, - stream->public.output_color_space, &black_color); + stream->output_color_space, &black_color); pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, &black_color); @@ -1011,7 +1011,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->program_timing( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, true); pipe_ctx->tg->funcs->set_static_screen_control( @@ -1037,7 +1037,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; @@ -1047,7 +1047,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->opp->funcs->opp_set_dyn_expansion( pipe_ctx->opp, COLOR_SPACE_YCBCR601, - stream->public.timing.display_color_depth, + stream->timing.display_color_depth, pipe_ctx->stream->signal); /* FPGA does not program backend */ @@ -1074,7 +1074,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->stream_enc->funcs->setup_stereo_sync( pipe_ctx->stream_enc, pipe_ctx->tg->inst, - stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); + stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ @@ -1086,20 +1086,20 @@ static enum dc_status apply_single_controller_ctx_to_hw( if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, - stream->public.output_color_space); + &stream->timing, + stream->output_color_space); if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, + &stream->timing, stream->phy_pix_clk, pipe_ctx->audio != NULL); if (dc_is_dvi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, + &stream->timing, (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? true : false); @@ -1129,9 +1129,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( #endif pipe_ctx->mi->funcs->allocate_mem_input( pipe_ctx->mi, - stream->public.timing.h_total, - stream->public.timing.v_total, - stream->public.timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, context->stream_count); pipe_ctx->stream->sink->link->psr_enabled = false; @@ -1228,7 +1228,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, - const struct core_stream *stream) + const struct dc_stream *stream) { uint32_t total_dest_line_time_ns; uint32_t pstate_blackout_duration_ns; @@ -1236,8 +1236,8 @@ static uint32_t compute_pstate_blackout_duration( pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; total_dest_line_time_ns = 1000000UL * - stream->public.timing.h_total / - stream->public.timing.pix_clk_khz + + stream->timing.h_total / + stream->timing.pix_clk_khz + pstate_blackout_duration_ns; return total_dest_line_time_ns; @@ -1805,19 +1805,19 @@ enum dc_status dce110_apply_ctx_to_hw( pipe_ctx->stream_enc->funcs->dp_audio_setup( pipe_ctx->stream_enc, pipe_ctx->audio->inst, - &pipe_ctx->stream->public.audio_info); + &pipe_ctx->stream->audio_info); else pipe_ctx->stream_enc->funcs->hdmi_audio_setup( pipe_ctx->stream_enc, pipe_ctx->audio->inst, - &pipe_ctx->stream->public.audio_info, + &pipe_ctx->stream->audio_info, &audio_output.crtc_info); pipe_ctx->audio->funcs->az_configure( pipe_ctx->audio, pipe_ctx->stream->signal, &audio_output.crtc_info, - &pipe_ctx->stream->public.audio_info); + &pipe_ctx->stream->audio_info); } status = apply_single_controller_ctx_to_hw( @@ -1862,13 +1862,13 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) default_adjust.out_color_space = COLOR_SPACE_SRGB; else default_adjust.out_color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; /* display color depth */ default_adjust.color_depth = - pipe_ctx->stream->public.timing.display_color_depth; + pipe_ctx->stream->timing.display_color_depth; /* Lb color depth */ default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; @@ -1932,35 +1932,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -1987,48 +1987,48 @@ static void set_plane_config( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; for (i = 0; i < 12; i++) tbl_entry.regval[i] = - pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx->opp->funcs->opp_set_csc_adjustment (pipe_ctx->opp, &tbl_entry); } - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -2260,7 +2260,7 @@ void dce110_fill_display_configs( for (j = 0; j < context->stream_count; j++) { int k; - const struct core_stream *stream = context->streams[j]; + const struct dc_stream *stream = context->streams[j]; struct dm_pp_single_disp_config *cfg = &pp_display_cfg->disp_configs[num_cfgs]; const struct pipe_ctx *pipe_ctx = NULL; @@ -2276,8 +2276,8 @@ void dce110_fill_display_configs( num_cfgs++; cfg->signal = pipe_ctx->stream->signal; cfg->pipe_idx = pipe_ctx->pipe_idx; - cfg->src_height = stream->public.src.height; - cfg->src_width = stream->public.src.width; + cfg->src_height = stream->src.height; + cfg->src_width = stream->src.width; cfg->ddi_channel_mapping = stream->sink->link->ddi_channel_mapping.raw; cfg->transmitter = @@ -2290,10 +2290,10 @@ void dce110_fill_display_configs( stream->sink->link->cur_link_settings.link_spread; cfg->sym_clock = stream->phy_pix_clk; /* Round v_refresh*/ - cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; - cfg->v_refresh /= stream->public.timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) - / stream->public.timing.v_total; + cfg->v_refresh = stream->timing.pix_clk_khz * 1000; + cfg->v_refresh /= stream->timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) + / stream->timing.v_total; } pp_display_cfg->display_count = num_cfgs; @@ -2305,7 +2305,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) uint32_t min_vertical_blank_time = -1; for (j = 0; j < context->stream_count; j++) { - const struct dc_stream *stream = &context->streams[j]->public; + struct dc_stream *stream = context->streams[j]; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; @@ -2388,7 +2388,7 @@ static void pplib_apply_display_requirements( /* TODO: is this still applicable?*/ if (pp_display_cfg->display_count == 1) { const struct dc_crtc_timing *timing = - &context->streams[0]->public.timing; + &context->streams[0]->timing; pp_display_cfg->crtc_index = pp_display_cfg->disp_configs[0].pipe_idx; @@ -2441,48 +2441,48 @@ static void dce110_program_front_end_for_pipe( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; for (i = 0; i < 12; i++) tbl_entry.regval[i] = - pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx->opp->funcs->opp_set_csc_adjustment (pipe_ctx->opp, &tbl_entry); } - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index c773351e93af..cc25c4b6c06f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -718,13 +718,13 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; /*TODO: is this halved for YCbCr 420? in that case we might want to move * the pixel clock normalization for hdmi up to here instead of doing it * in pll_adjust_pix_clk */ - pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; @@ -733,15 +733,15 @@ static void get_pixel_clock_parameters( LINK_RATE_REF_FREQ_IN_KHZ; pixel_clk_params->flags.ENABLE_SS = 0; pixel_clk_params->color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; pixel_clk_params->flags.DISPLAY_BLANKED = 1; - pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding == + pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420); - pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { pixel_clk_params->color_depth = COLOR_DEPTH_888; } - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; } } @@ -755,7 +755,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) &pipe_ctx->pll_settings); resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; return DC_OK; } @@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -837,9 +837,9 @@ bool dce110_validate_bandwidth( dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: %dx%d@%d Bandwidth validation failed!\n", __func__, - context->streams[0]->public.timing.h_addressable, - context->streams[0]->public.timing.v_addressable, - context->streams[0]->public.timing.pix_clk_khz); + context->streams[0]->timing.h_addressable, + context->streams[0]->timing.v_addressable, + context->streams[0]->timing.pix_clk_khz); if (memcmp(&dc->current_context->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { @@ -942,8 +942,8 @@ enum dc_status dce110_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -973,13 +973,13 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); @@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; @@ -1041,18 +1041,18 @@ static struct pipe_ctx *dce110_acquire_underlay( */ pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, - &stream->public.timing, + &stream->timing, false); pipe_ctx->tg->funcs->enable_advanced_request( pipe_ctx->tg, true, - &stream->public.timing); + &stream->timing); pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, - stream->public.timing.h_total, - stream->public.timing.v_total, - stream->public.timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, context->stream_count); color_space_to_black_color(dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 19cd99923b24..9589208ea0c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -698,7 +698,7 @@ static void destruct(struct dce110_resource_pool *pool) static struct clock_source *find_matching_pll( struct resource_context *res_ctx, const struct resource_pool *pool, - const struct core_stream *const stream) + const struct dc_stream *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: @@ -729,7 +729,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -843,7 +843,7 @@ enum dc_status resource_map_phy_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -916,8 +916,8 @@ enum dc_status dce112_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -947,13 +947,13 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index c6c0bbac5335..cb2c69fb05a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 0123006e5360..2fde43c91ad0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -676,7 +676,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -750,8 +750,8 @@ enum dc_status dce80_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -780,13 +780,13 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e738387d8ba3..1531b52e61c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -684,12 +684,12 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_color_space color_space; struct tg_color black_color = {0}; - bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? + bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? false:true; - bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY; /* by upper caller loop, pipe0 is parent pipe and be called first. @@ -722,7 +722,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->program_timing( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, true); pipe_ctx->opp->funcs->opp_set_stereo_polarity( @@ -742,7 +742,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( &stream->clamping); #endif /* program otg blank color */ - color_space = stream->public.output_color_space; + color_space = stream->output_color_space; color_space_to_black_color(dc, color_space, &black_color); pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, @@ -1053,16 +1053,16 @@ static bool patch_address_for_sbs_tb_stereo( bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && - (pipe_ctx->stream->public.timing.timing_3d_format == + (pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || - pipe_ctx->stream->public.timing.timing_3d_format == + pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { *addr = surface->address.grph_stereo.left_addr; surface->address.grph_stereo.left_addr = surface->address.grph_stereo.right_addr; return true; } else { - if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE && + if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; surface->address.grph_stereo.right_addr = @@ -1456,7 +1456,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream) + const struct dc_stream *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -1465,14 +1465,14 @@ static bool dcn10_set_output_transfer_func( xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; - if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + if (stream->out_transfer_func && + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); } else if (dcn10_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &xfm->regamma_params)) { + stream->out_transfer_func, &xfm->regamma_params)) { xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { @@ -1756,35 +1756,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -1798,14 +1798,14 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, int i; struct out_csc_color_matrix tbl_entry; - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { enum dc_color_space color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; //uint16_t matrix[12]; for (i = 0; i < 12; i++) - tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; @@ -1967,7 +1967,7 @@ static void update_dchubp_dpp( * pre-multiplied alpha. */ mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace( - pipe_ctx->stream->public.output_color_space) + pipe_ctx->stream->output_color_space) && per_pixel_alpha; pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); @@ -1975,7 +1975,7 @@ static void update_dchubp_dpp( dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color); } else { color_space_to_black_color( - dc, pipe_ctx->stream->public.output_color_space, + dc, pipe_ctx->stream->output_color_space, &black_color); } pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color); @@ -1991,7 +1991,7 @@ static void update_dchubp_dpp( program_gamut_remap(pipe_ctx); /*TODO add adjustments parameters*/ - ocsc.out_color_space = pipe_ctx->stream->public.output_color_space; + ocsc.out_color_space = pipe_ctx->stream->output_color_space; pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc); mi->funcs->mem_input_program_surface_config( @@ -2346,11 +2346,11 @@ static void set_plane_config( } static void dcn10_config_stereo_parameters( - struct core_stream *stream, struct crtc_stereo_flags *flags) + struct dc_stream *stream, struct crtc_stereo_flags *flags) { - enum view_3d_format view_format = stream->public.view_format; + enum view_3d_format view_format = stream->view_format; enum dc_timing_3d_format timing_3d_format =\ - stream->public.timing.timing_3d_format; + stream->timing.timing_3d_format; bool non_stereo_timing = false; if (timing_3d_format == TIMING_3D_FORMAT_NONE || @@ -2374,7 +2374,7 @@ static void dcn10_config_stereo_parameters( flags->DISABLE_STEREO_DP_SYNC = 1; } flags->RIGHT_EYE_POLARITY =\ - stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + stream->timing.flags.RIGHT_EYE_3D_POLARITY; if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) flags->FRAME_PACKED = 1; } @@ -2385,18 +2385,18 @@ static void dcn10_config_stereo_parameters( static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) { struct crtc_stereo_flags flags = { 0 }; - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; dcn10_config_stereo_parameters(stream, &flags); pipe_ctx->opp->funcs->opp_set_stereo_polarity( pipe_ctx->opp, flags.PROGRAM_STEREO == 1 ? true:false, - stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); + stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); pipe_ctx->tg->funcs->program_stereo( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, &flags); return; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index b901ef9689a6..33beb0bc3ddf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -787,8 +787,8 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct core_stream *stream = pipe_ctx->stream; - pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + const struct dc_stream *stream = pipe_ctx->stream; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; @@ -797,23 +797,23 @@ static void get_pixel_clock_parameters( LINK_RATE_REF_FREQ_IN_KHZ; pixel_clk_params->flags.ENABLE_SS = 0; pixel_clk_params->color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; pixel_clk_params->flags.DISPLAY_BLANKED = 1; - pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) pixel_clk_params->color_depth = COLOR_DEPTH_888; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) pixel_clk_params->requested_pix_clk /= 2; } -static void build_clamping_params(struct core_stream *stream) +static void build_clamping_params(struct dc_stream *stream) { stream->clamping.clamping_level = CLAMPING_FULL_RANGE; - stream->clamping.c_depth = stream->public.timing.display_color_depth; - stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding; + stream->clamping.c_depth = stream->timing.display_color_depth; + stream->clamping.pixel_encoding = stream->timing.pixel_encoding; } static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) @@ -826,7 +826,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) &pipe_ctx->pix_clk_params, &pipe_ctx->pll_settings); - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); @@ -844,7 +844,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -852,7 +852,7 @@ static enum dc_status build_mapped_resource( resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); stream->clamping.pixel_encoding = - stream->public.timing.pixel_encoding; + stream->timing.pixel_encoding; resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); @@ -896,8 +896,8 @@ enum dc_status dcn10_validate_with_context( return result; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -929,13 +929,13 @@ enum dc_status dcn10_validate_with_context( enum dc_status dcn10_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); @@ -960,7 +960,7 @@ enum dc_status dcn10_validate_guaranteed( static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 5a47d4c94df6..2ae5a607fb5a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,41 +36,18 @@ #include "mpc.h" #endif -struct core_stream; - #define MAX_CLOCK_SOURCES 7 void enable_surface_flip_reporting(struct dc_surface *dc_surface, uint32_t controller_id); -/********* core_stream ************/ #include "grph_object_id.h" #include "link_encoder.h" #include "stream_encoder.h" #include "clock_source.h" #include "audio.h" #include "hw_sequencer_types.h" -#include "opp.h" - -#define DC_STREAM_TO_CORE(dc_stream) container_of( \ - dc_stream, struct core_stream, public) - -struct core_stream { - struct dc_stream public; - - /* field internal to DC */ - struct dc_context *ctx; - struct dc_sink *sink; - /* used by DCP and FMT */ - struct bit_depth_reduction_params bit_depth_params; - struct clamping_and_pixel_encoding_params clamping; - - int phy_pix_clk; - enum signal_type signal; - - struct dc_stream_status status; -}; /************ link *****************/ struct link_init_data { @@ -85,7 +62,7 @@ struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( - const struct core_stream *stream, + const struct dc_stream *stream, struct dc_link *link, const struct dc_crtc_timing *timing); @@ -117,7 +94,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - const struct dc_stream *stream, + struct dc_stream *stream, struct validate_context *context); bool (*validate_bandwidth)( @@ -127,7 +104,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream); + struct dc_stream *stream); }; struct audio_support{ @@ -178,7 +155,7 @@ struct resource_pool { struct pipe_ctx { struct dc_surface *surface; - struct core_stream *stream; + struct dc_stream *stream; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -264,7 +241,7 @@ union bw_context { }; struct validate_context { - struct core_stream *streams[MAX_PIPES]; + struct dc_stream *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index d9af028a39df..5b4185053e9c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,7 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ struct dc_link; -struct core_stream; +struct dc_stream; struct dc_link_settings; bool dp_hbr_verify_link_cap( @@ -50,7 +50,7 @@ bool dp_validate_mode_timing( const struct dc_crtc_timing *timing); void decide_link_settings( - struct core_stream *stream, + struct dc_stream *stream, struct dc_link_settings *link_setting); bool perform_link_training_with_retries( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 0ee738774f9f..28fb02fb677e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -17,7 +17,6 @@ struct encoder_set_dp_phy_pattern_param; struct link_mst_stream_allocation_table; struct dc_link_settings; struct link_training_settings; -struct core_stream; struct pipe_ctx; struct encoder_init_data { @@ -94,7 +93,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, const struct core_stream *stream); + struct link_encoder *enc, const struct dc_stream *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index a3eec078dead..b2f7ba2115c9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -92,7 +92,7 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream); + const struct dc_stream *stream); void (*power_down)(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ed94df16a2d3..571bfae62a3c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,8 +103,8 @@ void resource_reference_clock_source( struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( - const struct core_stream *stream1, - const struct core_stream *stream2); + struct dc_stream *stream1, + struct dc_stream *stream2); struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, @@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - const struct core_stream *stream); + struct dc_stream *stream); bool resource_attach_surfaces_to_context( struct dc_surface *const *surfaces, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context, const struct resource_pool *pool); @@ -130,10 +130,10 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - const struct validate_context *old_context, const struct core_stream *stream); + struct validate_context *old_context, struct dc_stream *stream); bool is_stream_unchanged( - const struct core_stream *old_stream, const struct core_stream *stream); + struct dc_stream *old_stream, struct dc_stream *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], @@ -164,7 +164,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); -void resource_build_bit_depth_reduction_params(const struct core_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index d312874d95b5..dd024c99fb7e 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream) { return true; } + const struct dc_stream *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index a989d5de9f3c..358f8a855a59 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -111,7 +111,7 @@ struct freesync_state { }; struct freesync_entity { - const struct dc_stream *stream; + struct dc_stream *stream; struct mod_freesync_caps *caps; struct freesync_state state; struct mod_freesync_user_enable user_enable; @@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) * on the core_freesync->map and returns the corresponding index */ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { unsigned int index = 0; @@ -244,9 +244,8 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, } bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, struct mod_freesync_caps *caps) + struct dc_stream *stream, struct mod_freesync_caps *caps) { - struct core_stream *core_stream = NULL; struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; @@ -258,7 +257,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_stream = DC_STREAM_TO_CORE(stream); core_dc = DC_TO_CORE(core_freesync->dc); flag.save_per_edid = true; @@ -315,7 +313,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, if (caps->supported && nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz && nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz) - core_stream->public.ignore_msa_timing_param = 1; + stream->ignore_msa_timing_param = 1; core_freesync->num_entities++; return true; @@ -324,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { int i = 0; struct core_freesync *core_freesync = NULL; @@ -346,14 +344,12 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, } static void update_stream_freesync_context(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { unsigned int index; struct freesync_context *ctx; - struct core_stream *core_stream; - core_stream = DC_STREAM_TO_CORE(stream); - ctx = &core_stream->public.freesync_ctx; + ctx = &stream->freesync_ctx; index = map_index_from_stream(core_freesync, stream); @@ -372,19 +368,17 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync, } static void update_stream(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - unsigned int index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].caps->supported) { - core_stream->public.ignore_msa_timing_param = 1; + stream->ignore_msa_timing_param = 1; update_stream_freesync_context(core_freesync, stream); } } static void calc_freesync_range(struct core_freesync *core_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct freesync_state *state, unsigned int min_refresh_in_uhz, unsigned int max_refresh_in_uhz) @@ -458,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) / 2000; } -static void calc_v_total_from_duration(const struct dc_stream *stream, +static void calc_v_total_from_duration(struct dc_stream *stream, unsigned int duration_in_ns, int *v_total_nominal) { *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( @@ -467,7 +461,7 @@ static void calc_v_total_from_duration(const struct dc_stream *stream, } static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int index, int *v_total) { unsigned int frame_duration = 0; @@ -563,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state) * Sets freesync mode on a stream depending on current freesync state. */ static bool set_freesync_on_streams(struct core_freesync *core_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; unsigned int stream_idx, map_index = 0; @@ -735,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { unsigned int index, v_total, inserted_frame_v_total = 0; unsigned int min_frame_duration_in_ns, vmax, vmin = 0; @@ -845,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } void mod_freesync_update_state(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params) { bool freesync_program_required = false; @@ -935,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_params *freesync_params) { unsigned int index = 0; @@ -971,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, } bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { unsigned int stream_index, map_index; @@ -1023,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_user_enable *user_enable) { unsigned int index = 0; @@ -1041,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, bool *is_ramp_active) { unsigned int index = 0; @@ -1060,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, } bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *streams, + struct dc_stream *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps) @@ -1113,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *min_refresh, unsigned int *max_refresh) { @@ -1135,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *vmin, unsigned int *vmax) { @@ -1157,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, } bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *nom_v_pos, unsigned int *v_pos) { @@ -1185,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { unsigned int stream_index, map_index; struct freesync_state *state; @@ -1310,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync, } static void apply_below_the_range(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index, + struct dc_stream *stream, unsigned int map_index, unsigned int last_render_time_in_us) { unsigned int inserted_frame_duration_in_us = 0; @@ -1409,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, } static void apply_fixed_refresh(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index) + struct dc_stream *stream, unsigned int map_index) { unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1440,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, } void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 53c428b97902..2b9d45100bdd 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -101,67 +101,67 @@ struct mod_freesync_params { * Add stream to be tracked by module */ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, struct mod_freesync_caps *caps); + struct dc_stream *stream, struct mod_freesync_caps *caps); /* * Remove stream to be tracked by module */ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream); + struct dc_stream *stream); /* * Update the freesync state flags for each display and program * freesync accordingly */ void mod_freesync_update_state(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params); bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_params *freesync_params); bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, bool *is_ramp_active); bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *streams, + struct dc_stream *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *min_refresh, unsigned int *max_refresh); bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *vmin, unsigned int *vmax); bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *nom_v_pos, unsigned int *v_pos); void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams); + struct dc_stream **streams, int num_streams); void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams); + struct dc_stream **streams, int num_streams); void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int curr_time_stamp); #endif -- cgit v1.2.3-59-g8ed1b From 2f3bfb2794e1aed018e344469f9c371f36f12867 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Wed, 26 Jul 2017 14:42:38 -0400 Subject: drm/amd/display: safeguard compressor api Only call compressor api if it's available. Signed-off-by: Roman Li Reviewed-by: Bhawanpreet Lakha Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 15f6eeef343d..d45773087644 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1185,7 +1185,8 @@ static void power_down_all_hw_blocks(struct core_dc *dc) power_down_clock_sources(dc); #ifdef ENABLE_FBC - dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); + if (dc->fbc_compressor) + dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); #endif } @@ -1658,7 +1659,8 @@ enum dc_status dce110_apply_ctx_to_hw( set_safe_displaymarks(&context->res_ctx, dc->res_pool); #ifdef ENABLE_FBC - dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); + if (dc->fbc_compressor) + dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); #endif /*TODO: when pplib works*/ apply_min_clocks(dc, context, &clocks_state, true); @@ -2246,7 +2248,8 @@ static void init_hw(struct core_dc *dc) abm->funcs->abm_init(abm); } #ifdef ENABLE_FBC - dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); + if (dc->fbc_compressor) + dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); #endif } -- cgit v1.2.3-59-g8ed1b From 54e8695ef14acc04e9aa99957249f520cf52e826 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 26 Jul 2017 16:54:39 -0400 Subject: drm/amd/display: collapse dce11 reset_hw_ctx_wrap into 1 function Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 47 +++++++++------------- 1 file changed, 20 insertions(+), 27 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d45773087644..6afe572cfb06 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1345,28 +1345,6 @@ static void switch_dp_clock_sources( * Public functions ******************************************************************************/ -static void reset_single_pipe_hw_ctx( - const struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - core_link_disable_stream(pipe_ctx); - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); - if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { - dm_error("DC: failed to blank crtc!\n"); - BREAK_TO_DEBUGGER(); - } - pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); - pipe_ctx->mi->funcs->free_mem_input( - pipe_ctx->mi, context->stream_count); - resource_unreference_clock_source(&context->res_ctx, dc->res_pool, - &pipe_ctx->clock_source); - - dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx->pipe_idx); - - pipe_ctx->stream = NULL; -} - static void set_drr(struct pipe_ctx **pipe_ctx, int num_pipes, int vmin, int vmax) { @@ -1580,7 +1558,7 @@ static enum dc_status apply_ctx_to_hw_fpga( return DC_OK; } -static void reset_hw_ctx_wrap( +static void dce110_reset_hw_ctx_wrap( struct core_dc *dc, struct validate_context *context) { @@ -1603,9 +1581,24 @@ static void reset_hw_ctx_wrap( continue; if (!pipe_ctx->stream || - pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - reset_single_pipe_hw_ctx( - dc, pipe_ctx_old, dc->current_context); + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + core_link_disable_stream(pipe_ctx_old); + pipe_ctx_old->tg->funcs->set_blank(pipe_ctx_old->tg, true); + if (!hwss_wait_for_blank_complete(pipe_ctx_old->tg)) { + dm_error("DC: failed to blank crtc!\n"); + BREAK_TO_DEBUGGER(); + } + pipe_ctx_old->tg->funcs->disable_crtc(pipe_ctx_old->tg); + pipe_ctx_old->mi->funcs->free_mem_input( + pipe_ctx_old->mi, dc->current_context->stream_count); + resource_unreference_clock_source( + &dc->current_context->res_ctx, dc->res_pool, + &pipe_ctx_old->clock_source); + + dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); + + pipe_ctx_old->stream = NULL; + } } } @@ -2619,7 +2612,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .set_drr = set_drr, .get_position = get_position, .set_static_screen_control = set_static_screen_control, - .reset_hw_ctx_wrap = reset_hw_ctx_wrap, + .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, .setup_stereo = NULL, .set_avmute = dce110_set_avmute, -- cgit v1.2.3-59-g8ed1b From 1515a47b44c8667987d070fdc494691f91b44b46 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 26 Jul 2017 19:31:53 -0400 Subject: drm/amd/display: Rename firmware_info to dc_firmware_info This is to avoid conflicts with amdgpu's firmware_info once we merge amdgpu_dm_types with amdgpu_dm. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 14 +++++++------- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 2 +- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 2 +- .../gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 +- 11 files changed, 21 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 47a467688073..2c683d468bb8 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -622,17 +622,17 @@ static enum bp_result bios_parser_get_device_tag( static enum bp_result get_firmware_info_v1_4( struct bios_parser *bp, - struct firmware_info *info); + struct dc_firmware_info *info); static enum bp_result get_firmware_info_v2_1( struct bios_parser *bp, - struct firmware_info *info); + struct dc_firmware_info *info); static enum bp_result get_firmware_info_v2_2( struct bios_parser *bp, - struct firmware_info *info); + struct dc_firmware_info *info); static enum bp_result bios_parser_get_firmware_info( struct dc_bios *dcb, - struct firmware_info *info) + struct dc_firmware_info *info) { struct bios_parser *bp = BP_FROM_DCB(dcb); enum bp_result result = BP_RESULT_BADBIOSTABLE; @@ -676,7 +676,7 @@ static enum bp_result bios_parser_get_firmware_info( static enum bp_result get_firmware_info_v1_4( struct bios_parser *bp, - struct firmware_info *info) + struct dc_firmware_info *info) { ATOM_FIRMWARE_INFO_V1_4 *firmware_info = GET_IMAGE(ATOM_FIRMWARE_INFO_V1_4, @@ -726,7 +726,7 @@ static enum bp_result get_ss_info_v3_1( static enum bp_result get_firmware_info_v2_1( struct bios_parser *bp, - struct firmware_info *info) + struct dc_firmware_info *info) { ATOM_FIRMWARE_INFO_V2_1 *firmwareInfo = GET_IMAGE(ATOM_FIRMWARE_INFO_V2_1, DATA_TABLES(FirmwareInfo)); @@ -810,7 +810,7 @@ static enum bp_result get_firmware_info_v2_1( static enum bp_result get_firmware_info_v2_2( struct bios_parser *bp, - struct firmware_info *info) + struct dc_firmware_info *info) { ATOM_FIRMWARE_INFO_V2_2 *firmware_info; struct spread_spectrum_info internal_ss; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 3a69f9c5d20a..86fce5ae5856 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -81,7 +81,7 @@ static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, static enum bp_result bios_parser_get_firmware_info( struct dc_bios *dcb, - struct firmware_info *info); + struct dc_firmware_info *info); static enum bp_result bios_parser_get_encoder_cap_info( struct dc_bios *dcb, @@ -90,7 +90,7 @@ static enum bp_result bios_parser_get_encoder_cap_info( static enum bp_result get_firmware_info_v3_1( struct bios_parser *bp, - struct firmware_info *info); + struct dc_firmware_info *info); static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, struct atom_display_object_path_v2 *object); @@ -1583,7 +1583,7 @@ static void bios_parser_set_scratch_critical_state( static enum bp_result bios_parser_get_firmware_info( struct dc_bios *dcb, - struct firmware_info *info) + struct dc_firmware_info *info) { struct bios_parser *bp = BP_FROM_DCB(dcb); enum bp_result result = BP_RESULT_BADBIOSTABLE; @@ -1615,7 +1615,7 @@ static enum bp_result bios_parser_get_firmware_info( static enum bp_result get_firmware_info_v3_1( struct bios_parser *bp, - struct firmware_info *info) + struct dc_firmware_info *info) { struct atom_firmware_info_v3_1 *firmware_info; struct atom_display_controller_info_v4_1 *dce_info = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4068d53137f5..d381e380e974 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -126,7 +126,7 @@ struct resource_pool *dc_create_resource_pool( break; } if (res_pool != NULL) { - struct firmware_info fw_info = { { 0 } }; + struct dc_firmware_info fw_info = { { 0 } }; if (dc->ctx->dc_bios->funcs->get_firmware_info( dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 6e1291d5f51d..273d80a4ebce 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -84,7 +84,7 @@ struct dc_vbios_funcs { struct connector_device_tag_info *info); enum bp_result (*get_firmware_info)( struct dc_bios *bios, - struct firmware_info *info); + struct dc_firmware_info *info); enum bp_result (*get_spread_spectrum_info)( struct dc_bios *bios, enum as_signal_type signal, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 2205491c83e9..dd7e1dd62636 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1103,7 +1103,7 @@ static bool calc_pll_max_vco_construct( struct calc_pll_clock_source_init_data *init_data) { uint32_t i; - struct firmware_info fw_info = { { 0 } }; + struct dc_firmware_info fw_info = { { 0 } }; if (calc_pll_cs == NULL || init_data == NULL || init_data->bp == NULL) @@ -1185,7 +1185,7 @@ bool dce110_clk_src_construct( const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_mask *cs_mask) { - struct firmware_info fw_info = { { 0 } }; + struct dc_firmware_info fw_info = { { 0 } }; struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; struct calc_pll_clock_source_init_data calc_pll_cs_init_data; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 37d074f595fb..a73228b97da5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -424,7 +424,7 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce) struct dc_debug *debug = &clk_dce->base.ctx->dc->debug; struct dc_bios *bp = clk_dce->base.ctx->dc_bios; struct integrated_info info = { { { 0 } } }; - struct firmware_info fw_info = { { 0 } }; + struct dc_firmware_info fw_info = { { 0 } }; int i; if (bp->integrated_info) diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index cf98f2471023..9ac246f05110 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -819,7 +819,7 @@ static bool construct( { unsigned int i; struct dc_context *ctx = dc->ctx; - struct firmware_info info; + struct dc_firmware_info info; struct dc_bios *bp; struct dm_pp_static_clock_info static_clk_info = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index cc25c4b6c06f..5c1790b61290 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1190,7 +1190,7 @@ static bool construct( { unsigned int i; struct dc_context *ctx = dc->ctx; - struct firmware_info info; + struct dc_firmware_info info; struct dc_bios *bp; struct dm_pp_static_clock_info static_clk_info = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 2fde43c91ad0..92f01ed97621 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -833,7 +833,7 @@ static bool construct( { unsigned int i; struct dc_context *ctx = dc->ctx; - struct firmware_info info; + struct dc_firmware_info info; struct dc_bios *bp; struct dm_pp_static_clock_info static_clk_info = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index 10061cc4ba31..da08cc1c6dc3 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -320,7 +320,7 @@ void dal_i2caux_destroy( uint32_t dal_i2caux_get_reference_clock( struct dc_bios *bios) { - struct firmware_info info = { { 0 } }; + struct dc_firmware_info info = { { 0 } }; if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK) return 0; diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 9c0bf6521dd9..6cdbf84f34e6 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -154,7 +154,7 @@ struct embedded_panel_info { bool realtek_eDPToLVDS; }; -struct firmware_info { +struct dc_firmware_info { struct pll_info { uint32_t crystal_frequency; /* in KHz */ uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */ -- cgit v1.2.3-59-g8ed1b From bdf9a1a0e16c9e60be796341d79da87503a1cf70 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 25 Jul 2017 16:45:18 -0400 Subject: drm/amd/display: move ocsc programming from opp to dpp for dce Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 201 +------------------- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 31 --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 210 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 30 +++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 35 +++- .../drm/amd/display/dc/dce110/dce110_opp_csc_v.c | 45 +++-- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 2 - .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 6 - .../drm/amd/display/dc/dce110/dce110_transform_v.c | 2 + .../drm/amd/display/dc/dce110/dce110_transform_v.h | 7 + drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 7 +- 11 files changed, 306 insertions(+), 270 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index f716a9e8784e..7abf252369fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -55,31 +55,9 @@ enum { OUTPUT_CSC_MATRIX_SIZE = 12 }; -static const struct out_csc_color_matrix global_color_matrix[] = { -{ COLOR_SPACE_SRGB, - { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, -{ COLOR_SPACE_SRGB_LIMITED, - { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, -{ COLOR_SPACE_YCBCR601, - { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, - 0xF6B9, 0xE00, 0x1000} }, -{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, - 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, -/* TODO: correct values below */ -{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, - 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, -{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, - 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } -}; -enum csc_color_mode { - /* 00 - BITS2:0 Bypass */ - CSC_COLOR_MODE_GRAPHICS_BYPASS, - /* 01 - hard coded coefficient TV RGB */ - CSC_COLOR_MODE_GRAPHICS_PREDEFINED, - /* 04 - programmable OUTPUT CSC coefficient */ - CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, -}; + + @@ -781,181 +759,8 @@ void dce110_opp_program_fmt( return; } -static void program_color_matrix( - struct dce110_opp *opp110, - const struct out_csc_color_matrix *tbl_entry, - enum grph_color_adjust_option options) -{ - { - REG_SET_2(OUTPUT_CSC_C11_C12, 0, - OUTPUT_CSC_C11, tbl_entry->regval[0], - OUTPUT_CSC_C12, tbl_entry->regval[1]); - } - { - REG_SET_2(OUTPUT_CSC_C13_C14, 0, - OUTPUT_CSC_C11, tbl_entry->regval[2], - OUTPUT_CSC_C12, tbl_entry->regval[3]); - } - { - REG_SET_2(OUTPUT_CSC_C21_C22, 0, - OUTPUT_CSC_C11, tbl_entry->regval[4], - OUTPUT_CSC_C12, tbl_entry->regval[5]); - } - { - REG_SET_2(OUTPUT_CSC_C23_C24, 0, - OUTPUT_CSC_C11, tbl_entry->regval[6], - OUTPUT_CSC_C12, tbl_entry->regval[7]); - } - { - REG_SET_2(OUTPUT_CSC_C31_C32, 0, - OUTPUT_CSC_C11, tbl_entry->regval[8], - OUTPUT_CSC_C12, tbl_entry->regval[9]); - } - { - REG_SET_2(OUTPUT_CSC_C33_C34, 0, - OUTPUT_CSC_C11, tbl_entry->regval[10], - OUTPUT_CSC_C12, tbl_entry->regval[11]); - } -} -static bool configure_graphics_mode( - struct dce110_opp *opp110, - enum csc_color_mode config, - enum graphics_csc_adjust_type csc_adjust_type, - enum dc_color_space color_space) -{ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 0); - if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { - if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 4); - } else { - - switch (color_space) { - case COLOR_SPACE_SRGB: - /* by pass */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 0); - break; - case COLOR_SPACE_SRGB_LIMITED: - /* TV RGB */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 1); - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR601_LIMITED: - /* YCbCr601 */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 2); - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YCBCR709_LIMITED: - /* YCbCr709 */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 3); - break; - default: - return false; - } - } - } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { - switch (color_space) { - case COLOR_SPACE_SRGB: - /* by pass */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 0); - break; - break; - case COLOR_SPACE_SRGB_LIMITED: - /* TV RGB */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 1); - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR601_LIMITED: - /* YCbCr601 */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 2); - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YCBCR709_LIMITED: - /* YCbCr709 */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 3); - break; - default: - return false; - } - - } else - /* by pass */ - REG_SET(OUTPUT_CSC_CONTROL, 0, - OUTPUT_CSC_GRPH_MODE, 0); - - return true; -} - -void dce110_opp_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - enum csc_color_mode config = - CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - - program_color_matrix( - opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); - - /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ - configure_graphics_mode(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW, - tbl_entry->color_space); -} - -void dce110_opp_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - enum csc_color_mode config = - CSC_COLOR_MODE_GRAPHICS_PREDEFINED; - - if (default_adjust->force_hw_default == false) { - const struct out_csc_color_matrix *elm; - /* currently parameter not in use */ - enum grph_color_adjust_option option = - GRPH_COLOR_MATRIX_HW_DEFAULT; - uint32_t i; - /* - * HW default false we program locally defined matrix - * HW default true we use predefined hw matrix and we - * do not need to program matrix - * OEM wants the HW default via runtime parameter. - */ - option = GRPH_COLOR_MATRIX_SW; - - for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { - elm = &global_color_matrix[i]; - if (elm->color_space != default_adjust->out_color_space) - continue; - /* program the matrix with default values from this - * file */ - program_color_matrix(opp110, elm, option); - config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - break; - } - } - - /* configure the what we programmed : - * 1. Default values from this file - * 2. Use hardware default from ROM_A and we do not need to program - * matrix */ - - configure_graphics_mode(opp110, config, - default_adjust->csc_adjust_type, - default_adjust->out_color_space); -} /*****************************************/ @@ -964,8 +769,6 @@ void dce110_opp_set_csc_default( static const struct opp_funcs funcs = { .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, - .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, - .opp_set_csc_default = dce110_opp_set_csc_default, .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, .opp_set_regamma_mode = dce110_opp_set_regamma_mode, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index e5045d21a05c..ca09f52f49e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -57,13 +57,6 @@ enum dce110_opp_reg_type { SRI(REGAMMA_LUT_INDEX, DCP, id), \ SRI(REGAMMA_LUT_DATA, DCP, id), \ SRI(REGAMMA_CONTROL, DCP, id), \ - SRI(OUTPUT_CSC_C11_C12, DCP, id), \ - SRI(OUTPUT_CSC_C13_C14, DCP, id), \ - SRI(OUTPUT_CSC_C21_C22, DCP, id), \ - SRI(OUTPUT_CSC_C23_C24, DCP, id), \ - SRI(OUTPUT_CSC_C31_C32, DCP, id), \ - SRI(OUTPUT_CSC_C33_C34, DCP, id), \ - SRI(OUTPUT_CSC_CONTROL, DCP, id), \ SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ SRI(FMT_CONTROL, FMT, id), \ @@ -129,9 +122,6 @@ enum dce110_opp_reg_type { OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ - OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ - OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ - OPP_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ @@ -222,9 +212,6 @@ enum dce110_opp_reg_type { OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ - OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ - OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ - OPP_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ @@ -288,9 +275,6 @@ enum dce110_opp_reg_type { type REGAMMA_LUT_MEM_PWR_STATE; \ type REGAMMA_LUT_WRITE_EN_MASK; \ type GRPH_REGAMMA_MODE; \ - type OUTPUT_CSC_C11; \ - type OUTPUT_CSC_C12; \ - type OUTPUT_CSC_GRPH_MODE; \ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_TRUNCATE_EN; \ @@ -362,13 +346,6 @@ struct dce_opp_registers { uint32_t DCFE_MEM_PWR_STATUS; uint32_t REGAMMA_LUT_DATA; uint32_t REGAMMA_CONTROL; - uint32_t OUTPUT_CSC_C11_C12; - uint32_t OUTPUT_CSC_C13_C14; - uint32_t OUTPUT_CSC_C21_C22; - uint32_t OUTPUT_CSC_C23_C24; - uint32_t OUTPUT_CSC_C31_C32; - uint32_t OUTPUT_CSC_C33_C34; - uint32_t OUTPUT_CSC_CONTROL; uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; @@ -417,14 +394,6 @@ bool dce110_opp_program_regamma_pwl( void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, enum opp_regamma mode); -void dce110_opp_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry); - -void dce110_opp_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust); - /* FORMATTER RELATED */ void dce110_opp_program_bit_depth_reduction( struct output_pixel_processor *opp, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index c861fd7b5767..fb64dca427c1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -80,6 +80,37 @@ enum dcp_spatial_dither_depth { DCP_SPATIAL_DITHER_DEPTH_24BPP }; +enum csc_color_mode { + /* 00 - BITS2:0 Bypass */ + CSC_COLOR_MODE_GRAPHICS_BYPASS, + /* 01 - hard coded coefficient TV RGB */ + CSC_COLOR_MODE_GRAPHICS_PREDEFINED, + /* 04 - programmable OUTPUT CSC coefficient */ + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, +}; + +enum grph_color_adjust_option { + GRPH_COLOR_MATRIX_HW_DEFAULT = 1, + GRPH_COLOR_MATRIX_SW +}; + +static const struct out_csc_color_matrix global_color_matrix[] = { +{ COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, +{ COLOR_SPACE_SRGB_LIMITED, + { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, +{ COLOR_SPACE_YCBCR601, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, + 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, + 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, +/* TODO: correct values below */ +{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, +{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} } +}; + static bool setup_scaling_configuration( struct dce_transform *xfm_dce, const struct scaler_data *data) @@ -970,6 +1001,183 @@ static void dce_transform_reset(struct transform *xfm) xfm_dce->filter_v = NULL; } +static void program_color_matrix( + struct dce_transform *xfm_dce, + const struct out_csc_color_matrix *tbl_entry, + enum grph_color_adjust_option options) +{ + { + REG_SET_2(OUTPUT_CSC_C11_C12, 0, + OUTPUT_CSC_C11, tbl_entry->regval[0], + OUTPUT_CSC_C12, tbl_entry->regval[1]); + } + { + REG_SET_2(OUTPUT_CSC_C13_C14, 0, + OUTPUT_CSC_C11, tbl_entry->regval[2], + OUTPUT_CSC_C12, tbl_entry->regval[3]); + } + { + REG_SET_2(OUTPUT_CSC_C21_C22, 0, + OUTPUT_CSC_C11, tbl_entry->regval[4], + OUTPUT_CSC_C12, tbl_entry->regval[5]); + } + { + REG_SET_2(OUTPUT_CSC_C23_C24, 0, + OUTPUT_CSC_C11, tbl_entry->regval[6], + OUTPUT_CSC_C12, tbl_entry->regval[7]); + } + { + REG_SET_2(OUTPUT_CSC_C31_C32, 0, + OUTPUT_CSC_C11, tbl_entry->regval[8], + OUTPUT_CSC_C12, tbl_entry->regval[9]); + } + { + REG_SET_2(OUTPUT_CSC_C33_C34, 0, + OUTPUT_CSC_C11, tbl_entry->regval[10], + OUTPUT_CSC_C12, tbl_entry->regval[11]); + } +} + +static bool configure_graphics_mode( + struct dce_transform *xfm_dce, + enum csc_color_mode config, + enum graphics_csc_adjust_type csc_adjust_type, + enum dc_color_space color_space) +{ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + + if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { + if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 4); + } else { + + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + break; + case COLOR_SPACE_SRGB_LIMITED: + /* TV RGB */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 1); + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 2); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 3); + break; + default: + return false; + } + } + } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { + switch (color_space) { + case COLOR_SPACE_SRGB: + /* by pass */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + break; + break; + case COLOR_SPACE_SRGB_LIMITED: + /* TV RGB */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 1); + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: + /* YCbCr601 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 2); + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: + /* YCbCr709 */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 3); + break; + default: + return false; + } + + } else + /* by pass */ + REG_SET(OUTPUT_CSC_CONTROL, 0, + OUTPUT_CSC_GRPH_MODE, 0); + + return true; +} + +void dce110_opp_set_csc_adjustment( + struct transform *xfm, + const struct out_csc_color_matrix *tbl_entry) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + + program_color_matrix( + xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); + + /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ + configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW, + tbl_entry->color_space); +} + +void dce110_opp_set_csc_default( + struct transform *xfm, + const struct default_adjustment *default_adjust) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + enum csc_color_mode config = + CSC_COLOR_MODE_GRAPHICS_PREDEFINED; + + if (default_adjust->force_hw_default == false) { + const struct out_csc_color_matrix *elm; + /* currently parameter not in use */ + enum grph_color_adjust_option option = + GRPH_COLOR_MATRIX_HW_DEFAULT; + uint32_t i; + /* + * HW default false we program locally defined matrix + * HW default true we use predefined hw matrix and we + * do not need to program matrix + * OEM wants the HW default via runtime parameter. + */ + option = GRPH_COLOR_MATRIX_SW; + + for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { + elm = &global_color_matrix[i]; + if (elm->color_space != default_adjust->out_color_space) + continue; + /* program the matrix with default values from this + * file */ + program_color_matrix(xfm_dce, elm, option); + config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + break; + } + } + + /* configure the what we programmed : + * 1. Default values from this file + * 2. Use hardware default from ROM_A and we do not need to program + * matrix */ + + configure_graphics_mode(xfm_dce, config, + default_adjust->csc_adjust_type, + default_adjust->out_color_space); +} + + static const struct transform_funcs dce_transform_funcs = { .transform_reset = dce_transform_reset, @@ -977,6 +1185,8 @@ static const struct transform_funcs dce_transform_funcs = { dce_transform_set_scaler, .transform_set_gamut_remap = dce_transform_set_gamut_remap, + .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, + .opp_set_csc_default = dce110_opp_set_csc_default, .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth, .transform_get_optimal_number_of_taps = diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index ca6c621151b2..8632d8f4dac0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -44,6 +44,13 @@ SRI(GAMUT_REMAP_C23_C24, DCP, id), \ SRI(GAMUT_REMAP_C31_C32, DCP, id), \ SRI(GAMUT_REMAP_C33_C34, DCP, id), \ + SRI(OUTPUT_CSC_C11_C12, DCP, id), \ + SRI(OUTPUT_CSC_C13_C14, DCP, id), \ + SRI(OUTPUT_CSC_C21_C22, DCP, id), \ + SRI(OUTPUT_CSC_C23_C24, DCP, id), \ + SRI(OUTPUT_CSC_C31_C32, DCP, id), \ + SRI(OUTPUT_CSC_C33_C34, DCP, id), \ + SRI(OUTPUT_CSC_CONTROL, DCP, id), \ SRI(DENORM_CONTROL, DCP, id), \ SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \ SRI(OUT_ROUND_CONTROL, DCP, id), \ @@ -114,6 +121,9 @@ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ + XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ + XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ + XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ @@ -183,6 +193,9 @@ XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ + XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ + XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ + XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ @@ -249,6 +262,9 @@ type GAMUT_REMAP_C33; \ type GAMUT_REMAP_C34; \ type GRPH_GAMUT_REMAP_MODE; \ + type OUTPUT_CSC_C11; \ + type OUTPUT_CSC_C12; \ + type OUTPUT_CSC_GRPH_MODE; \ type SCL_MODE; \ type SCL_BYPASS_MODE; \ type SCL_PSCL_EN; \ @@ -302,6 +318,13 @@ struct dce_transform_registers { uint32_t GAMUT_REMAP_C23_C24; uint32_t GAMUT_REMAP_C31_C32; uint32_t GAMUT_REMAP_C33_C34; + uint32_t OUTPUT_CSC_C11_C12; + uint32_t OUTPUT_CSC_C13_C14; + uint32_t OUTPUT_CSC_C21_C22; + uint32_t OUTPUT_CSC_C23_C24; + uint32_t OUTPUT_CSC_C31_C32; + uint32_t OUTPUT_CSC_C33_C34; + uint32_t OUTPUT_CSC_CONTROL; uint32_t DENORM_CONTROL; uint32_t DCP_SPATIAL_DITHER_CNTL; uint32_t OUT_ROUND_CONTROL; @@ -381,5 +404,12 @@ bool dce_transform_get_optimal_number_of_taps( struct scaler_data *scl_data, const struct scaling_taps *in_taps); +void dce110_opp_set_csc_adjustment( + struct transform *xfm, + const struct out_csc_color_matrix *tbl_entry); + +void dce110_opp_set_csc_default( + struct transform *xfm, + const struct default_adjustment *default_adjust); #endif /* _DCE_DCE_TRANSFORM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6afe572cfb06..ad831e586021 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1868,8 +1868,8 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) /* Lb color depth */ default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; - pipe_ctx->opp->funcs->opp_set_csc_default( - pipe_ctx->opp, &default_adjust); + pipe_ctx->xfm->funcs->opp_set_csc_default( + pipe_ctx->xfm, &default_adjust); } @@ -1991,8 +1991,8 @@ static void set_plane_config( tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; - pipe_ctx->opp->funcs->opp_set_csc_adjustment - (pipe_ctx->opp, &tbl_entry); + pipe_ctx->xfm->funcs->opp_set_csc_adjustment + (pipe_ctx->xfm, &tbl_entry); } if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { @@ -2446,8 +2446,8 @@ static void dce110_program_front_end_for_pipe( tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; - pipe_ctx->opp->funcs->opp_set_csc_adjustment - (pipe_ctx->opp, &tbl_entry); + pipe_ctx->xfm->funcs->opp_set_csc_adjustment + (pipe_ctx->xfm, &tbl_entry); } if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { @@ -2587,8 +2587,31 @@ static void dce110_wait_for_mpcc_disconnect( /* do nothing*/ } +static void program_csc_matrix(struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix) +{ + int i; + struct out_csc_color_matrix tbl_entry; + + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment + == true) { + enum dc_color_space color_space = + pipe_ctx->stream->output_color_space; + + //uint16_t matrix[12]; + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; + + tbl_entry.color_space = color_space; + //tbl_entry.regval = matrix; + pipe_ctx->xfm->funcs->opp_set_csc_adjustment(pipe_ctx->xfm, &tbl_entry); + } +} + static const struct hw_sequencer_funcs dce110_funcs = { .program_gamut_remap = program_gamut_remap, + .program_csc_matrix = program_csc_matrix, .init_hw = init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, .apply_ctx_for_surface = dce110_apply_ctx_for_surface, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c index 019effe4c99c..feb397b5c1a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c @@ -24,7 +24,7 @@ */ #include "dm_services.h" -#include "dce/dce_opp.h" +#include "dce110_transform_v.h" #include "basics/conversion.h" /* include DCE11 register header files */ @@ -100,12 +100,17 @@ enum csc_color_mode { CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, }; +enum grph_color_adjust_option { + GRPH_COLOR_MATRIX_HW_DEFAULT = 1, + GRPH_COLOR_MATRIX_SW +}; + static void program_color_matrix_v( - struct dce110_opp *opp110, + struct dce_transform *xfm_dce, const struct out_csc_color_matrix *tbl_entry, enum grph_color_adjust_option options) { - struct dc_context *ctx = opp110->base.ctx; + struct dc_context *ctx = xfm_dce->base.ctx; uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); bool use_set_a = (get_reg_field_value(cntl_value, COL_MAN_OUTPUT_CSC_CONTROL, @@ -351,12 +356,12 @@ static void program_color_matrix_v( } static bool configure_graphics_mode_v( - struct dce110_opp *opp110, + struct dce_transform *xfm_dce, enum csc_color_mode config, enum graphics_csc_adjust_type csc_adjust_type, enum dc_color_space color_space) { - struct dc_context *ctx = opp110->base.ctx; + struct dc_context *ctx = xfm_dce->base.ctx; uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL; uint32_t value = dm_read_reg(ctx, addr); @@ -454,10 +459,10 @@ static bool configure_graphics_mode_v( } /*TODO: color depth is not correct when this is called*/ -static void set_Denormalization(struct output_pixel_processor *opp, +static void set_Denormalization(struct transform *xfm, enum dc_color_depth color_depth) { - uint32_t value = dm_read_reg(opp->ctx, mmDENORM_CLAMP_CONTROL); + uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL); switch (color_depth) { case COLOR_DEPTH_888: @@ -495,7 +500,7 @@ static void set_Denormalization(struct output_pixel_processor *opp, DENORM_CLAMP_CONTROL, DENORM_10BIT_OUT); - dm_write_reg(opp->ctx, mmDENORM_CLAMP_CONTROL, value); + dm_write_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL, value); } struct input_csc_matrix { @@ -524,10 +529,10 @@ static const struct input_csc_matrix input_csc_matrix[] = { }; static void program_input_csc( - struct output_pixel_processor *opp, enum dc_color_space color_space) + struct transform *xfm, enum dc_color_space color_space) { int arr_size = sizeof(input_csc_matrix)/sizeof(struct input_csc_matrix); - struct dc_context *ctx = opp->ctx; + struct dc_context *ctx = xfm->ctx; const uint32_t *regval = NULL; bool use_set_a; uint32_t value; @@ -664,10 +669,10 @@ static void program_input_csc( } void dce110_opp_v_set_csc_default( - struct output_pixel_processor *opp, + struct transform *xfm, const struct default_adjustment *default_adjust) { - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_PREDEFINED; @@ -692,13 +697,13 @@ void dce110_opp_v_set_csc_default( /* program the matrix with default values from this * file */ - program_color_matrix_v(opp110, elm, option); + program_color_matrix_v(xfm_dce, elm, option); config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; break; } } - program_input_csc(opp, default_adjust->in_color_space); + program_input_csc(xfm, default_adjust->in_color_space); /* configure the what we programmed : * 1. Default values from this file @@ -706,26 +711,26 @@ void dce110_opp_v_set_csc_default( * matrix */ - configure_graphics_mode_v(opp110, config, + configure_graphics_mode_v(xfm_dce, config, default_adjust->csc_adjust_type, default_adjust->out_color_space); - set_Denormalization(opp, default_adjust->color_depth); + set_Denormalization(xfm, default_adjust->color_depth); } void dce110_opp_v_set_csc_adjustment( - struct output_pixel_processor *opp, + struct transform *xfm, const struct out_csc_color_matrix *tbl_entry) { - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; program_color_matrix_v( - opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); + xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ - configure_graphics_mode_v(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW, + configure_graphics_mode_v(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW, tbl_entry->color_space); /*TODO: Check if denormalization is needed*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 6f8b414cabbc..24d9032faade 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -39,8 +39,6 @@ static const struct opp_funcs funcs = { .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v, .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v, - .opp_set_csc_default = dce110_opp_v_set_csc_default, - .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment, .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v, .opp_destroy = dce110_opp_destroy, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h index cb26c515d30f..7deaa4f5c659 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -33,13 +33,7 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110, struct dc_context *ctx); /* underlay callbacks */ -void dce110_opp_v_set_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust); -void dce110_opp_v_set_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry); bool dce110_opp_program_regamma_pwl_v( struct output_pixel_processor *opp, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index 8548248d4b19..f655145b3c47 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -681,6 +681,8 @@ static const struct transform_funcs dce110_xfmv_funcs = { .transform_set_scaler = dce110_xfmv_set_scaler, .transform_set_gamut_remap = dce110_xfmv_set_gamut_remap, + .opp_set_csc_default = dce110_opp_v_set_csc_default, + .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment, .transform_set_pixel_storage_depth = dce110_xfmv_set_pixel_storage_depth, .transform_get_optimal_number_of_taps = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h index 267af34db3e5..b7f8fdb392a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h @@ -34,4 +34,11 @@ bool dce110_transform_v_construct( struct dce_transform *xfm110, struct dc_context *ctx); +void dce110_opp_v_set_csc_default( + struct transform *xfm, + const struct default_adjustment *default_adjust); + +void dce110_opp_v_set_csc_adjustment( + struct transform *xfm, + const struct out_csc_color_matrix *tbl_entry); #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 01d6957c07fb..a4f8556d6797 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -217,13 +217,8 @@ enum fmt_stereo_action { FMT_STEREO_ACTION_UPDATE_POLARITY }; -enum grph_color_adjust_option { - GRPH_COLOR_MATRIX_HW_DEFAULT = 1, - GRPH_COLOR_MATRIX_SW -}; - struct opp_grph_csc_adjustment { - enum grph_color_adjust_option color_adjust_option; + //enum grph_color_adjust_option color_adjust_option; enum dc_color_space c_space; enum dc_color_depth color_depth; /* clean up to uint32_t */ enum graphics_csc_adjust_type csc_adjust_type; -- cgit v1.2.3-59-g8ed1b From 690b5e3960810c733f812f8849c3a05415c2f53d Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 27 Jul 2017 20:00:06 -0400 Subject: drm/amd/display: Initial prototype of FBC implementation - Protected by ENABLE_FBC compile flag Signed-off-by: Roman Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++- drivers/gpu/drm/amd/display/dc/dc.h | 3 + drivers/gpu/drm/amd/display/dc/dc_types.h | 3 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 69 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/inc/compressor.h | 1 + 5 files changed, 81 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index df8c5ca6b22a..1c0d21840cba 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -475,7 +475,9 @@ static bool construct(struct core_dc *dc, dc_version = resource_parse_asic_id(init_params->asic_id); dc->ctx->dce_version = dc_version; - +#ifdef ENABLE_FBC + dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; +#endif /* Resource should construct all asic specific resources. * This should be the only place where we need to parse the asic id */ @@ -919,7 +921,7 @@ bool dc_enable_stereo( #ifdef ENABLE_FBC if (fbc_compressor != NULL && fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor, - &pipe->tg->inst)) + NULL)) fbc_compressor->funcs->disable_fbc(fbc_compressor); #endif @@ -2066,3 +2068,4 @@ void dc_log_hw_state(struct dc *dc) if (core_dc->hwss.log_hw_state) core_dc->hwss.log_hw_state(core_dc); } + diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e9c9b91d1286..63fd5b3de738 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -231,6 +231,9 @@ struct dc_init_data { enum dce_environment dce_environment; struct dc_config flags; +#ifdef ENABLE_FBC + uint64_t fbc_gpu_addr; +#endif }; struct dc *dc_create(const struct dc_init_data *init_params); diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 99b893fbcb42..ee9e6bc88c32 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -92,6 +92,9 @@ struct dc_context { bool created_bios; struct gpio_service *gpio_service; struct i2caux *i2caux; +#ifdef ENABLE_FBC + uint64_t fbc_gpu_addr; +#endif }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ad831e586021..b62a7614fd28 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1528,6 +1528,69 @@ static void apply_min_clocks( } } +#ifdef ENABLE_FBC + +/* + * Check if FBC can be enabled + */ +static enum dc_status validate_fbc(struct core_dc *dc, + struct validate_context *context) +{ + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[0]; + + ASSERT(dc->fbc_compressor); + + /* FBC memory should be allocated */ + if (!dc->ctx->fbc_gpu_addr) + return DC_ERROR_UNEXPECTED; + + /* Only supports single display */ + if (context->stream_count != 1) + return DC_ERROR_UNEXPECTED; + + /* Only supports eDP */ + if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) + return DC_ERROR_UNEXPECTED; + + /* PSR should not be enabled */ + if (pipe_ctx->stream->sink->link->psr_enabled) + return DC_ERROR_UNEXPECTED; + + return DC_OK; +} + +/* + * Enable FBC + */ +static enum dc_status enable_fbc(struct core_dc *dc, + struct validate_context *context) +{ + enum dc_status status = validate_fbc(dc, context); + + if (status == DC_OK) { + /* Program GRPH COMPRESSED ADDRESS and PITCH */ + struct compr_addr_and_pitch_params params = {0, 0, 0}; + struct compressor *compr = dc->fbc_compressor; + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[0]; + + params.source_view_width = + pipe_ctx->stream->timing.h_addressable; + params.source_view_height = + pipe_ctx->stream->timing.v_addressable; + + compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; + + compr->funcs->surface_address_and_pitch(compr, ¶ms); + compr->funcs->set_fbc_invalidation_triggers(compr, 1); + + compr->funcs->enable_fbc(compr, ¶ms); + } + return status; +} +#endif + static enum dc_status apply_ctx_to_hw_fpga( struct core_dc *dc, struct validate_context *context) @@ -1836,6 +1899,11 @@ enum dc_status dce110_apply_ctx_to_hw( switch_dp_clock_sources(dc, &context->res_ctx); +#ifdef ENABLE_FBC + if (dc->fbc_compressor) + enable_fbc(dc, context); + +#endif return DC_OK; } @@ -2244,6 +2312,7 @@ static void init_hw(struct core_dc *dc) if (dc->fbc_compressor) dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); #endif + } void dce110_fill_display_configs( diff --git a/drivers/gpu/drm/amd/display/dc/inc/compressor.h b/drivers/gpu/drm/amd/display/dc/inc/compressor.h index 24cca18f3c8f..bcb18f5e1e60 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/compressor.h +++ b/drivers/gpu/drm/amd/display/dc/inc/compressor.h @@ -42,6 +42,7 @@ union fbc_physical_address { uint32_t low_part; int32_t high_part; } addr; + uint64_t quad_part; }; struct compr_addr_and_pitch_params { -- cgit v1.2.3-59-g8ed1b From 7a09f5be98df25a7253e4647e801120b37b90feb Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Fri, 28 Jul 2017 13:08:03 -0400 Subject: drm/amd/display: move regamma from opp to dpp for dce Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 237 -------------------- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 113 +--------- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 240 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 88 ++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 +- .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 88 ++++---- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 3 - .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 11 - .../drm/amd/display/dc/dce110/dce110_transform_v.c | 3 + .../drm/amd/display/dc/dce110/dce110_transform_v.h | 14 ++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 17 -- 11 files changed, 399 insertions(+), 433 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 7abf252369fb..348e4b7047f1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -92,242 +92,8 @@ enum { * ***************************************************************************** */ -static void regamma_config_regions_and_segments( - struct dce110_opp *opp110, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - - { - REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, - REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - } - { - REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); - - } - { - REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, - REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - } - { - REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, - REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); - } - - curve = params->arr_curve_points; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } - - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - - curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } - - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } -} - -static void program_pwl( - struct dce110_opp *opp110, - const struct pwl_params *params) -{ - uint32_t value; - int retval; - - { - uint8_t max_tries = 10; - uint8_t counter = 0; - - /* Power on LUT memory */ - if (REG(DCFE_MEM_PWR_CTRL)) - REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 1); - else - REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - - while (counter < max_tries) { - if (REG(DCFE_MEM_PWR_STATUS)) { - value = REG_READ(DCFE_MEM_PWR_STATUS); - REG_GET(DCFE_MEM_PWR_STATUS, - DCP_REGAMMA_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } else { - value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); - REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } - } - - if (counter == max_tries) { - dm_logger_write(opp110->base.ctx->logger, LOG_WARNING, - "%s: regamma lut was not powered on " - "in a timely manner," - " programming still proceeds\n", - __func__); - } - } - - REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, - REGAMMA_LUT_WRITE_EN_MASK, 7); - - REG_WRITE(REGAMMA_LUT_INDEX, 0); - - /* Program REGAMMA_LUT_DATA */ - { - uint32_t i = 0; - const struct pwl_result_data *rgb = params->rgb_resulted; - - while (i != params->hw_points_num) { - - REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); - - ++rgb; - ++i; - } - } - - /* we are done with DCP LUT memory; re-enable low power mode */ - if (REG(DCFE_MEM_PWR_CTRL)) - REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 0); - else - REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); -} - -bool dce110_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *params) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - /* Setup regions */ - regamma_config_regions_and_segments(opp110, params); - - /* Program PWL */ - program_pwl(opp110, params); - - return true; -} - -void dce110_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - if (REG(DCFE_MEM_PWR_CTRL)) - REG_UPDATE_2(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, power_on, - DCP_LUT_MEM_PWR_DIS, power_on); - else - REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, - DCP_LUT_LIGHT_SLEEP_DIS, power_on); - -} - -void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode) -{ - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); - - REG_SET(REGAMMA_CONTROL, 0, - GRPH_REGAMMA_MODE, mode); -} /** * set_truncation @@ -768,10 +534,7 @@ void dce110_opp_program_fmt( /*****************************************/ static const struct opp_funcs funcs = { - .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, - .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, - .opp_set_regamma_mode = dce110_opp_set_regamma_mode, .opp_destroy = dce110_opp_destroy, .opp_program_fmt = dce110_opp_program_fmt, .opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index ca09f52f49e5..0874c22b8b02 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -41,22 +41,6 @@ enum dce110_opp_reg_type { }; #define OPP_COMMON_REG_LIST_BASE(id) \ - SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ - SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ - SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ - SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ - SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ - SRI(REGAMMA_LUT_INDEX, DCP, id), \ - SRI(REGAMMA_LUT_DATA, DCP, id), \ - SRI(REGAMMA_CONTROL, DCP, id), \ SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ SRI(FMT_CONTROL, FMT, id), \ @@ -70,31 +54,24 @@ enum dce110_opp_reg_type { #define OPP_DCE_80_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) #define OPP_DCE_100_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ - SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) #define OPP_DCE_110_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) #define OPP_DCE_112_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ @@ -102,26 +79,12 @@ enum dce110_opp_reg_type { #define OPP_DCE_120_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(CONTROL, FMT_MEMORY, id) #define OPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ - OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ - OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ - OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ @@ -160,27 +123,18 @@ enum dce110_opp_reg_type { #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ @@ -191,27 +145,9 @@ enum dce110_opp_reg_type { OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ - OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ - OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ - OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ @@ -257,24 +193,6 @@ enum dce110_opp_reg_type { OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) #define OPP_REG_FIELD_LIST(type) \ - type DCP_REGAMMA_MEM_PWR_DIS; \ - type DCP_LUT_MEM_PWR_DIS; \ - type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ - type DCP_LUT_LIGHT_SLEEP_DIS; \ - type REGAMMA_CNTLA_EXP_REGION_START; \ - type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ - type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ - type REGAMMA_CNTLA_EXP_REGION_END; \ - type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ - type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ - type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ - type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ - type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ - type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ - type DCP_REGAMMA_MEM_PWR_STATE; \ - type REGAMMA_LUT_MEM_PWR_STATE; \ - type REGAMMA_LUT_WRITE_EN_MASK; \ - type GRPH_REGAMMA_MODE; \ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_TRUNCATE_EN; \ @@ -327,25 +245,6 @@ struct dce_opp_mask { }; struct dce_opp_registers { - uint32_t DCFE_MEM_PWR_CTRL; - uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; - uint32_t REGAMMA_CNTLA_START_CNTL; - uint32_t REGAMMA_CNTLA_SLOPE_CNTL; - uint32_t REGAMMA_CNTLA_END_CNTL1; - uint32_t REGAMMA_CNTLA_END_CNTL2; - uint32_t REGAMMA_CNTLA_REGION_0_1; - uint32_t REGAMMA_CNTLA_REGION_2_3; - uint32_t REGAMMA_CNTLA_REGION_4_5; - uint32_t REGAMMA_CNTLA_REGION_6_7; - uint32_t REGAMMA_CNTLA_REGION_8_9; - uint32_t REGAMMA_CNTLA_REGION_10_11; - uint32_t REGAMMA_CNTLA_REGION_12_13; - uint32_t REGAMMA_CNTLA_REGION_14_15; - uint32_t REGAMMA_LUT_WRITE_EN_MASK; - uint32_t REGAMMA_LUT_INDEX; - uint32_t DCFE_MEM_PWR_STATUS; - uint32_t REGAMMA_LUT_DATA; - uint32_t REGAMMA_CONTROL; uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; @@ -382,17 +281,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp); -/* REGAMMA RELATED */ -void dce110_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on); - -bool dce110_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *params); -void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode); /* FORMATTER RELATED */ void dce110_opp_program_bit_depth_reduction( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index fb64dca427c1..0e366021cf16 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1177,7 +1177,244 @@ void dce110_opp_set_csc_default( default_adjust->out_color_space); } +static void program_pwl( + struct dce_transform *xfm_dce, + const struct pwl_params *params) +{ + uint32_t value; + int retval; + + { + uint8_t max_tries = 10; + uint8_t counter = 0; + + /* Power on LUT memory */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 1); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); + + while (counter < max_tries) { + if (REG(DCFE_MEM_PWR_STATUS)) { + value = REG_READ(DCFE_MEM_PWR_STATUS); + REG_GET(DCFE_MEM_PWR_STATUS, + DCP_REGAMMA_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } else { + value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); + REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } + } + + if (counter == max_tries) { + dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, + "%s: regamma lut was not powered on " + "in a timely manner," + " programming still proceeds\n", + __func__); + } + } + + REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, + REGAMMA_LUT_WRITE_EN_MASK, 7); + + REG_WRITE(REGAMMA_LUT_INDEX, 0); + + /* Program REGAMMA_LUT_DATA */ + { + uint32_t i = 0; + const struct pwl_result_data *rgb = params->rgb_resulted; + + while (i != params->hw_points_num) { + + REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); + + ++rgb; + ++i; + } + } + + /* we are done with DCP LUT memory; re-enable low power mode */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 0); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); +} + +static void regamma_config_regions_and_segments( + struct dce_transform *xfm_dce, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + + { + REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); + } + { + REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); + + } + { + REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, + REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); + } + { + REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, + REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); + } + + curve = params->arr_curve_points; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + } + + curve += 2; + + { + REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } +} + + + +bool dce110_opp_program_regamma_pwl( + struct transform *xfm, + const struct pwl_params *params) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + /* Setup regions */ + regamma_config_regions_and_segments(xfm_dce, params); + + /* Program PWL */ + program_pwl(xfm_dce, params); + + return true; +} + +void dce110_opp_power_on_regamma_lut( + struct transform *xfm, + bool power_on) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE_2(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, power_on, + DCP_LUT_MEM_PWR_DIS, power_on); + else + REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, + DCP_LUT_LIGHT_SLEEP_DIS, power_on); + +} + +void dce110_opp_set_regamma_mode(struct transform *xfm, + enum opp_regamma mode) +{ + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); + + REG_SET(REGAMMA_CONTROL, 0, + GRPH_REGAMMA_MODE, mode); +} static const struct transform_funcs dce_transform_funcs = { .transform_reset = dce_transform_reset, @@ -1187,6 +1424,9 @@ static const struct transform_funcs dce_transform_funcs = { dce_transform_set_gamut_remap, .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, .opp_set_csc_default = dce110_opp_set_csc_default, + .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, + .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode, .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth, .transform_get_optimal_number_of_taps = diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index 8632d8f4dac0..f9622ff54560 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -51,6 +51,22 @@ SRI(OUTPUT_CSC_C31_C32, DCP, id), \ SRI(OUTPUT_CSC_C33_C34, DCP, id), \ SRI(OUTPUT_CSC_CONTROL, DCP, id), \ + SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ + SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ + SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ + SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ + SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ + SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ + SRI(REGAMMA_LUT_INDEX, DCP, id), \ + SRI(REGAMMA_LUT_DATA, DCP, id), \ + SRI(REGAMMA_CONTROL, DCP, id), \ SRI(DENORM_CONTROL, DCP, id), \ SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \ SRI(OUT_ROUND_CONTROL, DCP, id), \ @@ -124,6 +140,18 @@ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ + XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ @@ -161,6 +189,9 @@ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ + XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ + XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ @@ -196,6 +227,16 @@ XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ @@ -265,6 +306,24 @@ type OUTPUT_CSC_C11; \ type OUTPUT_CSC_C12; \ type OUTPUT_CSC_GRPH_MODE; \ + type DCP_REGAMMA_MEM_PWR_DIS; \ + type DCP_LUT_MEM_PWR_DIS; \ + type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ + type DCP_LUT_LIGHT_SLEEP_DIS; \ + type REGAMMA_CNTLA_EXP_REGION_START; \ + type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ + type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ + type REGAMMA_CNTLA_EXP_REGION_END; \ + type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ + type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ + type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ + type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ + type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ + type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ + type DCP_REGAMMA_MEM_PWR_STATE; \ + type REGAMMA_LUT_MEM_PWR_STATE; \ + type REGAMMA_LUT_WRITE_EN_MASK; \ + type GRPH_REGAMMA_MODE; \ type SCL_MODE; \ type SCL_BYPASS_MODE; \ type SCL_PSCL_EN; \ @@ -325,6 +384,23 @@ struct dce_transform_registers { uint32_t OUTPUT_CSC_C31_C32; uint32_t OUTPUT_CSC_C33_C34; uint32_t OUTPUT_CSC_CONTROL; + uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; + uint32_t REGAMMA_CNTLA_START_CNTL; + uint32_t REGAMMA_CNTLA_SLOPE_CNTL; + uint32_t REGAMMA_CNTLA_END_CNTL1; + uint32_t REGAMMA_CNTLA_END_CNTL2; + uint32_t REGAMMA_CNTLA_REGION_0_1; + uint32_t REGAMMA_CNTLA_REGION_2_3; + uint32_t REGAMMA_CNTLA_REGION_4_5; + uint32_t REGAMMA_CNTLA_REGION_6_7; + uint32_t REGAMMA_CNTLA_REGION_8_9; + uint32_t REGAMMA_CNTLA_REGION_10_11; + uint32_t REGAMMA_CNTLA_REGION_12_13; + uint32_t REGAMMA_CNTLA_REGION_14_15; + uint32_t REGAMMA_LUT_WRITE_EN_MASK; + uint32_t REGAMMA_LUT_INDEX; + uint32_t REGAMMA_LUT_DATA; + uint32_t REGAMMA_CONTROL; uint32_t DENORM_CONTROL; uint32_t DCP_SPATIAL_DITHER_CNTL; uint32_t OUT_ROUND_CONTROL; @@ -412,4 +488,16 @@ void dce110_opp_set_csc_default( struct transform *xfm, const struct default_adjustment *default_adjust); +/* REGAMMA RELATED */ +void dce110_opp_power_on_regamma_lut( + struct transform *xfm, + bool power_on); + +bool dce110_opp_program_regamma_pwl( + struct transform *xfm, + const struct pwl_params *params); + +void dce110_opp_set_regamma_mode(struct transform *xfm, + enum opp_regamma mode); + #endif /* _DCE_DCE_TRANSFORM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index b62a7614fd28..1f18fcf52661 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -625,26 +625,26 @@ static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, const struct dc_stream *stream) { - struct output_pixel_processor *opp = pipe_ctx->opp; + struct transform *xfm = pipe_ctx->xfm; - opp->funcs->opp_power_on_regamma_lut(opp, true); - opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; + xfm->funcs->opp_power_on_regamma_lut(xfm, true); + xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && stream->out_transfer_func->type == TF_TYPE_PREDEFINED && stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); + xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->out_transfer_func, &opp->regamma_params)) { - opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); + stream->out_transfer_func, &xfm->regamma_params)) { + xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); + xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); + xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); } - opp->funcs->opp_power_on_regamma_lut(opp, false); + xfm->funcs->opp_power_on_regamma_lut(xfm, false); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index 876445f14c85..c86105b8cfaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -29,12 +29,12 @@ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" -#include "dce/dce_opp.h" +#include "dce110_transform_v.h" -static void power_on_lut(struct output_pixel_processor *opp, +static void power_on_lut(struct transform *xfm, bool power_on, bool inputgamma, bool regamma) { - uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL); + uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); int i; if (power_on) { @@ -65,10 +65,10 @@ static void power_on_lut(struct output_pixel_processor *opp, COL_MAN_GAMMA_CORR_MEM_PWR_DIS); } - dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value); + dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); for (i = 0; i < 3; i++) { - value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL); + value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); if (get_reg_field_value(value, DCFEV_MEM_PWR_CTRL, COL_MAN_INPUT_GAMMA_MEM_PWR_DIS) && @@ -81,11 +81,11 @@ static void power_on_lut(struct output_pixel_processor *opp, } } -static void set_bypass_input_gamma(struct dce110_opp *opp110) +static void set_bypass_input_gamma(struct dce_transform *xfm_dce) { uint32_t value; - value = dm_read_reg(opp110->base.ctx, + value = dm_read_reg(xfm_dce->base.ctx, mmCOL_MAN_INPUT_GAMMA_CONTROL1); set_reg_field_value( @@ -94,11 +94,11 @@ static void set_bypass_input_gamma(struct dce110_opp *opp110) COL_MAN_INPUT_GAMMA_CONTROL1, INPUT_GAMMA_MODE); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmCOL_MAN_INPUT_GAMMA_CONTROL1, value); } -static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode) +static void configure_regamma_mode(struct dce_transform *xfm_dce, uint32_t mode) { uint32_t value = 0; @@ -108,7 +108,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode) GAMMA_CORR_CONTROL, GAMMA_CORR_MODE); - dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CONTROL, 0); + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); } /* @@ -128,7 +128,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode) ***************************************************************************** */ static void regamma_config_regions_and_segments( - struct dce110_opp *opp110, const struct pwl_params *params) + struct dce_transform *xfm_dce, const struct pwl_params *params) { const struct gamma_curve *curve; uint32_t value = 0; @@ -146,7 +146,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_START_CNTL, GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT); - dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, value); } { @@ -157,7 +157,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_SLOPE_CNTL, GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_SLOPE_CNTL, value); } { @@ -168,7 +168,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_END_CNTL1, GAMMA_CORR_CNTLA_EXP_REGION_END); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_END_CNTL1, value); } { @@ -185,7 +185,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_END_CNTL2, GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_END_CNTL2, value); } @@ -218,7 +218,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS); dm_write_reg( - opp110->base.ctx, + xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_0_1, value); } @@ -250,7 +250,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_2_3, GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_2_3, value); } @@ -282,7 +282,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_4_5, GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_4_5, value); } @@ -314,7 +314,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_6_7, GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_6_7, value); } @@ -346,7 +346,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_8_9, GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_8_9, value); } @@ -378,7 +378,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_10_11, GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_10_11, value); } @@ -410,7 +410,7 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_12_13, GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_12_13, value); } @@ -442,13 +442,13 @@ static void regamma_config_regions_and_segments( GAMMA_CORR_CNTLA_REGION_14_15, GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_REGION_14_15, value); } } -static void program_pwl(struct dce110_opp *opp110, +static void program_pwl(struct dce_transform *xfm_dce, const struct pwl_params *params) { uint32_t value = 0; @@ -459,10 +459,10 @@ static void program_pwl(struct dce110_opp *opp110, GAMMA_CORR_LUT_WRITE_EN_MASK, GAMMA_CORR_LUT_WRITE_EN_MASK); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_LUT_WRITE_EN_MASK, value); - dm_write_reg(opp110->base.ctx, + dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_LUT_INDEX, 0); /* Program REGAMMA_LUT_DATA */ @@ -473,15 +473,15 @@ static void program_pwl(struct dce110_opp *opp110, params->rgb_resulted; while (i != params->hw_points_num) { - dm_write_reg(opp110->base.ctx, addr, rgb->red_reg); - dm_write_reg(opp110->base.ctx, addr, rgb->green_reg); - dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg); + dm_write_reg(xfm_dce->base.ctx, addr, rgb->red_reg); + dm_write_reg(xfm_dce->base.ctx, addr, rgb->green_reg); + dm_write_reg(xfm_dce->base.ctx, addr, rgb->blue_reg); - dm_write_reg(opp110->base.ctx, addr, + dm_write_reg(xfm_dce->base.ctx, addr, rgb->delta_red_reg); - dm_write_reg(opp110->base.ctx, addr, + dm_write_reg(xfm_dce->base.ctx, addr, rgb->delta_green_reg); - dm_write_reg(opp110->base.ctx, addr, + dm_write_reg(xfm_dce->base.ctx, addr, rgb->delta_blue_reg); ++rgb; @@ -491,36 +491,36 @@ static void program_pwl(struct dce110_opp *opp110, } bool dce110_opp_program_regamma_pwl_v( - struct output_pixel_processor *opp, + struct transform *xfm, const struct pwl_params *params) { - struct dce110_opp *opp110 = TO_DCE110_OPP(opp); + struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); /* Setup regions */ - regamma_config_regions_and_segments(opp110, params); + regamma_config_regions_and_segments(xfm_dce, params); - set_bypass_input_gamma(opp110); + set_bypass_input_gamma(xfm_dce); /* Power on gamma LUT memory */ - power_on_lut(opp, true, false, true); + power_on_lut(xfm, true, false, true); /* Program PWL */ - program_pwl(opp110, params); + program_pwl(xfm_dce, params); /* program regamma config */ - configure_regamma_mode(opp110, 1); + configure_regamma_mode(xfm_dce, 1); /* Power return to auto back */ - power_on_lut(opp, false, false, true); + power_on_lut(xfm, false, false, true); return true; } void dce110_opp_power_on_regamma_lut_v( - struct output_pixel_processor *opp, + struct transform *xfm, bool power_on) { - uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL); + uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); set_reg_field_value( value, @@ -546,11 +546,11 @@ void dce110_opp_power_on_regamma_lut_v( DCFEV_MEM_PWR_CTRL, COL_MAN_INPUT_GAMMA_MEM_PWR_DIS); - dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value); + dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); } void dce110_opp_set_regamma_mode_v( - struct output_pixel_processor *opp, + struct transform *xfm, enum opp_regamma mode) { // TODO: need to implement the function diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 24d9032faade..69d6a110dbc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -37,10 +37,7 @@ /*****************************************/ static const struct opp_funcs funcs = { - .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v, - .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v, .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, - .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v, .opp_destroy = dce110_opp_destroy, .opp_program_fmt = dce110_opp_program_fmt, .opp_program_bit_depth_reduction = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h index 7deaa4f5c659..269c1a88d5bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -35,16 +35,5 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110, /* underlay callbacks */ -bool dce110_opp_program_regamma_pwl_v( - struct output_pixel_processor *opp, - const struct pwl_params *params); - -void dce110_opp_power_on_regamma_lut_v( - struct output_pixel_processor *opp, - bool power_on); - -void dce110_opp_set_regamma_mode_v( - struct output_pixel_processor *opp, - enum opp_regamma mode); #endif /* __DC_OPP_DCE110_V_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index f655145b3c47..c84823a40f61 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -683,6 +683,9 @@ static const struct transform_funcs dce110_xfmv_funcs = { dce110_xfmv_set_gamut_remap, .opp_set_csc_default = dce110_opp_v_set_csc_default, .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment, + .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v, + .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v, .transform_set_pixel_storage_depth = dce110_xfmv_set_pixel_storage_depth, .transform_get_optimal_number_of_taps = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h index b7f8fdb392a5..eeed3b9f90f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h @@ -41,4 +41,18 @@ void dce110_opp_v_set_csc_default( void dce110_opp_v_set_csc_adjustment( struct transform *xfm, const struct out_csc_color_matrix *tbl_entry); + + +bool dce110_opp_program_regamma_pwl_v( + struct transform *xfm, + const struct pwl_params *params); + +void dce110_opp_power_on_regamma_lut_v( + struct transform *xfm, + bool power_on); + +void dce110_opp_set_regamma_mode_v( + struct transform *xfm, + enum opp_regamma mode); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index a4f8556d6797..dadd2ad2e5b8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -251,24 +251,7 @@ enum ovl_csc_adjust_item { }; struct opp_funcs { - void (*opp_power_on_regamma_lut)( - struct output_pixel_processor *opp, - bool power_on); - - bool (*opp_program_regamma_pwl)( - struct output_pixel_processor *opp, - const struct pwl_params *params); - - void (*opp_set_regamma_mode)(struct output_pixel_processor *opp, - enum opp_regamma mode); - void (*opp_set_csc_adjustment)( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry); - - void (*opp_set_csc_default)( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust); /* FORMATTER RELATED */ -- cgit v1.2.3-59-g8ed1b From c9614aeb12f80fa7a787e608d75b707175997edd Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:24:04 -0400 Subject: drm/amd/display: Rename dc_surface to dc_plane_state find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_surface/struct dc_plane_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_update/struct dc_surface_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_status/struct dc_surface_status/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_dcc_cap/struct dc_surface_dcc_cap/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 16 ++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 22 +++++++++++----------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 6 +++--- .../drm/amd/display/dc/dce100/dce100_resource.h | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 14 +++++++------- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++++++------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +++--- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 2 +- 22 files changed, 84 insertions(+), 84 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7b597a0a2ab9..af6bed907d10 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1819,7 +1819,7 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, static bool fill_rects_from_plane_state( const struct drm_plane_state *state, - struct dc_surface *surface) + struct dc_plane_state *surface) { surface->src_rect.x = state->src_x >> 16; surface->src_rect.y = state->src_y >> 16; @@ -1894,7 +1894,7 @@ static int get_fb_info( static int fill_plane_attributes_from_fb( struct amdgpu_device *adev, - struct dc_surface *surface, + struct dc_plane_state *surface, const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) { uint64_t tiling_flags; @@ -2048,7 +2048,7 @@ static int fill_plane_attributes_from_fb( static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, - struct dc_surface *dc_surface) + struct dc_plane_state *dc_surface) { int i; struct dc_gamma *gamma; @@ -2072,7 +2072,7 @@ static void fill_gamma_from_crtc_state( static int fill_plane_attributes( struct amdgpu_device *adev, - struct dc_surface *surface, + struct dc_plane_state *surface, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state, bool addrReq) @@ -3059,7 +3059,7 @@ static int dm_plane_helper_prepare_fb( if (dm_plane_state_new->surface && dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_surface *surface = dm_plane_state_new->surface; + struct dc_plane_state *surface = dm_plane_state_new->surface; if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { surface->address.grph.addr.low_part = lower_32_bits(afb->address); @@ -3160,7 +3160,7 @@ int dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->surface) return true; - if (dc_validate_surface(dc, dm_plane_state->surface)) + if (dc_validate_plane(dc, dm_plane_state->surface)) return 0; return -EINVAL; @@ -3926,7 +3926,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; struct dc_stream *dc_stream_attach; - struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -4377,7 +4377,7 @@ static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream *stream, - struct dc_surface *surface) + struct dc_plane_state *surface) { uint32_t i = 0, j = 0; @@ -4699,7 +4699,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, pflip_needed = !state->allow_modeset; if (!pflip_needed) { - struct dc_surface *surface; + struct dc_plane_state *surface; surface = dc_create_surface(dc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index ce0223af7d5f..dcf1f77390a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -189,14 +189,14 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( struct amdgpu_framebuffer; struct amdgpu_display_manager; struct dc_validation_set; -struct dc_surface; +struct dc_plane_state; /* TODO rename to dc_stream_state */ struct dc_stream; struct dm_plane_state { struct drm_plane_state base; - struct dc_surface *surface; + struct dc_plane_state *surface; }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5acf4c697ae8..500788c35d70 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -645,7 +645,7 @@ static bool is_validation_required( return true; for (j = 0; j < set[i].surface_count; j++) { - struct dc_surface temp_surf; + struct dc_plane_state temp_surf; memset(&temp_surf, 0, sizeof(temp_surf)); temp_surf = *context->stream_status[i].surfaces[j]; @@ -684,7 +684,7 @@ static bool validate_surfaces( for (i = 0; i < set_count; i++) for (j = 0; j < set[i].surface_count; j++) - if (!dc_validate_surface(dc, set[i].surfaces[j])) + if (!dc_validate_plane(dc, set[i].surfaces[j])) return false; return true; @@ -978,7 +978,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_surface *surface = + const struct dc_plane_state *surface = context->stream_status[i].surfaces[j]; core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); @@ -1136,7 +1136,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) bool dc_commit_surfaces_to_stream( struct dc *dc, - struct dc_surface **new_surfaces, + struct dc_plane_state **new_surfaces, uint8_t new_surface_count, struct dc_stream *dc_stream) { @@ -1220,7 +1220,7 @@ void dc_release_validate_context(struct validate_context *context) static bool is_surface_in_context( const struct validate_context *context, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { int j; @@ -1470,7 +1470,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - struct dc_surface *new_surfaces[MAX_SURFACES] = {0}; + struct dc_plane_state *new_surfaces[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) new_surfaces[i] = srf_updates[i].surface; @@ -1496,7 +1496,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* save update parameters into surface */ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; if (srf_updates[i].flip_addr) { surface->address = srf_updates[i].flip_addr->address; @@ -1599,7 +1599,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1649,7 +1649,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index bf127a88e533..e8d4b8c3ac2b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -38,7 +38,7 @@ void pre_surface_trace( const struct dc *dc, - const struct dc_surface *const *surfaces, + const struct dc_plane_state *const *surfaces, int surface_count) { int i; @@ -46,7 +46,7 @@ void pre_surface_trace( struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { - const struct dc_surface *surface = surfaces[i]; + const struct dc_plane_state *surface = surfaces[i]; SURFACE_TRACE("Surface %d:\n", i); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 005eac5fae80..fd1d6be79fee 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -430,7 +430,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; @@ -529,7 +529,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; @@ -607,7 +607,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->src.width; @@ -814,7 +814,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -1028,7 +1028,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - struct dc_surface * const *surfaces, + struct dc_plane_state * const *surfaces, int surface_count, struct dc_stream *stream, struct validate_context *context, @@ -1075,7 +1075,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = surfaces[i]; + struct dc_plane_state *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, stream); @@ -1351,7 +1351,7 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct dc_surface *surface = to_pipe_ctx->surface; + struct dc_plane_state *surface = to_pipe_ctx->surface; struct dc_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; @@ -2055,7 +2055,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_surface *surface, + struct dc_plane_state *surface, struct dc_stream *stream) { uint16_t i = 0; @@ -2534,13 +2534,13 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) return res == DC_OK; } -bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface) +bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) { struct core_dc *core_dc = DC_TO_CORE(dc); /* TODO For now validates pixel format only */ - if (core_dc->res_pool->funcs->validate_surface) - return core_dc->res_pool->funcs->validate_surface(surface) == DC_OK; + if (core_dc->res_pool->funcs->validate_plane) + return core_dc->res_pool->funcs->validate_plane(plane_state) == DC_OK; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index eded6b7da97d..941b3671375d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -34,7 +34,7 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct dc_surface *surface) +static bool construct(struct dc_context *ctx, struct dc_plane_state *surface) { surface->ctx = ctx; memset(&surface->hdr_static_ctx, @@ -42,7 +42,7 @@ static bool construct(struct dc_context *ctx, struct dc_surface *surface) return true; } -static void destruct(struct dc_surface *surface) +static void destruct(struct dc_plane_state *surface) { if (surface->gamma_correction != NULL) { dc_gamma_release(&surface->gamma_correction); @@ -57,18 +57,18 @@ static void destruct(struct dc_surface *surface) /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_surface *surface, +void enable_surface_flip_reporting(struct dc_plane_state *surface, uint32_t controller_id) { surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } -struct dc_surface *dc_create_surface(const struct dc *dc) +struct dc_plane_state *dc_create_surface(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_surface *surface = dm_alloc(sizeof(*surface)); + struct dc_plane_state *surface = dm_alloc(sizeof(*surface)); if (NULL == surface) goto alloc_fail; @@ -88,7 +88,7 @@ alloc_fail: } const struct dc_surface_status *dc_surface_get_status( - const struct dc_surface *dc_surface) + const struct dc_plane_state *dc_surface) { const struct dc_surface_status *surface_status; struct core_dc *core_dc; @@ -120,13 +120,13 @@ const struct dc_surface_status *dc_surface_get_status( return surface_status; } -void dc_surface_retain(struct dc_surface *surface) +void dc_surface_retain(struct dc_plane_state *surface) { ASSERT(surface->ref_count > 0); ++surface->ref_count; } -void dc_surface_release(struct dc_surface *surface) +void dc_surface_release(struct dc_plane_state *surface) { ASSERT(surface->ref_count > 0); --surface->ref_count; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d03218d6210a..d1943b9644d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -92,7 +92,7 @@ struct dc_static_screen_events { /* Forward declaration*/ struct dc; -struct dc_surface; +struct dc_plane_state; struct validate_context; struct dc_cap_funcs { @@ -310,7 +310,7 @@ struct dc_surface_status { bool is_right_eye; }; -struct dc_surface { +struct dc_plane_state { struct dc_plane_address address; struct scaling_taps scaling_quality; @@ -367,7 +367,7 @@ struct dc_scaling_info { }; struct dc_surface_update { - struct dc_surface *surface; + struct dc_plane_state *surface; /* isr safe update parameters. null means no updates */ struct dc_flip_addrs *flip_addr; @@ -385,12 +385,12 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_surface *dc_create_surface(const struct dc *dc); +struct dc_plane_state *dc_create_surface(const struct dc *dc); const struct dc_surface_status *dc_surface_get_status( - const struct dc_surface *dc_surface); + const struct dc_plane_state *dc_surface); -void dc_surface_retain(struct dc_surface *dc_surface); -void dc_surface_release(struct dc_surface *dc_surface); +void dc_surface_retain(struct dc_plane_state *dc_surface); +void dc_surface_release(struct dc_plane_state *dc_surface); void dc_gamma_retain(struct dc_gamma *dc_gamma); void dc_gamma_release(struct dc_gamma **dc_gamma); @@ -424,7 +424,7 @@ struct dc_flip_addrs { bool dc_commit_surfaces_to_stream( struct dc *dc, - struct dc_surface **dc_surfaces, + struct dc_plane_state **dc_surfaces, uint8_t surface_count, struct dc_stream *stream); @@ -470,7 +470,7 @@ enum surface_update_type { struct dc_stream_status { int primary_otg_inst; int surface_count; - struct dc_surface *surfaces[MAX_SURFACE_NUM]; + struct dc_plane_state *surfaces[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -582,13 +582,13 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, */ struct dc_validation_set { struct dc_stream *stream; - struct dc_surface *surfaces[MAX_SURFACES]; + struct dc_plane_state *surfaces[MAX_SURFACES]; uint8_t surface_count; }; bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); -bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface); +bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); /* * This function takes a set of resources and checks that they are cofunctional. * diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 4c5e797da5b1..3c0b47373dfb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -528,7 +528,7 @@ enum dc_quantization_range { /* XFM */ -/* used in struct dc_surface */ +/* used in struct dc_plane_state */ struct scaling_taps { uint32_t v_taps; uint32_t h_taps; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ee9e6bc88c32..4fb9584452a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -34,7 +34,7 @@ #include "grph_object_defs.h" /* forward declarations */ -struct dc_surface; +struct dc_plane_state; struct dc_stream; struct dc_link; struct dc_sink; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index c46b3e82cdcc..af59ab93796a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -197,7 +197,7 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct dc_surface *surface) +bool dce_use_lut(const struct dc_plane_state *surface) { switch (surface->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index ade7507e99c7..d5cb98a92c53 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct dc_surface *surface); +bool dce_use_lut(const struct dc_plane_state *surface); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 59f4caf057f7..2cf2fefc3d79 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -804,10 +804,10 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool) *pool = NULL; } -enum dc_status dce100_validate_surface(const struct dc_surface *surface) +enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state) { - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return DC_OK; return DC_FAIL_SURFACE_VALIDATE; @@ -819,7 +819,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { .validate_with_context = dce100_validate_with_context, .validate_guaranteed = dce100_validate_guaranteed, .validate_bandwidth = dce100_validate_bandwidth, - .validate_surface = dce100_validate_surface, + .validate_plane = dce100_validate_plane, }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index 13fc637eb731..edc50caf04d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -16,6 +16,6 @@ struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, struct core_dc *dc); -enum dc_status dce100_validate_surface(const struct dc_surface *surface); +enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); #endif /* DCE100_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1f18fcf52661..84dc8916de96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,7 +215,7 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -2038,7 +2038,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2123,7 +2123,7 @@ static void set_plane_config( static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2138,7 +2138,7 @@ static void update_plane_addr(const struct core_dc *dc, void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2614,7 +2614,7 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 495f38750ae4..c68372fa1292 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -994,7 +994,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b31307b9d3e3..45f5fd63ce14 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -701,7 +701,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 6eeb5e9f656f..bcb66447b558 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -825,7 +825,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_with_context = dce80_validate_with_context, .validate_guaranteed = dce80_validate_guaranteed, .validate_bandwidth = dce80_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fa19c6b92f29..3979cb03cf8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1038,7 +1038,7 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && @@ -1065,7 +1065,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -1080,7 +1080,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_surface *surface) + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -1689,7 +1689,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_surface *dc_surface = pipe_ctx->surface; + struct dc_plane_state *dc_surface = pipe_ctx->surface; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1898,7 +1898,7 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; union plane_size size = surface->plane_size; struct default_adjustment ocsc = {0}; struct mpcc_cfg mpcc_cfg = {0}; @@ -2068,7 +2068,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context) { int i, be_idx; @@ -2468,7 +2468,7 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct timing_generator *tg = pipe_ctx->tg; if (surface->ctx->dc->debug.sanity_checks) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index da52971d3f06..44a87c9427f7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,7 +36,7 @@ #define MAX_CLOCK_SOURCES 7 -void enable_surface_flip_reporting(struct dc_surface *dc_surface, +void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, uint32_t controller_id); #include "grph_object_id.h" @@ -104,7 +104,7 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_stream *stream); - enum dc_status (*validate_surface)(const struct dc_surface *surface); + enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); }; struct audio_support{ @@ -154,7 +154,7 @@ struct resource_pool { }; struct pipe_ctx { - struct dc_surface *surface; + struct dc_plane_state *surface; struct dc_stream *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b2f7ba2115c9..c529ddd2e0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_surface *surface); + const struct dc_plane_state *surface); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ca3f49379bea..bfd7cfc86df0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( struct dc_stream *stream); bool resource_attach_surfaces_to_context( - struct dc_surface *const *surfaces, + struct dc_plane_state *const *surfaces, int surface_count, struct dc_stream *dc_stream, struct validate_context *context, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 0a872472ecba..0e978d921fdf 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger, void pre_surface_trace( const struct dc *dc, - const struct dc_surface *const *surfaces, + const struct dc_plane_state *const *surfaces, int surface_count); void update_surface_trace( -- cgit v1.2.3-59-g8ed1b From 0971c40e180696c3512b9a63ca7ca5161cbfce32 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:33:33 -0400 Subject: drm/amd/display: Rename dc_stream to dc_stream_state find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream/struct dc_stream_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_update/struct dc_stream_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_status/struct dc_stream_status/g' Plus some manual changes Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++++++------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 38 ++++++------ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 +++--- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 68 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 26 ++++----- drivers/gpu/drm/amd/display/dc/dc.h | 58 +++++++++--------- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 ++--- .../drm/amd/display/dc/dce110/dce110_resource.c | 8 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +-- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +-- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 10 ++-- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 11 ++-- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 13 ++--- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 50 ++++++++-------- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 28 ++++----- 29 files changed, 222 insertions(+), 222 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index af6bed907d10..497104a29d89 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -116,7 +116,8 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) if (acrtc_state->stream == NULL) { - DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); + DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", + crtc); return 0; } @@ -137,7 +138,8 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, acrtc->base.state); if (acrtc_state->stream == NULL) { - DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); + DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", + crtc); return 0; } @@ -1441,7 +1443,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, num_streams = dc_get_current_stream_count(adev->dm.dc); for (i = 0; i < num_streams; i++) { - struct dc_stream *stream; + struct dc_stream_state *stream; stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, @@ -1609,8 +1611,8 @@ struct dm_connector_state { container_of((x), struct dm_connector_state, base) static bool modeset_required(struct drm_crtc_state *crtc_state, - struct dc_stream *new_stream, - struct dc_stream *old_stream) + struct dc_stream_state *new_stream, + struct dc_stream_state *old_stream) { if (dc_is_stream_unchanged(new_stream, old_stream)) { crtc_state->mode_changed = false; @@ -2141,7 +2143,7 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id( static void update_stream_scaling_settings( const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, - struct dc_stream *stream) + struct dc_stream_state *stream) { enum amdgpu_rmx_type rmx_type; @@ -2285,7 +2287,7 @@ static enum dc_color_space get_output_color_space( /*****************************************************************************/ static void fill_stream_properties_from_drm_display_mode( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct drm_display_mode *mode_in, const struct drm_connector *connector) { @@ -2426,14 +2428,14 @@ static void decide_crtc_timing_for_drm_display_mode( } } -static struct dc_stream *create_stream_for_sink( +static struct dc_stream_state *create_stream_for_sink( struct amdgpu_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; const struct drm_connector *drm_connector; - struct dc_stream *stream = NULL; + struct dc_stream_state *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -2842,7 +2844,7 @@ int amdgpu_dm_connector_mode_valid( struct dc_sink *dc_sink; struct amdgpu_device *adev = connector->dev->dev_private; /* TODO: Unhardcode stream count */ - struct dc_stream *stream; + struct dc_stream_state *stream; struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || @@ -3119,7 +3121,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ - struct dc_stream *stream; + struct dc_stream_state *stream; if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) @@ -3770,7 +3772,7 @@ static bool is_scaling_state_different( static void remove_stream( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - struct dc_stream *stream) + struct dc_stream_state *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -3925,7 +3927,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, uint32_t i; struct drm_plane *plane; struct drm_plane_state *old_plane_state; - struct dc_stream *dc_stream_attach; + struct dc_stream_state *dc_stream_attach; struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); @@ -4061,7 +4063,7 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc *crtc, *pcrtc; struct drm_crtc_state *old_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - struct dc_stream *new_stream = NULL; + struct dc_stream_state *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -4220,7 +4222,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(acrtc->base.state); update_stream_scaling_settings(&con_new_state->base.crtc->mode, - con_new_state, (struct dc_stream *)new_acrtc_state->stream); + con_new_state, (struct dc_stream_state *)new_acrtc_state->stream); status = dc_stream_get_status(new_acrtc_state->stream); WARN_ON(!status); @@ -4376,7 +4378,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_plane_state *surface) { uint32_t i = 0, j = 0; @@ -4399,8 +4401,8 @@ static uint32_t add_val_sets_surface( static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, uint32_t set_count, - struct dc_stream *old_stream, - struct dc_stream *new_stream, + struct dc_stream_state *old_stream, + struct dc_stream_state *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; @@ -4423,7 +4425,7 @@ static uint32_t update_in_val_sets_stream( static uint32_t remove_from_val_sets( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { int i; @@ -4545,7 +4547,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; - struct dc_stream *new_stream = NULL; + struct dc_stream_state *new_stream = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_conn_state = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index dcf1f77390a8..cca65a37b213 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -201,7 +201,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - struct dc_stream *stream; + struct dc_stream_state *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0a615583de63..4a124537dc9a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -174,7 +174,7 @@ static void get_payload_table( */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable) { @@ -264,7 +264,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( */ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct amdgpu_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; @@ -290,7 +290,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( bool dm_helpers_dp_mst_send_payload_allocation( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, bool enable) { struct amdgpu_connector *aconnector; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 500788c35d70..8b6b7631d776 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -149,12 +149,12 @@ failed_alloc: } static bool stream_adjust_vmin_vmax(struct dc *dc, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, int vmin, int vmax) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream *stream = streams[0]; + struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -175,12 +175,12 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, } static bool stream_get_crtc_position(struct dc *dc, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream *stream = streams[0]; + struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; struct crtc_position position; @@ -200,7 +200,7 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) +static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); int i = 0; @@ -218,7 +218,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) return ret; } -static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) +static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); int i = 0; @@ -241,7 +241,7 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) } static void set_static_screen_events(struct dc *dc, - struct dc_stream **streams, + struct dc_stream_state **streams, int num_streams, const struct dc_static_screen_events *events) { @@ -252,7 +252,7 @@ static void set_static_screen_events(struct dc *dc, int num_pipes_affected = 0; for (i = 0; i < num_streams; i++) { - struct dc_stream *stream = streams[i]; + struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { if (core_dc->current_context->res_ctx.pipe_ctx[j].stream @@ -333,7 +333,7 @@ static void set_test_pattern( cust_pattern_size); } -void set_dither_option(struct dc_stream *stream, +void set_dither_option(struct dc_stream_state *stream, enum dc_dither_option option) { struct bit_depth_reduction_params params; @@ -769,7 +769,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -893,7 +893,7 @@ static bool context_changed( static bool streams_changed( struct core_dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { uint8_t i; @@ -912,7 +912,7 @@ static bool streams_changed( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { bool ret = true; @@ -958,7 +958,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; - struct dc_stream *dc_streams[MAX_STREAMS] = {0}; + struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; for (i = 0; i < context->stream_count; i++) dc_streams[i] = context->streams[i]; @@ -1031,7 +1031,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; dc_stream_log(stream, core_dc->ctx->logger, @@ -1046,7 +1046,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_commit_streams( struct dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1062,7 +1062,7 @@ bool dc_commit_streams( __func__, stream_count); for (i = 0; i < stream_count; i++) { - struct dc_stream *stream = streams[i]; + struct dc_stream_state *stream = streams[i]; struct dc_stream_status *status = dc_stream_get_status(stream); int j; @@ -1138,7 +1138,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_plane_state **new_surfaces, uint8_t new_surface_count, - struct dc_stream *dc_stream) + struct dc_stream_state *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -1395,7 +1395,7 @@ enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream *stream, + struct dc_stream_state *stream, struct dc_stream_update *stream_update) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1723,7 +1723,7 @@ uint8_t dc_get_current_stream_count(const struct dc *dc) return core_dc->current_context->stream_count; } -struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) +struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); if (i < core_dc->current_context->stream_count) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a983a5ee3172..7a2fe2f3e65c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; @@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; struct dc_link *link = stream->sink->link; @@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; @@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) } enum dc_status dc_link_validate_mode_timing( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing) { @@ -1374,7 +1374,7 @@ enum dc_status dc_link_validate_mode_timing( bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream *stream) + uint32_t frame_ramp, const struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct abm *abm = core_dc->res_pool->abm; @@ -1450,7 +1450,7 @@ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) } bool dc_link_setup_psr(struct dc_link *link, - const struct dc_stream *stream, struct psr_config *psr_config, + const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); @@ -1587,7 +1587,7 @@ void core_link_resume(struct dc_link *link) program_hpd_filter(link); } -static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream) +static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) { struct dc_link_settings *link_settings = &stream->sink->link->cur_link_settings; @@ -1696,7 +1696,7 @@ static void update_mst_stream_alloc_table( */ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1778,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 17506345f97a..50724f9a8e2c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1433,7 +1433,7 @@ bool dp_validate_mode_timing( return false; } -void decide_link_settings(struct dc_stream *stream, +void decide_link_settings(struct dc_stream_state *stream, struct dc_link_settings *link_setting) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fd1d6be79fee..ce0415f26600 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -294,8 +294,8 @@ void resource_reference_clock_source( } bool resource_are_streams_timing_synchronizable( - struct dc_stream *stream1, - struct dc_stream *stream2) + struct dc_stream_state *stream1, + struct dc_stream_state *stream2) { if (stream1->timing.h_total != stream2->timing.h_total) return false; @@ -431,7 +431,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; @@ -530,7 +530,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; @@ -608,7 +608,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->src.width; const int in_h = stream->src.height; @@ -920,7 +920,7 @@ struct pipe_ctx *find_idle_secondary_pipe( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; for (i = 0; i < MAX_PIPES; i++) { @@ -940,7 +940,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; struct resource_context *res_ctx = &context->res_ctx; @@ -979,7 +979,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( static void release_free_pipes_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -997,7 +997,7 @@ static void release_free_pipes_for_stream( static int acquire_first_split_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -1030,7 +1030,7 @@ static int acquire_first_split_pipe( bool resource_attach_surfaces_to_context( struct dc_plane_state * const *surfaces, int surface_count, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context, const struct resource_pool *pool) { @@ -1118,8 +1118,8 @@ bool resource_attach_surfaces_to_context( } -static bool is_timing_changed(struct dc_stream *cur_stream, - struct dc_stream *new_stream) +static bool is_timing_changed(struct dc_stream_state *cur_stream, + struct dc_stream_state *new_stream) { if (cur_stream == NULL) return true; @@ -1141,7 +1141,7 @@ static bool is_timing_changed(struct dc_stream *cur_stream, } static bool are_stream_backends_same( - struct dc_stream *stream_a, struct dc_stream *stream_b) + struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) { if (stream_a == stream_b) return true; @@ -1156,7 +1156,7 @@ static bool are_stream_backends_same( } bool dc_is_stream_unchanged( - struct dc_stream *old_stream, struct dc_stream *stream) + struct dc_stream_state *old_stream, struct dc_stream_state *stream) { if (!are_stream_backends_same(old_stream, stream)) @@ -1233,7 +1233,7 @@ static void set_audio_in_use( static int acquire_first_free_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -1260,7 +1260,7 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; int j = -1; @@ -1311,7 +1311,7 @@ static struct audio *find_first_free_audio( return 0; } -static void update_stream_signal(struct dc_stream *stream) +static void update_stream_signal(struct dc_stream_state *stream) { if (stream->output_signal == SIGNAL_TYPE_NONE) { struct dc_sink *dc_sink = stream->sink; @@ -1334,12 +1334,12 @@ static void update_stream_signal(struct dc_stream *stream) } bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream *stream) + struct validate_context *old_context, struct dc_stream_state *stream) { int i; for (i = 0; i < old_context->stream_count; i++) { - struct dc_stream *old_stream = old_context->streams[i]; + struct dc_stream_state *old_stream = old_context->streams[i]; if (are_stream_backends_same(old_stream, stream)) return true; @@ -1352,7 +1352,7 @@ static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { struct dc_plane_state *surface = to_pipe_ctx->surface; - struct dc_stream *stream = to_pipe_ctx->stream; + struct dc_stream_state *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; @@ -1360,14 +1360,14 @@ static void copy_pipe_ctx( to_pipe_ctx->surface = surface; } -static struct dc_stream *find_pll_sharable_stream( - struct dc_stream *stream_needs_pll, +static struct dc_stream_state *find_pll_sharable_stream( + struct dc_stream_state *stream_needs_pll, struct validate_context *context) { int i; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream_has_pll = context->streams[i]; + struct dc_stream_state *stream_has_pll = context->streams[i]; /* We are looking for non dp, non virtual stream */ if (resource_are_streams_timing_synchronizable( @@ -1411,7 +1411,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct dc_stream *stream) +static void calculate_phy_pix_clks(struct dc_stream_state *stream) { update_stream_signal(stream); @@ -1433,7 +1433,7 @@ enum dc_status resource_map_pool_resources( int i, j; for (i = 0; old_context && i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -1486,7 +1486,7 @@ enum dc_status resource_map_pool_resources( } for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; @@ -1581,7 +1581,7 @@ static void set_avi_info_frame( struct encoder_info_packet *info_packet, struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; struct info_frame info_frame = { {0} }; uint32_t pixel_encoding = 0; @@ -1821,7 +1821,7 @@ static void set_avi_info_frame( static void set_vendor_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { uint32_t length = 0; bool hdmi_vic_mode = false; @@ -1934,7 +1934,7 @@ static void set_vendor_info_packet( static void set_spd_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { /* SPD info packet for FreeSync */ @@ -2056,7 +2056,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, struct dc_plane_state *surface, - struct dc_stream *stream) + struct dc_stream_state *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; @@ -2159,7 +2159,7 @@ static void set_hdr_static_info_packet( static void set_vsc_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int vscPacketRevision = 0; unsigned int i; @@ -2312,7 +2312,7 @@ enum dc_status resource_map_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -2392,7 +2392,7 @@ bool pipe_need_reprogram( return false; } -void resource_build_bit_depth_reduction_params(struct dc_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth) { enum dc_dither_option option = stream->dither_option; @@ -2502,7 +2502,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) +bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_context *dc_ctx = core_dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a77e1e80d7c2..7a87f38f2324 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -34,7 +34,7 @@ * Private functions ******************************************************************************/ -static bool construct(struct dc_stream *stream, +static bool construct(struct dc_stream_state *stream, struct dc_sink *dc_sink_data) { uint32_t i = 0; @@ -84,7 +84,7 @@ static bool construct(struct dc_stream *stream, return true; } -static void destruct(struct dc_stream *stream) +static void destruct(struct dc_stream_state *stream) { dc_sink_release(stream->sink); if (stream->out_transfer_func != NULL) { @@ -94,14 +94,14 @@ static void destruct(struct dc_stream *stream) } } -void dc_stream_retain(struct dc_stream *stream) +void dc_stream_retain(struct dc_stream_state *stream) { ASSERT(stream->ref_count > 0); stream->ref_count++; } -void dc_stream_release(struct dc_stream *stream) +void dc_stream_release(struct dc_stream_state *stream) { if (stream != NULL) { @@ -115,15 +115,15 @@ void dc_stream_release(struct dc_stream *stream) } } -struct dc_stream *dc_create_stream_for_sink( +struct dc_stream_state *dc_create_stream_for_sink( struct dc_sink *sink) { - struct dc_stream *stream; + struct dc_stream_state *stream; if (sink == NULL) goto alloc_fail; - stream = dm_alloc(sizeof(struct dc_stream)); + stream = dm_alloc(sizeof(struct dc_stream_state)); if (NULL == stream) goto alloc_fail; @@ -143,7 +143,7 @@ alloc_fail: } struct dc_stream_status *dc_stream_get_status( - struct dc_stream *stream) + struct dc_stream_state *stream) { uint8_t i; struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); @@ -161,7 +161,7 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *stream, + const struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes) { int i; @@ -196,7 +196,7 @@ bool dc_stream_set_cursor_attributes( } bool dc_stream_set_cursor_position( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct dc_cursor_position *position) { int i; @@ -245,7 +245,7 @@ bool dc_stream_set_cursor_position( return true; } -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) { uint8_t i; struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); @@ -264,7 +264,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) return 0; } -bool dc_stream_get_scanoutpos(const struct dc_stream *stream, +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -297,7 +297,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, void dc_stream_log( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dal_logger *dm_logger, enum dc_log_type log_type) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d1943b9644d4..ab805965e321 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -101,30 +101,30 @@ struct dc_cap_funcs { struct dc_surface_dcc_cap *output); }; -struct dc_stream_funcs { +struct dc_stream_state_funcs { bool (*adjust_vmin_vmax)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, int vmin, int vmax); bool (*get_crtc_position)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos); bool (*set_gamut_remap)(struct dc *dc, - const struct dc_stream *stream); + const struct dc_stream_state *stream); bool (*program_csc_matrix)(struct dc *dc, - struct dc_stream *stream); + struct dc_stream_state *stream); void (*set_static_screen_events)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, const struct dc_static_screen_events *events); - void (*set_dither_option)(struct dc_stream *stream, + void (*set_dither_option)(struct dc_stream_state *stream, enum dc_dither_option option); }; @@ -190,7 +190,7 @@ struct dc_debug { struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; - struct dc_stream_funcs stream_funcs; + struct dc_stream_state_funcs stream_funcs; struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; @@ -426,7 +426,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_plane_state **dc_surfaces, uint8_t surface_count, - struct dc_stream *stream); + struct dc_stream_state *stream); bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -478,7 +478,7 @@ struct dc_stream_status { struct dc_link *link; }; -struct dc_stream { +struct dc_stream_state { struct dc_sink *sink; struct dc_crtc_timing timing; @@ -529,7 +529,7 @@ struct dc_stream_update { }; bool dc_is_stream_unchanged( - struct dc_stream *old_stream, struct dc_stream *stream); + struct dc_stream_state *old_stream, struct dc_stream_state *stream); /* * Setup stream attributes if no stream updates are provided @@ -548,30 +548,30 @@ bool dc_is_stream_unchanged( void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); /* * Log the current stream state. */ void dc_stream_log( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dal_logger *dc_logger, enum dc_log_type log_type); uint8_t dc_get_current_stream_count(const struct dc *dc); -struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); +struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); /* * Return the current frame counter. */ -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); /* TODO: Return parsed values rather than direct register read * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -bool dc_stream_get_scanoutpos(const struct dc_stream *stream, +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -581,12 +581,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, * Structure to store surface/stream associations for validation */ struct dc_validation_set { - struct dc_stream *stream; + struct dc_stream_state *stream; struct dc_plane_state *surfaces[MAX_SURFACES]; uint8_t surface_count; }; -bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); +bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); /* @@ -615,7 +615,7 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - struct dc_stream *stream); + struct dc_stream_state *stream); void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, @@ -644,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_commit_streams( struct dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count); /* * Enable stereo when commit_streams is not required, @@ -653,19 +653,19 @@ bool dc_commit_streams( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count); /** * Create a new default stream for the requested sink */ -struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); +struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); -void dc_stream_retain(struct dc_stream *dc_stream); -void dc_stream_release(struct dc_stream *dc_stream); +void dc_stream_retain(struct dc_stream_state *dc_stream); +void dc_stream_release(struct dc_stream_state *dc_stream); struct dc_stream_status *dc_stream_get_status( - struct dc_stream *dc_stream); + struct dc_stream_state *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( struct dc *dc, @@ -804,7 +804,7 @@ const struct graphics_object_id dc_get_link_id_at_index( /* Set backlight level of an embedded panel (eDP, LVDS). */ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream *stream); + uint32_t frame_ramp, const struct dc_stream_state *stream); bool dc_link_set_abm_disable(const struct dc_link *dc_link); @@ -813,7 +813,7 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); bool dc_link_setup_psr(struct dc_link *dc_link, - const struct dc_stream *stream, struct psr_config *psr_config, + const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context); /* Request DC to detect if there is a Panel connected. @@ -927,11 +927,11 @@ bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container ******************************************************************************/ /* TODO: Deprecated once we switch to dc_set_cursor_position */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *stream, + const struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct dc_cursor_position *position); /* Newer interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 4fb9584452a4..a47f7472ea92 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -35,7 +35,7 @@ /* forward declarations */ struct dc_plane_state; -struct dc_stream; +struct dc_stream_state; struct dc_link; struct dc_sink; struct dal; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 24d0c48258ee..5bb2ac71f297 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 5f05ca65281e..5960fb933f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -196,7 +196,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream); + const struct dc_stream_state *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 2cf2fefc3d79..98fb7f02a6fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -765,7 +765,7 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 84dc8916de96..e4310a376116 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,7 +623,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -745,7 +745,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { @@ -833,7 +833,7 @@ static void build_audio_output( const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; audio_output->engine_id = pipe_ctx->stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -981,7 +981,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -1037,7 +1037,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; @@ -1229,7 +1229,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { uint32_t total_dest_line_time_ns; uint32_t pstate_blackout_duration_ns; @@ -2325,7 +2325,7 @@ void dce110_fill_display_configs( for (j = 0; j < context->stream_count; j++) { int k; - const struct dc_stream *stream = context->streams[j]; + const struct dc_stream_state *stream = context->streams[j]; struct dm_pp_single_disp_config *cfg = &pp_display_cfg->disp_configs[num_cfgs]; const struct pipe_ctx *pipe_ctx = NULL; @@ -2370,7 +2370,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) uint32_t min_vertical_blank_time = -1; for (j = 0; j < context->stream_count; j++) { - struct dc_stream *stream = context->streams[j]; + struct dc_stream_state *stream = context->streams[j]; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 5c1790b61290..89b21bd57a35 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -718,7 +718,7 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; /*TODO: is this halved for YCbCr 420? in that case we might want to move * the pixel clock normalization for hdmi up to here instead of doing it @@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -973,7 +973,7 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index c68372fa1292..68554d6edd94 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -700,7 +700,7 @@ static void destruct(struct dce110_resource_pool *pool) static struct clock_source *find_matching_pll( struct resource_context *res_ctx, const struct resource_pool *pool, - const struct dc_stream *const stream) + const struct dc_stream_state *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: @@ -731,7 +731,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -845,7 +845,7 @@ enum dc_status resource_map_phy_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -949,7 +949,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index cb2c69fb05a6..feef559f1ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index bcb66447b558..734b35eddeed 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -677,7 +677,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -781,7 +781,7 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3979cb03cf8d..866f63d1259d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -679,7 +679,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space; struct tg_color black_color = {0}; bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? @@ -1445,7 +1445,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -2321,7 +2321,7 @@ static void set_plane_config( } static void dcn10_config_stereo_parameters( - struct dc_stream *stream, struct crtc_stereo_flags *flags) + struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { enum view_3d_format view_format = stream->view_format; enum dc_timing_3d_format timing_3d_format =\ @@ -2360,7 +2360,7 @@ static void dcn10_config_stereo_parameters( static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) { struct crtc_stereo_flags flags = { 0 }; - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; dcn10_config_stereo_parameters(stream, &flags); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9d44f42cbf96..5a9fcbc22d04 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -774,7 +774,7 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; @@ -796,7 +796,7 @@ static void get_pixel_clock_parameters( } -static void build_clamping_params(struct dc_stream *stream) +static void build_clamping_params(struct dc_stream_state *stream) { stream->clamping.clamping_level = CLAMPING_FULL_RANGE; stream->clamping.c_depth = stream->timing.display_color_depth; @@ -831,7 +831,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -916,7 +916,7 @@ enum dc_status dcn10_validate_with_context( enum dc_status dcn10_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -947,7 +947,7 @@ enum dc_status dcn10_validate_guaranteed( static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index e8bd501feb48..39010325cef9 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -45,7 +45,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable); @@ -54,13 +54,13 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( */ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, - const struct dc_stream *stream); + const struct dc_stream_state *stream); /* * Sends ALLOCATE_PAYLOAD message. */ bool dm_helpers_dp_mst_send_payload_allocation( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, bool enable); bool dm_helpers_dp_mst_start_top_mgr( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 44a87c9427f7..d5c0f9e34ce9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -60,7 +60,7 @@ struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing); @@ -92,7 +92,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context); bool (*validate_bandwidth)( @@ -102,8 +102,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream); - + struct dc_stream_state *stream); enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); }; @@ -155,7 +154,7 @@ struct resource_pool { struct pipe_ctx { struct dc_plane_state *surface; - struct dc_stream *stream; + struct dc_stream_state *stream; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -240,7 +239,7 @@ union bw_context { }; struct validate_context { - struct dc_stream *streams[MAX_PIPES]; + struct dc_stream_state *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index 1a4a605cb449..7168dcc70ae7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,7 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ struct dc_link; -struct dc_stream; +struct dc_stream_state; struct dc_link_settings; bool dp_hbr_verify_link_cap( @@ -50,7 +50,7 @@ bool dp_validate_mode_timing( const struct dc_crtc_timing *timing); void decide_link_settings( - struct dc_stream *stream, + struct dc_stream_state *stream, struct dc_link_settings *link_setting); bool perform_link_training_with_retries( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 28fb02fb677e..38e4070806cb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -93,7 +93,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, const struct dc_stream *stream); + struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index c529ddd2e0d5..7e03f8d45b2b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -92,7 +92,7 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream); + const struct dc_stream_state *stream); void (*power_down)(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index bfd7cfc86df0..aef1197cf749 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,8 +103,8 @@ void resource_reference_clock_source( struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( - struct dc_stream *stream1, - struct dc_stream *stream2); + struct dc_stream_state *stream1, + struct dc_stream_state *stream2); struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, @@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream); + struct dc_stream_state *stream); bool resource_attach_surfaces_to_context( struct dc_plane_state *const *surfaces, int surface_count, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context, const struct resource_pool *pool); @@ -130,8 +130,7 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream *stream); - + struct validate_context *old_context, struct dc_stream_state *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], @@ -162,7 +161,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); -void resource_build_bit_depth_reduction_params(struct dc_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index dd024c99fb7e..57b5a3babdf8 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream) { return true; } + const struct dc_stream_state *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 358f8a855a59..f0a3e4332a09 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -111,7 +111,7 @@ struct freesync_state { }; struct freesync_entity { - struct dc_stream *stream; + struct dc_stream_state *stream; struct mod_freesync_caps *caps; struct freesync_state state; struct mod_freesync_user_enable user_enable; @@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) * on the core_freesync->map and returns the corresponding index */ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index = 0; @@ -244,7 +244,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, } bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream, struct mod_freesync_caps *caps) + struct dc_stream_state *stream, struct mod_freesync_caps *caps) { struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; @@ -322,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i = 0; struct core_freesync *core_freesync = NULL; @@ -344,7 +344,7 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, } static void update_stream_freesync_context(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index; struct freesync_context *ctx; @@ -368,7 +368,7 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync, } static void update_stream(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].caps->supported) { @@ -378,7 +378,7 @@ static void update_stream(struct core_freesync *core_freesync, } static void calc_freesync_range(struct core_freesync *core_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct freesync_state *state, unsigned int min_refresh_in_uhz, unsigned int max_refresh_in_uhz) @@ -452,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) / 2000; } -static void calc_v_total_from_duration(struct dc_stream *stream, +static void calc_v_total_from_duration(struct dc_stream_state *stream, unsigned int duration_in_ns, int *v_total_nominal) { *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( @@ -461,7 +461,7 @@ static void calc_v_total_from_duration(struct dc_stream *stream, } static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int index, int *v_total) { unsigned int frame_duration = 0; @@ -557,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state) * Sets freesync mode on a stream depending on current freesync state. */ static bool set_freesync_on_streams(struct core_freesync *core_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; unsigned int stream_idx, map_index = 0; @@ -729,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { unsigned int index, v_total, inserted_frame_v_total = 0; unsigned int min_frame_duration_in_ns, vmax, vmin = 0; @@ -839,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } void mod_freesync_update_state(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_params *freesync_params) { bool freesync_program_required = false; @@ -929,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_params *freesync_params) { unsigned int index = 0; @@ -965,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, } bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { unsigned int stream_index, map_index; @@ -1017,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_user_enable *user_enable) { unsigned int index = 0; @@ -1035,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, bool *is_ramp_active) { unsigned int index = 0; @@ -1054,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, } bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *streams, + struct dc_stream_state *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps) @@ -1107,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *min_refresh, unsigned int *max_refresh) { @@ -1129,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *vmin, unsigned int *vmax) { @@ -1151,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, } bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *nom_v_pos, unsigned int *v_pos) { @@ -1179,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { unsigned int stream_index, map_index; struct freesync_state *state; @@ -1239,7 +1239,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, * is required, depending on the times calculated */ static void update_timestamps(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index, + const struct dc_stream_state *stream, unsigned int map_index, unsigned int last_render_time_in_us) { struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1304,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync, } static void apply_below_the_range(struct core_freesync *core_freesync, - struct dc_stream *stream, unsigned int map_index, + struct dc_stream_state *stream, unsigned int map_index, unsigned int last_render_time_in_us) { unsigned int inserted_frame_duration_in_us = 0; @@ -1403,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, } static void apply_fixed_refresh(struct core_freesync *core_freesync, - struct dc_stream *stream, unsigned int map_index) + struct dc_stream_state *stream, unsigned int map_index) { unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1434,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, } void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 2b9d45100bdd..84b53425f2c8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -101,67 +101,67 @@ struct mod_freesync_params { * Add stream to be tracked by module */ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream, struct mod_freesync_caps *caps); + struct dc_stream_state *stream, struct mod_freesync_caps *caps); /* * Remove stream to be tracked by module */ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream); + struct dc_stream_state *stream); /* * Update the freesync state flags for each display and program * freesync accordingly */ void mod_freesync_update_state(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_params *freesync_params); bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_params *freesync_params); bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, bool *is_ramp_active); bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *streams, + struct dc_stream_state *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *min_refresh, unsigned int *max_refresh); bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *vmin, unsigned int *vmax); bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *nom_v_pos, unsigned int *v_pos); void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams); + struct dc_stream_state **streams, int num_streams); void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams); + struct dc_stream_state **streams, int num_streams); void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int curr_time_stamp); #endif -- cgit v1.2.3-59-g8ed1b From 3be5262e353b8ab97c528bfc7d0dd3c820e4ba27 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:55:38 -0400 Subject: drm/amd/display: Rename more dc_surface stuff to plane_state Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 288 +++++++++++---------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 20 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 52 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 130 +++++----- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 188 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 190 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 74 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 32 +-- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 125 +++++---- .../drm/amd/display/dc/dce110/dce110_resource.c | 20 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 140 +++++----- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 2 +- 24 files changed, 658 insertions(+), 657 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 497104a29d89..08567b3631cf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -70,7 +70,7 @@ #include "i2caux_interface.h" -static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -79,14 +79,14 @@ static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, }; -static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ }; -static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ @@ -1285,11 +1285,11 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) return -1; } - for (i = 0; i < dm->dc->caps.max_surfaces; i++) { + for (i = 0; i < dm->dc->caps.max_planes; i++) { mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); if (!mode_info->planes[i]) { - DRM_ERROR("KMS: Failed to allocate surface\n"); + DRM_ERROR("KMS: Failed to allocate plane\n"); goto fail_free_planes; } mode_info->planes[i]->base.type = mode_info->plane_type[i]; @@ -1389,7 +1389,7 @@ fail_free_encoder: fail_free_connector: kfree(aconnector); fail_free_planes: - for (i = 0; i < dm->dc->caps.max_surfaces; i++) + for (i = 0; i < dm->dc->caps.max_planes; i++) kfree(mode_info->planes[i]); return -1; } @@ -1518,52 +1518,52 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - adev->mode_info.plane_type = dm_surfaces_type_carizzo; + adev->mode_info.plane_type = dm_plane_type_carizzo; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - adev->mode_info.plane_type = dm_surfaces_type_stoney; + adev->mode_info.plane_type = dm_plane_type_stoney; break; case CHIP_POLARIS11: case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_VEGA10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: adev->mode_info.num_crtc = 4; adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; #endif default: @@ -1821,50 +1821,50 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, static bool fill_rects_from_plane_state( const struct drm_plane_state *state, - struct dc_plane_state *surface) + struct dc_plane_state *plane_state) { - surface->src_rect.x = state->src_x >> 16; - surface->src_rect.y = state->src_y >> 16; + plane_state->src_rect.x = state->src_x >> 16; + plane_state->src_rect.y = state->src_y >> 16; /*we ignore for now mantissa and do not to deal with floating pixels :(*/ - surface->src_rect.width = state->src_w >> 16; + plane_state->src_rect.width = state->src_w >> 16; - if (surface->src_rect.width == 0) + if (plane_state->src_rect.width == 0) return false; - surface->src_rect.height = state->src_h >> 16; - if (surface->src_rect.height == 0) + plane_state->src_rect.height = state->src_h >> 16; + if (plane_state->src_rect.height == 0) return false; - surface->dst_rect.x = state->crtc_x; - surface->dst_rect.y = state->crtc_y; + plane_state->dst_rect.x = state->crtc_x; + plane_state->dst_rect.y = state->crtc_y; if (state->crtc_w == 0) return false; - surface->dst_rect.width = state->crtc_w; + plane_state->dst_rect.width = state->crtc_w; if (state->crtc_h == 0) return false; - surface->dst_rect.height = state->crtc_h; + plane_state->dst_rect.height = state->crtc_h; - surface->clip_rect = surface->dst_rect; + plane_state->clip_rect = plane_state->dst_rect; switch (state->rotation & DRM_MODE_ROTATE_MASK) { case DRM_MODE_ROTATE_0: - surface->rotation = ROTATION_ANGLE_0; + plane_state->rotation = ROTATION_ANGLE_0; break; case DRM_MODE_ROTATE_90: - surface->rotation = ROTATION_ANGLE_90; + plane_state->rotation = ROTATION_ANGLE_90; break; case DRM_MODE_ROTATE_180: - surface->rotation = ROTATION_ANGLE_180; + plane_state->rotation = ROTATION_ANGLE_180; break; case DRM_MODE_ROTATE_270: - surface->rotation = ROTATION_ANGLE_270; + plane_state->rotation = ROTATION_ANGLE_270; break; default: - surface->rotation = ROTATION_ANGLE_0; + plane_state->rotation = ROTATION_ANGLE_0; break; } @@ -1896,7 +1896,7 @@ static int get_fb_info( static int fill_plane_attributes_from_fb( struct amdgpu_device *adev, - struct dc_plane_state *surface, + struct dc_plane_state *plane_state, const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) { uint64_t tiling_flags; @@ -1916,28 +1916,28 @@ static int fill_plane_attributes_from_fb( switch (fb->format->format) { case DRM_FORMAT_C8: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; break; case DRM_FORMAT_RGB565: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; break; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; break; case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; break; case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; break; case DRM_FORMAT_NV21: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; + plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; break; case DRM_FORMAT_NV12: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; + plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; default: DRM_ERROR("Unsupported screen format %s\n", @@ -1945,45 +1945,45 @@ static int fill_plane_attributes_from_fb( return -EINVAL; } - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.type = PLN_ADDR_TYPE_GRAPHICS; - surface->address.grph.addr.low_part = lower_32_bits(fb_location); - surface->address.grph.addr.high_part = upper_32_bits(fb_location); - surface->plane_size.grph.surface_size.x = 0; - surface->plane_size.grph.surface_size.y = 0; - surface->plane_size.grph.surface_size.width = fb->width; - surface->plane_size.grph.surface_size.height = fb->height; - surface->plane_size.grph.surface_pitch = + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; + plane_state->address.grph.addr.low_part = lower_32_bits(fb_location); + plane_state->address.grph.addr.high_part = upper_32_bits(fb_location); + plane_state->plane_size.grph.surface_size.x = 0; + plane_state->plane_size.grph.surface_size.y = 0; + plane_state->plane_size.grph.surface_size.width = fb->width; + plane_state->plane_size.grph.surface_size.height = fb->height; + plane_state->plane_size.grph.surface_pitch = fb->pitches[0] / fb->format->cpp[0]; /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_SRGB; + plane_state->color_space = COLOR_SPACE_SRGB; } else { awidth = ALIGN(fb->width, 64); - surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - surface->address.video_progressive.luma_addr.low_part + plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; + plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(fb_location); - surface->address.video_progressive.chroma_addr.low_part + plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(fb_location) + (awidth * fb->height); - surface->plane_size.video.luma_size.x = 0; - surface->plane_size.video.luma_size.y = 0; - surface->plane_size.video.luma_size.width = awidth; - surface->plane_size.video.luma_size.height = fb->height; + plane_state->plane_size.video.luma_size.x = 0; + plane_state->plane_size.video.luma_size.y = 0; + plane_state->plane_size.video.luma_size.width = awidth; + plane_state->plane_size.video.luma_size.height = fb->height; /* TODO: unhardcode */ - surface->plane_size.video.luma_pitch = awidth; + plane_state->plane_size.video.luma_pitch = awidth; - surface->plane_size.video.chroma_size.x = 0; - surface->plane_size.video.chroma_size.y = 0; - surface->plane_size.video.chroma_size.width = awidth; - surface->plane_size.video.chroma_size.height = fb->height; - surface->plane_size.video.chroma_pitch = awidth / 2; + plane_state->plane_size.video.chroma_size.x = 0; + plane_state->plane_size.video.chroma_size.y = 0; + plane_state->plane_size.video.chroma_size.width = awidth; + plane_state->plane_size.video.chroma_size.height = fb->height; + plane_state->plane_size.video.chroma_pitch = awidth / 2; /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_YCBCR709; + plane_state->color_space = COLOR_SPACE_YCBCR709; } - memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); + memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); /* Fill GFX8 params */ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { @@ -1996,51 +1996,51 @@ static int fill_plane_attributes_from_fb( num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); /* XXX fix me for VI */ - surface->tiling_info.gfx8.num_banks = num_banks; - surface->tiling_info.gfx8.array_mode = + plane_state->tiling_info.gfx8.num_banks = num_banks; + plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_2D_TILED_THIN1; - surface->tiling_info.gfx8.tile_split = tile_split; - surface->tiling_info.gfx8.bank_width = bankw; - surface->tiling_info.gfx8.bank_height = bankh; - surface->tiling_info.gfx8.tile_aspect = mtaspect; - surface->tiling_info.gfx8.tile_mode = + plane_state->tiling_info.gfx8.tile_split = tile_split; + plane_state->tiling_info.gfx8.bank_width = bankw; + plane_state->tiling_info.gfx8.bank_height = bankh; + plane_state->tiling_info.gfx8.tile_aspect = mtaspect; + plane_state->tiling_info.gfx8.tile_mode = DC_ADDR_SURF_MICRO_TILING_DISPLAY; } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_1D_TILED_THIN1) { - surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; + plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; } - surface->tiling_info.gfx8.pipe_config = + plane_state->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); if (adev->asic_type == CHIP_VEGA10 || adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ - surface->tiling_info.gfx9.num_pipes = + plane_state->tiling_info.gfx9.num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; - surface->tiling_info.gfx9.num_banks = + plane_state->tiling_info.gfx9.num_banks = adev->gfx.config.gb_addr_config_fields.num_banks; - surface->tiling_info.gfx9.pipe_interleave = + plane_state->tiling_info.gfx9.pipe_interleave = adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; - surface->tiling_info.gfx9.num_shader_engines = + plane_state->tiling_info.gfx9.num_shader_engines = adev->gfx.config.gb_addr_config_fields.num_se; - surface->tiling_info.gfx9.max_compressed_frags = + plane_state->tiling_info.gfx9.max_compressed_frags = adev->gfx.config.gb_addr_config_fields.max_compress_frags; - surface->tiling_info.gfx9.num_rb_per_se = + plane_state->tiling_info.gfx9.num_rb_per_se = adev->gfx.config.gb_addr_config_fields.num_rb_per_se; - surface->tiling_info.gfx9.swizzle = + plane_state->tiling_info.gfx9.swizzle = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); - surface->tiling_info.gfx9.shaderEnable = 1; + plane_state->tiling_info.gfx9.shaderEnable = 1; } - surface->visible = true; - surface->scaling_quality.h_taps_c = 0; - surface->scaling_quality.v_taps_c = 0; + plane_state->visible = true; + plane_state->scaling_quality.h_taps_c = 0; + plane_state->scaling_quality.v_taps_c = 0; - /* is this needed? is surface zeroed at allocation? */ - surface->scaling_quality.h_taps = 0; - surface->scaling_quality.v_taps = 0; - surface->stereo_format = PLANE_STEREO_FORMAT_NONE; + /* is this needed? is plane_state zeroed at allocation? */ + plane_state->scaling_quality.h_taps = 0; + plane_state->scaling_quality.v_taps = 0; + plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; return ret; @@ -2050,7 +2050,7 @@ static int fill_plane_attributes_from_fb( static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_surface) + struct dc_plane_state *plane_state) { int i; struct dc_gamma *gamma; @@ -2069,12 +2069,12 @@ static void fill_gamma_from_crtc_state( gamma->blue[i] = lut[i].blue; } - dc_surface->gamma_correction = gamma; + plane_state->gamma_correction = gamma; } static int fill_plane_attributes( struct amdgpu_device *adev, - struct dc_plane_state *surface, + struct dc_plane_state *dc_plane_state, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state, bool addrReq) @@ -2085,12 +2085,12 @@ static int fill_plane_attributes( struct dc_transfer_func *input_tf; int ret = 0; - if (!fill_rects_from_plane_state(plane_state, surface)) + if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) return -EINVAL; ret = fill_plane_attributes_from_fb( crtc->dev->dev_private, - surface, + dc_plane_state, amdgpu_fb, addrReq); @@ -2105,11 +2105,11 @@ static int fill_plane_attributes( input_tf->type = TF_TYPE_PREDEFINED; input_tf->tf = TRANSFER_FUNCTION_SRGB; - surface->in_transfer_func = input_tf; + dc_plane_state->in_transfer_func = input_tf; /* In case of gamma set, update gamma value */ if (crtc_state->gamma_lut) - fill_gamma_from_crtc_state(crtc_state, surface); + fill_gamma_from_crtc_state(crtc_state, dc_plane_state); return ret; } @@ -2991,9 +2991,9 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); - if (old_dm_plane_state->surface) { - dm_plane_state->surface = old_dm_plane_state->surface; - dc_surface_retain(dm_plane_state->surface); + if (old_dm_plane_state->dc_state) { + dm_plane_state->dc_state = old_dm_plane_state->dc_state; + dc_plane_state_retain(dm_plane_state->dc_state); } return &dm_plane_state->base; @@ -3004,8 +3004,8 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane, { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); __drm_atomic_helper_plane_destroy_state(state); kfree(dm_plane_state); @@ -3059,18 +3059,18 @@ static int dm_plane_helper_prepare_fb( amdgpu_bo_ref(rbo); - if (dm_plane_state_new->surface && - dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_plane_state *surface = dm_plane_state_new->surface; + if (dm_plane_state_new->dc_state && + dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { + struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.grph.addr.low_part = lower_32_bits(afb->address); - surface->address.grph.addr.high_part = upper_32_bits(afb->address); + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); + plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); } else { awidth = ALIGN(new_state->fb->width, 64); - surface->address.video_progressive.luma_addr.low_part + plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(afb->address); - surface->address.video_progressive.chroma_addr.low_part + plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(afb->address) + (awidth * new_state->fb->height); } @@ -3159,10 +3159,10 @@ int dm_plane_atomic_check(struct drm_plane *plane, struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - if (!dm_plane_state->surface) + if (!dm_plane_state->dc_state) return true; - if (dc_validate_plane(dc, dm_plane_state->surface)) + if (dc_validate_plane(dc, dm_plane_state->dc_state)) return 0; return -EINVAL; @@ -3848,6 +3848,7 @@ static void amdgpu_dm_do_flip( struct amdgpu_device *adev = crtc->dev->dev_private; bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; struct dc_flip_addrs addr = { {0} }; + /* TODO eliminate or rename surface_update */ struct dc_surface_update surface_updates[1] = { {0} }; struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); @@ -3903,11 +3904,11 @@ static void amdgpu_dm_do_flip( if (acrtc->base.state->event) prepare_flip_isr(acrtc); - surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0]; + surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0]; surface_updates->flip_addr = &addr; - dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); + dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, @@ -3918,7 +3919,7 @@ static void amdgpu_dm_do_flip( spin_unlock_irqrestore(&crtc->dev->event_lock, flags); } -static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, +static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct drm_device *dev, struct amdgpu_display_manager *dm, struct drm_crtc *pcrtc, @@ -3928,7 +3929,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; struct dc_stream_state *dc_stream_attach; - struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -3956,8 +3957,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_lock_irqsave(&crtc->dev->event_lock, flags); if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { - DRM_ERROR("add_surface: acrtc %d, already busy\n", - acrtc_attach->crtc_id); + DRM_ERROR("%s: acrtc %d, already busy\n", + __func__, + acrtc_attach->crtc_id); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); /* In commit tail framework this cannot happen */ WARN_ON(1); @@ -3965,9 +3967,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_unlock_irqrestore(&crtc->dev->event_lock, flags); if (!pflip_needed) { - WARN_ON(!dm_plane_state->surface); + WARN_ON(!dm_plane_state->dc_state); - dc_surfaces_constructed[planes_count] = dm_plane_state->surface; + plane_states_constructed[planes_count] = dm_plane_state->dc_state; dc_stream_attach = acrtc_state->stream; planes_count++; @@ -4010,11 +4012,11 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); } - if (false == dc_commit_surfaces_to_stream(dm->dc, - dc_surfaces_constructed, - planes_count, - dc_stream_attach)) - dm_error("%s: Failed to attach surface!\n", __func__); + if (false == dc_commit_planes_to_stream(dm->dc, + plane_states_constructed, + planes_count, + dc_stream_attach)) + dm_error("%s: Failed to attach plane!\n", __func__); } else { /*TODO BUG Here should go disable planes on CRTC. */ } @@ -4226,16 +4228,16 @@ void amdgpu_dm_atomic_commit_tail( status = dc_stream_get_status(new_acrtc_state->stream); WARN_ON(!status); - WARN_ON(!status->surface_count); + WARN_ON(!status->plane_count); if (!new_acrtc_state->stream) continue; /*TODO How it works with MPO ?*/ - if (!dc_commit_surfaces_to_stream( + if (!dc_commit_planes_to_stream( dm->dc, - status->surfaces, - status->surface_count, + status->plane_states, + status->plane_count, new_acrtc_state->stream)) dm_error("%s: Failed to update stream scaling!\n", __func__); } @@ -4260,7 +4262,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(pcrtc->state); if (new_acrtc_state->stream) - amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); + amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank); } @@ -4375,27 +4377,27 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector dm_force_atomic_commit(&aconnector->base); } -static uint32_t add_val_sets_surface( +static uint32_t add_val_sets_plane( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream_state *stream, - struct dc_plane_state *surface) + struct dc_plane_state *plane_state) { uint32_t i = 0, j = 0; while (i < set_count) { if (val_sets[i].stream == stream) { - while (val_sets[i].surfaces[j]) + while (val_sets[i].plane_states[j]) j++; break; } ++i; } - val_sets[i].surfaces[j] = surface; - val_sets[i].surface_count++; + val_sets[i].plane_states[j] = plane_state; + val_sets[i].plane_count++; - return val_sets[i].surface_count; + return val_sets[i].plane_count; } static uint32_t update_in_val_sets_stream( @@ -4516,7 +4518,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, /* * This bool will be set for true for any modeset/reset - * or surface update which implies non fast surface update. + * or plane update which implies non fast surface update. */ bool lock_and_validation_needed = false; @@ -4701,13 +4703,13 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, pflip_needed = !state->allow_modeset; if (!pflip_needed) { - struct dc_plane_state *surface; + struct dc_plane_state *dc_plane_state; - surface = dc_create_surface(dc); + dc_plane_state = dc_create_plane_state(dc); ret = fill_plane_attributes( plane_crtc->dev->dev_private, - surface, + dc_plane_state, plane_state, crtc_state, false); @@ -4715,15 +4717,15 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); - dm_plane_state->surface = surface; + dm_plane_state->dc_state = dc_plane_state; - add_val_sets_surface(set, + add_val_sets_plane(set, set_count, new_acrtc_state->stream, - surface); + dc_plane_state); lock_and_validation_needed = true; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index cca65a37b213..e0a5632f00a3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -196,7 +196,7 @@ struct dc_stream; struct dm_plane_state { struct drm_plane_state base; - struct dc_plane_state *surface; + struct dc_plane_state *dc_state; }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 9a850227eeeb..28dbd18b2d86 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2594,15 +2594,15 @@ static void populate_initial_data( if (!pipe[i].stream || !pipe[i].bottom_pipe) continue; - ASSERT(pipe[i].surface); + ASSERT(pipe[i].plane_state); if (num_displays == 0) { - if (!pipe[i].surface->visible) + if (!pipe[i].plane_state->visible) data->d0_underlay_mode = bw_def_underlay_only; else data->d0_underlay_mode = bw_def_blend; } else { - if (!pipe[i].surface->visible) + if (!pipe[i].plane_state->visible) data->d1_underlay_mode = bw_def_underlay_only; else data->d1_underlay_mode = bw_def_blend; @@ -2620,7 +2620,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->rotation) { + switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2636,7 +2636,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->format) { + switch (pipe[i].plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: case SURFACE_PIXEL_FORMAT_GRPH_RGB565: @@ -2670,14 +2670,14 @@ static void populate_initial_data( data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.height); data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.width); data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed( - pipe[i].bottom_pipe->surface->plane_size.grph.surface_pitch); + pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch); data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.h_taps); data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.v_taps); data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.horz.value); data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.vert.value); - switch (pipe[i].bottom_pipe->surface->rotation) { + switch (pipe[i].bottom_pipe->plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0); break; @@ -2710,7 +2710,7 @@ static void populate_initial_data( data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); - if (pipe[i].surface) { + if (pipe[i].plane_state) { data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); @@ -2718,7 +2718,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->rotation) { + switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2734,7 +2734,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->format) { + switch (pipe[i].plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 7f7cb8ff124d..404b39e7b44b 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -233,16 +233,16 @@ static void pipe_ctx_to_e2e_pipe_params ( struct _vcs_dpi_display_pipe_params_st *input) { input->src.is_hsplit = false; - if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) input->src.is_hsplit = true; - else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface) + else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) input->src.is_hsplit = true; - input->src.dcc = pipe->surface->dcc.enable; + input->src.dcc = pipe->plane_state->dcc.enable; input->src.dcc_rate = 1; - input->src.meta_pitch = pipe->surface->dcc.grph.meta_pitch; + input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; input->src.source_scan = dm_horz; - input->src.sw_mode = pipe->surface->tiling_info.gfx9.swizzle; + input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; input->src.viewport_width = pipe->scl_data.viewport.width; input->src.viewport_height = pipe->scl_data.viewport.height; @@ -251,7 +251,7 @@ static void pipe_ctx_to_e2e_pipe_params ( input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ input->src.cur0_bpp = 32; - switch (pipe->surface->tiling_info.gfx9.swizzle) { + switch (pipe->plane_state->tiling_info.gfx9.swizzle) { /* for 4/8/16 high tiles */ case DC_SW_LINEAR: input->src.is_display_sw = 1; @@ -299,7 +299,7 @@ static void pipe_ctx_to_e2e_pipe_params ( break; } - switch (pipe->surface->rotation) { + switch (pipe->plane_state->rotation) { case ROTATION_ANGLE_0: case ROTATION_ANGLE_180: input->src.source_scan = dm_horz; @@ -314,7 +314,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } /* TODO: Fix pixel format mappings */ - switch (pipe->surface->format) { + switch (pipe->plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: input->src.source_format = dm_420_8; @@ -455,7 +455,7 @@ static void dcn_bw_calc_rq_dlg_ttu( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->flip_immediate); + pipe->plane_state->flip_immediate); } static void dcn_dml_wm_override( @@ -478,7 +478,7 @@ static void dcn_dml_wm_override( for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream || !pipe->surface) + if (!pipe->stream || !pipe->plane_state) continue; input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk; @@ -516,7 +516,7 @@ static void dcn_dml_wm_override( for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream || !pipe->surface) + if (!pipe->stream || !pipe->plane_state) continue; dml_rq_dlg_get_dlg_reg(dml, @@ -527,7 +527,7 @@ static void dcn_dml_wm_override( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->flip_immediate); + pipe->plane_state->flip_immediate); in_idx++; } dm_free(input); @@ -541,7 +541,7 @@ static void split_stream_across_pipes( { int pipe_idx = secondary_pipe->pipe_idx; - if (!primary_pipe->surface) + if (!primary_pipe->plane_state) return; *secondary_pipe = *primary_pipe; @@ -843,7 +843,7 @@ bool dcn_validate_bandwidth( if (!pipe->stream) continue; /* skip all but first of split pipes */ - if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; v->underscan_output[input_idx] = false; /* taken care of in recout already*/ @@ -869,7 +869,7 @@ bool dcn_validate_bandwidth( } } - if (!pipe->surface){ + if (!pipe->plane_state) { v->dcc_enable[input_idx] = dcn_bw_yes; v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; @@ -889,8 +889,8 @@ bool dcn_validate_bandwidth( v->viewport_width[input_idx] = pipe->scl_data.viewport.width; v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width; v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height; - if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) { - if (pipe->surface->rotation % 2 == 0) { + if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { + if (pipe->plane_state->rotation % 2 == 0) { int viewport_end = pipe->scl_data.viewport.width + pipe->scl_data.viewport.x; int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width @@ -919,17 +919,17 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->scl_data.recout.width; } - v->dcc_enable[input_idx] = pipe->surface->dcc.enable ? dcn_bw_yes : dcn_bw_no; + v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( - pipe->surface->format); + pipe->plane_state->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( - pipe->surface->tiling_info.gfx9.swizzle); + pipe->plane_state->tiling_info.gfx9.swizzle); v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth); v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps; v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps; v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c; v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c; - v->source_scan[input_idx] = (pipe->surface->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; + v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; @@ -996,7 +996,7 @@ bool dcn_validate_bandwidth( if (!pipe->stream) continue; /* skip all but first of split pipes */ - if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; @@ -1024,7 +1024,7 @@ bool dcn_validate_bandwidth( pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe->pipe_dlg_param.vblank_end = asic_blank_end; - if (pipe->surface) { + if (pipe->plane_state) { struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; if (v->dpp_per_plane[input_idx] == 2 || @@ -1036,7 +1036,7 @@ bool dcn_validate_bandwidth( TIMING_3D_FORMAT_TOP_AND_BOTTOM || pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE))) { - if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { + if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* update previously split pipe */ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx]; @@ -1057,12 +1057,12 @@ bool dcn_validate_bandwidth( } dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe); - } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { + } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* merge previously split pipe */ pipe->bottom_pipe = hsplit_pipe->bottom_pipe; if (hsplit_pipe->bottom_pipe) hsplit_pipe->bottom_pipe->top_pipe = pipe; - hsplit_pipe->surface = NULL; + hsplit_pipe->plane_state = NULL; hsplit_pipe->stream = NULL; hsplit_pipe->top_pipe = NULL; hsplit_pipe->bottom_pipe = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8b6b7631d776..ffc9c05e2fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -639,21 +639,21 @@ static bool is_validation_required( for (i = 0; i < set_count; i++) { - if (set[i].surface_count != context->stream_status[i].surface_count) + if (set[i].plane_count != context->stream_status[i].plane_count) return true; if (!dc_is_stream_unchanged(set[i].stream, context->streams[i])) return true; - for (j = 0; j < set[i].surface_count; j++) { - struct dc_plane_state temp_surf; - memset(&temp_surf, 0, sizeof(temp_surf)); + for (j = 0; j < set[i].plane_count; j++) { + struct dc_plane_state temp_plane; + memset(&temp_plane, 0, sizeof(temp_plane)); - temp_surf = *context->stream_status[i].surfaces[j]; - temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; - temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; - temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; + temp_plane = *context->stream_status[i].plane_states[j]; + temp_plane.clip_rect = set[i].plane_states[j]->clip_rect; + temp_plane.dst_rect.x = set[i].plane_states[j]->dst_rect.x; + temp_plane.dst_rect.y = set[i].plane_states[j]->dst_rect.y; - if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0) + if (memcmp(&temp_plane, set[i].plane_states[j], sizeof(temp_plane)) != 0) return true; } } @@ -683,8 +683,8 @@ static bool validate_surfaces( int i, j; for (i = 0; i < set_count; i++) - for (j = 0; j < set[i].surface_count; j++) - if (!dc_validate_plane(dc, set[i].surfaces[j])) + for (j = 0; j < set[i].plane_count; j++) + if (!dc_validate_plane(dc, set[i].plane_states[j])) return false; return true; @@ -977,11 +977,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; - for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_plane_state *surface = - context->stream_status[i].surfaces[j]; + for (j = 0; j < context->stream_status[i].plane_count; j++) { + const struct dc_plane_state *plane_state = + context->stream_status[i].plane_states[j]; - core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); + core_dc->hwss.apply_ctx_for_surface(core_dc, plane_state, context); /* * enable stereo @@ -1073,9 +1073,9 @@ bool dc_commit_streams( set[i].stream = stream; if (status) { - set[i].surface_count = status->surface_count; - for (j = 0; j < status->surface_count; j++) - set[i].surfaces[j] = status->surfaces[j]; + set[i].plane_count = status->plane_count; + for (j = 0; j < status->plane_count; j++) + set[i].plane_states[j] = status->plane_states[j]; } } @@ -1122,7 +1122,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) for (i = 0; i < core_dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].surface == NULL) + || context->res_ctx.pipe_ctx[i].plane_state == NULL) core_dc->hwss.power_down_front_end(core_dc, i); /* 3rd param should be true, temp w/a for RV*/ @@ -1134,10 +1134,10 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) return true; } -bool dc_commit_surfaces_to_stream( +bool dc_commit_planes_to_stream( struct dc *dc, - struct dc_plane_state **new_surfaces, - uint8_t new_surface_count, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; @@ -1162,37 +1162,37 @@ bool dc_commit_surfaces_to_stream( stream_update->dst = dc_stream->dst; stream_update->out_transfer_func = dc_stream->out_transfer_func; - for (i = 0; i < new_surface_count; i++) { - updates[i].surface = new_surfaces[i]; + for (i = 0; i < new_plane_count; i++) { + updates[i].surface = plane_states[i]; updates[i].gamma = - (struct dc_gamma *)new_surfaces[i]->gamma_correction; - updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func; - flip_addr[i].address = new_surfaces[i]->address; - flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate; - plane_info[i].color_space = new_surfaces[i]->color_space; - plane_info[i].format = new_surfaces[i]->format; - plane_info[i].plane_size = new_surfaces[i]->plane_size; - plane_info[i].rotation = new_surfaces[i]->rotation; - plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror; - plane_info[i].stereo_format = new_surfaces[i]->stereo_format; - plane_info[i].tiling_info = new_surfaces[i]->tiling_info; - plane_info[i].visible = new_surfaces[i]->visible; - plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha; - plane_info[i].dcc = new_surfaces[i]->dcc; - scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality; - scaling_info[i].src_rect = new_surfaces[i]->src_rect; - scaling_info[i].dst_rect = new_surfaces[i]->dst_rect; - scaling_info[i].clip_rect = new_surfaces[i]->clip_rect; + (struct dc_gamma *)plane_states[i]->gamma_correction; + updates[i].in_transfer_func = plane_states[i]->in_transfer_func; + flip_addr[i].address = plane_states[i]->address; + flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; + plane_info[i].color_space = plane_states[i]->color_space; + plane_info[i].format = plane_states[i]->format; + plane_info[i].plane_size = plane_states[i]->plane_size; + plane_info[i].rotation = plane_states[i]->rotation; + plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; + plane_info[i].stereo_format = plane_states[i]->stereo_format; + plane_info[i].tiling_info = plane_states[i]->tiling_info; + plane_info[i].visible = plane_states[i]->visible; + plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; + plane_info[i].dcc = plane_states[i]->dcc; + scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; + scaling_info[i].src_rect = plane_states[i]->src_rect; + scaling_info[i].dst_rect = plane_states[i]->dst_rect; + scaling_info[i].clip_rect = plane_states[i]->clip_rect; updates[i].flip_addr = &flip_addr[i]; updates[i].plane_info = &plane_info[i]; updates[i].scaling_info = &scaling_info[i]; } - dc_update_surfaces_and_stream( + dc_update_planes_and_stream( dc, updates, - new_surface_count, + new_plane_count, dc_stream, stream_update); dc_post_update_surfaces_to_stream(dc); @@ -1220,14 +1220,14 @@ void dc_release_validate_context(struct validate_context *context) static bool is_surface_in_context( const struct validate_context *context, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { int j; for (j = 0; j < MAX_PIPES; j++) { const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (surface == pipe_ctx->surface) { + if (plane_state == pipe_ctx->plane_state) { return true; } } @@ -1371,7 +1371,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; - if (stream_status == NULL || stream_status->surface_count != surface_count) + if (stream_status == NULL || stream_status->plane_count != surface_count) return UPDATE_TYPE_FULL; if (stream_update) @@ -1393,7 +1393,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; -void dc_update_surfaces_and_stream(struct dc *dc, +void dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update) @@ -1470,10 +1470,10 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - struct dc_plane_state *new_surfaces[MAX_SURFACES] = {0}; + struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) - new_surfaces[i] = srf_updates[i].surface; + new_planes[i] = srf_updates[i].surface; /* initialize scratch memory for building context */ context = dm_alloc(sizeof(*context)); @@ -1487,7 +1487,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, stream, + new_planes, surface_count, stream, context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; @@ -1542,7 +1542,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != surface) continue; resource_build_scaling_params(pipe_ctx); @@ -1599,14 +1599,14 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; + struct dc_plane_state *plane_state = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface) + if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) continue; - if (!pipe_ctx->surface || pipe_ctx->top_pipe) + if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; core_dc->hwss.pipe_control_lock( @@ -1622,15 +1622,15 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; - bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface; + bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; - if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface) + if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; if (!pipe_ctx->top_pipe) core_dc->hwss.apply_ctx_for_surface( - core_dc, pipe_ctx->surface, context); + core_dc, pipe_ctx->plane_state, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ dc_stream_set_cursor_position(pipe_ctx->stream, &position); @@ -1638,7 +1638,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (is_new_pipe_surface) { core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); core_dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->surface); + pipe_ctx, pipe_ctx->plane_state); core_dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } @@ -1649,16 +1649,16 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; + struct dc_plane_state *plane_state = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( - core_dc, surface, context); + core_dc, plane_state, context); for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; if (srf_updates[i].flip_addr) @@ -1669,7 +1669,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (srf_updates[i].in_transfer_func) core_dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->surface); + pipe_ctx, pipe_ctx->plane_state); if (stream_update != NULL && stream_update->out_transfer_func != NULL) { @@ -1690,9 +1690,9 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < surface_count; j++) { if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != pipe_ctx->surface) + srf_updates[j].surface != pipe_ctx->plane_state) continue; - if (!pipe_ctx->surface || pipe_ctx->top_pipe) + if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; core_dc->hwss.pipe_control_lock( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index e8d4b8c3ac2b..ca4f1db4a58a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -38,7 +38,7 @@ void pre_surface_trace( const struct dc *dc, - const struct dc_plane_state *const *surfaces, + const struct dc_plane_state *const *plane_states, int surface_count) { int i; @@ -46,111 +46,111 @@ void pre_surface_trace( struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { - const struct dc_plane_state *surface = surfaces[i]; + const struct dc_plane_state *plane_state = plane_states[i]; - SURFACE_TRACE("Surface %d:\n", i); + SURFACE_TRACE("Planes %d:\n", i); SURFACE_TRACE( - "surface->visible = %d;\n" - "surface->flip_immediate = %d;\n" - "surface->address.type = %d;\n" - "surface->address.grph.addr.quad_part = 0x%X;\n" - "surface->address.grph.meta_addr.quad_part = 0x%X;\n" - "surface->scaling_quality.h_taps = %d;\n" - "surface->scaling_quality.v_taps = %d;\n" - "surface->scaling_quality.h_taps_c = %d;\n" - "surface->scaling_quality.v_taps_c = %d;\n", - surface->visible, - surface->flip_immediate, - surface->address.type, - surface->address.grph.addr.quad_part, - surface->address.grph.meta_addr.quad_part, - surface->scaling_quality.h_taps, - surface->scaling_quality.v_taps, - surface->scaling_quality.h_taps_c, - surface->scaling_quality.v_taps_c); + "plane_state->visible = %d;\n" + "plane_state->flip_immediate = %d;\n" + "plane_state->address.type = %d;\n" + "plane_state->address.grph.addr.quad_part = 0x%X;\n" + "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n" + "plane_state->scaling_quality.h_taps = %d;\n" + "plane_state->scaling_quality.v_taps = %d;\n" + "plane_state->scaling_quality.h_taps_c = %d;\n" + "plane_state->scaling_quality.v_taps_c = %d;\n", + plane_state->visible, + plane_state->flip_immediate, + plane_state->address.type, + plane_state->address.grph.addr.quad_part, + plane_state->address.grph.meta_addr.quad_part, + plane_state->scaling_quality.h_taps, + plane_state->scaling_quality.v_taps, + plane_state->scaling_quality.h_taps_c, + plane_state->scaling_quality.v_taps_c); SURFACE_TRACE( - "surface->src_rect.x = %d;\n" - "surface->src_rect.y = %d;\n" - "surface->src_rect.width = %d;\n" - "surface->src_rect.height = %d;\n" - "surface->dst_rect.x = %d;\n" - "surface->dst_rect.y = %d;\n" - "surface->dst_rect.width = %d;\n" - "surface->dst_rect.height = %d;\n" - "surface->clip_rect.x = %d;\n" - "surface->clip_rect.y = %d;\n" - "surface->clip_rect.width = %d;\n" - "surface->clip_rect.height = %d;\n", - surface->src_rect.x, - surface->src_rect.y, - surface->src_rect.width, - surface->src_rect.height, - surface->dst_rect.x, - surface->dst_rect.y, - surface->dst_rect.width, - surface->dst_rect.height, - surface->clip_rect.x, - surface->clip_rect.y, - surface->clip_rect.width, - surface->clip_rect.height); + "plane_state->src_rect.x = %d;\n" + "plane_state->src_rect.y = %d;\n" + "plane_state->src_rect.width = %d;\n" + "plane_state->src_rect.height = %d;\n" + "plane_state->dst_rect.x = %d;\n" + "plane_state->dst_rect.y = %d;\n" + "plane_state->dst_rect.width = %d;\n" + "plane_state->dst_rect.height = %d;\n" + "plane_state->clip_rect.x = %d;\n" + "plane_state->clip_rect.y = %d;\n" + "plane_state->clip_rect.width = %d;\n" + "plane_state->clip_rect.height = %d;\n", + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->src_rect.width, + plane_state->src_rect.height, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->dst_rect.width, + plane_state->dst_rect.height, + plane_state->clip_rect.x, + plane_state->clip_rect.y, + plane_state->clip_rect.width, + plane_state->clip_rect.height); SURFACE_TRACE( - "surface->plane_size.grph.surface_size.x = %d;\n" - "surface->plane_size.grph.surface_size.y = %d;\n" - "surface->plane_size.grph.surface_size.width = %d;\n" - "surface->plane_size.grph.surface_size.height = %d;\n" - "surface->plane_size.grph.surface_pitch = %d;\n", - surface->plane_size.grph.surface_size.x, - surface->plane_size.grph.surface_size.y, - surface->plane_size.grph.surface_size.width, - surface->plane_size.grph.surface_size.height, - surface->plane_size.grph.surface_pitch); + "plane_state->plane_size.grph.surface_size.x = %d;\n" + "plane_state->plane_size.grph.surface_size.y = %d;\n" + "plane_state->plane_size.grph.surface_size.width = %d;\n" + "plane_state->plane_size.grph.surface_size.height = %d;\n" + "plane_state->plane_size.grph.surface_pitch = %d;\n", + plane_state->plane_size.grph.surface_size.x, + plane_state->plane_size.grph.surface_size.y, + plane_state->plane_size.grph.surface_size.width, + plane_state->plane_size.grph.surface_size.height, + plane_state->plane_size.grph.surface_pitch); SURFACE_TRACE( - "surface->tiling_info.gfx8.num_banks = %d;\n" - "surface->tiling_info.gfx8.bank_width = %d;\n" - "surface->tiling_info.gfx8.bank_width_c = %d;\n" - "surface->tiling_info.gfx8.bank_height = %d;\n" - "surface->tiling_info.gfx8.bank_height_c = %d;\n" - "surface->tiling_info.gfx8.tile_aspect = %d;\n" - "surface->tiling_info.gfx8.tile_aspect_c = %d;\n" - "surface->tiling_info.gfx8.tile_split = %d;\n" - "surface->tiling_info.gfx8.tile_split_c = %d;\n" - "surface->tiling_info.gfx8.tile_mode = %d;\n" - "surface->tiling_info.gfx8.tile_mode_c = %d;\n", - surface->tiling_info.gfx8.num_banks, - surface->tiling_info.gfx8.bank_width, - surface->tiling_info.gfx8.bank_width_c, - surface->tiling_info.gfx8.bank_height, - surface->tiling_info.gfx8.bank_height_c, - surface->tiling_info.gfx8.tile_aspect, - surface->tiling_info.gfx8.tile_aspect_c, - surface->tiling_info.gfx8.tile_split, - surface->tiling_info.gfx8.tile_split_c, - surface->tiling_info.gfx8.tile_mode, - surface->tiling_info.gfx8.tile_mode_c); + "plane_state->tiling_info.gfx8.num_banks = %d;\n" + "plane_state->tiling_info.gfx8.bank_width = %d;\n" + "plane_state->tiling_info.gfx8.bank_width_c = %d;\n" + "plane_state->tiling_info.gfx8.bank_height = %d;\n" + "plane_state->tiling_info.gfx8.bank_height_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_aspect = %d;\n" + "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_split = %d;\n" + "plane_state->tiling_info.gfx8.tile_split_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_mode = %d;\n" + "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n", + plane_state->tiling_info.gfx8.num_banks, + plane_state->tiling_info.gfx8.bank_width, + plane_state->tiling_info.gfx8.bank_width_c, + plane_state->tiling_info.gfx8.bank_height, + plane_state->tiling_info.gfx8.bank_height_c, + plane_state->tiling_info.gfx8.tile_aspect, + plane_state->tiling_info.gfx8.tile_aspect_c, + plane_state->tiling_info.gfx8.tile_split, + plane_state->tiling_info.gfx8.tile_split_c, + plane_state->tiling_info.gfx8.tile_mode, + plane_state->tiling_info.gfx8.tile_mode_c); SURFACE_TRACE( - "surface->tiling_info.gfx8.pipe_config = %d;\n" - "surface->tiling_info.gfx8.array_mode = %d;\n" - "surface->color_space = %d;\n" - "surface->dcc.enable = %d;\n" - "surface->format = %d;\n" - "surface->rotation = %d;\n" - "surface->stereo_format = %d;\n", - surface->tiling_info.gfx8.pipe_config, - surface->tiling_info.gfx8.array_mode, - surface->color_space, - surface->dcc.enable, - surface->format, - surface->rotation, - surface->stereo_format); - - SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", - surface->tiling_info.gfx9.swizzle); + "plane_state->tiling_info.gfx8.pipe_config = %d;\n" + "plane_state->tiling_info.gfx8.array_mode = %d;\n" + "plane_state->color_space = %d;\n" + "plane_state->dcc.enable = %d;\n" + "plane_state->format = %d;\n" + "plane_state->rotation = %d;\n" + "plane_state->stereo_format = %d;\n", + plane_state->tiling_info.gfx8.pipe_config, + plane_state->tiling_info.gfx8.array_mode, + plane_state->color_space, + plane_state->dcc.enable, + plane_state->format, + plane_state->rotation, + plane_state->stereo_format); + + SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n", + plane_state->tiling_info.gfx9.swizzle); SURFACE_TRACE("\n"); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ce0415f26600..4eef400cb551 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -430,17 +430,17 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; - struct rect surf_src = surface->src_rect; + struct rect surf_src = plane_state->src_rect; struct rect clip = { 0 }; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; bool pri_split = pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface; + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; bool sec_split = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface; + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { @@ -448,41 +448,41 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) sec_split = false; } - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); /* The actual clip is an intersection between stream * source and surface clip */ - clip.x = stream->src.x > surface->clip_rect.x ? - stream->src.x : surface->clip_rect.x; + clip.x = stream->src.x > plane_state->clip_rect.x ? + stream->src.x : plane_state->clip_rect.x; clip.width = stream->src.x + stream->src.width < - surface->clip_rect.x + surface->clip_rect.width ? + plane_state->clip_rect.x + plane_state->clip_rect.width ? stream->src.x + stream->src.width - clip.x : - surface->clip_rect.x + surface->clip_rect.width - clip.x ; + plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; - clip.y = stream->src.y > surface->clip_rect.y ? - stream->src.y : surface->clip_rect.y; + clip.y = stream->src.y > plane_state->clip_rect.y ? + stream->src.y : plane_state->clip_rect.y; clip.height = stream->src.y + stream->src.height < - surface->clip_rect.y + surface->clip_rect.height ? + plane_state->clip_rect.y + plane_state->clip_rect.height ? stream->src.y + stream->src.height - clip.y : - surface->clip_rect.y + surface->clip_rect.height - clip.y ; + plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio * num_pixels = clip.num_pix * scl_ratio */ - data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) * - surf_src.width / surface->dst_rect.width; + data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) * + surf_src.width / plane_state->dst_rect.width; data->viewport.width = clip.width * - surf_src.width / surface->dst_rect.width; + surf_src.width / plane_state->dst_rect.width; - data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) * - surf_src.height / surface->dst_rect.height; + data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) * + surf_src.height / plane_state->dst_rect.height; data->viewport.height = clip.height * - surf_src.height / surface->dst_rect.height; + surf_src.height / plane_state->dst_rect.height; /* Round down, compensate in init */ data->viewport_c.x = data->viewport.x / vpc_div; @@ -498,13 +498,13 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) /* Handle hsplit */ if (pri_split || sec_split) { /* HMirror XOR Secondary_pipe XOR Rotation_180 */ - bool right_view = (sec_split != surface->horizontal_mirror) != - (surface->rotation == ROTATION_ANGLE_180); + bool right_view = (sec_split != plane_state->horizontal_mirror) != + (plane_state->rotation == ROTATION_ANGLE_180); - if (surface->rotation == ROTATION_ANGLE_90 - || surface->rotation == ROTATION_ANGLE_270) + if (plane_state->rotation == ROTATION_ANGLE_90 + || plane_state->rotation == ROTATION_ANGLE_270) /* Secondary_pipe XOR Rotation_270 */ - right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split; + right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; if (right_view) { data->viewport.width /= 2; @@ -520,8 +520,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) } } - if (surface->rotation == ROTATION_ANGLE_90 || - surface->rotation == ROTATION_ANGLE_270) { + if (plane_state->rotation == ROTATION_ANGLE_90 || + plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -529,14 +529,14 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct rect surf_src = surface->src_rect; - struct rect surf_clip = surface->clip_rect; + struct rect surf_src = plane_state->src_rect; + struct rect surf_clip = plane_state->clip_rect; int recout_full_x, recout_full_y; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.recout.x = stream->dst.x; @@ -568,8 +568,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip - pipe_ctx->scl_data.recout.y; /* Handle h & vsplit */ - if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == - pipe_ctx->surface) { + if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == + pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; @@ -581,7 +581,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2; } } else if (pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else @@ -592,13 +592,13 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) */ - recout_full_x = stream->dst.x + (surface->dst_rect.x - stream->src.x) + recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) * stream->dst.width / stream->src.width - - surf_src.x * surface->dst_rect.width / surf_src.width + surf_src.x * plane_state->dst_rect.width / surf_src.width * stream->dst.width / stream->src.width; - recout_full_y = stream->dst.y + (surface->dst_rect.y - stream->src.y) + recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) * stream->dst.height / stream->src.height - - surf_src.y * surface->dst_rect.height / surf_src.height + surf_src.y * plane_state->dst_rect.height / surf_src.height * stream->dst.height / stream->src.height; recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; @@ -607,24 +607,24 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct rect surf_src = surface->src_rect; + struct rect surf_src = plane_state->src_rect; const int in_w = stream->src.width; const int in_h = stream->src.height; const int out_w = stream->dst.width; const int out_h = stream->dst.height; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction( surf_src.width, - surface->dst_rect.width); + plane_state->dst_rect.width); pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction( surf_src.height, - surface->dst_rect.height); + plane_state->dst_rect.height); if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; @@ -649,13 +649,13 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { struct scaler_data *data = &pipe_ctx->scl_data; - struct rect src = pipe_ctx->surface->src_rect; + struct rect src = pipe_ctx->plane_state->src_rect; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&src); rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); @@ -805,8 +805,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -814,7 +814,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -824,7 +824,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * Inits require viewport, taps, ratios and recout of split pipe */ pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( - pipe_ctx->surface->format); + pipe_ctx->plane_state->format); calculate_scaling_ratios(pipe_ctx); @@ -846,14 +846,14 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) /* Taps calculations */ res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); if (!res) { /* Try 24 bpp linebuffer */ pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); } if (res) @@ -869,10 +869,10 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->scl_data.viewport.width, pipe_ctx->scl_data.viewport.x, pipe_ctx->scl_data.viewport.y, - surface->dst_rect.height, - surface->dst_rect.width, - surface->dst_rect.x, - surface->dst_rect.y); + plane_state->dst_rect.height, + plane_state->dst_rect.width, + plane_state->dst_rect.x, + plane_state->dst_rect.y); return res; } @@ -885,7 +885,7 @@ enum dc_status resource_build_scaling_params_for_context( int i; for (i = 0; i < MAX_PIPES; i++) { - if (context->res_ctx.pipe_ctx[i].surface != NULL && + if (context->res_ctx.pipe_ctx[i].plane_state != NULL && context->res_ctx.pipe_ctx[i].stream != NULL) if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) return DC_FAIL_SCALING; @@ -954,13 +954,13 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( if (!head_pipe) ASSERT(0); - if (!head_pipe->surface) + if (!head_pipe->plane_state) return head_pipe; /* Re-use pipe already acquired for this stream if available*/ for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && - !res_ctx->pipe_ctx[i].surface) { + !res_ctx->pipe_ctx[i].plane_state) { return &res_ctx->pipe_ctx[i]; } } @@ -987,7 +987,7 @@ static void release_free_pipes_for_stream( /* never release the topmost pipe*/ if (res_ctx->pipe_ctx[i].stream == stream && res_ctx->pipe_ctx[i].top_pipe && - !res_ctx->pipe_ctx[i].surface) { + !res_ctx->pipe_ctx[i].plane_state) { memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx)); } } @@ -1005,7 +1005,7 @@ static int acquire_first_split_pipe( struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface) { + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) { pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; if (pipe_ctx->bottom_pipe) pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; @@ -1028,7 +1028,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - struct dc_plane_state * const *surfaces, + struct dc_plane_state * const *plane_states, int surface_count, struct dc_stream_state *stream, struct validate_context *context, @@ -1057,25 +1057,25 @@ bool resource_attach_surfaces_to_context( /* retain new surfaces */ for (i = 0; i < surface_count; i++) - dc_surface_retain(surfaces[i]); + dc_plane_state_retain(plane_states[i]); /* detach surfaces from pipes */ for (i = 0; i < pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == stream) { - context->res_ctx.pipe_ctx[i].surface = NULL; + context->res_ctx.pipe_ctx[i].plane_state = NULL; context->res_ctx.pipe_ctx[i].bottom_pipe = NULL; } /* release existing surfaces*/ - for (i = 0; i < stream_status->surface_count; i++) - dc_surface_release(stream_status->surfaces[i]); + for (i = 0; i < stream_status->plane_count; i++) + dc_plane_state_release(stream_status->plane_states[i]); - for (i = surface_count; i < stream_status->surface_count; i++) - stream_status->surfaces[i] = NULL; + for (i = surface_count; i < stream_status->plane_count; i++) + stream_status->plane_states[i] = NULL; tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = surfaces[i]; + struct dc_plane_state *plane_state = plane_states[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, stream); @@ -1087,11 +1087,11 @@ bool resource_attach_surfaces_to_context( } #endif if (!free_pipe) { - stream_status->surfaces[i] = NULL; + stream_status->plane_states[i] = NULL; return false; } - free_pipe->surface = surface; + free_pipe->plane_state = plane_state; if (tail_pipe) { free_pipe->tg = tail_pipe->tg; @@ -1110,9 +1110,9 @@ bool resource_attach_surfaces_to_context( /* assign new surfaces*/ for (i = 0; i < surface_count; i++) - stream_status->surfaces[i] = surfaces[i]; + stream_status->plane_states[i] = plane_states[i]; - stream_status->surface_count = surface_count; + stream_status->plane_count = surface_count; return true; } @@ -1180,17 +1180,17 @@ bool resource_validate_attach_surfaces( old_context->streams[j], context->streams[i])) { if (!resource_attach_surfaces_to_context( - old_context->stream_status[j].surfaces, - old_context->stream_status[j].surface_count, + old_context->stream_status[j].plane_states, + old_context->stream_status[j].plane_count, context->streams[i], context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; } - if (set[i].surface_count != 0) + if (set[i].plane_count != 0) if (!resource_attach_surfaces_to_context( - set[i].surfaces, - set[i].surface_count, + set[i].plane_states, + set[i].plane_count, context->streams[i], context, pool)) return false; @@ -1351,13 +1351,13 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct dc_plane_state *surface = to_pipe_ctx->surface; + struct dc_plane_state *plane_state = to_pipe_ctx->plane_state; struct dc_stream_state *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; - if (surface != NULL) - to_pipe_ctx->surface = surface; + if (plane_state != NULL) + to_pipe_ctx->plane_state = plane_state; } static struct dc_stream_state *find_pll_sharable_stream( @@ -2055,7 +2055,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_plane_state *surface, + struct dc_plane_state *plane_state, struct dc_stream_state *stream) { uint16_t i = 0; @@ -2063,10 +2063,10 @@ static void set_hdr_static_info_packet( struct dc_hdr_static_metadata hdr_metadata; uint32_t data; - if (!surface) + if (!plane_state) return; - hdr_metadata = surface->hdr_static_ctx; + hdr_metadata = plane_state->hdr_static_ctx; if (!hdr_metadata.hdr_supported) return; @@ -2204,11 +2204,11 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) int i, j; for (i = 0; i < context->stream_count; i++) { - for (j = 0; j < context->stream_status[i].surface_count; j++) - dc_surface_release( - context->stream_status[i].surfaces[j]); + for (j = 0; j < context->stream_status[i].plane_count; j++) + dc_plane_state_release( + context->stream_status[i].plane_states[j]); - context->stream_status[i].surface_count = 0; + context->stream_status[i].plane_count = 0; dc_stream_release(context->streams[i]); context->streams[i] = NULL; } @@ -2240,9 +2240,9 @@ void dc_resource_validate_ctx_copy_construct( for (i = 0; i < dst_ctx->stream_count; i++) { dc_stream_retain(dst_ctx->streams[i]); - for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) - dc_surface_retain( - dst_ctx->stream_status[i].surfaces[j]); + for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) + dc_plane_state_retain( + dst_ctx->stream_status[i].plane_states[j]); } /* context refcount should not be overridden */ @@ -2288,7 +2288,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->surface, pipe_ctx->stream); + pipe_ctx->plane_state, pipe_ctx->stream); } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(&info->vsc, pipe_ctx->stream); @@ -2296,7 +2296,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->surface, pipe_ctx->stream); + pipe_ctx->plane_state, pipe_ctx->stream); } patch_gamut_packet_checksum(&info->gamut); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 7a87f38f2324..2b6506822cca 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -185,7 +185,7 @@ bool dc_stream_set_cursor_attributes( if (pipe_ctx->stream != stream || !pipe_ctx->ipp) continue; - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) continue; pipe_ctx->ipp->funcs->ipp_cursor_set_attributes( @@ -229,14 +229,14 @@ bool dc_stream_set_cursor_position( }; if (pipe_ctx->stream != stream || - !pipe_ctx->ipp || !pipe_ctx->surface) + !pipe_ctx->ipp || !pipe_ctx->plane_state) continue; - if (pipe_ctx->surface->address.type + if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) pos_cpy.enable = false; - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) pos_cpy.enable = false; ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 941b3671375d..3bcca2d1872b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -34,75 +34,75 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct dc_plane_state *surface) +static bool construct(struct dc_context *ctx, struct dc_plane_state *plane_state) { - surface->ctx = ctx; - memset(&surface->hdr_static_ctx, + plane_state->ctx = ctx; + memset(&plane_state->hdr_static_ctx, 0, sizeof(struct dc_hdr_static_metadata)); return true; } -static void destruct(struct dc_plane_state *surface) +static void destruct(struct dc_plane_state *plane_state) { - if (surface->gamma_correction != NULL) { - dc_gamma_release(&surface->gamma_correction); + if (plane_state->gamma_correction != NULL) { + dc_gamma_release(&plane_state->gamma_correction); } - if (surface->in_transfer_func != NULL) { + if (plane_state->in_transfer_func != NULL) { dc_transfer_func_release( - surface->in_transfer_func); - surface->in_transfer_func = NULL; + plane_state->in_transfer_func); + plane_state->in_transfer_func = NULL; } } /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_plane_state *surface, +void enable_surface_flip_reporting(struct dc_plane_state *plane_state, uint32_t controller_id) { - surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; + plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } -struct dc_plane_state *dc_create_surface(const struct dc *dc) +struct dc_plane_state *dc_create_plane_state(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_plane_state *surface = dm_alloc(sizeof(*surface)); + struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); - if (NULL == surface) + if (NULL == plane_state) goto alloc_fail; - if (false == construct(core_dc->ctx, surface)) + if (false == construct(core_dc->ctx, plane_state)) goto construct_fail; - ++surface->ref_count; + ++plane_state->ref_count; - return surface; + return plane_state; construct_fail: - dm_free(surface); + dm_free(plane_state); alloc_fail: return NULL; } -const struct dc_surface_status *dc_surface_get_status( - const struct dc_plane_state *dc_surface) +const struct dc_plane_status *dc_plane_get_status( + const struct dc_plane_state *plane_state) { - const struct dc_surface_status *surface_status; + const struct dc_plane_status *plane_status; struct core_dc *core_dc; int i; - if (!dc_surface || - !dc_surface->ctx || - !dc_surface->ctx->dc) { + if (!plane_state || + !plane_state->ctx || + !plane_state->ctx->dc) { ASSERT(0); return NULL; /* remove this if above assert never hit */ } - surface_status = &dc_surface->status; - core_dc = DC_TO_CORE(dc_surface->ctx->dc); + plane_status = &plane_state->status; + core_dc = DC_TO_CORE(plane_state->ctx->dc); if (core_dc->current_context == NULL) return NULL; @@ -111,29 +111,29 @@ const struct dc_surface_status *dc_surface_get_status( struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != dc_surface) + if (pipe_ctx->plane_state != plane_state) continue; core_dc->hwss.update_pending_status(pipe_ctx); } - return surface_status; + return plane_status; } -void dc_surface_retain(struct dc_plane_state *surface) +void dc_plane_state_retain(struct dc_plane_state *plane_state) { - ASSERT(surface->ref_count > 0); - ++surface->ref_count; + ASSERT(plane_state->ref_count > 0); + ++plane_state->ref_count; } -void dc_surface_release(struct dc_plane_state *surface) +void dc_plane_state_release(struct dc_plane_state *plane_state) { - ASSERT(surface->ref_count > 0); - --surface->ref_count; + ASSERT(plane_state->ref_count > 0); + --plane_state->ref_count; - if (surface->ref_count == 0) { - destruct(surface); - dm_free(surface); + if (plane_state->ref_count == 0) { + destruct(plane_state); + dm_free(plane_state); } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ab805965e321..d1a6398043a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct dc_caps { uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; - uint32_t max_surfaces; + uint32_t max_planes; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; @@ -303,7 +303,7 @@ struct dc_transfer_func { * the last requested address and the currently active address so the called * can determine if there are any outstanding flips */ -struct dc_surface_status { +struct dc_plane_status { struct dc_plane_address requested_address; struct dc_plane_address current_address; bool is_flip_pending; @@ -338,7 +338,7 @@ struct dc_plane_state { bool horizontal_mirror; /* private to DC core */ - struct dc_surface_status status; + struct dc_plane_status status; struct dc_context *ctx; /* private to dc_surface.c */ @@ -385,12 +385,12 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_plane_state *dc_create_surface(const struct dc *dc); -const struct dc_surface_status *dc_surface_get_status( - const struct dc_plane_state *dc_surface); +struct dc_plane_state *dc_create_plane_state(const struct dc *dc); +const struct dc_plane_status *dc_plane_get_status( + const struct dc_plane_state *plane_state); -void dc_surface_retain(struct dc_plane_state *dc_surface); -void dc_surface_release(struct dc_plane_state *dc_surface); +void dc_plane_state_retain(struct dc_plane_state *plane_state); +void dc_plane_state_release(struct dc_plane_state *plane_state); void dc_gamma_retain(struct dc_gamma *dc_gamma); void dc_gamma_release(struct dc_gamma **dc_gamma); @@ -422,10 +422,10 @@ struct dc_flip_addrs { * This does not trigger a flip. No surface address is programmed. */ -bool dc_commit_surfaces_to_stream( +bool dc_commit_planes_to_stream( struct dc *dc, - struct dc_plane_state **dc_surfaces, - uint8_t surface_count, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *stream); bool dc_post_update_surfaces_to_stream( @@ -469,8 +469,8 @@ enum surface_update_type { struct dc_stream_status { int primary_otg_inst; - int surface_count; - struct dc_plane_state *surfaces[MAX_SURFACE_NUM]; + int plane_count; + struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -546,7 +546,7 @@ bool dc_is_stream_unchanged( * */ -void dc_update_surfaces_and_stream(struct dc *dc, +void dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); @@ -582,8 +582,8 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, */ struct dc_validation_set { struct dc_stream_state *stream; - struct dc_plane_state *surfaces[MAX_SURFACES]; - uint8_t surface_count; + struct dc_plane_state *plane_states[MAX_SURFACES]; + uint8_t plane_count; }; bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index af59ab93796a..8140ff31c3bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -197,9 +197,9 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct dc_plane_state *surface) +bool dce_use_lut(const struct dc_plane_state *plane_state) { - switch (surface->format) { + switch (plane_state->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index d5cb98a92c53..a0531b3aa6a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct dc_plane_state *surface); +bool dce_use_lut(const struct dc_plane_state *plane_state); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 98fb7f02a6fe..46f0c71fbac4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -705,13 +705,13 @@ static bool dce100_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -958,7 +958,7 @@ static bool construct( } } - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e4310a376116..ea9ce87d348a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,11 +215,11 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; - switch (surface->format) { + switch (plane_state->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: prescale_params->scale = 0x2020; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -250,14 +250,14 @@ static bool dce110_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->in_transfer_func) - tf = surface->in_transfer_func; + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; - build_prescale_params(&prescale_params, surface); + build_prescale_params(&prescale_params, plane_state); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - if (surface->gamma_correction && dce_use_lut(surface)) - ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction); + if (plane_state->gamma_correction && dce_use_lut(plane_state)) + ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); if (tf == NULL) { /* Default case if no input transfer function specified */ @@ -1119,7 +1119,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( if ((!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, sizeof(struct scaler_data)) != 0) && - pipe_ctx->surface) { + pipe_ctx->plane_state) { program_scaler(dc, pipe_ctx); } @@ -1916,11 +1916,11 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) struct default_adjustment default_adjust = { 0 }; default_adjust.force_hw_default = false; - if (pipe_ctx->surface == NULL) + if (pipe_ctx->plane_state == NULL) default_adjust.in_color_space = COLOR_SPACE_SRGB; else default_adjust.in_color_space = - pipe_ctx->surface->color_space; + pipe_ctx->plane_state->color_space; if (pipe_ctx->stream == NULL) default_adjust.out_color_space = COLOR_SPACE_SRGB; else @@ -1971,16 +1971,16 @@ static void program_surface_visibility(const struct core_dc *dc, /* For now we are supporting only two pipes */ ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); - if (pipe_ctx->bottom_pipe->surface->visible) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->bottom_pipe->plane_state->visible) { + if (pipe_ctx->plane_state->visible) blender_mode = BLND_MODE_BLENDING; else blender_mode = BLND_MODE_OTHER_PIPE; - } else if (!pipe_ctx->surface->visible) + } else if (!pipe_ctx->plane_state->visible) blank_target = true; - } else if (!pipe_ctx->surface->visible) + } else if (!pipe_ctx->plane_state->visible) blank_target = true; dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); @@ -2038,7 +2038,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2103,57 +2103,57 @@ static void set_plane_config( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, - &surface->plane_size, - surface->rotation, + plane_state->format, + &plane_state->tiling_info, + &plane_state->plane_size, + plane_state->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->visible); + mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); } static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->address, - surface->flip_immediate); + &plane_state->address, + plane_state->flip_immediate); - surface->status.requested_address = surface->address; + plane_state->status.requested_address = plane_state->address; } void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; - surface->status.is_flip_pending = + plane_state->status.is_flip_pending = pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); - if (surface->status.is_flip_pending && !surface->visible) + if (plane_state->status.is_flip_pending && !plane_state->visible) pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; - surface->status.current_address = pipe_ctx->mi->current_address; + plane_state->status.current_address = pipe_ctx->mi->current_address; if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && pipe_ctx->tg->funcs->is_stereo_left_eye) { - surface->status.is_right_eye =\ + plane_state->status.is_right_eye =\ !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); } } @@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2558,21 +2558,21 @@ static void dce110_program_front_end_for_pipe( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, - &surface->plane_size, - surface->rotation, + plane_state->format, + &plane_state->tiling_info, + &plane_state->plane_size, + plane_state->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->visible); + mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe:%d 0x%x: addr hi:0x%x, " @@ -2581,21 +2581,21 @@ static void dce110_program_front_end_for_pipe( " %d; dst: %d, %d, %d, %d;" "clip: %d, %d, %d, %d\n", pipe_ctx->pipe_idx, - pipe_ctx->surface, - pipe_ctx->surface->address.grph.addr.high_part, - pipe_ctx->surface->address.grph.addr.low_part, - pipe_ctx->surface->src_rect.x, - pipe_ctx->surface->src_rect.y, - pipe_ctx->surface->src_rect.width, - pipe_ctx->surface->src_rect.height, - pipe_ctx->surface->dst_rect.x, - pipe_ctx->surface->dst_rect.y, - pipe_ctx->surface->dst_rect.width, - pipe_ctx->surface->dst_rect.height, - pipe_ctx->surface->clip_rect.x, - pipe_ctx->surface->clip_rect.y, - pipe_ctx->surface->clip_rect.width, - pipe_ctx->surface->clip_rect.height); + pipe_ctx->plane_state, + pipe_ctx->plane_state->address.grph.addr.high_part, + pipe_ctx->plane_state->address.grph.addr.low_part, + pipe_ctx->plane_state->src_rect.x, + pipe_ctx->plane_state->src_rect.y, + pipe_ctx->plane_state->src_rect.width, + pipe_ctx->plane_state->src_rect.height, + pipe_ctx->plane_state->dst_rect.x, + pipe_ctx->plane_state->dst_rect.y, + pipe_ctx->plane_state->dst_rect.width, + pipe_ctx->plane_state->dst_rect.height, + pipe_ctx->plane_state->clip_rect.x, + pipe_ctx->plane_state->clip_rect.y, + pipe_ctx->plane_state->clip_rect.width, + pipe_ctx->plane_state->clip_rect.height); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe %d: width, height, x, y\n" @@ -2614,19 +2614,18 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context) { int i; - /* TODO remove when removing the surface reset workaroud*/ - if (!surface) + if (!plane_state) return; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; dce110_program_front_end_for_pipe(dc, pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 89b21bd57a35..f580da1b3249 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -764,9 +764,9 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne { if (pipe_ctx->pipe_idx != underlay_idx) return true; - if (!pipe_ctx->surface) + if (!pipe_ctx->plane_state) return false; - if (pipe_ctx->surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; return true; } @@ -901,22 +901,22 @@ static bool dce110_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 2) + if (set[i].plane_count > 2) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].surface_count == 2) { - if (set[i].surfaces[1]->format + if (set[i].plane_count == 2) { + if (set[i].plane_states[1]->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].surfaces[1]->src_rect.width > 1920 - || set[i].surfaces[1]->src_rect.height > 1080) + if (set[i].plane_states[1]->src_rect.width > 1920 + || set[i].plane_states[1]->src_rect.height > 1080) return false; if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) @@ -1351,7 +1351,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 68554d6edd94..420434d7283e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -889,13 +889,13 @@ static bool dce112_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -1319,7 +1319,7 @@ static bool construct( &res_create_funcs)) goto res_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 45f5fd63ce14..6448d15c02f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -982,7 +982,7 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 734b35eddeed..7473f58584c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -722,13 +722,13 @@ static bool dce80_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -959,7 +959,7 @@ static bool construct( } } - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 866f63d1259d..5922cf8272f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -986,7 +986,7 @@ static void reset_hw_ctx_wrap( struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx->stream || - !pipe_ctx->surface || + !pipe_ctx->plane_state || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { plane_atomic_disconnect(dc, i); @@ -1010,13 +1010,13 @@ static void reset_hw_ctx_wrap( /*if (!pipe_ctx_old->stream) continue;*/ - if (pipe_ctx->stream && pipe_ctx->surface + if (pipe_ctx->stream && pipe_ctx->plane_state && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) continue; plane_atomic_disable(dc, i); - if (!pipe_ctx->stream || !pipe_ctx->surface) + if (!pipe_ctx->stream || !pipe_ctx->plane_state) plane_atomic_power_down(dc, i); } @@ -1038,24 +1038,24 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; bool sec_split = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface; - if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; + if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && (pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { - *addr = surface->address.grph_stereo.left_addr; - surface->address.grph_stereo.left_addr = - surface->address.grph_stereo.right_addr; + *addr = plane_state->address.grph_stereo.left_addr; + plane_state->address.grph_stereo.left_addr = + plane_state->address.grph_stereo.right_addr; return true; } else { if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && - surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { - surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; - surface->address.grph_stereo.right_addr = - surface->address.grph_stereo.left_addr; + plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { + plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; + plane_state->address.grph_stereo.right_addr = + plane_state->address.grph_stereo.left_addr; } } return false; @@ -1065,22 +1065,22 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->address, - surface->flip_immediate); - surface->status.requested_address = surface->address; + &plane_state->address, + plane_state->flip_immediate); + plane_state->status.requested_address = plane_state->address; if (addr_patched) - pipe_ctx->surface->address.grph_stereo.left_addr = addr; + pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_plane_state *surface) + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -1089,12 +1089,12 @@ static bool dcn10_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->in_transfer_func) - tf = surface->in_transfer_func; + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; - if (surface->gamma_correction && dce_use_lut(surface)) + if (plane_state->gamma_correction && dce_use_lut(plane_state)) ipp->funcs->ipp_program_input_lut(ipp, - surface->gamma_correction); + plane_state->gamma_correction); if (tf == NULL) ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); @@ -1689,7 +1689,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_plane_state *dc_surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1704,24 +1704,24 @@ static void dcn10_power_on_fe( OPP_PIPE_CLOCK_EN, 1); /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ - if (dc_surface) { + if (plane_state) { dm_logger_write(dc->ctx->logger, LOG_DC, "Pipe:%d 0x%x: addr hi:0x%x, " "addr low:0x%x, " "src: %d, %d, %d," " %d; dst: %d, %d, %d, %d;\n", pipe_ctx->pipe_idx, - dc_surface, - dc_surface->address.grph.addr.high_part, - dc_surface->address.grph.addr.low_part, - dc_surface->src_rect.x, - dc_surface->src_rect.y, - dc_surface->src_rect.width, - dc_surface->src_rect.height, - dc_surface->dst_rect.x, - dc_surface->dst_rect.y, - dc_surface->dst_rect.width, - dc_surface->dst_rect.height); + plane_state, + plane_state->address.grph.addr.high_part, + plane_state->address.grph.addr.low_part, + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->src_rect.width, + plane_state->src_rect.height, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->dst_rect.width, + plane_state->dst_rect.height); dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE, "Pipe %d: width, height, x, y\n" @@ -1805,7 +1805,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) return true; @@ -1814,7 +1814,7 @@ static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1823,7 +1823,7 @@ static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1898,12 +1898,12 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_plane_state *surface = pipe_ctx->surface; - union plane_size size = surface->plane_size; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + union plane_size size = plane_state->plane_size; struct default_adjustment ocsc = {0}; struct mpcc_cfg mpcc_cfg = {0}; struct pipe_ctx *top_pipe; - bool per_pixel_alpha = surface->per_pixel_alpha && pipe_ctx->bottom_pipe; + bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ /* depends on DML calculation, DPP clock value may change dynamically */ @@ -1936,12 +1936,12 @@ static void update_dchubp_dpp( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); ipp->funcs->ipp_setup(ipp, - surface->format, + plane_state->format, 1, IPP_OUTPUT_FORMAT_12_BIT_FIX); @@ -1982,12 +1982,12 @@ static void update_dchubp_dpp( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, + plane_state->format, + &plane_state->tiling_info, &size, - surface->rotation, - &surface->dcc, - surface->horizontal_mirror); + plane_state->rotation, + &plane_state->dcc, + plane_state->horizontal_mirror); mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx)); } @@ -2025,7 +2025,7 @@ static void program_all_pipe_in_tree( pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx)); } - if (pipe_ctx->surface != NULL) { + if (pipe_ctx->plane_state != NULL) { dcn10_power_on_fe(dc, pipe_ctx, context); update_dchubp_dpp(dc, pipe_ctx, context); } @@ -2068,7 +2068,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context) { int i, be_idx; @@ -2076,11 +2076,11 @@ static void dcn10_apply_ctx_for_surface( if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); - if (!surface) + if (!plane_state) return; for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++) - if (surface == context->res_ctx.pipe_ctx[be_idx].surface) + if (plane_state == context->res_ctx.pipe_ctx[be_idx].plane_state) break; /* reset unused mpcc */ @@ -2089,7 +2089,7 @@ static void dcn10_apply_ctx_for_surface( struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; - if (!pipe_ctx->surface && !old_pipe_ctx->surface) + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; /* @@ -2097,7 +2097,7 @@ static void dcn10_apply_ctx_for_surface( * fairly hacky right now, using opp_id as indicator */ - if (pipe_ctx->surface && !old_pipe_ctx->surface) { + if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { if (pipe_ctx->mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) { dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); /* @@ -2109,7 +2109,7 @@ static void dcn10_apply_ctx_for_surface( } - if ((!pipe_ctx->surface && old_pipe_ctx->surface) + if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) || (!pipe_ctx->stream && old_pipe_ctx->stream)) { if (old_pipe_ctx->tg->inst != be_idx) continue; @@ -2135,7 +2135,7 @@ static void dcn10_apply_ctx_for_surface( old_pipe_ctx->top_pipe = NULL; old_pipe_ctx->bottom_pipe = NULL; - old_pipe_ctx->surface = NULL; + old_pipe_ctx->plane_state = NULL; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset mpcc for pipe %d\n", @@ -2146,7 +2146,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; /* looking for top pipe to program */ @@ -2468,34 +2468,34 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct timing_generator *tg = pipe_ctx->tg; - if (surface->ctx->dc->debug.sanity_checks) { - struct core_dc *dc = DC_TO_CORE(surface->ctx->dc); + if (plane_state->ctx->dc->debug.sanity_checks) { + struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); verify_allow_pstate_change_high(dc->hwseq); } - if (surface == NULL) + if (plane_state == NULL) return; - surface->status.is_flip_pending = + plane_state->status.is_flip_pending = pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); /* DCN we read INUSE address in MI, do we still need this wa? */ - if (surface->status.is_flip_pending && - !surface->visible) { + if (plane_state->status.is_flip_pending && + !plane_state->visible) { pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; BREAK_TO_DEBUGGER(); } - surface->status.current_address = pipe_ctx->mi->current_address; + plane_state->status.current_address = pipe_ctx->mi->current_address; if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && tg->funcs->is_stereo_left_eye) { - surface->status.is_right_eye = + plane_state->status.is_right_eye = !tg->funcs->is_stereo_left_eye(pipe_ctx->tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 5a9fcbc22d04..3fe6df92f91f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1406,7 +1406,7 @@ static bool construct( goto res_create_fail; dcn10_hw_sequencer_construct(dc); - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; dc->public.cap_funcs = cap_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d5c0f9e34ce9..3b3330c563e0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,7 +36,7 @@ #define MAX_CLOCK_SOURCES 7 -void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, +void enable_surface_flip_reporting(struct dc_plane_state *plane_state, uint32_t controller_id); #include "grph_object_id.h" @@ -153,7 +153,7 @@ struct resource_pool { }; struct pipe_ctx { - struct dc_plane_state *surface; + struct dc_plane_state *plane_state; struct dc_stream_state *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 7e03f8d45b2b..5d075f93b4b9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *surface); + const struct dc_plane_state *plane_state); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index aef1197cf749..7f30d9937d10 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( struct dc_stream_state *stream); bool resource_attach_surfaces_to_context( - struct dc_plane_state *const *surfaces, + struct dc_plane_state *const *plane_state, int surface_count, struct dc_stream_state *dc_stream, struct validate_context *context, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 0e978d921fdf..beb790937769 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger, void pre_surface_trace( const struct dc *dc, - const struct dc_plane_state *const *surfaces, + const struct dc_plane_state *const *plane_states, int surface_count); void update_surface_trace( -- cgit v1.2.3-59-g8ed1b From 6702a9ac53f88a373a9969b4dee292f4c5f023f5 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 11:51:21 -0400 Subject: drm/amd/display: Move scl_data to plane_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.scl_data/\.plane_res.scl_data/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->scl_data/->plane_res.scl_data/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 36 ++++---- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 84 ++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 100 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 34 +++---- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 28 +++--- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 +- 7 files changed, 145 insertions(+), 147 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 28dbd18b2d86..dba25853f7f9 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2613,13 +2613,13 @@ static void populate_initial_data( data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); - data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); + data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; - data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); - data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.h_taps); - data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); - data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); - data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); + data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); + data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); + data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); + data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value); + data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); @@ -2667,16 +2667,16 @@ static void populate_initial_data( data->fbc_en[num_displays * 2 + j] = false; data->lpt_en[num_displays * 2 + j] = false; - data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.height); - data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.width); + data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height); + data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width); data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed( pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch); - data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.h_taps); - data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.v_taps); + data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps); + data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps); data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( - pipe[i].bottom_pipe->scl_data.ratios.horz.value); + pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value); data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( - pipe[i].bottom_pipe->scl_data.ratios.vert.value); + pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); switch (pipe[i].bottom_pipe->plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0); @@ -2711,13 +2711,13 @@ static void populate_initial_data( data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); if (pipe[i].plane_state) { - data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); + data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; - data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); - data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.h_taps); - data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); - data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); - data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); + data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); + data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); + data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); + data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value); + data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 404b39e7b44b..cb762006e1c3 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -244,10 +244,10 @@ static void pipe_ctx_to_e2e_pipe_params ( input->src.source_scan = dm_horz; input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; - input->src.viewport_width = pipe->scl_data.viewport.width; - input->src.viewport_height = pipe->scl_data.viewport.height; - input->src.data_pitch = pipe->scl_data.viewport.width; - input->src.data_pitch_c = pipe->scl_data.viewport.width; + input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; + input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; + input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; + input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ input->src.cur0_bpp = 32; @@ -341,21 +341,21 @@ static void pipe_ctx_to_e2e_pipe_params ( break; } - input->scale_taps.htaps = pipe->scl_data.taps.h_taps; - input->scale_ratio_depth.hscl_ratio = pipe->scl_data.ratios.horz.value/4294967296.0; - input->scale_ratio_depth.vscl_ratio = pipe->scl_data.ratios.vert.value/4294967296.0; - input->scale_ratio_depth.vinit = pipe->scl_data.inits.v.value/4294967296.0; + input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; + input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; + input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; + input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; if (input->scale_ratio_depth.vinit < 1.0) input->scale_ratio_depth.vinit = 1; - input->scale_taps.vtaps = pipe->scl_data.taps.v_taps; - input->scale_taps.vtaps_c = pipe->scl_data.taps.v_taps_c; - input->scale_taps.htaps_c = pipe->scl_data.taps.h_taps_c; - input->scale_ratio_depth.hscl_ratio_c = pipe->scl_data.ratios.horz_c.value/4294967296.0; - input->scale_ratio_depth.vscl_ratio_c = pipe->scl_data.ratios.vert_c.value/4294967296.0; - input->scale_ratio_depth.vinit_c = pipe->scl_data.inits.v_c.value/4294967296.0; + input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; + input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; + input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; + input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; + input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; + input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0; if (input->scale_ratio_depth.vinit_c < 1.0) input->scale_ratio_depth.vinit_c = 1; - switch (pipe->scl_data.lb_params.depth) { + switch (pipe->plane_res.scl_data.lb_params.depth) { case LB_PIXEL_DEPTH_30BPP: input->scale_ratio_depth.lb_depth = 30; break; case LB_PIXEL_DEPTH_36BPP: @@ -367,11 +367,11 @@ static void pipe_ctx_to_e2e_pipe_params ( input->dest.vactive = pipe->stream->timing.v_addressable; - input->dest.recout_width = pipe->scl_data.recout.width; - input->dest.recout_height = pipe->scl_data.recout.height; + input->dest.recout_width = pipe->plane_res.scl_data.recout.width; + input->dest.recout_height = pipe->plane_res.scl_data.recout.height; - input->dest.full_recout_width = pipe->scl_data.recout.width; - input->dest.full_recout_height = pipe->scl_data.recout.height; + input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width; + input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height; input->dest.htotal = pipe->stream->timing.h_total; input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; @@ -885,38 +885,38 @@ bool dcn_validate_bandwidth( v->source_scan[input_idx] = dcn_bw_hor; } else { - v->viewport_height[input_idx] = pipe->scl_data.viewport.height; - v->viewport_width[input_idx] = pipe->scl_data.viewport.width; - v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width; - v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height; + v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; + v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; + v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; + v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { if (pipe->plane_state->rotation % 2 == 0) { - int viewport_end = pipe->scl_data.viewport.width - + pipe->scl_data.viewport.x; - int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width - + pipe->bottom_pipe->scl_data.viewport.x; + int viewport_end = pipe->plane_res.scl_data.viewport.width + + pipe->plane_res.scl_data.viewport.x; + int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width + + pipe->bottom_pipe->plane_res.scl_data.viewport.x; if (viewport_end > viewport_b_end) v->viewport_width[input_idx] = viewport_end - - pipe->bottom_pipe->scl_data.viewport.x; + - pipe->bottom_pipe->plane_res.scl_data.viewport.x; else v->viewport_width[input_idx] = viewport_b_end - - pipe->scl_data.viewport.x; + - pipe->plane_res.scl_data.viewport.x; } else { - int viewport_end = pipe->scl_data.viewport.height - + pipe->scl_data.viewport.y; - int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.height - + pipe->bottom_pipe->scl_data.viewport.y; + int viewport_end = pipe->plane_res.scl_data.viewport.height + + pipe->plane_res.scl_data.viewport.y; + int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height + + pipe->bottom_pipe->plane_res.scl_data.viewport.y; if (viewport_end > viewport_b_end) v->viewport_height[input_idx] = viewport_end - - pipe->bottom_pipe->scl_data.viewport.y; + - pipe->bottom_pipe->plane_res.scl_data.viewport.y; else v->viewport_height[input_idx] = viewport_b_end - - pipe->scl_data.viewport.y; + - pipe->plane_res.scl_data.viewport.y; } - v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width - + pipe->bottom_pipe->scl_data.recout.width; + v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width + + pipe->bottom_pipe->plane_res.scl_data.recout.width; } v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; @@ -924,11 +924,11 @@ bool dcn_validate_bandwidth( pipe->plane_state->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( pipe->plane_state->tiling_info.gfx9.swizzle); - v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth); - v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps; - v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps; - v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c; - v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c; + v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); + v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; + v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; + v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; + v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4eef400cb551..84a15a999117 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -432,7 +432,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct scaler_data *data = &pipe_ctx->scl_data; + struct scaler_data *data = &pipe_ctx->plane_res.scl_data; struct rect surf_src = plane_state->src_rect; struct rect clip = { 0 }; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 @@ -539,53 +539,53 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); - pipe_ctx->scl_data.recout.x = stream->dst.x; + pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; if (stream->src.x < surf_clip.x) - pipe_ctx->scl_data.recout.x += (surf_clip.x + pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x - stream->src.x) * stream->dst.width / stream->src.width; - pipe_ctx->scl_data.recout.width = surf_clip.width * + pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * stream->dst.width / stream->src.width; - if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x > + if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > stream->dst.x + stream->dst.width) - pipe_ctx->scl_data.recout.width = + pipe_ctx->plane_res.scl_data.recout.width = stream->dst.x + stream->dst.width - - pipe_ctx->scl_data.recout.x; + - pipe_ctx->plane_res.scl_data.recout.x; - pipe_ctx->scl_data.recout.y = stream->dst.y; + pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; if (stream->src.y < surf_clip.y) - pipe_ctx->scl_data.recout.y += (surf_clip.y + pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y - stream->src.y) * stream->dst.height / stream->src.height; - pipe_ctx->scl_data.recout.height = surf_clip.height * + pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * stream->dst.height / stream->src.height; - if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y > + if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y > stream->dst.y + stream->dst.height) - pipe_ctx->scl_data.recout.height = + pipe_ctx->plane_res.scl_data.recout.height = stream->dst.y + stream->dst.height - - pipe_ctx->scl_data.recout.y; + - pipe_ctx->plane_res.scl_data.recout.y; /* Handle h & vsplit */ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { - pipe_ctx->scl_data.recout.height /= 2; - pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; + pipe_ctx->plane_res.scl_data.recout.height /= 2; + pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; /* Floor primary pipe, ceil 2ndary pipe */ - pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2; + pipe_ctx->plane_res.scl_data.recout.height += pipe_ctx->plane_res.scl_data.recout.height % 2; } else { - pipe_ctx->scl_data.recout.width /= 2; - pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width; - pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2; + pipe_ctx->plane_res.scl_data.recout.width /= 2; + pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; + pipe_ctx->plane_res.scl_data.recout.width += pipe_ctx->plane_res.scl_data.recout.width % 2; } } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) - pipe_ctx->scl_data.recout.height /= 2; + pipe_ctx->plane_res.scl_data.recout.height /= 2; else - pipe_ctx->scl_data.recout.width /= 2; + pipe_ctx->plane_res.scl_data.recout.width /= 2; } /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset) @@ -601,8 +601,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip surf_src.y * plane_state->dst_rect.height / surf_src.height * stream->dst.height / stream->src.height; - recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; - recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y; + recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x; + recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y; } static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) @@ -619,36 +619,36 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); - pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction( + pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction( surf_src.width, plane_state->dst_rect.width); - pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction( + pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction( surf_src.height, plane_state->dst_rect.height); if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) - pipe_ctx->scl_data.ratios.horz.value *= 2; + pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) - pipe_ctx->scl_data.ratios.vert.value *= 2; + pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; - pipe_ctx->scl_data.ratios.vert.value = div64_s64( - pipe_ctx->scl_data.ratios.vert.value * in_h, out_h); - pipe_ctx->scl_data.ratios.horz.value = div64_s64( - pipe_ctx->scl_data.ratios.horz.value * in_w, out_w); + pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( + pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); + pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( + pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); - pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz; - pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert; + pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; + pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; - if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8 - || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) { - pipe_ctx->scl_data.ratios.horz_c.value /= 2; - pipe_ctx->scl_data.ratios.vert_c.value /= 2; + if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 + || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { + pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; + pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; } } static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - struct scaler_data *data = &pipe_ctx->scl_data; + struct scaler_data *data = &pipe_ctx->plane_res.scl_data; struct rect src = pipe_ctx->plane_state->src_rect; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; @@ -823,14 +823,14 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * lb depth calculation requires recout and taps require scaling ratios. * Inits require viewport, taps, ratios and recout of split pipe */ - pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( + pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( pipe_ctx->plane_state->format); calculate_scaling_ratios(pipe_ctx); calculate_viewport(pipe_ctx); - if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16) + if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16) return false; calculate_recout(pipe_ctx, &recout_skip); @@ -839,21 +839,21 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * Setting line buffer pixel depth to 24bpp yields banding * on certain displays, such as the Sharp 4k */ - pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; - pipe_ctx->scl_data.h_active = timing->h_addressable; - pipe_ctx->scl_data.v_active = timing->v_addressable; + pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable; + pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable; /* Taps calculations */ res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); if (!res) { /* Try 24 bpp linebuffer */ - pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); } if (res) @@ -865,10 +865,10 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) "y:%d\n dst_rect:\nheight:%d width:%d x:%d " "y:%d\n", __func__, - pipe_ctx->scl_data.viewport.height, - pipe_ctx->scl_data.viewport.width, - pipe_ctx->scl_data.viewport.x, - pipe_ctx->scl_data.viewport.y, + pipe_ctx->plane_res.scl_data.viewport.height, + pipe_ctx->plane_res.scl_data.viewport.width, + pipe_ctx->plane_res.scl_data.viewport.x, + pipe_ctx->plane_res.scl_data.viewport.y, plane_state->dst_rect.height, plane_state->dst_rect.width, plane_state->dst_rect.x, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 2b6506822cca..ef3a7b83cebe 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -223,9 +223,9 @@ bool dc_stream_set_cursor_position( struct dc_cursor_mi_param param = { .pixel_clk_khz = stream->timing.pix_clk_khz, .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz, - .viewport_x_start = pipe_ctx->scl_data.viewport.x, - .viewport_width = pipe_ctx->scl_data.viewport.width, - .h_scale_ratio = pipe_ctx->scl_data.ratios.horz + .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x, + .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width, + .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz }; if (pipe_ctx->stream != stream || diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ea9ce87d348a..dee18c92fd52 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -914,7 +914,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, { uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; - switch (pipe_ctx->scl_data.format) { + switch (pipe_ctx->plane_res.scl_data.format) { case PIXEL_FORMAT_ARGB8888: /* set boarder color to red */ color->color_r_cr = color_value; @@ -964,7 +964,7 @@ static void program_scaler(const struct core_dc *dc, pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( pipe_ctx->xfm, - pipe_ctx->scl_data.lb_params.depth, + pipe_ctx->plane_res.scl_data.lb_params.depth, &pipe_ctx->stream->bit_depth_params); if (pipe_ctx->tg->funcs->set_overscan_blank_color) @@ -973,7 +973,7 @@ static void program_scaler(const struct core_dc *dc, &color); pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, - &pipe_ctx->scl_data); + &pipe_ctx->plane_res.scl_data); } static enum dc_status dce110_prog_pixclk_crtc_otg( @@ -1114,10 +1114,10 @@ static enum dc_status apply_single_controller_ctx_to_hw( &stream->sink->link->cur_link_settings); } - pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; /* program_scaler and allocate_mem_input are not new asic */ if ((!pipe_ctx_old || - memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, + memcmp(&pipe_ctx_old->plane_res.scl_data, &pipe_ctx->plane_res.scl_data, sizeof(struct scaler_data)) != 0) && pipe_ctx->plane_state) { program_scaler(dc, pipe_ctx); @@ -1927,14 +1927,14 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) default_adjust.out_color_space = pipe_ctx->stream->output_color_space; default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; - default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; + default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; /* display color depth */ default_adjust.color_depth = pipe_ctx->stream->timing.display_color_depth; /* Lb color depth */ - default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; + default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; pipe_ctx->xfm->funcs->opp_set_csc_default( pipe_ctx->xfm, &default_adjust); @@ -2096,7 +2096,7 @@ static void set_plane_config( pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); - pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; program_scaler(dc, pipe_ctx); program_surface_visibility(dc, pipe_ctx); @@ -2552,7 +2552,7 @@ static void dce110_program_front_end_for_pipe( pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); - pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; program_scaler(dc, pipe_ctx); @@ -2602,14 +2602,14 @@ static void dce110_program_front_end_for_pipe( "viewport:%d, %d, %d, %d\n" "recout: %d, %d, %d, %d\n", pipe_ctx->pipe_idx, - pipe_ctx->scl_data.viewport.width, - pipe_ctx->scl_data.viewport.height, - pipe_ctx->scl_data.viewport.x, - pipe_ctx->scl_data.viewport.y, - pipe_ctx->scl_data.recout.width, - pipe_ctx->scl_data.recout.height, - pipe_ctx->scl_data.recout.x, - pipe_ctx->scl_data.recout.y); + pipe_ctx->plane_res.scl_data.viewport.width, + pipe_ctx->plane_res.scl_data.viewport.height, + pipe_ctx->plane_res.scl_data.viewport.x, + pipe_ctx->plane_res.scl_data.viewport.y, + pipe_ctx->plane_res.scl_data.recout.width, + pipe_ctx->plane_res.scl_data.recout.height, + pipe_ctx->plane_res.scl_data.recout.x, + pipe_ctx->plane_res.scl_data.recout.y); } static void dce110_apply_ctx_for_surface( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 5922cf8272f5..314d7645a898 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1728,14 +1728,14 @@ static void dcn10_power_on_fe( "viewport:%d, %d, %d, %d\n" "recout: %d, %d, %d, %d\n", pipe_ctx->pipe_idx, - pipe_ctx->scl_data.viewport.width, - pipe_ctx->scl_data.viewport.height, - pipe_ctx->scl_data.viewport.x, - pipe_ctx->scl_data.viewport.y, - pipe_ctx->scl_data.recout.width, - pipe_ctx->scl_data.recout.height, - pipe_ctx->scl_data.recout.x, - pipe_ctx->scl_data.recout.y); + pipe_ctx->plane_res.scl_data.viewport.width, + pipe_ctx->plane_res.scl_data.viewport.height, + pipe_ctx->plane_res.scl_data.viewport.x, + pipe_ctx->plane_res.scl_data.viewport.y, + pipe_ctx->plane_res.scl_data.recout.width, + pipe_ctx->plane_res.scl_data.recout.height, + pipe_ctx->plane_res.scl_data.recout.x, + pipe_ctx->plane_res.scl_data.recout.y); print_rq_dlg_ttu(dc, pipe_ctx); } } @@ -1860,7 +1860,7 @@ static void dcn10_get_surface_visual_confirm_color( { uint32_t color_value = MAX_TG_COLOR_VALUE; - switch (pipe_ctx->scl_data.format) { + switch (pipe_ctx->plane_res.scl_data.format) { case PIXEL_FORMAT_ARGB8888: /* set boarder color to red */ color->color_r_cr = color_value; @@ -1931,7 +1931,7 @@ static void update_dchubp_dpp( &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); - size.grph.surface_size = pipe_ctx->scl_data.viewport; + size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( @@ -1965,13 +1965,13 @@ static void update_dchubp_dpp( && per_pixel_alpha; dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg); - pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha; - pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; /* scaler configuration */ pipe_ctx->xfm->funcs->transform_set_scaler( - pipe_ctx->xfm, &pipe_ctx->scl_data); + pipe_ctx->xfm, &pipe_ctx->plane_res.scl_data); mi->funcs->mem_program_viewport(mi, - &pipe_ctx->scl_data.viewport, &pipe_ctx->scl_data.viewport_c); + &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); /*gamut remap*/ program_gamut_remap(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 6c937411af23..dbca1de89494 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -157,7 +157,7 @@ struct stream_resource { }; struct plane_resource { - int stub; + struct scaler_data scl_data; }; struct pipe_ctx { @@ -173,8 +173,6 @@ struct pipe_ctx { struct output_pixel_processor *opp; struct timing_generator *tg; - struct scaler_data scl_data; - struct stream_encoder *stream_enc; struct display_clock *dis_clk; struct clock_source *clock_source; -- cgit v1.2.3-59-g8ed1b From 86a66c4eb7365c96230bca218634439f7b057306 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 11:55:55 -0400 Subject: drm/amd/display: Move mi, ipp, xfm to plane_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.mi/\.plane_res.mi/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->mi/->plane_res.mi/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.ipp/\.plane_res.ipp/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->ipp/->plane_res.ipp/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.xfm/\.plane_res.xfm/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->xfm/->plane_res.xfm/g' To clean up bad renames: find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.min/\.min/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.min/->min/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.mic/->mic/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.mis/\.mis/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.mid/->mid/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.mid/\.mid/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.mis/->mis/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.min/\.min/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.min/->min/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.mic/->mic/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.mis/\.mis/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.mid/->mid/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.mid/\.mid/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/->plane_res\.mis/->mis/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/\.plane_res\.ipps/\.ipps/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/mpcc_cfg\.plane_res\.mi/mpcc_cfg\.mi/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/mi->plane_res\./mi->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/cfg->plane_res\./cfg->/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 20 +++--- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 10 +-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 80 +++++++++++----------- .../drm/amd/display/dc/dce110/dce110_resource.c | 8 +-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 40 +++++------ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 7 +- 8 files changed, 89 insertions(+), 88 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index cb762006e1c3..1922c13d6f22 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -547,9 +547,9 @@ static void split_stream_across_pipes( *secondary_pipe = *primary_pipe; secondary_pipe->pipe_idx = pipe_idx; - secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx]; - secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx]; - secondary_pipe->xfm = pool->transforms[secondary_pipe->pipe_idx]; + secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; + secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; + secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; if (primary_pipe->bottom_pipe) { secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 84a15a999117..7270f0de9598 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -845,15 +845,15 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable; /* Taps calculations */ - res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); + res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( + pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); if (!res) { /* Try 24 bpp linebuffer */ pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; - res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); + res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( + pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); } if (res) @@ -1012,9 +1012,9 @@ static int acquire_first_split_pipe( memset(pipe_ctx, 0, sizeof(*pipe_ctx)); pipe_ctx->tg = pool->timing_generators[i]; - pipe_ctx->mi = pool->mis[i]; - pipe_ctx->ipp = pool->ipps[i]; - pipe_ctx->xfm = pool->transforms[i]; + pipe_ctx->plane_res.mi = pool->mis[i]; + pipe_ctx->plane_res.ipp = pool->ipps[i]; + pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx->opp = pool->opps[i]; pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; @@ -1242,9 +1242,9 @@ static int acquire_first_free_pipe( struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; pipe_ctx->tg = pool->timing_generators[i]; - pipe_ctx->mi = pool->mis[i]; - pipe_ctx->ipp = pool->ipps[i]; - pipe_ctx->xfm = pool->transforms[i]; + pipe_ctx->plane_res.mi = pool->mis[i]; + pipe_ctx->plane_res.ipp = pool->ipps[i]; + pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx->opp = pool->opps[i]; pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index ef3a7b83cebe..10587896cc86 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -183,13 +183,13 @@ bool dc_stream_set_cursor_attributes( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if (pipe_ctx->stream != stream || !pipe_ctx->ipp) + if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.ipp) continue; if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) continue; - pipe_ctx->ipp->funcs->ipp_cursor_set_attributes( - pipe_ctx->ipp, attributes); + pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( + pipe_ctx->plane_res.ipp, attributes); } return true; @@ -218,7 +218,7 @@ bool dc_stream_set_cursor_position( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; struct dc_cursor_position pos_cpy = *position; struct dc_cursor_mi_param param = { .pixel_clk_khz = stream->timing.pix_clk_khz, @@ -229,7 +229,7 @@ bool dc_stream_set_cursor_position( }; if (pipe_ctx->stream != stream || - !pipe_ctx->ipp || !pipe_ctx->plane_state) + !pipe_ctx->plane_res.ipp || !pipe_ctx->plane_state) continue; if (pipe_ctx->plane_state->address.type diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index dee18c92fd52..1586dc95f5e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -242,7 +242,7 @@ static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; const struct dc_transfer_func *tf = NULL; struct ipp_prescale_params prescale_params = { 0 }; bool result = true; @@ -625,7 +625,7 @@ static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) { - struct transform *xfm = pipe_ctx->xfm; + struct transform *xfm = pipe_ctx->plane_res.xfm; xfm->funcs->opp_power_on_regamma_lut(xfm, true); xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; @@ -951,7 +951,7 @@ static void program_scaler(const struct core_dc *dc, #if defined(CONFIG_DRM_AMD_DC_DCN1_0) /* TOFPGA */ - if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL) + if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) return; #endif @@ -962,8 +962,8 @@ static void program_scaler(const struct core_dc *dc, pipe_ctx->stream->output_color_space, &color); - pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( - pipe_ctx->xfm, + pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( + pipe_ctx->plane_res.xfm, pipe_ctx->plane_res.scl_data.lb_params.depth, &pipe_ctx->stream->bit_depth_params); @@ -972,7 +972,7 @@ static void program_scaler(const struct core_dc *dc, pipe_ctx->tg, &color); - pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, + pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data); } @@ -1125,10 +1125,10 @@ static enum dc_status apply_single_controller_ctx_to_hw( /* mst support - use total stream count */ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (pipe_ctx->mi->funcs->allocate_mem_input != NULL) + if (pipe_ctx->plane_res.mi->funcs->allocate_mem_input != NULL) #endif - pipe_ctx->mi->funcs->allocate_mem_input( - pipe_ctx->mi, + pipe_ctx->plane_res.mi->funcs->allocate_mem_input( + pipe_ctx->plane_res.mi, stream->timing.h_total, stream->timing.v_total, stream->timing.pix_clk_khz, @@ -1260,16 +1260,16 @@ void dce110_set_displaymarks( total_dest_line_time_ns = compute_pstate_blackout_duration( dc->bw_vbios.blackout_duration, pipe_ctx->stream); - pipe_ctx->mi->funcs->mem_input_program_display_marks( - pipe_ctx->mi, + pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( + pipe_ctx->plane_res.mi, context->bw.dce.nbp_state_change_wm_ns[num_pipes], context->bw.dce.stutter_exit_wm_ns[num_pipes], context->bw.dce.urgent_wm_ns[num_pipes], total_dest_line_time_ns); if (i == underlay_idx) { num_pipes++; - pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( - pipe_ctx->mi, + pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( + pipe_ctx->plane_res.mi, context->bw.dce.nbp_state_change_wm_ns[num_pipes], context->bw.dce.stutter_exit_wm_ns[num_pipes], context->bw.dce.urgent_wm_ns[num_pipes], @@ -1294,15 +1294,15 @@ static void set_safe_displaymarks( if (res_ctx->pipe_ctx[i].stream == NULL) continue; - res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( - res_ctx->pipe_ctx[i].mi, + res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( + res_ctx->pipe_ctx[i].plane_res.mi, nbp_marks, max_marks, max_marks, MAX_WATERMARK); if (i == underlay_idx) - res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( - res_ctx->pipe_ctx[i].mi, + res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( + res_ctx->pipe_ctx[i].plane_res.mi, nbp_marks, max_marks, max_marks, @@ -1652,8 +1652,8 @@ static void dce110_reset_hw_ctx_wrap( BREAK_TO_DEBUGGER(); } pipe_ctx_old->tg->funcs->disable_crtc(pipe_ctx_old->tg); - pipe_ctx_old->mi->funcs->free_mem_input( - pipe_ctx_old->mi, dc->current_context->stream_count); + pipe_ctx_old->plane_res.mi->funcs->free_mem_input( + pipe_ctx_old->plane_res.mi, dc->current_context->stream_count); resource_unreference_clock_source( &dc->current_context->res_ctx, dc->res_pool, &pipe_ctx_old->clock_source); @@ -1936,8 +1936,8 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) /* Lb color depth */ default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; - pipe_ctx->xfm->funcs->opp_set_csc_default( - pipe_ctx->xfm, &default_adjust); + pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( + pipe_ctx->plane_res.xfm, &default_adjust); } @@ -2026,7 +2026,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) gamut_remap_matrix.matrix[10]; } - pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); + pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); } /** @@ -2037,7 +2037,7 @@ static void set_plane_config( struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { - struct mem_input *mi = pipe_ctx->mi; + struct mem_input *mi = pipe_ctx->plane_res.mi; struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; @@ -2059,8 +2059,8 @@ static void set_plane_config( tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; - pipe_ctx->xfm->funcs->opp_set_csc_adjustment - (pipe_ctx->xfm, &tbl_entry); + pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment + (pipe_ctx->plane_res.xfm, &tbl_entry); } if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { @@ -2094,7 +2094,7 @@ static void set_plane_config( gamut_remap_matrix.matrix[10]; } - pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); + pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; program_scaler(dc, pipe_ctx); @@ -2114,7 +2114,7 @@ static void set_plane_config( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( - pipe_ctx->mi, + pipe_ctx->plane_res.mi, plane_state->format, &plane_state->tiling_info, plane_state->rotation); @@ -2128,8 +2128,8 @@ static void update_plane_addr(const struct core_dc *dc, if (plane_state == NULL) return; - pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( - pipe_ctx->mi, + pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( + pipe_ctx->plane_res.mi, &plane_state->address, plane_state->flip_immediate); @@ -2144,14 +2144,14 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) return; plane_state->status.is_flip_pending = - pipe_ctx->mi->funcs->mem_input_is_flip_pending( - pipe_ctx->mi); + pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( + pipe_ctx->plane_res.mi); if (plane_state->status.is_flip_pending && !plane_state->visible) - pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; + pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; - plane_state->status.current_address = pipe_ctx->mi->current_address; - if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && + plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; + if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && pipe_ctx->tg->funcs->is_stereo_left_eye) { plane_state->status.is_right_eye =\ !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); @@ -2488,7 +2488,7 @@ static void dce110_set_bandwidth( static void dce110_program_front_end_for_pipe( struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct mem_input *mi = pipe_ctx->mi; + struct mem_input *mi = pipe_ctx->plane_res.mi; struct pipe_ctx *old_pipe = NULL; struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; @@ -2515,8 +2515,8 @@ static void dce110_program_front_end_for_pipe( tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; - pipe_ctx->xfm->funcs->opp_set_csc_adjustment - (pipe_ctx->xfm, &tbl_entry); + pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment + (pipe_ctx->plane_res.xfm, &tbl_entry); } if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { @@ -2550,7 +2550,7 @@ static void dce110_program_front_end_for_pipe( gamut_remap_matrix.matrix[10]; } - pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); + pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; @@ -2569,7 +2569,7 @@ static void dce110_program_front_end_for_pipe( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( - pipe_ctx->mi, + pipe_ctx->plane_res.mi, plane_state->format, &plane_state->tiling_info, plane_state->rotation); @@ -2673,7 +2673,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; - pipe_ctx->xfm->funcs->opp_set_csc_adjustment(pipe_ctx->xfm, &tbl_entry); + pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index f580da1b3249..04a508234251 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1017,9 +1017,9 @@ static struct pipe_ctx *dce110_acquire_underlay( return NULL; pipe_ctx->tg = pool->timing_generators[underlay_idx]; - pipe_ctx->mi = pool->mis[underlay_idx]; - /*pipe_ctx->ipp = res_ctx->pool->ipps[underlay_idx];*/ - pipe_ctx->xfm = pool->transforms[underlay_idx]; + pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; + /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ + pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; pipe_ctx->opp = pool->opps[underlay_idx]; pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = underlay_idx; @@ -1049,7 +1049,7 @@ static struct pipe_ctx *dce110_acquire_underlay( true, &stream->timing); - pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, + pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, stream->timing.h_total, stream->timing.v_total, stream->timing.pix_clk_khz, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 314d7645a898..1cf672d4a1ee 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1070,8 +1070,8 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct if (plane_state == NULL) return; addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); - pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( - pipe_ctx->mi, + pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( + pipe_ctx->plane_res.mi, &plane_state->address, plane_state->flip_immediate); plane_state->status.requested_address = plane_state->address; @@ -1082,7 +1082,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct static bool dcn10_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; const struct dc_transfer_func *tf = NULL; bool result = true; @@ -1447,7 +1447,7 @@ static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) { - struct transform *xfm = pipe_ctx->xfm; + struct transform *xfm = pipe_ctx->plane_res.xfm; if (xfm == NULL) return false; @@ -1778,7 +1778,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) gamut_remap_matrix.matrix[10]; } - pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); + pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); } @@ -1800,7 +1800,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; - pipe_ctx->xfm->funcs->opp_set_csc_adjustment(pipe_ctx->xfm, &tbl_entry); + pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry); } } static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) @@ -1896,8 +1896,8 @@ static void update_dchubp_dpp( struct validate_context *context) { struct dce_hwseq *hws = dc->hwseq; - struct mem_input *mi = pipe_ctx->mi; - struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct mem_input *mi = pipe_ctx->plane_res.mi; + struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; struct dc_plane_state *plane_state = pipe_ctx->plane_state; union plane_size size = plane_state->plane_size; struct default_adjustment ocsc = {0}; @@ -1935,7 +1935,7 @@ static void update_dchubp_dpp( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( - pipe_ctx->mi, + pipe_ctx->plane_res.mi, plane_state->format, &plane_state->tiling_info, plane_state->rotation); @@ -1968,8 +1968,8 @@ static void update_dchubp_dpp( pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; /* scaler configuration */ - pipe_ctx->xfm->funcs->transform_set_scaler( - pipe_ctx->xfm, &pipe_ctx->plane_res.scl_data); + pipe_ctx->plane_res.xfm->funcs->transform_set_scaler( + pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data); mi->funcs->mem_program_viewport(mi, &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); @@ -1978,7 +1978,7 @@ static void update_dchubp_dpp( /*TODO add adjustments parameters*/ ocsc.out_color_space = pipe_ctx->stream->output_color_space; - pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc); + pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(pipe_ctx->plane_res.xfm, &ocsc); mi->funcs->mem_input_program_surface_config( mi, @@ -2098,7 +2098,7 @@ static void dcn10_apply_ctx_for_surface( */ if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { - if (pipe_ctx->mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) { + if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) { dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); /* * power down fe will unlock when calling reset, need @@ -2124,7 +2124,7 @@ static void dcn10_apply_ctx_for_surface( dc->res_pool->mpc, old_pipe_ctx->opp, old_pipe_ctx->pipe_idx); - old_pipe_ctx->opp->mpcc_disconnect_pending[old_pipe_ctx->mi->mpcc_id] = true; + old_pipe_ctx->opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", @@ -2481,19 +2481,19 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) return; plane_state->status.is_flip_pending = - pipe_ctx->mi->funcs->mem_input_is_flip_pending( - pipe_ctx->mi); + pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( + pipe_ctx->plane_res.mi); /* DCN we read INUSE address in MI, do we still need this wa? */ if (plane_state->status.is_flip_pending && !plane_state->visible) { - pipe_ctx->mi->current_address = - pipe_ctx->mi->request_address; + pipe_ctx->plane_res.mi->current_address = + pipe_ctx->plane_res.mi->request_address; BREAK_TO_DEBUGGER(); } - plane_state->status.current_address = pipe_ctx->mi->current_address; - if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && + plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; + if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && tg->funcs->is_stereo_left_eye) { plane_state->status.is_right_eye = !tg->funcs->is_stereo_left_eye(pipe_ctx->tg); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 3fe6df92f91f..710e514ee950 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -963,9 +963,9 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( idle_pipe->tg = head_pipe->tg; idle_pipe->opp = head_pipe->opp; - idle_pipe->mi = pool->mis[idle_pipe->pipe_idx]; - idle_pipe->ipp = pool->ipps[idle_pipe->pipe_idx]; - idle_pipe->xfm = pool->transforms[idle_pipe->pipe_idx]; + idle_pipe->plane_res.mi = pool->mis[idle_pipe->pipe_idx]; + idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; + idle_pipe->plane_res.xfm = pool->transforms[idle_pipe->pipe_idx]; return idle_pipe; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index dbca1de89494..4640c43d17a4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -158,6 +158,10 @@ struct stream_resource { struct plane_resource { struct scaler_data scl_data; + + struct mem_input *mi; + struct input_pixel_processor *ipp; + struct transform *xfm; }; struct pipe_ctx { @@ -167,9 +171,6 @@ struct pipe_ctx { struct plane_resource plane_res; struct stream_resource stream_res; - struct mem_input *mi; - struct input_pixel_processor *ipp; - struct transform *xfm; struct output_pixel_processor *opp; struct timing_generator *tg; -- cgit v1.2.3-59-g8ed1b From a6a6cb349e39ef23a341a17752eebf69a5c0d7ff Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 13:55:28 -0400 Subject: drm/amd/display: Move OPP to stream_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipes->opp/pipes->stream_res\.opp/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/ctx->opp->/ctx->stream_res\.opp->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe->opp/pipe->stream_res\.opp/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx->opp/pipe_ctx->stream_res\.opp/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 12 +++++------ .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 +++++++++++----------- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +-- 8 files changed, 30 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ffc9c05e2fb5..507732e4b67b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -365,8 +365,8 @@ void set_dither_option(struct dc_stream_state *stream, resource_build_bit_depth_reduction_params(stream, ¶ms); stream->bit_depth_params = params; - pipes->opp->funcs-> - opp_program_bit_depth_reduction(pipes->opp, ¶ms); + pipes->stream_res.opp->funcs-> + opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); } static void allocate_dc_stream_funcs(struct core_dc *core_dc) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 231cade5e1fd..0c90060c0f62 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2372,8 +2372,8 @@ static void set_crtc_test_pattern(struct dc_link *link, { /* disable bit depth reduction */ pipe_ctx->stream->bit_depth_params = params; - pipe_ctx->opp->funcs-> - opp_program_bit_depth_reduction(pipe_ctx->opp, ¶ms); + pipe_ctx->stream_res.opp->funcs-> + opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms); pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg, controller_test_pattern, color_depth); @@ -2385,8 +2385,8 @@ static void set_crtc_test_pattern(struct dc_link *link, resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms); pipe_ctx->stream->bit_depth_params = params; - pipe_ctx->opp->funcs-> - opp_program_bit_depth_reduction(pipe_ctx->opp, ¶ms); + pipe_ctx->stream_res.opp->funcs-> + opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms); pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg, CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7270f0de9598..ba529f8b24e8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1015,7 +1015,7 @@ static int acquire_first_split_pipe( pipe_ctx->plane_res.mi = pool->mis[i]; pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; - pipe_ctx->opp = pool->opps[i]; + pipe_ctx->stream_res.opp = pool->opps[i]; pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; @@ -1095,7 +1095,7 @@ bool resource_attach_surfaces_to_context( if (tail_pipe) { free_pipe->tg = tail_pipe->tg; - free_pipe->opp = tail_pipe->opp; + free_pipe->stream_res.opp = tail_pipe->stream_res.opp; free_pipe->stream_enc = tail_pipe->stream_enc; free_pipe->audio = tail_pipe->audio; free_pipe->clock_source = tail_pipe->clock_source; @@ -1245,7 +1245,7 @@ static int acquire_first_free_pipe( pipe_ctx->plane_res.mi = pool->mis[i]; pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; - pipe_ctx->opp = pool->opps[i]; + pipe_ctx->stream_res.opp = pool->opps[i]; pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1586dc95f5e4..0601105a5e3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1044,16 +1044,16 @@ static enum dc_status apply_single_controller_ctx_to_hw( /* */ dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); - pipe_ctx->opp->funcs->opp_set_dyn_expansion( - pipe_ctx->opp, + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601, stream->timing.display_color_depth, pipe_ctx->stream->signal); /* FPGA does not program backend */ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { - pipe_ctx->opp->funcs->opp_program_fmt( - pipe_ctx->opp, + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( + pipe_ctx->stream_res.opp, &stream->bit_depth_params, &stream->clamping); return DC_OK; @@ -1078,8 +1078,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ - pipe_ctx->opp->funcs->opp_program_fmt( - pipe_ctx->opp, + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( + pipe_ctx->stream_res.opp, &stream->bit_depth_params, &stream->clamping); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 04a508234251..4b7bce2427a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1020,7 +1020,7 @@ static struct pipe_ctx *dce110_acquire_underlay( pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; - pipe_ctx->opp = pool->opps[underlay_idx]; + pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = underlay_idx; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1cf672d4a1ee..2db6b46baa6c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -720,8 +720,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( &stream->timing, true); - pipe_ctx->opp->funcs->opp_set_stereo_polarity( - pipe_ctx->opp, + pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity( + pipe_ctx->stream_res.opp, enableStereo, rightEyePolarity); @@ -731,8 +731,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt; - pipe_ctx->opp->funcs->opp_program_fmt( - pipe_ctx->opp, + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( + pipe_ctx->stream_res.opp, &stream->bit_depth_params, &stream->clamping); #endif @@ -1946,7 +1946,7 @@ static void update_dchubp_dpp( IPP_OUTPUT_FORMAT_12_BIT_FIX); mpcc_cfg.mi = mi; - mpcc_cfg.opp = pipe_ctx->opp; + mpcc_cfg.opp = pipe_ctx->stream_res.opp; for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) mpcc_cfg.z_index++; if (dc->public.debug.surface_visual_confirm) @@ -2122,9 +2122,9 @@ static void dcn10_apply_ctx_for_surface( /* reset mpc */ dc->res_pool->mpc->funcs->remove( dc->res_pool->mpc, - old_pipe_ctx->opp, + old_pipe_ctx->stream_res.opp, old_pipe_ctx->pipe_idx); - old_pipe_ctx->opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true; + old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", @@ -2364,8 +2364,8 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) dcn10_config_stereo_parameters(stream, &flags); - pipe_ctx->opp->funcs->opp_set_stereo_polarity( - pipe_ctx->opp, + pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity( + pipe_ctx->stream_res.opp, flags.PROGRAM_STEREO == 1 ? true:false, stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); @@ -2441,13 +2441,13 @@ static void dcn10_wait_for_mpcc_disconnect( { int i; - if (!pipe_ctx->opp) + if (!pipe_ctx->stream_res.opp) return; for (i = 0; i < MAX_PIPES; i++) { - if (pipe_ctx->opp->mpcc_disconnect_pending[i]) { + if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) { res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i); - pipe_ctx->opp->mpcc_disconnect_pending[i] = false; + pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false; res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true); /*dm_logger_write(dc->ctx->logger, LOG_ERROR, "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n", diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 710e514ee950..e15eec315228 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -961,7 +961,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( idle_pipe->stream = head_pipe->stream; idle_pipe->tg = head_pipe->tg; - idle_pipe->opp = head_pipe->opp; + idle_pipe->stream_res.opp = head_pipe->stream_res.opp; idle_pipe->plane_res.mi = pool->mis[idle_pipe->pipe_idx]; idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 4640c43d17a4..24a525495bfc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -153,7 +153,7 @@ struct resource_pool { }; struct stream_resource { - int stub; + struct output_pixel_processor *opp; }; struct plane_resource { @@ -171,7 +171,6 @@ struct pipe_ctx { struct plane_resource plane_res; struct stream_resource stream_res; - struct output_pixel_processor *opp; struct timing_generator *tg; struct stream_encoder *stream_enc; -- cgit v1.2.3-59-g8ed1b From 6b670fa965b620bf0131a0a339a388a0581bc466 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 13:59:26 -0400 Subject: drm/amd/display: Move TG to stream_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipes->tg/pipes->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/ctx->tg->/ctx->stream_res\.tg->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe->tg/pipe->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx->tg/pipe_ctx->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[pipe_offset\]\.tg/pipe_ctx\[pipe_offset\]\.stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/grouped_pipes\[i\]->tg/grouped_pipes\[i\]->stream_^Cs\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/grouped_pipes\[0\]->tg/grouped_pipes\[0\]->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/grouped_pipes\[1\]->tg/grouped_pipes\[1\]->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx\[i\]->tg/pipe_ctx\[i\]->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx_old->tg/pipe_ctx_old->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_set\[j\]->tg/pipe_set\[j\]->stream_res\.tg/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx\[i\]\.tg/pipe_ctx\[i\]\.stream_res\.tg/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 64 +++++++-------- .../drm/amd/display/dc/dce110/dce110_resource.c | 12 +-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 96 +++++++++++----------- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +- 13 files changed, 105 insertions(+), 106 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 507732e4b67b..61c2a210c123 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -846,7 +846,7 @@ static void program_timing_sync( for (j = 0; j < group_size; j++) { struct pipe_ctx *temp; - if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) { + if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) { if (j == 0) break; @@ -859,7 +859,7 @@ static void program_timing_sync( /* remove any other unblanked pipes as they have already been synced */ for (j = j + 1; j < group_size; j++) { - if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) { + if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) { group_size--; pipe_set[j] = pipe_set[group_size]; j--; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index ca4f1db4a58a..21af3bc057c7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -309,7 +309,7 @@ void context_timing_trace( || pipe_ctx->pipe_idx == underlay_idx) continue; - pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &position); + pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); h_pos[i] = position.horizontal_count; v_pos[i] = position.vertical_count; } @@ -320,7 +320,7 @@ void context_timing_trace( continue; TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", - pipe_ctx->tg->inst, + pipe_ctx->stream_res.tg->inst, pipe_ctx->stream->timing.h_total, pipe_ctx->stream->timing.v_total, h_pos[i], v_pos[i]); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 7a2fe2f3e65c..2c43edf2c7c4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1398,7 +1398,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, */ controller_id = core_dc->current_context-> - res_ctx.pipe_ctx[i].tg->inst + + res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; } } @@ -1504,7 +1504,7 @@ bool dc_link_setup_psr(struct dc_link *link, */ psr_context->controllerId = core_dc->current_context->res_ctx. - pipe_ctx[i].tg->inst + 1; + pipe_ctx[i].stream_res.tg->inst + 1; break; } } @@ -1879,7 +1879,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) } /* turn off otg test pattern if enable */ - pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, COLOR_DEPTH_UNDEFINED); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 0c90060c0f62..eda25942aea0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2375,7 +2375,7 @@ static void set_crtc_test_pattern(struct dc_link *link, pipe_ctx->stream_res.opp->funcs-> opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms); - pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, controller_test_pattern, color_depth); } break; @@ -2388,7 +2388,7 @@ static void set_crtc_test_pattern(struct dc_link *link, pipe_ctx->stream_res.opp->funcs-> opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms); - pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, color_depth); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ba529f8b24e8..5326713bf3fb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1011,7 +1011,7 @@ static int acquire_first_split_pipe( pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; memset(pipe_ctx, 0, sizeof(*pipe_ctx)); - pipe_ctx->tg = pool->timing_generators[i]; + pipe_ctx->stream_res.tg = pool->timing_generators[i]; pipe_ctx->plane_res.mi = pool->mis[i]; pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; @@ -1094,7 +1094,7 @@ bool resource_attach_surfaces_to_context( free_pipe->plane_state = plane_state; if (tail_pipe) { - free_pipe->tg = tail_pipe->tg; + free_pipe->stream_res.tg = tail_pipe->stream_res.tg; free_pipe->stream_res.opp = tail_pipe->stream_res.opp; free_pipe->stream_enc = tail_pipe->stream_enc; free_pipe->audio = tail_pipe->audio; @@ -1241,7 +1241,7 @@ static int acquire_first_free_pipe( if (!res_ctx->pipe_ctx[i].stream) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - pipe_ctx->tg = pool->timing_generators[i]; + pipe_ctx->stream_res.tg = pool->timing_generators[i]; pipe_ctx->plane_res.mi = pool->mis[i]; pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; @@ -1532,7 +1532,7 @@ enum dc_status resource_map_pool_resources( pipe_ctx->audio); } - context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst; + context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; } return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 10587896cc86..2de37fed12a5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -253,7 +253,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { - struct timing_generator *tg = res_ctx->pipe_ctx[i].tg; + struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; if (res_ctx->pipe_ctx[i].stream != stream) continue; @@ -277,7 +277,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { - struct timing_generator *tg = res_ctx->pipe_ctx[i].tg; + struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; if (res_ctx->pipe_ctx[i].stream != stream) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 8140ff31c3bd..4894e1755d84 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -53,7 +53,7 @@ void dce_pipe_control_lock(struct core_dc *dc, struct dce_hwseq *hws = dc->hwseq; /* Not lock pipe when blank */ - if (lock && pipe->tg->funcs->is_blanked(pipe->tg)) + if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) return; val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx], diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 0601105a5e3f..1d7c7fb668be 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -710,7 +710,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) */ uint32_t active_total_with_borders; uint32_t early_control = 0; - struct timing_generator *tg = pipe_ctx->tg; + struct timing_generator *tg = pipe_ctx->stream_res.tg; /* TODOFPGA may change to hwss.update_info_frame */ dce110_update_info_frame(pipe_ctx); @@ -967,9 +967,9 @@ static void program_scaler(const struct core_dc *dc, pipe_ctx->plane_res.scl_data.lb_params.depth, &pipe_ctx->stream->bit_depth_params); - if (pipe_ctx->tg->funcs->set_overscan_blank_color) - pipe_ctx->tg->funcs->set_overscan_blank_color( - pipe_ctx->tg, + if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) + pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( + pipe_ctx->stream_res.tg, &color); pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, @@ -991,15 +991,15 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( /* program blank color */ color_space_to_black_color(dc, stream->output_color_space, &black_color); - pipe_ctx->tg->funcs->set_blank_color( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_blank_color( + pipe_ctx->stream_res.tg, &black_color); /* * Must blank CRTC after disabling power gating and before any * programming, otherwise CRTC will be hung in bad state */ - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); + pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx->clock_source, @@ -1009,19 +1009,19 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( return DC_ERROR_UNEXPECTED; } - pipe_ctx->tg->funcs->program_timing( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->program_timing( + pipe_ctx->stream_res.tg, &stream->timing, true); - pipe_ctx->tg->funcs->set_static_screen_control( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_static_screen_control( + pipe_ctx->stream_res.tg, 0x182); } if (!pipe_ctx_old->stream) { - if (false == pipe_ctx->tg->funcs->enable_crtc( - pipe_ctx->tg)) { + if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( + pipe_ctx->stream_res.tg)) { BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; } @@ -1073,7 +1073,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) pipe_ctx->stream_enc->funcs->setup_stereo_sync( pipe_ctx->stream_enc, - pipe_ctx->tg->inst, + pipe_ctx->stream_res.tg->inst, stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); @@ -1359,7 +1359,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx, */ for (i = 0; i < num_pipes; i++) { - pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); + pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms); } } @@ -1372,7 +1372,7 @@ static void get_position(struct pipe_ctx **pipe_ctx, /* TODO: handle pipes > 1 */ for (i = 0; i < num_pipes; i++) - pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position); + pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); } static void set_static_screen_control(struct pipe_ctx **pipe_ctx, @@ -1393,8 +1393,8 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, #endif for (i = 0; i < num_pipes; i++) - pipe_ctx[i]->tg->funcs-> - set_static_screen_control(pipe_ctx[i]->tg, value); + pipe_ctx[i]->stream_res.tg->funcs-> + set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); } /* unit: in_khz before mode set, get pixel clock from context. ASIC register @@ -1646,12 +1646,12 @@ static void dce110_reset_hw_ctx_wrap( if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { core_link_disable_stream(pipe_ctx_old); - pipe_ctx_old->tg->funcs->set_blank(pipe_ctx_old->tg, true); - if (!hwss_wait_for_blank_complete(pipe_ctx_old->tg)) { + pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); + if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { dm_error("DC: failed to blank crtc!\n"); BREAK_TO_DEBUGGER(); } - pipe_ctx_old->tg->funcs->disable_crtc(pipe_ctx_old->tg); + pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); pipe_ctx_old->plane_res.mi->funcs->free_mem_input( pipe_ctx_old->plane_res.mi, dc->current_context->stream_count); resource_unreference_clock_source( @@ -1984,7 +1984,7 @@ static void program_surface_visibility(const struct core_dc *dc, blank_target = true; dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); + pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); } @@ -2152,9 +2152,9 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && - pipe_ctx->tg->funcs->is_stereo_left_eye) { + pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { plane_state->status.is_right_eye =\ - !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); + !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); } } @@ -2218,28 +2218,28 @@ static void dce110_enable_timing_synchronization( * Since HW doesn't care which one, we always assign * the 1st one in the group. */ gsl_params.gsl_group = 0; - gsl_params.gsl_master = grouped_pipes[0]->tg->inst; + gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; for (i = 0; i < group_size; i++) - grouped_pipes[i]->tg->funcs->setup_global_swap_lock( - grouped_pipes[i]->tg, &gsl_params); + grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( + grouped_pipes[i]->stream_res.tg, &gsl_params); /* Reset slave controllers on master VSync */ DC_SYNC_INFO("GSL: enabling trigger-reset\n"); for (i = 1 /* skip the master */; i < group_size; i++) - grouped_pipes[i]->tg->funcs->enable_reset_trigger( - grouped_pipes[i]->tg, gsl_params.gsl_group); + grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( + grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group); for (i = 1 /* skip the master */; i < group_size; i++) { DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); - wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); /* Regardless of success of the wait above, remove the reset or * the driver will start timing out on Display requests. */ DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); - grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); + grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg); } @@ -2247,7 +2247,7 @@ static void dce110_enable_timing_synchronization( * is that the sync'ed displays will not drift out of sync over time*/ DC_SYNC_INFO("GSL: Restoring register states.\n"); for (i = 0; i < group_size; i++) - grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); + grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); DC_SYNC_INFO("GSL: Set-up complete.\n"); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 4b7bce2427a8..94058ee16029 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1016,7 +1016,7 @@ static struct pipe_ctx *dce110_acquire_underlay( if (res_ctx->pipe_ctx[underlay_idx].stream) return NULL; - pipe_ctx->tg = pool->timing_generators[underlay_idx]; + pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; @@ -1040,12 +1040,12 @@ static struct pipe_ctx *dce110_acquire_underlay( * need to be enabled */ - pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, &stream->timing, false); - pipe_ctx->tg->funcs->enable_advanced_request( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->enable_advanced_request( + pipe_ctx->stream_res.tg, true, &stream->timing); @@ -1057,8 +1057,8 @@ static struct pipe_ctx *dce110_acquire_underlay( color_space_to_black_color(dc, COLOR_SPACE_YCBCR601, &black_color); - pipe_ctx->tg->funcs->set_blank_color( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_blank_color( + pipe_ctx->stream_res.tg, &black_color); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 2db6b46baa6c..99ef0f25492c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -699,7 +699,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( /* HW program guide assume display already disable * by unplug sequence. OTG assume stop. */ - pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, true); + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx->clock_source, @@ -708,15 +708,15 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; } - pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; - pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; - pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; - pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; + pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; + pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; + pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; + pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; - pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal; + pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal; - pipe_ctx->tg->funcs->program_timing( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->program_timing( + pipe_ctx->stream_res.tg, &stream->timing, true); @@ -729,7 +729,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( /* TODO: OPP FMT, ABM. etc. should be done here. */ /* or FPGA now. instance 0 only. TODO: move to opp.c */ - inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt; + inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx->stream_res.opp, @@ -739,15 +739,15 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( /* program otg blank color */ color_space = stream->output_color_space; color_space_to_black_color(dc, color_space, &black_color); - pipe_ctx->tg->funcs->set_blank_color( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->set_blank_color( + pipe_ctx->stream_res.tg, &black_color); - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); - hwss_wait_for_blank_complete(pipe_ctx->tg); + pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); + hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg); /* VTG is within DCHUB command block. DCFCLK is always on */ - if (false == pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) { + if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; } @@ -787,9 +787,9 @@ static void reset_back_end_for_pipe( * parent pipe. */ if (pipe_ctx->top_pipe == NULL) { - pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); - pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, false); + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); } if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) @@ -807,7 +807,7 @@ static void reset_back_end_for_pipe( pipe_ctx->stream = NULL; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset back end for pipe %d, tg:%d\n", - pipe_ctx->pipe_idx, pipe_ctx->tg->inst); + pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); } /* trigger HW to start disconnect plane from stream on the next vsync */ @@ -974,7 +974,7 @@ static void reset_hw_ctx_wrap( /* Lock*/ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; - struct timing_generator *tg = cur_pipe_ctx->tg; + struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) tg->funcs->lock(tg); @@ -995,7 +995,7 @@ static void reset_hw_ctx_wrap( /* Unlock*/ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; - struct timing_generator *tg = cur_pipe_ctx->tg; + struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) tg->funcs->unlock(tg); @@ -1488,9 +1488,9 @@ static void dcn10_pipe_control_lock( verify_allow_pstate_change_high(dc->hwseq); if (lock) - pipe->tg->funcs->lock(pipe->tg); + pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); else - pipe->tg->funcs->unlock(pipe->tg); + pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); @@ -1545,8 +1545,8 @@ static void dcn10_enable_timing_synchronization( DC_SYNC_INFO("Setting up OTG reset trigger\n"); for (i = 1; i < group_size; i++) - grouped_pipes[i]->tg->funcs->enable_reset_trigger( - grouped_pipes[i]->tg, grouped_pipes[0]->tg->inst); + grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( + grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst); DC_SYNC_INFO("Waiting for trigger\n"); @@ -1554,10 +1554,10 @@ static void dcn10_enable_timing_synchronization( /* Need to get only check 1 pipe for having reset as all the others are * synchronized. Look at last pipe programmed to reset. */ - wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->tg); + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg); for (i = 1; i < group_size; i++) - grouped_pipes[i]->tg->funcs->disable_reset_trigger( - grouped_pipes[i]->tg); + grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( + grouped_pipes[i]->stream_res.tg); DC_SYNC_INFO("Sync complete\n"); } @@ -1700,7 +1700,7 @@ static void dcn10_power_on_fe( HUBP_CLOCK_ENABLE, 1); /* make sure OPP_PIPE_CLOCK_EN = 1 */ - REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst], + REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst], OPP_PIPE_CLOCK_EN, 1); /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ @@ -1920,7 +1920,7 @@ static void update_dchubp_dpp( * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG */ - REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->tg->inst); + REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); update_plane_addr(dc, pipe_ctx); @@ -2012,17 +2012,17 @@ static void program_all_pipe_in_tree( verify_allow_pstate_change_high(dc->hwseq); } - pipe_ctx->tg->funcs->lock(pipe_ctx->tg); + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); - pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; - pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; - pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; - pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; - pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal; + pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; + pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; + pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; + pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; + pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal; - pipe_ctx->tg->funcs->program_global_sync( - pipe_ctx->tg); - pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx)); + pipe_ctx->stream_res.tg->funcs->program_global_sync( + pipe_ctx->stream_res.tg); + pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx)); } if (pipe_ctx->plane_state != NULL) { @@ -2098,20 +2098,20 @@ static void dcn10_apply_ctx_for_surface( */ if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { - if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) { + if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) { dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); /* * power down fe will unlock when calling reset, need * to lock it back here. Messy, need rework. */ - pipe_ctx->tg->funcs->lock(pipe_ctx->tg); + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); } } if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) || (!pipe_ctx->stream && old_pipe_ctx->stream)) { - if (old_pipe_ctx->tg->inst != be_idx) + if (old_pipe_ctx->stream_res.tg->inst != be_idx) continue; if (!old_pipe_ctx->top_pipe) { @@ -2279,7 +2279,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx, * some GSL stuff */ for (i = 0; i < num_pipes; i++) { - pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); + pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms); } } @@ -2292,7 +2292,7 @@ static void get_position(struct pipe_ctx **pipe_ctx, /* TODO: handle pipes > 1 */ for (i = 0; i < num_pipes; i++) - pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position); + pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); } static void set_static_screen_control(struct pipe_ctx **pipe_ctx, @@ -2307,8 +2307,8 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, value |= 0x2; for (i = 0; i < num_pipes; i++) - pipe_ctx[i]->tg->funcs-> - set_static_screen_control(pipe_ctx[i]->tg, value); + pipe_ctx[i]->stream_res.tg->funcs-> + set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); } static void set_plane_config( @@ -2369,8 +2369,8 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) flags.PROGRAM_STEREO == 1 ? true:false, stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); - pipe_ctx->tg->funcs->program_stereo( - pipe_ctx->tg, + pipe_ctx->stream_res.tg->funcs->program_stereo( + pipe_ctx->stream_res.tg, &stream->timing, &flags); @@ -2469,7 +2469,7 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; - struct timing_generator *tg = pipe_ctx->tg; + struct timing_generator *tg = pipe_ctx->stream_res.tg; if (plane_state->ctx->dc->debug.sanity_checks) { struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); @@ -2496,7 +2496,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && tg->funcs->is_stereo_left_eye) { plane_state->status.is_right_eye = - !tg->funcs->is_stereo_left_eye(pipe_ctx->tg); + !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index e15eec315228..bb9a42d0a147 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -960,7 +960,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( return false; idle_pipe->stream = head_pipe->stream; - idle_pipe->tg = head_pipe->tg; + idle_pipe->stream_res.tg = head_pipe->stream_res.tg; idle_pipe->stream_res.opp = head_pipe->stream_res.opp; idle_pipe->plane_res.mi = pool->mis[idle_pipe->pipe_idx]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 24a525495bfc..488ade37e353 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -154,6 +154,7 @@ struct resource_pool { struct stream_resource { struct output_pixel_processor *opp; + struct timing_generator *tg; }; struct plane_resource { @@ -171,8 +172,6 @@ struct pipe_ctx { struct plane_resource plane_res; struct stream_resource stream_res; - struct timing_generator *tg; - struct stream_encoder *stream_enc; struct display_clock *dis_clk; struct clock_source *clock_source; diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 52361d1472fa..24e47eb8cf3f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -214,7 +214,7 @@ bool dce110_vblank_set( uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; struct timing_generator *tg = - core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].tg; + core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; if (enable) { if (!tg->funcs->arm_vert_intr(tg, 2)) { -- cgit v1.2.3-59-g8ed1b From 8e9c4c8cf35ff23aafc69f9ef4c9cc471dac4094 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 14:36:12 -0400 Subject: drm/amd/display: Move stream_enc to stream_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipes->stream_enc/pipes->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/ctx->stream_enc->/ctx->stream_res\.stream_enc->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe->stream_enc/pipe->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx->stream_enc/pipe_ctx->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[pipe_offset\]\.stream_enc/pipe_ctx\[pipe_offset\]\.stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[i\]->stream_enc/grouped_pipes\[i\]->stream_^Cs\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[0\]->stream_enc/grouped_pipes\[0\]->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[1\]->stream_enc/grouped_pipes\[1\]->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]->stream_enc/pipe_ctx\[i\]->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx_old->stream_enc/pipe_ctx_old->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_set\[j\]->stream_enc/pipe_set\[j\]->stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]\.stream_enc/pipe_ctx\[i\]\.stream_res\.stream_enc/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipes\[i\]\.stream_enc/pipes\[i\]\.stream_res\.stream_enc/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 16 ++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 72 +++++++++++----------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- 8 files changed, 58 insertions(+), 58 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 61c2a210c123..748e709c611f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -161,7 +161,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_res.stream_enc) { core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); /* build and update the info frame */ @@ -189,7 +189,7 @@ static bool stream_get_crtc_position(struct dc *dc, struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_res.stream_enc) { core_dc->hwss.get_position(&pipe, 1, &position); *v_pos = position.vertical_count; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 2c43edf2c7c4..6a3d2ad97d5d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1311,8 +1311,8 @@ static enum dc_status enable_link(struct pipe_ctx *pipe_ctx) /* un-mute audio */ /* TODO: audio should be per stream rather than per link */ - pipe_ctx->stream_enc->funcs->audio_mute_control( - pipe_ctx->stream_enc, false); + pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( + pipe_ctx->stream_res.stream_enc, false); } return status; @@ -1699,7 +1699,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; - struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; + struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; struct fixed31_32 avg_time_slots_per_mtp; struct fixed31_32 pbn; @@ -1718,7 +1718,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) &proposed_table, true)) { update_mst_stream_alloc_table( - link, pipe_ctx->stream_enc, &proposed_table); + link, pipe_ctx->stream_res.stream_enc, &proposed_table); } else dm_logger_write(link->ctx->logger, LOG_WARNING, @@ -1781,7 +1781,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; - struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; + struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0); uint8_t i; @@ -1808,7 +1808,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) false)) { update_mst_stream_alloc_table( - link, pipe_ctx->stream_enc, &proposed_table); + link, pipe_ctx->stream_res.stream_enc, &proposed_table); } else { dm_logger_write(link->ctx->logger, LOG_WARNING, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index eda25942aea0..3d296b1d118f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2464,7 +2464,7 @@ bool dc_link_dp_set_test_pattern( * MuteAudioEndpoint(pPathMode->pDisplayPath, true); */ /* Blank stream */ - pipes->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); + pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); } dp_set_hw_test_pattern(link, test_pattern, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index f2f57a75f864..7d52c6c7cf89 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -243,12 +243,12 @@ void dp_retrain_link_dp_test(struct dc_link *link, if (pipes[i].stream != NULL && pipes[i].stream->sink != NULL && pipes[i].stream->sink->link != NULL && - pipes[i].stream_enc != NULL && + pipes[i].stream_res.stream_enc != NULL && pipes[i].stream->sink->link == link) { dm_delay_in_microseconds(link->ctx, 100); - pipes[i].stream_enc->funcs->dp_blank( - pipes[i].stream_enc); + pipes[i].stream_res.stream_enc->funcs->dp_blank( + pipes[i].stream_res.stream_enc); /* disable any test pattern that might be active */ dp_set_hw_test_pattern(link, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 5326713bf3fb..13feff1003d8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -925,7 +925,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( int i; for (i = 0; i < MAX_PIPES; i++) { if (res_ctx->pipe_ctx[i].stream == stream && - res_ctx->pipe_ctx[i].stream_enc) { + res_ctx->pipe_ctx[i].stream_res.stream_enc) { return &res_ctx->pipe_ctx[i]; break; } @@ -1096,7 +1096,7 @@ bool resource_attach_surfaces_to_context( if (tail_pipe) { free_pipe->stream_res.tg = tail_pipe->stream_res.tg; free_pipe->stream_res.opp = tail_pipe->stream_res.opp; - free_pipe->stream_enc = tail_pipe->stream_enc; + free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; free_pipe->audio = tail_pipe->audio; free_pipe->clock_source = tail_pipe->clock_source; free_pipe->top_pipe = tail_pipe; @@ -1461,12 +1461,12 @@ enum dc_status resource_map_pool_resources( copy_pipe_ctx(old_pipe_ctx, pipe_ctx); /* Split pipe resource, do not acquire back end */ - if (!pipe_ctx->stream_enc) + if (!pipe_ctx->stream_res.stream_enc) continue; set_stream_engine_in_use( &context->res_ctx, pool, - pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc); /* Switch to dp clock source only if there is * no non dp stream that shares the same timing @@ -1503,16 +1503,16 @@ enum dc_status resource_map_pool_resources( pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; - pipe_ctx->stream_enc = + pipe_ctx->stream_res.stream_enc = find_first_free_match_stream_enc_for_link( &context->res_ctx, pool, stream); - if (!pipe_ctx->stream_enc) + if (!pipe_ctx->stream_res.stream_enc) return DC_NO_STREAM_ENG_RESOURCE; set_stream_engine_in_use( &context->res_ctx, pool, - pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc); /* TODO: Add check if ASIC support and EDID audio */ if (!stream->sink->converter_disable_audio && @@ -2382,7 +2382,7 @@ bool pipe_need_reprogram( && pipe_ctx_old->stream != pipe_ctx->stream) return true; - if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc) + if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) return true; if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1d7c7fb668be..48d151039fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -659,7 +659,7 @@ static enum dc_status bios_parser_crtc_source_select( struct bp_crtc_source_select crtc_source_select = {0}; const struct dc_sink *sink = pipe_ctx->stream->sink; - crtc_source_select.engine_id = pipe_ctx->stream_enc->id; + crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id; crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; /*TODO: Need to un-hardcode color depth, dp_audio and account for * the case where signal and sink signal is different (translator @@ -684,16 +684,16 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) { ASSERT(pipe_ctx->stream); - if (pipe_ctx->stream_enc == NULL) + if (pipe_ctx->stream_res.stream_enc == NULL) return; /* this is not root pipe */ if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( + pipe_ctx->stream_res.stream_enc, &pipe_ctx->encoder_info_frame); else if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->update_dp_info_packets( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( + pipe_ctx->stream_res.stream_enc, &pipe_ctx->encoder_info_frame); } @@ -731,7 +731,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) /* enable audio only within mode set */ if (pipe_ctx->audio != NULL) { if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); } /* For MST, there are multiply stream go to only one link. @@ -739,7 +739,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) * disconnect them during disable_stream * BY this, it is logic clean to separate stream and link */ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, - pipe_ctx->stream_enc->id, true); + pipe_ctx->stream_res.stream_enc->id, true); } @@ -752,11 +752,11 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->dp_audio_disable( - pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( + pipe_ctx->stream_res.stream_enc); else - pipe_ctx->stream_enc->funcs->hdmi_audio_disable( - pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( + pipe_ctx->stream_res.stream_enc); pipe_ctx->audio = NULL; @@ -768,24 +768,24 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) } if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( - pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( + pipe_ctx->stream_res.stream_enc); if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->stop_dp_info_packets( - pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( + pipe_ctx->stream_res.stream_enc); - pipe_ctx->stream_enc->funcs->audio_mute_control( - pipe_ctx->stream_enc, true); + pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( + pipe_ctx->stream_res.stream_enc, true); /* blank at encoder level */ if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); link->link_enc->funcs->connect_dig_be_to_fe( link->link_enc, - pipe_ctx->stream_enc->id, + pipe_ctx->stream_res.stream_enc->id, false); } @@ -799,14 +799,14 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; - pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); + pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); } void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) { - if (pipe_ctx != NULL && pipe_ctx->stream_enc != NULL) - pipe_ctx->stream_enc->funcs->set_avmute(pipe_ctx->stream_enc, enable); + if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) + pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); } static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) @@ -834,7 +834,7 @@ static void build_audio_output( struct audio_output *audio_output) { const struct dc_stream_state *stream = pipe_ctx->stream; - audio_output->engine_id = pipe_ctx->stream_enc->id; + audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -1071,8 +1071,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->stream->signal); if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) - pipe_ctx->stream_enc->funcs->setup_stereo_sync( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( + pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.tg->inst, stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); @@ -1084,21 +1084,21 @@ static enum dc_status apply_single_controller_ctx_to_hw( &stream->clamping); if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( + pipe_ctx->stream_res.stream_enc, &stream->timing, stream->output_color_space); if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute( + pipe_ctx->stream_res.stream_enc, &stream->timing, stream->phy_pix_clk, pipe_ctx->audio != NULL); if (dc_is_dvi_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( + pipe_ctx->stream_res.stream_enc, &stream->timing, (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? true : false); @@ -1860,13 +1860,13 @@ enum dc_status dce110_apply_ctx_to_hw( build_audio_output(pipe_ctx, &audio_output); if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_enc->funcs->dp_audio_setup( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( + pipe_ctx->stream_res.stream_enc, pipe_ctx->audio->inst, &pipe_ctx->stream->audio_info); else - pipe_ctx->stream_enc->funcs->hdmi_audio_setup( - pipe_ctx->stream_enc, + pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( + pipe_ctx->stream_res.stream_enc, pipe_ctx->audio->inst, &pipe_ctx->stream->audio_info, &audio_output.crtc_info); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 99ef0f25492c..16ac96358620 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -770,7 +770,7 @@ static void reset_back_end_for_pipe( { int i; - if (pipe_ctx->stream_enc == NULL) { + if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 488ade37e353..4d35c6d120a7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -155,6 +155,7 @@ struct resource_pool { struct stream_resource { struct output_pixel_processor *opp; struct timing_generator *tg; + struct stream_encoder *stream_enc; }; struct plane_resource { @@ -172,7 +173,6 @@ struct pipe_ctx { struct plane_resource plane_res; struct stream_resource stream_res; - struct stream_encoder *stream_enc; struct display_clock *dis_clk; struct clock_source *clock_source; -- cgit v1.2.3-59-g8ed1b From afaacef482759215681ad0a8c6a8b60cc7d29592 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 14:59:17 -0400 Subject: drm/amd/display: Move audio to stream_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipes->audio/pipes->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_with_clk_src->audio/pipe_with_clk_src->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/ctx->audio->/ctx->stream_res\.audio->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe->audio/pipe->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx->audio/pipe_ctx->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[pipe_offset\]\.audio/pipe_ctx\[pipe_offset\]\.stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[i\]->audio/grouped_pipes\[i\]->stream_^Cs\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[0\]->audio/grouped_pipes\[0\]->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[1\]->audio/grouped_pipes\[1\]->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]->audio/pipe_ctx\[i\]->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx_old->audio/pipe_ctx_old->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_set\[j\]->audio/pipe_set\[j\]->stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]\.audio/pipe_ctx\[i\]\.stream_res\.audio/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipes\[i\]\.audio/pipes\[i\]\.stream_res\.audio/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 12 ++++---- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 32 +++++++++++----------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +- 4 files changed, 25 insertions(+), 26 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 6a3d2ad97d5d..9665fc127fe2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1305,9 +1305,9 @@ static enum dc_status enable_link(struct pipe_ctx *pipe_ctx) break; } - if (pipe_ctx->audio && status == DC_OK) { + if (pipe_ctx->stream_res.audio && status == DC_OK) { /* notify audio driver for audio modes of monitor */ - pipe_ctx->audio->funcs->az_enable(pipe_ctx->audio); + pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); /* un-mute audio */ /* TODO: audio should be per stream rather than per link */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 13feff1003d8..5c1d3c568090 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1097,7 +1097,7 @@ bool resource_attach_surfaces_to_context( free_pipe->stream_res.tg = tail_pipe->stream_res.tg; free_pipe->stream_res.opp = tail_pipe->stream_res.opp; free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; - free_pipe->audio = tail_pipe->audio; + free_pipe->stream_res.audio = tail_pipe->stream_res.audio; free_pipe->clock_source = tail_pipe->clock_source; free_pipe->top_pipe = tail_pipe; tail_pipe->bottom_pipe = free_pipe; @@ -1481,7 +1481,7 @@ enum dc_status resource_map_pool_resources( pipe_ctx->clock_source); set_audio_in_use(&context->res_ctx, pool, - pipe_ctx->audio); + pipe_ctx->stream_res.audio); } } @@ -1518,7 +1518,7 @@ enum dc_status resource_map_pool_resources( if (!stream->sink->converter_disable_audio && dc_is_audio_capable_signal(pipe_ctx->stream->signal) && stream->audio_info.mode_count) { - pipe_ctx->audio = find_first_free_audio( + pipe_ctx->stream_res.audio = find_first_free_audio( &context->res_ctx, pool); /* @@ -1526,10 +1526,10 @@ enum dc_status resource_map_pool_resources( * There are asics which has number of audio * resources less then number of pipes */ - if (pipe_ctx->audio) + if (pipe_ctx->stream_res.audio) set_audio_in_use( &context->res_ctx, pool, - pipe_ctx->audio); + pipe_ctx->stream_res.audio); } context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; @@ -2375,7 +2375,7 @@ bool pipe_need_reprogram( if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) return true; - if (pipe_ctx_old->audio != pipe_ctx->audio) + if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) return true; if (pipe_ctx_old->clock_source != pipe_ctx->clock_source diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 48d151039fe8..ef5d496656e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -729,7 +729,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) tg->funcs->set_early_control(tg, early_control); /* enable audio only within mode set */ - if (pipe_ctx->audio != NULL) { + if (pipe_ctx->stream_res.audio != NULL) { if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); } @@ -748,8 +748,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; - if (pipe_ctx->audio) { - pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); + if (pipe_ctx->stream_res.audio) { + pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( @@ -758,7 +758,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( pipe_ctx->stream_res.stream_enc); - pipe_ctx->audio = NULL; + pipe_ctx->stream_res.audio = NULL; /* TODO: notify audio driver for if audio modes list changed * add audio mode list change flag */ @@ -1094,7 +1094,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->stream_res.stream_enc, &stream->timing, stream->phy_pix_clk, - pipe_ctx->audio != NULL); + pipe_ctx->stream_res.audio != NULL); if (dc_is_dvi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( @@ -1792,13 +1792,13 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) continue; - if (pipe_ctx->audio != NULL) { + if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output; build_audio_output(pipe_ctx, &audio_output); - pipe_ctx->audio->funcs->wall_dto_setup( - pipe_ctx->audio, + pipe_ctx->stream_res.audio->funcs->wall_dto_setup( + pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &audio_output.pll_info); @@ -1820,13 +1820,13 @@ enum dc_status dce110_apply_ctx_to_hw( if (!dc_is_dp_signal(pipe_ctx->stream->signal)) continue; - if (pipe_ctx->audio != NULL) { + if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output; build_audio_output(pipe_ctx, &audio_output); - pipe_ctx->audio->funcs->wall_dto_setup( - pipe_ctx->audio, + pipe_ctx->stream_res.audio->funcs->wall_dto_setup( + pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &audio_output.pll_info); @@ -1853,7 +1853,7 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->top_pipe) continue; - if (context->res_ctx.pipe_ctx[i].audio != NULL) { + if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) { struct audio_output audio_output; @@ -1862,17 +1862,17 @@ enum dc_status dce110_apply_ctx_to_hw( if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( pipe_ctx->stream_res.stream_enc, - pipe_ctx->audio->inst, + pipe_ctx->stream_res.audio->inst, &pipe_ctx->stream->audio_info); else pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( pipe_ctx->stream_res.stream_enc, - pipe_ctx->audio->inst, + pipe_ctx->stream_res.audio->inst, &pipe_ctx->stream->audio_info, &audio_output.crtc_info); - pipe_ctx->audio->funcs->az_configure( - pipe_ctx->audio, + pipe_ctx->stream_res.audio->funcs->az_configure( + pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &pipe_ctx->stream->audio_info); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 4d35c6d120a7..6f09653ac2cb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -156,6 +156,7 @@ struct stream_resource { struct output_pixel_processor *opp; struct timing_generator *tg; struct stream_encoder *stream_enc; + struct audio *audio; }; struct plane_resource { @@ -176,8 +177,6 @@ struct pipe_ctx { struct display_clock *dis_clk; struct clock_source *clock_source; - struct audio *audio; - struct pixel_clk_params pix_clk_params; struct pll_settings pll_settings; -- cgit v1.2.3-59-g8ed1b From 10688217e3af3ec73892139bed3d23a6e1170a14 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 15:17:43 -0400 Subject: drm/amd/display: Move pix_clk_params into stream_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipes->pix_clk_params/pipes->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_with_clk_src->pix_clk_params/pipe_with_clk_src->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/ctx->pix_clk_params->/ctx->stream_res\.pix_clk_params->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe->pix_clk_params/pipe->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx->pix_clk_params/pipe_ctx->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[pipe_offset\]\.pix_clk_params/pipe_ctx\[pipe_offset\]\.stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[i\]->pix_clk_params/grouped_pipes\[i\]->stream_^Cs\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[0\]->pix_clk_params/grouped_pipes\[0\]->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[1\]->pix_clk_params/grouped_pipes\[1\]->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]->pix_clk_params/pipe_ctx\[i\]->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx_old->pix_clk_params/pipe_ctx_old->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_set\[j\]->pix_clk_params/pipe_set\[j\]->stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]\.pix_clk_params/pipe_ctx\[i\]\.stream_res\.pix_clk_params/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipes\[i\]\.pix_clk_params/pipes\[i\]\.stream_res\.pix_clk_params/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 ++-- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 14 +++++++------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 ++- 7 files changed, 19 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 9665fc127fe2..1279eb1dfc2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1620,8 +1620,8 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) uint32_t numerator; uint32_t denominator; - bpc = get_color_depth(pipe_ctx->pix_clk_params.color_depth); - kbps = pipe_ctx->pix_clk_params.requested_pix_clk * bpc * 3; + bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth); + kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3; /* * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 7d52c6c7cf89..822568767f2d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -77,11 +77,11 @@ void dp_enable_link_phy( if (pipes[i].clock_source != NULL && pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { pipes[i].clock_source = dp_cs; - pipes[i].pix_clk_params.requested_pix_clk = + pipes[i].stream_res.pix_clk_params.requested_pix_clk = pipes[i].stream->timing.pix_clk_khz; pipes[i].clock_source->funcs->program_pix_clk( pipes[i].clock_source, - &pipes[i].pix_clk_params, + &pipes[i].stream_res.pix_clk_params, &pipes[i].pll_settings); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ef5d496656e5..93161a92a427 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -870,20 +870,20 @@ static void build_audio_output( stream->timing.display_color_depth; audio_output->crtc_info.requested_pixel_clock = - pipe_ctx->pix_clk_params.requested_pix_clk; + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; audio_output->crtc_info.calculated_pixel_clock = - pipe_ctx->pix_clk_params.requested_pix_clk; + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; /*for HDMI, audio ACR is with deep color ratio factor*/ if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && audio_output->crtc_info.requested_pixel_clock == stream->timing.pix_clk_khz) { - if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { audio_output->crtc_info.requested_pixel_clock = audio_output->crtc_info.requested_pixel_clock/2; audio_output->crtc_info.calculated_pixel_clock = - pipe_ctx->pix_clk_params.requested_pix_clk/2; + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2; } } @@ -1003,7 +1003,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx->clock_source, - &pipe_ctx->pix_clk_params, + &pipe_ctx->stream_res.pix_clk_params, &pipe_ctx->pll_settings)) { BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; @@ -1425,9 +1425,9 @@ static uint32_t get_max_pixel_clock_for_all_paths( if (pipe_ctx->top_pipe) continue; - if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) + if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk) max_pix_clk = - pipe_ctx->pix_clk_params.requested_pix_clk; + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; } if (max_pix_clk == 0) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 94058ee16029..c677f98c3516 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -748,10 +748,10 @@ static void get_pixel_clock_parameters( enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); + get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx->clock_source, - &pipe_ctx->pix_clk_params, + &pipe_ctx->stream_res.pix_clk_params, &pipe_ctx->pll_settings); resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 16ac96358620..e69839802889 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -703,7 +703,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( if (false == pipe_ctx->clock_source->funcs->program_pix_clk( pipe_ctx->clock_source, - &pipe_ctx->pix_clk_params, + &pipe_ctx->stream_res.pix_clk_params, &pipe_ctx->pll_settings)) { BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; @@ -1910,7 +1910,7 @@ static void update_dchubp_dpp( enable_dppclk( dc->hwseq, pipe_ctx->pipe_idx, - pipe_ctx->pix_clk_params.requested_pix_clk, + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); dc->current_context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index bb9a42d0a147..ff2dcb7a491d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -806,11 +806,11 @@ static void build_clamping_params(struct dc_stream_state *stream) static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); + get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx->clock_source, - &pipe_ctx->pix_clk_params, + &pipe_ctx->stream_res.pix_clk_params, &pipe_ctx->pll_settings); pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 6f09653ac2cb..968835191da8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -157,6 +157,8 @@ struct stream_resource { struct timing_generator *tg; struct stream_encoder *stream_enc; struct audio *audio; + + struct pixel_clk_params pix_clk_params; }; struct plane_resource { @@ -177,7 +179,6 @@ struct pipe_ctx { struct display_clock *dis_clk; struct clock_source *clock_source; - struct pixel_clk_params pix_clk_params; struct pll_settings pll_settings; /*fmt*/ -- cgit v1.2.3-59-g8ed1b From 96c50c0d0cead772001fd4ab1861594c059e7e0f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sun, 30 Jul 2017 15:58:26 -0400 Subject: drm/amd/display: Move encoder_info_frame to stream_res find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipes->encoder_info_frame/pipes->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_with_clk_src->encoder_info_frame/pipe_with_clk_src->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/ctx->encoder_info_frame->/ctx->stream_res\.encoder_info_frame->/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe->encoder_info_frame/pipe->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/pipe_ctx->encoder_info_frame/pipe_ctx->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[pipe_offset\]\.encoder_info_frame/pipe_ctx\[pipe_offset\]\.stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[i\]->encoder_info_frame/grouped_pipes\[i\]->stream_^Cs\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[0\]->encoder_info_frame/grouped_pipes\[0\]->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/grouped_pipes\[1\]->encoder_info_frame/grouped_pipes\[1\]->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]->encoder_info_frame/pipe_ctx\[i\]->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx_old->encoder_info_frame/pipe_ctx_old->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_set\[j\]->encoder_info_frame/pipe_set\[j\]->stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipe_ctx\[i\]\.encoder_info_frame/pipe_ctx\[i\]\.stream_res\.encoder_info_frame/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i \ 's/pipes\[i\]\.encoder_info_frame/pipes\[i\]\.stream_res\.encoder_info_frame/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 +--- 3 files changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 5c1d3c568090..30237f049c99 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2267,7 +2267,7 @@ struct clock_source *dc_resource_find_first_free_pll( void resource_build_info_frame(struct pipe_ctx *pipe_ctx) { enum signal_type signal = SIGNAL_TYPE_NONE; - struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame; + struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; /* default all packets to invalid */ info->avi.valid = false; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 93161a92a427..d3368a8bd1d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -690,11 +690,11 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( pipe_ctx->stream_res.stream_enc, - &pipe_ctx->encoder_info_frame); + &pipe_ctx->stream_res.encoder_info_frame); else if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( pipe_ctx->stream_res.stream_enc, - &pipe_ctx->encoder_info_frame); + &pipe_ctx->stream_res.encoder_info_frame); } void dce110_enable_stream(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 968835191da8..b3005629ab21 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -159,6 +159,7 @@ struct stream_resource { struct audio *audio; struct pixel_clk_params pix_clk_params; + struct encoder_info_frame encoder_info_frame; }; struct plane_resource { @@ -181,9 +182,6 @@ struct pipe_ctx { struct pll_settings pll_settings; - /*fmt*/ - struct encoder_info_frame encoder_info_frame; - uint8_t pipe_idx; struct pipe_ctx *top_pipe; -- cgit v1.2.3-59-g8ed1b From 3e9ad6164b98f82ff4b191980c502f09fee4deef Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Thu, 3 Aug 2017 00:22:25 -0400 Subject: drm/amd/display: add programming for 0 plane case Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 45 +++++++++++++--------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 17 ++++++-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 29 ++++++++++---- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +- 4 files changed, 64 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 748e709c611f..f305780c36ce 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -978,10 +978,10 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].plane_count; j++) { - const struct dc_plane_state *plane_state = - context->stream_status[i].plane_states[j]; - - core_dc->hwss.apply_ctx_for_surface(core_dc, plane_state, context); + core_dc->hwss.apply_ctx_for_surface( + core_dc, context->streams[i], + context->stream_status[i].plane_count, + context); /* * enable stereo @@ -1391,6 +1391,21 @@ enum surface_update_type dc_check_update_surfaces_for_stream( return overall_type; } +static struct dc_stream_status *stream_get_status( + struct validate_context *ctx, + struct dc_stream_state *stream) +{ + uint8_t i; + + for (i = 0; i < ctx->stream_count; i++) { + if (stream == ctx->streams[i]) { + return &ctx->stream_status[i]; + } + } + + return NULL; +} + enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_planes_and_stream(struct dc *dc, @@ -1405,16 +1420,6 @@ void dc_update_planes_and_stream(struct dc *dc, const struct dc_stream_status *stream_status; struct dc_context *dc_ctx = core_dc->ctx; - /* Currently this function do not result in any HW programming - * when called with 0 surface. But proceeding will cause - * SW state to be updated in validate_context. So we might as - * well make it not do anything at all until the hw programming - * is implemented properly to handle 0 surface case. - * TODO: fix hw programming then remove this early return - */ - if (surface_count == 0) - return; - stream_status = dc_stream_get_status(stream); ASSERT(stream_status); @@ -1595,7 +1600,7 @@ void dc_update_planes_and_stream(struct dc *dc, } if (surface_count == 0) - core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); + core_dc->hwss.apply_ctx_for_surface(core_dc, stream, surface_count, context); /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { @@ -1625,12 +1630,16 @@ void dc_update_planes_and_stream(struct dc *dc, bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; + if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; - if (!pipe_ctx->top_pipe) + if (!pipe_ctx->top_pipe && pipe_ctx->stream) { + struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); + core_dc->hwss.apply_ctx_for_surface( - core_dc, pipe_ctx->plane_state, context); + core_dc, pipe_ctx->stream, stream_status->plane_count, context); + } /* TODO: this is a hack w/a for switching from mpo to pipe split */ dc_stream_set_cursor_position(pipe_ctx->stream, &position); @@ -1653,7 +1662,7 @@ void dc_update_planes_and_stream(struct dc *dc, if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( - core_dc, plane_state, context); + core_dc, stream, surface_count, context); for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d3368a8bd1d5..59925723271e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2614,18 +2614,27 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *plane_state, + const struct dc_stream_state *stream, + int num_planes, struct validate_context *context) { - int i; + int i, be_idx; - if (!plane_state) + if (num_planes == 0) return; + be_idx = -1; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (stream == context->res_ctx.pipe_ctx[i].stream) { + be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; + break; + } + } + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->plane_state != plane_state) + if (pipe_ctx->stream == stream) continue; dce110_program_front_end_for_pipe(dc, pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 114dd279fe47..948aaeb73122 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2151,7 +2151,8 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *plane_state, + const struct dc_stream_state *stream, + int num_planes, struct validate_context *context) { int i, be_idx; @@ -2159,12 +2160,26 @@ static void dcn10_apply_ctx_for_surface( if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); - if (!plane_state) - return; - - for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++) - if (plane_state == context->res_ctx.pipe_ctx[be_idx].plane_state) + be_idx = -1; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (stream == context->res_ctx.pipe_ctx[i].stream) { + be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; break; + } + } + + ASSERT(be_idx != -1); + + if (num_planes == 0) { + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *old_pipe_ctx = + &dc->current_context->res_ctx.pipe_ctx[i]; + + if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) + dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx); + } + return; + } /* reset unused mpcc */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -2229,7 +2244,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->plane_state != plane_state) + if (pipe_ctx->stream != stream) continue; /* looking for top pipe to program */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 5d075f93b4b9..7689e372b9da 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,8 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_plane_state *plane_state, + const struct dc_stream_state *stream, + int num_planes, struct validate_context *context); void (*set_plane_config)( -- cgit v1.2.3-59-g8ed1b From f0c4d9977ae215859ff13304ef0fc02a8b779478 Mon Sep 17 00:00:00 2001 From: Corbin McElhanney Date: Thu, 3 Aug 2017 14:20:14 -0400 Subject: drm/amd/display: fix HDMI 12bits last two bits are zero issue (FF-158) -[FF N-1] HDMI Deep Color Mode incorrect bit depth: FMT_DYNAMIC_EXP_EN is being reset to 0 Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 +++++++++++------ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 3 ++- 2 files changed, 13 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 59925723271e..c29e51409286 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1044,14 +1044,14 @@ static enum dc_status apply_single_controller_ctx_to_hw( /* */ dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); - pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( - pipe_ctx->stream_res.opp, - COLOR_SPACE_YCBCR601, - stream->timing.display_color_depth, - pipe_ctx->stream->signal); - /* FPGA does not program backend */ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, + COLOR_SPACE_YCBCR601, + stream->timing.display_color_depth, + pipe_ctx->stream->signal); + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx->stream_res.opp, &stream->bit_depth_params, @@ -1064,6 +1064,11 @@ static enum dc_status apply_single_controller_ctx_to_hw( BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; } + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, + COLOR_SPACE_YCBCR601, + stream->timing.display_color_depth, + pipe_ctx->stream->signal); if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) stream->sink->link->link_enc->funcs->setup( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 38d15f7c2a88..8048782ac599 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -240,7 +240,8 @@ static void oppn10_set_dyn_expansion( /*01 - 8-bit -> 12-bit dynamic expansion*/ if (signal == SIGNAL_TYPE_HDMI_TYPE_A || signal == SIGNAL_TYPE_DISPLAY_PORT || - signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { + signal == SIGNAL_TYPE_DISPLAY_PORT_MST || + signal == SIGNAL_TYPE_VIRTUAL) { switch (color_dpth) { case COLOR_DEPTH_888: REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, -- cgit v1.2.3-59-g8ed1b From a2607aef3d0210859d4e9cae6bba7e134ec720d8 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 8 Aug 2017 11:35:10 -0400 Subject: drm/amd/display: Fix regression in dce110_apply_ctx_for_surfaces Caused by "add programming for 0 plane case" which was tested on DCN but not on DCE. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c29e51409286..5b46e776b9b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2639,7 +2639,7 @@ static void dce110_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->stream == stream) + if (pipe_ctx->stream != stream) continue; dce110_program_front_end_for_pipe(dc, pipe_ctx); -- cgit v1.2.3-59-g8ed1b From 5394eb82133b6e9897b9d6e5aed13c08dd71d8c2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 10 Aug 2017 14:22:21 -0400 Subject: drm/amd/display/dc: Make dce110_validate_bandwidth static (v2) Not used outside of the dce110_resource.c. v2: make a bunch of other functions static as well. Signed-off-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index c677f98c3516..a7f30dcc906c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -565,7 +565,7 @@ static const struct encoder_feature_support link_enc_feature = { .flags.bits.IS_YCBCR_CAPABLE = true }; -struct link_encoder *dce110_link_encoder_create( +static struct link_encoder *dce110_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = @@ -813,7 +813,7 @@ static enum dc_status build_mapped_resource( return DC_OK; } -bool dce110_validate_bandwidth( +static bool dce110_validate_bandwidth( const struct core_dc *dc, struct validate_context *context) { @@ -927,7 +927,7 @@ static bool dce110_validate_surface_sets( return true; } -enum dc_status dce110_validate_with_context( +static enum dc_status dce110_validate_with_context( const struct core_dc *dc, const struct dc_validation_set set[], int set_count, @@ -971,7 +971,7 @@ enum dc_status dce110_validate_with_context( return result; } -enum dc_status dce110_validate_guaranteed( +static enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) -- cgit v1.2.3-59-g8ed1b From 77a4ea53fd89ccf823e77cc31cea808a3589f732 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Wed, 2 Aug 2017 16:56:03 -0400 Subject: drm/amd/display: change bw_dceip and bw_vbios into pointers -Change bw_calcs_dceip into pointer -Change bw_calcs_vbios into pointer This is needed for flattening of core_dc into dc, as without this the diags build fails Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 34 +++++++-------- .../drm/amd/display/dc/dce112/dce112_resource.c | 50 +++++++++++----------- .../drm/amd/display/dc/dce120/dce120_resource.c | 24 +++++------ drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 4 +- 6 files changed, 83 insertions(+), 57 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index aeed95a5d097..477024c467e6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -433,6 +433,13 @@ static void destruct(struct core_dc *dc) dm_free(dc->ctx); dc->ctx = NULL; + + dm_free(dc->bw_vbios); + dc->bw_vbios = NULL; + + dm_free(dc->bw_dceip); + dc->bw_dceip = NULL; + } static bool construct(struct core_dc *dc, @@ -440,8 +447,25 @@ static bool construct(struct core_dc *dc, { struct dal_logger *logger; struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); + struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip)); + struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios)); + enum dce_version dc_version = DCE_VERSION_UNKNOWN; + if (!dc_dceip) { + dm_error("%s: failed to create dceip\n", __func__); + goto dceip_fail; + } + + dc->bw_dceip = dc_dceip; + + if (!dc_vbios) { + dm_error("%s: failed to create vbios\n", __func__); + goto vbios_fail; + } + + dc->bw_vbios = dc_vbios; + if (!dc_ctx) { dm_error("%s: failed to create ctx\n", __func__); goto ctx_fail; @@ -544,6 +568,8 @@ bios_fail: logger_fail: val_ctx_fail: ctx_fail: +dceip_fail: +vbios_fail: destruct(dc); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5b46e776b9b7..ccde7c80d658 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1264,7 +1264,7 @@ void dce110_set_displaymarks( continue; total_dest_line_time_ns = compute_pstate_blackout_duration( - dc->bw_vbios.blackout_duration, pipe_ctx->stream); + dc->bw_vbios->blackout_duration, pipe_ctx->stream); pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( pipe_ctx->plane_res.mi, context->bw.dce.nbp_state_change_wm_ns[num_pipes], diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index a7f30dcc906c..56be84ce5a0d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -826,8 +826,8 @@ static bool dce110_validate_bandwidth( if (bw_calcs( dc->ctx, - &dc->bw_dceip, - &dc->bw_vbios, + dc->bw_dceip, + dc->bw_vbios, context->res_ctx.pipe_ctx, dc->res_pool->pipe_count, &context->bw.dce)) @@ -1127,21 +1127,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) DM_PP_CLOCK_TYPE_ENGINE_CLK, &clks); /* convert all the clock fro kHz to fix point mHz */ - dc->bw_vbios.high_sclk = bw_frc_to_fixed( + dc->bw_vbios->high_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels-1], 1000); - dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels/8], 1000); - dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*2/8], 1000); - dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*3/8], 1000); - dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*4/8], 1000); - dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*5/8], 1000); - dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*6/8], 1000); - dc->bw_vbios.low_sclk = bw_frc_to_fixed( + dc->bw_vbios->low_sclk = bw_frc_to_fixed( clks.clocks_in_khz[0], 1000); dc->sclk_lvls = clks; @@ -1150,11 +1150,11 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) dc->ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clks); - dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed( + dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels-1], 1000); - dc->bw_vbios.mid_voltage_max_dispclk = bw_frc_to_fixed( + dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels>>1], 1000); - dc->bw_vbios.low_voltage_max_dispclk = bw_frc_to_fixed( + dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( clks.clocks_in_khz[0], 1000); /*do memory clock*/ @@ -1163,12 +1163,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) DM_PP_CLOCK_TYPE_MEMORY_CLK, &clks); - dc->bw_vbios.low_yclk = bw_frc_to_fixed( + dc->bw_vbios->low_yclk = bw_frc_to_fixed( clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.mid_yclk = bw_frc_to_fixed( + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.high_yclk = bw_frc_to_fixed( + dc->bw_vbios->high_yclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1000); } @@ -1353,7 +1353,7 @@ static bool construct( dc->public.caps.max_planes = pool->base.pipe_count; - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); + bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 420434d7283e..d6e58a25f3d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -771,8 +771,8 @@ bool dce112_validate_bandwidth( if (bw_calcs( dc->ctx, - &dc->bw_dceip, - &dc->bw_vbios, + dc->bw_dceip, + dc->bw_vbios, context->res_ctx.pipe_ctx, dc->res_pool->pipe_count, &context->bw.dce)) @@ -1018,21 +1018,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) DM_PP_CLOCK_TYPE_ENGINE_CLK, &clks); /* convert all the clock fro kHz to fix point mHz */ - dc->bw_vbios.high_sclk = bw_frc_to_fixed( + dc->bw_vbios->high_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels-1], 1000); - dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels/8], 1000); - dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*2/8], 1000); - dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*3/8], 1000); - dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*4/8], 1000); - dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*5/8], 1000); - dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels*6/8], 1000); - dc->bw_vbios.low_sclk = bw_frc_to_fixed( + dc->bw_vbios->low_sclk = bw_frc_to_fixed( clks.clocks_in_khz[0], 1000); /*do memory clock*/ @@ -1041,12 +1041,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) DM_PP_CLOCK_TYPE_MEMORY_CLK, &clks); - dc->bw_vbios.low_yclk = bw_frc_to_fixed( + dc->bw_vbios->low_yclk = bw_frc_to_fixed( clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.mid_yclk = bw_frc_to_fixed( + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.high_yclk = bw_frc_to_fixed( + dc->bw_vbios->high_yclk = bw_frc_to_fixed( clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1000); @@ -1054,21 +1054,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) } /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ - dc->bw_vbios.high_sclk = bw_frc_to_fixed( + dc->bw_vbios->high_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); - dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); - dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); - dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); - dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); - dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); - dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); - dc->bw_vbios.low_sclk = bw_frc_to_fixed( + dc->bw_vbios->low_sclk = bw_frc_to_fixed( eng_clks.data[0].clocks_in_khz, 1000); /*do memory clock*/ @@ -1082,12 +1082,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): * YCLK = UMACLK*m_memoryTypeMultiplier */ - dc->bw_vbios.low_yclk = bw_frc_to_fixed( + dc->bw_vbios->low_yclk = bw_frc_to_fixed( mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.mid_yclk = bw_frc_to_fixed( + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.high_yclk = bw_frc_to_fixed( + dc->bw_vbios->high_yclk = bw_frc_to_fixed( mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); @@ -1325,7 +1325,7 @@ static bool construct( if (!dce112_hw_sequencer_construct(dc)) goto res_create_fail; - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); + bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index d4e962756fbb..562ae2205a90 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -729,21 +729,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) } /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ - dc->bw_vbios.high_sclk = bw_frc_to_fixed( + dc->bw_vbios->high_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); - dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); - dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); - dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); - dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); - dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); - dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); - dc->bw_vbios.low_sclk = bw_frc_to_fixed( + dc->bw_vbios->low_sclk = bw_frc_to_fixed( eng_clks.data[0].clocks_in_khz, 1000); /*do memory clock*/ @@ -770,12 +770,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): * YCLK = UMACLK*m_memoryTypeMultiplier */ - dc->bw_vbios.low_yclk = bw_frc_to_fixed( + dc->bw_vbios->low_yclk = bw_frc_to_fixed( mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.mid_yclk = bw_frc_to_fixed( + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.high_yclk = bw_frc_to_fixed( + dc->bw_vbios->high_yclk = bw_frc_to_fixed( mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); @@ -984,7 +984,7 @@ static bool construct( dc->public.caps.max_planes = pool->base.pipe_count; - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); + bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index 1ecb54603e17..982f7170f5d2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -29,8 +29,8 @@ struct core_dc { struct dm_pp_clock_levels sclk_lvls; /* Inputs into BW and WM calculations. */ - struct bw_calcs_dceip bw_dceip; - struct bw_calcs_vbios bw_vbios; + struct bw_calcs_dceip *bw_dceip; + struct bw_calcs_vbios *bw_vbios; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 struct dcn_soc_bounding_box dcn_soc; struct dcn_ip_params dcn_ip; -- cgit v1.2.3-59-g8ed1b From fb3466a450cc4684654367ae2f47fc3fc7846574 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 1 Aug 2017 15:00:25 -0400 Subject: drm/amd/display: Flattening core_dc to dc -Flattening core_dc to dc Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 73 +++++----- drivers/gpu/drm/amd/display/dc/core/dc.c | 162 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 20 +-- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 10 +- drivers/gpu/drm/amd/display/dc/dc.h | 71 +++++++-- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 5 +- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 6 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 22 +-- .../drm/amd/display/dc/dce100/dce100_resource.h | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 72 ++++----- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 26 ++-- .../drm/amd/display/dc/dce110/dce110_resource.h | 4 +- .../amd/display/dc/dce112/dce112_hw_sequencer.c | 5 +- .../amd/display/dc/dce112/dce112_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 26 ++-- .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- .../amd/display/dc/dce120/dce120_hw_sequencer.c | 5 +- .../amd/display/dc/dce120/dce120_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 18 +-- .../drm/amd/display/dc/dce120/dce120_resource.h | 4 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 5 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 46 +++--- .../gpu/drm/amd/display/dc/dce80/dce80_resource.h | 8 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 1 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 108 +++++++------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 34 ++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 55 ------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 +- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 12 +- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 50 ++++--- drivers/gpu/drm/amd/display/dc/inc/resource.h | 15 +- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 6 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 1 - .../gpu/drm/amd/display/include/logger_interface.h | 10 +- .../drm/amd/display/modules/freesync/freesync.c | 11 +- 51 files changed, 507 insertions(+), 527 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/core_dc.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6fb1b9a91993..f0dfd3c3c12c 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -27,7 +27,6 @@ #include "dcn_calcs.h" #include "dcn_calc_auto.h" #include "dc.h" -#include "core_dc.h" #include "dal_asic_id.h" #include "resource.h" @@ -399,7 +398,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } static void dcn_bw_calc_rq_dlg_ttu( - const struct core_dc *dc, + const struct dc *dc, const struct dcn_bw_internal_vars *v, struct pipe_ctx *pipe, int in_idx) @@ -674,45 +673,45 @@ static void calc_wm_sets_and_perf_params( context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; } -static bool dcn_bw_apply_registry_override(struct core_dc *dc) +static bool dcn_bw_apply_registry_override(struct dc *dc) { bool updated = false; kernel_fpu_begin(); - if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns - && dc->public.debug.sr_exit_time_ns) { + if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns + && dc->debug.sr_exit_time_ns) { updated = true; - dc->dcn_soc->sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0; + dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; } if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) - != dc->public.debug.sr_enter_plus_exit_time_ns - && dc->public.debug.sr_enter_plus_exit_time_ns) { + != dc->debug.sr_enter_plus_exit_time_ns + && dc->debug.sr_enter_plus_exit_time_ns) { updated = true; dc->dcn_soc->sr_enter_plus_exit_time = - dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0; + dc->debug.sr_enter_plus_exit_time_ns / 1000.0; } - if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->public.debug.urgent_latency_ns - && dc->public.debug.urgent_latency_ns) { + if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns + && dc->debug.urgent_latency_ns) { updated = true; - dc->dcn_soc->urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0; + dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; } if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) - != dc->public.debug.percent_of_ideal_drambw - && dc->public.debug.percent_of_ideal_drambw) { + != dc->debug.percent_of_ideal_drambw + && dc->debug.percent_of_ideal_drambw) { updated = true; dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = - dc->public.debug.percent_of_ideal_drambw; + dc->debug.percent_of_ideal_drambw; } if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) - != dc->public.debug.dram_clock_change_latency_ns - && dc->public.debug.dram_clock_change_latency_ns) { + != dc->debug.dram_clock_change_latency_ns + && dc->debug.dram_clock_change_latency_ns) { updated = true; dc->dcn_soc->dram_clock_change_latency = - dc->public.debug.dram_clock_change_latency_ns / 1000.0; + dc->debug.dram_clock_change_latency_ns / 1000.0; } kernel_fpu_end(); @@ -720,7 +719,7 @@ static bool dcn_bw_apply_registry_override(struct core_dc *dc) } bool dcn_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { const struct resource_pool *pool = dc->res_pool; @@ -730,8 +729,8 @@ bool dcn_validate_bandwidth( bool bw_limit_pass; float bw_limit; - if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) - dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); + if (dcn_bw_apply_registry_override(dc)) + dcn_bw_sync_calcs_and_dml(dc); memset(v, 0, sizeof(*v)); kernel_fpu_begin(); @@ -850,7 +849,7 @@ bool dcn_validate_bandwidth( v->phyclk_per_state[1] = v->phyclkv_mid0p72; v->phyclk_per_state[0] = v->phyclkv_min0p65; - if (dc->public.debug.disable_pipe_split) { + if (dc->debug.disable_pipe_split) { v->max_dispclk[0] = v->max_dppclk_vmin0p65; } @@ -982,15 +981,15 @@ bool dcn_validate_bandwidth( mode_support_and_system_configuration(v); if (v->voltage_level == 0 && - (dc->public.debug.sr_exit_time_dpm0_ns - || dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) { - struct core_dc *dc_core = DC_TO_CORE(&dc->public); + (dc->debug.sr_exit_time_dpm0_ns + || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { + struct dc *dc_core = dc; - if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns) + if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) v->sr_enter_plus_exit_time = - dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; - if (dc->public.debug.sr_exit_time_dpm0_ns) - v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f; + dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; + if (dc->debug.sr_exit_time_dpm0_ns) + v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; mode_support_and_system_configuration(v); @@ -1020,7 +1019,7 @@ bool dcn_validate_bandwidth( context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000); context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000); - if (dc->public.debug.max_disp_clk == true) + if (dc->debug.max_disp_clk == true) context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; @@ -1109,13 +1108,13 @@ bool dcn_validate_bandwidth( input_idx++; } - if (dc->public.debug.use_dml_wm) + if (dc->debug.use_dml_wm) dcn_dml_wm_override(v, (struct display_mode_lib *) &dc->dml, context, pool); } if (v->voltage_level == 0) { - struct core_dc *dc_core = DC_TO_CORE(&dc->public); + struct dc *dc_core = dc; dc_core->dml.soc.sr_enter_plus_exit_time_us = dc_core->dcn_soc->sr_enter_plus_exit_time; @@ -1138,7 +1137,7 @@ bool dcn_validate_bandwidth( } unsigned int dcn_find_normalized_clock_vdd_Level( - const struct core_dc *dc, + const struct dc *dc, enum dm_pp_clock_type clocks_type, int clocks_in_khz) { @@ -1228,7 +1227,7 @@ unsigned int dcn_find_normalized_clock_vdd_Level( } unsigned int dcn_find_dcfclk_suits_all( - const struct core_dc *dc, + const struct dc *dc, struct clocks_value *clocks) { unsigned vdd_level, vdd_level_temp; @@ -1270,7 +1269,7 @@ unsigned int dcn_find_dcfclk_suits_all( return dcf_clk; } -void dcn_bw_update_from_pplib(struct core_dc *dc) +void dcn_bw_update_from_pplib(struct dc *dc) { struct dc_context *ctx = dc->ctx; struct dm_pp_clock_levels_with_voltage clks = {0}; @@ -1310,7 +1309,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc) kernel_fpu_end(); } -void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) +void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) { struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0}; int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz, @@ -1388,7 +1387,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges); } -void dcn_bw_sync_calcs_and_dml(struct core_dc *dc) +void dcn_bw_sync_calcs_and_dml(struct dc *dc) { kernel_fpu_begin(); dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 40d65b758994..44c7b52e4a00 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -35,7 +35,6 @@ #include "clock_source.h" #include "dc_bios_types.h" -#include "dce_calcs.h" #include "bios_parser_interface.h" #include "include/irq_service_interface.h" #include "transform.h" @@ -52,7 +51,7 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static void destroy_links(struct core_dc *dc) +static void destroy_links(struct dc *dc) { uint32_t i; @@ -63,7 +62,7 @@ static void destroy_links(struct core_dc *dc) } static bool create_links( - struct core_dc *dc, + struct dc *dc, uint32_t num_virtual_links) { int i; @@ -153,7 +152,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, int vmin, int vmax) { /* TODO: Support multiple streams */ - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -179,7 +178,7 @@ static bool stream_get_crtc_position(struct dc *dc, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -202,7 +201,7 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -220,7 +219,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -245,7 +244,7 @@ static void set_static_screen_events(struct dc *dc, int num_streams, const struct dc_static_screen_events *events) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; int j = 0; struct pipe_ctx *pipes_affected[MAX_PIPES]; @@ -270,7 +269,7 @@ static void set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; for (i = 0; i < core_dc->link_count; i++) { @@ -288,7 +287,7 @@ static void perform_link_training(struct dc *dc, struct dc_link_settings *link_setting, bool skip_video_pattern) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; for (i = 0; i < core_dc->link_count; i++) @@ -369,48 +368,48 @@ void set_dither_option(struct dc_stream_state *stream, opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); } -static void allocate_dc_stream_funcs(struct core_dc *core_dc) +static void allocate_dc_stream_funcs(struct dc *core_dc) { if (core_dc->hwss.set_drr != NULL) { - core_dc->public.stream_funcs.adjust_vmin_vmax = + core_dc->stream_funcs.adjust_vmin_vmax = stream_adjust_vmin_vmax; } - core_dc->public.stream_funcs.set_static_screen_events = + core_dc->stream_funcs.set_static_screen_events = set_static_screen_events; - core_dc->public.stream_funcs.get_crtc_position = + core_dc->stream_funcs.get_crtc_position = stream_get_crtc_position; - core_dc->public.stream_funcs.set_gamut_remap = + core_dc->stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->public.stream_funcs.program_csc_matrix = + core_dc->stream_funcs.program_csc_matrix = program_csc_matrix; - core_dc->public.stream_funcs.set_dither_option = + core_dc->stream_funcs.set_dither_option = set_dither_option; - core_dc->public.link_funcs.set_drive_settings = + core_dc->link_funcs.set_drive_settings = set_drive_settings; - core_dc->public.link_funcs.perform_link_training = + core_dc->link_funcs.perform_link_training = perform_link_training; - core_dc->public.link_funcs.set_preferred_link_settings = + core_dc->link_funcs.set_preferred_link_settings = set_preferred_link_settings; - core_dc->public.link_funcs.enable_hpd = + core_dc->link_funcs.enable_hpd = enable_hpd; - core_dc->public.link_funcs.disable_hpd = + core_dc->link_funcs.disable_hpd = disable_hpd; - core_dc->public.link_funcs.set_test_pattern = + core_dc->link_funcs.set_test_pattern = set_test_pattern; } -static void destruct(struct core_dc *dc) +static void destruct(struct dc *dc) { dc_release_validate_context(dc->current_context); dc->current_context = NULL; @@ -446,10 +445,11 @@ static void destruct(struct core_dc *dc) dm_free(dc->dcn_ip); dc->dcn_ip = NULL; + #endif } -static bool construct(struct core_dc *dc, +static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; @@ -508,7 +508,7 @@ static bool construct(struct core_dc *dc, dc_ctx->cgs_device = init_params->cgs_device; dc_ctx->driver_context = init_params->driver; - dc_ctx->dc = &dc->public; + dc_ctx->dc = dc; dc_ctx->asic_id = init_params->asic_id; /* Create logger */ @@ -621,7 +621,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); + struct dc *core_dc = dm_alloc(sizeof(*core_dc)); unsigned int full_pipe_count; if (NULL == core_dc) @@ -636,23 +636,23 @@ struct dc *dc_create(const struct dc_init_data *init_params) full_pipe_count = core_dc->res_pool->pipe_count; if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) full_pipe_count--; - core_dc->public.caps.max_streams = min( + core_dc->caps.max_streams = min( full_pipe_count, core_dc->res_pool->stream_enc_count); - core_dc->public.caps.max_links = core_dc->link_count; - core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; + core_dc->caps.max_links = core_dc->link_count; + core_dc->caps.max_audios = core_dc->res_pool->audio_count; - core_dc->public.config = init_params->flags; + core_dc->config = init_params->flags; dm_logger_write(core_dc->ctx->logger, LOG_DC, "Display Core initialized\n"); /* TODO: missing feature to be enabled */ - core_dc->public.debug.disable_dfs_bypass = true; + core_dc->debug.disable_dfs_bypass = true; - return &core_dc->public; + return core_dc; construct_fail: dm_free(core_dc); @@ -663,14 +663,14 @@ alloc_fail: void dc_destroy(struct dc **dc) { - struct core_dc *core_dc = DC_TO_CORE(*dc); + struct dc *core_dc = *dc; destruct(core_dc); dm_free(core_dc); *dc = NULL; } static bool is_validation_required( - const struct core_dc *dc, + const struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -705,7 +705,7 @@ static bool is_validation_required( } static bool validate_streams ( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -719,7 +719,7 @@ static bool validate_streams ( } static bool validate_surfaces( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -734,11 +734,11 @@ static bool validate_surfaces( } struct validate_context *dc_get_validate_context( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -773,11 +773,11 @@ context_alloc_fail: } bool dc_validate_resources( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -811,10 +811,10 @@ context_alloc_fail: } bool dc_validate_guaranteed( - const struct dc *dc, + struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -844,7 +844,7 @@ context_alloc_fail: } static void program_timing_sync( - struct core_dc *core_dc, + struct dc *core_dc, struct validate_context *ctx) { int i, j; @@ -918,7 +918,7 @@ static void program_timing_sync( } static bool context_changed( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { uint8_t i; @@ -935,7 +935,7 @@ static bool context_changed( } static bool streams_changed( - struct core_dc *dc, + struct dc *dc, struct dc_stream_state *streams[], uint8_t stream_count) { @@ -961,7 +961,7 @@ bool dc_enable_stereo( bool ret = true; int i, j; struct pipe_ctx *pipe; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; #ifdef ENABLE_FBC struct compressor *fbc_compressor = core_dc->fbc_compressor; @@ -996,7 +996,7 @@ bool dc_enable_stereo( */ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_bios *dcb = core_dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; @@ -1064,7 +1064,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c bool dc_commit_context(struct dc *dc, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; if (false == context_changed(core_dc, context)) @@ -1092,7 +1092,7 @@ bool dc_commit_streams( struct dc_stream_state *streams[], uint8_t stream_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; @@ -1158,7 +1158,7 @@ context_alloc_fail: bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct validate_context *context = core_dc->current_context; post_surface_trace(dc); @@ -1375,7 +1375,7 @@ static enum surface_update_type get_scaling_info_update_type( } static enum surface_update_type det_surface_update( - const struct core_dc *dc, + const struct dc *dc, const struct dc_surface_update *u, int surface_index) { @@ -1410,7 +1410,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( struct dc_stream_update *stream_update, const struct dc_stream_status *stream_status) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1456,7 +1456,7 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct validate_context *context; int i, j; enum surface_update_type update_type; @@ -1781,29 +1781,29 @@ context_alloc_fail: DC_ERROR("Failed to allocate new validate context!\n"); } -uint8_t dc_get_current_stream_count(const struct dc *dc) +uint8_t dc_get_current_stream_count(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->current_context->stream_count; } -struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if (i < core_dc->current_context->stream_count) return core_dc->current_context->streams[i]; return NULL; } -struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) +struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]; } -struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) +struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { return core_dc->res_pool->dwbc[(int)pipe]; } else { @@ -1814,20 +1814,20 @@ struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) const struct graphics_object_id dc_get_link_id_at_index( struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]->link_id; } enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]->irq_source_hpd; } const struct audio **dc_get_audios(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return (const struct audio **)core_dc->res_pool->audios; } @@ -1836,24 +1836,24 @@ enum dc_irq_source dc_interrupt_to_irq_source( uint32_t src_id, uint32_t ext_id) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); } -void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) +void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) { - struct core_dc *core_dc; + struct dc *core_dc; if (dc == NULL) return; - core_dc = DC_TO_CORE(dc); + core_dc = dc; dal_irq_service_set(core_dc->res_pool->irqs, src, enable); } void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; dal_irq_service_ack(core_dc->res_pool->irqs, src); } @@ -1861,7 +1861,7 @@ void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; atomic_t ref_count; switch (power_state) { @@ -1889,9 +1889,9 @@ void dc_set_power_state( } -void dc_resume(const struct dc *dc) +void dc_resume(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; uint32_t i; @@ -1906,7 +1906,7 @@ bool dc_read_aux_dpcd( uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( @@ -1926,7 +1926,7 @@ bool dc_write_aux_dpcd( const uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( @@ -1947,7 +1947,7 @@ bool dc_read_aux_i2c( uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( @@ -1968,7 +1968,7 @@ bool dc_write_aux_i2c( const uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( @@ -1990,7 +1990,7 @@ bool dc_query_ddc_data( uint8_t *read_buf, uint32_t read_size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; @@ -2010,7 +2010,7 @@ bool dc_submit_i2c( uint32_t link_index, struct i2c_command *cmd) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; struct ddc_service *ddc = link->ddc; @@ -2129,7 +2129,7 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct mem_input *mi = NULL; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { @@ -2155,7 +2155,7 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) void dc_log_hw_state(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if (core_dc->hwss.log_hw_state) core_dc->hwss.log_hw_state(core_dc); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 21af3bc057c7..d74eed8f9b96 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -37,12 +37,12 @@ } while (0) void pre_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { @@ -158,12 +158,12 @@ void pre_surface_trace( } void update_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_surface_update *updates, int surface_count) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { @@ -279,9 +279,9 @@ void update_surface_trace( SURFACE_TRACE("\n"); } -void post_surface_trace(const struct dc *dc) +void post_surface_trace(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; SURFACE_TRACE("post surface process.\n"); @@ -289,11 +289,11 @@ void post_surface_trace(const struct dc *dc) } void context_timing_trace( - const struct dc *dc, + struct dc *dc, struct resource_context *res_ctx) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; struct crtc_position position; @@ -328,11 +328,11 @@ void context_timing_trace( } void context_clock_trace( - const struct dc *dc, + struct dc *dc, struct validate_context *context) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7b1f2493cbc9..71993d5983bf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "core_types.h" -#include "core_dc.h" #include "timing_generator.h" #include "hw_sequencer.h" @@ -55,7 +54,7 @@ static const struct tg_color black_color_format[] = { }; void color_space_to_black_color( - const struct core_dc *dc, + const struct dc *dc, enum dc_color_space colorspace, struct tg_color *black_color) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index b858fec72bd7..1888bf4d2c3f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -26,14 +26,13 @@ #include "dm_services.h" #include "dm_helpers.h" #include "dc.h" -#include "core_dc.h" #include "grph_object_id.h" #include "gpio_service_interface.h" #include "core_status.h" #include "dc_link_dp.h" #include "dc_link_ddc.h" #include "link_hwss.h" -#include "stream_encoder.h" + #include "link_encoder.h" #include "hw_sequencer.h" #include "resource.h" @@ -1392,7 +1391,7 @@ enum dc_status dc_link_validate_mode_timing( bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; @@ -1431,7 +1430,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, bool dc_link_set_abm_disable(const struct dc_link *link) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct abm *abm = core_dc->res_pool->abm; if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) @@ -1445,7 +1444,7 @@ bool dc_link_set_abm_disable(const struct dc_link *link) bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1456,7 +1455,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1469,7 +1468,7 @@ bool dc_link_setup_psr(struct dc_link *link, const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; int i; @@ -1874,7 +1873,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) void core_link_enable_stream(struct pipe_ctx *pipe_ctx) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; enum dc_status status = enable_link(pipe_ctx); @@ -1907,7 +1906,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) void core_link_disable_stream(struct pipe_ctx *pipe_ctx) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); @@ -1919,7 +1918,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) return; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 9d5fe658d14c..0144c98fd0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -10,7 +10,6 @@ #include "core_status.h" #include "dpcd_defs.h" -#include "core_dc.h" #include "resource.h" /* maximum pre emphasis level allowed for each voltage swing level*/ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index d19c663c257f..da880bd02ad7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -3,7 +3,7 @@ #include "dm_services.h" #include "dc.h" -#include "inc/core_dc.h" +#include "inc/core_types.h" #include "include/ddc_service_types.h" #include "include/i2caux_interface.h" #include "link_hwss.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index d2b8f27416d6..2b357318f945 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -92,7 +92,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) } struct resource_pool *dc_create_resource_pool( - struct core_dc *dc, + struct dc *dc, int num_virtual_links, enum dce_version dc_version, struct hw_asic_id asic_id) @@ -153,7 +153,7 @@ struct resource_pool *dc_create_resource_pool( return res_pool; } -void dc_destroy_resource_pool(struct core_dc *dc) +void dc_destroy_resource_pool(struct dc *dc) { if (dc) { if (dc->res_pool) @@ -193,7 +193,7 @@ static void update_num_audio( bool resource_construct( unsigned int num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct resource_pool *pool, const struct resource_create_funcs *create_funcs) { @@ -892,7 +892,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) enum dc_status resource_build_scaling_params_for_context( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context) { int i; @@ -1438,7 +1438,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) } enum dc_status resource_map_pool_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -2316,7 +2316,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) } enum dc_status resource_map_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -2343,7 +2343,7 @@ enum dc_status resource_map_clock_resources( else { pipe_ctx->clock_source = NULL; - if (!dc->public.config.disable_disp_pll_sharing) + if (!dc->config.disable_disp_pll_sharing) resource_find_used_clk_src_for_sharing( &context->res_ctx, pipe_ctx); @@ -2515,9 +2515,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) +bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_context *dc_ctx = core_dc->ctx; struct dc_link *link = stream->sink->link; struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; @@ -2547,9 +2547,9 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) return res == DC_OK; } -bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) +bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; /* TODO For now validates pixel format only */ if (core_dc->res_pool->funcs->validate_plane) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 47e407dab4a3..5e4f7f08e3db 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -144,7 +144,7 @@ struct dc_stream_status *dc_stream_get_status( struct dc_stream_state *stream) { uint8_t i; - struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct dc *dc = stream->ctx->dc; for (i = 0; i < dc->current_context->stream_count; i++) { if (stream == dc->current_context->streams[i]) { @@ -163,7 +163,7 @@ bool dc_stream_set_cursor_attributes( const struct dc_cursor_attributes *attributes) { int i; - struct core_dc *core_dc; + struct dc *core_dc; struct resource_context *res_ctx; if (NULL == stream) { @@ -175,7 +175,7 @@ bool dc_stream_set_cursor_attributes( return false; } - core_dc = DC_TO_CORE(stream->ctx->dc); + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -198,7 +198,7 @@ bool dc_stream_set_cursor_position( const struct dc_cursor_position *position) { int i; - struct core_dc *core_dc; + struct dc *core_dc; struct resource_context *res_ctx; if (NULL == stream) { @@ -211,7 +211,7 @@ bool dc_stream_set_cursor_position( return false; } - core_dc = DC_TO_CORE(stream->ctx->dc); + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -246,7 +246,7 @@ bool dc_stream_set_cursor_position( uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) { uint8_t i; - struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -270,7 +270,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, { uint8_t i; bool ret = false; - struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = &core_dc->current_context->res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index da19c7fa5151..0b6410fb2f3e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -28,7 +28,7 @@ #include "dc.h" /* DC core (private) */ -#include "core_dc.h" +#include "core_types.h" #include "transform.h" /******************************************************************************* @@ -64,9 +64,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, /*register_flip_interrupt(surface);*/ } -struct dc_plane_state *dc_create_plane_state(const struct dc *dc) +struct dc_plane_state *dc_create_plane_state(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); @@ -91,7 +91,7 @@ const struct dc_plane_status *dc_plane_get_status( const struct dc_plane_state *plane_state) { const struct dc_plane_status *plane_status; - struct core_dc *core_dc; + struct dc *core_dc; int i; if (!plane_state || @@ -102,7 +102,7 @@ const struct dc_plane_status *dc_plane_get_status( } plane_status = &plane_state->status; - core_dc = DC_TO_CORE(plane_state->ctx->dc); + core_dc = plane_state->ctx->dc; if (core_dc->current_context == NULL) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e62d15d90fdb..68056d888def 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -34,14 +34,19 @@ #include "grph_object_ctrl_defs.h" #include +#include "inc/hw_sequencer.h" +#include "dml/display_mode_lib.h" + + + #define MAX_SURFACES 3 #define MAX_STREAMS 6 #define MAX_SINKS_PER_LINK 4 + /******************************************************************************* * Display Core Interfaces ******************************************************************************/ - struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -186,7 +191,9 @@ struct dc_debug { bool disable_psr; bool force_abm_enable; }; - +struct validate_context; +struct resource_pool; +struct dce_hwseq; struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; @@ -194,6 +201,40 @@ struct dc { struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; + + struct dc_context *ctx; + + uint8_t link_count; + struct dc_link *links[MAX_PIPES * 2]; + + struct validate_context *current_context; + struct resource_pool *res_pool; + + /* Display Engine Clock levels */ + struct dm_pp_clock_levels sclk_lvls; + + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip *bw_dceip; + struct bw_calcs_vbios *bw_vbios; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; + struct display_mode_lib dml; +#endif + + /* HW functions */ + struct hw_sequencer_funcs hwss; + struct dce_hwseq *hwseq; + + /* temp store of dm_pp_display_configuration + * to compare to see if display config changed + */ + struct dm_pp_display_configuration prev_display_config; + + /* FBC compressor */ +#ifdef ENABLE_FBC + struct compressor *fbc_compressor; +#endif }; enum frame_buffer_mode { @@ -384,7 +425,7 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_plane_state *dc_create_plane_state(const struct dc *dc); +struct dc_plane_state *dc_create_plane_state(struct dc *dc); const struct dc_plane_status *dc_plane_get_status( const struct dc_plane_state *plane_state); @@ -558,8 +599,8 @@ void dc_stream_log( struct dal_logger *dc_logger, enum dc_log_type log_type); -uint8_t dc_get_current_stream_count(const struct dc *dc); -struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); +uint8_t dc_get_current_stream_count(struct dc *dc); +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); /* * Return the current frame counter. @@ -585,9 +626,9 @@ struct dc_validation_set { uint8_t plane_count; }; -bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); +bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); -bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); +bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); /* * This function takes a set of resources and checks that they are cofunctional. * @@ -595,12 +636,12 @@ bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_s * No hardware is programmed for call. Only validation is done. */ struct validate_context *dc_get_validate_context( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count); bool dc_validate_resources( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count); @@ -613,7 +654,7 @@ bool dc_validate_resources( */ bool dc_validate_guaranteed( - const struct dc *dc, + struct dc *dc, struct dc_stream_state *stream); void dc_resource_validate_ctx_copy_construct( @@ -764,7 +805,7 @@ struct dc_link { /* Private to DC core */ - const struct core_dc *dc; + const struct dc *dc; struct dc_context *ctx; @@ -795,9 +836,9 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); * boot time. They cannot be created or destroyed. * Use dc_get_caps() to get number of links. */ -struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); +struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); -struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe); +struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe); /* Return id of physical connector represented by a dc_link at link_index.*/ const struct graphics_object_id dc_get_link_id_at_index( @@ -948,7 +989,7 @@ enum dc_irq_source dc_interrupt_to_irq_source( struct dc *dc, uint32_t src_id, uint32_t ext_id); -void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); +void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index); @@ -960,7 +1001,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state); -void dc_resume(const struct dc *dc); +void dc_resume(struct dc *dc); /* * DPCD access interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 922af2d1b91a..0654fe34627c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -34,7 +34,6 @@ #include "dce_clock_source.h" -#include "core_dc.h" #include "reg_helper.h" #define REG(reg)\ @@ -609,7 +608,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( struct pll_settings *pll_settings) { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); + struct dc *dc_core = cs->ctx->dc; struct validate_context *context = dc_core->current_context; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; @@ -624,7 +623,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( struct pll_settings *pll_settings) { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); + struct dc *dc_core = cs->ctx->dc; struct validate_context *context = dc_core->current_context; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 7bb2eaf07da5..9d67340a6b8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -29,14 +29,12 @@ #include "fixed32_32.h" #include "bios_parser_interface.h" #include "dc.h" -#include "core_dc.h" #include "dce_abm.h" #include "dmcu.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "dcn_calcs.h" -#include "core_dc.h" #endif - +#include "core_types.h" #define TO_DCE_CLOCKS(clocks)\ @@ -368,7 +366,7 @@ static int dce_psr_set_clock( { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct dc_context *ctx = clk_dce->base.ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct dc *core_dc = ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; int actual_clk_khz = requested_clk_khz; @@ -385,7 +383,7 @@ static int dce112_set_clock( struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct bp_set_dce_clock_parameters dce_clk_params; struct dc_bios *bp = clk->ctx->dc_bios; - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct dc *core_dc = clk->ctx->dc; struct abm *abm = core_dc->res_pool->abm; struct dmcu *dmcu = core_dc->res_pool->dmcu; int actual_clock = requested_clk_khz; @@ -621,7 +619,7 @@ static bool dce_apply_clock_voltage_request( if (send_request) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (clk->ctx->dce_version >= DCN_VERSION_1_0) { - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct dc *core_dc = clk->ctx->dc; /*use dcfclk request voltage*/ clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock_voltage_req.clocks_in_khz = diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 4894e1755d84..d2e66b1bc0ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -26,7 +26,7 @@ #include "dce_hwseq.h" #include "reg_helper.h" #include "hw_sequencer.h" -#include "core_dc.h" +#include "core_types.h" #define CTX \ hws->ctx @@ -44,7 +44,7 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, DCFE_CLOCK_ENABLE, enable); } -void dce_pipe_control_lock(struct core_dc *dc, +void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 9a97d8ee7971..3a1eb6a79d66 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -528,7 +528,7 @@ enum blnd_mode { void dce_enable_fe_clock(struct dce_hwseq *hwss, unsigned int inst, bool enable); -void dce_pipe_control_lock(struct core_dc *dc, +void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index c638f47acefc..b7e51c5ed1b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -24,7 +24,6 @@ */ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "hw_sequencer.h" #include "dce100_hw_sequencer.h" @@ -71,7 +70,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { /***************************PIPE_CONTROL***********************************/ static bool dce100_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -107,7 +106,7 @@ static bool dce100_enable_display_power_gating( } static void dce100_pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -127,7 +126,7 @@ static void dce100_pplib_apply_display_requirements( } void dce100_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { @@ -143,7 +142,7 @@ void dce100_set_bandwidth( /**************************************************************************/ -bool dce100_hw_sequencer_construct(struct core_dc *dc) +bool dce100_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index 24433f0e770b..c04aa15cd656 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -28,13 +28,13 @@ #include "core_types.h" -struct core_dc; +struct dc; struct validate_context; -bool dce100_hw_sequencer_construct(struct core_dc *dc); +bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 46f0c71fbac4..b2b03633eb4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -652,7 +652,7 @@ static void destruct(struct dce110_resource_pool *pool) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -688,7 +688,7 @@ static enum dc_status build_mapped_resource( } bool dce100_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ @@ -720,7 +720,7 @@ static bool dce100_validate_surface_sets( } enum dc_status dce100_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -764,7 +764,7 @@ enum dc_status dce100_validate_with_context( } enum dc_status dce100_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -784,7 +784,7 @@ enum dc_status dce100_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -824,7 +824,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -909,9 +909,9 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = @@ -958,7 +958,7 @@ static bool construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -978,7 +978,7 @@ res_create_fail: struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index edc50caf04d1..ca7b2b7c1a48 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -8,13 +8,13 @@ #ifndef DCE100_RESOURCE_H_ #define DCE100_RESOURCE_H_ -struct core_dc; +struct dc; struct resource_pool; struct dc_validation_set; struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ccde7c80d658..e6c6f1108078 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -164,7 +164,7 @@ static void enable_display_pipe_clock_gating( } static bool dce110_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -944,7 +944,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, } } -static void program_scaler(const struct core_dc *dc, +static void program_scaler(const struct dc *dc, const struct pipe_ctx *pipe_ctx) { struct tg_color color = {0}; @@ -955,7 +955,7 @@ static void program_scaler(const struct core_dc *dc, return; #endif - if (dc->public.debug.surface_visual_confirm) + if (dc->debug.surface_visual_confirm) get_surface_visual_confirm_color(pipe_ctx, &color); else color_space_to_black_color(dc, @@ -979,7 +979,7 @@ static void program_scaler(const struct core_dc *dc, static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. @@ -1035,7 +1035,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( static enum dc_status apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. @@ -1146,7 +1146,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( /******************************************************************************/ -static void power_down_encoders(struct core_dc *dc) +static void power_down_encoders(struct dc *dc) { int i; @@ -1156,7 +1156,7 @@ static void power_down_encoders(struct core_dc *dc) } } -static void power_down_controllers(struct core_dc *dc) +static void power_down_controllers(struct dc *dc) { int i; @@ -1166,7 +1166,7 @@ static void power_down_controllers(struct core_dc *dc) } } -static void power_down_clock_sources(struct core_dc *dc) +static void power_down_clock_sources(struct dc *dc) { int i; @@ -1181,7 +1181,7 @@ static void power_down_clock_sources(struct core_dc *dc) } } -static void power_down_all_hw_blocks(struct core_dc *dc) +static void power_down_all_hw_blocks(struct dc *dc) { power_down_encoders(dc); @@ -1196,7 +1196,7 @@ static void power_down_all_hw_blocks(struct core_dc *dc) } static void disable_vga_and_power_gate_all_controllers( - struct core_dc *dc) + struct dc *dc) { int i; struct timing_generator *tg; @@ -1224,7 +1224,7 @@ static void disable_vga_and_power_gate_all_controllers( * 3. Enable power gating for controller * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) */ -void dce110_enable_accelerated_mode(struct core_dc *dc) +void dce110_enable_accelerated_mode(struct dc *dc) { power_down_all_hw_blocks(dc); @@ -1250,7 +1250,7 @@ static uint32_t compute_pstate_blackout_duration( } void dce110_set_displaymarks( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context) { uint8_t i, num_pipes; @@ -1316,7 +1316,7 @@ static void set_safe_displaymarks( } static void switch_dp_clock_sources( - const struct core_dc *dc, + const struct dc *dc, struct resource_context *res_ctx) { uint8_t i; @@ -1408,7 +1408,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, * may read PLL register to get pixel clock */ static uint32_t get_max_pixel_clock_for_all_paths( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool pre_mode_set) { @@ -1449,7 +1449,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( * etc support for dcn1.0 */ static void apply_min_clocks( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) @@ -1538,7 +1538,7 @@ static void apply_min_clocks( /* * Check if FBC can be enabled */ -static enum dc_status validate_fbc(struct core_dc *dc, +static enum dc_status validate_fbc(struct dc *dc, struct validate_context *context) { struct pipe_ctx *pipe_ctx = @@ -1568,7 +1568,7 @@ static enum dc_status validate_fbc(struct core_dc *dc, /* * Enable FBC */ -static enum dc_status enable_fbc(struct core_dc *dc, +static enum dc_status enable_fbc(struct dc *dc, struct validate_context *context) { enum dc_status status = validate_fbc(dc, context); @@ -1597,7 +1597,7 @@ static enum dc_status enable_fbc(struct core_dc *dc, #endif static enum dc_status apply_ctx_to_hw_fpga( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { enum dc_status status = DC_ERROR_UNEXPECTED; @@ -1627,7 +1627,7 @@ static enum dc_status apply_ctx_to_hw_fpga( } static void dce110_reset_hw_ctx_wrap( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { int i; @@ -1672,7 +1672,7 @@ static void dce110_reset_hw_ctx_wrap( enum dc_status dce110_apply_ctx_to_hw( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dc_bios *dcb = dc->ctx->dc_bios; @@ -1965,7 +1965,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) * -------------------------------------------------| * ******************************************************************************/ -static void program_surface_visibility(const struct core_dc *dc, +static void program_surface_visibility(const struct dc *dc, struct pipe_ctx *pipe_ctx) { enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; @@ -2038,7 +2038,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) * TODO REMOVE, USE UPDATE INSTEAD */ static void set_plane_config( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { @@ -2117,7 +2117,7 @@ static void set_plane_config( if (mi->funcs->set_blank) mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2125,7 +2125,7 @@ static void set_plane_config( plane_state->rotation); } -static void update_plane_addr(const struct core_dc *dc, +static void update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; @@ -2163,7 +2163,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) } } -void dce110_power_down(struct core_dc *dc) +void dce110_power_down(struct dc *dc) { power_down_all_hw_blocks(dc); disable_vga_and_power_gate_all_controllers(dc); @@ -2208,7 +2208,7 @@ static bool wait_for_reset_trigger_to_occur( /* Enable timing synchronization for a group of Timing Generators. */ static void dce110_enable_timing_synchronization( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) @@ -2257,7 +2257,7 @@ static void dce110_enable_timing_synchronization( DC_SYNC_INFO("GSL: Set-up complete.\n"); } -static void init_hw(struct core_dc *dc) +static void init_hw(struct dc *dc) { int i; struct dc_bios *bp; @@ -2394,7 +2394,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) } static int determine_sclk_from_bounding_box( - const struct core_dc *dc, + const struct dc *dc, int required_sclk) { int i; @@ -2420,7 +2420,7 @@ static int determine_sclk_from_bounding_box( } static void pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2474,7 +2474,7 @@ static void pplib_apply_display_requirements( } static void dce110_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { @@ -2491,7 +2491,7 @@ static void dce110_set_bandwidth( } static void dce110_program_front_end_for_pipe( - struct core_dc *dc, struct pipe_ctx *pipe_ctx) + struct dc *dc, struct pipe_ctx *pipe_ctx) { struct mem_input *mi = pipe_ctx->plane_res.mi; struct pipe_ctx *old_pipe = NULL; @@ -2572,7 +2572,7 @@ static void dce110_program_front_end_for_pipe( if (mi->funcs->set_blank) mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2618,7 +2618,7 @@ static void dce110_program_front_end_for_pipe( } static void dce110_apply_ctx_for_surface( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context) @@ -2648,7 +2648,7 @@ static void dce110_apply_ctx_for_surface( } } -static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) +static void dce110_power_down_fe(struct dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) @@ -2662,7 +2662,7 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) } static void dce110_wait_for_mpcc_disconnect( - struct core_dc *dc, + struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { @@ -2724,7 +2724,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect }; -bool dce110_hw_sequencer_construct(struct core_dc *dc) +bool dce110_hw_sequencer_construct(struct dc *dc) { dc->hwss = dce110_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 89782ca1917f..d710f6e6dc07 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -29,20 +29,20 @@ #include "core_types.h" #define GAMMA_HW_POINTS_NUM 256 -struct core_dc; +struct dc; struct validate_context; struct dm_pp_display_configuration; -bool dce110_hw_sequencer_construct(struct core_dc *dc); +bool dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( - struct core_dc *dc, + struct dc *dc, struct validate_context *context); void dce110_set_display_clock(struct validate_context *context); void dce110_set_displaymarks( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context); void dce110_enable_stream(struct pipe_ctx *pipe_ctx); @@ -55,9 +55,9 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); -void dce110_enable_accelerated_mode(struct core_dc *dc); +void dce110_enable_accelerated_mode(struct dc *dc); -void dce110_power_down(struct core_dc *dc); +void dce110_power_down(struct dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 56be84ce5a0d..2154c2e567f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -772,7 +772,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -814,7 +814,7 @@ static enum dc_status build_mapped_resource( } static bool dce110_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { bool result = false; @@ -928,7 +928,7 @@ static bool dce110_validate_surface_sets( } static enum dc_status dce110_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -972,7 +972,7 @@ static enum dc_status dce110_validate_with_context( } static enum dc_status dce110_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -992,7 +992,7 @@ static enum dc_status dce110_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -1008,7 +1008,7 @@ static struct pipe_ctx *dce110_acquire_underlay( const struct resource_pool *pool, struct dc_stream_state *stream) { - struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct dc *dc = stream->ctx->dc; struct resource_context *res_ctx = &context->res_ctx; unsigned int underlay_idx = pool->underlay_pipe_index; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; @@ -1117,7 +1117,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) return true; } -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels clks = {0}; @@ -1184,7 +1184,7 @@ const struct resource_caps *dce110_resource_cap( static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool, struct hw_asic_id asic_id) { @@ -1206,9 +1206,9 @@ static bool construct( pool->base.pipe_count = pool->base.res_cap->num_timing_generator; pool->base.underlay_pipe_index = pool->base.pipe_count; - dc->public.caps.max_downscale_ratio = 150; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 150; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1351,7 +1351,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); @@ -1366,7 +1366,7 @@ res_create_fail: struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct hw_asic_id asic_id) { struct dce110_resource_pool *pool = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h index 8e2e85dd30b9..5bb692d037d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -28,7 +28,7 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; #define TO_DCE110_RES_POOL(pool)\ @@ -42,7 +42,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct hw_asic_id asic_id); #endif /* __DC_RESOURCE_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c index 204f613467b7..8816e09110e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce112_hw_sequencer.h" @@ -112,7 +111,7 @@ static void dce112_init_pte(struct dc_context *ctx) } static bool dce112_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -153,7 +152,7 @@ static bool dce112_enable_display_power_gating( return false; } -bool dce112_hw_sequencer_construct(struct core_dc *dc) +bool dce112_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h index d96c582da45c..37bd60cc93f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce112_hw_sequencer_construct(struct core_dc *dc); +bool dce112_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index d6e58a25f3d0..89a8dfa68c01 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -723,7 +723,7 @@ static struct clock_source *find_matching_pll( } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -759,7 +759,7 @@ static enum dc_status build_mapped_resource( } bool dce112_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { bool result = false; @@ -837,7 +837,7 @@ bool dce112_validate_bandwidth( } enum dc_status resource_map_phy_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -904,7 +904,7 @@ static bool dce112_validate_surface_sets( } enum dc_status dce112_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -948,7 +948,7 @@ enum dc_status dce112_validate_with_context( } enum dc_status dce112_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *stream, struct validate_context *context) { @@ -968,7 +968,7 @@ enum dc_status dce112_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -997,7 +997,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .validate_plane = dce100_validate_plane }; -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; @@ -1153,7 +1153,7 @@ const struct resource_caps *dce112_resource_cap( static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1170,9 +1170,9 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = pool->base.res_cap->num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1319,7 +1319,7 @@ static bool construct( &res_create_funcs)) goto res_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) @@ -1338,7 +1338,7 @@ res_create_fail: struct resource_pool *dce112_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index feef559f1ecd..69f8f689196d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -28,27 +28,27 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce112_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); enum dc_status dce112_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, struct validate_context *old_context); enum dc_status dce112_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 91301b412aa0..d6225f332431 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce120_hw_sequencer.h" #include "dce/dce_hwseq.h" @@ -149,7 +148,7 @@ static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id) #endif static bool dce120_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -247,7 +246,7 @@ static void dce120_update_dchub( -bool dce120_hw_sequencer_construct(struct core_dc *dc) +bool dce120_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h index 3402413c7156..6448a17c2fde 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce120_hw_sequencer_construct(struct core_dc *dc); +bool dce120_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 562ae2205a90..b8fcdff40db3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -410,7 +410,7 @@ void dce120_clock_source_destroy(struct clock_source **clk_src) } -bool dce120_hw_sequencer_create(struct core_dc *dc) +bool dce120_hw_sequencer_create(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure @@ -704,7 +704,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { .validate_plane = dce100_validate_plane }; -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; @@ -831,7 +831,7 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -847,10 +847,10 @@ static bool construct( pool->base.pipe_count = res_cap.num_timing_generator; pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; - dc->public.debug = debug_defaults; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; + dc->debug = debug_defaults; /************************************************* * Create resources * @@ -982,7 +982,7 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); @@ -1003,7 +1003,7 @@ res_create_fail: struct resource_pool *dce120_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h index 038c78dcc247..3d1f3cf012f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h @@ -28,12 +28,12 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce120_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCE120_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index 4cba80ff6ca4..28fe3824441f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce80_hw_sequencer.h" @@ -72,7 +71,7 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = { /***************************PIPE_CONTROL***********************************/ static bool dce80_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -107,7 +106,7 @@ static bool dce80_enable_display_power_gating( return false; } -bool dce80_hw_sequencer_construct(struct core_dc *dc) +bool dce80_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h index 7cc203f433d3..9d6dd05bd596 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce80_hw_sequencer_construct(struct core_dc *dc); +bool dce80_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 132117e8bb77..838bfdaee009 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -684,7 +684,7 @@ static void destruct(struct dce110_resource_pool *pool) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -720,7 +720,7 @@ static enum dc_status build_mapped_resource( } bool dce80_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ @@ -752,7 +752,7 @@ static bool dce80_validate_surface_sets( } enum dc_status dce80_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -795,7 +795,7 @@ enum dc_status dce80_validate_with_context( } enum dc_status dce80_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -815,7 +815,7 @@ enum dc_status dce80_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -845,7 +845,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { static bool dce80_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -865,9 +865,9 @@ static bool dce80_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -974,7 +974,7 @@ static bool dce80_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -993,7 +993,7 @@ res_create_fail: struct resource_pool *dce80_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); @@ -1010,7 +1010,7 @@ struct resource_pool *dce80_create_resource_pool( static bool dce81_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1030,9 +1030,9 @@ static bool dce81_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_81.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1139,7 +1139,7 @@ static bool dce81_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -1158,7 +1158,7 @@ res_create_fail: struct resource_pool *dce81_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); @@ -1175,7 +1175,7 @@ struct resource_pool *dce81_create_resource_pool( static bool dce83_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1195,9 +1195,9 @@ static bool dce83_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_83.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1300,7 +1300,7 @@ static bool dce83_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -1319,7 +1319,7 @@ res_create_fail: struct resource_pool *dce83_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h index 04f0cfe24ef2..eff31ab83a39 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h @@ -28,20 +28,20 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce80_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); struct resource_pool *dce81_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); struct resource_pool *dce83_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c index 11386121f8ed..684241cb40d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c @@ -26,7 +26,6 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "reg_helper.h" -#include "core_dc.h" #include "resource.h" #include "dwb.h" #include "dcn10_dwb.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 184627c8685e..d5d2398d92b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -52,7 +52,7 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -static void log_mpc_crc(struct core_dc *dc) +static void log_mpc_crc(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dce_hwseq *hws = dc->hwseq; @@ -130,7 +130,7 @@ static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); } -static void dcn10_log_hubbub_state(struct core_dc *dc) +static void dcn10_log_hubbub_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; @@ -157,7 +157,7 @@ static void dcn10_log_hubbub_state(struct core_dc *dc) DTN_INFO("\n"); } -static void dcn10_log_hw_state(struct core_dc *dc) +static void dcn10_log_hw_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; @@ -273,7 +273,7 @@ static void verify_allow_pstate_change_high( forced_pstate_allow = true; if (should_log_hw_state) { - dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc)); + dcn10_log_hw_state(hws->ctx->dc); } BREAK_TO_DEBUGGER(); @@ -746,7 +746,7 @@ static void power_on_plane( "Un-gated front end for pipe %d\n", plane_id); } -static void bios_golden_init(struct core_dc *dc) +static void bios_golden_init(struct dc *dc) { struct dc_bios *bp = dc->ctx->dc_bios; int i; @@ -762,7 +762,7 @@ static void bios_golden_init(struct core_dc *dc) } } -static void dcn10_init_hw(struct core_dc *dc) +static void dcn10_init_hw(struct dc *dc) { int i; struct abm *abm = dc->res_pool->abm; @@ -773,7 +773,7 @@ static void dcn10_init_hw(struct core_dc *dc) REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); REG_WRITE(DIO_MEM_PWR_CTRL, 0); - if (!dc->public.debug.disable_clock_gate) { + if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); @@ -830,7 +830,7 @@ static void dcn10_init_hw(struct core_dc *dc) /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ REG_WRITE(DIO_MEM_PWR_CTRL, 0); - if (!dc->public.debug.disable_clock_gate) { + if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); @@ -845,7 +845,7 @@ static void dcn10_init_hw(struct core_dc *dc) static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space; @@ -932,7 +932,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( } static void reset_back_end_for_pipe( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -979,7 +979,7 @@ static void reset_back_end_for_pipe( } /* trigger HW to start disconnect plane from stream on the next vsync */ -static void plane_atomic_disconnect(struct core_dc *dc, +static void plane_atomic_disconnect(struct dc *dc, int fe_idx) { struct mem_input *mi = dc->res_pool->mis[fe_idx]; @@ -1004,10 +1004,10 @@ static void plane_atomic_disconnect(struct core_dc *dc, if (opp_id == dc->res_pool->pipe_count) return; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); mi->funcs->dcc_control(mi, false, false); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx); @@ -1015,7 +1015,7 @@ static void plane_atomic_disconnect(struct core_dc *dc, /* disable HW used by plane. * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct core_dc *dc, +static void plane_atomic_disable(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1037,7 +1037,7 @@ static void plane_atomic_disable(struct core_dc *dc, mi->opp_id = 0xf; mi->mpcc_id = 0xf; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); REG_UPDATE(HUBP_CLK_CNTL[fe_idx], @@ -1049,7 +1049,7 @@ static void plane_atomic_disable(struct core_dc *dc, REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 0); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } @@ -1057,7 +1057,7 @@ static void plane_atomic_disable(struct core_dc *dc, * kill power to plane hw * note: cannot power down until plane is disable */ -static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) +static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; struct transform *xfm = dc->res_pool->transforms[fe_idx]; @@ -1072,13 +1072,13 @@ static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) dm_logger_write(dc->ctx->logger, LOG_DC, "Power gated front end %d\n", fe_idx); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void reset_front_end( - struct core_dc *dc, + struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1097,7 +1097,7 @@ static void reset_front_end( REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); tg->funcs->unlock(tg); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(hws); if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) @@ -1112,7 +1112,7 @@ static void reset_front_end( fe_idx); } -static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) +static void dcn10_power_down_fe(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; struct transform *xfm = dc->res_pool->transforms[fe_idx]; @@ -1129,12 +1129,12 @@ static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) dm_logger_write(dc->ctx->logger, LOG_DC, "Power gated front end %d\n", fe_idx); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void reset_hw_ctx_wrap( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { int i; @@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(struct dce_hwseq *hws) DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); } -static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) +static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; @@ -1657,7 +1657,7 @@ static bool dcn10_set_output_transfer_func( } static void dcn10_pipe_control_lock( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe, bool lock) { @@ -1669,7 +1669,7 @@ static void dcn10_pipe_control_lock( if (pipe->top_pipe) return; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); if (lock) @@ -1677,7 +1677,7 @@ static void dcn10_pipe_control_lock( else pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } @@ -1719,7 +1719,7 @@ static bool wait_for_reset_trigger_to_occur( } static void dcn10_enable_timing_synchronization( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) @@ -1748,7 +1748,7 @@ static void dcn10_enable_timing_synchronization( } static void print_rq_dlg_ttu( - struct core_dc *core_dc, + struct dc *core_dc, struct pipe_ctx *pipe_ctx) { dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, @@ -1870,14 +1870,14 @@ static void print_rq_dlg_ttu( } static void dcn10_power_on_fe( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -1928,7 +1928,7 @@ static void dcn10_power_on_fe( print_rq_dlg_ttu(dc, pipe_ctx); } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } } @@ -2084,7 +2084,7 @@ static void dcn10_get_surface_visual_confirm_color( } static void update_dchubp_dpp( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -2126,7 +2126,7 @@ static void update_dchubp_dpp( size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2142,7 +2142,7 @@ static void update_dchubp_dpp( mpcc_cfg.opp = pipe_ctx->stream_res.opp; for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) mpcc_cfg.z_index++; - if (dc->public.debug.surface_visual_confirm) + if (dc->debug.surface_visual_confirm) dcn10_get_surface_visual_confirm_color( pipe_ctx, &mpcc_cfg.black_color); else @@ -2187,7 +2187,7 @@ static void update_dchubp_dpp( static void program_all_pipe_in_tree( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -2201,7 +2201,7 @@ static void program_all_pipe_in_tree( /* watermark is for all pipes */ program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { /* pstate stuck check after watermark update */ verify_allow_pstate_change_high(dc->hwseq); } @@ -2236,7 +2236,7 @@ static void program_all_pipe_in_tree( update_dchubp_dpp(dc, pipe_ctx, context); } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { /* pstate stuck check after each pipe is programmed */ verify_allow_pstate_change_high(dc->hwseq); } @@ -2246,7 +2246,7 @@ static void program_all_pipe_in_tree( } static void dcn10_pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2273,14 +2273,14 @@ static void dcn10_pplib_apply_display_requirements( } static void dcn10_apply_ctx_for_surface( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context) { int i, be_idx; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); be_idx = -1; @@ -2351,7 +2351,7 @@ static void dcn10_apply_ctx_for_surface( "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", old_pipe_ctx->mpcc->inst);*/ - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); old_pipe_ctx->top_pipe = NULL; @@ -2422,18 +2422,18 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void dcn10_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { struct dm_pp_clock_for_voltage_req clock; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2488,7 +2488,7 @@ static void dcn10_set_bandwidth( } dcn10_pplib_apply_display_requirements(dc, context); - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2541,7 +2541,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, } static void set_plane_config( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { @@ -2586,7 +2586,7 @@ static void dcn10_config_stereo_parameters( return; } -static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) +static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) { struct crtc_stereo_flags flags = { 0 }; struct dc_stream_state *stream = pipe_ctx->stream; @@ -2607,13 +2607,13 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) } static void dcn10_wait_for_mpcc_disconnect( - struct core_dc *dc, + struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { int i; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2631,14 +2631,14 @@ static void dcn10_wait_for_mpcc_disconnect( } } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } } static bool dcn10_dummy_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -2652,7 +2652,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) struct timing_generator *tg = pipe_ctx->stream_res.tg; if (plane_state->ctx->dc->debug.sanity_checks) { - struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); + struct dc *dc = plane_state->ctx->dc; verify_allow_pstate_change_high(dc->hwseq); } @@ -2716,7 +2716,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { }; -void dcn10_hw_sequencer_construct(struct core_dc *dc) +void dcn10_hw_sequencer_construct(struct dc *dc) { dc->hwss = dcn10_funcs; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 28218dc43522..8bb09de8dcd7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -void dcn10_hw_sequencer_construct(struct core_dc *dc); +void dcn10_hw_sequencer_construct(struct dc *dc); extern void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index c36843d497ac..2d9e88f08abb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -825,7 +825,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -872,7 +872,7 @@ static enum dc_status build_mapped_resource( } enum dc_status dcn10_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -917,7 +917,7 @@ enum dc_status dcn10_validate_with_context( } enum dc_status dcn10_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -937,7 +937,7 @@ enum dc_status dcn10_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } if (result == DC_OK && !dcn_validate_bandwidth(dc, context)) @@ -1221,7 +1221,7 @@ static struct resource_funcs dcn10_res_pool_funcs = { static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dcn10_resource_pool *pool) { int i; @@ -1244,16 +1244,16 @@ static bool construct( /* TODO: Hardcode to correct number of functional controllers */ pool->base.pipe_count = 4; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 256; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 256; - dc->public.caps.max_slave_planes = 1; + dc->caps.max_slave_planes = 1; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) - dc->public.debug = debug_defaults_drv; + dc->debug = debug_defaults_drv; else - dc->public.debug = debug_defaults_diags; + dc->debug = debug_defaults_diags; /************************************************* * Create resources * @@ -1327,7 +1327,7 @@ static bool construct( if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { dc->dcn_soc->urgent_latency = 3; - dc->public.debug.disable_dmcu = true; + dc->debug.disable_dmcu = true; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; } @@ -1347,10 +1347,10 @@ static bool construct( } } - if (!dc->public.debug.disable_pplib_clock_request) + if (!dc->debug.disable_pplib_clock_request) dcn_bw_update_from_pplib(dc); dcn_bw_sync_calcs_and_dml(dc); - if (!dc->public.debug.disable_pplib_wm_range) + if (!dc->debug.disable_pplib_wm_range) dcn_bw_notify_pplib_of_wm_ranges(dc); { @@ -1424,9 +1424,9 @@ static bool construct( goto res_create_fail; dcn10_hw_sequencer_construct(dc); - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; - dc->public.cap_funcs = cap_funcs; + dc->cap_funcs = cap_funcs; return true; @@ -1449,7 +1449,7 @@ dwbc_create_fail: struct resource_pool *dcn10_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dcn10_resource_pool *pool = dm_alloc(sizeof(struct dcn10_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h index 5f84dbd0bdea..8f71225bc61b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h @@ -31,7 +31,7 @@ #define TO_DCN10_RES_POOL(pool)\ container_of(pool, struct dcn10_resource_pool, base) -struct core_dc; +struct dc; struct resource_pool; struct _vcs_dpi_display_pipe_params_st; @@ -40,7 +40,7 @@ struct dcn10_resource_pool { }; struct resource_pool *dcn10_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h deleted file mode 100644 index ebe1fd78a92a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * core_dc.h - * - * Created on: Nov 13, 2015 - * Author: yonsun - */ - -#ifndef __CORE_DC_H__ -#define __CORE_DC_H__ - -#include "core_types.h" -#include "hw_sequencer.h" -#include "compressor.h" - -#define DC_TO_CORE(dc)\ - container_of(dc, struct core_dc, public) - -struct core_dc { - struct dc public; - struct dc_context *ctx; - - uint8_t link_count; - struct dc_link *links[MAX_PIPES * 2]; - - struct validate_context *current_context; - struct resource_pool *res_pool; - - /* Display Engine Clock levels */ - struct dm_pp_clock_levels sclk_lvls; - - /* Inputs into BW and WM calculations. */ - struct bw_calcs_dceip *bw_dceip; - struct bw_calcs_vbios *bw_vbios; -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc; - struct dcn_ip_params *dcn_ip; - struct display_mode_lib dml; -#endif - - /* HW functions */ - struct hw_sequencer_funcs hwss; - struct dce_hwseq *hwseq; - - /* temp store of dm_pp_display_configuration - * to compare to see if display config changed - */ - struct dm_pp_display_configuration prev_display_config; - - /* FBC compressor */ -#ifdef ENABLE_FBC - struct compressor *fbc_compressor; -#endif -}; - -#endif /* __CORE_DC_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 28454028434c..f8ade552c595 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -52,7 +52,7 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, /************ link *****************/ struct link_init_data { - const struct core_dc *dc; + const struct dc *dc; struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ uint32_t connector_index; /* this will be mapped to the HPD pins */ uint32_t link_index; /* this is mapped to DAL display_index @@ -87,19 +87,19 @@ struct resource_funcs { struct link_encoder *(*link_enc_create)( const struct encoder_init_data *init); enum dc_status (*validate_with_context)( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, struct validate_context *old_context); enum dc_status (*validate_guaranteed)( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *stream, struct validate_context *context); bool (*validate_bandwidth)( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 36c48f7d3f56..6a205b010084 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -33,7 +33,7 @@ #include "bw_fixed.h" struct pipe_ctx; -struct core_dc; +struct dc; struct validate_context; struct dce_bw_output; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 7e8abcd60d12..58744fe87ed8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -34,7 +34,7 @@ #include "display_clock.h" #include "../dml/display_mode_lib.h" -struct core_dc; +struct dc; struct validate_context; /******************************************************************************* @@ -620,16 +620,16 @@ struct dcn_ip_params { extern const struct dcn_ip_params dcn10_ip_defaults; bool dcn_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); unsigned int dcn_find_dcfclk_suits_all( - const struct core_dc *dc, + const struct dc *dc, struct clocks_value *clocks); -void dcn_bw_update_from_pplib(struct core_dc *dc); -void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc); -void dcn_bw_sync_calcs_and_dml(struct core_dc *dc); +void dcn_bw_update_from_pplib(struct dc *dc); +void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc); +void dcn_bw_sync_calcs_and_dml(struct dc *dc); #endif /* __DCN_CALCS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index a02f18ae527d..f876a11c903f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -30,6 +30,7 @@ #include "dml/display_mode_structs.h" +struct dchub_init_data; struct cstate_pstate_watermarks_st { uint32_t cstate_exit_ns; uint32_t cstate_enter_plus_exit_ns; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 7689e372b9da..c73dca9f6d46 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -25,8 +25,10 @@ #ifndef __DC_HW_SEQUENCER_H__ #define __DC_HW_SEQUENCER_H__ -#include "core_types.h" -#include "timing_generator.h" +#include "dc_types.h" +#include "clock_source.h" +#include "inc/hw/timing_generator.h" +#include "core_status.h" enum pipe_gating_control { PIPE_GATING_CONTROL_DISABLE = 0, @@ -46,25 +48,31 @@ struct dce_hwseq { struct dce_hwseq_wa wa; }; +struct pipe_ctx; +struct validate_context; +struct dchub_init_data; +struct dc_static_screen_events; +struct resource_pool; +struct resource_context; struct hw_sequencer_funcs { - void (*init_hw)(struct core_dc *dc); + void (*init_hw)(struct dc *dc); enum dc_status (*apply_ctx_to_hw)( - struct core_dc *dc, struct validate_context *context); + struct dc *dc, struct validate_context *context); void (*reset_hw_ctx_wrap)( - struct core_dc *dc, struct validate_context *context); + struct dc *dc, struct validate_context *context); void (*apply_ctx_for_surface)( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context); void (*set_plane_config)( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx); @@ -77,7 +85,7 @@ struct hw_sequencer_funcs { uint16_t *matrix); void (*update_plane_addr)( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx); void (*update_dchub)( @@ -95,12 +103,12 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); - void (*power_down)(struct core_dc *dc); + void (*power_down)(struct dc *dc); - void (*enable_accelerated_mode)(struct core_dc *dc); + void (*enable_accelerated_mode)(struct dc *dc); void (*enable_timing_synchronization)( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]); @@ -110,14 +118,14 @@ struct hw_sequencer_funcs { bool clock_gating); bool (*enable_display_power_gating)( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct core_dc *dc, int fe_idx); + void (*power_down_front_end)(struct dc *dc, int fe_idx); - void (*power_on_front_end)(struct core_dc *dc, + void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, struct validate_context *context); @@ -131,12 +139,12 @@ struct hw_sequencer_funcs { struct dc_link_settings *link_settings); void (*pipe_control_lock)( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe, bool lock); void (*set_bandwidth)( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed); @@ -152,23 +160,23 @@ struct hw_sequencer_funcs { enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc); + struct dc *dc); void (*setup_stereo)( struct pipe_ctx *pipe_ctx, - struct core_dc *dc); + struct dc *dc); void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); - void (*log_hw_state)(struct core_dc *dc); + void (*log_hw_state)(struct dc *dc); - void (*wait_for_mpcc_disconnect)(struct core_dc *dc, + void (*wait_for_mpcc_disconnect)(struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( - const struct core_dc *dc, + const struct dc *dc, enum dc_color_space colorspace, struct tg_color *black_color); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 7f30d9937d10..13218a52e2fa 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -27,7 +27,6 @@ #include "core_types.h" #include "core_status.h" -#include "core_dc.h" #include "dal_asic_id.h" /* TODO unhardcode, 4 for CZ*/ @@ -67,27 +66,27 @@ struct resource_create_funcs { bool resource_construct( unsigned int num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct resource_pool *pool, const struct resource_create_funcs *create_funcs); struct resource_pool *dc_create_resource_pool( - struct core_dc *dc, + struct dc *dc, int num_virtual_links, enum dce_version dc_version, struct hw_asic_id asic_id); -void dc_destroy_resource_pool(struct core_dc *dc); +void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context); void resource_build_info_frame(struct pipe_ctx *pipe_ctx); @@ -148,12 +147,12 @@ void resource_validate_ctx_update_pointer_after_copy( struct validate_context *dst_ctx); enum dc_status resource_map_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); enum dc_status resource_map_phy_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 24e47eb8cf3f..e3a12f3e0642 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -34,8 +34,8 @@ #include "ivsrcid/ivsrcid_vislands30.h" -#include "core_dc.h" - +#include "dc.h" +#include "core_types.h" static bool hpd_ack( struct irq_service *irq_service, const struct irq_source_info *info) @@ -206,7 +206,7 @@ bool dce110_vblank_set( bool enable) { struct dc_context *dc_ctx = irq_service->ctx; - struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc); + struct dc *core_dc = irq_service->ctx->dc; enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source( irq_service->ctx->dc, info->src_id, diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index 7e8cb22f280f..f458ef8e4c57 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -36,7 +36,6 @@ #include "ivsrcid/ivsrcid_vislands30.h" #include "dc_types.h" -#include "inc/core_dc.h" static bool hpd_ack( struct irq_service *irq_service, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index beb790937769..93c8556358f0 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -76,23 +76,23 @@ void logger_write(struct dal_logger *logger, void *paralist); void pre_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count); void update_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_surface_update *updates, int surface_count); -void post_surface_trace(const struct dc *dc); +void post_surface_trace(struct dc *dc); void context_timing_trace( - const struct dc *dc, + struct dc *dc, struct resource_context *res_ctx); void context_clock_trace( - const struct dc *dc, + struct dc *dc, struct validate_context *context); /* Any function which is empty or have incomplete implementation should be diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f0a3e4332a09..f49203b3eb94 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -27,7 +27,6 @@ #include "dc.h" #include "mod_freesync.h" #include "core_types.h" -#include "core_dc.h" #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 @@ -146,7 +145,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) struct core_freesync *core_freesync = dm_alloc(sizeof(struct core_freesync)); - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct persistent_data_flag flag; @@ -246,7 +245,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct dc_stream_state *stream, struct mod_freesync_caps *caps) { - struct core_dc *core_dc = NULL; + struct dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; struct persistent_data_flag flag; @@ -257,7 +256,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = DC_TO_CORE(core_freesync->dc); + core_dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; @@ -971,14 +970,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, unsigned int stream_index, map_index; int persistent_data = 0; struct persistent_data_flag flag; - struct core_dc *core_dc = NULL; + struct dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; if (mod_freesync == NULL) return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = DC_TO_CORE(core_freesync->dc); + core_dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; -- cgit v1.2.3-59-g8ed1b From 1dc904974eb7deef924650adc5af542878ce2040 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 31 Jul 2017 11:29:25 -0400 Subject: drm/amd/display: Per stream validate_context build v2. Until now new context would start as empty, then populated with exsisting pipes + new. Now we start with duplication of existing context and then add/delete from the context pipes as needed. This allows to do a per stream resource population, start discarding dc_validation_set and by this brings DC closer to to DRM. v2: Add some fixes and rebase. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 ++- drivers/gpu/drm/amd/display/dc/core/dc.c | 108 +---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 468 +++++++++++++++------ drivers/gpu/drm/amd/display/dc/dc.h | 32 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 78 +--- .../drm/amd/display/dc/dce110/dce110_resource.c | 86 +--- .../drm/amd/display/dc/dce112/dce112_resource.c | 143 +++---- .../drm/amd/display/dc/dce112/dce112_resource.h | 5 + .../drm/amd/display/dc/dce120/dce120_resource.c | 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 79 +--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 85 ++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 19 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 6 +- 13 files changed, 577 insertions(+), 604 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d28de04efa42..17e9bf7a2ebb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -25,6 +25,7 @@ #include "dm_services_types.h" #include "dc.h" +#include "dc/inc/core_types.h" #include "vid.h" #include "amdgpu.h" @@ -690,13 +691,33 @@ struct drm_atomic_state * dm_atomic_state_alloc(struct drm_device *dev) { struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); + struct validate_context *new_ctx; + struct amdgpu_device *adev = dev->dev_private; + struct dc *dc = adev->dm.dc; - if (!state || drm_atomic_state_init(dev, &state->base) < 0) { - kfree(state); + if (!state) return NULL; - } + + if (drm_atomic_state_init(dev, &state->base) < 0) + goto fail; + + /* copy existing configuration */ + new_ctx = dm_alloc(sizeof(*new_ctx)); + + if (!new_ctx) + goto fail; + + atomic_inc(&new_ctx->ref_count); + + dc_resource_validate_ctx_copy_construct_current(dc, new_ctx); + + state->context = new_ctx; return &state->base; + +fail: + kfree(state); + return NULL; } static void @@ -4418,7 +4439,6 @@ static int do_aquire_global_lock( int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { - struct dm_atomic_state *dm_state; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; struct drm_plane *plane; @@ -4432,6 +4452,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, int set_count; struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); /* * This bool will be set for true for any modeset/reset @@ -4446,8 +4467,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, return ret; } - dm_state = to_dm_atomic_state(state); - /* copy existing configuration */ set_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -4490,8 +4509,17 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (modereset_required(crtc_state)) { - /* i.e. reset mode */ + /* i.e. reset mode */ if (new_acrtc_state->stream) { + + if (!dc_remove_stream_from_ctx( + dc, + dm_state->context, + new_acrtc_state->stream)) { + ret = -EINVAL; + goto fail; + } + set_count = remove_from_val_sets( set, set_count, @@ -4539,8 +4567,19 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (modeset_required(crtc_state, new_stream, old_acrtc_state->stream)) { - if (new_acrtc_state->stream) + if (new_acrtc_state->stream) { + + if (!dc_remove_stream_from_ctx( + dc, + dm_state->context, + new_acrtc_state->stream)) { + ret = -EINVAL; + goto fail; + } + + dc_stream_release(new_acrtc_state->stream); + } new_acrtc_state->stream = new_stream; @@ -4551,6 +4590,14 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, new_acrtc_state->stream, crtc); + if (!dc_add_stream_to_ctx( + dc, + dm_state->context, + new_acrtc_state->stream)) { + ret = -EINVAL; + goto fail; + } + lock_and_validation_needed = true; } else { /* @@ -4667,9 +4714,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, ret = do_aquire_global_lock(dev, state); if (ret) goto fail; - WARN_ON(dm_state->context); - dm_state->context = dc_get_validate_context(dc, set, set_count); - if (!dm_state->context) { + + if (!dc_validate_global_state(dc, set, set_count, dm_state->context)) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 44c7b52e4a00..10126d9a7233 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -669,41 +669,6 @@ void dc_destroy(struct dc **dc) *dc = NULL; } -static bool is_validation_required( - const struct dc *dc, - const struct dc_validation_set set[], - int set_count) -{ - const struct validate_context *context = dc->current_context; - int i, j; - - if (context->stream_count != set_count) - return true; - - for (i = 0; i < set_count; i++) { - - if (set[i].plane_count != context->stream_status[i].plane_count) - return true; - if (!dc_is_stream_unchanged(set[i].stream, context->streams[i])) - return true; - - for (j = 0; j < set[i].plane_count; j++) { - struct dc_plane_state temp_plane; - memset(&temp_plane, 0, sizeof(temp_plane)); - - temp_plane = *context->stream_status[i].plane_states[j]; - temp_plane.clip_rect = set[i].plane_states[j]->clip_rect; - temp_plane.dst_rect.x = set[i].plane_states[j]->dst_rect.x; - temp_plane.dst_rect.y = set[i].plane_states[j]->dst_rect.y; - - if (memcmp(&temp_plane, set[i].plane_states[j], sizeof(temp_plane)) != 0) - return true; - } - } - - return false; -} - static bool validate_streams ( struct dc *dc, const struct dc_validation_set set[], @@ -733,52 +698,12 @@ static bool validate_surfaces( return true; } -struct validate_context *dc_get_validate_context( - struct dc *dc, - const struct dc_validation_set set[], - uint8_t set_count) -{ - struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; - - - context = dm_alloc(sizeof(struct validate_context)); - if (context == NULL) - goto context_alloc_fail; - - atomic_inc(&context->ref_count); - - if (!is_validation_required(core_dc, set, set_count)) { - dc_resource_validate_ctx_copy_construct(core_dc->current_context, context); - return context; - } - - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, set_count, context, core_dc->current_context); - -context_alloc_fail: - if (result != DC_OK) { - dm_logger_write(core_dc->ctx->logger, LOG_WARNING, - "%s:resource validation failed, dc_status:%d\n", - __func__, - result); - - dc_release_validate_context(context); - context = NULL; - } - - return context; - -} - bool dc_validate_resources( struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; + bool result = false; struct validate_context *context; if (!validate_streams(dc, set, set_count)) @@ -793,21 +718,16 @@ bool dc_validate_resources( atomic_inc(&context->ref_count); - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, set_count, context, NULL); + dc_resource_validate_ctx_copy_construct_current(dc, context); -context_alloc_fail: - if (result != DC_OK) { - dm_logger_write(core_dc->ctx->logger, LOG_WARNING, - "%s:resource validation failed, dc_status:%d\n", - __func__, - result); - } + result = dc_validate_with_context( + dc, set, set_count, context); +context_alloc_fail: dc_release_validate_context(context); context = NULL; - return result == DC_OK; + return result; } bool dc_validate_guaranteed( @@ -1093,7 +1013,7 @@ bool dc_commit_streams( uint8_t stream_count) { struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; + bool result = false; struct validate_context *context; struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; int i; @@ -1135,13 +1055,11 @@ bool dc_commit_streams( atomic_inc(&context->ref_count); - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, stream_count, context, core_dc->current_context); - if (result != DC_OK){ - dm_logger_write(core_dc->ctx->logger, LOG_ERROR, - "%s: Context validation failed! dc_status:%d\n", - __func__, - result); + dc_resource_validate_ctx_copy_construct_current(dc, context); + + result = dc_validate_with_context( + dc, set, stream_count, context); + if (!result) { BREAK_TO_DEBUGGER(); goto fail; } @@ -1152,7 +1070,7 @@ fail: dc_release_validate_context(context); context_alloc_fail: - return (result == DC_OK); + return result; } bool dc_post_update_surfaces_to_stream(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2b357318f945..f640986c6fd2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -938,7 +938,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( int i; for (i = 0; i < MAX_PIPES; i++) { if (res_ctx->pipe_ctx[i].stream == stream && - res_ctx->pipe_ctx[i].stream_res.stream_enc) { + !res_ctx->pipe_ctx[i].top_pipe) { return &res_ctx->pipe_ctx[i]; break; } @@ -1217,29 +1217,31 @@ bool resource_validate_attach_surfaces( #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 -static void set_stream_engine_in_use( +static void update_stream_engine_usage( struct resource_context *res_ctx, const struct resource_pool *pool, - struct stream_encoder *stream_enc) + struct stream_encoder *stream_enc, + bool acquired) { int i; for (i = 0; i < pool->stream_enc_count; i++) { if (pool->stream_enc[i] == stream_enc) - res_ctx->is_stream_enc_acquired[i] = true; + res_ctx->is_stream_enc_acquired[i] = acquired; } } /* TODO: release audio object */ -static void set_audio_in_use( +static void update_audio_usage( struct resource_context *res_ctx, const struct resource_pool *pool, - struct audio *audio) + struct audio *audio, + bool acquired) { int i; for (i = 0; i < pool->audio_count; i++) { if (pool->audios[i] == audio) - res_ctx->is_audio_acquired[i] = true; + res_ctx->is_audio_acquired[i] = acquired; } } @@ -1361,6 +1363,100 @@ bool resource_is_stream_unchanged( return false; } +bool dc_add_stream_to_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream) +{ + struct dc_context *dc_ctx = dc->ctx; + enum dc_status res; + + if (new_ctx->stream_count >= dc->res_pool->pipe_count) { + DC_ERROR("Max streams reached, can add stream %p !\n", stream); + return DC_ERROR_UNEXPECTED; + } + + new_ctx->streams[new_ctx->stream_count] = stream; + dc_stream_retain(stream); + new_ctx->stream_count++; + + res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); + if (res != DC_OK) + DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res); + + return res == DC_OK; +} + +bool dc_remove_stream_from_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream) +{ + int i, j; + struct dc_context *dc_ctx = dc->ctx; + struct pipe_ctx *del_pipe = NULL; + + /*TODO MPO to remove extra pipe or in surface remove ?*/ + + /* Release primary and secondary pipe (if exsist) */ + for (i = 0; i < MAX_PIPES; i++) { + if (new_ctx->res_ctx.pipe_ctx[i].stream == stream) { + del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; + + if (del_pipe->stream_res.stream_enc) + update_stream_engine_usage( + &new_ctx->res_ctx, + dc->res_pool, + del_pipe->stream_res.stream_enc, + false); + + if (del_pipe->stream_res.audio) + update_audio_usage( + &new_ctx->res_ctx, + dc->res_pool, + del_pipe->stream_res.audio, + false); + + memset(del_pipe, 0, sizeof(*del_pipe)); + } + } + + if (!del_pipe) { + DC_ERROR("Pipe not found for stream %p !\n", stream); + return DC_ERROR_UNEXPECTED; + } + + for (i = 0; i < new_ctx->stream_count; i++) + if (new_ctx->streams[i] == stream) + break; + + if (new_ctx->streams[i] != stream) { + DC_ERROR("Context doesn't have stream %p !\n", stream); + return DC_ERROR_UNEXPECTED; + } + + dc_stream_release(new_ctx->streams[i]); + new_ctx->stream_count--; + + /*TODO move into dc_remove_surface_from_ctx ?*/ + for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) + dc_plane_state_release(new_ctx->stream_status[i].plane_states[j]); + + /* Trim back arrays */ + for (; i < new_ctx->stream_count; i++) { + new_ctx->streams[i] = new_ctx->streams[i + 1]; + new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; + } + + new_ctx->streams[new_ctx->stream_count] = NULL; + memset( + &new_ctx->stream_status[new_ctx->stream_count], + 0, + sizeof(new_ctx->stream_status[0])); + + return DC_OK; +} + static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { @@ -1440,15 +1536,16 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) enum dc_status resource_map_pool_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { const struct resource_pool *pool = dc->res_pool; - int i, j; - - for (i = 0; old_context && i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + int i; + struct dc_context *dc_ctx = dc->ctx; + struct pipe_ctx *pipe_ctx = NULL; + int pipe_idx = -1; - if (!resource_is_stream_unchanged(old_context, stream)) { + /* TODO Check if this is needed */ + /*if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { stream->bit_depth_params = old_context->streams[i]->bit_depth_params; @@ -1456,119 +1553,228 @@ enum dc_status resource_map_pool_resources( continue; } } + */ - /* mark resources used for stream that is already active */ - for (j = 0; j < pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - const struct pipe_ctx *old_pipe_ctx = - &old_context->res_ctx.pipe_ctx[j]; - - if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) - continue; + /* acquire new resources */ + pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); - if (old_pipe_ctx->top_pipe) - continue; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (pipe_idx < 0) + acquire_first_split_pipe(&context->res_ctx, pool, stream); +#endif + if (pipe_idx < 0) + return DC_NO_CONTROLLER_RESOURCE; + + pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + + pipe_ctx->stream_res.stream_enc = + find_first_free_match_stream_enc_for_link( + &context->res_ctx, pool, stream); + + if (!pipe_ctx->stream_res.stream_enc) + return DC_NO_STREAM_ENG_RESOURCE; + + update_stream_engine_usage( + &context->res_ctx, pool, + pipe_ctx->stream_res.stream_enc, + true); + + /* TODO: Add check if ASIC support and EDID audio */ + if (!stream->sink->converter_disable_audio && + dc_is_audio_capable_signal(pipe_ctx->stream->signal) && + stream->audio_info.mode_count) { + pipe_ctx->stream_res.audio = find_first_free_audio( + &context->res_ctx, pool); + + /* + * Audio assigned in order first come first get. + * There are asics which has number of audio + * resources less then number of pipes + */ + if (pipe_ctx->stream_res.audio) + update_audio_usage(&context->res_ctx, pool, + pipe_ctx->stream_res.audio, true); + } - pipe_ctx->stream = stream; - copy_pipe_ctx(old_pipe_ctx, pipe_ctx); + for (i = 0; i < context->stream_count; i++) + if (context->streams[i] == stream) { + context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; + return DC_OK; + } - /* Split pipe resource, do not acquire back end */ - if (!pipe_ctx->stream_res.stream_enc) - continue; + DC_ERROR("Stream %p not found in new ctx!\n", stream); + return DC_ERROR_UNEXPECTED; +} - set_stream_engine_in_use( - &context->res_ctx, pool, - pipe_ctx->stream_res.stream_enc); +/* first stream in the context is used to populate the rest */ +void validate_guaranteed_copy_streams( + struct validate_context *context, + int max_streams) +{ + int i; - /* Switch to dp clock source only if there is - * no non dp stream that shares the same timing - * with the dp stream. - */ - if (dc_is_dp_signal(pipe_ctx->stream->signal) && - !find_pll_sharable_stream(stream, context)) - pipe_ctx->clock_source = pool->dp_clock_source; + for (i = 1; i < max_streams; i++) { + context->streams[i] = context->streams[0]; - resource_reference_clock_source( - &context->res_ctx, pool, - pipe_ctx->clock_source); + copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], + &context->res_ctx.pipe_ctx[i]); + context->res_ctx.pipe_ctx[i].stream = + context->res_ctx.pipe_ctx[0].stream; - set_audio_in_use(&context->res_ctx, pool, - pipe_ctx->stream_res.audio); - } + dc_stream_retain(context->streams[i]); + context->stream_count++; } +} - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - struct pipe_ctx *pipe_ctx = NULL; - int pipe_idx = -1; +void dc_resource_validate_ctx_copy_construct_current( + const struct dc *dc, + struct validate_context *dst_ctx) +{ + dc_resource_validate_ctx_copy_construct(dc->current_context, dst_ctx); +} - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - /* acquire new resources */ - pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (pipe_idx < 0) - acquire_first_split_pipe(&context->res_ctx, pool, stream); -#endif - if (pipe_idx < 0) - return DC_NO_CONTROLLER_RESOURCE; +bool dc_validate_with_context( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *context) +{ + int i, j; + enum dc_status res = DC_ERROR_UNEXPECTED; + bool found = false; + int old_stream_count = context->stream_count; + struct dc_stream_state *del_streams[MAX_PIPES] = { 0 }; + struct dc_stream_state *add_streams[MAX_PIPES] = { 0 }; + int del_streams_count = 0; + int add_streams_count = 0; - pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; - pipe_ctx->stream_res.stream_enc = - find_first_free_match_stream_enc_for_link( - &context->res_ctx, pool, stream); + /* First remove from context all deleted streams */ + for (i = 0; i < old_stream_count; i++) { + struct dc_stream_state *stream = context->streams[i]; + + for (j = 0; j < set_count; j++) { + if (stream == set[j].stream) { + found = true; + break; + } + } - if (!pipe_ctx->stream_res.stream_enc) - return DC_NO_STREAM_ENG_RESOURCE; + if (!found) + del_streams[del_streams_count++] = stream; - set_stream_engine_in_use( - &context->res_ctx, pool, - pipe_ctx->stream_res.stream_enc); + found = false; + } - /* TODO: Add check if ASIC support and EDID audio */ - if (!stream->sink->converter_disable_audio && - dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->audio_info.mode_count) { - pipe_ctx->stream_res.audio = find_first_free_audio( - &context->res_ctx, pool); + /* Now add new ones */ + for (i = 0; i < set_count; i++) { + struct dc_stream_state *stream = set[i].stream; - /* - * Audio assigned in order first come first get. - * There are asics which has number of audio - * resources less then number of pipes - */ - if (pipe_ctx->stream_res.audio) - set_audio_in_use( - &context->res_ctx, pool, - pipe_ctx->stream_res.audio); + for (j = 0; j < old_stream_count; j++) { + if (stream == context->streams[j]) { + found = true; + break; + } } - context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; + if (!found) + add_streams[add_streams_count++] = stream; + + found = false; } - return DC_OK; + for (i = 0; i < del_streams_count; i++) + if (!dc_remove_stream_from_ctx(dc, context, del_streams[i])) + goto fail; + + for (i = 0; i < add_streams_count; i++) + if (!dc_add_stream_to_ctx(dc, context, add_streams[i])) + goto fail; + + if (!dc_validate_global_state(dc, set, set_count, context)) + goto fail; + + res = DC_OK; + +fail: + if (res != DC_OK) { + dm_logger_write(dc->ctx->logger, LOG_WARNING, + "%s:resource validation failed, dc_status:%d\n", + __func__, + res); +} + return res == DC_OK; } -/* first stream in the context is used to populate the rest */ -void validate_guaranteed_copy_streams( - struct validate_context *context, - int max_streams) +bool dc_validate_global_state( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *new_ctx) { - int i; + enum dc_status result = DC_ERROR_UNEXPECTED; + struct dc_context *dc_ctx = dc->ctx; + struct validate_context *old_context = dc->current_context; + int i, j; - for (i = 1; i < max_streams; i++) { - context->streams[i] = context->streams[0]; + if (dc->res_pool->funcs->validate_global && + dc->res_pool->funcs->validate_global(dc, set, set_count, + old_context, new_ctx) != DC_OK) + return false; - copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], - &context->res_ctx.pipe_ctx[i]); - context->res_ctx.pipe_ctx[i].stream = - context->res_ctx.pipe_ctx[0].stream; + /* TODO without this SWDEV-114774 brakes */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; - dc_stream_retain(context->streams[i]); - context->stream_count++; + if (pipe_ctx->top_pipe) + memset(pipe_ctx, 0, sizeof(*pipe_ctx)); + } + + for (i = 0; new_ctx && i < new_ctx->stream_count; i++) { + struct dc_stream_state *stream = new_ctx->streams[i]; + + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; + + if (pipe_ctx->stream != stream) + continue; + + /* Switch to dp clock source only if there is + * no non dp stream that shares the same timing + * with the dp stream. + */ + if (dc_is_dp_signal(pipe_ctx->stream->signal) && + !find_pll_sharable_stream(stream, new_ctx)) { + + resource_unreference_clock_source( + &new_ctx->res_ctx, + dc->res_pool, + &pipe_ctx->clock_source); + pipe_ctx->clock_source = dc->res_pool->dp_clock_source; + resource_reference_clock_source( + &new_ctx->res_ctx, + dc->res_pool, + pipe_ctx->clock_source); + } + } + } + + /*TODO This should be ok */ + /* Split pipe resource, do not acquire back end */ + + if (!resource_validate_attach_surfaces( + set, set_count, old_context, new_ctx, dc->res_pool)) { + DC_ERROR("Failed to attach surface to stream!\n"); + return DC_FAIL_ATTACH_SURFACES; } + + result = resource_build_scaling_params_for_context(dc, new_ctx); + + if (result == DC_OK) + if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx)) + result = DC_FAIL_BANDWIDTH_VALIDATE; + + return result; } static void patch_gamut_packet_checksum( @@ -2318,54 +2524,40 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) enum dc_status resource_map_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { - int i, j; - const struct resource_pool *pool = dc->res_pool; - /* acquire new resources */ - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; + const struct resource_pool *pool = dc->res_pool; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( + &context->res_ctx, stream); - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = pool->dp_clock_source; + else { + pipe_ctx->clock_source = NULL; - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = pool->dp_clock_source; - else { - pipe_ctx->clock_source = NULL; - - if (!dc->config.disable_disp_pll_sharing) - resource_find_used_clk_src_for_sharing( - &context->res_ctx, - pipe_ctx); - - if (pipe_ctx->clock_source == NULL) - pipe_ctx->clock_source = - dc_resource_find_first_free_pll( - &context->res_ctx, - pool); - } + if (!dc->config.disable_disp_pll_sharing) + resource_find_used_clk_src_for_sharing( + &context->res_ctx, + pipe_ctx); - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (pipe_ctx->clock_source == NULL) + pipe_ctx->clock_source = + dc_resource_find_first_free_pll( + &context->res_ctx, + pool); + } - resource_reference_clock_source( - &context->res_ctx, pool, - pipe_ctx->clock_source); + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - /* only one cs per stream regardless of mpo */ - break; - } - } + resource_reference_clock_source( + &context->res_ctx, pool, + pipe_ctx->clock_source); return DC_OK; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 629aa3c323ca..2b4fc6616243 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -618,6 +618,16 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *h_position, uint32_t *v_position); +bool dc_remove_stream_from_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream); + +bool dc_add_stream_to_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream); + /* * Structure to store surface/stream associations for validation */ @@ -630,16 +640,18 @@ struct dc_validation_set { bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); -/* - * This function takes a set of resources and checks that they are cofunctional. - * - * After this call: - * No hardware is programmed for call. Only validation is done. - */ -struct validate_context *dc_get_validate_context( + +bool dc_validate_with_context( struct dc *dc, const struct dc_validation_set set[], - uint8_t set_count); + int set_count, + struct validate_context *context); + +bool dc_validate_global_state( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *new_ctx); bool dc_validate_resources( struct dc *dc, @@ -662,6 +674,10 @@ void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, struct validate_context *dst_ctx); +void dc_resource_validate_ctx_copy_construct_current( + const struct dc *dc, + struct validate_context *dst_ctx); + void dc_resource_validate_ctx_destruct(struct validate_context *context); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index b2b03633eb4f..c9dad4e2a7c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -654,35 +654,20 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; - - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -719,48 +704,17 @@ static bool dce100_validate_surface_sets( return true; } -enum dc_status dce100_validate_with_context( +enum dc_status dce100_validate_global( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *old_context, + struct validate_context *context) { - struct dc_context *dc_ctx = dc->ctx; - enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce100_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - - if (result == DC_OK) - result = resource_map_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); - - if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - if (!dce100_validate_bandwidth(dc, context)) - result = DC_FAIL_BANDWIDTH_VALIDATE; - - return result; + return DC_OK; } enum dc_status dce100_validate_guaranteed( @@ -774,13 +728,13 @@ enum dc_status dce100_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_clock_resources(dc, context, NULL); + result = resource_map_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -816,10 +770,10 @@ enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state) static const struct resource_funcs dce100_res_pool_funcs = { .destroy = dce100_destroy_resource_pool, .link_enc_create = dce100_link_encoder_create, - .validate_with_context = dce100_validate_with_context, .validate_guaranteed = dce100_validate_guaranteed, .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, + .validate_global = dce100_validate_global }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 2154c2e567f2..d682180f2eaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -774,41 +774,26 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; - - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + if (!is_surface_pixel_format_supported(pipe_ctx, + dc->res_pool->underlay_pipe_index)) + return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; - if (!is_surface_pixel_format_supported(pipe_ctx, - dc->res_pool->underlay_pipe_index)) - return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + if (status != DC_OK) + return status; - if (status != DC_OK) - return status; + /* TODO: validate audio ASIC caps, encoder */ - /* TODO: validate audio ASIC caps, encoder */ - - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -927,48 +912,17 @@ static bool dce110_validate_surface_sets( return true; } -static enum dc_status dce110_validate_with_context( +enum dc_status dce110_validate_global( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *old_context, + struct validate_context *context) { - struct dc_context *dc_ctx = dc->ctx; - enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce110_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - - if (result == DC_OK) - result = resource_map_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); - - if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - if (!dce110_validate_bandwidth(dc, context)) - result = DC_FAIL_BANDWIDTH_VALIDATE; - - return result; + return DC_OK; } static enum dc_status dce110_validate_guaranteed( @@ -982,13 +936,13 @@ static enum dc_status dce110_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_clock_resources(dc, context, NULL); + result = resource_map_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -1078,10 +1032,10 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce110_res_pool_funcs = { .destroy = dce110_destroy_resource_pool, .link_enc_create = dce110_link_encoder_create, - .validate_with_context = dce110_validate_with_context, .validate_guaranteed = dce110_validate_guaranteed, .validate_bandwidth = dce110_validate_bandwidth, .acquire_idle_pipe_for_layer = dce110_acquire_underlay, + .validate_global = dce110_validate_global }; static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 89a8dfa68c01..85a396ef5aa5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -725,35 +725,20 @@ static struct clock_source *find_matching_pll( static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + if (status != DC_OK) + return status; - if (status != DC_OK) - return status; - - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -839,45 +824,32 @@ bool dce112_validate_bandwidth( enum dc_status resource_map_phy_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { - uint8_t i, j; /* acquire new resources */ - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( + &context->res_ctx, stream); - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = - dc->res_pool->dp_clock_source; - else - pipe_ctx->clock_source = find_matching_pll( - &context->res_ctx, dc->res_pool, - stream); + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = + dc->res_pool->dp_clock_source; + else + pipe_ctx->clock_source = find_matching_pll( + &context->res_ctx, dc->res_pool, + stream); - resource_reference_clock_source( - &context->res_ctx, - dc->res_pool, - pipe_ctx->clock_source); + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - /* only one cs per stream regardless of mpo */ - break; - } - } + resource_reference_clock_source( + &context->res_ctx, + dc->res_pool, + pipe_ctx->clock_source); return DC_OK; } @@ -903,46 +875,21 @@ static bool dce112_validate_surface_sets( return true; } -enum dc_status dce112_validate_with_context( +enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream) { - struct dc_context *dc_ctx = dc->ctx; enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce112_validate_surface_sets(set, set_count)) - return DC_FAIL_SURFACE_VALIDATE; - - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); + result = resource_map_pool_resources(dc, new_ctx, dc_stream); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } + result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - if (!dce112_validate_bandwidth(dc, context)) - result = DC_FAIL_BANDWIDTH_VALIDATE; + result = build_mapped_resource(dc, new_ctx, dc_stream); return result; } @@ -958,13 +905,13 @@ enum dc_status dce112_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, stream); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context, NULL); + result = resource_map_phy_clock_resources(dc, context, stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -979,6 +926,19 @@ enum dc_status dce112_validate_guaranteed( return result; } +enum dc_status dce112_validate_global( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *old_context, + struct validate_context *context) +{ + if (!dce112_validate_surface_sets(set, set_count)) + return DC_FAIL_SURFACE_VALIDATE; + + return DC_OK; +} + static void dce112_destroy_resource_pool(struct resource_pool **pool) { struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); @@ -991,10 +951,11 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce112_res_pool_funcs = { .destroy = dce112_destroy_resource_pool, .link_enc_create = dce112_link_encoder_create, - .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_plane = dce100_validate_plane + .validate_plane = dce100_validate_plane, + .add_stream_to_ctx = dce112_add_stream_to_ctx, + .validate_global = dce112_validate_global }; static void bw_calcs_data_update_from_pplib(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index 69f8f689196d..f1834bfe3d1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -51,6 +51,11 @@ bool dce112_validate_bandwidth( struct dc *dc, struct validate_context *context); +enum dc_status dce112_add_stream_to_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream); + #endif /* __DC_RESOURCE_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b8fcdff40db3..e5d2d98982f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -698,10 +698,10 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce120_res_pool_funcs = { .destroy = dce120_destroy_resource_pool, .link_enc_create = dce120_link_encoder_create, - .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_plane = dce100_validate_plane + .validate_plane = dce100_validate_plane, + .add_stream_to_ctx = dce112_add_stream_to_ctx }; static void bw_calcs_data_update_from_pplib(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 838bfdaee009..ac3f42a44030 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -686,35 +686,20 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; - - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -751,47 +736,17 @@ static bool dce80_validate_surface_sets( return true; } -enum dc_status dce80_validate_with_context( +enum dc_status dce80_validate_global( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *old_context, + struct validate_context *context) { - struct dc_context *dc_ctx = dc->ctx; - enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce80_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - - if (result == DC_OK) - result = resource_map_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); - - if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - result = dce80_validate_bandwidth(dc, context); - - return result; + return DC_OK; } enum dc_status dce80_validate_guaranteed( @@ -805,13 +760,13 @@ enum dc_status dce80_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_clock_resources(dc, context, NULL); + result = resource_map_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -837,10 +792,10 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce80_res_pool_funcs = { .destroy = dce80_destroy_resource_pool, .link_enc_create = dce80_link_encoder_create, - .validate_with_context = dce80_validate_with_context, .validate_guaranteed = dce80_validate_guaranteed, .validate_bandwidth = dce80_validate_bandwidth, - .validate_plane = dce100_validate_plane + .validate_plane = dce100_validate_plane, + .validate_global = dce80_validate_global }; static bool dce80_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 954c234090db..ee43cbc70c8a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -48,6 +48,7 @@ #include "dce/dce_hwseq.h" #include "../virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" +#include "dce112/dce112_resource.h" #include "vega10/soc15ip.h" @@ -840,17 +841,15 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; - - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - if (old_context && resource_is_stream_unchanged(old_context, stream)) { + /*TODO Seems unneeded anymore */ + /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { - /* todo: shouldn't have to copy missing parameter here */ + todo: shouldn't have to copy missing parameter here resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); stream->clamping.pixel_encoding = @@ -863,68 +862,34 @@ static enum dc_status build_mapped_resource( continue; } } + */ - for (j = 0; j < dc->res_pool->pipe_count ; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + status = build_pipe_hw_param(pipe_ctx); - status = build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; - - /* do not need to validate non root pipes */ - break; - } - } + if (status != DC_OK) + return status; return DC_OK; } -enum dc_status dcn10_validate_with_context( +enum dc_status dcn10_add_stream_to_ctx( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream) { - enum dc_status result = DC_OK; - int i; - - if (set_count == 0) - return result; - - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - if (result != DC_OK) - return result; - - result = resource_map_phy_clock_resources(dc, context, old_context); - if (result != DC_OK) - return result; + enum dc_status result = DC_ERROR_UNEXPECTED; - result = build_mapped_resource(dc, context, old_context); - if (result != DC_OK) - return result; + result = resource_map_pool_resources(dc, new_ctx, dc_stream); - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) - return DC_FAIL_ATTACH_SURFACES; + if (result == DC_OK) + result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); - result = resource_build_scaling_params_for_context(dc, context); - if (result != DC_OK) - return result; - if (!dcn_validate_bandwidth(dc, context)) - return DC_FAIL_BANDWIDTH_VALIDATE; + if (result == DC_OK) + result = build_mapped_resource(dc, new_ctx, dc_stream); return result; } @@ -940,13 +905,13 @@ enum dc_status dcn10_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context, NULL); + result = resource_map_phy_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -1226,10 +1191,10 @@ static struct dc_cap_funcs cap_funcs = { static struct resource_funcs dcn10_res_pool_funcs = { .destroy = dcn10_destroy_resource_pool, .link_enc_create = dcn10_link_encoder_create, - .validate_with_context = dcn10_validate_with_context, .validate_guaranteed = dcn10_validate_guaranteed, .validate_bandwidth = dcn_validate_bandwidth, .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, + .add_stream_to_ctx = dcn10_add_stream_to_ctx }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index a3f0039088ab..9a3239028377 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -87,12 +87,6 @@ struct resource_funcs { void (*destroy)(struct resource_pool **pool); struct link_encoder *(*link_enc_create)( const struct encoder_init_data *init); - enum dc_status (*validate_with_context)( - struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context); enum dc_status (*validate_guaranteed)( struct dc *dc, @@ -103,11 +97,24 @@ struct resource_funcs { struct dc *dc, struct validate_context *context); + enum dc_status (*validate_global)( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *old_context, + struct validate_context *context); + struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, struct dc_stream_state *stream); + enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); + + enum dc_status (*add_stream_to_ctx)( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 9085ec7ceac7..ebc0f5b02365 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -82,7 +82,7 @@ void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context); + struct dc_stream_state *stream); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); @@ -150,12 +150,12 @@ void resource_validate_ctx_update_pointer_after_copy( enum dc_status resource_map_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context); + struct dc_stream_state *stream); enum dc_status resource_map_phy_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context); + struct dc_stream_state *stream); bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, -- cgit v1.2.3-59-g8ed1b From 1bd4653a29a49f6fd732cd294e0f87b15feec5a8 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Wed, 16 Aug 2017 19:06:49 -0400 Subject: drm/amd/display: increase polling interval for fbc status update 1.Fixing error message: "wait counter exceeded, changes to HW not applied" 2. Added "FBC status changed to 0/1" logs Signed-off-by: Roman Li Reviewed-by: Bhawanpreet Lakha Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 9759d8e790a3..2e97e5757fb9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -115,7 +115,7 @@ static void wait_for_fbc_state_changed( FBC_STATUS, FBC_ENABLE_STATUS) == enabled) break; - udelay(10); + msleep(10); counter++; } @@ -124,7 +124,13 @@ static void wait_for_fbc_state_changed( cp110->base.ctx->logger, LOG_WARNING, "%s: wait counter exceeded, changes to HW not applied", __func__); + } else { + dm_logger_write( + cp110->base.ctx->logger, LOG_SYNC, + "FBC status changed to %d", enabled); } + + } void dce110_compressor_power_up_fbc(struct compressor *compressor) -- cgit v1.2.3-59-g8ed1b From 3005e437e70fd4d1da64d91b4ef027f62d3b9a41 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Thu, 17 Aug 2017 16:24:11 -0400 Subject: drm/amd/display: re-enable audio after LT test [Description] Audio should be attached to the same pipe once it is attached. We will not remove audio endpoint in disable stream. We will reeanble the audio after automated link training test Signed-off-by: Wenjing Liu Reviewed-by: Tony Cheng Reviewed-by: Charlene Liu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 14 ++++++++++++++ .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 -- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index e12f1f9fb590..3a5abd92036a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -310,6 +310,20 @@ void dp_retrain_link_dp_test(struct dc_link *link, link->dc->hwss.unblank_stream(&pipes[i], link_setting); + + if (pipes[i].stream_res.audio) { + /* notify audio driver for + * audio modes of monitor */ + pipes[i].stream_res.audio->funcs->az_enable( + pipes[i].stream_res.audio); + + /* un-mute audio */ + /* TODO: audio should be per stream rather than + * per link */ + pipes[i].stream_res.stream_enc->funcs-> + audio_mute_control( + pipes[i].stream_res.stream_enc, false); + } } } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e6c6f1108078..7516c198d13a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -758,8 +758,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( pipe_ctx->stream_res.stream_enc); - pipe_ctx->stream_res.audio = NULL; - /* TODO: notify audio driver for if audio modes list changed * add audio mode list change flag */ /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, -- cgit v1.2.3-59-g8ed1b From a0c38ebaa1fe99ea8d112d808d84a2e75194fcf6 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 21 Aug 2017 12:59:41 -0400 Subject: drm/amd/display: write dpcd 0x600 to 2 for DP/eDP when powerdown Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++++++++- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index ee9b98472029..0bdd41ca8799 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1977,7 +1977,7 @@ bool dc_link_setup_psr(struct dc_link *link, #if defined(CONFIG_DRM_AMD_DC_DCN1_0) /*skip power down the single pipe since it blocks the cstate*/ if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev)) - psr_context->psr_level.bits.SKIP_SINGLE_OTG_DISABLE = false; + psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; #endif /* SMU will perform additional powerdown sequence. diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 7516c198d13a..8ba61b9b8792 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1147,8 +1147,16 @@ static enum dc_status apply_single_controller_ctx_to_hw( static void power_down_encoders(struct dc *dc) { int i; - + enum connector_id connector_id; for (i = 0; i < dc->link_count; i++) { + connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); + if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || + (connector_id == CONNECTOR_ID_EDP)) { + + if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) + dp_receiver_power_ctrl(dc->links[i], false); + } + dc->links[i]->link_enc->funcs->disable_output( dc->links[i]->link_enc, SIGNAL_TYPE_NONE); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index d710f6e6dc07..ac418fd83894 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -67,5 +67,6 @@ void dce110_fill_display_configs( uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context); +void dp_receiver_power_ctrl(struct dc_link *link, bool on); #endif /* __DC_HWSS_DCE110_H__ */ -- cgit v1.2.3-59-g8ed1b From 19f89e2392e692208a0a00465d30b2b2bf43e9a9 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 11 Aug 2017 10:43:45 -0400 Subject: drm/amd/display: Per plane validation context build. Introduce add/remove plane to/from context. Make DC wrapper to use them in WIndows/Diags. Use them in dc_update_surface_to_stream. Call add/remove plane from Linux DM. Remove dc_validation_set from dc_validate_global_state interface and by this remove clean Linux DM from using it. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 165 ++++------ drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 362 +++++++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 37 ++- .../drm/amd/display/dc/dce100/dce100_resource.c | 16 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 26 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 16 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 - 9 files changed, 353 insertions(+), 300 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e037ed85a5cc..e8835e751702 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4304,77 +4304,6 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector dm_force_atomic_commit(&aconnector->base); } -static uint32_t add_val_sets_plane( - struct dc_validation_set *val_sets, - uint32_t set_count, - const struct dc_stream_state *stream, - struct dc_plane_state *plane_state) -{ - uint32_t i = 0, j = 0; - - while (i < set_count) { - if (val_sets[i].stream == stream) { - while (val_sets[i].plane_states[j]) - j++; - break; - } - ++i; - } - - val_sets[i].plane_states[j] = plane_state; - val_sets[i].plane_count++; - - return val_sets[i].plane_count; -} - -static uint32_t update_in_val_sets_stream( - struct dc_validation_set *val_sets, - uint32_t set_count, - struct dc_stream_state *old_stream, - struct dc_stream_state *new_stream, - struct drm_crtc *crtc) -{ - uint32_t i = 0; - - while (i < set_count) { - if (val_sets[i].stream == old_stream) - break; - ++i; - } - - val_sets[i].stream = new_stream; - - if (i == set_count) - /* nothing found. add new one to the end */ - return set_count + 1; - - return set_count; -} - -static uint32_t remove_from_val_sets( - struct dc_validation_set *val_sets, - uint32_t set_count, - const struct dc_stream_state *stream) -{ - int i; - - for (i = 0; i < set_count; i++) - if (val_sets[i].stream == stream) - break; - - if (i == set_count) { - /* nothing found */ - return set_count; - } - - set_count--; - - for (; i < set_count; i++) - val_sets[i] = val_sets[i + 1]; - - return set_count; -} - /*` * Grabs all modesetting locks to serialize against any blocking commits, * Waits for completion of all non blocking commits. @@ -4438,10 +4367,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dc *dc = adev->dm.dc; struct drm_connector *connector; struct drm_connector_state *conn_state; - int set_count; - struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + bool pflip_needed = !state->allow_modeset; /* * This bool will be set for true for any modeset/reset @@ -4460,16 +4388,44 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, ASSERT(dm_state->context); dc_resource_validate_ctx_copy_construct_current(dc, dm_state->context); - /* copy existing configuration */ - set_count = 0; - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + /* Remove exiting planes if they are disabled or their CRTC is updated */ + for_each_crtc_in_state(state, crtc, crtc_state, i) { + new_acrtc_state = to_dm_crtc_state(crtc_state); - old_acrtc_state = to_dm_crtc_state(crtc->state); + if (pflip_needed) + continue; - if (old_acrtc_state->stream) { - dc_stream_retain(old_acrtc_state->stream); - set[set_count].stream = old_acrtc_state->stream; - ++set_count; + for_each_plane_in_state(state, plane, plane_state, j) { + struct drm_crtc *plane_crtc = plane_state->crtc; + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + + if (plane->type == DRM_PLANE_TYPE_CURSOR) + continue; + + if (crtc != plane_crtc || !dm_plane_state->dc_state) + continue; + + WARN_ON(!new_acrtc_state->stream); + + if (drm_atomic_plane_disabling(plane->state, plane_state) || + drm_atomic_crtc_needs_modeset(crtc_state)) { + if (!dc_remove_plane_from_context( + dc, + new_acrtc_state->stream, + dm_plane_state->dc_state, + dm_state->context)) { + + ret = EINVAL; + goto fail; + } + + } + + dc_plane_state_release(dm_plane_state->dc_state); + dm_plane_state->dc_state = NULL; + + DRM_DEBUG_KMS("Disabling DRM plane: %d on DRM crtc %d\n", + plane->base.id, crtc->base.id); } } @@ -4513,11 +4469,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } - set_count = remove_from_val_sets( - set, - set_count, - new_acrtc_state->stream); - dc_stream_release(new_acrtc_state->stream); new_acrtc_state->stream = NULL; @@ -4576,13 +4527,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, new_acrtc_state->stream = new_stream; - set_count = update_in_val_sets_stream( - set, - set_count, - old_acrtc_state->stream, - new_acrtc_state->stream, - crtc); - if (!dc_add_stream_to_ctx( dc, dm_state->context, @@ -4639,32 +4583,32 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } + /* Add new planes */ for_each_crtc_in_state(state, crtc, crtc_state, i) { new_acrtc_state = to_dm_crtc_state(crtc_state); + if (pflip_needed) + continue; + for_each_plane_in_state(state, plane, plane_state, j) { struct drm_crtc *plane_crtc = plane_state->crtc; - struct drm_framebuffer *fb = plane_state->fb; - bool pflip_needed; struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); /*TODO Implement atomic check for cursor plane */ if (plane->type == DRM_PLANE_TYPE_CURSOR) continue; - if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active) + if (crtc != plane_crtc) continue; - WARN_ON(!new_acrtc_state->stream); - - pflip_needed = !state->allow_modeset; - if (!pflip_needed) { + if (!drm_atomic_plane_disabling(plane->state, plane_state)) { struct dc_plane_state *dc_plane_state; + WARN_ON(!new_acrtc_state->stream); + dc_plane_state = dc_create_plane_state(dc); - if (dm_plane_state->dc_state) - dc_plane_state_release(dm_plane_state->dc_state); + WARN_ON(dm_plane_state->dc_state); dm_plane_state->dc_state = dc_plane_state; @@ -4677,10 +4621,17 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - add_val_sets_plane(set, - set_count, - new_acrtc_state->stream, - dc_plane_state); + + if (!dc_add_plane_to_context( + dc, + new_acrtc_state->stream, + dc_plane_state, + dm_state->context)) { + + ret = EINVAL; + goto fail; + } + lock_and_validation_needed = true; } @@ -4708,7 +4659,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - if (!dc_validate_global_state(dc, set, set_count, dm_state->context)) { + if (!dc_validate_global_state(dc, dm_state->context)) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ab2b8f23b20a..79980cb0900c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1305,10 +1305,16 @@ void dc_update_planes_and_stream(struct dc *dc, dc_resource_validate_ctx_copy_construct( core_dc->current_context, context); + /*remove old surfaces from context */ + if (!dc_rem_all_planes_for_stream(dc, stream, context)) { + + BREAK_TO_DEBUGGER(); + goto fail; + } + /* add surface to context */ - if (!resource_attach_surfaces_to_context( - new_planes, surface_count, stream, - context, core_dc->res_pool)) { + if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) { + BREAK_TO_DEBUGGER(); goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fbfe15f783c0..6eee1b1a563e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -946,6 +946,26 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( return NULL; } +static struct pipe_ctx *resource_get_tail_pipe_for_stream( + struct resource_context *res_ctx, + struct dc_stream_state *stream) +{ + struct pipe_ctx *head_pipe, *tail_pipe; + head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); + + if (!head_pipe) + return NULL; + + tail_pipe = head_pipe->bottom_pipe; + + while (tail_pipe) { + head_pipe = tail_pipe; + tail_pipe = tail_pipe->bottom_pipe; + } + + return head_pipe; +} + /* * A free_pipe for a stream is defined here as a pipe * that has no surface attached yet @@ -990,22 +1010,6 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( } -static void release_free_pipes_for_stream( - struct resource_context *res_ctx, - struct dc_stream_state *stream) -{ - int i; - - for (i = MAX_PIPES - 1; i >= 0; i--) { - /* never release the topmost pipe*/ - if (res_ctx->pipe_ctx[i].stream == stream && - res_ctx->pipe_ctx[i].top_pipe && - !res_ctx->pipe_ctx[i].plane_state) { - memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx)); - } - } -} - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) static int acquire_first_split_pipe( struct resource_context *res_ctx, @@ -1040,96 +1044,235 @@ static int acquire_first_split_pipe( } #endif -bool resource_attach_surfaces_to_context( - struct dc_plane_state * const *plane_states, - int surface_count, +bool dc_add_plane_to_context( + const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context, - const struct resource_pool *pool) + struct dc_plane_state *plane_state, + struct validate_context *context) { int i; - struct pipe_ctx *tail_pipe; + struct resource_pool *pool = dc->res_pool; + struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; struct dc_stream_status *stream_status = NULL; + for (i = 0; i < context->stream_count; i++) + if (context->streams[i] == stream) { + stream_status = &context->stream_status[i]; + break; + } + if (stream_status == NULL) { + dm_error("Existing stream not found; failed to attach surface!\n"); + return false; + } + + + if (stream_status->plane_count == MAX_SURFACE_NUM) { + dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", + plane_state, MAX_SURFACE_NUM); + return false; + } + + head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); + + if (!head_pipe) { + dm_error("Head pipe not found for stream_state %p !\n", stream); + return false; + } + + /* retain new surfaces */ + dc_plane_state_retain(plane_state); + + free_pipe = acquire_free_pipe_for_stream(context, pool, stream); - if (surface_count > MAX_SURFACE_NUM) { - dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n", - surface_count, MAX_SURFACE_NUM); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (!free_pipe) { + int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); + if (pipe_idx >= 0) + free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; + } +#endif + if (!free_pipe) { + stream_status->plane_states[i] = NULL; return false; } + free_pipe->plane_state = plane_state; + + if (head_pipe != free_pipe) { + + tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream); + ASSERT(tail_pipe); + + free_pipe->stream_res.tg = tail_pipe->stream_res.tg; + free_pipe->stream_res.opp = tail_pipe->stream_res.opp; + free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; + free_pipe->stream_res.audio = tail_pipe->stream_res.audio; + free_pipe->clock_source = tail_pipe->clock_source; + free_pipe->top_pipe = tail_pipe; + tail_pipe->bottom_pipe = free_pipe; + } + + /* assign new surfaces*/ + stream_status->plane_states[stream_status->plane_count] = plane_state; + + stream_status->plane_count++; + + return true; +} + +bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct validate_context *context) +{ + int i; + struct dc_stream_status *stream_status = NULL; + struct resource_pool *pool = dc->res_pool; + for (i = 0; i < context->stream_count; i++) if (context->streams[i] == stream) { stream_status = &context->stream_status[i]; break; } + if (stream_status == NULL) { - dm_error("Existing stream not found; failed to attach surfaces\n"); + dm_error("Existing stream not found; failed to remove plane.\n"); return false; } - /* retain new surfaces */ - for (i = 0; i < surface_count; i++) - dc_plane_state_retain(plane_states[i]); - - /* detach surfaces from pipes */ - for (i = 0; i < pool->pipe_count; i++) - if (context->res_ctx.pipe_ctx[i].stream == stream) { - context->res_ctx.pipe_ctx[i].plane_state = NULL; - context->res_ctx.pipe_ctx[i].bottom_pipe = NULL; - } + /* release pipe for plane*/ + for (i = pool->pipe_count - 1; i >= 0; i--) { + struct pipe_ctx *pipe_ctx; - /* release existing surfaces*/ - for (i = 0; i < stream_status->plane_count; i++) - dc_plane_state_release(stream_status->plane_states[i]); + if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) { + pipe_ctx = &context->res_ctx.pipe_ctx[i]; - for (i = surface_count; i < stream_status->plane_count; i++) - stream_status->plane_states[i] = NULL; + if (pipe_ctx->top_pipe) + pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; - tail_pipe = NULL; - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *plane_state = plane_states[i]; - struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - context, pool, stream); + /* Second condition is to avoid setting NULL to top pipe + * of tail pipe making it look like head pipe in subsequent + * deletes + */ + if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) + pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (!free_pipe) { - int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); - if (pipe_idx >= 0) - free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; - } -#endif - if (!free_pipe) { - stream_status->plane_states[i] = NULL; - return false; + /* + * For head pipe detach surfaces from pipe for tail + * pipe just zero it out + */ + if (!pipe_ctx->top_pipe) { + pipe_ctx->plane_state = NULL; + pipe_ctx->bottom_pipe = NULL; + } else { + memset(pipe_ctx, 0, sizeof(*pipe_ctx)); + } } + } + - free_pipe->plane_state = plane_state; + for (i = 0; i < stream_status->plane_count; i++) { + if (stream_status->plane_states[i] == plane_state) { - if (tail_pipe) { - free_pipe->stream_res.tg = tail_pipe->stream_res.tg; - free_pipe->stream_res.opp = tail_pipe->stream_res.opp; - free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; - free_pipe->stream_res.audio = tail_pipe->stream_res.audio; - free_pipe->clock_source = tail_pipe->clock_source; - free_pipe->top_pipe = tail_pipe; - tail_pipe->bottom_pipe = free_pipe; + dc_plane_state_release(stream_status->plane_states[i]); + break; } + } - tail_pipe = free_pipe; + if (i == stream_status->plane_count) { + dm_error("Existing plane_state not found; failed to detach it!\n"); + return false; } - release_free_pipes_for_stream(&context->res_ctx, stream); + stream_status->plane_count--; - /* assign new surfaces*/ - for (i = 0; i < surface_count; i++) - stream_status->plane_states[i] = plane_states[i]; + /* Trim back arrays */ + for (i = 0; i < stream_status->plane_count; i++) + stream_status->plane_states[i] = stream_status->plane_states[i + 1]; + + stream_status->plane_states[stream_status->plane_count] = NULL; + + return true; +} + +bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct validate_context *context) +{ + int i, old_plane_count; + struct dc_stream_status *stream_status = NULL; + struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; + + for (i = 0; i < context->stream_count; i++) + if (context->streams[i] == stream) { + stream_status = &context->stream_status[i]; + break; + } + + if (stream_status == NULL) { + dm_error("Existing stream %p not found!\n", stream); + return false; + } + + old_plane_count = stream_status->plane_count; - stream_status->plane_count = surface_count; + for (i = 0; i < old_plane_count; i++) + del_planes[i] = stream_status->plane_states[i]; + + for (i = 0; i < old_plane_count; i++) + if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) + return false; return true; } +static bool add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + const struct dc_validation_set set[], + int set_count, + struct validate_context *context) +{ + int i, j; + + for (i = 0; i < set_count; i++) + if (set[i].stream == stream) + break; + + if (i == set_count) { + dm_error("Stream %p not found in set!\n", stream); + return false; + } + + for (j = 0; j < set[i].plane_count; j++) + if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) + return false; + + return true; +} + +bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, + struct validate_context *context) +{ + struct dc_validation_set set; + int i; + + set.stream = stream; + set.plane_count = plane_count; + + for (i = 0; i < plane_count; i++) + set.plane_states[i] = plane_states[i]; + + return add_all_planes_for_stream(dc, stream, &set, 1, context); +} + + static bool is_timing_changed(struct dc_stream_state *cur_stream, struct dc_stream_state *new_stream) @@ -1178,41 +1321,6 @@ bool dc_is_stream_unchanged( return true; } -bool resource_validate_attach_surfaces( - const struct dc_validation_set set[], - int set_count, - const struct validate_context *old_context, - struct validate_context *context, - const struct resource_pool *pool) -{ - int i, j; - - for (i = 0; i < set_count; i++) { - for (j = 0; old_context && j < old_context->stream_count; j++) - if (dc_is_stream_unchanged( - old_context->streams[j], - context->streams[i])) { - if (!resource_attach_surfaces_to_context( - old_context->stream_status[j].plane_states, - old_context->stream_status[j].plane_count, - context->streams[i], - context, pool)) - return false; - context->stream_status[i] = old_context->stream_status[j]; - } - if (set[i].plane_count != 0) - if (!resource_attach_surfaces_to_context( - set[i].plane_states, - set[i].plane_count, - context->streams[i], - context, pool)) - return false; - - } - - return true; -} - /* Maximum TMDS single link pixel clock 165MHz */ #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 @@ -1392,23 +1500,22 @@ bool dc_remove_stream_from_ctx( struct validate_context *new_ctx, struct dc_stream_state *stream) { - int i, j; + int i; struct dc_context *dc_ctx = dc->ctx; struct pipe_ctx *del_pipe = NULL; - /*TODO MPO to remove extra pipe or in surface remove ?*/ - - /* Release primary and secondary pipe (if exsist) */ + /* Release primary pipe */ for (i = 0; i < MAX_PIPES; i++) { - if (new_ctx->res_ctx.pipe_ctx[i].stream == stream) { + if (new_ctx->res_ctx.pipe_ctx[i].stream == stream && + !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; - if (del_pipe->stream_res.stream_enc) - update_stream_engine_usage( - &new_ctx->res_ctx, + ASSERT(del_pipe->stream_res.stream_enc); + update_stream_engine_usage( + &new_ctx->res_ctx, dc->res_pool, - del_pipe->stream_res.stream_enc, - false); + del_pipe->stream_res.stream_enc, + false); if (del_pipe->stream_res.audio) update_audio_usage( @@ -1418,6 +1525,8 @@ bool dc_remove_stream_from_ctx( false); memset(del_pipe, 0, sizeof(*del_pipe)); + + break; } } @@ -1438,10 +1547,6 @@ bool dc_remove_stream_from_ctx( dc_stream_release(new_ctx->streams[i]); new_ctx->stream_count--; - /*TODO move into dc_remove_surface_from_ctx ?*/ - for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) - dc_plane_state_release(new_ctx->stream_status[i].plane_states[j]); - /* Trim back arrays */ for (; i < new_ctx->stream_count; i++) { new_ctx->streams[i] = new_ctx->streams[i + 1]; @@ -1636,18 +1741,14 @@ void dc_resource_validate_ctx_copy_construct_current( bool dc_validate_global_state( struct dc *dc, - const struct dc_validation_set set[], - int set_count, struct validate_context *new_ctx) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct dc_context *dc_ctx = dc->ctx; - struct validate_context *old_context = dc->current_context; int i, j; if (dc->res_pool->funcs->validate_global && - dc->res_pool->funcs->validate_global(dc, set, set_count, - old_context, new_ctx) != DC_OK) + dc->res_pool->funcs->validate_global( + dc, new_ctx) != DC_OK) return false; /* TODO without this SWDEV-114774 brakes */ @@ -1687,15 +1788,6 @@ bool dc_validate_global_state( } } - /*TODO This should be ok */ - /* Split pipe resource, do not acquire back end */ - - if (!resource_validate_attach_surfaces( - set, set_count, old_context, new_ctx, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - result = resource_build_scaling_params_for_context(dc, new_ctx); if (result == DC_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9cc1c28caa4e..55fc58102515 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -619,15 +619,40 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *h_position, uint32_t *v_position); -bool dc_remove_stream_from_ctx( +bool dc_add_stream_to_ctx( struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream); + +bool dc_remove_stream_from_ctx( + struct dc *dc, struct validate_context *new_ctx, struct dc_stream_state *stream); -bool dc_add_stream_to_ctx( - struct dc *dc, - struct validate_context *new_ctx, - struct dc_stream_state *stream); + +bool dc_add_plane_to_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct validate_context *context); + +bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct validate_context *context); + +bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct validate_context *context); + +bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, + struct validate_context *context); /* * Structure to store surface/stream associations for validation @@ -644,8 +669,6 @@ bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); bool dc_validate_global_state( struct dc *dc, - const struct dc_validation_set set[], - int set_count, struct validate_context *new_ctx); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index c9dad4e2a7c8..c991610315b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -684,19 +684,18 @@ bool dce100_validate_bandwidth( } static bool dce100_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 1) + if (context->stream_status[i].plane_count > 1) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -706,12 +705,9 @@ static bool dce100_validate_surface_sets( enum dc_status dce100_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce100_validate_surface_sets(set, set_count)) + if (!dce100_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index d682180f2eaf..18c67f89e9b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -880,31 +880,30 @@ static bool dce110_validate_bandwidth( } static bool dce110_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 2) + if (context->stream_status[i].plane_count > 2) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].plane_count == 2) { - if (set[i].plane_states[1]->format + if (context->stream_status[i].plane_count == 2) { + if (context->stream_status[i].plane_states[1]->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].plane_states[1]->src_rect.width > 1920 - || set[i].plane_states[1]->src_rect.height > 1080) + if (context->stream_status[i].plane_states[1]->src_rect.width > 1920 + || context->stream_status[i].plane_states[1]->src_rect.height > 1080) return false; - if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) return false; } } @@ -914,12 +913,9 @@ static bool dce110_validate_surface_sets( enum dc_status dce110_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce110_validate_surface_sets(set, set_count)) + if (!dce110_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 85a396ef5aa5..d5a8ee69171d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -855,19 +855,18 @@ enum dc_status resource_map_phy_clock_resources( } static bool dce112_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 1) + if (context->stream_status[i].plane_count > 1) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -928,12 +927,9 @@ enum dc_status dce112_validate_guaranteed( enum dc_status dce112_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce112_validate_surface_sets(set, set_count)) + if (!dce112_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index ac3f42a44030..945ff7ee6cd9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -716,19 +716,18 @@ bool dce80_validate_bandwidth( } static bool dce80_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 1) + if (context->stream_status[i].plane_count > 1) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -738,12 +737,9 @@ static bool dce80_validate_surface_sets( enum dc_status dce80_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce80_validate_surface_sets(set, set_count)) + if (!dce80_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 62bd11d250c5..bd1a6367872f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -99,9 +99,6 @@ struct resource_funcs { enum dc_status (*validate_global)( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( -- cgit v1.2.3-59-g8ed1b From 41f97c0773aed681ad65fa27ee88b503fbdcd298 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Thu, 24 Aug 2017 17:40:00 -0400 Subject: drm/amd/display: DF C-state entry blocked when DPMS Signed-off-by: Hersen Wu Reviewed-by: Hersen Wu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 9 +++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 48 +++++++++++++++++++++- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 9 ++++ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++ 7 files changed, 74 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index dc1b7d061be2..a20dc24db0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -830,6 +830,8 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); + dc->hwss.ready_shared_resources(dc); + for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); @@ -879,6 +881,8 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c dc_retain_validate_context(dc->current_context); + dc->hwss.optimize_shared_resources(dc); + return (result == DC_OK); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 8ba61b9b8792..3502faa1458f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2697,6 +2697,10 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } } +static void ready_shared_resources(struct dc *dc) {} + +static void optimize_shared_resources(struct dc *dc) {} + static const struct hw_sequencer_funcs dce110_funcs = { .program_gamut_remap = program_gamut_remap, .program_csc_matrix = program_csc_matrix, @@ -2727,7 +2731,10 @@ static const struct hw_sequencer_funcs dce110_funcs = { .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, .setup_stereo = NULL, .set_avmute = dce110_set_avmute, - .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect + .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, + .ready_shared_resources = ready_shared_resources, + .optimize_shared_resources = optimize_shared_resources, + }; bool dce110_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 4a24893486e8..9c54cae28997 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -776,6 +776,50 @@ static void power_on_plane( "Un-gated front end for pipe %d\n", plane_id); } +static void undo_DEGVIDCN10_253_wa(struct dc *dc) +{ + struct dce_hwseq *hws = dc->hwseq; + struct mem_input *mi = dc->res_pool->mis[0]; + + mi->funcs->set_blank(mi, true); + + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + + hubp_pg_control(hws, 0, false); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); +} + +static void ready_shared_resources(struct dc *dc) +{ + if (dc->current_context->stream_count == 0 && + !dc->debug.disable_stutter) + undo_DEGVIDCN10_253_wa(dc); +} + +static void apply_DEGVIDCN10_253_wa(struct dc *dc) +{ + struct dce_hwseq *hws = dc->hwseq; + struct mem_input *mi = dc->res_pool->mis[0]; + + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + + hubp_pg_control(hws, 0, true); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + + mi->funcs->set_hubp_blank_en(mi, false); +} + +static void optimize_shared_resources(struct dc *dc) +{ + if (dc->current_context->stream_count == 0 && + !dc->debug.disable_stutter) + apply_DEGVIDCN10_253_wa(dc); +} + static void bios_golden_init(struct dc *dc) { struct dc_bios *bp = dc->ctx->dc_bios; @@ -2829,7 +2873,9 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .setup_stereo = dcn10_setup_stereo, .set_avmute = dce110_set_avmute, .log_hw_state = dcn10_log_hw_state, - .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .ready_shared_resources = ready_shared_resources, + .optimize_shared_resources = optimize_shared_resources, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 0a47e6ad4286..9008cd03b139 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -56,6 +56,14 @@ static void min10_set_blank(struct mem_input *mem_input, bool blank) } } +static void min10_set_hubp_blank_en(struct mem_input *mem_input, bool blank) +{ + struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + uint32_t blank_en = blank ? 1 : 0; + + REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); +} + static void min10_vready_workaround(struct mem_input *mem_input, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) { @@ -771,6 +779,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { .set_blank = min10_set_blank, .dcc_control = min10_dcc_control, .mem_program_viewport = min_set_viewport, + .set_hubp_blank_en = min10_set_hubp_blank_en, }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 4af40f5138fc..d09ed13fb8ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -439,6 +439,7 @@ static const struct dc_debug debug_defaults_diags = { .force_abm_enable = false, .timing_trace = true, .clock_trace = true, + .disable_stutter = true, #if defined(CONFIG_DRM_AMD_DC_DCN1_0) .disable_pplib_clock_request = true, .disable_pplib_wm_range = true, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 6f4f04da9e28..6cef9ad0af91 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -161,6 +161,8 @@ struct mem_input_funcs { struct dchub_init_data *dh_data); void (*set_blank)(struct mem_input *mi, bool blank); + void (*set_hubp_blank_en)(struct mem_input *mi, bool blank); + }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index c73dca9f6d46..01e426194163 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -173,6 +173,9 @@ struct hw_sequencer_funcs { void (*wait_for_mpcc_disconnect)(struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); + + void (*ready_shared_resources)(struct dc *dc); + void (*optimize_shared_resources)(struct dc *dc); }; void color_space_to_black_color( -- cgit v1.2.3-59-g8ed1b From 608ac7bb3924178d7bfa8b88d79d3d9d72b8f485 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Fri, 25 Aug 2017 16:16:10 -0400 Subject: drm/amd/display: Rename dc validate_context and current_context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename all the dc validate_context to dc_state and dc current_context to current_state. Signed-off-by: Jerry Zuo Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 108 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 40 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 38 ++++---- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 8 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 10 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 70 ++++++------- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +-- .../drm/amd/display/dc/dce110/dce110_resource.c | 16 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +-- .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 10 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 62 ++++++------ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 14 +-- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 14 +-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 22 ++--- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 4 +- 32 files changed, 263 insertions(+), 264 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c44b82036fa..9b018115d97e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -711,7 +711,7 @@ dm_atomic_state_clear(struct drm_atomic_state *state) struct dm_atomic_state *dm_state = to_dm_atomic_state(state); if (dm_state->context) { - dc_release_validate_context(dm_state->context); + dc_release_state(dm_state->context); dm_state->context = NULL; } @@ -4098,7 +4098,7 @@ void amdgpu_dm_atomic_commit_tail( } if (dm_state->context) - WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); + WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index e0a5632f00a3..71cbee199016 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -209,7 +209,7 @@ struct dm_crtc_state { struct dm_atomic_state { struct drm_atomic_state base; - struct validate_context *context; + struct dc_state *context; }; #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6c85a54e47d6..ee1b76c074e6 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -476,7 +476,7 @@ static void dcn_bw_calc_rq_dlg_ttu( static void dcn_dml_wm_override( const struct dcn_bw_internal_vars *v, struct display_mode_lib *dml, - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool) { int i, in_idx, active_count; @@ -593,7 +593,7 @@ static void split_stream_across_pipes( } static void calc_wm_sets_and_perf_params( - struct validate_context *context, + struct dc_state *context, struct dcn_bw_internal_vars *v) { /* Calculate set A last to keep internal var state consistent for required config */ @@ -721,7 +721,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) bool dcn_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { const struct resource_pool *pool = dc->res_pool; struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a20dc24db0d5..53f814dcc24d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -160,7 +160,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, bool ret = false; for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { dc->hwss.set_drr(&pipe, 1, vmin, vmax); @@ -187,7 +187,7 @@ static bool stream_get_crtc_position(struct dc *dc, for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { dc->hwss.get_position(&pipe, 1, &position); @@ -207,8 +207,8 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { + pipes = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.program_gamut_remap(pipes); ret = true; } @@ -224,10 +224,10 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_context->res_ctx.pipe_ctx[i].stream + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + pipes = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.program_csc_matrix(pipes, stream->output_color_space, stream->csc_color_matrix.matrix); @@ -252,10 +252,10 @@ static void set_static_screen_events(struct dc *dc, struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { - if (dc->current_context->res_ctx.pipe_ctx[j].stream + if (dc->current_state->res_ctx.pipe_ctx[j].stream == stream) { pipes_affected[num_pipes_affected++] = - &dc->current_context->res_ctx.pipe_ctx[j]; + &dc->current_state->res_ctx.pipe_ctx[j]; } } } @@ -334,7 +334,7 @@ void set_dither_option(struct dc_stream_state *stream, { struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; - struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; memset(¶ms, 0, sizeof(params)); if (!stream) @@ -408,8 +408,8 @@ static void allocate_dc_stream_funcs(struct dc *dc) static void destruct(struct dc *dc) { - dc_release_validate_context(dc->current_context); - dc->current_context = NULL; + dc_release_state(dc->current_state); + dc->current_state = NULL; destroy_links(dc); @@ -494,9 +494,9 @@ static bool construct(struct dc *dc, goto fail; } - dc->current_context = dc_create_state(); + dc->current_state = dc_create_state(); - if (!dc->current_context) { + if (!dc->current_state) { dm_error("%s: failed to create validate ctx\n", __func__); goto fail; } @@ -668,12 +668,12 @@ bool dc_validate_guaranteed( struct dc_stream_state *stream) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; + struct dc_state *context; if (!dc_validate_stream(dc, stream)) return false; - context = dm_alloc(sizeof(struct validate_context)); + context = dm_alloc(sizeof(struct dc_state)); if (context == NULL) goto context_alloc_fail; @@ -682,7 +682,7 @@ bool dc_validate_guaranteed( result = dc->res_pool->funcs->validate_guaranteed( dc, stream, context); - dc_release_validate_context(context); + dc_release_state(context); context_alloc_fail: if (result != DC_OK) { @@ -697,7 +697,7 @@ context_alloc_fail: static void program_timing_sync( struct dc *dc, - struct validate_context *ctx) + struct dc_state *ctx) { int i, j; int group_index = 0; @@ -771,15 +771,15 @@ static void program_timing_sync( static bool context_changed( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { uint8_t i; - if (context->stream_count != dc->current_context->stream_count) + if (context->stream_count != dc->current_state->stream_count) return true; - for (i = 0; i < dc->current_context->stream_count; i++) { - if (dc->current_context->streams[i] != context->streams[i]) + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->streams[i] != context->streams[i]) return true; } @@ -788,7 +788,7 @@ static bool context_changed( bool dc_enable_stereo( struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count) { @@ -800,7 +800,7 @@ bool dc_enable_stereo( if (context != NULL) pipe = &context->res_ctx.pipe_ctx[i]; else - pipe = &dc->current_context->res_ctx.pipe_ctx[i]; + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { if (streams[j] && streams[j] == pipe->stream && dc->hwss.setup_stereo) @@ -816,7 +816,7 @@ bool dc_enable_stereo( * Applies given context to HW and copy it into current context. * It's up to the user to release the src context afterwards. */ -static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) +static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -875,18 +875,18 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - dc_release_validate_context(dc->current_context); + dc_release_state(dc->current_state); - dc->current_context = context; + dc->current_state = context; - dc_retain_validate_context(dc->current_context); + dc_retain_state(dc->current_state); dc->hwss.optimize_shared_resources(dc); return (result == DC_OK); } -bool dc_commit_context(struct dc *dc, struct validate_context *context) +bool dc_commit_state(struct dc *dc, struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; int i; @@ -905,7 +905,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) LOG_DC); } - result = dc_commit_context_no_check(dc, context); + result = dc_commit_state_no_check(dc, context); return (result == DC_OK); } @@ -914,7 +914,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct validate_context *context = dc->current_context; + struct dc_state *context = dc->current_state; post_surface_trace(dc); @@ -999,9 +999,9 @@ bool dc_commit_planes_to_stream( return true; } -struct validate_context *dc_create_state(void) +struct dc_state *dc_create_state(void) { - struct validate_context *context = dm_alloc(sizeof(struct validate_context)); + struct dc_state *context = dm_alloc(sizeof(struct dc_state)); if (!context) return NULL; @@ -1010,13 +1010,13 @@ struct validate_context *dc_create_state(void) return context; } -void dc_retain_validate_context(struct validate_context *context) +void dc_retain_state(struct dc_state *context) { ASSERT(atomic_read(&context->ref_count) > 0); atomic_inc(&context->ref_count); } -void dc_release_validate_context(struct validate_context *context) +void dc_release_state(struct dc_state *context) { ASSERT(atomic_read(&context->ref_count) > 0); atomic_dec(&context->ref_count); @@ -1028,7 +1028,7 @@ void dc_release_validate_context(struct validate_context *context) } static bool is_surface_in_context( - const struct validate_context *context, + const struct dc_state *context, const struct dc_plane_state *plane_state) { int j; @@ -1145,7 +1145,7 @@ static enum surface_update_type det_surface_update( const struct dc_surface_update *u, int surface_index) { - const struct validate_context *context = dc->current_context; + const struct dc_state *context = dc->current_state; enum surface_update_type type = UPDATE_TYPE_FAST; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1200,7 +1200,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( } static struct dc_stream_status *stream_get_status( - struct validate_context *ctx, + struct dc_state *ctx, struct dc_stream_state *stream) { uint8_t i; @@ -1221,7 +1221,7 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct validate_context *context; + struct dc_state *context; int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; @@ -1239,7 +1239,7 @@ void dc_update_planes_and_stream(struct dc *dc, ASSERT(0); } #endif - context = dc->current_context; + context = dc->current_state; /* update current stream with the new updates */ if (stream_update) { @@ -1293,7 +1293,7 @@ void dc_update_planes_and_stream(struct dc *dc, goto context_alloc_fail; dc_resource_validate_ctx_copy_construct( - dc->current_context, context); + dc->current_state, context); /*remove old surfaces from context */ if (!dc_rem_all_planes_for_stream(dc, stream, context)) { @@ -1437,7 +1437,7 @@ void dc_update_planes_and_stream(struct dc *dc, /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[j]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; @@ -1524,7 +1524,7 @@ void dc_update_planes_and_stream(struct dc *dc, } } - if (dc->current_context != context) { + if (dc->current_state != context) { /* Since memory free requires elevated IRQL, an interrupt * request is generated by mem free. If this happens @@ -1534,16 +1534,16 @@ void dc_update_planes_and_stream(struct dc *dc, * then free the old context. */ - struct validate_context *old = dc->current_context; + struct dc_state *old = dc->current_state; - dc->current_context = context; - dc_release_validate_context(old); + dc->current_state = context; + dc_release_state(old); } return; fail: - dc_release_validate_context(context); + dc_release_state(context); context_alloc_fail: DC_ERROR("Failed to allocate new validate context!\n"); @@ -1551,13 +1551,13 @@ context_alloc_fail: uint8_t dc_get_current_stream_count(struct dc *dc) { - return dc->current_context->stream_count; + return dc->current_state->stream_count; } struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - if (i < dc->current_context->stream_count) - return dc->current_context->streams[i]; + if (i < dc->current_state->stream_count) + return dc->current_state->streams[i]; return NULL; } @@ -1634,11 +1634,11 @@ void dc_set_power_state( */ /* Preserve refcount */ - ref_count = dc->current_context->ref_count; - dc_resource_validate_ctx_destruct(dc->current_context); - memset(dc->current_context, 0, - sizeof(*dc->current_context)); - dc->current_context->ref_count = ref_count; + ref_count = dc->current_state->ref_count; + dc_resource_validate_ctx_destruct(dc->current_state); + memset(dc->current_state, 0, + sizeof(*dc->current_state)); + dc->current_state->ref_count = ref_count; break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index d74eed8f9b96..6acee5426e4b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -329,7 +329,7 @@ void context_timing_trace( void context_clock_trace( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) struct dc *core_dc = dc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 0bdd41ca8799..65e12614d96c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1819,14 +1819,14 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx. + if (core_dc->current_state->res_ctx. pipe_ctx[i].stream == stream) /* DMCU -1 for all controller id values, * therefore +1 here */ controller_id = - core_dc->current_context-> + core_dc->current_state-> res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; } @@ -1926,13 +1926,13 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->engineId = link->link_enc->preferred_engine; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream + if (core_dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { /* dmcu -1 for all controller id values, * therefore +1 here */ psr_context->controllerId = - core_dc->current_context->res_ctx. + core_dc->current_state->res_ctx. pipe_ctx[i].stream_res.tg->inst + 1; break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 446e2933474c..5f2b52e41427 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2406,7 +2406,7 @@ bool dc_link_dp_set_test_pattern( const unsigned char *p_custom_pattern, unsigned int cust_pattern_size) { - struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; struct pipe_ctx *pipe_ctx = &pipes[0]; unsigned int lane; unsigned int i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 23d8b614e0fd..3427fb5b7e30 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -62,7 +62,7 @@ void dp_enable_link_phy( struct link_encoder *link_enc = link->link_enc; struct pipe_ctx *pipes = - link->dc->current_context->res_ctx.pipe_ctx; + link->dc->current_state->res_ctx.pipe_ctx; struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; unsigned int i; @@ -262,7 +262,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, bool skip_video_pattern) { struct pipe_ctx *pipes = - &link->dc->current_context->res_ctx.pipe_ctx[0]; + &link->dc->current_state->res_ctx.pipe_ctx[0]; unsigned int i; for (i = 0; i < MAX_PIPES; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9eb8d48bc889..727afeaa3830 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -893,7 +893,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) enum dc_status resource_build_scaling_params_for_context( const struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; @@ -971,7 +971,7 @@ static struct pipe_ctx *resource_get_tail_pipe_for_stream( * that has no surface attached yet */ static struct pipe_ctx *acquire_free_pipe_for_stream( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { @@ -1048,7 +1048,7 @@ bool dc_add_plane_to_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context) + struct dc_state *context) { int i; struct resource_pool *pool = dc->res_pool; @@ -1124,7 +1124,7 @@ bool dc_remove_plane_from_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context) + struct dc_state *context) { int i; struct dc_stream_status *stream_status = NULL; @@ -1199,7 +1199,7 @@ bool dc_remove_plane_from_context( bool dc_rem_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context) + struct dc_state *context) { int i, old_plane_count; struct dc_stream_status *stream_status = NULL; @@ -1233,7 +1233,7 @@ static bool add_all_planes_for_stream( struct dc_stream_state *stream, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct dc_state *context) { int i, j; @@ -1258,7 +1258,7 @@ bool dc_add_all_planes_for_stream( struct dc_stream_state *stream, struct dc_plane_state * const *plane_states, int plane_count, - struct validate_context *context) + struct dc_state *context) { struct dc_validation_set set; int i; @@ -1434,7 +1434,7 @@ static struct audio *find_first_free_audio( } bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream_state *stream) + struct dc_state *old_context, struct dc_stream_state *stream) { int i; @@ -1450,7 +1450,7 @@ bool resource_is_stream_unchanged( bool dc_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream) { struct dc_context *dc_ctx = dc->ctx; @@ -1474,7 +1474,7 @@ bool dc_add_stream_to_ctx( bool dc_remove_stream_from_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream) { int i; @@ -1553,7 +1553,7 @@ static void copy_pipe_ctx( static struct dc_stream_state *find_pll_sharable_stream( struct dc_stream_state *stream_needs_pll, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1615,7 +1615,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) enum dc_status resource_map_pool_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { const struct resource_pool *pool = dc->res_pool; @@ -1689,7 +1689,7 @@ enum dc_status resource_map_pool_resources( /* first stream in the context is used to populate the rest */ void validate_guaranteed_copy_streams( - struct validate_context *context, + struct dc_state *context, int max_streams) { int i; @@ -1709,14 +1709,14 @@ void validate_guaranteed_copy_streams( void dc_resource_validate_ctx_copy_construct_current( const struct dc *dc, - struct validate_context *dst_ctx) + struct dc_state *dst_ctx) { - dc_resource_validate_ctx_copy_construct(dc->current_context, dst_ctx); + dc_resource_validate_ctx_copy_construct(dc->current_state, dst_ctx); } bool dc_validate_global_state( struct dc *dc, - struct validate_context *new_ctx) + struct dc_state *new_ctx) { enum dc_status result = DC_ERROR_UNEXPECTED; int i, j; @@ -2413,7 +2413,7 @@ static void set_vsc_info_packet( /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ } -void dc_resource_validate_ctx_destruct(struct validate_context *context) +void dc_resource_validate_ctx_destruct(struct dc_state *context) { int i, j; @@ -2433,8 +2433,8 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) * by the src_ctx */ void dc_resource_validate_ctx_copy_construct( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx) + const struct dc_state *src_ctx, + struct dc_state *dst_ctx) { int i, j; atomic_t ref_count = dst_ctx->ref_count; @@ -2518,7 +2518,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) enum dc_status resource_map_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { /* acquire new resources */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 0e7cc293184e..a421779093d9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -169,10 +169,9 @@ struct dc_stream_status *dc_stream_get_status( uint8_t i; struct dc *dc = stream->ctx->dc; - for (i = 0; i < dc->current_context->stream_count; i++) { - if (stream == dc->current_context->streams[i]) { - return &dc->current_context->stream_status[i]; - } + for (i = 0; i < dc->current_state->stream_count; i++) { + if (stream == dc->current_state->streams[i]) + return &dc->current_state->stream_status[i]; } return NULL; @@ -199,7 +198,7 @@ bool dc_stream_set_cursor_attributes( } core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; + res_ctx = &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -235,7 +234,7 @@ bool dc_stream_set_cursor_position( } core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; + res_ctx = &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -271,7 +270,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) uint8_t i; struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; + &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; @@ -295,7 +294,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, bool ret = false; struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; + &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 0b6410fb2f3e..e96f63eed070 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -104,12 +104,12 @@ const struct dc_plane_status *dc_plane_get_status( plane_status = &plane_state->status; core_dc = plane_state->ctx->dc; - if (core_dc->current_context == NULL) + if (core_dc->current_state == NULL) return NULL; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = - &core_dc->current_context->res_ctx.pipe_ctx[i]; + &core_dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->plane_state != plane_state) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 55fc58102515..d1d5737398df 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -99,7 +99,7 @@ struct dc_static_screen_events { /* Forward declaration*/ struct dc; struct dc_plane_state; -struct validate_context; +struct dc_state; struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, @@ -192,7 +192,7 @@ struct dc_debug { bool disable_psr; bool force_abm_enable; }; -struct validate_context; +struct dc_state; struct resource_pool; struct dce_hwseq; struct dc { @@ -208,7 +208,7 @@ struct dc { uint8_t link_count; struct dc_link *links[MAX_PIPES * 2]; - struct validate_context *current_context; + struct dc_state *current_state; struct resource_pool *res_pool; /* Display Engine Clock levels */ @@ -621,12 +621,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, bool dc_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream); bool dc_remove_stream_from_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream); @@ -634,25 +634,25 @@ bool dc_add_plane_to_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context); + struct dc_state *context); bool dc_remove_plane_from_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context); + struct dc_state *context); bool dc_rem_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context); + struct dc_state *context); bool dc_add_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state * const *plane_states, int plane_count, - struct validate_context *context); + struct dc_state *context); /* * Structure to store surface/stream associations for validation @@ -669,7 +669,7 @@ bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); bool dc_validate_global_state( struct dc *dc, - struct validate_context *new_ctx); + struct dc_state *new_ctx); /* * This function takes a stream and checks if it is guaranteed to be supported. @@ -680,14 +680,14 @@ bool dc_validate_global_state( */ void dc_resource_validate_ctx_copy_construct( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx); + const struct dc_state *src_ctx, + struct dc_state *dst_ctx); void dc_resource_validate_ctx_copy_construct_current( const struct dc *dc, - struct validate_context *dst_ctx); + struct dc_state *dst_ctx); -void dc_resource_validate_ctx_destruct(struct validate_context *context); +void dc_resource_validate_ctx_destruct(struct dc_state *context); /* * TODO update to make it about validation sets @@ -698,7 +698,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context); * Phy, Encoder, Timing Generator are programmed and enabled. * New streams are enabled with blank stream; no memory read. */ -bool dc_commit_context(struct dc *dc, struct validate_context *context); +bool dc_commit_state(struct dc *dc, struct dc_state *context); /* * Set up streams and links associated to drive sinks @@ -714,7 +714,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_enable_stereo( struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count); @@ -737,9 +737,9 @@ enum surface_update_type dc_check_update_surfaces_for_stream( const struct dc_stream_status *stream_status); -struct validate_context *dc_create_state(void); -void dc_retain_validate_context(struct validate_context *context); -void dc_release_validate_context(struct validate_context *context); +struct dc_state *dc_create_state(void); +void dc_retain_state(struct dc_state *context); +void dc_release_state(struct dc_state *context); /******************************************************************************* * Link Interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 0654fe34627c..d3b61b92ebec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -609,7 +609,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; + struct dc_state *context = dc_core->current_state; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; /* This function need separate to different DCE version, before separate, just use pixel clock */ @@ -624,7 +624,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; + struct dc_state *context = dc_core->current_state; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; /* This function need separate to different DCE version, before separate, just use pixel clock */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index b7e51c5ed1b1..492ea6069eb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -107,7 +107,7 @@ static bool dce100_enable_display_power_gating( static void dce100_pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -127,14 +127,14 @@ static void dce100_pplib_apply_display_requirements( void dce100_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); - dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } dce100_pplib_apply_display_requirements(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index c04aa15cd656..770b5bb1ff40 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -29,13 +29,13 @@ #include "core_types.h" struct dc; -struct validate_context; +struct dc_state; bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed); #endif /* __DC_HWSS_DCE100_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index c991610315b2..36d79175354c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -653,7 +653,7 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -674,7 +674,7 @@ static enum dc_status build_mapped_resource( bool dce100_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; @@ -684,7 +684,7 @@ bool dce100_validate_bandwidth( } static bool dce100_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -705,7 +705,7 @@ static bool dce100_validate_surface_sets( enum dc_status dce100_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce100_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -716,7 +716,7 @@ enum dc_status dce100_validate_global( enum dc_status dce100_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3502faa1458f..1c6e2006f2a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -976,11 +976,11 @@ static void program_scaler(const struct dc *dc, static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -1032,11 +1032,11 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( static enum dc_status apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; /* */ @@ -1257,7 +1257,7 @@ static uint32_t compute_pstate_blackout_duration( void dce110_set_displaymarks( const struct dc *dc, - struct validate_context *context) + struct dc_state *context) { uint8_t i, num_pipes; unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; @@ -1415,7 +1415,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, */ static uint32_t get_max_pixel_clock_for_all_paths( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool pre_mode_set) { uint32_t max_pix_clk = 0; @@ -1456,7 +1456,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( */ static void apply_min_clocks( struct dc *dc, - struct validate_context *context, + struct dc_state *context, enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) { @@ -1545,7 +1545,7 @@ static void apply_min_clocks( * Check if FBC can be enabled */ static enum dc_status validate_fbc(struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; @@ -1575,7 +1575,7 @@ static enum dc_status validate_fbc(struct dc *dc, * Enable FBC */ static enum dc_status enable_fbc(struct dc *dc, - struct validate_context *context) + struct dc_state *context) { enum dc_status status = validate_fbc(dc, context); @@ -1604,14 +1604,14 @@ static enum dc_status enable_fbc(struct dc *dc, static enum dc_status apply_ctx_to_hw_fpga( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { enum dc_status status = DC_ERROR_UNEXPECTED; int i; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -1634,7 +1634,7 @@ static enum dc_status apply_ctx_to_hw_fpga( static void dce110_reset_hw_ctx_wrap( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1642,7 +1642,7 @@ static void dce110_reset_hw_ctx_wrap( /* look up the targets that have been removed since last commit */ for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; /* Note: We need to disable output if clock sources change, @@ -1664,9 +1664,9 @@ static void dce110_reset_hw_ctx_wrap( } pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); pipe_ctx_old->plane_res.mi->funcs->free_mem_input( - pipe_ctx_old->plane_res.mi, dc->current_context->stream_count); + pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); resource_unreference_clock_source( - &dc->current_context->res_ctx, dc->res_pool, + &dc->current_state->res_ctx, dc->res_pool, &pipe_ctx_old->clock_source); dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); @@ -1679,7 +1679,7 @@ static void dce110_reset_hw_ctx_wrap( enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; @@ -1705,7 +1705,7 @@ enum dc_status dce110_apply_ctx_to_hw( /* below is for real asic only */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) @@ -1735,31 +1735,31 @@ enum dc_status dce110_apply_ctx_to_hw( #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (dc->ctx->dce_version >= DCN_VERSION_1_0) { if (context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + > dc->current_state->bw.dcn.cur_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; } if (context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; } if (context->bw.dcn.calc_clk.dispclk_khz - > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.cur_clk.dispclk_khz = + dc->current_state->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; context->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; @@ -1767,7 +1767,7 @@ enum dc_status dce110_apply_ctx_to_hw( } else #endif if (context->bw.dce.dispclk_khz - > dc->current_context->bw.dce.dispclk_khz) { + > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); @@ -1848,7 +1848,7 @@ enum dc_status dce110_apply_ctx_to_hw( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -2327,7 +2327,7 @@ static void init_hw(struct dc *dc) } void dce110_fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg) { int j; @@ -2375,7 +2375,7 @@ void dce110_fill_display_configs( pp_display_cfg->display_count = num_cfgs; } -uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) +uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) { uint8_t j; uint32_t min_vertical_blank_time = -1; @@ -2427,7 +2427,7 @@ static int determine_sclk_from_bounding_box( static void pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2481,16 +2481,16 @@ static void pplib_apply_display_requirements( static void dce110_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { dce110_set_displaymarks(dc, context); - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); - dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } pplib_apply_display_requirements(dc, context); @@ -2508,8 +2508,8 @@ static void dce110_program_front_end_for_pipe( memset(&tbl_entry, 0, sizeof(tbl_entry)); - if (dc->current_context) - old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + if (dc->current_state) + old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; memset(&adjust, 0, sizeof(adjust)); adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -2627,7 +2627,7 @@ static void dce110_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context) + struct dc_state *context) { int i, be_idx; @@ -2657,7 +2657,7 @@ static void dce110_apply_ctx_for_surface( static void dce110_power_down_fe(struct dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ - if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) + if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) return; dc->hwss.enable_display_power_gating( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index ac418fd83894..baa20c1f17ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -30,20 +30,20 @@ #define GAMMA_HW_POINTS_NUM 256 struct dc; -struct validate_context; +struct dc_state; struct dm_pp_display_configuration; bool dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, - struct validate_context *context); + struct dc_state *context); -void dce110_set_display_clock(struct validate_context *context); +void dce110_set_display_clock(struct dc_state *context); void dce110_set_displaymarks( const struct dc *dc, - struct validate_context *context); + struct dc_state *context); void dce110_enable_stream(struct pipe_ctx *pipe_ctx); @@ -62,10 +62,10 @@ void dce110_power_down(struct dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); void dce110_fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); -uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context); +uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 18c67f89e9b5..94b6eb83e01e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -773,7 +773,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -800,7 +800,7 @@ static enum dc_status build_mapped_resource( static bool dce110_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { bool result = false; @@ -826,7 +826,7 @@ static bool dce110_validate_bandwidth( context->streams[0]->timing.v_addressable, context->streams[0]->timing.pix_clk_khz); - if (memcmp(&dc->current_context->bw.dce, + if (memcmp(&dc->current_state->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( @@ -880,7 +880,7 @@ static bool dce110_validate_bandwidth( } static bool dce110_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -913,7 +913,7 @@ static bool dce110_validate_surface_sets( enum dc_status dce110_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce110_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -924,7 +924,7 @@ enum dc_status dce110_validate_global( static enum dc_status dce110_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -954,7 +954,7 @@ static enum dc_status dce110_validate_guaranteed( } static struct pipe_ctx *dce110_acquire_underlay( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { @@ -976,7 +976,7 @@ static struct pipe_ctx *dce110_acquire_underlay( pipe_ctx->stream = stream; - if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) { + if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { struct tg_color black_color = {0}; struct dc_bios *dcb = dc->ctx->dc_bios; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index d5a8ee69171d..de6f71d8a89b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -724,7 +724,7 @@ static struct clock_source *find_matching_pll( static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -745,7 +745,7 @@ static enum dc_status build_mapped_resource( bool dce112_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { bool result = false; @@ -768,7 +768,7 @@ bool dce112_validate_bandwidth( "%s: Bandwidth validation failed!", __func__); - if (memcmp(&dc->current_context->bw.dce, + if (memcmp(&dc->current_state->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( @@ -823,7 +823,7 @@ bool dce112_validate_bandwidth( enum dc_status resource_map_phy_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { @@ -855,7 +855,7 @@ enum dc_status resource_map_phy_clock_resources( } static bool dce112_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -876,7 +876,7 @@ static bool dce112_validate_surface_sets( enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -896,7 +896,7 @@ enum dc_status dce112_add_stream_to_ctx( enum dc_status dce112_validate_guaranteed( struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -927,7 +927,7 @@ enum dc_status dce112_validate_guaranteed( enum dc_status dce112_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce112_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index f1834bfe3d1e..d5c19d34eb0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -39,21 +39,21 @@ enum dc_status dce112_validate_with_context( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context); + struct dc_state *context, + struct dc_state *old_context); enum dc_status dce112_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context); + struct dc_state *context); bool dce112_validate_bandwidth( struct dc *dc, - struct validate_context *context); + struct dc_state *context); enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 945ff7ee6cd9..316080767a21 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -685,7 +685,7 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -706,7 +706,7 @@ static enum dc_status build_mapped_resource( bool dce80_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; @@ -716,7 +716,7 @@ bool dce80_validate_bandwidth( } static bool dce80_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -737,7 +737,7 @@ static bool dce80_validate_surface_sets( enum dc_status dce80_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce80_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -748,7 +748,7 @@ enum dc_status dce80_validate_global( enum dc_status dce80_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9c54cae28997..71ff1cedbdf4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -793,7 +793,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) static void ready_shared_resources(struct dc *dc) { - if (dc->current_context->stream_count == 0 && + if (dc->current_state->stream_count == 0 && !dc->debug.disable_stutter) undo_DEGVIDCN10_253_wa(dc); } @@ -815,7 +815,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) static void optimize_shared_resources(struct dc *dc) { - if (dc->current_context->stream_count == 0 && + if (dc->current_state->stream_count == 0 && !dc->debug.disable_stutter) apply_DEGVIDCN10_253_wa(dc); } @@ -918,7 +918,7 @@ static void dcn10_init_hw(struct dc *dc) static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -1008,7 +1008,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( static void reset_back_end_for_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1040,7 +1040,7 @@ static void reset_back_end_for_pipe( &pipe_ctx->clock_source); for (i = 0; i < dc->res_pool->pipe_count; i++) - if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx) + if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) break; if (i == dc->res_pool->pipe_count) @@ -1206,14 +1206,14 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) static void reset_hw_ctx_wrap( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; /* Reset Front End*/ /* Lock*/ for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) @@ -1222,7 +1222,7 @@ static void reset_hw_ctx_wrap( /* Disconnect*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx->stream || @@ -1234,7 +1234,7 @@ static void reset_hw_ctx_wrap( } /* Unlock*/ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) @@ -1244,7 +1244,7 @@ static void reset_hw_ctx_wrap( /* Disable and Powerdown*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; /*if (!pipe_ctx_old->stream) @@ -1263,7 +1263,7 @@ static void reset_hw_ctx_wrap( /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx_old->stream) @@ -1271,7 +1271,7 @@ static void reset_hw_ctx_wrap( if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context); + reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); } } @@ -1943,7 +1943,7 @@ static void print_rq_dlg_ttu( static void dcn10_power_on_fe( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; @@ -2244,7 +2244,7 @@ static void dcn10_program_pte_vm(struct mem_input *mem_input, static void update_dchubp_dpp( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->plane_res.mi; @@ -2263,7 +2263,7 @@ static void update_dchubp_dpp( pipe_ctx->pipe_idx, pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); - dc->current_context->bw.dcn.cur_clk.dppclk_div = + dc->current_state->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; @@ -2350,7 +2350,7 @@ static void update_dchubp_dpp( static void program_all_pipe_in_tree( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; @@ -2408,7 +2408,7 @@ static void program_all_pipe_in_tree( static void dcn10_pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2437,7 +2437,7 @@ static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context) + struct dc_state *context) { int i, be_idx; @@ -2457,7 +2457,7 @@ static void dcn10_apply_ctx_for_surface( if (num_planes == 0) { for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); @@ -2471,7 +2471,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; @@ -2591,7 +2591,7 @@ static void dcn10_apply_ctx_for_surface( static void dcn10_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { struct pp_smu_display_requirement_rv *smu_req_cur = @@ -2607,25 +2607,25 @@ static void dcn10_set_bandwidth( return; if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz - > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.cur_clk.dispclk_khz = + dc->current_state->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { smu_req.hard_min_dcefclk_khz = context->bw.dcn.calc_clk.dcfclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + > dc->current_state->bw.dcn.cur_clk.fclk_khz) { smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { - dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = + > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { + dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; @@ -2640,15 +2640,15 @@ static void dcn10_set_bandwidth( /* Decrease in freq is increase in period so opposite comparison for dram_ccm */ if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us - < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) { - dc->current_context->bw.dcn.calc_clk.dram_ccm_us = + < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) { + dc->current_state->bw.dcn.calc_clk.dram_ccm_us = context->bw.dcn.calc_clk.dram_ccm_us; context->bw.dcn.cur_clk.dram_ccm_us = context->bw.dcn.calc_clk.dram_ccm_us; } if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us - < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) { - dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us = + < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) { + dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us = context->bw.dcn.calc_clk.min_active_dram_ccm_us; context->bw.dcn.cur_clk.min_active_dram_ccm_us = context->bw.dcn.calc_clk.min_active_dram_ccm_us; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 8bb09de8dcd7..ca53dc1cc19b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -32,7 +32,7 @@ struct dc; void dcn10_hw_sequencer_construct(struct dc *dc); extern void fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index d09ed13fb8ea..fff86ad0c411 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -850,7 +850,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -887,7 +887,7 @@ static enum dc_status build_mapped_resource( enum dc_status dcn10_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -907,7 +907,7 @@ enum dc_status dcn10_add_stream_to_ctx( enum dc_status dcn10_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -935,7 +935,7 @@ enum dc_status dcn10_validate_guaranteed( } static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index bd1a6367872f..71eb9859faf2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -80,7 +80,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); #include "transform.h" struct resource_pool; -struct validate_context; +struct dc_state; struct resource_context; struct resource_funcs { @@ -91,18 +91,18 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context); + struct dc_state *context); bool (*validate_bandwidth)( struct dc *dc, - struct validate_context *context); + struct dc_state *context); enum dc_status (*validate_global)( struct dc *dc, - struct validate_context *context); + struct dc_state *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream); @@ -110,7 +110,7 @@ struct resource_funcs { enum dc_status (*add_stream_to_ctx)( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream); }; @@ -252,7 +252,7 @@ union bw_context { struct dce_bw_output dce; }; -struct validate_context { +struct dc_state { struct dc_stream_state *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 6a205b010084..ae2399f16d1c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -34,7 +34,7 @@ struct pipe_ctx; struct dc; -struct validate_context; +struct dc_state; struct dce_bw_output; enum bw_calcs_version { diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 58744fe87ed8..1e231f6de732 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -35,7 +35,7 @@ #include "../dml/display_mode_lib.h" struct dc; -struct validate_context; +struct dc_state; /******************************************************************************* * DCN data structures. @@ -621,7 +621,7 @@ extern const struct dcn_ip_params dcn10_ip_defaults; bool dcn_validate_bandwidth( struct dc *dc, - struct validate_context *context); + struct dc_state *context); unsigned int dcn_find_dcfclk_suits_all( const struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 01e426194163..aae7629b1c08 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -49,7 +49,7 @@ struct dce_hwseq { }; struct pipe_ctx; -struct validate_context; +struct dc_state; struct dchub_init_data; struct dc_static_screen_events; struct resource_pool; @@ -60,16 +60,16 @@ struct hw_sequencer_funcs { void (*init_hw)(struct dc *dc); enum dc_status (*apply_ctx_to_hw)( - struct dc *dc, struct validate_context *context); + struct dc *dc, struct dc_state *context); void (*reset_hw_ctx_wrap)( - struct dc *dc, struct validate_context *context); + struct dc *dc, struct dc_state *context); void (*apply_ctx_for_surface)( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context); + struct dc_state *context); void (*set_plane_config)( const struct dc *dc, @@ -127,7 +127,7 @@ struct hw_sequencer_funcs { void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, - struct validate_context *context); + struct dc_state *context); void (*update_info_frame)(struct pipe_ctx *pipe_ctx); @@ -145,7 +145,7 @@ struct hw_sequencer_funcs { void (*set_bandwidth)( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed); void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, @@ -159,7 +159,7 @@ struct hw_sequencer_funcs { enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc); void (*setup_stereo)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ebc0f5b02365..41437da5fb9b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -81,14 +81,14 @@ void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( const struct dc *dc, - struct validate_context *context); + struct dc_state *context); void resource_build_info_frame(struct pipe_ctx *pipe_ctx); @@ -122,7 +122,7 @@ bool resource_attach_surfaces_to_context( struct dc_plane_state *const *plane_state, int surface_count, struct dc_stream_state *dc_stream, - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool); struct pipe_ctx *find_idle_secondary_pipe( @@ -130,31 +130,31 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream_state *stream); + struct dc_state *old_context, struct dc_stream_state *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, - const struct validate_context *old_context, - struct validate_context *context, + const struct dc_state *old_context, + struct dc_state *context, const struct resource_pool *pool); void validate_guaranteed_copy_streams( - struct validate_context *context, + struct dc_state *context, int max_streams); void resource_validate_ctx_update_pointer_after_copy( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx); + const struct dc_state *src_ctx, + struct dc_state *dst_ctx); enum dc_status resource_map_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); enum dc_status resource_map_phy_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); bool pipe_need_reprogram( diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index e3a12f3e0642..7cce28489dba 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -214,7 +214,7 @@ bool dce110_vblank_set( uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; struct timing_generator *tg = - core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; + core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; if (enable) { if (!tg->funcs->arm_vert_intr(tg, 2)) { diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 93c8556358f0..6641e8001e97 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -32,7 +32,7 @@ struct dc_context; struct dc_link; struct dc_surface_update; struct resource_context; -struct validate_context; +struct dc_state; /* * @@ -93,7 +93,7 @@ void context_timing_trace( void context_clock_trace( struct dc *dc, - struct validate_context *context); + struct dc_state *context); /* Any function which is empty or have incomplete implementation should be * marked by this macro. -- cgit v1.2.3-59-g8ed1b From ab8db3e1653c50ae19d1c31d82f94beb5115aeef Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 28 Aug 2017 14:25:01 -0400 Subject: drm/amd/display: Move dis_clk into dc_state. dis_clk is single instance across pipes. Signed-off-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 38 +++++++----- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 10 +++- drivers/gpu/drm/amd/display/dc/dc.h | 5 ++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 67 ++++++++++------------ .../drm/amd/display/dc/dce110/dce110_resource.c | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 7 ++- 7 files changed, 78 insertions(+), 57 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 6bf8af7a592d..ab6ad946231e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -573,6 +573,8 @@ static bool construct(struct dc *dc, if (!dc->res_pool) goto fail; + dc_resource_state_construct(dc, dc->current_state); + if (!create_links(dc, init_params->num_virtual_links)) goto fail; @@ -677,6 +679,8 @@ bool dc_validate_guaranteed( if (context == NULL) goto context_alloc_fail; + dc_resource_state_construct(dc, dc->current_state); + atomic_inc(&context->ref_count); result = dc->res_pool->funcs->validate_guaranteed( @@ -1622,6 +1626,8 @@ void dc_set_power_state( switch (power_state) { case DC_ACPI_CM_POWER_STATE_D0: + dc_resource_state_construct(dc, dc->current_state); + dc->hwss.init_hw(dc); break; default: @@ -1638,6 +1644,7 @@ void dc_set_power_state( dc_resource_state_destruct(dc->current_state); memset(dc->current_state, 0, sizeof(*dc->current_state)); + dc->current_state->ref_count = ref_count; break; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 65e12614d96c..b95b58d3648a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1181,7 +1181,9 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) &downspread.raw, sizeof(downspread)); } -static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) +static enum dc_status enable_link_dp( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) { struct dc_stream_state *stream = pipe_ctx->stream; enum dc_status status; @@ -1201,14 +1203,14 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) max_link_rate = LINK_RATE_HIGH3; if (link_settings.link_rate == max_link_rate) { - if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { - if (pipe_ctx->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL) - pipe_ctx->dis_clk->funcs->set_min_clocks_state( - pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); + if (state->dis_clk->funcs->set_min_clocks_state) { + if (state->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL) + state->dis_clk->funcs->set_min_clocks_state( + state->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); } else { uint32_t dp_phyclk_in_khz; const struct clocks_value clocks_value = - pipe_ctx->dis_clk->cur_clocks_value; + state->dis_clk->cur_clocks_value; /* 27mhz = 27000000hz= 27000khz */ dp_phyclk_in_khz = link_settings.link_rate * 27000; @@ -1216,8 +1218,8 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) if (((clocks_value.max_non_dp_phyclk_in_khz != 0) && (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) || (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) { - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + state->dis_clk->funcs->apply_clock_voltage_request( + state->dis_clk, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, dp_phyclk_in_khz, false, @@ -1256,7 +1258,9 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) return status; } -static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) +static enum dc_status enable_link_dp_mst( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) { struct dc_link *link = pipe_ctx->stream->sink->link; @@ -1269,7 +1273,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) /* set the sink to MST mode before enabling the link */ dp_enable_mst_on_sink(link, true); - return enable_link_dp(pipe_ctx); + return enable_link_dp(state, pipe_ctx); } static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, @@ -1709,16 +1713,18 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) } /****************************enable_link***********************************/ -static enum dc_status enable_link(struct pipe_ctx *pipe_ctx) +static enum dc_status enable_link( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) { enum dc_status status = DC_ERROR_UNEXPECTED; switch (pipe_ctx->stream->signal) { case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_EDP: - status = enable_link_dp(pipe_ctx); + status = enable_link_dp(state, pipe_ctx); break; case SIGNAL_TYPE_DISPLAY_PORT_MST: - status = enable_link_dp_mst(pipe_ctx); + status = enable_link_dp_mst(state, pipe_ctx); msleep(200); break; case SIGNAL_TYPE_DVI_SINGLE_LINK: @@ -2285,11 +2291,13 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) return DC_OK; } -void core_link_enable_stream(struct pipe_ctx *pipe_ctx) +void core_link_enable_stream( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) { struct dc *core_dc = pipe_ctx->stream->ctx->dc; - enum dc_status status = enable_link(pipe_ctx); + enum dc_status status = enable_link(state, pipe_ctx); if (status != DC_OK) { dm_logger_write(pipe_ctx->stream->ctx->logger, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index a4e92219a594..c7bb966e8b29 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1033,7 +1033,6 @@ static int acquire_first_split_pipe( pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx->stream_res.opp = pool->opps[i]; - pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; pipe_ctx->stream = stream; @@ -1368,7 +1367,6 @@ static int acquire_first_free_pipe( pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx->stream_res.opp = pool->opps[i]; - pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; @@ -1714,6 +1712,14 @@ void dc_resource_state_copy_construct_current( dc_resource_state_copy_construct(dc->current_state, dst_ctx); } + +void dc_resource_state_construct( + const struct dc *dc, + struct dc_state *dst_ctx) +{ + dst_ctx->dis_clk = dc->res_pool->display_clock; +} + bool dc_validate_global_state( struct dc *dc, struct dc_state *new_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f3ccc2043405..e2159306a9c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -679,6 +679,11 @@ bool dc_validate_global_state( * No hardware is programmed for call. Only validation is done. */ + +void dc_resource_state_construct( + const struct dc *dc, + struct dc_state *dst_ctx); + void dc_resource_state_copy_construct( const struct dc_state *src_ctx, struct dc_state *dst_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1c6e2006f2a1..42caad423430 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -828,6 +828,7 @@ static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) } static void build_audio_output( + struct dc_state *state, const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { @@ -889,8 +890,8 @@ static void build_audio_output( if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { audio_output->pll_info.dp_dto_source_clock_in_khz = - pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( - pipe_ctx->dis_clk); + state->dis_clk->funcs->get_dp_ref_clk_frequency( + state->dis_clk); } audio_output->pll_info.feed_back_divider = @@ -1109,7 +1110,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( resource_build_info_frame(pipe_ctx); dce110_update_info_frame(pipe_ctx); if (!pipe_ctx_old->stream) { - core_link_enable_stream(pipe_ctx); + core_link_enable_stream(context, pipe_ctx); if (dc_is_dp_signal(pipe_ctx->stream->signal)) @@ -1461,42 +1462,34 @@ static void apply_min_clocks( bool pre_mode_set) { struct state_dependent_clocks req_clocks = {0}; - struct pipe_ctx *pipe_ctx; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->dis_clk != NULL) - break; - } if (!pre_mode_set) { /* set clock_state without verification */ - if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { - pipe_ctx->dis_clk->funcs->set_min_clocks_state( - pipe_ctx->dis_clk, *clocks_state); + if (context->dis_clk->funcs->set_min_clocks_state) { + context->dis_clk->funcs->set_min_clocks_state( + context->dis_clk, *clocks_state); return; } /* TODO: This is incorrect. Figure out how to fix. */ - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + context->dis_clk->funcs->apply_clock_voltage_request( + context->dis_clk, DM_PP_CLOCK_TYPE_DISPLAY_CLK, - pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, + context->dis_clk->cur_clocks_value.dispclk_in_khz, pre_mode_set, false); - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + context->dis_clk->funcs->apply_clock_voltage_request( + context->dis_clk, DM_PP_CLOCK_TYPE_PIXELCLK, - pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, + context->dis_clk->cur_clocks_value.max_pixelclk_in_khz, pre_mode_set, false); - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + context->dis_clk->funcs->apply_clock_voltage_request( + context->dis_clk, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, - pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, + context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, pre_mode_set, false); return; @@ -1510,28 +1503,28 @@ static void apply_min_clocks( req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( dc, context, true); - if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { - *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( - pipe_ctx->dis_clk, &req_clocks); - pipe_ctx->dis_clk->funcs->set_min_clocks_state( - pipe_ctx->dis_clk, *clocks_state); + if (context->dis_clk->funcs->get_required_clocks_state) { + *clocks_state = context->dis_clk->funcs->get_required_clocks_state( + context->dis_clk, &req_clocks); + context->dis_clk->funcs->set_min_clocks_state( + context->dis_clk, *clocks_state); } else { - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + context->dis_clk->funcs->apply_clock_voltage_request( + context->dis_clk, DM_PP_CLOCK_TYPE_DISPLAY_CLK, req_clocks.display_clk_khz, pre_mode_set, false); - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + context->dis_clk->funcs->apply_clock_voltage_request( + context->dis_clk, DM_PP_CLOCK_TYPE_PIXELCLK, req_clocks.pixel_clk_khz, pre_mode_set, false); - pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( - pipe_ctx->dis_clk, + context->dis_clk->funcs->apply_clock_voltage_request( + context->dis_clk, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, req_clocks.pixel_clk_khz, pre_mode_set, @@ -1806,7 +1799,7 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output; - build_audio_output(pipe_ctx, &audio_output); + build_audio_output(context, pipe_ctx, &audio_output); pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, @@ -1834,7 +1827,7 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output; - build_audio_output(pipe_ctx, &audio_output); + build_audio_output(context, pipe_ctx, &audio_output); pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, @@ -1868,7 +1861,7 @@ enum dc_status dce110_apply_ctx_to_hw( struct audio_output audio_output; - build_audio_output(pipe_ctx, &audio_output); + build_audio_output(context, pipe_ctx, &audio_output); if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 94b6eb83e01e..4942460d42ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -971,7 +971,6 @@ static struct pipe_ctx *dce110_acquire_underlay( /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; - pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = underlay_idx; pipe_ctx->stream = stream; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 71eb9859faf2..915d5c10361b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -70,7 +70,9 @@ enum dc_status dc_link_validate_mode_timing( void core_link_resume(struct dc_link *link); -void core_link_enable_stream(struct pipe_ctx *pipe_ctx); +void core_link_enable_stream( + struct dc_state *state, + struct pipe_ctx *pipe_ctx); void core_link_disable_stream(struct pipe_ctx *pipe_ctx); @@ -188,7 +190,6 @@ struct pipe_ctx { struct plane_resource plane_res; struct stream_resource stream_res; - struct display_clock *dis_clk; struct clock_source *clock_source; struct pll_settings pll_settings; @@ -268,6 +269,8 @@ struct dc_state { struct dcn_bw_internal_vars dcn_bw_vars; #endif + struct display_clock *dis_clk; + atomic_t ref_count; }; -- cgit v1.2.3-59-g8ed1b From 1f0997f1555571a9c16205a851ffbce92097196d Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 28 Aug 2017 19:33:23 -0400 Subject: drm/amd/display: not override the FMT setting set by VBIOS for eDP Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 42caad423430..3b4ca1a9217f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1082,11 +1082,14 @@ static enum dc_status apply_single_controller_ctx_to_hw( /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ - pipe_ctx->stream_res.opp->funcs->opp_program_fmt( + if (pipe_ctx->stream->signal != SIGNAL_TYPE_EDP && + pipe_ctx->stream->signal != SIGNAL_TYPE_LVDS) { + /*for embedded panel, don't override VBIOS's setting*/ + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx->stream_res.opp, &stream->bit_depth_params, &stream->clamping); - + } if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( pipe_ctx->stream_res.stream_enc, -- cgit v1.2.3-59-g8ed1b From 1e4cee77bbd50d6c868439bfaf8ad61b6c6fcfc3 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 28 Aug 2017 19:35:25 -0400 Subject: drm/amd/display: add backlight control in blankstream. Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3b4ca1a9217f..9fb0ba7e7b7d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -778,9 +778,11 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) /* blank at encoder level */ - if (dc_is_dp_signal(pipe_ctx->stream->signal)) + if (dc_is_dp_signal(pipe_ctx->stream->signal)) { + if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP) + link->link_enc->funcs->backlight_control(link->link_enc, false); pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); - + } link->link_enc->funcs->connect_dig_be_to_fe( link->link_enc, pipe_ctx->stream_res.stream_enc->id, @@ -792,12 +794,15 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings) { struct encoder_unblank_param params = { { 0 } }; + struct dc_link *link = pipe_ctx->stream->sink->link; /* only 3 items below are used by unblank */ params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); + if (link->connector_signal == SIGNAL_TYPE_EDP) + link->link_enc->funcs->backlight_control(link->link_enc, true); } -- cgit v1.2.3-59-g8ed1b From 07fde11f27fb4de3b63ef117593291b094a23e15 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Fri, 25 Aug 2017 16:44:20 -0400 Subject: drm/amd/display: program fbc for scatter/gather Fixing screen flickering when FBC enabled on Stoney Signed-off-by: Roman Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 2e97e5757fb9..f82c26995609 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -189,7 +189,7 @@ void dce110_compressor_enable_fbc( (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) { uint32_t addr; - uint32_t value; + uint32_t value, misc_value; addr = mmFBC_CNTL; @@ -206,9 +206,23 @@ void dce110_compressor_enable_fbc( compressor->attached_inst = params->inst; cp110->offsets = reg_offsets[params->inst]; - /*Toggle it as there is bug in HW */ + /* Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); dm_write_reg(compressor->ctx, addr, value); + + /* FBC usage with scatter & gather for dce110 */ + misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC); + + set_reg_field_value(misc_value, 1, + FBC_MISC, FBC_INVALIDATE_ON_ERROR); + set_reg_field_value(misc_value, 1, + FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR); + set_reg_field_value(misc_value, 0x14, + FBC_MISC, FBC_SLOW_REQ_INTERVAL); + + dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value); + + /* Enable FBC */ set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); dm_write_reg(compressor->ctx, addr, value); -- cgit v1.2.3-59-g8ed1b From 1d9521a74029c3afcf996e207ecd61a74414dd68 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 25 Aug 2017 16:33:40 -0400 Subject: drm/amd/display: Set add_stream_ctx for CZ, Hawaii and others Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce100/dce100_resource.c | 19 +++++++++++++++++++ .../gpu/drm/amd/display/dc/dce100/dce100_resource.h | 5 +++++ .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 20 ++++++++++++++++++++ .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 1 + 4 files changed, 45 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 36d79175354c..ca6c7c2a1b4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -713,6 +713,24 @@ enum dc_status dce100_validate_global( return DC_OK; } +enum dc_status dce100_add_stream_to_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) +{ + enum dc_status result = DC_ERROR_UNEXPECTED; + + result = resource_map_pool_resources(dc, new_ctx, dc_stream); + + if (result == DC_OK) + result = resource_map_clock_resources(dc, new_ctx, dc_stream); + + if (result == DC_OK) + result = build_mapped_resource(dc, new_ctx, dc_stream); + + return result; +} + enum dc_status dce100_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, @@ -769,6 +787,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { .validate_guaranteed = dce100_validate_guaranteed, .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, + .add_stream_to_ctx = dce100_add_stream_to_ctx, .validate_global = dce100_validate_global }; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index ca7b2b7c1a48..f52cae24ee23 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -18,4 +18,9 @@ struct resource_pool *dce100_create_resource_pool( enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); +enum dc_status dce100_add_stream_to_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream); + #endif /* DCE100_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 4942460d42ca..41bfddf9574e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -921,6 +921,25 @@ enum dc_status dce110_validate_global( return DC_OK; } +static enum dc_status dce110_add_stream_to_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) +{ + enum dc_status result = DC_ERROR_UNEXPECTED; + + result = resource_map_pool_resources(dc, new_ctx, dc_stream); + + if (result == DC_OK) + result = resource_map_clock_resources(dc, new_ctx, dc_stream); + + + if (result == DC_OK) + result = build_mapped_resource(dc, new_ctx, dc_stream); + + return result; +} + static enum dc_status dce110_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, @@ -1030,6 +1049,7 @@ static const struct resource_funcs dce110_res_pool_funcs = { .validate_guaranteed = dce110_validate_guaranteed, .validate_bandwidth = dce110_validate_bandwidth, .acquire_idle_pipe_for_layer = dce110_acquire_underlay, + .add_stream_to_ctx = dce110_add_stream_to_ctx, .validate_global = dce110_validate_global }; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 316080767a21..9234086aac27 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -791,6 +791,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_guaranteed = dce80_validate_guaranteed, .validate_bandwidth = dce80_validate_bandwidth, .validate_plane = dce100_validate_plane, + .add_stream_to_ctx = dce100_add_stream_to_ctx, .validate_global = dce80_validate_global }; -- cgit v1.2.3-59-g8ed1b From 4451a2551dcac9ea8c90829e0fcc798b834deb6b Mon Sep 17 00:00:00 2001 From: Shirish S Date: Mon, 21 Aug 2017 14:02:17 +0530 Subject: drm/amd/display: dce110: fix plane validation For MPO to work with per surface rendering and flipping, the previous logic of restricting plane[1] only as underlay needs to be removed. validate_surface_sets() now checks only the width and height bounds in case of underlay rather than checking format. Without this patch one cannot set underlay only. Signed-off-by: Shirish S Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 41bfddf9574e..25eda52c32ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -891,21 +891,14 @@ static bool dce110_validate_surface_sets( if (context->stream_status[i].plane_count > 2) return false; - if (context->stream_status[i].plane_states[0]->format - >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if ((context->stream_status[i].plane_states[i]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) && + (context->stream_status[i].plane_states[i]->src_rect.width > 1920 || + context->stream_status[i].plane_states[i]->src_rect.height > 1080)) return false; - if (context->stream_status[i].plane_count == 2) { - if (context->stream_status[i].plane_states[1]->format - < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) - return false; - if (context->stream_status[i].plane_states[1]->src_rect.width > 1920 - || context->stream_status[i].plane_states[1]->src_rect.height > 1080) - return false; - - if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) - return false; - } + /* irrespective of plane format, stream should be RGB encoded */ + if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) + return false; } return true; -- cgit v1.2.3-59-g8ed1b From 1b7441b00a986cbed017a13ccf316efb54ab7a4b Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 1 Sep 2017 12:51:47 -0400 Subject: drm/amd/display: fix crc_source_select use hardcoded color depth Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 9fb0ba7e7b7d..47e8b582445e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -667,7 +667,25 @@ static enum dc_status bios_parser_crtc_source_select( crtc_source_select.signal = pipe_ctx->stream->signal; crtc_source_select.enable_dp_audio = false; crtc_source_select.sink_signal = pipe_ctx->stream->signal; - crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; + + switch (pipe_ctx->stream->timing.display_color_depth) { + case COLOR_DEPTH_666: + crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR; + break; + case COLOR_DEPTH_888: + crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; + break; + case COLOR_DEPTH_101010: + crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR; + break; + case COLOR_DEPTH_121212: + crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR; + break; + default: + BREAK_TO_DEBUGGER(); + crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; + break; + } dcb = sink->ctx->dc_bios; -- cgit v1.2.3-59-g8ed1b From 603767f903bf5bf301728b197dcde63cf880fe2e Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Fri, 1 Sep 2017 16:14:01 -0400 Subject: drm/amd/display: fix default dithering bug: default is mapped to no dithering. default to spatial dithering based on color depth Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 20 +++----------------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 16 ++++++++++++++++ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 14 +++++--------- 3 files changed, 24 insertions(+), 26 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ab6ad946231e..d5320f7162b4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -341,23 +341,9 @@ void set_dither_option(struct dc_stream_state *stream, return; if (option > DITHER_OPTION_MAX) return; - if (option == DITHER_OPTION_DEFAULT) { - switch (stream->timing.display_color_depth) { - case COLOR_DEPTH_666: - stream->dither_option = DITHER_OPTION_SPATIAL6; - break; - case COLOR_DEPTH_888: - stream->dither_option = DITHER_OPTION_SPATIAL8; - break; - case COLOR_DEPTH_101010: - stream->dither_option = DITHER_OPTION_SPATIAL10; - break; - default: - option = DITHER_OPTION_DISABLE; - } - } else { - stream->dither_option = option; - } + + stream->dither_option = option; + resource_build_bit_depth_reduction_params(stream, ¶ms); stream->bit_depth_params = params; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fbf7747424a9..ce721b77c1bc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2607,6 +2607,22 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); + if (option == DITHER_OPTION_DEFAULT) { + switch (stream->timing.display_color_depth) { + case COLOR_DEPTH_666: + option = DITHER_OPTION_SPATIAL6; + break; + case COLOR_DEPTH_888: + option = DITHER_OPTION_SPATIAL8; + break; + case COLOR_DEPTH_101010: + option = DITHER_OPTION_SPATIAL10; + break; + default: + option = DITHER_OPTION_DISABLE; + } + } + if (option == DITHER_OPTION_DISABLE) return; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 47e8b582445e..b36220bc619d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1104,15 +1104,11 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); -/*vbios crtc_source_selection and encoder_setup will override fmt_C*/ - if (pipe_ctx->stream->signal != SIGNAL_TYPE_EDP && - pipe_ctx->stream->signal != SIGNAL_TYPE_LVDS) { - /*for embedded panel, don't override VBIOS's setting*/ - pipe_ctx->stream_res.opp->funcs->opp_program_fmt( - pipe_ctx->stream_res.opp, - &stream->bit_depth_params, - &stream->clamping); - } + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( + pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( pipe_ctx->stream_res.stream_enc, -- cgit v1.2.3-59-g8ed1b From 4a6295361c737a80e9f079952ac863a3b0c26acf Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 28 Aug 2017 18:43:45 -0400 Subject: drm/amd/display: Don't reset clock source at unref Powering down the clock source during unref is unsafe as we might want to unref during atomic_check Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 25 ++++++++++++++-------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 +++++++++----- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 +++++--- drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 ++-- 4 files changed, 35 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ce721b77c1bc..57c3dcd3fadd 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -261,31 +261,34 @@ bool resource_construct( } -void resource_unreference_clock_source( +bool resource_unreference_clock_source( struct resource_context *res_ctx, const struct resource_pool *pool, - struct clock_source **clock_source) + struct clock_source *clock_source) { int i; + bool need_reset = false; + for (i = 0; i < pool->clk_src_count; i++) { - if (pool->clock_sources[i] != *clock_source) + if (pool->clock_sources[i] != clock_source) continue; res_ctx->clock_source_ref_count[i]--; if (res_ctx->clock_source_ref_count[i] == 0) - (*clock_source)->funcs->cs_power_down(*clock_source); + need_reset = true; break; } - if (pool->dp_clock_source == *clock_source) { + if (pool->dp_clock_source == clock_source) { res_ctx->dp_clock_source_ref_count--; if (res_ctx->dp_clock_source_ref_count == 0) - (*clock_source)->funcs->cs_power_down(*clock_source); + need_reset = true; } - *clock_source = NULL; + + return need_reset; } void resource_reference_clock_source( @@ -1756,10 +1759,14 @@ bool dc_validate_global_state( if (dc_is_dp_signal(pipe_ctx->stream->signal) && !find_pll_sharable_stream(stream, new_ctx)) { - resource_unreference_clock_source( + if (resource_unreference_clock_source( &new_ctx->res_ctx, dc->res_pool, - &pipe_ctx->clock_source); + pipe_ctx->clock_source)) { + pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source); + pipe_ctx->clock_source = NULL; + } + pipe_ctx->clock_source = dc->res_pool->dp_clock_source; resource_reference_clock_source( &new_ctx->res_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index b36220bc619d..75c636cba545 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1362,9 +1362,12 @@ static void switch_dp_clock_sources( if (clk_src && clk_src != pipe_ctx->clock_source) { - resource_unreference_clock_source( - res_ctx, dc->res_pool, - &pipe_ctx->clock_source); + if (resource_unreference_clock_source(res_ctx, + dc->res_pool, pipe_ctx->clock_source)) { + pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source); + pipe_ctx->clock_source = NULL; + } + pipe_ctx->clock_source = clk_src; resource_reference_clock_source( res_ctx, dc->res_pool, clk_src); @@ -1680,9 +1683,12 @@ static void dce110_reset_hw_ctx_wrap( pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); pipe_ctx_old->plane_res.mi->funcs->free_mem_input( pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); - resource_unreference_clock_source( + if (resource_unreference_clock_source( &dc->current_state->res_ctx, dc->res_pool, - &pipe_ctx_old->clock_source); + pipe_ctx_old->clock_source)) { + pipe_ctx_old->clock_source->funcs->cs_power_down(pipe_ctx_old->clock_source); + pipe_ctx_old->clock_source = NULL; + } dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 6b76fc417456..7460560fbefc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1045,9 +1045,12 @@ static void reset_back_end_for_pipe( } if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) - resource_unreference_clock_source( - &context->res_ctx, dc->res_pool, - &pipe_ctx->clock_source); + if (resource_unreference_clock_source(&context->res_ctx, + dc->res_pool, pipe_ctx->clock_source)) { + pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source); + pipe_ctx->clock_source = NULL; + } + for (i = 0; i < dc->res_pool->pipe_count; i++) if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 41437da5fb9b..cf1797c191e9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -92,10 +92,10 @@ enum dc_status resource_build_scaling_params_for_context( void resource_build_info_frame(struct pipe_ctx *pipe_ctx); -void resource_unreference_clock_source( +bool resource_unreference_clock_source( struct resource_context *res_ctx, const struct resource_pool *pool, - struct clock_source **clock_source); + struct clock_source *clock_source); void resource_reference_clock_source( struct resource_context *res_ctx, -- cgit v1.2.3-59-g8ed1b From 9d0dcecd93e4997c65b18404f1ab2fce2ab79010 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 28 Aug 2017 19:05:17 -0400 Subject: drm/amd/display: Power down clock source at commit Still one more in dc_validate_global Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 ++++++++++------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 22 ++++++++++++++------ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++-------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 ++ 4 files changed, 46 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 57c3dcd3fadd..9aa0da743174 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -275,8 +275,10 @@ bool resource_unreference_clock_source( res_ctx->clock_source_ref_count[i]--; - if (res_ctx->clock_source_ref_count[i] == 0) + if (res_ctx->clock_source_ref_count[i] == 0) { + res_ctx->clock_source_changed[i] = true; need_reset = true; + } break; } @@ -284,8 +286,10 @@ bool resource_unreference_clock_source( if (pool->dp_clock_source == clock_source) { res_ctx->dp_clock_source_ref_count--; - if (res_ctx->dp_clock_source_ref_count == 0) + if (res_ctx->dp_clock_source_ref_count == 0) { + res_ctx->dp_clock_source_changed = true; need_reset = true; + } } return need_reset; @@ -1502,6 +1506,10 @@ bool dc_remove_stream_from_ctx( del_pipe->stream_res.audio, false); + resource_unreference_clock_source(&new_ctx->res_ctx, + dc->res_pool, + del_pipe->clock_source); + memset(del_pipe, 0, sizeof(*del_pipe)); break; @@ -1759,13 +1767,10 @@ bool dc_validate_global_state( if (dc_is_dp_signal(pipe_ctx->stream->signal) && !find_pll_sharable_stream(stream, new_ctx)) { - if (resource_unreference_clock_source( + resource_unreference_clock_source( &new_ctx->res_ctx, dc->res_pool, - pipe_ctx->clock_source)) { - pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source); - pipe_ctx->clock_source = NULL; - } + pipe_ctx->clock_source); pipe_ctx->clock_source = dc->res_pool->dp_clock_source; resource_reference_clock_source( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 75c636cba545..96db166b7fba 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1683,18 +1683,28 @@ static void dce110_reset_hw_ctx_wrap( pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); pipe_ctx_old->plane_res.mi->funcs->free_mem_input( pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); - if (resource_unreference_clock_source( - &dc->current_state->res_ctx, dc->res_pool, - pipe_ctx_old->clock_source)) { - pipe_ctx_old->clock_source->funcs->cs_power_down(pipe_ctx_old->clock_source); - pipe_ctx_old->clock_source = NULL; - } dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); pipe_ctx_old->stream = NULL; } } + + /* power down changed clock sources */ + for (i = 0; i < dc->res_pool->clk_src_count; i++) + if (context->res_ctx.clock_source_changed[i]) { + struct clock_source *clk = dc->res_pool->clock_sources[i]; + + clk->funcs->cs_power_down(clk); + context->res_ctx.clock_source_changed[i] = false; + } + + if (context->res_ctx.dp_clock_source_changed) { + struct clock_source *clk = dc->res_pool->dp_clock_source; + + clk->funcs->cs_power_down(clk); + context->res_ctx.clock_source_changed[i] = false; + } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7460560fbefc..a1f4a00e5e04 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1044,14 +1044,6 @@ static void reset_back_end_for_pipe( pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); } - if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) - if (resource_unreference_clock_source(&context->res_ctx, - dc->res_pool, pipe_ctx->clock_source)) { - pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source); - pipe_ctx->clock_source = NULL; - } - - for (i = 0; i < dc->res_pool->pipe_count; i++) if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) break; @@ -1273,6 +1265,22 @@ static void reset_hw_ctx_wrap( plane_atomic_power_down(dc, i); } + /* power down changed clock sources */ + for (i = 0; i < dc->res_pool->clk_src_count; i++) + if (context->res_ctx.clock_source_changed[i]) { + struct clock_source *clk = dc->res_pool->clock_sources[i]; + + clk->funcs->cs_power_down(clk); + context->res_ctx.clock_source_changed[i] = false; + } + + if (context->res_ctx.dp_clock_source_changed) { + struct clock_source *clk = dc->res_pool->dp_clock_source; + + clk->funcs->cs_power_down(clk); + context->res_ctx.dp_clock_source_changed = false; + } + /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 915d5c10361b..b6a513d6feda 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -213,7 +213,9 @@ struct resource_context { bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; + bool clock_source_changed[MAX_CLOCK_SOURCES]; uint8_t dp_clock_source_ref_count; + bool dp_clock_source_changed; }; struct dce_bw_output { -- cgit v1.2.3-59-g8ed1b From b8ea60cea245e8cd68b6ac45b9680a590f76391a Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 28 Aug 2017 19:44:38 -0400 Subject: drm/amd/display: Remove switching of clk sources at end of commit This should be taken care of in validate now. All of timing sync is quite broken at the moment anyways. Will submit another patch set to address that. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 36 ---------------------- 1 file changed, 36 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 96db166b7fba..c57dc45d6677 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1344,40 +1344,6 @@ static void set_safe_displaymarks( } } -static void switch_dp_clock_sources( - const struct dc *dc, - struct resource_context *res_ctx) -{ - uint8_t i; - for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - - if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) - continue; - - if (dc_is_dp_signal(pipe_ctx->stream->signal)) { - struct clock_source *clk_src = - resource_find_used_clk_src_for_sharing( - res_ctx, pipe_ctx); - - if (clk_src && - clk_src != pipe_ctx->clock_source) { - if (resource_unreference_clock_source(res_ctx, - dc->res_pool, pipe_ctx->clock_source)) { - pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source); - pipe_ctx->clock_source = NULL; - } - - pipe_ctx->clock_source = clk_src; - resource_reference_clock_source( - res_ctx, dc->res_pool, clk_src); - - dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); - } - } - } -} - /******************************************************************************* * Public functions ******************************************************************************/ @@ -1939,8 +1905,6 @@ enum dc_status dce110_apply_ctx_to_hw( dcb->funcs->set_scratch_critical_state(dcb, false); - switch_dp_clock_sources(dc, &context->res_ctx); - #ifdef ENABLE_FBC if (dc->fbc_compressor) enable_fbc(dc, context); -- cgit v1.2.3-59-g8ed1b From 21e67d4d52ca8688feb8c4f6e6d29b2d16d578ad Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 5 Sep 2017 15:50:48 -0400 Subject: drm/amd/display: No need to keep track of unreffed clk sources This simplifies clock source reprogramming a bit. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 18 ++-------------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 21 +++++------------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 25 +++++++--------------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 -- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- 5 files changed, 16 insertions(+), 52 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9aa0da743174..15b627548cd2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -261,13 +261,12 @@ bool resource_construct( } -bool resource_unreference_clock_source( +void resource_unreference_clock_source( struct resource_context *res_ctx, const struct resource_pool *pool, struct clock_source *clock_source) { int i; - bool need_reset = false; for (i = 0; i < pool->clk_src_count; i++) { if (pool->clock_sources[i] != clock_source) @@ -275,24 +274,11 @@ bool resource_unreference_clock_source( res_ctx->clock_source_ref_count[i]--; - if (res_ctx->clock_source_ref_count[i] == 0) { - res_ctx->clock_source_changed[i] = true; - need_reset = true; - } - break; } - if (pool->dp_clock_source == clock_source) { + if (pool->dp_clock_source == clock_source) res_ctx->dp_clock_source_ref_count--; - - if (res_ctx->dp_clock_source_ref_count == 0) { - res_ctx->dp_clock_source_changed = true; - need_reset = true; - } - } - - return need_reset; } void resource_reference_clock_source( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c57dc45d6677..31592e53f504 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1640,6 +1640,8 @@ static void dce110_reset_hw_ctx_wrap( if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + struct clock_source *old_clk = pipe_ctx_old->clock_source; + core_link_disable_stream(pipe_ctx_old); pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { @@ -1650,27 +1652,14 @@ static void dce110_reset_hw_ctx_wrap( pipe_ctx_old->plane_res.mi->funcs->free_mem_input( pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); + if (old_clk) + old_clk->funcs->cs_power_down(old_clk); + dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); pipe_ctx_old->stream = NULL; } } - - /* power down changed clock sources */ - for (i = 0; i < dc->res_pool->clk_src_count; i++) - if (context->res_ctx.clock_source_changed[i]) { - struct clock_source *clk = dc->res_pool->clock_sources[i]; - - clk->funcs->cs_power_down(clk); - context->res_ctx.clock_source_changed[i] = false; - } - - if (context->res_ctx.dp_clock_source_changed) { - struct clock_source *clk = dc->res_pool->dp_clock_source; - - clk->funcs->cs_power_down(clk); - context->res_ctx.clock_source_changed[i] = false; - } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 6fee6957c1a6..c8c4b951ee1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1265,22 +1265,6 @@ static void reset_hw_ctx_wrap( plane_atomic_power_down(dc, i); } - /* power down changed clock sources */ - for (i = 0; i < dc->res_pool->clk_src_count; i++) - if (context->res_ctx.clock_source_changed[i]) { - struct clock_source *clk = dc->res_pool->clock_sources[i]; - - clk->funcs->cs_power_down(clk); - context->res_ctx.clock_source_changed[i] = false; - } - - if (context->res_ctx.dp_clock_source_changed) { - struct clock_source *clk = dc->res_pool->dp_clock_source; - - clk->funcs->cs_power_down(clk); - context->res_ctx.dp_clock_source_changed = false; - } - /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = @@ -1291,9 +1275,16 @@ static void reset_hw_ctx_wrap( continue; if (!pipe_ctx->stream || - pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + struct clock_source *old_clk = pipe_ctx_old->clock_source; + reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); + + if (old_clk) + old_clk->funcs->cs_power_down(old_clk); + } } + } static bool patch_address_for_sbs_tb_stereo( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b6a513d6feda..915d5c10361b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -213,9 +213,7 @@ struct resource_context { bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; - bool clock_source_changed[MAX_CLOCK_SOURCES]; uint8_t dp_clock_source_ref_count; - bool dp_clock_source_changed; }; struct dce_bw_output { diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index cf1797c191e9..614bb691ab59 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -92,7 +92,7 @@ enum dc_status resource_build_scaling_params_for_context( void resource_build_info_frame(struct pipe_ctx *pipe_ctx); -bool resource_unreference_clock_source( +void resource_unreference_clock_source( struct resource_context *res_ctx, const struct resource_pool *pool, struct clock_source *clock_source); -- cgit v1.2.3-59-g8ed1b From 05230fa90d96523755ddad30972a25b6651de739 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Tue, 5 Sep 2017 18:23:46 -0400 Subject: drm/amd/display: Disable FBC for linear tiling - Fixing text console on FBC-enabled builds Signed-off-by: Roman Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 31592e53f504..37497e88a930 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1552,6 +1552,10 @@ static enum dc_status validate_fbc(struct dc *dc, if (pipe_ctx->stream->sink->link->psr_enabled) return DC_ERROR_UNEXPECTED; + /* Only for non-linear tiling */ + if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) + return DC_ERROR_UNEXPECTED; + return DC_OK; } -- cgit v1.2.3-59-g8ed1b From f6baff4d1a0e3235b4a8ffd755e257b998705419 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 8 Sep 2017 10:24:21 -0400 Subject: drm/amd/display: Change comments to bring in line with internal tree Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +++----- drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c | 2 +- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 37497e88a930..5bbfc34d6f01 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1439,13 +1439,11 @@ static uint32_t get_max_pixel_clock_for_all_paths( return max_pix_clk; } -/* Find clock state based on clock requested. if clock value is 0, simply +/* + * Find clock state based on clock requested. if clock value is 0, simply * set clock state as requested without finding clock state by clock value - *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. - * - * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value - * etc support for dcn1.0 */ + static void apply_min_clocks( struct dc *dc, struct dc_state *context, diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c index 98ce0fe5ac37..d3eaf8977a60 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c @@ -372,7 +372,7 @@ static enum aux_channel_operation_result get_channel_status( 10, aux110->timeout_period/10); /* Note that the following bits are set in 'status.bits' - * during CTS 4.2.1.2: + * during CTS 4.2.1.2 (FW 3.3.1): * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP, * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H. * -- cgit v1.2.3-59-g8ed1b From 2004f45ef83f07f43f5da6ede780b08068c7583d Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 27 Sep 2017 10:53:50 -0400 Subject: drm/amd/display: Use kernel alloc/free Abstractions are frowned upon. cocci script: virtual context virtual patch virtual org virtual report @@ expression ptr; @@ - dm_alloc(ptr) + kzalloc(ptr, GFP_KERNEL) @@ expression ptr, size; @@ - dm_realloc(ptr, size) + krealloc(ptr, size, GFP_KERNEL) @@ expression ptr; @@ - dm_free(ptr) + kfree(ptr) v2: use GFP_KERNEL, not GFP_ATOMIC. add cocci script Reviewed-by: Alex Deucher Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/basics/logger.c | 18 ++++--- drivers/gpu/drm/amd/display/dc/basics/vector.c | 19 +++---- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 17 +++--- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 14 ++--- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 5 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc.c | 42 ++++++++------- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 18 +++---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 11 ++-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 15 +++--- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 +++-- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +-- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce110/dce110_compressor.c | 6 +-- .../drm/amd/display/dc/dce110/dce110_resource.c | 61 ++++++++++++---------- .../drm/amd/display/dc/dce112/dce112_compressor.c | 6 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce120/dce120_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce80/dce80_compressor.c | 6 +-- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 47 +++++++++-------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 56 ++++++++++---------- drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c | 4 +- drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 21 ++++---- drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 6 +-- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 2 +- drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 6 +-- .../amd/display/dc/i2caux/dce100/i2caux_dce100.c | 4 +- .../display/dc/i2caux/dce110/aux_engine_dce110.c | 6 +-- .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 7 +-- .../dc/i2caux/dce110/i2c_sw_engine_dce110.c | 7 +-- .../amd/display/dc/i2caux/dce110/i2caux_dce110.c | 6 +-- .../amd/display/dc/i2caux/dce112/i2caux_dce112.c | 4 +- .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 4 +- .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c | 6 +-- .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c | 6 +-- .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 6 +-- .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 4 +- .../display/dc/i2caux/diagnostics/i2caux_diag.c | 7 +-- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c | 6 +-- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 5 +- .../amd/display/dc/irq/dce120/irq_service_dce120.c | 5 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 5 +- .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 5 +- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 2 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../display/dc/virtual/virtual_stream_encoder.c | 4 +- .../drm/amd/display/modules/freesync/freesync.c | 14 ++--- 59 files changed, 362 insertions(+), 330 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 36635486b937..dba54c0a7b5f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2429,7 +2429,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) if (WARN_ON(!crtc->state)) return NULL; - state = dm_alloc(sizeof(*state)); + state = kzalloc(sizeof(*state), GFP_KERNEL); __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 5895dd3903a3..afb6d2d80e0c 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -70,8 +70,8 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; - logger->log_buffer = (char *)dm_alloc(logger->log_buffer_size * - sizeof(char)); + logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char), + GFP_KERNEL); if (!logger->log_buffer) return false; @@ -97,7 +97,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, static void destruct(struct dal_logger *logger) { if (logger->log_buffer) { - dm_free(logger->log_buffer); + kfree(logger->log_buffer); logger->log_buffer = NULL; } } @@ -105,12 +105,13 @@ static void destruct(struct dal_logger *logger) struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask) { /* malloc struct */ - struct dal_logger *logger = dm_alloc(sizeof(struct dal_logger)); + struct dal_logger *logger = kzalloc(sizeof(struct dal_logger), + GFP_KERNEL); if (!logger) return NULL; if (!construct(ctx, logger, log_mask)) { - dm_free(logger); + kfree(logger); return NULL; } @@ -122,7 +123,7 @@ uint32_t dal_logger_destroy(struct dal_logger **logger) if (logger == NULL || *logger == NULL) return 1; destruct(*logger); - dm_free(*logger); + kfree(*logger); *logger = NULL; return 0; @@ -390,7 +391,8 @@ void dm_logger_open( entry->type = log_type; entry->logger = logger; - entry->buf = dm_alloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char)); + entry->buf = kzalloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char), + GFP_KERNEL); entry->buf_offset = 0; entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char); @@ -421,7 +423,7 @@ void dm_logger_close(struct log_entry *entry) cleanup: if (entry->buf) { - dm_free(entry->buf); + kfree(entry->buf); entry->buf = NULL; entry->buf_offset = 0; entry->max_buf_bytes = 0; diff --git a/drivers/gpu/drm/amd/display/dc/basics/vector.c b/drivers/gpu/drm/amd/display/dc/basics/vector.c index bb72a1857160..e00fc4db3ac4 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/vector.c +++ b/drivers/gpu/drm/amd/display/dc/basics/vector.c @@ -40,7 +40,7 @@ bool dal_vector_construct( return false; } - vector->container = dm_alloc(struct_size * capacity); + vector->container = kzalloc(struct_size * capacity, GFP_KERNEL); if (vector->container == NULL) return false; vector->capacity = capacity; @@ -67,7 +67,7 @@ bool dal_vector_presized_costruct( return false; } - vector->container = dm_alloc(struct_size * count); + vector->container = kzalloc(struct_size * count, GFP_KERNEL); if (vector->container == NULL) return false; @@ -95,7 +95,7 @@ struct vector *dal_vector_presized_create( void *initial_value, uint32_t struct_size) { - struct vector *vector = dm_alloc(sizeof(struct vector)); + struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL); if (vector == NULL) return NULL; @@ -105,7 +105,7 @@ struct vector *dal_vector_presized_create( return vector; BREAK_TO_DEBUGGER(); - dm_free(vector); + kfree(vector); return NULL; } @@ -114,7 +114,7 @@ struct vector *dal_vector_create( uint32_t capacity, uint32_t struct_size) { - struct vector *vector = dm_alloc(sizeof(struct vector)); + struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL); if (vector == NULL) return NULL; @@ -123,7 +123,7 @@ struct vector *dal_vector_create( return vector; BREAK_TO_DEBUGGER(); - dm_free(vector); + kfree(vector); return NULL; } @@ -131,7 +131,7 @@ void dal_vector_destruct( struct vector *vector) { if (vector->container != NULL) - dm_free(vector->container); + kfree(vector->container); vector->count = 0; vector->capacity = 0; } @@ -142,7 +142,7 @@ void dal_vector_destroy( if (vector == NULL || *vector == NULL) return; dal_vector_destruct(*vector); - dm_free(*vector); + kfree(*vector); *vector = NULL; } @@ -290,7 +290,8 @@ bool dal_vector_reserve(struct vector *vector, uint32_t capacity) if (capacity <= vector->capacity) return true; - new_container = dm_realloc(vector->container, capacity * vector->struct_size); + new_container = krealloc(vector->container, + capacity * vector->struct_size, GFP_KERNEL); if (new_container) { vector->container = new_container; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 2c411441771b..47d673a1f688 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -116,14 +116,14 @@ struct dc_bios *bios_parser_create( { struct bios_parser *bp = NULL; - bp = dm_alloc(sizeof(struct bios_parser)); + bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); if (!bp) return NULL; if (bios_parser_construct(bp, init, dce_version)) return &bp->base; - dm_free(bp); + kfree(bp); BREAK_TO_DEBUGGER(); return NULL; } @@ -131,10 +131,10 @@ struct dc_bios *bios_parser_create( static void destruct(struct bios_parser *bp) { if (bp->base.bios_local_image) - dm_free(bp->base.bios_local_image); + kfree(bp->base.bios_local_image); if (bp->base.integrated_info) - dm_free(bp->base.integrated_info); + kfree(bp->base.integrated_info); } static void bios_parser_destroy(struct dc_bios **dcb) @@ -148,7 +148,7 @@ static void bios_parser_destroy(struct dc_bios **dcb) destruct(bp); - dm_free(bp); + kfree(bp); *dcb = NULL; } @@ -3531,7 +3531,8 @@ static void process_ext_display_connection_info(struct bios_parser *bp) uint8_t *original_bios; /* Step 1: Replace bios image with the new copy which will be * patched */ - bp->base.bios_local_image = dm_alloc(bp->base.bios_size); + bp->base.bios_local_image = kzalloc(bp->base.bios_size, + GFP_KERNEL); if (bp->base.bios_local_image == NULL) { BREAK_TO_DEBUGGER(); /* Failed to alloc bp->base.bios_local_image */ @@ -3965,7 +3966,7 @@ static struct integrated_info *bios_parser_create_integrated_info( struct bios_parser *bp = BP_FROM_DCB(dcb); struct integrated_info *info = NULL; - info = dm_alloc(sizeof(struct integrated_info)); + info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); if (info == NULL) { ASSERT_CRITICAL(0); @@ -3975,7 +3976,7 @@ static struct integrated_info *bios_parser_create_integrated_info( if (construct_integrated_info(bp, info) == BP_RESULT_OK) return info; - dm_free(info); + kfree(info); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 95fe50f62c57..3f8e605efde9 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -107,10 +107,10 @@ static struct atom_encoder_caps_record *get_encoder_cap_record( static void destruct(struct bios_parser *bp) { if (bp->base.bios_local_image) - dm_free(bp->base.bios_local_image); + kfree(bp->base.bios_local_image); if (bp->base.integrated_info) - dm_free(bp->base.integrated_info); + kfree(bp->base.integrated_info); } static void firmware_parser_destroy(struct dc_bios **dcb) @@ -124,7 +124,7 @@ static void firmware_parser_destroy(struct dc_bios **dcb) destruct(bp); - dm_free(bp); + kfree(bp); *dcb = NULL; } @@ -2030,7 +2030,7 @@ static struct integrated_info *bios_parser_create_integrated_info( struct bios_parser *bp = BP_FROM_DCB(dcb); struct integrated_info *info = NULL; - info = dm_alloc(sizeof(struct integrated_info)); + info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); if (info == NULL) { ASSERT_CRITICAL(0); @@ -2040,7 +2040,7 @@ static struct integrated_info *bios_parser_create_integrated_info( if (construct_integrated_info(bp, info) == BP_RESULT_OK) return info; - dm_free(info); + kfree(info); return NULL; } @@ -2205,14 +2205,14 @@ struct dc_bios *firmware_parser_create( { struct bios_parser *bp = NULL; - bp = dm_alloc(sizeof(struct bios_parser)); + bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); if (!bp) return NULL; if (bios_parser_construct(bp, init, dce_version)) return &bp->base; - dm_free(bp); + kfree(bp); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index dba25853f7f9..15cbfc400633 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2792,7 +2792,8 @@ bool bw_calcs(struct dc_context *ctx, int pipe_count, struct dce_bw_output *calcs_output) { - struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data)); + struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data), + GFP_KERNEL); populate_initial_data(pipe, pipe_count, data); @@ -3248,7 +3249,7 @@ bool bw_calcs(struct dc_context *ctx, calcs_output->sclk_khz = 0; } - dm_free(data); + kfree(data); return is_display_configuration_supported(vbios, calcs_output); } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1b0f64756be6..91f43a1b88ee 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -481,8 +481,8 @@ static void dcn_dml_wm_override( { int i, in_idx, active_count; - struct _vcs_dpi_display_e2e_pipe_params_st *input = dm_alloc(pool->pipe_count * - sizeof(struct _vcs_dpi_display_e2e_pipe_params_st)); + struct _vcs_dpi_display_e2e_pipe_params_st *input = kzalloc(pool->pipe_count * sizeof(struct _vcs_dpi_display_e2e_pipe_params_st), + GFP_KERNEL); struct wm { double urgent; struct _vcs_dpi_cstate_pstate_watermarks_st cpstate; @@ -560,7 +560,7 @@ static void dcn_dml_wm_override( pipe->plane_state->flip_immediate); in_idx++; } - dm_free(input); + kfree(input); } static void split_stream_across_pipes( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 58c5083bef2a..d86d9796e4cc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -113,7 +113,7 @@ static bool create_links( } for (i = 0; i < num_virtual_links; i++) { - struct dc_link *link = dm_alloc(sizeof(*link)); + struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL); struct encoder_init_data enc_init = {0}; if (link == NULL) { @@ -127,7 +127,7 @@ static bool create_links( link->link_id.type = OBJECT_TYPE_CONNECTOR; link->link_id.id = CONNECTOR_ID_VIRTUAL; link->link_id.enum_id = ENUM_ID_1; - link->link_enc = dm_alloc(sizeof(*link->link_enc)); + link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL); enc_init.ctx = dc->ctx; enc_init.channel = CHANNEL_ID_UNKNOWN; @@ -413,20 +413,20 @@ static void destruct(struct dc *dc) if (dc->ctx->logger) dal_logger_destroy(&dc->ctx->logger); - dm_free(dc->ctx); + kfree(dc->ctx); dc->ctx = NULL; - dm_free(dc->bw_vbios); + kfree(dc->bw_vbios); dc->bw_vbios = NULL; - dm_free(dc->bw_dceip); + kfree(dc->bw_dceip); dc->bw_dceip = NULL; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - dm_free(dc->dcn_soc); + kfree(dc->dcn_soc); dc->dcn_soc = NULL; - dm_free(dc->dcn_ip); + kfree(dc->dcn_ip); dc->dcn_ip = NULL; #endif @@ -436,12 +436,15 @@ static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; - struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); - struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip)); - struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios)); + struct dc_context *dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); + struct bw_calcs_dceip *dc_dceip = kzalloc(sizeof(*dc_dceip), + GFP_KERNEL); + struct bw_calcs_vbios *dc_vbios = kzalloc(sizeof(*dc_vbios), + GFP_KERNEL); #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc = dm_alloc(sizeof(*dcn_soc)); - struct dcn_ip_params *dcn_ip = dm_alloc(sizeof(*dcn_ip)); + struct dcn_soc_bounding_box *dcn_soc = kzalloc(sizeof(*dcn_soc), + GFP_KERNEL); + struct dcn_ip_params *dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL); #endif enum dce_version dc_version = DCE_VERSION_UNKNOWN; @@ -604,7 +607,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct dc *dc = dm_alloc(sizeof(*dc)); + struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL); unsigned int full_pipe_count; if (NULL == dc) @@ -638,7 +641,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) return dc; construct_fail: - dm_free(dc); + kfree(dc); alloc_fail: return NULL; @@ -647,7 +650,7 @@ alloc_fail: void dc_destroy(struct dc **dc) { destruct(*dc); - dm_free(*dc); + kfree(*dc); *dc = NULL; } @@ -900,7 +903,7 @@ bool dc_commit_planes_to_stream( struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; struct dc_stream_update *stream_update = - dm_alloc(sizeof(struct dc_stream_update)); + kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); if (!stream_update) { BREAK_TO_DEBUGGER(); @@ -951,13 +954,14 @@ bool dc_commit_planes_to_stream( dc_post_update_surfaces_to_stream(dc); - dm_free(stream_update); + kfree(stream_update); return true; } struct dc_state *dc_create_state(void) { - struct dc_state *context = dm_alloc(sizeof(struct dc_state)); + struct dc_state *context = kzalloc(sizeof(struct dc_state), + GFP_KERNEL); if (!context) return NULL; @@ -979,7 +983,7 @@ void dc_release_state(struct dc_state *context) if (atomic_read(&context->ref_count) == 0) { dc_resource_state_destruct(context); - dm_free(context); + kfree(context); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 845ec421d861..43ebd8941b77 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1100,7 +1100,7 @@ create_fail: struct dc_link *link_create(const struct link_init_data *init_params) { struct dc_link *link = - dm_alloc(sizeof(*link)); + kzalloc(sizeof(*link), GFP_KERNEL); if (NULL == link) goto alloc_fail; @@ -1111,7 +1111,7 @@ struct dc_link *link_create(const struct link_init_data *init_params) return link; construct_fail: - dm_free(link); + kfree(link); alloc_fail: return NULL; @@ -1120,7 +1120,7 @@ alloc_fail: void link_destroy(struct dc_link **link) { destruct(*link); - dm_free(*link); + kfree(*link); *link = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index d09e539397ea..226512c11ab7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -130,7 +130,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_ { struct i2c_payloads *payloads; - payloads = dm_alloc(sizeof(struct i2c_payloads)); + payloads = kzalloc(sizeof(struct i2c_payloads), GFP_KERNEL); if (!payloads) return NULL; @@ -139,7 +139,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_ &payloads->payloads, ctx, count, sizeof(struct i2c_payload))) return payloads; - dm_free(payloads); + kfree(payloads); return NULL; } @@ -159,7 +159,7 @@ void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p) if (!p || !*p) return; dal_vector_destruct(&(*p)->payloads); - dm_free(*p); + kfree(*p); *p = NULL; } @@ -168,7 +168,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_ { struct aux_payloads *payloads; - payloads = dm_alloc(sizeof(struct aux_payloads)); + payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL); if (!payloads) return NULL; @@ -177,7 +177,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_ &payloads->payloads, ctx, count, sizeof(struct aux_payload))) return payloads; - dm_free(payloads); + kfree(payloads); return NULL; } @@ -197,7 +197,7 @@ void dal_ddc_aux_payloads_destroy(struct aux_payloads **p) return; dal_vector_destruct(&(*p)->payloads); - dm_free(*p); + kfree(*p); *p = NULL; } @@ -290,7 +290,7 @@ struct ddc_service *dal_ddc_service_create( { struct ddc_service *ddc_service; - ddc_service = dm_alloc(sizeof(struct ddc_service)); + ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL); if (!ddc_service) return NULL; @@ -298,7 +298,7 @@ struct ddc_service *dal_ddc_service_create( if (construct(ddc_service, init_data)) return ddc_service; - dm_free(ddc_service); + kfree(ddc_service); return NULL; } @@ -315,7 +315,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc) return; } destruct(*ddc); - dm_free(*ddc); + kfree(*ddc); *ddc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index dcfdfebd5c62..1832f252edab 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -160,7 +160,7 @@ void dc_destroy_resource_pool(struct dc *dc) dc->res_pool->funcs->destroy(&dc->res_pool); if (dc->hwseq) - dm_free(dc->hwseq); + kfree(dc->hwseq); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index 7717350297a5..b3bbafc8fd6a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -34,7 +34,7 @@ static void destruct(struct dc_sink *sink) { if (sink->dc_container_id) { - dm_free(sink->dc_container_id); + kfree(sink->dc_container_id); sink->dc_container_id = NULL; } } @@ -74,13 +74,13 @@ void dc_sink_release(struct dc_sink *sink) if (atomic_read(&sink->ref_count) == 0) { destruct(sink); - dm_free(sink); + kfree(sink); } } struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) { - struct dc_sink *sink = dm_alloc(sizeof(*sink)); + struct dc_sink *sink = kzalloc(sizeof(*sink), GFP_KERNEL); if (NULL == sink) goto alloc_fail; @@ -93,7 +93,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) return sink; construct_fail: - dm_free(sink); + kfree(sink); alloc_fail: return NULL; @@ -117,7 +117,8 @@ bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container { if (dc_sink && container_id) { if (!dc_sink->dc_container_id) - dc_sink->dc_container_id = dm_alloc(sizeof(*dc_sink->dc_container_id)); + dc_sink->dc_container_id = kzalloc(sizeof(*dc_sink->dc_container_id), + GFP_KERNEL); if (dc_sink->dc_container_id) { memmove(&dc_sink->dc_container_id->guid, &container_id->guid, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a421779093d9..d5da847ffad6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -131,7 +131,7 @@ void dc_stream_release(struct dc_stream_state *stream) if (atomic_read(&stream->ref_count) == 0) { destruct(stream); - dm_free(stream); + kfree(stream); } } } @@ -144,7 +144,7 @@ struct dc_stream_state *dc_create_stream_for_sink( if (sink == NULL) goto alloc_fail; - stream = dm_alloc(sizeof(struct dc_stream_state)); + stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); if (NULL == stream) goto alloc_fail; @@ -157,7 +157,7 @@ struct dc_stream_state *dc_create_stream_for_sink( return stream; construct_fail: - dm_free(stream); + kfree(stream); alloc_fail: return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index e96f63eed070..511ada94530e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -68,7 +68,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) { struct dc *core_dc = dc; - struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); + struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state), + GFP_KERNEL); if (NULL == plane_state) goto alloc_fail; @@ -81,7 +82,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) return plane_state; construct_fail: - dm_free(plane_state); + kfree(plane_state); alloc_fail: return NULL; @@ -133,7 +134,7 @@ void dc_plane_state_release(struct dc_plane_state *plane_state) if (atomic_read(&plane_state->ref_count) == 0) { destruct(plane_state); - dm_free(plane_state); + kfree(plane_state); } } @@ -149,14 +150,14 @@ void dc_gamma_release(struct dc_gamma **gamma) atomic_dec(&(*gamma)->ref_count); if (atomic_read(&(*gamma)->ref_count) == 0) - dm_free((*gamma)); + kfree((*gamma)); *gamma = NULL; } struct dc_gamma *dc_create_gamma() { - struct dc_gamma *gamma = dm_alloc(sizeof(*gamma)); + struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL); if (gamma == NULL) goto alloc_fail; @@ -181,12 +182,12 @@ void dc_transfer_func_release(struct dc_transfer_func *tf) atomic_dec(&tf->ref_count); if (atomic_read(&tf->ref_count) == 0) - dm_free(tf); + kfree(tf); } struct dc_transfer_func *dc_create_transfer_func() { - struct dc_transfer_func *tf = dm_alloc(sizeof(*tf)); + struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL); if (tf == NULL) goto alloc_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 0e9d914e1a8f..0e0336c5af4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -462,7 +462,7 @@ struct abm *dce_abm_create( const struct dce_abm_shift *abm_shift, const struct dce_abm_mask *abm_mask) { - struct dce_abm *abm_dce = dm_alloc(sizeof(*abm_dce)); + struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL); if (abm_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -480,6 +480,6 @@ void dce_abm_destroy(struct abm **abm) { struct dce_abm *abm_dce = TO_DCE_ABM(*abm); - dm_free(abm_dce); + kfree(abm_dce); *abm = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index b94c1e5d85cb..198f4532e100 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -897,7 +897,7 @@ void dce_aud_destroy(struct audio **audio) { struct dce_audio *aud = DCE_AUD(*audio); - dm_free(aud); + kfree(aud); *audio = NULL; } @@ -909,7 +909,7 @@ struct audio *dce_audio_create( const struct dce_aduio_mask *masks ) { - struct dce_audio *audio = dm_alloc(sizeof(*audio)); + struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); if (audio == NULL) { ASSERT_CRITICAL(audio); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index d3b61b92ebec..31280d252753 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1084,12 +1084,14 @@ static void get_ss_info_from_atombios( if (*ss_entries_num == 0) return; - ss_info = dm_alloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num)); + ss_info = kzalloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num), + GFP_KERNEL); ss_info_cur = ss_info; if (ss_info == NULL) return; - ss_data = dm_alloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num)); + ss_data = kzalloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num), + GFP_KERNEL); if (ss_data == NULL) goto out_free_info; @@ -1157,14 +1159,14 @@ static void get_ss_info_from_atombios( } *spread_spectrum_data = ss_data; - dm_free(ss_info); + kfree(ss_info); return; out_free_data: - dm_free(ss_data); + kfree(ss_data); *ss_entries_num = 0; out_free_info: - dm_free(ss_info); + kfree(ss_info); } static void ss_info_from_atombios_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 06d9a3e7c8a2..3e9ff2f5472d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -719,7 +719,7 @@ struct display_clock *dce_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -742,7 +742,7 @@ struct display_clock *dce110_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -767,7 +767,7 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -788,7 +788,7 @@ struct display_clock *dce112_disp_clk_create( struct display_clock *dce120_disp_clk_create(struct dc_context *ctx) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); struct dm_pp_clock_levels_with_voltage clk_level_info = {0}; if (clk_dce == NULL) { @@ -822,6 +822,6 @@ void dce_disp_clk_destroy(struct display_clock **disp_clk) { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); - dm_free(clk_dce); + kfree(clk_dce); *disp_clk = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 313f61bf06e1..f9873cad40e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -573,7 +573,7 @@ struct dmcu *dce_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -595,7 +595,7 @@ struct dmcu *dcn10_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -615,6 +615,6 @@ void dce_dmcu_destroy(struct dmcu **dmcu) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); - dm_free(dmcu_dce); + kfree(dmcu_dce); *dmcu = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index e010cf10d605..fa481d481132 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -261,6 +261,6 @@ void dce_ipp_construct( void dce_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCE_IPP(*ipp)); + kfree(TO_DCE_IPP(*ipp)); *ipp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 0ce94ede80bf..2ce730de0dc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1108,7 +1108,7 @@ void dce110_link_encoder_hw_init( void dce110_link_encoder_destroy(struct link_encoder **enc) { - dm_free(TO_DCE110_LINK_ENC(*enc)); + kfree(TO_DCE110_LINK_ENC(*enc)); *enc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 348e4b7047f1..c0736aeabd85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -563,7 +563,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp) { if (*opp) - dm_free(FROM_DCE11_OPP(*opp)); + kfree(FROM_DCE11_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index ca6c7c2a1b4c..9a75bde32611 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -370,7 +370,7 @@ static struct timing_generator *dce100_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -380,7 +380,7 @@ static struct timing_generator *dce100_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -389,7 +389,7 @@ static struct stream_encoder *dce100_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -400,7 +400,7 @@ static struct stream_encoder *dce100_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -422,7 +422,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce100_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -467,7 +467,8 @@ static struct mem_input *dce100_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -481,7 +482,7 @@ static struct mem_input *dce100_mem_input_create( static void dce100_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -490,7 +491,7 @@ static struct transform *dce100_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -501,14 +502,14 @@ static struct transform *dce100_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } static struct input_pixel_processor *dce100_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -532,7 +533,7 @@ struct link_encoder *dce100_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -549,7 +550,7 @@ struct link_encoder *dce100_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -558,7 +559,7 @@ struct output_pixel_processor *dce100_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -568,7 +569,7 @@ struct output_pixel_processor *dce100_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -580,7 +581,7 @@ struct clock_source *dce100_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -597,7 +598,7 @@ struct clock_source *dce100_clock_source_create( void dce100_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -616,19 +617,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -768,7 +769,7 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -950,7 +951,7 @@ struct resource_pool *dce100_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index f82c26995609..90770cb2ffcd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -388,7 +388,7 @@ void dce110_compressor_set_fbc_invalidation_triggers( struct compressor *dce110_compressor_create(struct dc_context *ctx) { struct dce110_compressor *cp110 = - dm_alloc(sizeof(struct dce110_compressor)); + kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL); if (!cp110) return NULL; @@ -397,13 +397,13 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx) return &cp110->base; BREAK_TO_DEBUGGER(); - dm_free(cp110); + kfree(cp110); return NULL; } void dce110_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE110_COMPRESSOR(*compressor)); + kfree(TO_DCE110_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 25eda52c32ef..787e20e15221 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -405,7 +405,7 @@ static struct timing_generator *dce110_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -414,7 +414,7 @@ static struct timing_generator *dce110_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -423,7 +423,7 @@ static struct stream_encoder *dce110_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -434,7 +434,7 @@ static struct stream_encoder *dce110_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -460,7 +460,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce110_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -505,7 +505,8 @@ static struct mem_input *dce110_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -519,7 +520,7 @@ static struct mem_input *dce110_mem_input_create( static void dce110_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -528,7 +529,7 @@ static struct transform *dce110_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -538,14 +539,14 @@ static struct transform *dce110_transform_create( return &transform->base; BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } static struct input_pixel_processor *dce110_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -569,7 +570,7 @@ static struct link_encoder *dce110_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -586,7 +587,7 @@ static struct link_encoder *dce110_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -595,7 +596,7 @@ static struct output_pixel_processor *dce110_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -605,7 +606,7 @@ static struct output_pixel_processor *dce110_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -617,7 +618,7 @@ struct clock_source *dce110_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -642,15 +643,15 @@ void dce110_clock_source_destroy(struct clock_source **clk_src) dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); if (dce110_clk_src->dp_ss_params) - dm_free(dce110_clk_src->dp_ss_params); + kfree(dce110_clk_src->dp_ss_params); if (dce110_clk_src->hdmi_ss_params) - dm_free(dce110_clk_src->hdmi_ss_params); + kfree(dce110_clk_src->hdmi_ss_params); if (dce110_clk_src->dvi_ss_params) - dm_free(dce110_clk_src->dvi_ss_params); + kfree(dce110_clk_src->dvi_ss_params); - dm_free(dce110_clk_src); + kfree(dce110_clk_src); *clk_src = NULL; } @@ -669,19 +670,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -1031,7 +1032,7 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1048,10 +1049,14 @@ static const struct resource_funcs dce110_res_pool_funcs = { static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) { - struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); - struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); - struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); - struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); + struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), + GFP_KERNEL); + struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), + GFP_KERNEL); + struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), + GFP_KERNEL); + struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), + GFP_KERNEL); if ((dce110_tgv == NULL) || (dce110_xfmv == NULL) || @@ -1332,7 +1337,7 @@ struct resource_pool *dce110_create_resource_pool( struct hw_asic_id asic_id) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c index 75af2125344b..e75895baa132 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c @@ -839,7 +839,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, struct compressor *dce112_compressor_create(struct dc_context *ctx) { struct dce112_compressor *cp110 = - dm_alloc(sizeof(struct dce112_compressor)); + kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL); if (!cp110) return NULL; @@ -848,12 +848,12 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx) return &cp110->base; BREAK_TO_DEBUGGER(); - dm_free(cp110); + kfree(cp110); return NULL; } void dce112_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE112_COMPRESSOR(*compressor)); + kfree(TO_DCE112_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index de6f71d8a89b..4e2ed3429a90 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -410,7 +410,7 @@ static struct timing_generator *dce112_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -419,7 +419,7 @@ static struct timing_generator *dce112_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -428,7 +428,7 @@ static struct stream_encoder *dce112_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -439,7 +439,7 @@ static struct stream_encoder *dce112_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -461,7 +461,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce112_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -501,7 +501,8 @@ static struct mem_input *dce112_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -514,7 +515,7 @@ static struct mem_input *dce112_mem_input_create( static void dce112_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -523,7 +524,7 @@ static struct transform *dce112_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -535,7 +536,7 @@ static struct transform *dce112_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -554,7 +555,7 @@ struct link_encoder *dce112_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -571,14 +572,14 @@ struct link_encoder *dce112_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } static struct input_pixel_processor *dce112_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -595,7 +596,7 @@ struct output_pixel_processor *dce112_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -605,7 +606,7 @@ struct output_pixel_processor *dce112_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -617,7 +618,7 @@ struct clock_source *dce112_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -634,7 +635,7 @@ struct clock_source *dce112_clock_source_create( void dce112_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -653,19 +654,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -940,7 +941,7 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1298,7 +1299,7 @@ struct resource_pool *dce112_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index e5d2d98982f7..6b5d5948ddb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -351,7 +351,7 @@ struct output_pixel_processor *dce120_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -361,7 +361,7 @@ struct output_pixel_processor *dce120_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -388,7 +388,7 @@ struct clock_source *dce120_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(*clk_src)); + kzalloc(sizeof(*clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -405,7 +405,7 @@ struct clock_source *dce120_clock_source_create( void dce120_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -428,7 +428,7 @@ static struct timing_generator *dce120_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -437,13 +437,13 @@ static struct timing_generator *dce120_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } static void dce120_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -462,7 +462,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -471,7 +471,7 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } @@ -483,7 +483,7 @@ static void destruct(struct dce110_resource_pool *pool) for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -539,7 +539,7 @@ static struct link_encoder *dce120_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -556,14 +556,14 @@ static struct link_encoder *dce120_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } static struct input_pixel_processor *dce120_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -580,7 +580,7 @@ static struct stream_encoder *dce120_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -591,7 +591,7 @@ static struct stream_encoder *dce120_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -614,7 +614,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce120_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -654,7 +654,8 @@ static struct mem_input *dce120_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -670,7 +671,7 @@ static struct transform *dce120_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -682,7 +683,7 @@ static struct transform *dce120_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -691,7 +692,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1006,7 +1007,7 @@ struct resource_pool *dce120_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c index 77626d7624c6..cc1c0d390945 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c @@ -819,7 +819,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, struct compressor *dce80_compressor_create(struct dc_context *ctx) { struct dce80_compressor *cp80 = - dm_alloc(sizeof(struct dce80_compressor)); + kzalloc(sizeof(struct dce80_compressor), GFP_KERNEL); if (!cp80) return NULL; @@ -828,12 +828,12 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx) return &cp80->base; BREAK_TO_DEBUGGER(); - dm_free(cp80); + kfree(cp80); return NULL; } void dce80_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE80_COMPRESSOR(*compressor)); + kfree(TO_DCE80_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5453f02ea8ca..170509a4a221 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -399,7 +399,7 @@ static struct timing_generator *dce80_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -408,7 +408,7 @@ static struct timing_generator *dce80_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -417,7 +417,7 @@ static struct output_pixel_processor *dce80_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -427,7 +427,7 @@ static struct output_pixel_processor *dce80_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -436,7 +436,7 @@ static struct stream_encoder *dce80_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -447,7 +447,7 @@ static struct stream_encoder *dce80_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -469,7 +469,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce80_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -514,7 +514,8 @@ static struct mem_input *dce80_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -528,7 +529,7 @@ static struct mem_input *dce80_mem_input_create( static void dce80_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -537,7 +538,7 @@ static struct transform *dce80_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -549,7 +550,7 @@ static struct transform *dce80_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -565,7 +566,7 @@ struct link_encoder *dce80_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -582,7 +583,7 @@ struct link_encoder *dce80_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -594,7 +595,7 @@ struct clock_source *dce80_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -611,14 +612,14 @@ struct clock_source *dce80_clock_source_create( void dce80_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } static struct input_pixel_processor *dce80_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -645,19 +646,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -781,7 +782,7 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -948,7 +949,7 @@ struct resource_pool *dce80_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; @@ -1113,7 +1114,7 @@ struct resource_pool *dce81_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; @@ -1274,7 +1275,7 @@ struct resource_pool *dce83_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 5e0e2464eab3..67bd6a738fe9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -225,7 +225,7 @@ static void ippn10_cursor_set_position( static void dcn10_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCN10_IPP(*ipp)); + kfree(TO_DCN10_IPP(*ipp)); *ipp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 8048782ac599..a136f70b7a3c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -314,7 +314,7 @@ static void oppn10_set_stereo_polarity( static void dcn10_opp_destroy(struct output_pixel_processor **opp) { - dm_free(TO_DCN10_OPP(*opp)); + kfree(TO_DCN10_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 298eb44ad9bf..71adda0e5b59 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -468,7 +468,7 @@ static const struct dc_debug debug_defaults_diags = { static void dcn10_dpp_destroy(struct transform **xfm) { - dm_free(TO_DCN10_DPP(*xfm)); + kfree(TO_DCN10_DPP(*xfm)); *xfm = NULL; } @@ -477,7 +477,7 @@ static struct transform *dcn10_dpp_create( uint32_t inst) { struct dcn10_dpp *dpp = - dm_alloc(sizeof(struct dcn10_dpp)); + kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); if (!dpp) return NULL; @@ -487,7 +487,7 @@ static struct transform *dcn10_dpp_create( return &dpp->base; BREAK_TO_DEBUGGER(); - dm_free(dpp); + kfree(dpp); return NULL; } @@ -495,7 +495,7 @@ static struct input_pixel_processor *dcn10_ipp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_ipp *ipp = - dm_alloc(sizeof(struct dcn10_ipp)); + kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -512,7 +512,7 @@ static struct output_pixel_processor *dcn10_opp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_opp *opp = - dm_alloc(sizeof(struct dcn10_opp)); + kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); if (!opp) { BREAK_TO_DEBUGGER(); @@ -526,7 +526,8 @@ static struct output_pixel_processor *dcn10_opp_create( static struct mpc *dcn10_mpc_create(struct dc_context *ctx) { - struct dcn10_mpc *mpc10 = dm_alloc(sizeof(struct dcn10_mpc)); + struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), + GFP_KERNEL); if (!mpc10) return NULL; @@ -545,7 +546,7 @@ static struct timing_generator *dcn10_timing_generator_create( uint32_t instance) { struct dcn10_timing_generator *tgn10 = - dm_alloc(sizeof(struct dcn10_timing_generator)); + kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL); if (!tgn10) return NULL; @@ -577,7 +578,7 @@ struct link_encoder *dcn10_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -594,7 +595,7 @@ struct link_encoder *dcn10_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -606,7 +607,7 @@ struct clock_source *dcn10_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -641,7 +642,7 @@ static struct stream_encoder *dcn10_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -652,7 +653,7 @@ static struct stream_encoder *dcn10_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -671,7 +672,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dcn10_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -698,13 +699,13 @@ static const struct resource_create_funcs res_create_maximus_funcs = { void dcn10_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) { - struct pp_smu_funcs_rv *pp_smu = dm_alloc(sizeof(*pp_smu)); + struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); if (!pp_smu) return pp_smu; @@ -722,13 +723,13 @@ static void destruct(struct dcn10_resource_pool *pool) /* TODO: free dcn version of stream encoder once implemented * rather than using virtual stream encoder */ - dm_free(pool->base.stream_enc[i]); + kfree(pool->base.stream_enc[i]); pool->base.stream_enc[i] = NULL; } } if (pool->base.mpc != NULL) { - dm_free(TO_DCN10_MPC(pool->base.mpc)); + kfree(TO_DCN10_MPC(pool->base.mpc)); pool->base.mpc = NULL; } for (i = 0; i < pool->base.pipe_count; i++) { @@ -742,7 +743,7 @@ static void destruct(struct dcn10_resource_pool *pool) pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCN10_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCN10_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -751,14 +752,14 @@ static void destruct(struct dcn10_resource_pool *pool) } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.audio_count; i++) { @@ -767,7 +768,7 @@ static void destruct(struct dcn10_resource_pool *pool) } for (i = 0; i < pool->base.res_cap->num_dwb; i++) { - dm_free(pool->base.dwbc[i]); + kfree(pool->base.dwbc[i]); pool->base.dwbc[i] = NULL; } @@ -792,7 +793,7 @@ static void destruct(struct dcn10_resource_pool *pool) if (pool->base.display_clock != NULL) dce_disp_clk_destroy(&pool->base.display_clock); - dm_free(pool->base.pp_smu); + kfree(pool->base.pp_smu); } static struct mem_input *dcn10_mem_input_create( @@ -800,7 +801,7 @@ static struct mem_input *dcn10_mem_input_create( uint32_t inst) { struct dcn10_mem_input *mem_inputn10 = - dm_alloc(sizeof(struct dcn10_mem_input)); + kzalloc(sizeof(struct dcn10_mem_input), GFP_KERNEL); if (!mem_inputn10) return NULL; @@ -810,7 +811,7 @@ static struct mem_input *dcn10_mem_input_create( return &mem_inputn10->base; BREAK_TO_DEBUGGER(); - dm_free(mem_inputn10); + kfree(mem_inputn10); return NULL; } @@ -1207,7 +1208,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool) struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); destruct(dcn10_pool); - dm_free(dcn10_pool); + kfree(dcn10_pool); *pool = NULL; } @@ -1239,7 +1240,8 @@ static bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { - struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc)); + struct dcn10_dwbc *dwbc10 = kzalloc(sizeof(struct dcn10_dwbc), + GFP_KERNEL); if (!dwbc10) { dm_error("DC: failed to create dwbc10!\n"); @@ -1517,7 +1519,7 @@ struct resource_pool *dcn10_create_resource_pool( struct dc *dc) { struct dcn10_resource_pool *pool = - dm_alloc(sizeof(struct dcn10_resource_pool)); + kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c index d42eb3de2ea4..1d1efd72b291 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c @@ -239,7 +239,7 @@ struct gpio *dal_gpio_create( uint32_t en, enum gpio_pin_output_state output_state) { - struct gpio *gpio = dm_alloc(sizeof(struct gpio)); + struct gpio *gpio = kzalloc(sizeof(struct gpio), GFP_KERNEL); if (!gpio) { ASSERT_CRITICAL(false); @@ -266,7 +266,7 @@ void dal_gpio_destroy( dal_gpio_close(*gpio); - dm_free(*gpio); + kfree(*gpio); *gpio = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c index eeb1cd0f75a6..d4e5ef64e489 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c @@ -59,7 +59,7 @@ struct gpio_service *dal_gpio_service_create( uint32_t index_of_id; - service = dm_alloc(sizeof(struct gpio_service)); + service = kzalloc(sizeof(struct gpio_service), GFP_KERNEL); if (!service) { BREAK_TO_DEBUGGER(); @@ -98,7 +98,8 @@ struct gpio_service *dal_gpio_service_create( if (number_of_bits) { uint32_t index_of_uint = 0; - slot = dm_alloc(number_of_uints * sizeof(uint32_t)); + slot = kzalloc(number_of_uints * sizeof(uint32_t), + GFP_KERNEL); if (!slot) { BREAK_TO_DEBUGGER(); @@ -130,11 +131,11 @@ failure_2: slot = service->busyness[index_of_id]; if (slot) - dm_free(slot); + kfree(slot); }; failure_1: - dm_free(service); + kfree(service); return NULL; } @@ -171,13 +172,13 @@ void dal_gpio_service_destroy( uint32_t *slot = (*ptr)->busyness[index_of_id]; if (slot) - dm_free(slot); + kfree(slot); ++index_of_id; } while (index_of_id < GPIO_ID_COUNT); } - dm_free(*ptr); + kfree(*ptr); *ptr = NULL; } @@ -399,7 +400,7 @@ void dal_gpio_destroy_irq( dal_gpio_close(*irq); dal_gpio_destroy(irq); - dm_free(*irq); + kfree(*irq); *irq = NULL; } @@ -417,7 +418,7 @@ struct ddc *dal_gpio_create_ddc( if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) return NULL; - ddc = dm_alloc(sizeof(struct ddc)); + ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL); if (!ddc) { BREAK_TO_DEBUGGER(); @@ -450,7 +451,7 @@ failure_2: dal_gpio_destroy(&ddc->pin_data); failure_1: - dm_free(ddc); + kfree(ddc); return NULL; } @@ -466,7 +467,7 @@ void dal_gpio_destroy_ddc( dal_ddc_close(*ddc); dal_gpio_destroy(&(*ddc)->pin_data); dal_gpio_destroy(&(*ddc)->pin_clock); - dm_free(*ddc); + kfree(*ddc); *ddc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c index 47e0f8f24a86..7b6efa4f2efd 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c @@ -55,7 +55,7 @@ static void destroy( destruct(pin); - dm_free(pin); + kfree(pin); *ptr = NULL; } @@ -225,7 +225,7 @@ struct hw_gpio_pin *dal_hw_ddc_create( enum gpio_id id, uint32_t en) { - struct hw_ddc *pin = dm_alloc(sizeof(struct hw_ddc)); + struct hw_ddc *pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); if (!pin) { ASSERT_CRITICAL(false); @@ -237,7 +237,7 @@ struct hw_gpio_pin *dal_hw_ddc_create( ASSERT_CRITICAL(false); - dm_free(pin); + kfree(pin); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index f7d049c0e62a..87b580fa4bc9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -101,7 +101,7 @@ void dal_hw_factory_destroy( return; } - dm_free(*factory); + kfree(*factory); *factory = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c index 9634e8841d90..0c255c02045b 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c @@ -72,7 +72,7 @@ static void destroy( destruct(hpd); - dm_free(hpd); + kfree(hpd); *ptr = NULL; } @@ -157,7 +157,7 @@ struct hw_gpio_pin *dal_hw_hpd_create( enum gpio_id id, uint32_t en) { - struct hw_hpd *hpd = dm_alloc(sizeof(struct hw_hpd)); + struct hw_hpd *hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL); if (!hpd) { ASSERT_CRITICAL(false); @@ -169,7 +169,7 @@ struct hw_gpio_pin *dal_hw_hpd_create( ASSERT_CRITICAL(false); - dm_free(hpd); + kfree(hpd); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c index 0712cafb4c42..c45a2ee8c336 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c @@ -88,7 +88,7 @@ struct i2caux *dal_i2caux_dce100_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -106,7 +106,7 @@ struct i2caux *dal_i2caux_dce100_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c index d3eaf8977a60..4b673b48bf42 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c @@ -87,7 +87,7 @@ static void destroy( destruct(engine); - dm_free(engine); + kfree(engine); *aux_engine = NULL; } @@ -464,7 +464,7 @@ struct aux_engine *dal_aux_engine_dce110_create( return NULL; } - engine = dm_alloc(sizeof(*engine)); + engine = kzalloc(sizeof(*engine), GFP_KERNEL); if (!engine) { ASSERT_CRITICAL(false); @@ -476,7 +476,7 @@ struct aux_engine *dal_aux_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c index 80d06ad78e07..aab77a81008a 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c @@ -469,7 +469,7 @@ static void destroy( dal_i2c_hw_engine_destruct(&engine_dce110->base); - dm_free(engine_dce110); + kfree(engine_dce110); *i2c_engine = NULL; } @@ -559,7 +559,8 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create( return NULL; } - engine_dce10 = dm_alloc(sizeof(struct i2c_hw_engine_dce110)); + engine_dce10 = kzalloc(sizeof(struct i2c_hw_engine_dce110), + GFP_KERNEL); if (!engine_dce10) { ASSERT_CRITICAL(false); @@ -571,7 +572,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine_dce10); + kfree(engine_dce10); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c index 996813d9165f..bf2c4b240b78 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c @@ -88,7 +88,7 @@ static void destroy( destruct(sw_engine); - dm_free(sw_engine); + kfree(sw_engine); *engine = NULL; } @@ -153,7 +153,8 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create( return NULL; } - engine_dce110 = dm_alloc(sizeof(struct i2c_sw_engine_dce110)); + engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110), + GFP_KERNEL); if (!engine_dce110) { ASSERT_CRITICAL(false); @@ -165,7 +166,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine_dce110); + kfree(engine_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c index 1c00ed0010d9..ae9adb389319 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c @@ -68,7 +68,7 @@ static void destroy( destruct(i2caux_dce110); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); *i2c_engine = NULL; } @@ -299,7 +299,7 @@ struct i2caux *dal_i2caux_dce110_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -317,7 +317,7 @@ struct i2caux *dal_i2caux_dce110_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c index d74f3f15d600..715ba4390957 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c @@ -122,7 +122,7 @@ struct i2caux *dal_i2caux_dce112_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -134,7 +134,7 @@ struct i2caux *dal_i2caux_dce112_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 91198295f1a4..d52827ae3f1a 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -101,7 +101,7 @@ struct i2caux *dal_i2caux_dce120_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -119,7 +119,7 @@ struct i2caux *dal_i2caux_dce120_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c index 423c38ac880c..d41e37c94214 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c @@ -190,7 +190,7 @@ static void destroy( destruct(engine); - dm_free(engine); + kfree(engine); *i2c_engine = NULL; } @@ -867,7 +867,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_hw_engine_dce80)); + engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -879,7 +879,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c index 804a3266c578..6be77bc931c6 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c @@ -103,7 +103,7 @@ static void destroy( destruct(sw_engine); - dm_free(sw_engine); + kfree(sw_engine); *engine = NULL; } @@ -165,7 +165,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_sw_engine_dce80)); + engine = kzalloc(sizeof(struct i2c_sw_engine_dce80), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -177,7 +177,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c index 5e71450c44e0..d3c157e5eccd 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c @@ -101,7 +101,7 @@ static void destroy( destruct(i2caux_dce80); - dm_free(i2caux_dce80); + kfree(i2caux_dce80); *i2c_engine = NULL; } @@ -277,7 +277,7 @@ struct i2caux *dal_i2caux_dce80_create( struct dc_context *ctx) { struct i2caux_dce80 *i2caux_dce80 = - dm_alloc(sizeof(struct i2caux_dce80)); + kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL); if (!i2caux_dce80) { BREAK_TO_DEBUGGER(); @@ -289,7 +289,7 @@ struct i2caux *dal_i2caux_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(i2caux_dce80); + kfree(i2caux_dce80); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index 9f17d2e4376b..f8659f1c5f9d 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -101,7 +101,7 @@ struct i2caux *dal_i2caux_dcn10_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -119,7 +119,7 @@ struct i2caux *dal_i2caux_dcn10_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c index 029bf735036c..1fdb3252920b 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c @@ -59,7 +59,7 @@ static void destroy( { destruct(*i2c_engine); - dm_free(*i2c_engine); + kfree(*i2c_engine); *i2c_engine = NULL; } @@ -90,7 +90,8 @@ static bool construct( struct i2caux *dal_i2caux_diag_fpga_create( struct dc_context *ctx) { - struct i2caux *i2caux = dm_alloc(sizeof(struct i2caux)); + struct i2caux *i2caux = kzalloc(sizeof(struct i2caux), + GFP_KERNEL); if (!i2caux) { ASSERT_CRITICAL(false); @@ -102,7 +103,7 @@ struct i2caux *dal_i2caux_diag_fpga_create( ASSERT_CRITICAL(false); - dm_free(i2caux); + kfree(i2caux); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c index 95bc4457d44b..9d0077ade12c 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c @@ -541,7 +541,7 @@ static void destroy( { dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr)); - dm_free(*ptr); + kfree(*ptr); *ptr = NULL; } @@ -592,7 +592,7 @@ struct i2c_engine *dal_i2c_sw_engine_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_sw_engine)); + engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -604,7 +604,7 @@ struct i2c_engine *dal_i2c_sw_engine_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 7cce28489dba..a6c3a7229def 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -422,7 +422,8 @@ bool construct( struct irq_service *dal_irq_service_dce110_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -430,6 +431,6 @@ struct irq_service *dal_irq_service_dce110_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 3871633ac635..61d7c286802a 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -281,7 +281,8 @@ static bool construct( struct irq_service *dal_irq_service_dce120_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -289,6 +290,6 @@ struct irq_service *dal_irq_service_dce120_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index f458ef8e4c57..d6e1fb665d90 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -293,7 +293,8 @@ static bool construct( struct irq_service *dal_irq_service_dce80_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -301,7 +302,7 @@ struct irq_service *dal_irq_service_dce80_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index be59f0a654e2..f6e861162a6e 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -348,7 +348,8 @@ static bool construct( struct irq_service *dal_irq_service_dcn10_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -356,6 +357,6 @@ struct irq_service *dal_irq_service_dcn10_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index 0a1fae4ef83a..ce20622c7c89 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -66,7 +66,7 @@ void dal_irq_service_destroy(struct irq_service **irq_service) return; } - dm_free(*irq_service); + kfree(*irq_service); *irq_service = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 57b5a3babdf8..db513abd735a 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -87,7 +87,7 @@ static void virtual_link_encoder_connect_dig_be_to_fe( static void virtual_link_encoder_destroy(struct link_encoder **enc) { - dm_free(*enc); + kfree(*enc); *enc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 7fe6085e6e37..3dc1733eea20 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -121,7 +121,7 @@ bool virtual_stream_encoder_construct( struct stream_encoder *virtual_stream_encoder_create( struct dc_context *ctx, struct dc_bios *bp) { - struct stream_encoder *enc = dm_alloc(sizeof(*enc)); + struct stream_encoder *enc = kzalloc(sizeof(*enc), GFP_KERNEL); if (!enc) return NULL; @@ -130,7 +130,7 @@ struct stream_encoder *virtual_stream_encoder_create( return enc; BREAK_TO_DEBUGGER(); - dm_free(enc); + kfree(enc); return NULL; } diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 52350d0e68d0..4d7db4aa28e0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -143,7 +143,7 @@ static bool check_dc_support(const struct dc *dc) struct mod_freesync *mod_freesync_create(struct dc *dc) { struct core_freesync *core_freesync = - dm_alloc(sizeof(struct core_freesync)); + kzalloc(sizeof(struct core_freesync), GFP_KERNEL); struct persistent_data_flag flag; @@ -153,8 +153,8 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) if (core_freesync == NULL) goto fail_alloc_context; - core_freesync->map = dm_alloc(sizeof(struct freesync_entity) * - MOD_FREESYNC_MAX_CONCURRENT_STREAMS); + core_freesync->map = kzalloc(sizeof(struct freesync_entity) * MOD_FREESYNC_MAX_CONCURRENT_STREAMS, + GFP_KERNEL); if (core_freesync->map == NULL) goto fail_alloc_map; @@ -197,10 +197,10 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) return &core_freesync->public; fail_construct: - dm_free(core_freesync->map); + kfree(core_freesync->map); fail_alloc_map: - dm_free(core_freesync); + kfree(core_freesync); fail_alloc_context: return NULL; @@ -217,9 +217,9 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) if (core_freesync->map[i].stream) dc_stream_release(core_freesync->map[i].stream); - dm_free(core_freesync->map); + kfree(core_freesync->map); - dm_free(core_freesync); + kfree(core_freesync); } } -- cgit v1.2.3-59-g8ed1b From 8c0dc2b9891155afc3b1fbf6b04839819ec9099b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 28 Sep 2017 10:22:48 +1000 Subject: amdgpu/dc: move filter taps to being static const data (v2) This just adds two accessor methods, and moves all the data to static const. v2: fix dcn build. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce/dce_scl_filters.c | 78 ++++++++++++---------- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 2 +- .../drm/amd/display/dc/dce110/dce110_transform_v.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 4 +- 5 files changed, 49 insertions(+), 39 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c index 2cfdb835f1a8..6243450b41b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c @@ -25,7 +25,7 @@ #include "transform.h" -const uint16_t filter_2tap_16p[18] = { +static const uint16_t filter_2tap_16p[18] = { 4096, 0, 3840, 256, 3584, 512, @@ -37,7 +37,7 @@ const uint16_t filter_2tap_16p[18] = { 2048, 2048 }; -const uint16_t filter_3tap_16p_upscale[27] = { +static const uint16_t filter_3tap_16p_upscale[27] = { 2048, 2048, 0, 1708, 2424, 16348, 1372, 2796, 16308, @@ -49,7 +49,7 @@ const uint16_t filter_3tap_16p_upscale[27] = { 0, 4096, 0 }; -const uint16_t filter_3tap_16p_117[27] = { +static const uint16_t filter_3tap_16p_117[27] = { 2048, 2048, 0, 1824, 2276, 16376, 1600, 2496, 16380, @@ -61,7 +61,7 @@ const uint16_t filter_3tap_16p_117[27] = { 428, 3236, 428 }; -const uint16_t filter_3tap_16p_150[27] = { +static const uint16_t filter_3tap_16p_150[27] = { 2048, 2048, 0, 1872, 2184, 36, 1692, 2308, 88, @@ -73,7 +73,7 @@ const uint16_t filter_3tap_16p_150[27] = { 696, 2696, 696 }; -const uint16_t filter_3tap_16p_183[27] = { +static const uint16_t filter_3tap_16p_183[27] = { 2048, 2048, 0, 1892, 2104, 92, 1744, 2152, 196, @@ -85,7 +85,7 @@ const uint16_t filter_3tap_16p_183[27] = { 900, 2292, 900 }; -const uint16_t filter_4tap_16p_upscale[36] = { +static const uint16_t filter_4tap_16p_upscale[36] = { 0, 4096, 0, 0, 16240, 4056, 180, 16380, 16136, 3952, 404, 16364, @@ -97,7 +97,7 @@ const uint16_t filter_4tap_16p_upscale[36] = { 16128, 2304, 2304, 16128 }; -const uint16_t filter_4tap_16p_117[36] = { +static const uint16_t filter_4tap_16p_117[36] = { 428, 3236, 428, 0, 276, 3232, 604, 16364, 148, 3184, 800, 16340, @@ -109,7 +109,7 @@ const uint16_t filter_4tap_16p_117[36] = { 16212, 2216, 2216, 16212 }; -const uint16_t filter_4tap_16p_150[36] = { +static const uint16_t filter_4tap_16p_150[36] = { 696, 2700, 696, 0, 560, 2700, 848, 16364, 436, 2676, 1008, 16348, @@ -121,7 +121,7 @@ const uint16_t filter_4tap_16p_150[36] = { 16376, 2052, 2052, 16376 }; -const uint16_t filter_4tap_16p_183[36] = { +static const uint16_t filter_4tap_16p_183[36] = { 940, 2208, 940, 0, 832, 2200, 1052, 4, 728, 2180, 1164, 16, @@ -133,7 +133,7 @@ const uint16_t filter_4tap_16p_183[36] = { 232, 1812, 1812, 232 }; -const uint16_t filter_2tap_64p[66] = { +static const uint16_t filter_2tap_64p[66] = { 4096, 0, 4032, 64, 3968, 128, @@ -168,7 +168,7 @@ const uint16_t filter_2tap_64p[66] = { 2112, 1984, 2048, 2048 }; -const uint16_t filter_3tap_64p_upscale[99] = { +static const uint16_t filter_3tap_64p_upscale[99] = { 2048, 2048, 0, 1960, 2140, 16376, 1876, 2236, 16364, @@ -204,7 +204,7 @@ const uint16_t filter_3tap_64p_upscale[99] = { 0, 4096, 0 }; -const uint16_t filter_3tap_64p_117[99] = { +static const uint16_t filter_3tap_64p_117[99] = { 2048, 2048, 0, 1992, 2104, 16380, 1936, 2160, 16380, @@ -240,7 +240,7 @@ const uint16_t filter_3tap_64p_117[99] = { 428, 3236, 428 }; -const uint16_t filter_3tap_64p_150[99] = { +static const uint16_t filter_3tap_64p_150[99] = { 2048, 2048, 0, 2004, 2080, 8, 1960, 2116, 16, @@ -276,7 +276,7 @@ const uint16_t filter_3tap_64p_150[99] = { 696, 2696, 696 }; -const uint16_t filter_3tap_64p_183[99] = { +static const uint16_t filter_3tap_64p_183[99] = { 2048, 2048, 0, 2008, 2060, 20, 1968, 2076, 44, @@ -312,7 +312,7 @@ const uint16_t filter_3tap_64p_183[99] = { 900, 2292, 900 }; -const uint16_t filter_4tap_64p_upscale[132] = { +static const uint16_t filter_4tap_64p_upscale[132] = { 0, 4096, 0, 0, 16344, 4092, 40, 0, 16308, 4084, 84, 16380, @@ -347,7 +347,7 @@ const uint16_t filter_4tap_64p_upscale[132] = { 16116, 2388, 2216, 16140, 16128, 2304, 2304, 16128 }; -const uint16_t filter_4tap_64p_117[132] = { +static const uint16_t filter_4tap_64p_117[132] = { 420, 3248, 420, 0, 380, 3248, 464, 16380, 344, 3248, 508, 16372, @@ -382,7 +382,7 @@ const uint16_t filter_4tap_64p_117[132] = { 16212, 2276, 2160, 16212, 16212, 2220, 2220, 16212 }; -const uint16_t filter_4tap_64p_150[132] = { +static const uint16_t filter_4tap_64p_150[132] = { 696, 2700, 696, 0, 660, 2704, 732, 16380, 628, 2704, 768, 16376, @@ -417,7 +417,7 @@ const uint16_t filter_4tap_64p_150[132] = { 4, 2112, 1996, 16364, 16380, 2072, 2036, 16372 }; -const uint16_t filter_4tap_64p_183[132] = { +static const uint16_t filter_4tap_64p_183[132] = { 944, 2204, 944, 0, 916, 2204, 972, 0, 888, 2200, 996, 0, @@ -452,7 +452,7 @@ const uint16_t filter_4tap_64p_183[132] = { 252, 1832, 1784, 220, 236, 1808, 1808, 236 }; -const uint16_t filter_5tap_64p_upscale[165] = { +static const uint16_t filter_5tap_64p_upscale[165] = { 15936, 2496, 2496, 15936, 0, 15948, 2404, 2580, 15924, 0, 15960, 2312, 2664, 15912, 4, @@ -487,7 +487,7 @@ const uint16_t filter_5tap_64p_upscale[165] = { 16376, 48, 4092, 16336, 4, 0, 0, 4096, 0, 0 }; -const uint16_t filter_5tap_64p_117[165] = { +static const uint16_t filter_5tap_64p_117[165] = { 16056, 2372, 2372, 16056, 0, 16052, 2312, 2432, 16060, 0, 16052, 2252, 2488, 16064, 0, @@ -522,7 +522,7 @@ const uint16_t filter_5tap_64p_117[165] = { 16248, 504, 3428, 408, 16268, 16256, 456, 3428, 456, 16256 }; -const uint16_t filter_5tap_64p_150[165] = { +static const uint16_t filter_5tap_64p_150[165] = { 16368, 2064, 2064, 16368, 0, 16352, 2028, 2100, 16380, 16380, 16340, 1996, 2132, 12, 16376, @@ -557,7 +557,7 @@ const uint16_t filter_5tap_64p_150[165] = { 16248, 860, 2708, 788, 16252, 16248, 824, 2708, 824, 16248 }; -const uint16_t filter_5tap_64p_183[165] = { +static const uint16_t filter_5tap_64p_183[165] = { 228, 1816, 1816, 228, 0, 216, 1792, 1836, 248, 16380, 200, 1772, 1860, 264, 16376, @@ -592,7 +592,7 @@ const uint16_t filter_5tap_64p_183[165] = { 16340, 1000, 2232, 944, 16336, 16340, 972, 2232, 972, 16340 }; -const uint16_t filter_6tap_64p_upscale[198] = { +static const uint16_t filter_6tap_64p_upscale[198] = { 0, 0, 4092, 0, 0, 0, 12, 16332, 4092, 52, 16368, 0, 24, 16280, 4088, 108, 16356, 0, @@ -627,7 +627,7 @@ const uint16_t filter_6tap_64p_upscale[198] = { 104, 15816, 2588, 2416, 15840, 92, 100, 15828, 2504, 2504, 15828, 100 }; -const uint16_t filter_6tap_64p_117[198] = { +static const uint16_t filter_6tap_64p_117[198] = { 16168, 476, 3568, 476, 16168, 0, 16180, 428, 3564, 528, 16156, 0, 16192, 376, 3556, 584, 16144, 4, @@ -662,7 +662,7 @@ const uint16_t filter_6tap_64p_117[198] = { 40, 15956, 2496, 2376, 15944, 44, 40, 15952, 2436, 2436, 15952, 40 }; -const uint16_t filter_6tap_64p_150[198] = { +static const uint16_t filter_6tap_64p_150[198] = { 16148, 920, 2724, 920, 16148, 0, 16152, 880, 2724, 956, 16148, 0, 16152, 844, 2720, 996, 16144, 0, @@ -697,7 +697,7 @@ const uint16_t filter_6tap_64p_150[198] = { 16292, 8, 2172, 2108, 16356, 16304, 16300, 16372, 2140, 2140, 16372, 16300 }; -const uint16_t filter_6tap_64p_183[198] = { +static const uint16_t filter_6tap_64p_183[198] = { 16296, 1032, 2196, 1032, 16296, 0, 16292, 1004, 2200, 1060, 16304, 16380, 16288, 976, 2200, 1088, 16308, 16380, @@ -732,7 +732,7 @@ const uint16_t filter_6tap_64p_183[198] = { 16288, 296, 1880, 1840, 256, 16296, 16292, 276, 1860, 1860, 276, 16292 }; -const uint16_t filter_7tap_64p_upscale[231] = { +static const uint16_t filter_7tap_64p_upscale[231] = { 176, 15760, 2488, 2488, 15760, 176, 0, 172, 15772, 2404, 2572, 15752, 180, 16380, 168, 15784, 2324, 2656, 15740, 184, 16380, @@ -767,7 +767,7 @@ const uint16_t filter_7tap_64p_upscale[231] = { 0, 16364, 56, 4092, 16328, 16, 16380, 0, 0, 0, 4096, 0, 0, 0 }; -const uint16_t filter_7tap_64p_117[231] = { +static const uint16_t filter_7tap_64p_117[231] = { 92, 15868, 2464, 2464, 15868, 92, 0, 96, 15864, 2404, 2528, 15876, 88, 0, 100, 15860, 2344, 2584, 15884, 84, 0, @@ -802,7 +802,7 @@ const uint16_t filter_7tap_64p_117[231] = { 68, 16108, 504, 3572, 396, 16140, 60, 64, 16124, 452, 3576, 452, 16124, 64 }; -const uint16_t filter_7tap_64p_150[231] = { +static const uint16_t filter_7tap_64p_150[231] = { 16224, 16380, 2208, 2208, 16380, 16224, 0, 16232, 16360, 2172, 2236, 16, 16216, 0, 16236, 16340, 2140, 2268, 40, 16212, 0, @@ -837,7 +837,7 @@ const uint16_t filter_7tap_64p_150[231] = { 16380, 16076, 1020, 2740, 944, 16076, 0, 0, 16076, 984, 2740, 984, 16076, 0 }; -const uint16_t filter_7tap_64p_183[231] = { +static const uint16_t filter_7tap_64p_183[231] = { 16216, 324, 1884, 1884, 324, 16216, 0, 16220, 304, 1864, 1904, 344, 16216, 0, 16224, 284, 1844, 1924, 364, 16216, 0, @@ -872,7 +872,7 @@ const uint16_t filter_7tap_64p_183[231] = { 16316, 16284, 1132, 2216, 1076, 16268, 16324, 16320, 16276, 1104, 2216, 1104, 16276, 16320 }; -const uint16_t filter_8tap_64p_upscale[264] = { +static const uint16_t filter_8tap_64p_upscale[264] = { 0, 0, 0, 4096, 0, 0, 0, 0, 16376, 20, 16328, 4092, 56, 16364, 4, 0, 16372, 36, 16272, 4088, 116, 16340, 12, 0, @@ -907,7 +907,7 @@ const uint16_t filter_8tap_64p_upscale[264] = { 16328, 248, 15692, 2616, 2448, 15716, 240, 16332, 16332, 244, 15704, 2532, 2532, 15704, 244, 16332 }; -const uint16_t filter_8tap_64p_117[264] = { +static const uint16_t filter_8tap_64p_117[264] = { 116, 16100, 428, 3564, 428, 16100, 116, 0, 112, 16116, 376, 3564, 484, 16084, 120, 16380, 104, 16136, 324, 3560, 540, 16064, 124, 16380, @@ -942,7 +942,7 @@ const uint16_t filter_8tap_64p_117[264] = { 16372, 136, 15816, 2548, 2428, 15804, 148, 16368, 16372, 140, 15812, 2488, 2488, 15812, 140, 16372 }; -const uint16_t filter_8tap_64p_150[264] = { +static const uint16_t filter_8tap_64p_150[264] = { 16380, 16020, 1032, 2756, 1032, 16020, 16380, 0, 0, 16020, 992, 2756, 1068, 16024, 16376, 0, 4, 16020, 952, 2752, 1108, 16024, 16372, 0, @@ -977,7 +977,7 @@ const uint16_t filter_8tap_64p_150[264] = { 44, 16160, 24, 2244, 2180, 16364, 16176, 40, 44, 16168, 4, 2212, 2212, 4, 16168, 44 }; -const uint16_t filter_8tap_64p_183[264] = { +static const uint16_t filter_8tap_64p_183[264] = { 16264, 16264, 1164, 2244, 1164, 16264, 16264, 0, 16268, 16256, 1136, 2240, 1188, 16272, 16260, 0, 16272, 16248, 1108, 2240, 1216, 16280, 16256, 0, @@ -1107,3 +1107,13 @@ const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio) else return filter_8tap_64p_183; } + +const uint16_t *get_filter_2tap_16p(void) +{ + return filter_2tap_16p; +} + +const uint16_t *get_filter_2tap_64p(void) +{ + return filter_2tap_64p; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 0e366021cf16..a8f60d7531be 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -306,7 +306,7 @@ static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio) else if (taps == 3) return get_filter_3tap_16p(ratio); else if (taps == 2) - return filter_2tap_16p; + return get_filter_2tap_16p(); else if (taps == 1) return NULL; else { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index c84823a40f61..47390dc58306 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -489,7 +489,7 @@ static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) if (taps == 4) return get_filter_4tap_64p(ratio); else if (taps == 2) - return filter_2tap_64p; + return get_filter_2tap_64p(); else if (taps == 1) return NULL; else { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index b62cb38f523c..82b8887d4973 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -240,7 +240,7 @@ static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) else if (taps == 3) return get_filter_3tap_64p(ratio); else if (taps == 2) - return filter_2tap_64p; + return get_filter_2tap_64p(); else if (taps == 1) return NULL; else { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 32947450e702..9d4a3a0098a9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -240,8 +240,8 @@ struct transform_funcs { }; -extern const uint16_t filter_2tap_16p[18]; -extern const uint16_t filter_2tap_64p[66]; +const uint16_t *get_filter_2tap_16p(void); +const uint16_t *get_filter_2tap_64p(void); const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio); const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio); const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio); -- cgit v1.2.3-59-g8ed1b From ca19d1a68b7e0f1d0717bd3f2d9d75cb3c568ddb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 13:15:55 +1000 Subject: amdgpu/dc: make timing generator constructor return void. This can't fail as is. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 9 ++------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 8 ++------ drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 7 +------ drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h | 2 +- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 8 ++------ 5 files changed, 8 insertions(+), 26 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 9a75bde32611..6765162a0d78 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -375,13 +375,8 @@ static struct timing_generator *dce100_timing_generator_create( if (!tg110) return NULL; - if (dce110_timing_generator_construct(tg110, ctx, instance, - offsets)) - return &tg110->base; - - BREAK_TO_DEBUGGER(); - kfree(tg110); - return NULL; + dce110_timing_generator_construct(tg110, ctx, instance, offsets); + return &tg110->base; } static struct stream_encoder *dce100_stream_encoder_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 787e20e15221..3d91f2a49d1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -410,12 +410,8 @@ static struct timing_generator *dce110_timing_generator_create( if (!tg110) return NULL; - if (dce110_timing_generator_construct(tg110, ctx, instance, offsets)) - return &tg110->base; - - BREAK_TO_DEBUGGER(); - kfree(tg110); - return NULL; + dce110_timing_generator_construct(tg110, ctx, instance, offsets); + return &tg110->base; } static struct stream_encoder *dce110_stream_encoder_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 7f93d6d83cfd..bcd544d85621 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1941,15 +1941,12 @@ static const struct timing_generator_funcs dce110_tg_funcs = { .arm_vert_intr = dce110_arm_vert_intr, }; -bool dce110_timing_generator_construct( +void dce110_timing_generator_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx, uint32_t instance, const struct dce110_timing_generator_offsets *offsets) { - if (!tg110) - return false; - tg110->controller_id = CONTROLLER_ID_D0 + instance; tg110->base.inst = instance; @@ -1966,6 +1963,4 @@ bool dce110_timing_generator_construct( tg110->min_h_blank = 56; tg110->min_h_front_porch = 4; tg110->min_h_back_porch = 4; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index a5d63c626ada..bd8d0ab668b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -118,7 +118,7 @@ struct dce110_timing_generator { #define DCE110TG_FROM_TG(tg)\ container_of(tg, struct dce110_timing_generator, base) -bool dce110_timing_generator_construct( +void dce110_timing_generator_construct( struct dce110_timing_generator *tg, struct dc_context *ctx, uint32_t instance, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 4e2ed3429a90..a06a68521c59 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -415,12 +415,8 @@ static struct timing_generator *dce112_timing_generator_create( if (!tg110) return NULL; - if (dce110_timing_generator_construct(tg110, ctx, instance, offsets)) - return &tg110->base; - - BREAK_TO_DEBUGGER(); - kfree(tg110); - return NULL; + dce110_timing_generator_construct(tg110, ctx, instance, offsets); + return &tg110->base; } static struct stream_encoder *dce112_stream_encoder_create( -- cgit v1.2.3-59-g8ed1b From f29f918f2868ece27c8aff0edc84c7d7fbdc5598 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 13:15:56 +1000 Subject: amdgpu/dc: make stream encoder constructor return void. The checks weren't useful here really. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 9 +-------- drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 11 +++-------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 12 ++++-------- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 14 +++++--------- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 12 ++++-------- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 12 ++++-------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 12 ++++-------- 8 files changed, 26 insertions(+), 58 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 532c6e638943..b2add58ef889 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -1605,7 +1605,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = { }; -bool dce110_stream_encoder_construct( +void dce110_stream_encoder_construct( struct dce110_stream_encoder *enc110, struct dc_context *ctx, struct dc_bios *bp, @@ -1614,11 +1614,6 @@ bool dce110_stream_encoder_construct( const struct dce_stream_encoder_shift *se_shift, const struct dce_stream_encoder_mask *se_mask) { - if (!enc110) - return false; - if (!bp) - return false; - enc110->base.funcs = &dce110_str_enc_funcs; enc110->base.ctx = ctx; enc110->base.id = eng_id; @@ -1626,6 +1621,4 @@ bool dce110_stream_encoder_construct( enc110->regs = regs; enc110->se_shift = se_shift; enc110->se_mask = se_mask; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index ff8ca1246650..6c28229c76eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -697,7 +697,7 @@ struct dce110_stream_encoder { const struct dce_stream_encoder_mask *se_mask; }; -bool dce110_stream_encoder_construct( +void dce110_stream_encoder_construct( struct dce110_stream_encoder *enc110, struct dc_context *ctx, struct dc_bios *bp, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 6765162a0d78..75961338a8e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -389,14 +389,9 @@ static struct stream_encoder *dce100_stream_encoder_create( if (!enc110) return NULL; - if (dce110_stream_encoder_construct( - enc110, ctx, ctx->dc_bios, eng_id, - &stream_enc_regs[eng_id], &se_shift, &se_mask)) - return &enc110->base; - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); + return &enc110->base; } #define SRII(reg_name, block, id)\ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 3d91f2a49d1d..9faf2feabdf1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -424,14 +424,10 @@ static struct stream_encoder *dce110_stream_encoder_create( if (!enc110) return NULL; - if (dce110_stream_encoder_construct( - enc110, ctx, ctx->dc_bios, eng_id, - &stream_enc_regs[eng_id], &se_shift, &se_mask)) - return &enc110->base; - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc110->base; } #define SRII(reg_name, block, id)\ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index a06a68521c59..0011dd704af0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -428,15 +428,11 @@ static struct stream_encoder *dce112_stream_encoder_create( if (!enc110) return NULL; - - if (dce110_stream_encoder_construct( - enc110, ctx, ctx->dc_bios, eng_id, - &stream_enc_regs[eng_id], &se_shift, &se_mask)) - return &enc110->base; - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc110->base; } #define SRII(reg_name, block, id)\ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index a6f93a42c2ec..a63193913496 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -585,14 +585,10 @@ static struct stream_encoder *dce120_stream_encoder_create( if (!enc110) return NULL; - if (dce110_stream_encoder_construct( - enc110, ctx, ctx->dc_bios, eng_id, - &stream_enc_regs[eng_id], &se_shift, &se_mask)) - return &enc110->base; - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc110->base; } #define SRII(reg_name, block, id)\ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 170509a4a221..0b309acab6b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -441,14 +441,10 @@ static struct stream_encoder *dce80_stream_encoder_create( if (!enc110) return NULL; - if (dce110_stream_encoder_construct( - enc110, ctx, ctx->dc_bios, eng_id, - &stream_enc_regs[eng_id], &se_shift, &se_mask)) - return &enc110->base; - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc110->base; } #define SRII(reg_name, block, id)\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index e21ba8c2f8d4..5d6dd7f30253 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -627,14 +627,10 @@ static struct stream_encoder *dcn10_stream_encoder_create( if (!enc110) return NULL; - if (dce110_stream_encoder_construct( - enc110, ctx, ctx->dc_bios, eng_id, - &stream_enc_regs[eng_id], &se_shift, &se_mask)) - return &enc110->base; - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc110->base; } static const struct dce_hwseq_registers hwseq_reg = { -- cgit v1.2.3-59-g8ed1b From c60ae11201caff8b0c5c23e4349bf42388e3828b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 13:15:57 +1000 Subject: amdgpu/dc: make link encoder construct void. This only ever returned true. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 4 +--- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../gpu/drm/amd/display/dc/dce100/dce100_resource.c | 21 +++++++-------------- .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 21 +++++++-------------- .../gpu/drm/amd/display/dc/dce112/dce112_resource.c | 21 +++++++-------------- .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 20 +++++++------------- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 21 +++++++-------------- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 20 +++++++------------- 8 files changed, 44 insertions(+), 86 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 2ce730de0dc3..37aeddfb7431 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -914,7 +914,7 @@ bool dce110_link_encoder_validate_dp_output( return false; } -bool dce110_link_encoder_construct( +void dce110_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, const struct encoder_feature_support *enc_features, @@ -1013,8 +1013,6 @@ bool dce110_link_encoder_construct( bp_cap_info.DP_HBR3_EN; enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; } - - return true; } bool dce110_link_encoder_validate_output_with_stream( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 5960fb933f1f..be0a45bdc5e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -168,7 +168,7 @@ struct dce110_link_encoder { }; -bool dce110_link_encoder_construct( +void dce110_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, const struct encoder_feature_support *enc_features, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 75961338a8e4..0084645837ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -528,20 +528,13 @@ struct link_encoder *dce100_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( - enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[enc_init_data->transmitter], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source])) { - - return &enc110->base; - } - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source]); + return &enc110->base; } struct output_pixel_processor *dce100_opp_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 9faf2feabdf1..2c24f2b882fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -567,20 +567,13 @@ static struct link_encoder *dce110_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( - enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[enc_init_data->transmitter], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source])) { - - return &enc110->base; - } - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source]); + return &enc110->base; } static struct output_pixel_processor *dce110_opp_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 0011dd704af0..7aac8fdb3030 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -552,20 +552,13 @@ struct link_encoder *dce112_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( - enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[enc_init_data->transmitter], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source])) { - - return &enc110->base; - } - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source]); + return &enc110->base; } static struct input_pixel_processor *dce112_ipp_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index a63193913496..7de99c454f4b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -544,20 +544,14 @@ static struct link_encoder *dce120_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( - enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[enc_init_data->transmitter], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source])) { - - return &enc110->base; - } + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source]); - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + return &enc110->base; } static struct input_pixel_processor *dce120_ipp_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 0b309acab6b1..3603ae93cd72 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -567,20 +567,13 @@ struct link_encoder *dce80_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( - enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[enc_init_data->transmitter], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source])) { - - return &enc110->base; - } - - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source]); + return &enc110->base; } struct clock_source *dce80_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 5d6dd7f30253..c2df57b5e921 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -563,20 +563,14 @@ struct link_encoder *dcn10_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( - enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[enc_init_data->transmitter], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source])) { - - return &enc110->base; - } + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source]); - BREAK_TO_DEBUGGER(); - kfree(enc110); - return NULL; + return &enc110->base; } struct clock_source *dcn10_clock_source_create( -- cgit v1.2.3-59-g8ed1b From 9cf29399f615fc13732f3c8ba3f5ff47e2ca256d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 13:15:58 +1000 Subject: amdgpu/dc: make opp construct void. This doesn't return anything except true. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 2 +- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 10 +++------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 10 +++------- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 10 +++------- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 10 +++------- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 10 +++------- 7 files changed, 17 insertions(+), 39 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index c0736aeabd85..3931412ab6d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -540,7 +540,7 @@ static const struct opp_funcs funcs = { .opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction }; -bool dce110_opp_construct(struct dce110_opp *opp110, +void dce110_opp_construct(struct dce110_opp *opp110, struct dc_context *ctx, uint32_t inst, const struct dce_opp_registers *regs, @@ -556,8 +556,6 @@ bool dce110_opp_construct(struct dce110_opp *opp110, opp110->regs = regs; opp110->opp_shift = opp_shift; opp110->opp_mask = opp_mask; - - return true; } void dce110_opp_destroy(struct output_pixel_processor **opp) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index 0874c22b8b02..2ab0147cbd9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -272,7 +272,7 @@ struct dce110_opp { const struct dce_opp_mask *opp_mask; }; -bool dce110_opp_construct(struct dce110_opp *opp110, +void dce110_opp_construct(struct dce110_opp *opp110, struct dc_context *ctx, uint32_t inst, const struct dce_opp_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 0084645837ec..729d82eb6500 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -547,13 +547,9 @@ struct output_pixel_processor *dce100_opp_create( if (!opp) return NULL; - if (dce110_opp_construct(opp, - ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - kfree(opp); - return NULL; + dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; } struct clock_source *dce100_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 2c24f2b882fe..8e3f365177b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -586,13 +586,9 @@ static struct output_pixel_processor *dce110_opp_create( if (!opp) return NULL; - if (dce110_opp_construct(opp, - ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - kfree(opp); - return NULL; + dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; } struct clock_source *dce110_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 7aac8fdb3030..3cb18cecb800 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -586,13 +586,9 @@ struct output_pixel_processor *dce112_opp_create( if (!opp) return NULL; - if (dce110_opp_construct(opp, - ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - kfree(opp); - return NULL; + dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; } struct clock_source *dce112_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 7de99c454f4b..ea234376c0e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -356,13 +356,9 @@ struct output_pixel_processor *dce120_opp_create( if (!opp) return NULL; - if (dce110_opp_construct(opp, - ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - kfree(opp); - return NULL; + dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; } static const struct bios_registers bios_regs = { diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 3603ae93cd72..71f265b6b670 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -422,13 +422,9 @@ static struct output_pixel_processor *dce80_opp_create( if (!opp) return NULL; - if (dce110_opp_construct(opp, - ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - kfree(opp); - return NULL; + dce110_opp_construct(opp, + ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; } static struct stream_encoder *dce80_stream_encoder_create( -- cgit v1.2.3-59-g8ed1b From 5fb005c4583749f54d5bab6622dbed1d2d56c268 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 13:15:59 +1000 Subject: amdgpu/dc: make dce transform constructor void This never returns anything but true. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 +- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 11 +++-------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 10 +++------- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 13 ++++--------- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 13 ++++--------- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 13 ++++--------- 7 files changed, 20 insertions(+), 46 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index a8f60d7531be..c40d2e9e5f7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1437,7 +1437,7 @@ static const struct transform_funcs dce_transform_funcs = { /* Constructor, Destructor */ /*****************************************/ -bool dce_transform_construct( +void dce_transform_construct( struct dce_transform *xfm_dce, struct dc_context *ctx, uint32_t inst, @@ -1462,6 +1462,4 @@ bool dce_transform_construct( xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/ - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index 805bb9c4e188..e1f1e5129f86 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -481,7 +481,7 @@ struct dce_transform { bool prescaler_on; }; -bool dce_transform_construct(struct dce_transform *xfm_dce, +void dce_transform_construct(struct dce_transform *xfm_dce, struct dc_context *ctx, uint32_t inst, const struct dce_transform_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 729d82eb6500..1caf2983dda5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -486,14 +486,9 @@ static struct transform *dce100_transform_create( if (!transform) return NULL; - if (dce_transform_construct(transform, ctx, inst, - &xfm_regs[inst], &xfm_shift, &xfm_mask)) { - return &transform->base; - } - - BREAK_TO_DEBUGGER(); - kfree(transform); - return NULL; + dce_transform_construct(transform, ctx, inst, + &xfm_regs[inst], &xfm_shift, &xfm_mask); + return &transform->base; } static struct input_pixel_processor *dce100_ipp_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 8e3f365177b8..45c5facf79b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -526,13 +526,9 @@ static struct transform *dce110_transform_create( if (!transform) return NULL; - if (dce_transform_construct(transform, ctx, inst, - &xfm_regs[inst], &xfm_shift, &xfm_mask)) - return &transform->base; - - BREAK_TO_DEBUGGER(); - kfree(transform); - return NULL; + dce_transform_construct(transform, ctx, inst, + &xfm_regs[inst], &xfm_shift, &xfm_mask); + return &transform->base; } static struct input_pixel_processor *dce110_ipp_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 3cb18cecb800..251e4a29d56f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -521,15 +521,10 @@ static struct transform *dce112_transform_create( if (!transform) return NULL; - if (dce_transform_construct(transform, ctx, inst, - &xfm_regs[inst], &xfm_shift, &xfm_mask)) { - transform->lb_memory_size = 0x1404; /*5124*/ - return &transform->base; - } - - BREAK_TO_DEBUGGER(); - kfree(transform); - return NULL; + dce_transform_construct(transform, ctx, inst, + &xfm_regs[inst], &xfm_shift, &xfm_mask); + transform->lb_memory_size = 0x1404; /*5124*/ + return &transform->base; } static const struct encoder_feature_support link_enc_feature = { diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index ea234376c0e2..13d75df71396 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -662,15 +662,10 @@ static struct transform *dce120_transform_create( if (!transform) return NULL; - if (dce_transform_construct(transform, ctx, inst, - &xfm_regs[inst], &xfm_shift, &xfm_mask)) { - transform->lb_memory_size = 0x1404; /*5124*/ - return &transform->base; - } - - BREAK_TO_DEBUGGER(); - kfree(transform); - return NULL; + dce_transform_construct(transform, ctx, inst, + &xfm_regs[inst], &xfm_shift, &xfm_mask); + transform->lb_memory_size = 0x1404; /*5124*/ + return &transform->base; } static void dce120_destroy_resource_pool(struct resource_pool **pool) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 71f265b6b670..db8afb6491cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -535,15 +535,10 @@ static struct transform *dce80_transform_create( if (!transform) return NULL; - if (dce_transform_construct(transform, ctx, inst, - &xfm_regs[inst], &xfm_shift, &xfm_mask)) { - transform->prescaler_on = false; - return &transform->base; - } - - BREAK_TO_DEBUGGER(); - kfree(transform); - return NULL; + dce_transform_construct(transform, ctx, inst, + &xfm_regs[inst], &xfm_shift, &xfm_mask); + transform->prescaler_on = false; + return &transform->base; } static const struct encoder_feature_support link_enc_feature = { -- cgit v1.2.3-59-g8ed1b From 4dec2aa9eb1386e592d76f380360360178c4af02 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 14:34:35 +1000 Subject: amdgpu/dc: make program_regamma_pwl return void The return value was unused. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +--- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +- 6 files changed, 6 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index c40d2e9e5f7c..ae32af31eff1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1375,7 +1375,7 @@ static void regamma_config_regions_and_segments( -bool dce110_opp_program_regamma_pwl( +void dce110_opp_program_regamma_pwl( struct transform *xfm, const struct pwl_params *params) { @@ -1386,8 +1386,6 @@ bool dce110_opp_program_regamma_pwl( /* Program PWL */ program_pwl(xfm_dce, params); - - return true; } void dce110_opp_power_on_regamma_lut( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index e1f1e5129f86..bfc94b4927b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -506,7 +506,7 @@ void dce110_opp_power_on_regamma_lut( struct transform *xfm, bool power_on); -bool dce110_opp_program_regamma_pwl( +void dce110_opp_program_regamma_pwl( struct transform *xfm, const struct pwl_params *params); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index c86105b8cfaf..e98ed3058ea2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -490,7 +490,7 @@ static void program_pwl(struct dce_transform *xfm_dce, } } -bool dce110_opp_program_regamma_pwl_v( +void dce110_opp_program_regamma_pwl_v( struct transform *xfm, const struct pwl_params *params) { @@ -512,8 +512,6 @@ bool dce110_opp_program_regamma_pwl_v( /* Power return to auto back */ power_on_lut(xfm, false, false, true); - - return true; } void dce110_opp_power_on_regamma_lut_v( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h index eeed3b9f90f7..b70780210aad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h @@ -43,7 +43,7 @@ void dce110_opp_v_set_csc_adjustment( const struct out_csc_color_matrix *tbl_entry); -bool dce110_opp_program_regamma_pwl_v( +void dce110_opp_program_regamma_pwl_v( struct transform *xfm, const struct pwl_params *params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index ac03b04f1ea5..8607ab2da610 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -183,7 +183,7 @@ void dpp_reset(struct transform *xfm_base) -static bool dcn10_dpp_cm_set_regamma_pwl( +static void dcn10_dpp_cm_set_regamma_pwl( struct transform *xfm_base, const struct pwl_params *params) { struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); @@ -198,8 +198,6 @@ static bool dcn10_dpp_cm_set_regamma_pwl( dcn10_dpp_cm_program_regamma_lut( xfm_base, params->rgb_resulted, params->hw_points_num); - - return true; } static void dcn10_dpp_cm_set_regamma_mode( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 9d4a3a0098a9..785d39706832 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -213,7 +213,7 @@ struct transform_funcs { struct transform *xfm, const struct pwl_params *params); - bool (*opp_program_regamma_pwl)( + void (*opp_program_regamma_pwl)( struct transform *xfm, const struct pwl_params *params); void (*opp_set_regamma_mode)( -- cgit v1.2.3-59-g8ed1b From c13b408b81f8a101501d78ca499afee98e0f0ab9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 14:34:39 +1000 Subject: amdgpu/dc: another round of dce/dcn construct cleanups. This removes any remaining pointless return codepaths from the DCE code. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce100/dce100_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce100/dce100_resource.c | 4 +--- .../drm/amd/display/dc/dce110/dce110_compressor.c | 11 +++-------- .../drm/amd/display/dc/dce110/dce110_compressor.h | 2 +- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 6 ++---- .../display/dc/dce110/dce110_timing_generator_v.c | 7 +------ .../display/dc/dce110/dce110_timing_generator_v.h | 2 +- .../drm/amd/display/dc/dce112/dce112_compressor.c | 11 +++-------- .../drm/amd/display/dc/dce112/dce112_compressor.h | 2 +- .../drm/amd/display/dc/dce112/dce112_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce112/dce112_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce112/dce112_resource.c | 3 +-- .../drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce120/dce120_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 8 ++------ .../amd/display/dc/dce120/dce120_timing_generator.c | 7 +------ .../amd/display/dc/dce120/dce120_timing_generator.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_compressor.c | 11 +++-------- .../gpu/drm/amd/display/dc/dce80/dce80_compressor.h | 2 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 9 +++------ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 4 +--- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 20 ++++++-------------- 32 files changed, 47 insertions(+), 108 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index 492ea6069eb4..e7a694835e3e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -142,13 +142,11 @@ void dce100_set_bandwidth( /**************************************************************************/ -bool dce100_hw_sequencer_construct(struct dc *dc) +void dce100_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.set_bandwidth = dce100_set_bandwidth; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index 770b5bb1ff40..cb5384ef46c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -31,7 +31,7 @@ struct dc; struct dc_state; -bool dce100_hw_sequencer_construct(struct dc *dc); +void dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 1caf2983dda5..0db987d504c0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -909,9 +909,7 @@ static bool construct( goto res_create_fail; /* Create hardware sequencer */ - if (!dce100_hw_sequencer_construct(dc)) - goto res_create_fail; - + dce100_hw_sequencer_construct(dc); return true; res_create_fail: diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 90770cb2ffcd..3872febb4f6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -393,12 +393,8 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx) if (!cp110) return NULL; - if (dce110_compressor_construct(cp110, ctx)) - return &cp110->base; - - BREAK_TO_DEBUGGER(); - kfree(cp110); - return NULL; + dce110_compressor_construct(cp110, ctx); + return &cp110->base; } void dce110_compressor_destroy(struct compressor **compressor) @@ -485,7 +481,7 @@ static const struct compressor_funcs dce110_compressor_funcs = { }; -bool dce110_compressor_construct(struct dce110_compressor *compressor, +void dce110_compressor_construct(struct dce110_compressor *compressor, struct dc_context *ctx) { @@ -522,6 +518,5 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, compressor->base.funcs = &dce110_compressor_funcs; #endif - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h index 460cb77b8d75..26c7335a1cbf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h @@ -42,7 +42,7 @@ struct dce110_compressor { struct compressor *dce110_compressor_create(struct dc_context *ctx); -bool dce110_compressor_construct(struct dce110_compressor *cp110, +void dce110_compressor_construct(struct dce110_compressor *cp110, struct dc_context *ctx); void dce110_compressor_destroy(struct compressor **cp); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5bbfc34d6f01..de154329b049 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2723,10 +2723,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { }; -bool dce110_hw_sequencer_construct(struct dc *dc) +void dce110_hw_sequencer_construct(struct dc *dc) { dc->hwss = dce110_funcs; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index baa20c1f17ad..db6c19cd15eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -33,7 +33,7 @@ struct dc; struct dc_state; struct dm_pp_display_configuration; -bool dce110_hw_sequencer_construct(struct dc *dc); +void dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 69d6a110dbc3..3545e43a4b77 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -44,13 +44,11 @@ static const struct opp_funcs funcs = { dce110_opp_program_bit_depth_reduction }; -bool dce110_opp_v_construct(struct dce110_opp *opp110, +void dce110_opp_v_construct(struct dce110_opp *opp110, struct dc_context *ctx) { opp110->base.funcs = &funcs; opp110->base.ctx = ctx; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h index 269c1a88d5bb..152af4c418cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -29,7 +29,7 @@ #include "opp.h" #include "core_types.h" -bool dce110_opp_v_construct(struct dce110_opp *opp110, +void dce110_opp_v_construct(struct dce110_opp *opp110, struct dc_context *ctx); /* underlay callbacks */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 45c5facf79b1..017a1fd1f659 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1041,8 +1041,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) (dce110_oppv == NULL)) return false; - if (!dce110_opp_v_construct(dce110_oppv, ctx)) - return false; + dce110_opp_v_construct(dce110_oppv, ctx); dce110_timing_generator_v_construct(dce110_tgv, ctx); dce110_mem_input_v_construct(dce110_miv, ctx); @@ -1292,8 +1291,7 @@ static bool construct( goto res_create_fail; /* Create hardware sequencer */ - if (!dce110_hw_sequencer_construct(dc)) - goto res_create_fail; + dce110_hw_sequencer_construct(dc); dc->caps.max_planes = pool->base.pipe_count; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 93ca6ae48cb9..07d9303d5477 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -668,13 +668,10 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = { dce110_timing_generator_v_enable_advanced_request }; -bool dce110_timing_generator_v_construct( +void dce110_timing_generator_v_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx) { - if (!tg110) - return false; - tg110->controller_id = CONTROLLER_ID_UNDERLAY0; tg110->base.funcs = &dce110_tg_v_funcs; @@ -688,6 +685,4 @@ bool dce110_timing_generator_v_construct( tg110->min_h_blank = 56; tg110->min_h_front_porch = 4; tg110->min_h_back_porch = 4; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h index 7e49ca8e26ad..d2623a5994e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h @@ -26,7 +26,7 @@ #ifndef __DC_TIMING_GENERATOR_V_DCE110_H__ #define __DC_TIMING_GENERATOR_V_DCE110_H__ -bool dce110_timing_generator_v_construct( +void dce110_timing_generator_v_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c index e75895baa132..69649928768c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c @@ -791,7 +791,7 @@ void dce112_compressor_set_fbc_invalidation_triggers( dm_write_reg(compressor->ctx, addr, value); } -bool dce112_compressor_construct(struct dce112_compressor *compressor, +void dce112_compressor_construct(struct dce112_compressor *compressor, struct dc_context *ctx) { struct dc_bios *bp = ctx->dc_bios; @@ -833,7 +833,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, compressor->base.embedded_panel_v_size = panel_info.lcd_timing.vertical_addressable; } - return true; } struct compressor *dce112_compressor_create(struct dc_context *ctx) @@ -844,12 +843,8 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx) if (!cp110) return NULL; - if (dce112_compressor_construct(cp110, ctx)) - return &cp110->base; - - BREAK_TO_DEBUGGER(); - kfree(cp110); - return NULL; + dce112_compressor_construct(cp110, ctx); + return &cp110->base; } void dce112_compressor_destroy(struct compressor **compressor) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h index 106506387270..f1227133f6df 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h @@ -42,7 +42,7 @@ struct dce112_compressor { struct compressor *dce112_compressor_create(struct dc_context *ctx); -bool dce112_compressor_construct(struct dce112_compressor *cp110, +void dce112_compressor_construct(struct dce112_compressor *cp110, struct dc_context *ctx); void dce112_compressor_destroy(struct compressor **cp); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c index 8816e09110e1..1e4a7c13f0ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c @@ -152,14 +152,12 @@ static bool dce112_enable_display_power_gating( return false; } -bool dce112_hw_sequencer_construct(struct dc *dc) +void dce112_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure */ dce110_hw_sequencer_construct(dc); dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h index 37bd60cc93f9..e646f4a37fa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h @@ -30,7 +30,7 @@ struct dc; -bool dce112_hw_sequencer_construct(struct dc *dc); +void dce112_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 251e4a29d56f..11902a2fdaa4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1256,8 +1256,7 @@ static bool construct( dc->caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ - if (!dce112_hw_sequencer_construct(dc)) - goto res_create_fail; + dce112_hw_sequencer_construct(dc); bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 56e3b124f19c..1a0b54d6034e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -245,7 +245,7 @@ static void dce120_update_dchub( -bool dce120_hw_sequencer_construct(struct dc *dc) +void dce120_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure @@ -253,7 +253,5 @@ bool dce120_hw_sequencer_construct(struct dc *dc) dce110_hw_sequencer_construct(dc); dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating; dc->hwss.update_dchub = dce120_update_dchub; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h index 6448a17c2fde..77a6b86d7606 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h @@ -30,7 +30,7 @@ struct dc; -bool dce120_hw_sequencer_construct(struct dc *dc); +void dce120_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 13d75df71396..3ed28a870e20 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -429,12 +429,8 @@ static struct timing_generator *dce120_timing_generator_create( if (!tg110) return NULL; - if (dce120_timing_generator_construct(tg110, ctx, instance, offsets)) - return &tg110->base; - - BREAK_TO_DEBUGGER(); - kfree(tg110); - return NULL; + dce120_timing_generator_construct(tg110, ctx, instance, offsets); + return &tg110->base; } static void dce120_transform_destroy(struct transform **xfm) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 791c9b084941..95d871be3a0b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -1143,15 +1143,12 @@ static const struct timing_generator_funcs dce120_tg_funcs = { }; -bool dce120_timing_generator_construct( +void dce120_timing_generator_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx, uint32_t instance, const struct dce110_timing_generator_offsets *offsets) { - if (!tg110) - return false; - tg110->controller_id = CONTROLLER_ID_D0 + instance; tg110->base.inst = instance; @@ -1175,6 +1172,4 @@ bool dce120_timing_generator_construct( tg110->min_h_sync_width = 8; tg110->min_v_sync_width = 1; tg110->min_v_blank = 3; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h index 243c0a3493da..d69871ec0dde 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h @@ -32,7 +32,7 @@ #include "dce110/dce110_timing_generator.h" -bool dce120_timing_generator_construct( +void dce120_timing_generator_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx, uint32_t instance, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c index cc1c0d390945..951f2caba9b3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c @@ -771,7 +771,7 @@ void dce80_compressor_set_fbc_invalidation_triggers( dm_write_reg(compressor->ctx, addr, value); } -bool dce80_compressor_construct(struct dce80_compressor *compressor, +void dce80_compressor_construct(struct dce80_compressor *compressor, struct dc_context *ctx) { struct dc_bios *bp = ctx->dc_bios; @@ -813,7 +813,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, compressor->base.embedded_panel_v_size = panel_info.lcd_timing.vertical_addressable; } - return true; } struct compressor *dce80_compressor_create(struct dc_context *ctx) @@ -824,12 +823,8 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx) if (!cp80) return NULL; - if (dce80_compressor_construct(cp80, ctx)) - return &cp80->base; - - BREAK_TO_DEBUGGER(); - kfree(cp80); - return NULL; + dce80_compressor_construct(cp80, ctx); + return &cp80->base; } void dce80_compressor_destroy(struct compressor **compressor) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h index 01290969ff92..cca58b044402 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h @@ -42,7 +42,7 @@ struct dce80_compressor { struct compressor *dce80_compressor_create(struct dc_context *ctx); -bool dce80_compressor_construct(struct dce80_compressor *cp80, +void dce80_compressor_construct(struct dce80_compressor *cp80, struct dc_context *ctx); void dce80_compressor_destroy(struct compressor **cp); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index 28fe3824441f..ccfcf1c0eeb3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -106,14 +106,12 @@ static bool dce80_enable_display_power_gating( return false; } -bool dce80_hw_sequencer_construct(struct dc *dc) +void dce80_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating; dc->hwss.pipe_control_lock = dce_pipe_control_lock; dc->hwss.set_bandwidth = dce100_set_bandwidth; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h index 9d6dd05bd596..7a1b31def66f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h @@ -30,7 +30,7 @@ struct dc; -bool dce80_hw_sequencer_construct(struct dc *dc); +void dce80_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5e00ca6a1292..c6571a908786 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -910,8 +910,7 @@ static bool dce80_construct( goto res_create_fail; /* Create hardware sequencer */ - if (!dce80_hw_sequencer_construct(dc)) - goto res_create_fail; + dce80_hw_sequencer_construct(dc); return true; @@ -1075,8 +1074,7 @@ static bool dce81_construct( goto res_create_fail; /* Create hardware sequencer */ - if (!dce80_hw_sequencer_construct(dc)) - goto res_create_fail; + dce80_hw_sequencer_construct(dc); return true; @@ -1236,8 +1234,7 @@ static bool dce83_construct( goto res_create_fail; /* Create hardware sequencer */ - if (!dce80_hw_sequencer_construct(dc)) - goto res_create_fail; + dce80_hw_sequencer_construct(dc); return true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 8607ab2da610..9d9604f05095 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -397,7 +397,7 @@ static const struct transform_funcs dcn10_dpp_funcs = { /* Constructor, Destructor */ /*****************************************/ -bool dcn10_dpp_construct( +void dcn10_dpp_construct( struct dcn10_dpp *xfm, struct dc_context *ctx, uint32_t inst, @@ -421,6 +421,4 @@ bool dcn10_dpp_construct( xfm->lb_bits_per_entry = LB_BITS_PER_ENTRY; xfm->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index afe9d8f629d6..a1f6b01a2eb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -1356,7 +1356,7 @@ void ippn10_cnv_setup ( void ippn10_full_bypass(struct transform *xfm_base); -bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, +void dcn10_dpp_construct(struct dcn10_dpp *xfm110, struct dc_context *ctx, uint32_t inst, const struct dcn_dpp_registers *tf_regs, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 9008cd03b139..c8088489c6a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -786,7 +786,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { /* Constructor, Destructor */ /*****************************************/ -bool dcn10_mem_input_construct( +void dcn10_mem_input_construct( struct dcn10_mem_input *mi, struct dc_context *ctx, uint32_t inst, @@ -802,7 +802,5 @@ bool dcn10_mem_input_construct( mi->base.inst = inst; mi->base.opp_id = 0xf; mi->base.mpcc_id = 0xf; - - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h index acee05155b5b..aefd3e7bd7eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h @@ -538,7 +538,7 @@ struct dcn10_mem_input { const struct dcn_mi_mask *mi_mask; }; -bool dcn10_mem_input_construct( +void dcn10_mem_input_construct( struct dcn10_mem_input *mi, struct dc_context *ctx, uint32_t inst, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index c2df57b5e921..fb3ef134ea12 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -462,13 +462,9 @@ static struct transform *dcn10_dpp_create( if (!dpp) return NULL; - if (dcn10_dpp_construct(dpp, ctx, inst, - &tf_regs[inst], &tf_shift, &tf_mask)) - return &dpp->base; - - BREAK_TO_DEBUGGER(); - kfree(dpp); - return NULL; + dcn10_dpp_construct(dpp, ctx, inst, + &tf_regs[inst], &tf_shift, &tf_mask); + return &dpp->base; } static struct input_pixel_processor *dcn10_ipp_create( @@ -771,13 +767,9 @@ static struct mem_input *dcn10_mem_input_create( if (!mem_inputn10) return NULL; - if (dcn10_mem_input_construct(mem_inputn10, ctx, inst, - &mi_regs[inst], &mi_shift, &mi_mask)) - return &mem_inputn10->base; - - BREAK_TO_DEBUGGER(); - kfree(mem_inputn10); - return NULL; + dcn10_mem_input_construct(mem_inputn10, ctx, inst, + &mi_regs[inst], &mi_shift, &mi_mask); + return &mem_inputn10->base; } static void get_pixel_clock_parameters( -- cgit v1.2.3-59-g8ed1b From 94de2bbdfa613165ff20a3e958775c8d01581946 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 14:34:40 +1000 Subject: amdgpu/dc: remove pointless return from build_pipe_hw_param This never returned anything else. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 6 +----- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 10 ++-------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h | 2 +- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 6 +----- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 6 +----- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 11 ++--------- 6 files changed, 8 insertions(+), 33 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 0db987d504c0..b1cf591b3408 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -631,16 +631,12 @@ static enum dc_status build_mapped_resource( struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); if (!pipe_ctx) return DC_ERROR_UNEXPECTED; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; + dce110_resource_build_pipe_hw_param(pipe_ctx); resource_build_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 017a1fd1f659..89036aff9021 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -724,7 +724,7 @@ static void get_pixel_clock_parameters( } } -enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) +void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( @@ -734,8 +734,6 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; - - return DC_OK; } static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) @@ -754,7 +752,6 @@ static enum dc_status build_mapped_resource( struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); if (!pipe_ctx) @@ -764,10 +761,7 @@ static enum dc_status build_mapped_resource( dc->res_pool->underlay_pipe_index)) return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; + dce110_resource_build_pipe_hw_param(pipe_ctx); /* TODO: validate audio ASIC caps, encoder */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h index 5bb692d037d9..e5f168c1f8c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -38,7 +38,7 @@ struct dce110_resource_pool { struct resource_pool base; }; -enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); +void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 11902a2fdaa4..663e0a047a4b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -704,16 +704,12 @@ static enum dc_status build_mapped_resource( struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); if (!pipe_ctx) return DC_ERROR_UNEXPECTED; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; + dce110_resource_build_pipe_hw_param(pipe_ctx); resource_build_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index c6571a908786..9c18efd3446f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -665,16 +665,12 @@ static enum dc_status build_mapped_resource( struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); if (!pipe_ctx) return DC_ERROR_UNEXPECTED; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; + dce110_resource_build_pipe_hw_param(pipe_ctx); resource_build_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index fb3ef134ea12..dc878f77837b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -805,7 +805,7 @@ static void build_clamping_params(struct dc_stream_state *stream) stream->clamping.pixel_encoding = stream->timing.pixel_encoding; } -static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) +static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); @@ -820,8 +820,6 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); build_clamping_params(pipe_ctx->stream); - - return DC_OK; } static enum dc_status build_mapped_resource( @@ -829,7 +827,6 @@ static enum dc_status build_mapped_resource( struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); /*TODO Seems unneeded anymore */ @@ -853,11 +850,7 @@ static enum dc_status build_mapped_resource( if (!pipe_ctx) return DC_ERROR_UNEXPECTED; - status = build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; - + build_pipe_hw_param(pipe_ctx); return DC_OK; } -- cgit v1.2.3-59-g8ed1b From bd42a6f45180b3bd2bfe260959f53344f2636e71 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Oct 2017 13:49:43 +1000 Subject: amdgpu/dc: drop dce110_types.h Doesn't appear to be used. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_types.h | 30 ---------------------- 1 file changed, 30 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h deleted file mode 100644 index 55f52382ddfb..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef _DCE110_TYPES_H_ -#define __DCE110_TYPES_H_ - -#define GAMMA_SEGMENTS_NUM 16 - -#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_DCE110_DCE110_TYPES_H_ */ -- cgit v1.2.3-59-g8ed1b From 2016b641f421ecb28c21e34063ac8bd43ca6cfdc Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Oct 2017 13:49:44 +1000 Subject: amdgpu/dc: drop hw_sequencer_types.h This isn't used or required. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../display/dc/dce110/dce110_timing_generator.h | 1 - .../display/dc/dce120/dce120_timing_generator.h | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 - .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 1 - .../drm/amd/display/include/hw_sequencer_types.h | 33 ---------------------- 5 files changed, 37 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/include/hw_sequencer_types.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index bd8d0ab668b7..82737dea6984 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -28,7 +28,6 @@ #include "timing_generator.h" #include "../include/grph_object_id.h" -#include "../include/hw_sequencer_types.h" /* GSL Sync related values */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h index d69871ec0dde..549d70b23e82 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h @@ -28,7 +28,6 @@ #include "timing_generator.h" #include "../include/grph_object_id.h" -#include "../include/hw_sequencer_types.h" #include "dce110/dce110_timing_generator.h" diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 1a1d322da8cc..c47ce6b9fc6b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -46,7 +46,6 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, #include "stream_encoder.h" #include "clock_source.h" #include "audio.h" -#include "hw_sequencer_types.h" #include "dm_pp_smu.h" diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 6ff90a0fef24..3050afe8e8a9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -6,7 +6,6 @@ #ifndef STREAM_ENCODER_H_ #define STREAM_ENCODER_H_ -#include "include/hw_sequencer_types.h" #include "audio_types.h" struct dc_bios; diff --git a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h deleted file mode 100644 index 8ba9f65276f5..000000000000 --- a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DAL_HW_SEQUENCER_TYPES_H__ -#define __DAL_HW_SEQUENCER_TYPES_H__ - -#include "signal_types.h" -#include "grph_object_defs.h" -#include "link_service_types.h" - -#endif -- cgit v1.2.3-59-g8ed1b From 5667ff5c117f2d8735f27a267bc68a0811c55075 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Oct 2017 14:27:13 +1000 Subject: amdgpu/dc: fix a bunch of misc whitespace. This just aligns a few things with kernel style. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 ++-- drivers/gpu/drm/amd/display/dc/dc_types.h | 16 ++++---- .../display/dc/dce110/dce110_timing_generator.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 ++++---- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 46 +++++++++++----------- .../amd/display/include/grph_object_ctrl_defs.h | 20 +++++----- 6 files changed, 55 insertions(+), 55 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 888d268e9622..3c323c1ea366 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1473,10 +1473,10 @@ void decide_link_settings(struct dc_stream_state *stream, return; } - /* search for the minimum link setting that: - * 1. is supported according to the link training result - * 2. could support the b/w requested by the timing - */ + /* search for the minimum link setting that: + * 1. is supported according to the link training result + * 2. could support the b/w requested by the timing + */ while (current_link_setting.link_rate <= link->verified_link_cap.link_rate) { link_bw = bandwidth_in_kbps_from_link_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index a47f7472ea92..6b891fde400c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -429,14 +429,14 @@ union audio_sample_rates { }; struct audio_speaker_flags { - uint32_t FL_FR:1; - uint32_t LFE:1; - uint32_t FC:1; - uint32_t RL_RR:1; - uint32_t RC:1; - uint32_t FLC_FRC:1; - uint32_t RLC_RRC:1; - uint32_t SUPPORT_AI:1; + uint32_t FL_FR:1; + uint32_t LFE:1; + uint32_t FC:1; + uint32_t RL_RR:1; + uint32_t RC:1; + uint32_t FLC_FRC:1; + uint32_t RLC_RRC:1; + uint32_t SUPPORT_AI:1; }; struct audio_speaker_info { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index bcd544d85621..67ac737eaa7e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1238,8 +1238,8 @@ void dce110_timing_generator_setup_global_swap_lock( DCP_GSL_CONTROL, DCP_GSL_HSYNC_FLIP_FORCE_DELAY); - /* Keep signal low (pending high) during 6 lines. - * Also defines minimum interval before re-checking signal. */ + /* Keep signal low (pending high) during 6 lines. + * Also defines minimum interval before re-checking signal. */ set_reg_field_value(value, HFLIP_CHECK_DELAY, DCP_GSL_CONTROL, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c4875c3a0d93..d3fee15aeb79 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2396,14 +2396,14 @@ static void program_all_pipe_in_tree( dcn10_power_on_fe(dc, pipe_ctx, context); /* temporary dcn1 wa: - * watermark update requires toggle after a/b/c/d sets are programmed - * if hubp is pg then wm value doesn't get properaged to hubp - * need to toggle after ungate to ensure wm gets to hubp. - * - * final solution: we need to get SMU to do the toggle as - * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have - * both driver and fw accessing same register - */ + * watermark update requires toggle after a/b/c/d sets are programmed + * if hubp is pg then wm value doesn't get properaged to hubp + * need to toggle after ungate to ensure wm gets to hubp. + * + * final solution: we need to get SMU to do the toggle as + * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have + * both driver and fw accessing same register + */ toggle_watermark_change_req(dc->hwseq); update_dchubp_dpp(dc, pipe_ctx, context); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index c8088489c6a2..a28495d95a15 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -697,37 +697,37 @@ static void min10_set_vm_context0_settings(struct mem_input *mem_input, } static void min_set_viewport( - struct mem_input *mem_input, - const struct rect *viewport, - const struct rect *viewport_c) + struct mem_input *mem_input, + const struct rect *viewport, + const struct rect *viewport_c) { struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); - REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, - PRI_VIEWPORT_WIDTH, viewport->width, - PRI_VIEWPORT_HEIGHT, viewport->height); + REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, + PRI_VIEWPORT_WIDTH, viewport->width, + PRI_VIEWPORT_HEIGHT, viewport->height); - REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, - PRI_VIEWPORT_X_START, viewport->x, - PRI_VIEWPORT_Y_START, viewport->y); + REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, + PRI_VIEWPORT_X_START, viewport->x, + PRI_VIEWPORT_Y_START, viewport->y); - /*for stereo*/ - REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, - SEC_VIEWPORT_WIDTH, viewport->width, - SEC_VIEWPORT_HEIGHT, viewport->height); + /*for stereo*/ + REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, + SEC_VIEWPORT_WIDTH, viewport->width, + SEC_VIEWPORT_HEIGHT, viewport->height); - REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, - SEC_VIEWPORT_X_START, viewport->x, - SEC_VIEWPORT_Y_START, viewport->y); + REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, + SEC_VIEWPORT_X_START, viewport->x, + SEC_VIEWPORT_Y_START, viewport->y); - /* DC supports NV12 only at the moment */ - REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, - PRI_VIEWPORT_WIDTH_C, viewport_c->width, - PRI_VIEWPORT_HEIGHT_C, viewport_c->height); + /* DC supports NV12 only at the moment */ + REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, + PRI_VIEWPORT_WIDTH_C, viewport_c->width, + PRI_VIEWPORT_HEIGHT_C, viewport_c->height); - REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, - PRI_VIEWPORT_X_START_C, viewport_c->x, - PRI_VIEWPORT_Y_START_C, viewport_c->y); + REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, + PRI_VIEWPORT_X_START_C, viewport_c->x, + PRI_VIEWPORT_Y_START_C, viewport_c->y); } void dcn10_mem_input_read_state(struct dcn10_mem_input *mi, diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 92fe00fab87c..7a9b43f84a31 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -183,9 +183,9 @@ struct dc_firmware_info { }; struct step_and_delay_info { - uint32_t step; - uint32_t delay; - uint32_t recommended_ref_div; + uint32_t step; + uint32_t delay; + uint32_t recommended_ref_div; }; struct spread_spectrum_info { @@ -266,16 +266,16 @@ struct transmitter_configuration { #define NUMBER_OF_AVAILABLE_SCLK 5 struct i2c_reg_info { - unsigned char i2c_reg_index; - unsigned char i2c_reg_val; + unsigned char i2c_reg_index; + unsigned char i2c_reg_val; }; struct ext_hdmi_settings { - unsigned char slv_addr; - unsigned char reg_num; - struct i2c_reg_info reg_settings[9]; - unsigned char reg_num_6g; - struct i2c_reg_info reg_settings_6g[3]; + unsigned char slv_addr; + unsigned char reg_num; + struct i2c_reg_info reg_settings[9]; + unsigned char reg_num_6g; + struct i2c_reg_info reg_settings_6g[3]; }; -- cgit v1.2.3-59-g8ed1b From d029810caafa4e6b146274560154e3f0f0381fb5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Oct 2017 14:27:14 +1000 Subject: amdgpu/dc: kfree already checks for NULL. Don't bother checking for it. Found with the cocci ifnullfree.cocci script. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/vector.c | 3 +-- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 7 ++----- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 7 ++----- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +-- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 11 +++-------- 5 files changed, 9 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/basics/vector.c b/drivers/gpu/drm/amd/display/dc/basics/vector.c index e00fc4db3ac4..217b8f1f7bf6 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/vector.c +++ b/drivers/gpu/drm/amd/display/dc/basics/vector.c @@ -130,8 +130,7 @@ struct vector *dal_vector_create( void dal_vector_destruct( struct vector *vector) { - if (vector->container != NULL) - kfree(vector->container); + kfree(vector->container); vector->count = 0; vector->capacity = 0; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 2e003b5c8d08..6d2f886f7ff4 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -119,11 +119,8 @@ struct dc_bios *bios_parser_create( static void destruct(struct bios_parser *bp) { - if (bp->base.bios_local_image) - kfree(bp->base.bios_local_image); - - if (bp->base.integrated_info) - kfree(bp->base.integrated_info); + kfree(bp->base.bios_local_image); + kfree(bp->base.integrated_info); } static void bios_parser_destroy(struct dc_bios **dcb) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 0c623b314577..3d65e2ab9bf1 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -85,11 +85,8 @@ static struct atom_encoder_caps_record *get_encoder_cap_record( static void destruct(struct bios_parser *bp) { - if (bp->base.bios_local_image) - kfree(bp->base.bios_local_image); - - if (bp->base.integrated_info) - kfree(bp->base.integrated_info); + kfree(bp->base.bios_local_image); + kfree(bp->base.integrated_info); } static void firmware_parser_destroy(struct dc_bios **dcb) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 1832f252edab..99a4d19f582d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -159,8 +159,7 @@ void dc_destroy_resource_pool(struct dc *dc) if (dc->res_pool) dc->res_pool->funcs->destroy(&dc->res_pool); - if (dc->hwseq) - kfree(dc->hwseq); + kfree(dc->hwseq); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 89036aff9021..28e768de744c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -619,14 +619,9 @@ void dce110_clock_source_destroy(struct clock_source **clk_src) dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); - if (dce110_clk_src->dp_ss_params) - kfree(dce110_clk_src->dp_ss_params); - - if (dce110_clk_src->hdmi_ss_params) - kfree(dce110_clk_src->hdmi_ss_params); - - if (dce110_clk_src->dvi_ss_params) - kfree(dce110_clk_src->dvi_ss_params); + kfree(dce110_clk_src->dp_ss_params); + kfree(dce110_clk_src->hdmi_ss_params); + kfree(dce110_clk_src->dvi_ss_params); kfree(dce110_clk_src); *clk_src = NULL; -- cgit v1.2.3-59-g8ed1b From 6bf520280f3621d458e2ef3bd3c48acb89a39af7 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Tue, 5 Sep 2017 12:20:39 -0400 Subject: drm/amd/display: Driver message to SMU to indicate display off Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 38 ++++++++++++++-------- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- 4 files changed, 28 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f41f15faf019..47f16a4b9f27 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -763,7 +763,7 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); - dc->hwss.ready_shared_resources(dc); + dc->hwss.ready_shared_resources(dc, context); for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index de154329b049..b3448a41718e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1889,6 +1889,7 @@ enum dc_status dce110_apply_ctx_to_hw( return status; } + /* pplib is notified if disp_num changed */ dc->hwss.set_bandwidth(dc, context, true); /* to save power */ @@ -2683,7 +2684,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } } -static void ready_shared_resources(struct dc *dc) {} +static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} static void optimize_shared_resources(struct dc *dc) {} diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d3fee15aeb79..e60be00abcf2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -802,18 +802,14 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) IP_REQUEST_EN, 0); } -static void ready_shared_resources(struct dc *dc) -{ - if (dc->current_state->stream_count == 0 && - !dc->debug.disable_stutter) - undo_DEGVIDCN10_253_wa(dc); -} - static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = dc->res_pool->mis[0]; + if (dc->debug.disable_stutter) + return; + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); @@ -824,13 +820,6 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) mi->funcs->set_hubp_blank_en(mi, false); } -static void optimize_shared_resources(struct dc *dc) -{ - if (dc->current_state->stream_count == 0 && - !dc->debug.disable_stutter) - apply_DEGVIDCN10_253_wa(dc); -} - static void bios_golden_init(struct dc *dc) { struct dc_bios *bp = dc->ctx->dc_bios; @@ -2445,6 +2434,27 @@ static void dcn10_pplib_apply_display_requirements( dc->prev_display_config = *pp_display_cfg; } +static void optimize_shared_resources(struct dc *dc) +{ + if (dc->current_state->stream_count == 0) { + apply_DEGVIDCN10_253_wa(dc); + /* S0i2 message */ + dcn10_pplib_apply_display_requirements(dc, dc->current_state); + } +} + +static void ready_shared_resources(struct dc *dc, struct dc_state *context) +{ + if (dc->current_state->stream_count == 0 && + !dc->debug.disable_stutter) + undo_DEGVIDCN10_253_wa(dc); + + /* S0i2 message */ + if (dc->current_state->stream_count == 0 && + context->stream_count != 0) + dcn10_pplib_apply_display_requirements(dc, context); +} + static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index aae7629b1c08..1fa2edc6cfb1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -174,7 +174,7 @@ struct hw_sequencer_funcs { struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); - void (*ready_shared_resources)(struct dc *dc); + void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); }; -- cgit v1.2.3-59-g8ed1b From e008b0bcc63793d3e42fd88f412a90f329a05865 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 7 Sep 2017 17:02:47 -0400 Subject: drm/amd/display: Add FBC on/off to front-end programming - Fixing text mode for cases when VT-switch doesn't result in timing change Signed-off-by: Roman Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index b3448a41718e..590b2ad37105 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2554,6 +2554,15 @@ static void dce110_program_front_end_for_pipe( program_scaler(dc, pipe_ctx); +#ifdef ENABLE_FBC + if (dc->fbc_compressor && old_pipe->stream) { + if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) + dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); + else + enable_fbc(dc, dc->current_state); + } +#endif + mi->funcs->mem_input_program_surface_config( mi, plane_state->format, -- cgit v1.2.3-59-g8ed1b From 98b49c2f9c66cf42b6d762498e2d9f327e439416 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 11 Sep 2017 16:28:21 -0400 Subject: drm/amd/display: fix multi-display on CZ - fixed wrong index in dce110_validate_surface_sets() - formatted for better readability Signed-off-by: Roman Li Reviewed-by: Harry Wentland igned-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_resource.c | 29 ++++++++++++++++------ 1 file changed, 21 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 28e768de744c..8e4ec61d59a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -849,7 +849,7 @@ static bool dce110_validate_bandwidth( static bool dce110_validate_surface_sets( struct dc_state *context) { - int i; + int i, j; for (i = 0; i < context->stream_count; i++) { if (context->stream_status[i].plane_count == 0) @@ -858,14 +858,27 @@ static bool dce110_validate_surface_sets( if (context->stream_status[i].plane_count > 2) return false; - if ((context->stream_status[i].plane_states[i]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) && - (context->stream_status[i].plane_states[i]->src_rect.width > 1920 || - context->stream_status[i].plane_states[i]->src_rect.height > 1080)) - return false; + for (j = 0; j < context->stream_status[i].plane_count; j++) { + struct dc_plane_state *plane = + context->stream_status[i].plane_states[j]; - /* irrespective of plane format, stream should be RGB encoded */ - if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) - return false; + /* underlay validation */ + if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + + if ((plane->src_rect.width > 1920 || + plane->src_rect.height > 1080)) + return false; + + /* irrespective of plane format, + * stream should be RGB encoded + */ + if (context->streams[i]->timing.pixel_encoding + != PIXEL_ENCODING_RGB) + return false; + + } + + } } return true; -- cgit v1.2.3-59-g8ed1b From 68d77dd8214e5186d535ec7af29722aaad621824 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Wed, 13 Sep 2017 11:36:34 -0400 Subject: drm/amd/display: power_down_Hw need signal type to turnoff backlight Signed-off-by: Charlene Liu Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 590b2ad37105..d83a330712f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1171,6 +1171,7 @@ static void power_down_encoders(struct dc *dc) { int i; enum connector_id connector_id; + enum signal_type signal = SIGNAL_TYPE_NONE; for (i = 0; i < dc->link_count; i++) { connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || @@ -1178,10 +1179,12 @@ static void power_down_encoders(struct dc *dc) if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(dc->links[i], false); + if (connector_id == CONNECTOR_ID_EDP) + signal = SIGNAL_TYPE_EDP; } dc->links[i]->link_enc->funcs->disable_output( - dc->links[i]->link_enc, SIGNAL_TYPE_NONE); + dc->links[i]->link_enc, signal); } } -- cgit v1.2.3-59-g8ed1b From 5eefbc40173644b5f74d7e074ba6cd8de5563e05 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Fri, 15 Sep 2017 17:42:20 -0400 Subject: drm/amd/display: moving backlight registers to hwsequencer Signed-off-by: Yue Hin Lau Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 ++- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 47 +++++++--- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 79 +--------------- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 27 ++---- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 103 ++++++++++++++++++++- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 + .../amd/display/dc/virtual/virtual_link_encoder.c | 8 +- 9 files changed, 158 insertions(+), 127 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c7751a31081a..976f0f136f29 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1807,7 +1807,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) else dp_disable_link_phy_mst(link, signal); } else - link->link_enc->funcs->disable_output(link->link_enc, signal); + link->link_enc->funcs->disable_output(link->link_enc, signal, link); } enum dc_status dc_link_validate_mode_timing( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 5f815cab94b5..fa2250554be5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -94,7 +94,7 @@ void dp_enable_link_phy( link_enc, link_settings, clock_source); - link_enc->funcs->backlight_control(link_enc, true); + link->dc->hwss.backlight_control(link, true); } else link_enc->funcs->enable_dp_output( link_enc, @@ -138,12 +138,12 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) dp_receiver_power_ctrl(link, false); if (signal == SIGNAL_TYPE_EDP) { - link->link_enc->funcs->backlight_control(link->link_enc, false); + link->dc->hwss.backlight_control(link, false); edp_receiver_ready_T9(link); - link->link_enc->funcs->disable_output(link->link_enc, signal); + link->link_enc->funcs->disable_output(link->link_enc, signal, link); link->link_enc->funcs->power_control(link->link_enc, false); } else - link->link_enc->funcs->disable_output(link->link_enc, signal); + link->link_enc->funcs->disable_output(link->link_enc, signal, link); /* Clear current link setting.*/ memset(&link->cur_link_settings, 0, @@ -286,7 +286,8 @@ void dp_retrain_link_dp_test(struct dc_link *link, link->link_enc->funcs->disable_output( link->link_enc, - SIGNAL_TYPE_DISPLAY_PORT); + SIGNAL_TYPE_DISPLAY_PORT, + link); /* Clear current link setting. */ memset(&link->cur_link_settings, 0, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 5798001da770..227c9b655b65 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -27,6 +27,10 @@ #include "hw_sequencer.h" +#define BL_REG_LIST()\ + SR(LVTMA_PWRSEQ_CNTL), \ + SR(LVTMA_PWRSEQ_STATE) + #define HWSEQ_DCEF_REG_LIST_DCE8() \ .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ @@ -86,24 +90,27 @@ SRII(BLND_CONTROL, BLND, 0),\ SRII(BLND_CONTROL, BLND, 1),\ SR(BLNDV_CONTROL),\ - HWSEQ_PIXEL_RATE_REG_LIST(CRTC) + HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ + BL_REG_LIST() #define HWSEQ_DCE8_REG_LIST() \ HWSEQ_DCEF_REG_LIST_DCE8(), \ HWSEQ_BLND_REG_LIST(), \ - HWSEQ_PIXEL_RATE_REG_LIST(CRTC) + HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ + BL_REG_LIST() #define HWSEQ_DCE10_REG_LIST() \ HWSEQ_DCEF_REG_LIST(), \ HWSEQ_BLND_REG_LIST(), \ - HWSEQ_PIXEL_RATE_REG_LIST(CRTC) + HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ + BL_REG_LIST() #define HWSEQ_ST_REG_LIST() \ HWSEQ_DCE11_REG_LIST_BASE(), \ .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ - .BLND_CONTROL[2] = mmBLNDV_CONTROL, + .BLND_CONTROL[2] = mmBLNDV_CONTROL #define HWSEQ_CZ_REG_LIST() \ HWSEQ_DCE11_REG_LIST_BASE(), \ @@ -123,12 +130,14 @@ SR(DCHUB_FB_LOCATION),\ SR(DCHUB_AGP_BASE),\ SR(DCHUB_AGP_BOT),\ - SR(DCHUB_AGP_TOP) + SR(DCHUB_AGP_TOP), \ + BL_REG_LIST() #define HWSEQ_DCE112_REG_LIST() \ HWSEQ_DCE10_REG_LIST(), \ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ - HWSEQ_PHYPLL_REG_LIST(CRTC) + HWSEQ_PHYPLL_REG_LIST(CRTC), \ + BL_REG_LIST() #define HWSEQ_DCN_REG_LIST()\ SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \ @@ -228,9 +237,15 @@ SR(D2VGA_CONTROL), \ SR(D3VGA_CONTROL), \ SR(D4VGA_CONTROL), \ - SR(DC_IP_REQUEST_CNTL) + SR(DC_IP_REQUEST_CNTL), \ + BL_REG_LIST() struct dce_hwseq_registers { + + /* Backlight registers */ + uint32_t LVTMA_PWRSEQ_CNTL; + uint32_t LVTMA_PWRSEQ_STATE; + uint32_t DCFE_CLOCK_CONTROL[6]; uint32_t DCFEV_CLOCK_CONTROL; uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; @@ -375,20 +390,24 @@ struct dce_hwseq_registers { HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ - HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ @@ -396,14 +415,16 @@ struct dce_hwseq_registers { SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ - SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) + SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ - HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) + HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ @@ -467,7 +488,8 @@ struct dce_hwseq_registers { HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ - HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) #define HWSEQ_REG_FIELD_LIST(type) \ type DCFE_CLOCK_ENABLE; \ @@ -497,7 +519,8 @@ struct dce_hwseq_registers { type PHYSICAL_PAGE_NUMBER_LSB;\ type LOGICAL_ADDR; \ type ENABLE_L1_TLB;\ - type SYSTEM_ACCESS_MODE; + type SYSTEM_ACCESS_MODE;\ + type LVTMA_BLON; #define HWSEQ_DCN_REG_FIELD_LIST(type) \ type VUPDATE_NO_LOCK_EVENT_CLEAR; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 37aeddfb7431..1cb727bdaa56 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -122,7 +122,6 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .psr_program_dp_dphy_fast_training = dce110_psr_program_dp_dphy_fast_training, .psr_program_secondary_packet = dce110_psr_program_secondary_packet, - .backlight_control = dce110_link_encoder_edp_backlight_control, .power_control = dce110_link_encoder_edp_power_control, .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, .enable_hpd = dce110_link_encoder_enable_hpd, @@ -674,16 +673,6 @@ static void aux_initialize( } -/*todo: cloned in stream enc, fix*/ -static bool is_panel_backlight_on(struct dce110_link_encoder *enc110) -{ - uint32_t value; - - REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); - - return value; -} - void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, bool exit_link_training_required) { @@ -718,69 +707,6 @@ void dce110_psr_program_secondary_packet(struct link_encoder *enc, DP_SEC_GSP0_PRIORITY, 1); } -/*todo: cloned in stream enc, fix*/ -/* - * @brief - * eDP only. Control the backlight of the eDP panel - */ -void dce110_link_encoder_edp_backlight_control( - struct link_encoder *enc, - bool enable) -{ - struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - struct dc_context *ctx = enc110->base.ctx; - struct bp_transmitter_control cntl = { 0 }; - - if (dal_graphics_object_id_get_connector_id(enc110->base.connector) - != CONNECTOR_ID_EDP) { - BREAK_TO_DEBUGGER(); - return; - } - - if (enable && is_panel_backlight_on(enc110)) { - dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, - "%s: panel already powered up. Do nothing.\n", - __func__); - return; - } - - if (!enable && !is_panel_backlight_on(enc110)) { - dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, - "%s: panel already powered down. Do nothing.\n", - __func__); - return; - } - - /* Send VBIOS command to control eDP panel backlight */ - - dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, - "%s: backlight action: %s\n", - __func__, (enable ? "On":"Off")); - - cntl.action = enable ? - TRANSMITTER_CONTROL_BACKLIGHT_ON : - TRANSMITTER_CONTROL_BACKLIGHT_OFF; - /*cntl.engine_id = ctx->engine;*/ - cntl.transmitter = enc110->base.transmitter; - cntl.connector_obj_id = enc110->base.connector; - /*todo: unhardcode*/ - cntl.lanes_number = LANE_COUNT_FOUR; - cntl.hpd_sel = enc110->base.hpd_source; - - /* For eDP, the following delays might need to be considered - * after link training completed: - * idle period - min. accounts for required BS-Idle pattern, - * max. allows for source frame synchronization); - * 50 msec max. delay from valid video data from source - * to video on dislpay or backlight enable. - * - * Disable the delay for now. - * Enable it in the future if necessary. - */ - /* dc_service_sleep_in_milliseconds(50); */ - link_transmitter_control(enc110, &cntl); -} - static bool is_dig_enabled(const struct dce110_link_encoder *enc110) { uint32_t value; @@ -1279,7 +1205,8 @@ void dce110_link_encoder_enable_dp_mst_output( */ void dce110_link_encoder_disable_output( struct link_encoder *enc, - enum signal_type signal) + enum signal_type signal, + struct dc_link *link) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); struct dc_context *ctx = enc110->base.ctx; @@ -1291,7 +1218,7 @@ void dce110_link_encoder_disable_output( return; } if (enc110->base.connector.id == CONNECTOR_ID_EDP) - dce110_link_encoder_edp_backlight_control(enc, false); + ctx->dc->hwss.backlight_control(link, false); /* Power-down RX and disable GPU PHY should be paired. * Disabling PHY without powering down RX may cause * symbol lock loss, on which we will get DP Sink interrupt. */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 05463df7e636..c65def5f6a44 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -69,10 +69,6 @@ SRI(DP_DPHY_FAST_TRAINING, DP, id), \ SRI(DP_SEC_CNTL1, DP, id) -#define LE_EDP_REG_LIST(id)\ - SR(LVTMA_PWRSEQ_CNTL), \ - SR(LVTMA_PWRSEQ_STATE) - #define LE_COMMON_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ @@ -81,38 +77,32 @@ #define LE_DCE80_REG_LIST(id)\ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id), \ - LE_EDP_REG_LIST(id) + LE_COMMON_REG_LIST_BASE(id) #define LE_DCE100_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - SR(DCI_MEM_PWR_STATUS), \ - LE_EDP_REG_LIST(id) + SR(DCI_MEM_PWR_STATUS) #define LE_DCE110_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ - SR(DCI_MEM_PWR_STATUS), \ - LE_EDP_REG_LIST(id) + SR(DCI_MEM_PWR_STATUS) #define LE_DCE120_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ - SR(DCI_MEM_PWR_STATUS), \ - LE_EDP_REG_LIST(id) + SR(DCI_MEM_PWR_STATUS) #define LE_DCN10_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ - SR(DMU_MEM_PWR_CNTL), \ - LE_EDP_REG_LIST(id) + SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) struct dce110_link_enc_aux_registers { uint32_t AUX_CONTROL; @@ -243,7 +233,8 @@ void dce110_link_encoder_enable_dp_mst_output( /* disable PHY output */ void dce110_link_encoder_disable_output( struct link_encoder *link_enc, - enum signal_type signal); + enum signal_type signal, + struct dc_link *link); /* set DP lane settings */ void dce110_link_encoder_dp_set_lane_settings( @@ -259,10 +250,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table); -void dce110_link_encoder_edp_backlight_control( - struct link_encoder *enc, - bool enable); - void dce110_link_encoder_edp_power_control( struct link_encoder *enc, bool power_up); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d83a330712f7..9fc43bcac5bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -56,6 +56,15 @@ #include "dce/dce_11_0_sh_mask.h" #include "custom_float.h" +#define CTX \ + hws->ctx +#define REG(reg)\ + hws->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + struct dce110_hw_seq_reg_offsets { uint32_t crtc; }; @@ -761,6 +770,92 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) } +/*todo: cloned in stream enc, fix*/ +static bool is_panel_backlight_on(struct dce_hwseq *hws) +{ + uint32_t value; + + REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); + + return value; +} + +static enum bp_result link_transmitter_control( + struct dc_link *link, + struct bp_transmitter_control *cntl) +{ + enum bp_result result; + struct dc_bios *bp = link->dc->ctx->dc_bios; + + result = bp->funcs->transmitter_control(bp, cntl); + + return result; +} + + +/*todo: cloned in stream enc, fix*/ +/* + * @brief + * eDP only. Control the backlight of the eDP panel + */ +void hwss_blacklight_control( + struct dc_link *link, + bool enable) +{ + struct dce_hwseq *hws = link->dc->hwseq; + struct dc_context *ctx = link->dc->ctx; + struct bp_transmitter_control cntl = { 0 }; + + if (dal_graphics_object_id_get_connector_id(link->link_id) + != CONNECTOR_ID_EDP) { + BREAK_TO_DEBUGGER(); + return; + } + + if (enable && is_panel_backlight_on(hws)) { + dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, + "%s: panel already powered up. Do nothing.\n", + __func__); + return; + } + + if (!enable && !is_panel_backlight_on(hws)) { + dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, + "%s: panel already powered down. Do nothing.\n", + __func__); + return; + } + + /* Send VBIOS command to control eDP panel backlight */ + + dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, + "%s: backlight action: %s\n", + __func__, (enable ? "On":"Off")); + + cntl.action = enable ? + TRANSMITTER_CONTROL_BACKLIGHT_ON : + TRANSMITTER_CONTROL_BACKLIGHT_OFF; + /*cntl.engine_id = ctx->engine;*/ + cntl.transmitter = link->link_enc->transmitter; + cntl.connector_obj_id = link->link_enc->connector; + /*todo: unhardcode*/ + cntl.lanes_number = LANE_COUNT_FOUR; + cntl.hpd_sel = link->link_enc->hpd_source; + + /* For eDP, the following delays might need to be considered + * after link training completed: + * idle period - min. accounts for required BS-Idle pattern, + * max. allows for source frame synchronization); + * 50 msec max. delay from valid video data from source + * to video on dislpay or backlight enable. + * + * Disable the delay for now. + * Enable it in the future if necessary. + */ + /* dc_service_sleep_in_milliseconds(50); */ + link_transmitter_control(link, &cntl); +} + void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -798,7 +893,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) /* blank at encoder level */ if (dc_is_dp_signal(pipe_ctx->stream->signal)) { if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP) - link->link_enc->funcs->backlight_control(link->link_enc, false); + hwss_blacklight_control(link, false); pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); } link->link_enc->funcs->connect_dig_be_to_fe( @@ -820,7 +915,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); if (link->connector_signal == SIGNAL_TYPE_EDP) - link->link_enc->funcs->backlight_control(link->link_enc, true); + hwss_blacklight_control(link, true); } @@ -1184,7 +1279,7 @@ static void power_down_encoders(struct dc *dc) } dc->links[i]->link_enc->funcs->disable_output( - dc->links[i]->link_enc, signal); + dc->links[i]->link_enc, signal, dc->links[i]); } } @@ -2733,7 +2828,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, - + .backlight_control = hwss_blacklight_control }; void dce110_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 961bbcc9202c..6cd6bc7d15fb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -111,7 +111,7 @@ struct link_encoder_funcs { const struct dc_link_settings *link_settings, enum clock_source_id clock_source); void (*disable_output)(struct link_encoder *link_enc, - enum signal_type signal); + enum signal_type signal, struct dc_link *link); void (*dp_set_lane_settings)(struct link_encoder *enc, const struct link_training_settings *link_settings); void (*dp_set_phy_pattern)(struct link_encoder *enc, @@ -123,8 +123,6 @@ struct link_encoder_funcs { bool exit_link_training_required); void (*psr_program_secondary_packet)(struct link_encoder *enc, unsigned int sdp_transmit_line_num_deadline); - void (*backlight_control) (struct link_encoder *enc, - bool enable); void (*power_control) (struct link_encoder *enc, bool power_up); void (*connect_dig_be_to_fe)(struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 1fa2edc6cfb1..210874f37722 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -176,6 +176,10 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); + + void (*backlight_control)( + struct dc_link *link, + bool enable); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index db513abd735a..4f405348130f 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -58,7 +58,8 @@ static void virtual_link_encoder_enable_dp_mst_output( static void virtual_link_encoder_disable_output( struct link_encoder *link_enc, - enum signal_type signal) {} + enum signal_type signal, + struct dc_link *link) {} static void virtual_link_encoder_dp_set_lane_settings( struct link_encoder *enc, @@ -72,10 +73,6 @@ static void virtual_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table) {} -static void virtual_link_encoder_edp_backlight_control( - struct link_encoder *enc, - bool enable) {} - static void virtual_link_encoder_edp_power_control( struct link_encoder *enc, bool power_up) {} @@ -105,7 +102,6 @@ static const struct link_encoder_funcs virtual_lnk_enc_funcs = { .dp_set_phy_pattern = virtual_link_encoder_dp_set_phy_pattern, .update_mst_stream_allocation_table = virtual_link_encoder_update_mst_stream_allocation_table, - .backlight_control = virtual_link_encoder_edp_backlight_control, .power_control = virtual_link_encoder_edp_power_control, .connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe, .destroy = virtual_link_encoder_destroy -- cgit v1.2.3-59-g8ed1b From dbaed8037c6c606456c182f5fc327f9d405a7ffe Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Tue, 19 Sep 2017 11:35:23 -0400 Subject: drm/amd/display: edp backlight regression fix Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 5 +++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 + 2 files changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index db6c19cd15eb..3e95f7f92c73 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -68,5 +68,10 @@ void dce110_fill_display_configs( uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); + +void hwss_blacklight_control( + struct dc_link *link, + bool enable); + #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 82a985a981be..bf5c9243ba7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2897,6 +2897,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .backlight_control = hwss_blacklight_control }; -- cgit v1.2.3-59-g8ed1b From 19af33aca4384f840838a781f105726bb24c604f Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 20 Sep 2017 14:06:24 -0400 Subject: drm/amd/display: make sure BL off to mainlink off has enough time Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 9fc43bcac5bc..f28fce6e6ba4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -819,13 +819,6 @@ void hwss_blacklight_control( return; } - if (!enable && !is_panel_backlight_on(hws)) { - dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, - "%s: panel already powered down. Do nothing.\n", - __func__); - return; - } - /* Send VBIOS command to control eDP panel backlight */ dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, -- cgit v1.2.3-59-g8ed1b From 8740196935625dfb171ab115120315060e4a8a41 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Mon, 25 Sep 2017 18:03:14 -0400 Subject: drm/amd/display: Move power control from link encoder to hwsequencer A recent commit moved the backlight control code along with the register defines, but did not move the power control code. This along with remnant fields in the dce110_link_enc_registers struct made it so that the code still compiled, but any attempts to access the LVTMA_PWRSEQ_STATE register led to reading from an address of 0. This patch corrects that. Also, rename blacklight_control to edp_backlight_control (Typo fix). Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 8 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 18 ++- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 171 +-------------------- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 8 - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 155 +++++++++++++++++-- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 6 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 - drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 7 +- drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 4 + .../amd/display/dc/virtual/virtual_link_encoder.c | 5 - 12 files changed, 190 insertions(+), 214 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a58e61b6e9f9..feb10be0ce4c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -78,14 +78,15 @@ static void destruct(struct dc_link *link) dc_sink_release(link->remote_sinks[i]); } -static struct gpio *get_hpd_gpio(const struct dc_link *link) +struct gpio *get_hpd_gpio(struct dc_bios *dcb, + struct graphics_object_id link_id, + struct gpio_service *gpio_service) { enum bp_result bp_result; - struct dc_bios *dcb = link->ctx->dc_bios; struct graphics_object_hpd_info hpd_info; struct gpio_pin_info pin_info; - if (dcb->funcs->get_hpd_info(dcb, link->link_id, &hpd_info) != BP_RESULT_OK) + if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK) return NULL; bp_result = dcb->funcs->get_gpio_pin_info(dcb, @@ -97,7 +98,7 @@ static struct gpio *get_hpd_gpio(const struct dc_link *link) } return dal_gpio_service_create_irq( - link->ctx->gpio_service, + gpio_service, pin_info.offset, pin_info.mask); } @@ -153,7 +154,7 @@ static bool program_hpd_filter( } /* Obtain HPD handle */ - hpd = get_hpd_gpio(link); + hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); if (!hpd) return result; @@ -186,7 +187,7 @@ static bool detect_sink(struct dc_link *link, enum dc_connection_type *type) struct gpio *hpd_pin; /* todo: may need to lock gpio access */ - hpd_pin = get_hpd_gpio(link); + hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); if (hpd_pin == NULL) goto hpd_gpio_failure; @@ -795,7 +796,7 @@ static enum hpd_source_id get_hpd_line( struct gpio *hpd; enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN; - hpd = get_hpd_gpio(link); + hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); if (hpd) { switch (dal_irq_get_source(hpd)) { @@ -965,7 +966,7 @@ static bool construct( goto create_fail; } - hpd_gpio = get_hpd_gpio(link); + hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); if (hpd_gpio != NULL) link->irq_source_hpd = dal_irq_get_source(hpd_gpio); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index fa2250554be5..34b6d1cb151e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -89,12 +89,12 @@ void dp_enable_link_phy( if (dc_is_dp_sst_signal(signal)) { if (signal == SIGNAL_TYPE_EDP) { - link_enc->funcs->power_control(link_enc, true); + link->dc->hwss.edp_power_control(link->link_enc, true); link_enc->funcs->enable_dp_output( link_enc, link_settings, clock_source); - link->dc->hwss.backlight_control(link, true); + link->dc->hwss.edp_backlight_control(link, true); } else link_enc->funcs->enable_dp_output( link_enc, @@ -138,10 +138,10 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) dp_receiver_power_ctrl(link, false); if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.backlight_control(link, false); + link->dc->hwss.edp_backlight_control(link, false); edp_receiver_ready_T9(link); link->link_enc->funcs->disable_output(link->link_enc, signal, link); - link->link_enc->funcs->power_control(link->link_enc, false); + link->dc->hwss.edp_power_control(link->link_enc, false); } else link->link_enc->funcs->disable_output(link->link_enc, signal, link); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 227c9b655b65..0a058e0c3fec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -391,23 +391,27 @@ struct dce_hwseq_registers { HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ - HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ @@ -416,7 +420,8 @@ struct dce_hwseq_registers { SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ - HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ @@ -424,7 +429,8 @@ struct dce_hwseq_registers { HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ - HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ @@ -489,7 +495,8 @@ struct dce_hwseq_registers { HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ - HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh) + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) #define HWSEQ_REG_FIELD_LIST(type) \ type DCFE_CLOCK_ENABLE; \ @@ -520,7 +527,8 @@ struct dce_hwseq_registers { type LOGICAL_ADDR; \ type ENABLE_L1_TLB;\ type SYSTEM_ACCESS_MODE;\ - type LVTMA_BLON; + type LVTMA_BLON;\ + type LVTMA_PWRSEQ_TARGET_STATE_R; #define HWSEQ_DCN_REG_FIELD_LIST(type) \ type VUPDATE_NO_LOCK_EVENT_CLEAR; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 1cb727bdaa56..0cf0fff74d44 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -82,13 +82,6 @@ #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 -/* all values are in milliseconds */ -/* For eDP, after power-up/power/down, - * 300/500 msec max. delay from LCDVCC to black video generation */ -#define PANEL_POWER_UP_TIMEOUT 300 -#define PANEL_POWER_DOWN_TIMEOUT 500 -#define HPD_CHECK_INTERVAL 10 - /* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */ #define TMDS_MIN_PIXEL_CLOCK 25000 /* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */ @@ -122,7 +115,6 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .psr_program_dp_dphy_fast_training = dce110_psr_program_dp_dphy_fast_training, .psr_program_secondary_packet = dce110_psr_program_secondary_packet, - .power_control = dce110_link_encoder_edp_power_control, .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, .enable_hpd = dce110_link_encoder_enable_hpd, .disable_hpd = dce110_link_encoder_disable_hpd, @@ -492,165 +484,6 @@ static void configure_encoder( REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); } -static bool is_panel_powered_on(struct dce110_link_encoder *enc110) -{ - bool ret; - uint32_t value; - - REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value); - ret = value; - - return ret == 1; -} - - -/* TODO duplicate of dc_link.c version */ -static struct gpio *get_hpd_gpio(const struct link_encoder *enc) -{ - enum bp_result bp_result; - struct dc_bios *dcb = enc->ctx->dc_bios; - struct graphics_object_hpd_info hpd_info; - struct gpio_pin_info pin_info; - - if (dcb->funcs->get_hpd_info(dcb, enc->connector, &hpd_info) != BP_RESULT_OK) - return NULL; - - bp_result = dcb->funcs->get_gpio_pin_info(dcb, - hpd_info.hpd_int_gpio_uid, &pin_info); - - if (bp_result != BP_RESULT_OK) { - ASSERT(bp_result == BP_RESULT_NORECORD); - return NULL; - } - - return dal_gpio_service_create_irq( - enc->ctx->gpio_service, - pin_info.offset, - pin_info.mask); -} - -/* - * @brief - * eDP only. - */ -static void link_encoder_edp_wait_for_hpd_ready( - struct dce110_link_encoder *enc110, - bool power_up) -{ - struct dc_context *ctx = enc110->base.ctx; - struct graphics_object_id connector = enc110->base.connector; - struct gpio *hpd; - bool edp_hpd_high = false; - uint32_t time_elapsed = 0; - uint32_t timeout = power_up ? - PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; - - if (dal_graphics_object_id_get_connector_id(connector) != - CONNECTOR_ID_EDP) { - BREAK_TO_DEBUGGER(); - return; - } - - if (!power_up) - /* from KV, we will not HPD low after turning off VCC - - * instead, we will check the SW timer in power_up(). */ - return; - - /* when we power on/off the eDP panel, - * we need to wait until SENSE bit is high/low */ - - /* obtain HPD */ - /* TODO what to do with this? */ - hpd = get_hpd_gpio(&enc110->base); - - if (!hpd) { - BREAK_TO_DEBUGGER(); - return; - } - - dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); - - /* wait until timeout or panel detected */ - - do { - uint32_t detected = 0; - - dal_gpio_get_value(hpd, &detected); - - if (!(detected ^ power_up)) { - edp_hpd_high = true; - break; - } - - msleep(HPD_CHECK_INTERVAL); - - time_elapsed += HPD_CHECK_INTERVAL; - } while (time_elapsed < timeout); - - dal_gpio_close(hpd); - - dal_gpio_destroy_irq(&hpd); - - if (false == edp_hpd_high) { - dm_logger_write(ctx->logger, LOG_ERROR, - "%s: wait timed out!\n", __func__); - } -} - -/* - * @brief - * eDP only. Control the power of the eDP panel. - */ -void dce110_link_encoder_edp_power_control( - struct link_encoder *enc, - bool power_up) -{ - struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - struct dc_context *ctx = enc110->base.ctx; - struct bp_transmitter_control cntl = { 0 }; - enum bp_result bp_result; - - if (dal_graphics_object_id_get_connector_id(enc110->base.connector) != - CONNECTOR_ID_EDP) { - BREAK_TO_DEBUGGER(); - return; - } - - if ((power_up && !is_panel_powered_on(enc110)) || - (!power_up && is_panel_powered_on(enc110))) { - - /* Send VBIOS command to prompt eDP panel power */ - - dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, - "%s: Panel Power action: %s\n", - __func__, (power_up ? "On":"Off")); - - cntl.action = power_up ? - TRANSMITTER_CONTROL_POWER_ON : - TRANSMITTER_CONTROL_POWER_OFF; - cntl.transmitter = enc110->base.transmitter; - cntl.connector_obj_id = enc110->base.connector; - cntl.coherent = false; - cntl.lanes_number = LANE_COUNT_FOUR; - cntl.hpd_sel = enc110->base.hpd_source; - - bp_result = link_transmitter_control(enc110, &cntl); - - if (BP_RESULT_OK != bp_result) { - - dm_logger_write(ctx->logger, LOG_ERROR, - "%s: Panel Power bp_result: %d\n", - __func__, bp_result); - } - } else { - dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, - "%s: Skipping Panel Power action: %s\n", - __func__, (power_up ? "On":"Off")); - } - - link_encoder_edp_wait_for_hpd_ready(enc110, true); -} - static void aux_initialize( struct dce110_link_encoder *enc110) { @@ -1018,7 +851,7 @@ void dce110_link_encoder_hw_init( ASSERT(result == BP_RESULT_OK); } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - enc->funcs->power_control(&enc110->base, true); + ctx->dc->hwss.edp_power_control(enc, true); } aux_initialize(enc110); @@ -1218,7 +1051,7 @@ void dce110_link_encoder_disable_output( return; } if (enc110->base.connector.id == CONNECTOR_ID_EDP) - ctx->dc->hwss.backlight_control(link, false); + ctx->dc->hwss.edp_backlight_control(link, false); /* Power-down RX and disable GPU PHY should be paired. * Disabling PHY without powering down RX may cause * symbol lock loss, on which we will get DP Sink interrupt. */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index c65def5f6a44..494067dedd03 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -114,10 +114,6 @@ struct dce110_link_enc_hpd_registers { }; struct dce110_link_enc_registers { - /* Backlight registers */ - uint32_t LVTMA_PWRSEQ_CNTL; - uint32_t LVTMA_PWRSEQ_STATE; - /* DMCU registers */ uint32_t MASTER_COMM_DATA_REG1; uint32_t MASTER_COMM_DATA_REG2; @@ -250,10 +246,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table); -void dce110_link_encoder_edp_power_control( - struct link_encoder *enc, - bool power_up); - void dce110_link_encoder_connect_dig_be_to_fe( struct link_encoder *enc, enum engine_id engine, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index f28fce6e6ba4..a891e387ed7b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -32,6 +32,7 @@ #include "dce110_hw_sequencer.h" #include "dce110_timing_generator.h" #include "dce/dce_hwseq.h" +#include "gpio_service_interface.h" #ifdef ENABLE_FBC #include "dce110_compressor.h" @@ -45,10 +46,10 @@ #include "transform.h" #include "stream_encoder.h" #include "link_encoder.h" +#include "link_hwss.h" #include "clock_source.h" #include "abm.h" #include "audio.h" -#include "dce/dce_hwseq.h" #include "reg_helper.h" /* include DCE11 register header files */ @@ -56,6 +57,15 @@ #include "dce/dce_11_0_sh_mask.h" #include "custom_float.h" +/* + * All values are in milliseconds; + * For eDP, after power-up/power/down, + * 300/500 msec max. delay from LCDVCC to black video generation + */ +#define PANEL_POWER_UP_TIMEOUT 300 +#define PANEL_POWER_DOWN_TIMEOUT 500 +#define HPD_CHECK_INTERVAL 10 + #define CTX \ hws->ctx #define REG(reg)\ @@ -780,25 +790,150 @@ static bool is_panel_backlight_on(struct dce_hwseq *hws) return value; } +static bool is_panel_powered_on(struct dce_hwseq *hws) +{ + uint32_t value; + + REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value); + return value == 1; +} + static enum bp_result link_transmitter_control( - struct dc_link *link, + struct dc_bios *bios, struct bp_transmitter_control *cntl) { enum bp_result result; - struct dc_bios *bp = link->dc->ctx->dc_bios; - result = bp->funcs->transmitter_control(bp, cntl); + result = bios->funcs->transmitter_control(bios, cntl); return result; } +/* + * @brief + * eDP only. + */ +void hwss_edp_wait_for_hpd_ready( + struct link_encoder *enc, + bool power_up) +{ + struct dc_context *ctx = enc->ctx; + struct graphics_object_id connector = enc->connector; + struct gpio *hpd; + bool edp_hpd_high = false; + uint32_t time_elapsed = 0; + uint32_t timeout = power_up ? + PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; + + if (dal_graphics_object_id_get_connector_id(connector) + != CONNECTOR_ID_EDP) { + BREAK_TO_DEBUGGER(); + return; + } + + if (!power_up) + /* + * From KV, we will not HPD low after turning off VCC - + * instead, we will check the SW timer in power_up(). + */ + return; + + /* + * When we power on/off the eDP panel, + * we need to wait until SENSE bit is high/low. + */ + + /* obtain HPD */ + /* TODO what to do with this? */ + hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); + + if (!hpd) { + BREAK_TO_DEBUGGER(); + return; + } + + dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); + + /* wait until timeout or panel detected */ + + do { + uint32_t detected = 0; + + dal_gpio_get_value(hpd, &detected); + + if (!(detected ^ power_up)) { + edp_hpd_high = true; + break; + } + + msleep(HPD_CHECK_INTERVAL); + + time_elapsed += HPD_CHECK_INTERVAL; + } while (time_elapsed < timeout); + + dal_gpio_close(hpd); + + dal_gpio_destroy_irq(&hpd); + + if (false == edp_hpd_high) { + dm_logger_write(ctx->logger, LOG_ERROR, + "%s: wait timed out!\n", __func__); + } +} + +void hwss_edp_power_control( + struct link_encoder *enc, + bool power_up) +{ + struct dc_context *ctx = enc->ctx; + struct dce_hwseq *hwseq = ctx->dc->hwseq; + struct bp_transmitter_control cntl = { 0 }; + enum bp_result bp_result; + + + if (dal_graphics_object_id_get_connector_id(enc->connector) + != CONNECTOR_ID_EDP) { + BREAK_TO_DEBUGGER(); + return; + } + + if (power_up != is_panel_powered_on(hwseq)) { + /* Send VBIOS command to prompt eDP panel power */ + + dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, + "%s: Panel Power action: %s\n", + __func__, (power_up ? "On":"Off")); + + cntl.action = power_up ? + TRANSMITTER_CONTROL_POWER_ON : + TRANSMITTER_CONTROL_POWER_OFF; + cntl.transmitter = enc->transmitter; + cntl.connector_obj_id = enc->connector; + cntl.coherent = false; + cntl.lanes_number = LANE_COUNT_FOUR; + cntl.hpd_sel = enc->hpd_source; + + bp_result = link_transmitter_control(ctx->dc_bios, &cntl); + + if (bp_result != BP_RESULT_OK) + dm_logger_write(ctx->logger, LOG_ERROR, + "%s: Panel Power bp_result: %d\n", + __func__, bp_result); + } else { + dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, + "%s: Skipping Panel Power action: %s\n", + __func__, (power_up ? "On":"Off")); + } + + hwss_edp_wait_for_hpd_ready(enc, true); +} /*todo: cloned in stream enc, fix*/ /* * @brief * eDP only. Control the backlight of the eDP panel */ -void hwss_blacklight_control( +void hwss_edp_backlight_control( struct dc_link *link, bool enable) { @@ -828,6 +963,7 @@ void hwss_blacklight_control( cntl.action = enable ? TRANSMITTER_CONTROL_BACKLIGHT_ON : TRANSMITTER_CONTROL_BACKLIGHT_OFF; + /*cntl.engine_id = ctx->engine;*/ cntl.transmitter = link->link_enc->transmitter; cntl.connector_obj_id = link->link_enc->connector; @@ -846,7 +982,7 @@ void hwss_blacklight_control( * Enable it in the future if necessary. */ /* dc_service_sleep_in_milliseconds(50); */ - link_transmitter_control(link, &cntl); + link_transmitter_control(link->dc->ctx->dc_bios, &cntl); } void dce110_disable_stream(struct pipe_ctx *pipe_ctx) @@ -886,7 +1022,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) /* blank at encoder level */ if (dc_is_dp_signal(pipe_ctx->stream->signal)) { if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP) - hwss_blacklight_control(link, false); + hwss_edp_backlight_control(link, false); pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); } link->link_enc->funcs->connect_dig_be_to_fe( @@ -908,7 +1044,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); if (link->connector_signal == SIGNAL_TYPE_EDP) - hwss_blacklight_control(link, true); + hwss_edp_backlight_control(link, true); } @@ -2821,7 +2957,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, - .backlight_control = hwss_blacklight_control + .edp_backlight_control = hwss_edp_backlight_control, + .edp_power_control = hwss_edp_power_control, }; void dce110_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 3e95f7f92c73..a1e964af60ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -69,7 +69,11 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); -void hwss_blacklight_control( +void hwss_edp_power_control( + struct link_encoder *enc, + bool power_up); + +void hwss_edp_backlight_control( struct dc_link *link, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 014911ebdbd6..efa3f6f97baf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2903,7 +2903,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, - .backlight_control = hwss_blacklight_control + .edp_backlight_control = hwss_edp_backlight_control, + .edp_power_control = hwss_edp_power_control }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 6cd6bc7d15fb..3d33bcda7059 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -123,8 +123,6 @@ struct link_encoder_funcs { bool exit_link_training_required); void (*psr_program_secondary_packet)(struct link_encoder *enc, unsigned int sdp_transmit_line_num_deadline); - void (*power_control) (struct link_encoder *enc, - bool power_up); void (*connect_dig_be_to_fe)(struct link_encoder *enc, enum engine_id engine, bool connect); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 210874f37722..bf3ab5d7398e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -28,6 +28,7 @@ #include "dc_types.h" #include "clock_source.h" #include "inc/hw/timing_generator.h" +#include "inc/hw/link_encoder.h" #include "core_status.h" enum pipe_gating_control { @@ -176,8 +177,10 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); - - void (*backlight_control)( + void (*edp_power_control)( + struct link_encoder *enc, + bool enable); + void (*edp_backlight_control)( struct dc_link *link, bool enable); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h index f7994cfc850d..f2b8c9a376d5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h @@ -40,6 +40,10 @@ enum dc_status core_link_write_dpcd( const uint8_t *data, uint32_t size); +struct gpio *get_hpd_gpio(struct dc_bios *dcb, + struct graphics_object_id link_id, + struct gpio_service *gpio_service); + void dp_enable_link_phy( struct dc_link *link, enum signal_type signal, diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 4f405348130f..88c2bde3f039 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -73,10 +73,6 @@ static void virtual_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table) {} -static void virtual_link_encoder_edp_power_control( - struct link_encoder *enc, - bool power_up) {} - static void virtual_link_encoder_connect_dig_be_to_fe( struct link_encoder *enc, enum engine_id engine, @@ -102,7 +98,6 @@ static const struct link_encoder_funcs virtual_lnk_enc_funcs = { .dp_set_phy_pattern = virtual_link_encoder_dp_set_phy_pattern, .update_mst_stream_allocation_table = virtual_link_encoder_update_mst_stream_allocation_table, - .power_control = virtual_link_encoder_edp_power_control, .connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe, .destroy = virtual_link_encoder_destroy }; -- cgit v1.2.3-59-g8ed1b From 3eab79163fcb0f7777440dfe360d2eedbbcc47b9 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Tue, 26 Sep 2017 15:35:42 +0530 Subject: drm/amd/display: make FBC configurable option Currently FBC is guarded with ENABLE_FBC macro, which needs to be manually enabled in Makefile. This patch moves it to Kconfig so that there wont be any need to additional patch to be carried for enabling or disabling on every SoC. Signed-off-by: Shirish S Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 10 ++++++++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 4 ++-- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 16 ++++++++-------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 4 ++-- 7 files changed, 25 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 6d1086d0a277..ec3285f65517 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,6 +17,16 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. +config DRM_AMD_DC_FBC + bool "AMD FBC - Enable Frame Buffer Compression" + depends on DRM_AMD_DC + help + Choose this option if you want to use frame buffer compression + support. + This is a power optimisation feature, check its availability + on your hardware before enabling this option. + + config DRM_AMD_DC_DCN1_0 bool "DCN 1.0 Raven family" depends on DRM_AMD_DC && X86 diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3439bc46a4a2..a5c72dbc2dcc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -507,7 +507,7 @@ static bool construct(struct dc *dc, dc_version = resource_parse_asic_id(init_params->asic_id); dc->ctx->dce_version = dc_version; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; #endif /* Resource should construct all asic specific resources. diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index bf83459456a8..adadfad2bd51 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -258,7 +258,7 @@ struct dc { struct dm_pp_display_configuration prev_display_config; /* FBC compressor */ -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) struct compressor *fbc_compressor; #endif }; @@ -293,7 +293,7 @@ struct dc_init_data { struct dc_config flags; uint32_t log_mask; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) uint64_t fbc_gpu_addr; #endif }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 4bd74fc6c782..a8698e399111 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -92,7 +92,7 @@ struct dc_context { bool created_bios; struct gpio_service *gpio_service; struct i2caux *i2caux; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) uint64_t fbc_gpu_addr; #endif }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 3872febb4f6b..6923662413cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -514,7 +514,7 @@ void dce110_compressor_construct(struct dce110_compressor *compressor, compressor->base.lpt_channels_num = 0; compressor->base.attached_inst = 0; compressor->base.is_enabled = false; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) compressor->base.funcs = &dce110_compressor_funcs; #endif diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index a891e387ed7b..247e81806c4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -34,7 +34,7 @@ #include "dce/dce_hwseq.h" #include "gpio_service_interface.h" -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) #include "dce110_compressor.h" #endif @@ -1445,7 +1445,7 @@ static void power_down_all_hw_blocks(struct dc *dc) power_down_clock_sources(dc); -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) if (dc->fbc_compressor) dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); #endif @@ -1618,7 +1618,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, if (events->cursor_update) value |= 0x2; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) value |= 0x84; #endif @@ -1748,7 +1748,7 @@ static void apply_min_clocks( } } -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) /* * Check if FBC can be enabled @@ -1940,7 +1940,7 @@ enum dc_status dce110_apply_ctx_to_hw( set_safe_displaymarks(&context->res_ctx, dc->res_pool); -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) if (dc->fbc_compressor) dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); #endif @@ -2124,7 +2124,7 @@ enum dc_status dce110_apply_ctx_to_hw( dcb->funcs->set_scratch_critical_state(dcb, false); -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) if (dc->fbc_compressor) enable_fbc(dc, context); @@ -2533,7 +2533,7 @@ static void init_hw(struct dc *dc) abm->funcs->init_backlight(abm); abm->funcs->abm_init(abm); } -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) if (dc->fbc_compressor) dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); #endif @@ -2781,7 +2781,7 @@ static void dce110_program_front_end_for_pipe( program_scaler(dc, pipe_ctx); -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) if (dc->fbc_compressor && old_pipe->stream) { if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 8e4ec61d59a4..db96d2b47ff1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -52,7 +52,7 @@ #include "dce/dce_abm.h" #include "dce/dce_dmcu.h" -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) #include "dce110/dce110_compressor.h" #endif @@ -1279,7 +1279,7 @@ static bool construct( } } -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) dc->fbc_compressor = dce110_compressor_create(ctx); -- cgit v1.2.3-59-g8ed1b From 4176664b1fc8aa052f886037590cac4fb0dd8afb Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 27 Sep 2017 23:23:16 -0400 Subject: drm/amd/display: audio dynamic resource acquired related Signed-off-by: Charlene Liu Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 24 ++++++++++++++++------ drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 12 +++++++++-- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 7 ++++++- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++- drivers/gpu/drm/amd/display/dc/inc/resource.h | 5 +++++ 10 files changed, 47 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index e414e4770789..2d59f77fa9a2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -2323,14 +2323,14 @@ void core_link_enable_stream( allocate_mst_payload(pipe_ctx); } -void core_link_disable_stream(struct pipe_ctx *pipe_ctx) +void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) { struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); - core_dc->hwss.disable_stream(pipe_ctx); + core_dc->hwss.disable_stream(pipe_ctx, option); disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 34b6d1cb151e..9a33b471270a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -282,7 +282,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, dp_receiver_power_ctrl(link, false); - link->dc->hwss.disable_stream(&pipes[i]); + link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE); link->link_enc->funcs->disable_output( link->link_enc, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index bbfec7cb2ad1..68c613229a10 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -242,7 +242,10 @@ bool resource_construct( pool->stream_enc_count++; } } - + dc->caps.dynamic_audio = false; + if (pool->audio_count < pool->stream_enc_count) { + dc->caps.dynamic_audio = true; + } for (i = 0; i < num_virtual_links; i++) { pool->stream_enc[pool->stream_enc_count] = virtual_stream_encoder_create( @@ -1330,7 +1333,7 @@ static void update_stream_engine_usage( } /* TODO: release audio object */ -static void update_audio_usage( +void update_audio_usage( struct resource_context *res_ctx, const struct resource_pool *pool, struct audio *audio, @@ -1414,12 +1417,21 @@ static struct audio *find_first_free_audio( const struct resource_pool *pool) { int i; - for (i = 0; i < pool->audio_count; i++) { - if (res_ctx->is_audio_acquired[i] == false) { - return pool->audios[i]; + if (pool->audio_count >= pool->stream_enc_count) { + for (i = 0; i < pool->audio_count; i++) { + if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { + /*we have enough audio endpoint, no need to do dynamic distribution*/ + return pool->audios[i]; + } } - } + } else { /*first come first serve*/ + for (i = 0; i < pool->audio_count; i++) { + if (res_ctx->is_audio_acquired[i] == false) { + return pool->audios[i]; + } + } + } return 0; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index adadfad2bd51..2517fb821fff 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -58,6 +58,7 @@ struct dc_caps { uint32_t i2c_speed_in_khz; unsigned int max_cursor_size; bool dcc_const_color; + bool dynamic_audio; }; struct dc_dcc_surface_param { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 247e81806c4a..453d2ffd5c4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -985,10 +985,11 @@ void hwss_edp_backlight_control( link_transmitter_control(link->dc->ctx->dc_bios, &cntl); } -void dce110_disable_stream(struct pipe_ctx *pipe_ctx) +void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) { struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; + struct dc *dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream_res.audio) { pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); @@ -999,6 +1000,13 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) else pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( pipe_ctx->stream_res.stream_enc); + /*don't free audio if it is from retrain or internal disable stream*/ + if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) { + /*we have to dynamic arbitrate the audio endpoints*/ + pipe_ctx->stream_res.audio = NULL; + /*we free the resource, need reset is_audio_acquired*/ + update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); + } /* TODO: notify audio driver for if audio modes list changed * add audio mode list change flag */ @@ -1871,7 +1879,7 @@ static void dce110_reset_hw_ctx_wrap( pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { struct clock_source *old_clk = pipe_ctx_old->clock_source; - core_link_disable_stream(pipe_ctx_old); + core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { dm_error("DC: failed to blank crtc!\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index a1e964af60ac..4d72bb99be93 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -47,7 +47,7 @@ void dce110_set_displaymarks( void dce110_enable_stream(struct pipe_ctx *pipe_ctx); -void dce110_disable_stream(struct pipe_ctx *pipe_ctx); +void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option); void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 84d9d202d3b5..072c48188b79 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1025,7 +1025,7 @@ static void reset_back_end_for_pipe( * which is used by otg. Move disable_link after disable_crtc */ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) - core_link_disable_stream(pipe_ctx); + core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); /* by upper caller loop, parent pipe: pipe0, will be reset last. * back end share by all pipes and will be disable only when disable diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index ff23f268fe02..5230dddc8617 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -58,6 +58,11 @@ struct link_init_data { TODO: remove it when DC is complete. */ }; +enum { + FREE_ACQUIRED_RESOURCE = 0, + KEEP_ACQUIRED_RESOURCE = 1, +}; + struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); @@ -72,7 +77,7 @@ void core_link_enable_stream( struct dc_state *state, struct pipe_ctx *pipe_ctx); -void core_link_disable_stream(struct pipe_ctx *pipe_ctx); +void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option); void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); /********** DAL Core*********************/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index bf3ab5d7398e..8734689a9245 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -134,7 +134,8 @@ struct hw_sequencer_funcs { void (*enable_stream)(struct pipe_ctx *pipe_ctx); - void (*disable_stream)(struct pipe_ctx *pipe_ctx); + void (*disable_stream)(struct pipe_ctx *pipe_ctx, + int option); void (*unblank_stream)(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 614bb691ab59..5467332faf7b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -164,4 +164,9 @@ bool pipe_need_reprogram( void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth); +void update_audio_usage( + struct resource_context *res_ctx, + const struct resource_pool *pool, + struct audio *audio, + bool acquired); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ -- cgit v1.2.3-59-g8ed1b From d050f8ed14494ea23c6e10b5893010946ef0f78b Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Fri, 29 Sep 2017 16:36:34 -0400 Subject: drm/amd/display: add dpms state to DC - avoid eDP screen flash 4 times when resume from s3 - improve s3 and boot time Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++ drivers/gpu/drm/amd/display/dc/dc.h | 5 +++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++++---- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 +++--- 5 files changed, 58 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 09bab93815a3..d963de753e63 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -332,7 +332,16 @@ static void set_dither_option(struct dc_stream_state *stream, { struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; - struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; + struct pipe_ctx *pipes; + int i; + + for (i = 0; i < MAX_PIPES; i++) { + if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == + stream) { + pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; + break; + } + } memset(¶ms, 0, sizeof(params)); if (!stream) @@ -349,6 +358,31 @@ static void set_dither_option(struct dc_stream_state *stream, opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); } +void set_dpms( + struct dc *dc, + struct dc_stream_state *stream, + bool dpms_off) +{ + struct pipe_ctx *pipe_ctx; + int i; + + for (i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + break; + } + } + + if (stream->dpms_off != dpms_off) { + stream->dpms_off = dpms_off; + if (dpms_off) + core_link_disable_stream(pipe_ctx, + KEEP_ACQUIRED_RESOURCE); + else + core_link_enable_stream(dc->current_state, pipe_ctx); + } +} + static void allocate_dc_stream_funcs(struct dc *dc) { if (dc->hwss.set_drr != NULL) { @@ -371,6 +405,9 @@ static void allocate_dc_stream_funcs(struct dc *dc) dc->stream_funcs.set_dither_option = set_dither_option; + dc->stream_funcs.set_dpms = + set_dpms; + dc->link_funcs.set_drive_settings = set_drive_settings; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 2d59f77fa9a2..72e56fbe4a42 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -2321,6 +2321,10 @@ void core_link_enable_stream( if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) allocate_mst_payload(pipe_ctx); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + core_dc->hwss.unblank_stream(pipe_ctx, + &pipe_ctx->stream->sink->link->cur_link_settings); } void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5a378cc5daaf..7a5e53ffac2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -133,6 +133,10 @@ struct dc_stream_state_funcs { void (*set_dither_option)(struct dc_stream_state *stream, enum dc_dither_option option); + + void (*set_dpms)(struct dc *dc, + struct dc_stream_state *stream, + bool dpms_off); }; struct link_training_settings; @@ -566,6 +570,7 @@ struct dc_stream_state { int phy_pix_clk; enum signal_type signal; + bool dpms_off; struct dc_stream_status status; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 453d2ffd5c4a..81ebf2b9c71d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1364,12 +1364,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( resource_build_info_frame(pipe_ctx); dce110_update_info_frame(pipe_ctx); if (!pipe_ctx_old->stream) { - core_link_enable_stream(context, pipe_ctx); - - - if (dc_is_dp_signal(pipe_ctx->stream->signal)) - dce110_unblank_stream(pipe_ctx, - &stream->sink->link->cur_link_settings); + if (!pipe_ctx->stream->dpms_off) + core_link_enable_stream(context, pipe_ctx); } pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; @@ -1879,7 +1875,10 @@ static void dce110_reset_hw_ctx_wrap( pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { struct clock_source *old_clk = pipe_ctx_old->clock_source; - core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); + /* disable already, no need to disable again */ + if (!pipe_ctx->stream->dpms_off) + core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); + pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { dm_error("DC: failed to blank crtc!\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 012ba7c9ca8d..494f833208f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1037,12 +1037,11 @@ static void reset_back_end_for_pipe( return; } - /* TODOFPGA break core_link_disable_stream into 2 functions: - * disable_stream and disable_link. disable_link will disable PHYPLL - * which is used by otg. Move disable_link after disable_crtc - */ - if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) - core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + /* DPMS may already disable */ + if (!pipe_ctx->stream->dpms_off) + core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); + } /* by upper caller loop, parent pipe: pipe0, will be reset last. * back end share by all pipes and will be disable only when disable -- cgit v1.2.3-59-g8ed1b From 067c878a220cbe6198b3cfdc7f372adab4762ad8 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 3 Oct 2017 15:03:49 -0400 Subject: drm/amd/display: Fixed switching mode half screen gamma incorrect. Half screen gamma setting and cursor are incorrect when switching mode through win+p due to wrong programming gamma sequence (In case of bottom pipe, gamma and cursor are programmed before front end programmed, pipe is power gated). change: 1. Cache curor attributes to stream 2. Move set gamma and cursor inside front end programming. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 15 --------------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 9 ++++++++- drivers/gpu/drm/amd/display/dc/dc.h | 4 +++- .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 10 ++++++++++ .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 +++++++++++++++++ 5 files changed, 38 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d963de753e63..92fab09843e4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1269,10 +1269,6 @@ static void commit_planes_for_stream(struct dc *dc, /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; - bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; - struct dc_cursor_position position = { 0 }; - if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; @@ -1283,17 +1279,6 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.apply_ctx_for_surface( dc, pipe_ctx->stream, stream_status->plane_count, context); } - - /* TODO: this is a hack w/a for switching from mpo to pipe split */ - dc_stream_set_cursor_position(pipe_ctx->stream, &position); - - if (is_new_pipe_surface) { - dc->hwss.update_plane_addr(dc, pipe_ctx); - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); - } } if (update_type > UPDATE_TYPE_FAST) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index c19b478bcdc7..3dd44bef56eb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -173,7 +173,7 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream_state *stream, + struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes) { int i; @@ -189,6 +189,11 @@ bool dc_stream_set_cursor_attributes( return false; } + if (attributes->address.quad_part == 0) { + dm_error("DC: Cursor address is 0!\n"); + return false; + } + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_state->res_ctx; @@ -214,6 +219,8 @@ bool dc_stream_set_cursor_attributes( pipe_ctx->plane_res.xfm, attributes); } + stream->cursor_attributes = *attributes; + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7a5e53ffac2e..c832d5abbbdf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -574,6 +574,8 @@ struct dc_stream_state { struct dc_stream_status status; + struct dc_cursor_attributes cursor_attributes; + /* from stream struct */ struct kref refcount; }; @@ -1013,7 +1015,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); ******************************************************************************/ /* TODO: Deprecated once we switch to dc_set_cursor_position */ bool dc_stream_set_cursor_attributes( - const struct dc_stream_state *stream, + struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 81ebf2b9c71d..bf7318246401 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2725,6 +2725,8 @@ static void dce110_program_front_end_for_pipe( struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; + struct pipe_ctx *cur_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; unsigned int i; memset(&tbl_entry, 0, sizeof(tbl_entry)); @@ -2815,6 +2817,14 @@ static void dce110_program_front_end_for_pipe( &plane_state->tiling_info, plane_state->rotation); + /* Moved programming gamma from dc to hwss */ + if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { + dc->hwss.set_input_transfer_func( + pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func( + pipe_ctx, pipe_ctx->stream); + } + dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe:%d 0x%x: addr hi:0x%x, " "addr low:0x%x, " diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 494f833208f9..ee63155c1895 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2408,6 +2408,10 @@ static void program_all_pipe_in_tree( } if (pipe_ctx->plane_state != NULL) { + struct dc_cursor_position position = { 0 }; + struct pipe_ctx *cur_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + dcn10_power_on_fe(dc, pipe_ctx, context); /* temporary dcn1 wa: @@ -2422,6 +2426,19 @@ static void program_all_pipe_in_tree( toggle_watermark_change_req(dc->hwseq); update_dchubp_dpp(dc, pipe_ctx, context); + + /* TODO: this is a hack w/a for switching from mpo to pipe split */ + dc_stream_set_cursor_position(pipe_ctx->stream, &position); + + dc_stream_set_cursor_attributes(pipe_ctx->stream, + &pipe_ctx->stream->cursor_attributes); + + if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { + dc->hwss.set_input_transfer_func( + pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func( + pipe_ctx, pipe_ctx->stream); + } } if (dc->debug.sanity_checks) { -- cgit v1.2.3-59-g8ed1b From 8feabd03d34e4555c119e69269dae28f52e0d86c Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Mon, 2 Oct 2017 14:39:42 -0400 Subject: drm/amd/display: rename struct mem_input to hubp for dcn Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 22 +-- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 19 +-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 88 ++++++------ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 157 ++++++++++----------- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 49 +++---- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 26 ++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 105 ++++++++++++++ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 3 - 13 files changed, 286 insertions(+), 195 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index fd1db8dc2f35..c37f130b0170 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -485,6 +485,7 @@ static void split_stream_across_pipes( secondary_pipe->pipe_idx = pipe_idx; secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; + secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; if (primary_pipe->bottom_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index fe66c6a21bc3..4df5bf750257 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -47,6 +47,7 @@ #include "dc_link_ddc.h" #include "dm_helpers.h" #include "mem_input.h" +#include "hubp.h" /******************************************************************************* diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7d750369b78b..4fb4f0068f1b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1024,7 +1024,7 @@ static int acquire_first_split_pipe( memset(pipe_ctx, 0, sizeof(*pipe_ctx)); pipe_ctx->stream_res.tg = pool->timing_generators[i]; - pipe_ctx->plane_res.mi = pool->mis[i]; + pipe_ctx->plane_res.hubp = pool->hubps[i]; pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx->stream_res.opp = pool->opps[i]; @@ -1359,6 +1359,7 @@ static int acquire_first_free_pipe( pipe_ctx->stream_res.tg = pool->timing_generators[i]; pipe_ctx->plane_res.mi = pool->mis[i]; + pipe_ctx->plane_res.hubp = pool->hubps[i]; pipe_ctx->plane_res.ipp = pool->ipps[i]; pipe_ctx->plane_res.xfm = pool->transforms[i]; pipe_ctx->stream_res.opp = pool->opps[i]; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 3dd44bef56eb..411678736ed4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -200,7 +200,7 @@ bool dc_stream_set_cursor_attributes( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.mi || !pipe_ctx->plane_res.xfm) + if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.xfm) continue; if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) continue; @@ -210,10 +210,15 @@ bool dc_stream_set_cursor_attributes( pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( pipe_ctx->plane_res.ipp, attributes); - if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL) + if (pipe_ctx->plane_res.hubp != NULL) + pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( + pipe_ctx->plane_res.hubp, attributes); + + if (pipe_ctx->plane_res.mi != NULL) pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( pipe_ctx->plane_res.mi, attributes); + if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL) pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( pipe_ctx->plane_res.xfm, attributes); @@ -248,7 +253,7 @@ bool dc_stream_set_cursor_position( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; - struct mem_input *mi = pipe_ctx->plane_res.mi; + struct hubp *hubp = pipe_ctx->plane_res.hubp; struct transform *xfm = pipe_ctx->plane_res.xfm; struct dc_cursor_position pos_cpy = *position; struct dc_cursor_mi_param param = { @@ -260,7 +265,7 @@ bool dc_stream_set_cursor_position( }; if (pipe_ctx->stream != stream || - !pipe_ctx->plane_res.mi || + (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || !pipe_ctx->plane_state || !pipe_ctx->plane_res.xfm) continue; @@ -276,11 +281,12 @@ bool dc_stream_set_cursor_position( if (ipp->funcs->ipp_cursor_set_position != NULL) ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); - if (mi->funcs->set_cursor_attributes != NULL) - mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); + if (hubp != NULL) + hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); + + if (xfm != NULL) + xfm->funcs->set_cursor_position(xfm, &pos_cpy, ¶m, hubp->curs_attr.width); - if (xfm->funcs->set_cursor_attributes != NULL) - xfm->funcs->set_cursor_position(xfm, &pos_cpy, ¶m, mi->curs_attr.width); } return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 83d9caa4f438..ed301c3b2736 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -685,9 +685,6 @@ void dce_mem_input_construct( dce_mi->regs = regs; dce_mi->shifts = mi_shift; dce_mi->masks = mi_mask; - - dce_mi->base.mpcc_id = 0xf; - dce_mi->base.opp_id = 0xf; } void dce112_mem_input_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index bf7318246401..867a0eb9f2e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1378,15 +1378,14 @@ static enum dc_status apply_single_controller_ctx_to_hw( } /* mst support - use total stream count */ -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (pipe_ctx->plane_res.mi->funcs->allocate_mem_input != NULL) -#endif + if (pipe_ctx->plane_res.mi != NULL) { pipe_ctx->plane_res.mi->funcs->allocate_mem_input( - pipe_ctx->plane_res.mi, - stream->timing.h_total, - stream->timing.v_total, - stream->timing.pix_clk_khz, - context->stream_count); + pipe_ctx->plane_res.mi, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, + context->stream_count); + } pipe_ctx->stream->sink->link->psr_enabled = false; @@ -1556,7 +1555,7 @@ static void set_safe_displaymarks( SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; for (i = 0; i < MAX_PIPES; i++) { - if (res_ctx->pipe_ctx[i].stream == NULL) + if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) continue; res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( @@ -1565,6 +1564,7 @@ static void set_safe_displaymarks( max_marks, max_marks, MAX_WATERMARK); + if (i == underlay_idx) res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( res_ctx->pipe_ctx[i].plane_res.mi, @@ -1572,6 +1572,7 @@ static void set_safe_displaymarks( max_marks, max_marks, MAX_WATERMARK); + } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ee63155c1895..c34dbcd1fba4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -172,10 +172,10 @@ static void dcn10_log_hw_state(struct dc *dc) "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n"); for (i = 0; i < pool->pipe_count; i++) { - struct mem_input *mi = pool->mis[i]; + struct hubp *hubp = pool->hubps[i]; struct dcn_hubp_state s; - dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s); + hubp1_read_state(TO_DCN10_HUBP(hubp), &s); DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t " "%xh \t %xh \t %xh \t " @@ -803,7 +803,7 @@ static void power_on_plane( static void undo_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; - struct mem_input *mi = dc->res_pool->mis[0]; + struct hubp *hubp = dc->res_pool->hubps[0]; int pwr_status = 0; REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status); @@ -811,7 +811,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) if (pwr_status == 2) return; - mi->funcs->set_blank(mi, true); + hubp->funcs->set_blank(hubp, true); REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); @@ -824,7 +824,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; - struct mem_input *mi = dc->res_pool->mis[0]; + struct hubp *hubp = dc->res_pool->hubps[0]; if (dc->debug.disable_stutter) return; @@ -836,7 +836,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); - mi->funcs->set_hubp_blank_en(mi, false); + hubp->funcs->set_hubp_blank_en(hubp, false); } static void bios_golden_init(struct dc *dc) @@ -1070,7 +1070,7 @@ static void reset_back_end_for_pipe( static void plane_atomic_disconnect(struct dc *dc, int fe_idx) { - struct mem_input *mi = dc->res_pool->mis[fe_idx]; + struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id, z_idx; int mpcc_id = -1; @@ -1094,7 +1094,7 @@ static void plane_atomic_disconnect(struct dc *dc, if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); - mi->funcs->dcc_control(mi, false, false); + hubp->funcs->dcc_control(hubp, false, false); if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); @@ -1108,20 +1108,20 @@ static void plane_atomic_disable(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; - struct mem_input *mi = dc->res_pool->mis[fe_idx]; + struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; - int opp_id = mi->opp_id; + int opp_id = hubp->opp_id; if (opp_id == 0xf) return; - mpc->funcs->wait_for_idle(mpc, mi->mpcc_id); - dc->res_pool->opps[mi->opp_id]->mpcc_disconnect_pending[mi->mpcc_id] = false; + mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); + dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, "[debug_mpo: atomic disable finished on mpcc %d]\n", fe_idx);*/ - mi->funcs->set_blank(mi, true); + hubp->funcs->set_blank(hubp, true); if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); @@ -1171,7 +1171,7 @@ static void reset_front_end( { struct dce_hwseq *hws = dc->hwseq; struct timing_generator *tg; - int opp_id = dc->res_pool->mis[fe_idx]->opp_id; + int opp_id = dc->res_pool->hubps[fe_idx]->opp_id; /*Already reset*/ if (opp_id == 0xf) @@ -1353,8 +1353,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c if (plane_state == NULL) return; addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); - pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( - pipe_ctx->plane_res.mi, + pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( + pipe_ctx->plane_res.hubp, &plane_state->address, plane_state->flip_immediate); plane_state->status.requested_address = plane_state->address; @@ -1759,8 +1759,8 @@ static void dcn10_pipe_control_lock( struct pipe_ctx *pipe, bool lock) { - struct mem_input *mi = NULL; - mi = dc->res_pool->mis[pipe->pipe_idx]; + struct hubp *hubp = NULL; + hubp = dc->res_pool->hubps[pipe->pipe_idx]; /* use TG master update lock to lock everything on the TG * therefore only top pipe need to lock */ @@ -2181,7 +2181,7 @@ static void dcn10_get_surface_visual_confirm_color( } } -static void mmhub_read_vm_system_aperture_settings(struct dcn10_mem_input *mi, +static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, struct vm_system_aperture_param *apt, struct dce_hwseq *hws) { @@ -2206,7 +2206,7 @@ static void mmhub_read_vm_system_aperture_settings(struct dcn10_mem_input *mi, } /* Temporary read settings, future will get values from kmd directly */ -static void mmhub_read_vm_context0_settings(struct dcn10_mem_input *mi, +static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, struct vm_context0_param *vm0, struct dce_hwseq *hws) { @@ -2250,22 +2250,22 @@ static void mmhub_read_vm_context0_settings(struct dcn10_mem_input *mi, vm0->pte_base.quad_part -= fb_offset.quad_part; } -static void dcn10_program_pte_vm(struct mem_input *mem_input, +static void dcn10_program_pte_vm(struct hubp *hubp, enum surface_pixel_format format, union dc_tiling_info *tiling_info, enum dc_rotation_angle rotation, struct dce_hwseq *hws) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); struct vm_system_aperture_param apt = { {{ 0 } } }; struct vm_context0_param vm0 = { { { 0 } } }; - mmhub_read_vm_system_aperture_settings(mi, &apt, hws); - mmhub_read_vm_context0_settings(mi, &vm0, hws); + mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws); + mmhub_read_vm_context0_settings(hubp1, &vm0, hws); - mem_input->funcs->mem_input_set_vm_system_aperture_settings(mem_input, &apt); - mem_input->funcs->mem_input_set_vm_context0_settings(mem_input, &vm0); + hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); + hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0); } static void update_dchubp_dpp( @@ -2274,7 +2274,7 @@ static void update_dchubp_dpp( struct dc_state *context) { struct dce_hwseq *hws = dc->hwseq; - struct mem_input *mi = pipe_ctx->plane_res.mi; + struct hubp *hubp = pipe_ctx->plane_res.hubp; struct transform *xfm = pipe_ctx->plane_res.xfm; struct dc_plane_state *plane_state = pipe_ctx->plane_state; union plane_size size = plane_state->plane_size; @@ -2299,8 +2299,8 @@ static void update_dchubp_dpp( */ REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); - mi->funcs->mem_input_setup( - mi, + hubp->funcs->hubp_setup( + hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, @@ -2310,7 +2310,7 @@ static void update_dchubp_dpp( if (dc->config.gpu_vm_support) dcn10_program_pte_vm( - pipe_ctx->plane_res.mi, + pipe_ctx->plane_res.hubp, plane_state->format, &plane_state->tiling_info, plane_state->rotation, @@ -2321,7 +2321,7 @@ static void update_dchubp_dpp( plane_state->format, EXPANSION_MODE_ZERO); - mpcc_cfg.dpp_id = mi->inst; + mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree); for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) @@ -2340,15 +2340,15 @@ static void update_dchubp_dpp( mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace( pipe_ctx->stream->output_color_space) && per_pixel_alpha; - mi->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg); - mi->opp_id = mpcc_cfg.opp_id; + hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg); + hubp->opp_id = mpcc_cfg.opp_id; pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; /* scaler configuration */ pipe_ctx->plane_res.xfm->funcs->transform_set_scaler( pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data); - mi->funcs->mem_program_viewport(mi, + hubp->funcs->mem_program_viewport(hubp, &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); /*gamut remap*/ @@ -2358,8 +2358,8 @@ static void update_dchubp_dpp( pipe_ctx->stream->output_color_space, pipe_ctx->stream->csc_color_matrix.matrix); - mi->funcs->mem_input_program_surface_config( - mi, + hubp->funcs->hubp_program_surface_config( + hubp, plane_state->format, &plane_state->tiling_info, &size, @@ -2370,7 +2370,7 @@ static void update_dchubp_dpp( dc->hwss.update_plane_addr(dc, pipe_ctx); if (is_pipe_tree_visible(pipe_ctx)) - mi->funcs->set_blank(mi, false); + hubp->funcs->set_blank(hubp, false); } @@ -2550,7 +2550,7 @@ static void dcn10_apply_ctx_for_surface( */ if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { - if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) { + if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) { dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); /* * power down fe will unlock when calling reset, need @@ -2577,7 +2577,7 @@ static void dcn10_apply_ctx_for_surface( &(old_pipe_ctx->stream_res.opp->mpc_tree), old_pipe_ctx->stream_res.opp->inst, old_pipe_ctx->pipe_idx); - old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true; + old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", @@ -2861,7 +2861,7 @@ static void dcn10_wait_for_mpcc_disconnect( if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) { res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i); pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false; - res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true); + res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true); /*dm_logger_write(dc->ctx->logger, LOG_ERROR, "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n", i);*/ @@ -2892,11 +2892,11 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) return; plane_state->status.is_flip_pending = - pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( - pipe_ctx->plane_res.mi); + pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending( + pipe_ctx->plane_res.hubp); - plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; - if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && + plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address; + if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && tg->funcs->is_stereo_left_eye) { plane_state->status.is_right_eye = !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index 2336da54000c..9ee42d9840fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -29,18 +29,18 @@ #include "basics/conversion.h" #define REG(reg)\ - mi->mi_regs->reg + hubp1->mi_regs->reg #define CTX \ - mi->base.ctx + hubp1->base.ctx #undef FN #define FN(reg_name, field_name) \ - mi->mi_shift->field_name, mi->mi_mask->field_name + hubp1->mi_shift->field_name, hubp1->mi_mask->field_name -void hubp1_set_blank(struct mem_input *mem_input, bool blank) +void hubp1_set_blank(struct hubp *hubp, bool blank) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; REG_UPDATE_2(DCHUBP_CNTL, @@ -51,24 +51,24 @@ void hubp1_set_blank(struct mem_input *mem_input, bool blank) REG_WAIT(DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, 1, 1, 200); - mem_input->mpcc_id = 0xf; - mem_input->opp_id = 0xf; + hubp->mpcc_id = 0xf; + hubp->opp_id = 0xf; } } -static void hubp1_set_hubp_blank_en(struct mem_input *mem_input, bool blank) +static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); } -static void hubp1_vready_workaround(struct mem_input *mem_input, +static void hubp1_vready_workaround(struct hubp *hubp, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) { uint32_t value = 0; - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); /* set HBUBREQ_DEBUG_DB[12] = 1 */ value = REG_READ(HUBPREQ_DEBUG_DB); @@ -88,7 +88,7 @@ static void hubp1_vready_workaround(struct mem_input *mem_input, } void hubp1_program_tiling( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp1, const union dc_tiling_info *info, const enum surface_pixel_format pixel_format) { @@ -108,7 +108,7 @@ void hubp1_program_tiling( } void hubp1_program_size_and_rotation( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp1, enum dc_rotation_angle rotation, enum surface_pixel_format format, const union plane_size *plane_size, @@ -170,7 +170,7 @@ void hubp1_program_size_and_rotation( } void hubp1_program_pixel_format( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp1, enum surface_pixel_format format) { uint32_t red_bar = 3; @@ -246,11 +246,11 @@ void hubp1_program_pixel_format( } bool hubp1_program_surface_flip_and_addr( - struct mem_input *mem_input, + struct hubp *hubp, const struct dc_plane_address *address, bool flip_immediate) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); /* program flip type */ REG_SET(DCSURF_FLIP_CONTROL, 0, @@ -387,20 +387,20 @@ bool hubp1_program_surface_flip_and_addr( break; } - mem_input->request_address = *address; + hubp->request_address = *address; if (flip_immediate) - mem_input->current_address = *address; + hubp->current_address = *address; return true; } -void hubp1_dcc_control(struct mem_input *mem_input, bool enable, +void hubp1_dcc_control(struct hubp *hubp, bool enable, bool independent_64b_blks) { uint32_t dcc_en = enable ? 1 : 0; uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); REG_UPDATE_2(DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, dcc_en, @@ -408,7 +408,7 @@ void hubp1_dcc_control(struct mem_input *mem_input, bool enable, } void hubp1_program_surface_config( - struct mem_input *mem_input, + struct hubp *hubp, enum surface_pixel_format format, union dc_tiling_info *tiling_info, union plane_size *plane_size, @@ -416,20 +416,20 @@ void hubp1_program_surface_config( struct dc_plane_dcc_param *dcc, bool horizontal_mirror) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - hubp1_dcc_control(mem_input, dcc->enable, dcc->grph.independent_64b_blks); - hubp1_program_tiling(mi, tiling_info, format); + hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); + hubp1_program_tiling(hubp1, tiling_info, format); hubp1_program_size_and_rotation( - mi, rotation, format, plane_size, dcc, horizontal_mirror); - hubp1_program_pixel_format(mi, format); + hubp1, rotation, format, plane_size, dcc, horizontal_mirror); + hubp1_program_pixel_format(hubp1, format); } void hubp1_program_requestor( - struct mem_input *mem_input, + struct hubp *hubp, struct _vcs_dpi_display_rq_regs_st *rq_regs) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); REG_UPDATE(HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); @@ -460,11 +460,11 @@ void hubp1_program_requestor( void hubp1_program_deadline( - struct mem_input *mem_input, + struct hubp *hubp, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, struct _vcs_dpi_display_ttu_regs_st *ttu_attr) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); /* DLG - Per hubp */ REG_SET_2(BLANK_OFFSET_0, 0, @@ -581,7 +581,7 @@ void hubp1_program_deadline( } static void hubp1_setup( - struct mem_input *mem_input, + struct hubp *hubp, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, struct _vcs_dpi_display_ttu_regs_st *ttu_attr, struct _vcs_dpi_display_rq_regs_st *rq_regs, @@ -590,27 +590,15 @@ static void hubp1_setup( /* otg is locked when this func is called. Register are double buffered. * disable the requestors is not needed */ - hubp1_program_requestor(mem_input, rq_regs); - hubp1_program_deadline(mem_input, dlg_attr, ttu_attr); - hubp1_vready_workaround(mem_input, pipe_dest); + hubp1_program_requestor(hubp, rq_regs); + hubp1_program_deadline(hubp, dlg_attr, ttu_attr); + hubp1_vready_workaround(hubp, pipe_dest); } -void hubp1_program_display_marks( - struct mem_input *mem_input, - struct dce_watermarks nbp, - struct dce_watermarks stutter, - struct dce_watermarks urgent, - uint32_t total_dest_line_time_ns) -{ - /* only for dce - * dcn use only program_watermarks - */ -} - -bool hubp1_is_flip_pending(struct mem_input *mem_input) +bool hubp1_is_flip_pending(struct hubp *hubp) { uint32_t flip_pending = 0; - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); struct dc_plane_address earliest_inuse_address; REG_GET(DCSURF_FLIP_CONTROL, @@ -625,20 +613,20 @@ bool hubp1_is_flip_pending(struct mem_input *mem_input) if (flip_pending) return true; - if (earliest_inuse_address.grph.addr.quad_part != mem_input->request_address.grph.addr.quad_part) + if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) return true; - mem_input->current_address = mem_input->request_address; + hubp->current_address = hubp->request_address; return false; } uint32_t aperture_default_system = 1; uint32_t context0_default_system; /* = 0;*/ -static void hubp1_set_vm_system_aperture_settings(struct mem_input *mem_input, +static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, struct vm_system_aperture_param *apt) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); PHYSICAL_ADDRESS_LOC mc_vm_apt_default; PHYSICAL_ADDRESS_LOC mc_vm_apt_low; PHYSICAL_ADDRESS_LOC mc_vm_apt_high; @@ -664,10 +652,10 @@ static void hubp1_set_vm_system_aperture_settings(struct mem_input *mem_input, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); } -static void hubp1_set_vm_context0_settings(struct mem_input *mem_input, +static void hubp1_set_vm_context0_settings(struct hubp *hubp, const struct vm_context0_param *vm0) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); /* pte base */ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); @@ -700,11 +688,11 @@ static void hubp1_set_vm_context0_settings(struct mem_input *mem_input, } void min_set_viewport( - struct mem_input *mem_input, + struct hubp *hubp, const struct rect *viewport, const struct rect *viewport_c) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, PRI_VIEWPORT_WIDTH, viewport->width, @@ -733,7 +721,7 @@ void min_set_viewport( PRI_VIEWPORT_Y_START_C, viewport_c->y); } -void dcn10_mem_input_read_state(struct dcn10_mem_input *mi, +void hubp1_read_state(struct dcn10_hubp *hubp1, struct dcn_hubp_state *s) { REG_GET(DCSURF_SURFACE_CONFIG, @@ -783,7 +771,7 @@ enum cursor_lines_per_chunk { }; static bool ippn10_cursor_program_control( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp1, bool pixel_data_invert, enum dc_cursor_color_format color_format) { @@ -849,15 +837,15 @@ static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk( } void hubp1_cursor_set_attributes( - struct mem_input *mem_input, + struct hubp *hubp, const struct dc_cursor_attributes *attr) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); enum cursor_pitch hw_pitch = ippn10_get_cursor_pitch(attr->pitch); enum cursor_lines_per_chunk lpc = ippn10_get_lines_per_chunk( attr->width, attr->color_format); - mem_input->curs_attr = *attr; + hubp->curs_attr = *attr; REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); @@ -871,17 +859,17 @@ void hubp1_cursor_set_attributes( CURSOR_MODE, attr->color_format, CURSOR_PITCH, hw_pitch, CURSOR_LINES_PER_CHUNK, lpc); - ippn10_cursor_program_control(mi, + ippn10_cursor_program_control(hubp1, attr->attribute_flags.bits.INVERT_PIXEL_DATA, attr->color_format); } void hubp1_cursor_set_position( - struct mem_input *mem_input, + struct hubp *hubp, const struct dc_cursor_position *pos, const struct dc_cursor_mi_param *param) { - struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start; uint32_t cur_en = pos->enable ? 1 : 0; uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; @@ -893,7 +881,7 @@ void hubp1_cursor_set_position( * TODO: Look at combining cursor_set_position() and * cursor_set_attributes() into cursor_update() */ - if (mem_input->curs_attr.address.quad_part == 0) + if (hubp->curs_attr.address.quad_part == 0) return; dst_x_offset *= param->ref_clk_khz; @@ -909,11 +897,11 @@ void hubp1_cursor_set_position( if (src_x_offset >= (int)param->viewport_width) cur_en = 0; /* not visible beyond right edge*/ - if (src_x_offset + (int)mem_input->curs_attr.width < 0) + if (src_x_offset + (int)hubp->curs_attr.width < 0) cur_en = 0; /* not visible beyond left edge*/ if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) - hubp1_cursor_set_attributes(mem_input, &mem_input->curs_attr); + hubp1_cursor_set_attributes(hubp, &hubp->curs_attr); REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, cur_en); @@ -930,16 +918,15 @@ void hubp1_cursor_set_position( /* TODO Handle surface pixel formats other than 4:4:4 */ } -static struct mem_input_funcs dcn10_mem_input_funcs = { - .mem_input_program_display_marks = hubp1_program_display_marks, - .mem_input_program_surface_flip_and_addr = +static struct hubp_funcs dcn10_hubp_funcs = { + .hubp_program_surface_flip_and_addr = hubp1_program_surface_flip_and_addr, - .mem_input_program_surface_config = + .hubp_program_surface_config = hubp1_program_surface_config, - .mem_input_is_flip_pending = hubp1_is_flip_pending, - .mem_input_setup = hubp1_setup, - .mem_input_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, - .mem_input_set_vm_context0_settings = hubp1_set_vm_context0_settings, + .hubp_is_flip_pending = hubp1_is_flip_pending, + .hubp_setup = hubp1_setup, + .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, + .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, .set_blank = hubp1_set_blank, .dcc_control = hubp1_dcc_control, .mem_program_viewport = min_set_viewport, @@ -952,22 +939,22 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { /* Constructor, Destructor */ /*****************************************/ -void dcn10_mem_input_construct( - struct dcn10_mem_input *mi, +void dcn10_hubp_construct( + struct dcn10_hubp *hubp1, struct dc_context *ctx, uint32_t inst, const struct dcn_mi_registers *mi_regs, const struct dcn_mi_shift *mi_shift, const struct dcn_mi_mask *mi_mask) { - mi->base.funcs = &dcn10_mem_input_funcs; - mi->base.ctx = ctx; - mi->mi_regs = mi_regs; - mi->mi_shift = mi_shift; - mi->mi_mask = mi_mask; - mi->base.inst = inst; - mi->base.opp_id = 0xf; - mi->base.mpcc_id = 0xf; + hubp1->base.funcs = &dcn10_hubp_funcs; + hubp1->base.ctx = ctx; + hubp1->mi_regs = mi_regs; + hubp1->mi_shift = mi_shift; + hubp1->mi_mask = mi_mask; + hubp1->base.inst = inst; + hubp1->base.opp_id = 0xf; + hubp1->base.mpcc_id = 0xf; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h index 5c5eed5c95d5..66db453c801b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h @@ -25,10 +25,10 @@ #ifndef __DC_MEM_INPUT_DCN10_H__ #define __DC_MEM_INPUT_DCN10_H__ -#include "mem_input.h" +#include "hubp.h" -#define TO_DCN10_MEM_INPUT(mi)\ - container_of(mi, struct dcn10_mem_input, base) +#define TO_DCN10_HUBP(hubp)\ + container_of(hubp, struct dcn10_hubp, base) #define MI_REG_LIST_DCN(id)\ SRI(DCHUBP_CNTL, HUBP, id),\ @@ -584,15 +584,15 @@ struct dcn_mi_mask { DCN_MI_REG_FIELD_LIST(uint32_t); }; -struct dcn10_mem_input { - struct mem_input base; +struct dcn10_hubp { + struct hubp base; const struct dcn_mi_registers *mi_regs; const struct dcn_mi_shift *mi_shift; const struct dcn_mi_mask *mi_mask; }; void hubp1_program_surface_config( - struct mem_input *mem_input, + struct hubp *hubp, enum surface_pixel_format format, union dc_tiling_info *tiling_info, union plane_size *plane_size, @@ -601,20 +601,20 @@ void hubp1_program_surface_config( bool horizontal_mirror); void hubp1_program_deadline( - struct mem_input *mem_input, + struct hubp *hubp, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, struct _vcs_dpi_display_ttu_regs_st *ttu_attr); void hubp1_program_requestor( - struct mem_input *mem_input, + struct hubp *hubp, struct _vcs_dpi_display_rq_regs_st *rq_regs); void hubp1_program_pixel_format( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp, enum surface_pixel_format format); void hubp1_program_size_and_rotation( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp, enum dc_rotation_angle rotation, enum surface_pixel_format format, const union plane_size *plane_size, @@ -622,45 +622,38 @@ void hubp1_program_size_and_rotation( bool horizontal_mirror); void hubp1_program_tiling( - struct dcn10_mem_input *mi, + struct dcn10_hubp *hubp, const union dc_tiling_info *info, const enum surface_pixel_format pixel_format); -void hubp1_dcc_control(struct mem_input *mem_input, +void hubp1_dcc_control(struct hubp *hubp, bool enable, bool independent_64b_blks); -void hubp1_program_display_marks( - struct mem_input *mem_input, - struct dce_watermarks nbp, - struct dce_watermarks stutter, - struct dce_watermarks urgent, - uint32_t total_dest_line_time_ns); - bool hubp1_program_surface_flip_and_addr( - struct mem_input *mem_input, + struct hubp *hubp, const struct dc_plane_address *address, bool flip_immediate); -bool hubp1_is_flip_pending(struct mem_input *mem_input); +bool hubp1_is_flip_pending(struct hubp *hubp); void hubp1_cursor_set_attributes( - struct mem_input *mem_input, + struct hubp *hubp, const struct dc_cursor_attributes *attr); void hubp1_cursor_set_position( - struct mem_input *mem_input, + struct hubp *hubp, const struct dc_cursor_position *pos, const struct dc_cursor_mi_param *param); -void hubp1_set_blank(struct mem_input *mem_input, bool blank); +void hubp1_set_blank(struct hubp *hubp, bool blank); -void min_set_viewport(struct mem_input *mem_input, +void min_set_viewport(struct hubp *hubp, const struct rect *viewport, const struct rect *viewport_c); -void dcn10_mem_input_construct( - struct dcn10_mem_input *mi, +void dcn10_hubp_construct( + struct dcn10_hubp *hubp1, struct dc_context *ctx, uint32_t inst, const struct dcn_mi_registers *mi_regs, @@ -684,7 +677,7 @@ struct dcn_hubp_state { uint32_t qos_level_low_wm; uint32_t qos_level_high_wm; }; -void dcn10_mem_input_read_state(struct dcn10_mem_input *mi, +void hubp1_read_state(struct dcn10_hubp *hubp1, struct dcn_hubp_state *s); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 2caad73257e0..93edbba762e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -704,9 +704,9 @@ static void destruct(struct dcn10_resource_pool *pool) if (pool->base.ipps[i] != NULL) pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); - if (pool->base.mis[i] != NULL) { - kfree(TO_DCN10_MEM_INPUT(pool->base.mis[i])); - pool->base.mis[i] = NULL; + if (pool->base.hubps[i] != NULL) { + kfree(TO_DCN10_HUBP(pool->base.hubps[i])); + pool->base.hubps[i] = NULL; } if (pool->base.irqs != NULL) { @@ -753,19 +753,19 @@ static void destruct(struct dcn10_resource_pool *pool) kfree(pool->base.pp_smu); } -static struct mem_input *dcn10_mem_input_create( +static struct hubp *dcn10_hubp_create( struct dc_context *ctx, uint32_t inst) { - struct dcn10_mem_input *mem_inputn10 = - kzalloc(sizeof(struct dcn10_mem_input), GFP_KERNEL); + struct dcn10_hubp *hubp1 = + kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); - if (!mem_inputn10) + if (!hubp1) return NULL; - dcn10_mem_input_construct(mem_inputn10, ctx, inst, - &mi_regs[inst], &mi_shift, &mi_mask); - return &mem_inputn10->base; + dcn10_hubp_construct(hubp1, ctx, inst, + &mi_regs[inst], &mi_shift, &mi_mask); + return &hubp1->base; } static void get_pixel_clock_parameters( @@ -918,7 +918,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( idle_pipe->stream_res.tg = head_pipe->stream_res.tg; idle_pipe->stream_res.opp = head_pipe->stream_res.opp; - idle_pipe->plane_res.mi = pool->mis[idle_pipe->pipe_idx]; + idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; idle_pipe->plane_res.xfm = pool->transforms[idle_pipe->pipe_idx]; @@ -1357,8 +1357,8 @@ static bool construct( if ((pipe_fuses & (1 << i)) != 0) continue; - pool->base.mis[j] = dcn10_mem_input_create(ctx, i); - if (pool->base.mis[j] == NULL) { + pool->base.hubps[j] = dcn10_hubp_create(ctx, i); + if (pool->base.hubps[j] == NULL) { BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create memory input!\n"); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 118122d12e2b..45518c05e846 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -32,6 +32,7 @@ #include "ddc_service_types.h" #include "dc_bios_types.h" #include "mem_input.h" +#include "hubp.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mpc.h" #endif @@ -129,6 +130,7 @@ struct audio_support{ struct resource_pool { struct mem_input *mis[MAX_PIPES]; + struct hubp *hubps[MAX_PIPES]; struct input_pixel_processor *ipps[MAX_PIPES]; struct transform *transforms[MAX_PIPES]; struct output_pixel_processor *opps[MAX_PIPES]; @@ -178,7 +180,7 @@ struct stream_resource { struct plane_resource { struct scaler_data scl_data; - + struct hubp *hubp; struct mem_input *mi; struct input_pixel_processor *ipp; struct transform *xfm; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h new file mode 100644 index 000000000000..0d186be24cf4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -0,0 +1,105 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HUBP_H__ +#define __DAL_HUBP_H__ + +#include "mem_input.h" + +struct hubp { + struct hubp_funcs *funcs; + struct dc_context *ctx; + struct dc_plane_address request_address; + struct dc_plane_address current_address; + int inst; + int opp_id; + int mpcc_id; + struct dc_cursor_attributes curs_attr; +}; + + +struct hubp_funcs { + void (*hubp_setup)( + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*dcc_control)(struct hubp *hubp, bool enable, + bool independent_64b_blks); + void (*mem_program_viewport)( + struct hubp *hubp, + const struct rect *viewport, + const struct rect *viewport_c); + + bool (*hubp_program_surface_flip_and_addr)( + struct hubp *hubp, + const struct dc_plane_address *address, + bool flip_immediate); + + void (*hubp_program_pte_vm)( + struct hubp *hubp, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + + void (*hubp_set_vm_system_aperture_settings)( + struct hubp *hubp, + struct vm_system_aperture_param *apt); + + void (*hubp_set_vm_context0_settings)( + struct hubp *hubp, + const struct vm_context0_param *vm0); + + void (*hubp_program_surface_config)( + struct hubp *hubp, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + union plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror); + + bool (*hubp_is_flip_pending)(struct hubp *hubp); + + void (*hubp_update_dchub)(struct hubp *hubp, + struct dchub_init_data *dh_data); + + void (*set_blank)(struct hubp *hubp, bool blank); + void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); + + void (*set_cursor_attributes)( + struct hubp *hubp, + const struct dc_cursor_attributes *attr); + + void (*set_cursor_position)( + struct hubp *hubp, + const struct dc_cursor_position *pos, + const struct dc_cursor_mi_param *param); + +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 5c8e45ba8f45..3e1e7e6a8792 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -69,10 +69,7 @@ struct mem_input { struct dc_plane_address request_address; struct dc_plane_address current_address; int inst; - int opp_id; - int mpcc_id; struct stutter_modes stutter_mode; - struct dc_cursor_attributes curs_attr; }; struct vm_system_aperture_param { -- cgit v1.2.3-59-g8ed1b From e6f4f9cfde0f586c276190f541ecfc80d9b688bc Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Thu, 5 Oct 2017 16:00:29 -0400 Subject: drm/amd/display: fix null dereference in reset hw ctx Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 867a0eb9f2e0..5e5763c0ee94 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1877,7 +1877,7 @@ static void dce110_reset_hw_ctx_wrap( struct clock_source *old_clk = pipe_ctx_old->clock_source; /* disable already, no need to disable again */ - if (!pipe_ctx->stream->dpms_off) + if (pipe_ctx->stream && !pipe_ctx->stream->dpms_off) core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); -- cgit v1.2.3-59-g8ed1b From b9b171fffc9358be9e98cbc2bc7ef3fbe029f170 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Tue, 10 Oct 2017 16:28:02 -0400 Subject: drm/amd/display: LGD panel willl flash line under window Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5e5763c0ee94..e8b8daeeed97 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1399,6 +1399,15 @@ static void power_down_encoders(struct dc *dc) int i; enum connector_id connector_id; enum signal_type signal = SIGNAL_TYPE_NONE; + + /* do not know BIOS back-front mapping, simply blank all. It will not + * hurt for non-DP + */ + for (i = 0; i < dc->res_pool->stream_enc_count; i++) { + dc->res_pool->stream_enc[i]->funcs->dp_blank( + dc->res_pool->stream_enc[i]); + } + for (i = 0; i < dc->link_count; i++) { connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || -- cgit v1.2.3-59-g8ed1b From 9b38bd1b8f5c874c3d1f330e0dcf4e7d84137477 Mon Sep 17 00:00:00 2001 From: "Jerry (Fangzhi) Zuo" Date: Fri, 20 Oct 2017 16:45:53 -0400 Subject: drm/amd/display:: Fix NULL pointer in Raven hotplug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Programming sequence to frontend and backend has been switched. In such case, program_scaler() is getting called when programming frontend, and should be removed from backend programming routine. Reviewed-by: Harry Wentland Signed-off-by: Jerry (Fangzhi) Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e8b8daeeed97..2a6d3ca12954 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1369,13 +1369,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( } pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; - /* program_scaler and allocate_mem_input are not new asic */ - if ((!pipe_ctx_old || - memcmp(&pipe_ctx_old->plane_res.scl_data, &pipe_ctx->plane_res.scl_data, - sizeof(struct scaler_data)) != 0) && - pipe_ctx->plane_state) { - program_scaler(dc, pipe_ctx); - } /* mst support - use total stream count */ if (pipe_ctx->plane_res.mi != NULL) { -- cgit v1.2.3-59-g8ed1b From 3b21b6d239f43c0d797bf0deb8c0f8c846862eb1 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Tue, 17 Oct 2017 15:36:13 -0400 Subject: drm/amd/display: Fix no display on Fiji MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allocate memory for the second pipe allocate_mem_input() needs to be done prior to program pipe front end. It shows sensitive to Fiji. Failure to do so will cause error in allocate memory  allocate_mem_input() on the second connected display. Signed-off-by: Jerry Zuo Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2a6d3ca12954..399a5984ada3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1370,16 +1370,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; - /* mst support - use total stream count */ - if (pipe_ctx->plane_res.mi != NULL) { - pipe_ctx->plane_res.mi->funcs->allocate_mem_input( - pipe_ctx->plane_res.mi, - stream->timing.h_total, - stream->timing.v_total, - stream->timing.pix_clk_khz, - context->stream_count); - } - pipe_ctx->stream->sink->link->psr_enabled = false; return DC_OK; @@ -2891,6 +2881,15 @@ static void dce110_apply_ctx_for_surface( if (pipe_ctx->stream != stream) continue; + /* Need to allocate mem before program front end for Fiji */ + if (pipe_ctx->plane_res.mi != NULL) + pipe_ctx->plane_res.mi->funcs->allocate_mem_input( + pipe_ctx->plane_res.mi, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, + pipe_ctx->stream->timing.pix_clk_khz, + context->stream_count); + dce110_program_front_end_for_pipe(dc, pipe_ctx); program_surface_visibility(dc, pipe_ctx); -- cgit v1.2.3-59-g8ed1b From bf5563ede9f254fba083c6b56e4ca8b836babb1d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 7 Nov 2017 05:30:47 +1000 Subject: amdgpu/dc: fix indentation warning from smatch. This fixes all the current smatch: warn: inconsistent indenting Reviewed-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Dave Airlie Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 +- .../gpu/drm/amd/display/dc/bios/command_table2.c | 18 ++++++------- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +-- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 26 +++++++++---------- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 16 ++++++------ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 30 +++++++++++----------- .../display/dc/dce120/dce120_timing_generator.c | 7 +++-- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 2 +- .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 30 +++++++++++----------- 10 files changed, 68 insertions(+), 69 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 43e9a9959288..1ee1717f2e6f 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -1373,7 +1373,7 @@ static enum bp_result get_firmware_info_v3_1( bp->cmd_tbl.get_smu_clock_info(bp) * 10; } - return BP_RESULT_OK; + return BP_RESULT_OK; } static enum bp_result bios_parser_get_encoder_cap_info( diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c index 64eab356d336..ba68693758a7 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c @@ -373,15 +373,15 @@ static void init_set_crtc_timing(struct bios_parser *bp) uint32_t dtd_version = BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming); - switch (dtd_version) { - case 3: - bp->cmd_tbl.set_crtc_timing = - set_crtc_using_dtd_timing_v3; - break; - default: - bp->cmd_tbl.set_crtc_timing = NULL; - break; - } + switch (dtd_version) { + case 3: + bp->cmd_tbl.set_crtc_timing = + set_crtc_using_dtd_timing_v3; + break; + default: + bp->cmd_tbl.set_crtc_timing = NULL; + break; + } } static enum bp_result set_crtc_using_dtd_timing_v3( diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index e1515230c661..3dce35e66b09 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1155,7 +1155,7 @@ static unsigned int dcn_find_normalized_clock_vdd_Level( unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels); if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) { - vdd_level = dcn_bw_v_max0p91; + vdd_level = dcn_bw_v_max0p91; BREAK_TO_DEBUGGER(); } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) { vdd_level = dcn_bw_v_max0p9; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 572b885195c7..de04b95e103a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -182,11 +182,11 @@ bool dc_stream_set_cursor_attributes( if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); - return false; + return false; } if (NULL == attributes) { dm_error("DC: attributes is NULL!\n"); - return false; + return false; } if (attributes->address.quad_part == 0) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index 526ec5c8eafd..d882adf746a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -179,19 +179,19 @@ static void check_audio_bandwidth_hdmi( /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number * of Audio samples per line multiplied by 10 - Layout 1) */ - samples /= 32; - samples *= crtc_info->v_active; - /*Number of samples multiplied by 10, per second */ - samples *= crtc_info->refresh_rate; - /*Number of Audio samples per second */ - samples /= 10; - - /* @todo do it after deep color is implemented - * 8xx - deep color bandwidth scaling - * Extra bandwidth is avaliable in deep color b/c link runs faster than - * pixel rate. This has the effect of allowing more tmds characters to - * be transmitted during blank - */ + samples /= 32; + samples *= crtc_info->v_active; + /*Number of samples multiplied by 10, per second */ + samples *= crtc_info->refresh_rate; + /*Number of Audio samples per second */ + samples /= 10; + + /* @todo do it after deep color is implemented + * 8xx - deep color bandwidth scaling + * Extra bandwidth is avaliable in deep color b/c link runs faster than + * pixel rate. This has the effect of allowing more tmds characters to + * be transmitted during blank + */ switch (crtc_info->color_depth) { case COLOR_DEPTH_888: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 3691c7498d08..fd77df573b61 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -130,14 +130,14 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) if (wait == true) { for (retryCount = 0; retryCount <= 100; retryCount++) { dce_get_dmcu_psr_state(dmcu, &psr_state); - if (enable) { - if (psr_state != 0) - break; - } else { - if (psr_state == 0) - break; - } - udelay(10); + if (enable) { + if (psr_state != 0) + break; + } else { + if (psr_state == 0) + break; + } + udelay(10); } } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 399a5984ada3..1229a3315018 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -775,8 +775,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) * connect DIG back_end to front_end while enable_stream and * disconnect them during disable_stream * BY this, it is logic clean to separate stream and link */ - link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, - pipe_ctx->stream_res.stream_enc->id, true); + link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, + pipe_ctx->stream_res.stream_enc->id, true); } @@ -1306,7 +1306,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->timing.display_color_depth, pipe_ctx->stream->signal); - pipe_ctx->stream_res.opp->funcs->opp_program_fmt( + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx->stream_res.opp, &stream->bit_depth_params, &stream->clamping); @@ -2594,21 +2594,21 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) uint8_t j; uint32_t min_vertical_blank_time = -1; - for (j = 0; j < context->stream_count; j++) { - struct dc_stream_state *stream = context->streams[j]; - uint32_t vertical_blank_in_pixels = 0; - uint32_t vertical_blank_time = 0; + for (j = 0; j < context->stream_count; j++) { + struct dc_stream_state *stream = context->streams[j]; + uint32_t vertical_blank_in_pixels = 0; + uint32_t vertical_blank_time = 0; - vertical_blank_in_pixels = stream->timing.h_total * - (stream->timing.v_total - - stream->timing.v_addressable); + vertical_blank_in_pixels = stream->timing.h_total * + (stream->timing.v_total + - stream->timing.v_addressable); - vertical_blank_time = vertical_blank_in_pixels - * 1000 / stream->timing.pix_clk_khz; + vertical_blank_time = vertical_blank_in_pixels + * 1000 / stream->timing.pix_clk_khz; - if (min_vertical_blank_time > vertical_blank_time) - min_vertical_blank_time = vertical_blank_time; - } + if (min_vertical_blank_time > vertical_blank_time) + min_vertical_blank_time = vertical_blank_time; + } return min_vertical_blank_time; } diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 95d871be3a0b..2502182d5e82 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -293,10 +293,9 @@ void dce120_timing_generator_tear_down_global_swap_lock( FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0, FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0); - CRTC_REG_SET_2( - CRTC0_CRTC_GSL_CONTROL, - CRTC_GSL_CHECK_LINE_NUM, 0, - CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/ + CRTC_REG_SET_2(CRTC0_CRTC_GSL_CONTROL, + CRTC_GSL_CHECK_LINE_NUM, 0, + CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/ } /* Reset slave controllers on master VSync */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 7784001c3a17..40627c244bf5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -124,7 +124,7 @@ static void program_gamut_remap( const uint16_t *regval, enum gamut_remap_select select) { - uint16_t selection = 0; + uint16_t selection = 0; struct color_matrices_reg gam_regs; if (regval == NULL || select == GAMUT_REMAP_BYPASS) { diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c index 1a5b3f70ddc9..56e25b3d65fd 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c @@ -133,13 +133,13 @@ static void release_engine( safe_to_reset = (i2c_sw_status == 1); } - if (safe_to_reset) - REG_UPDATE_2( - DC_I2C_CONTROL, - DC_I2C_SOFT_RESET, 1, - DC_I2C_SW_STATUS_RESET, 1); - else - REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1); + if (safe_to_reset) + REG_UPDATE_2( + DC_I2C_CONTROL, + DC_I2C_SOFT_RESET, 1, + DC_I2C_SW_STATUS_RESET, 1); + else + REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1); /* HW I2c engine - clock gating feature */ if (!hw_engine->engine_keep_power_up_count) @@ -301,16 +301,16 @@ static bool process_transaction( * For an I2C send operation, the LSB must be programmed to 0; * for I2C receive operation, the LSB must be programmed to 1. */ if (hw_engine->transaction_count == 0) { - value = REG_SET_4(DC_I2C_DATA, 0, - DC_I2C_DATA_RW, false, - DC_I2C_DATA, request->address, - DC_I2C_INDEX, 0, - DC_I2C_INDEX_WRITE, 1); + value = REG_SET_4(DC_I2C_DATA, 0, + DC_I2C_DATA_RW, false, + DC_I2C_DATA, request->address, + DC_I2C_INDEX, 0, + DC_I2C_INDEX_WRITE, 1); hw_engine->buffer_used_write = 0; } else - value = REG_SET_2(DC_I2C_DATA, 0, - DC_I2C_DATA_RW, false, - DC_I2C_DATA, request->address); + value = REG_SET_2(DC_I2C_DATA, 0, + DC_I2C_DATA_RW, false, + DC_I2C_DATA, request->address); hw_engine->buffer_used_write++; -- cgit v1.2.3-59-g8ed1b From 827f11e97dbc591f0c9619151b9a89f082e8ecb8 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 17 Oct 2017 17:18:24 -0400 Subject: drm/amd/display: Should disable when new stream is null core_link_disable_stream should be called when the new stream is null (i.e. want to disable). Modify the if condition to reflect that. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1229a3315018..be14a2665072 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1868,8 +1868,10 @@ static void dce110_reset_hw_ctx_wrap( pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { struct clock_source *old_clk = pipe_ctx_old->clock_source; - /* disable already, no need to disable again */ - if (pipe_ctx->stream && !pipe_ctx->stream->dpms_off) + /* Disable if new stream is null. O/w, if stream is + * disabled already, no need to disable again. + */ + if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); -- cgit v1.2.3-59-g8ed1b From 93984bbc70b3f321b8f6a3ec303e31b084e54230 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Mon, 20 Nov 2017 10:37:08 +0530 Subject: drm/amd/display: check plane state before validating fbc While validation fbc, array_mode of the pipe is accessed without checking plane_state exists for it. Causing to null pointer dereferencing followed by reboot when a crtc associated with external display(not connected) is page flipped. This patch adds a check for plane_state before using it to validate fbc. Signed-off-by: Shirish S Reviewed-by: Roman Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index be14a2665072..c3de7f305cd3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1774,6 +1774,10 @@ static enum dc_status validate_fbc(struct dc *dc, if (pipe_ctx->stream->sink->link->psr_enabled) return DC_ERROR_UNEXPECTED; + /* Nothing to compress */ + if (!pipe_ctx->plane_state) + return DC_ERROR_UNEXPECTED; + /* Only for non-linear tiling */ if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) return DC_ERROR_UNEXPECTED; -- cgit v1.2.3-59-g8ed1b From 2f2c3b36fc5a3dc9fd2cf22a2f368502a70eea5d Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 22 Nov 2017 16:47:35 +0000 Subject: drm/amd/display: fix memory leaks on error exit return Currently in the case where some of the allocations fail for dce110_tgv, dce110_xfmv, dce110_miv or dce110_oppv then the exit return path ends up leaking allocated objects. Fix this by kfree'ing them before returning. Also re-work the comparison of the null pointers to use the !ptr idiom. Detected by CoverityScan, CID#1460246, 1460325, 1460324, 1460392 ("Resource Leak") Fixes: c4562236b3bc ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Colin Ian King Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index db96d2b47ff1..61adb8174ce0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1037,11 +1037,13 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), GFP_KERNEL); - if ((dce110_tgv == NULL) || - (dce110_xfmv == NULL) || - (dce110_miv == NULL) || - (dce110_oppv == NULL)) - return false; + if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { + kfree(dce110_tgv); + kfree(dce110_xfmv); + kfree(dce110_miv); + kfree(dce110_oppv); + return false; + } dce110_opp_v_construct(dce110_oppv, ctx); -- cgit v1.2.3-59-g8ed1b From 2b7c97d687e81db07d8c67b32ff920e7bf59444e Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 15 Nov 2017 18:27:31 -0500 Subject: drm/amd/display: fix seq issue: turn on clock before programming afmt. Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 5 +++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 22 ++++++++++------------ 2 files changed, 15 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 4fd49a16c3b6..c04d67db9cea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -87,6 +87,11 @@ static void dce110_update_generic_info_packet( */ uint32_t max_retries = 50; + REG_GET(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, ®val); + /*we need turn on clock before programming AFMT block*/ + if (regval != 1) + REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); + if (REG(AFMT_VBI_PACKET_CONTROL1)) { if (packet_index >= 8) ASSERT(0); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c3de7f305cd3..07ff8d2faf3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -991,6 +991,16 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) struct dc_link *link = stream->sink->link; struct dc *dc = pipe_ctx->stream->ctx->dc; + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( + pipe_ctx->stream_res.stream_enc); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( + pipe_ctx->stream_res.stream_enc); + + pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( + pipe_ctx->stream_res.stream_enc, true); if (pipe_ctx->stream_res.audio) { pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); @@ -1015,18 +1025,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) */ } - if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( - pipe_ctx->stream_res.stream_enc); - - if (dc_is_dp_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( - pipe_ctx->stream_res.stream_enc); - - pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( - pipe_ctx->stream_res.stream_enc, true); - - /* blank at encoder level */ if (dc_is_dp_signal(pipe_ctx->stream->signal)) { if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP) -- cgit v1.2.3-59-g8ed1b From b001965d4eb5e4c0e3de7dc6dce1d45ca25232a7 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:11:44 -0500 Subject: drm/amd/display: Fix use before NULL check in validate_timing Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1124 dce110_timing_generator_validate_timing() warn: variable dereferenced before check 'timing' (see line 1116) Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 67ac737eaa7e..4befce6cd87a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1112,10 +1112,7 @@ bool dce110_timing_generator_validate_timing( enum signal_type signal) { uint32_t h_blank; - uint32_t h_back_porch; - uint32_t hsync_offset = timing->h_border_right + - timing->h_front_porch; - uint32_t h_sync_start = timing->h_addressable + hsync_offset; + uint32_t h_back_porch, hsync_offset, h_sync_start; struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); @@ -1124,6 +1121,9 @@ bool dce110_timing_generator_validate_timing( if (!timing) return false; + hsync_offset = timing->h_border_right + timing->h_front_porch; + h_sync_start = timing->h_addressable + hsync_offset; + /* Currently we don't support 3D, so block all 3D timings */ if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) return false; -- cgit v1.2.3-59-g8ed1b From 553aae12e3ad4d4d9cb9accb129a8c818bce506b Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Mon, 16 Oct 2017 10:43:59 -0400 Subject: drm/amd/display: Add APU cap in dc_caps Some features should only be enabled on APUs or should not be enabled on APUs. Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + 5 files changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7240db2e6f09..e8894ad3adf4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -558,6 +558,7 @@ static bool construct(struct dc *dc, dc_version = resource_parse_asic_id(init_params->asic_id); dc->ctx->dce_version = dc_version; + #if defined(CONFIG_DRM_AMD_DC_FBC) dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9d8f4a55c74e..9ca838b3c4d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -60,6 +60,7 @@ struct dc_caps { unsigned int max_video_width; bool dcc_const_color; bool dynamic_audio; + bool is_apu; }; struct dc_dcc_surface_param { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 61adb8174ce0..5228ee78f7e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1156,6 +1156,7 @@ static bool construct( dc->caps.max_downscale_ratio = 150; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 9c18efd3446f..8f2bd56f3461 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -957,6 +957,7 @@ static bool dce81_construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * @@ -1121,6 +1122,7 @@ static bool dce83_construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9fc8f827f2a1..f59b2ab6c134 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1235,6 +1235,7 @@ static bool construct( dc->caps.max_cursor_size = 256; dc->caps.max_slave_planes = 1; + dc->caps.is_apu = true; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; -- cgit v1.2.3-59-g8ed1b From 3dc780ec3473200ef870eae9b19169445d76be4c Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 17 Oct 2017 14:48:11 -0400 Subject: drm/amd/display: Move lock to front end program. Moved lock and unlock to apply_ctx_to_surface, since all the front end programming is within apply_ctx_to_surface. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 52 +--------------------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 +++++++ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +++++- 3 files changed, 29 insertions(+), 52 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e8894ad3adf4..9925d0e01c04 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -839,7 +839,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; - int i, j, k, l; + int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; disable_dangling_plane(dc, context); @@ -893,15 +893,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - for (i = 0; i < context->stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - pipe = &context->res_ctx.pipe_ctx[j]; - - if (!pipe->top_pipe && pipe->stream == context->streams[i]) - dc->hwss.pipe_control_lock(dc, pipe, false); - } - } - dc_release_state(dc->current_state); dc->current_state = context; @@ -1313,27 +1304,6 @@ static void commit_planes_for_stream(struct dc *dc, return; } - /* Lock pipes for provided surfaces, or all active if full update*/ - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *plane_state = srf_updates[i].surface; - - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) - continue; - if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) - continue; - - dc->hwss.pipe_control_lock( - dc, - pipe_ctx, - true); - } - if (update_type == UPDATE_TYPE_FULL) - break; - } - /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1390,26 +1360,6 @@ static void commit_planes_for_stream(struct dc *dc, } } } - - /* Unlock pipes */ - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - for (j = 0; j < surface_count; j++) { - if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != pipe_ctx->plane_state) - continue; - if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) - continue; - - dc->hwss.pipe_control_lock( - dc, - pipe_ctx, - false); - - break; - } - } } void dc_commit_updates_for_stream(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 07ff8d2faf3f..61e11a1161bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2873,8 +2873,14 @@ static void dce110_apply_ctx_for_surface( be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (stream == context->res_ctx.pipe_ctx[i].stream) { be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; + if (!pipe_ctx->top_pipe && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, true); break; } } @@ -2898,6 +2904,16 @@ static void dce110_apply_ctx_for_surface( program_surface_visibility(dc, pipe_ctx); } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if ((stream == pipe_ctx->stream) && + (!pipe_ctx->top_pipe) && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, false); + } } static void dce110_power_down_fe(struct dc *dc, int fe_idx) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 961ad5c3b454..ac731c46419d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2550,6 +2550,11 @@ static void dcn10_apply_ctx_for_surface( if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->inst == be_idx && + !pipe_ctx->top_pipe) + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); + /* * Powergate reused pipes that are not powergated * fairly hacky right now, using opp_id as indicator @@ -2605,13 +2610,19 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream != stream) continue; /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) + if (!pipe_ctx->top_pipe) { program_all_pipe_in_tree(dc, pipe_ctx, context); + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->inst == be_idx && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); + } } dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, -- cgit v1.2.3-59-g8ed1b From 56ef6ed9faf35b9057630dd12aeca134f98214ec Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Mon, 23 Oct 2017 17:02:02 -0400 Subject: drm/amd/display: Move hdr_metadata from plane to stream Need to move HDR Metadata from Surface to Stream since there is only one infoframe possible per stream. Also cleaning up some duplicate definitions. Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++++--- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 +++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 41 +++++++++------------- drivers/gpu/drm/amd/display/dc/dc.h | 35 +++++------------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 9 +++++ .../drm/amd/display/dc/dce/dce_stream_encoder.c | 11 +++++- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +- 8 files changed, 65 insertions(+), 60 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bc596df85ca9..55317c029d44 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1007,6 +1007,7 @@ bool dc_commit_planes_to_stream( flip_addr[i].address = plane_states[i]->address; flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; plane_info[i].color_space = plane_states[i]->color_space; + plane_info[i].input_tf = plane_states[i]->input_tf; plane_info[i].format = plane_states[i]->format; plane_info[i].plane_size = plane_states[i]->plane_size; plane_info[i].rotation = plane_states[i]->rotation; @@ -1132,12 +1133,12 @@ static enum surface_update_type get_plane_info_update_type( /* Full update parameters */ temp_plane_info.color_space = u->surface->color_space; + temp_plane_info.input_tf = u->surface->input_tf; temp_plane_info.dcc = u->surface->dcc; temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; temp_plane_info.plane_size = u->surface->plane_size; temp_plane_info.rotation = u->surface->rotation; temp_plane_info.stereo_format = u->surface->stereo_format; - temp_plane_info.input_csc_enabled = u->surface->input_csc_color_matrix.enable_adjustment; if (surface_index == 0) temp_plane_info.visible = u->plane_info->visible; @@ -1218,7 +1219,6 @@ static enum surface_update_type det_surface_update( overall_type = type; if (u->in_transfer_func || - u->hdr_static_metadata || u->input_csc_color_matrix) { if (overall_type < UPDATE_TYPE_MED) overall_type = UPDATE_TYPE_MED; @@ -1350,14 +1350,25 @@ static void commit_planes_for_stream(struct dc *dc, pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) dc->hwss.set_input_transfer_func( pipe_ctx, pipe_ctx->plane_state); + } + } + + if (update_type > UPDATE_TYPE_FAST) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; + + if (!pipe_ctx->stream) + continue; if (stream_update != NULL && - stream_update->out_transfer_func != NULL) { + stream_update->out_transfer_func != NULL) { dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } - if (srf_updates[i].hdr_static_metadata) { + if (stream_update != NULL && + stream_update->hdr_static_metadata) { resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 6acee5426e4b..2e509382935f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -137,6 +137,7 @@ void pre_surface_trace( "plane_state->tiling_info.gfx8.pipe_config = %d;\n" "plane_state->tiling_info.gfx8.array_mode = %d;\n" "plane_state->color_space = %d;\n" + "plane_state->input_tf = %d;\n" "plane_state->dcc.enable = %d;\n" "plane_state->format = %d;\n" "plane_state->rotation = %d;\n" @@ -144,6 +145,7 @@ void pre_surface_trace( plane_state->tiling_info.gfx8.pipe_config, plane_state->tiling_info.gfx8.array_mode, plane_state->color_space, + plane_state->input_tf, plane_state->dcc.enable, plane_state->format, plane_state->rotation, @@ -184,6 +186,7 @@ void update_surface_trace( if (update->plane_info) { SURFACE_TRACE( "plane_info->color_space = %d;\n" + "plane_info->input_tf = %d;\n" "plane_info->format = %d;\n" "plane_info->plane_size.grph.surface_pitch = %d;\n" "plane_info->plane_size.grph.surface_size.height = %d;\n" @@ -192,6 +195,7 @@ void update_surface_trace( "plane_info->plane_size.grph.surface_size.y = %d;\n" "plane_info->rotation = %d;\n", update->plane_info->color_space, + update->plane_info->input_tf, update->plane_info->format, update->plane_info->plane_size.grph.surface_pitch, update->plane_info->plane_size.grph.surface_size.height, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b7422d3b71ef..15e518aba916 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2319,20 +2319,13 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_plane_state *plane_state, struct dc_stream_state *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; - struct dc_hdr_static_metadata hdr_metadata; uint32_t data; - if (!plane_state) - return; - - hdr_metadata = plane_state->hdr_static_ctx; - - if (!hdr_metadata.hdr_supported) + if (!stream->hdr_static_metadata.hdr_supported) return; if (dc_is_hdmi_signal(signal)) { @@ -2352,55 +2345,55 @@ static void set_hdr_static_info_packet( i = 2; } - data = hdr_metadata.is_hdr; + data = stream->hdr_static_metadata.is_hdr; info_packet->sb[i++] = data ? 0x02 : 0x00; info_packet->sb[i++] = 0x00; - data = hdr_metadata.chromaticity_green_x / 2; + data = stream->hdr_static_metadata.chromaticity_green_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_green_y / 2; + data = stream->hdr_static_metadata.chromaticity_green_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_blue_x / 2; + data = stream->hdr_static_metadata.chromaticity_blue_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_blue_y / 2; + data = stream->hdr_static_metadata.chromaticity_blue_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_red_x / 2; + data = stream->hdr_static_metadata.chromaticity_red_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_red_y / 2; + data = stream->hdr_static_metadata.chromaticity_red_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_white_point_x / 2; + data = stream->hdr_static_metadata.chromaticity_white_point_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_white_point_y / 2; + data = stream->hdr_static_metadata.chromaticity_white_point_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.max_luminance; + data = stream->hdr_static_metadata.max_luminance; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.min_luminance; + data = stream->hdr_static_metadata.min_luminance; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.maximum_content_light_level; + data = stream->hdr_static_metadata.maximum_content_light_level; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.maximum_frame_average_light_level; + data = stream->hdr_static_metadata.maximum_frame_average_light_level; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; @@ -2551,16 +2544,14 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); - set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->plane_state, pipe_ctx->stream); + set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(&info->vsc, pipe_ctx->stream); set_spd_info_packet(&info->spd, pipe_ctx->stream); - set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->plane_state, pipe_ctx->stream); + set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); } patch_gamut_packet_checksum(&info->gamut); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9833b9de650f..e39371797eeb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -334,24 +334,6 @@ enum color_transfer_func { transfer_func_gamma_26 }; -enum color_color_space { - color_space_unsupported, - color_space_srgb, - color_space_bt601, - color_space_bt709, - color_space_xv_ycc_bt601, - color_space_xv_ycc_bt709, - color_space_xr_rgb, - color_space_bt2020, - color_space_adobe, - color_space_dci_p3, - color_space_sc_rgb_ms_ref, - color_space_display_native, - color_space_app_ctrl, - color_space_dolby_vision, - color_space_custom_coordinates -}; - struct dc_hdr_static_metadata { /* display chromaticities and white point in units of 0.00001 */ unsigned int chromaticity_green_x; @@ -427,7 +409,6 @@ struct dc_plane_state { union dc_tiling_info tiling_info; struct dc_plane_dcc_param dcc; - struct dc_hdr_static_metadata hdr_static_ctx; struct dc_gamma *gamma_correction; struct dc_transfer_func *in_transfer_func; @@ -435,13 +416,12 @@ struct dc_plane_state { struct csc_transform input_csc_color_matrix; struct fixed31_32 coeff_reduction_factor; - // sourceContentAttribute cache - bool is_source_input_valid; - struct dc_hdr_static_metadata source_input_mastering_info; - enum color_color_space source_input_color_space; - enum color_transfer_func source_input_tf; + // TODO: No longer used, remove + struct dc_hdr_static_metadata hdr_static_ctx; enum dc_color_space color_space; + enum color_transfer_func input_tf; + enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; @@ -467,7 +447,8 @@ struct dc_plane_info { enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; - enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ + enum dc_color_space color_space; + enum color_transfer_func input_tf; bool horizontal_mirror; bool visible; bool per_pixel_alpha; @@ -488,13 +469,13 @@ struct dc_surface_update { struct dc_flip_addrs *flip_addr; struct dc_plane_info *plane_info; struct dc_scaling_info *scaling_info; + /* following updates require alloc/sleep/spin that is not isr safe, * null means no updates */ /* gamma TO BE REMOVED */ struct dc_gamma *gamma; struct dc_transfer_func *in_transfer_func; - struct dc_hdr_static_metadata *hdr_static_metadata; struct csc_transform *input_csc_color_matrix; struct fixed31_32 *coeff_reduction_factor; @@ -591,6 +572,7 @@ struct dc_stream_state { struct freesync_context freesync_ctx; + struct dc_hdr_static_metadata hdr_static_metadata; struct dc_transfer_func *out_transfer_func; struct colorspace_transform gamut_remap_matrix; struct csc_transform csc_color_matrix; @@ -631,6 +613,7 @@ struct dc_stream_update { struct rect src; struct rect dst; struct dc_transfer_func *out_transfer_func; + struct dc_hdr_static_metadata *hdr_static_metadata; }; bool dc_is_stream_unchanged( diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 1a9f57fb0838..ea58d106fb55 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -492,15 +492,24 @@ struct dc_cursor_attributes { enum dc_color_space { COLOR_SPACE_UNKNOWN, COLOR_SPACE_SRGB, + COLOR_SPACE_XR_RGB, COLOR_SPACE_SRGB_LIMITED, + COLOR_SPACE_MSREF_SCRGB, COLOR_SPACE_YCBCR601, COLOR_SPACE_YCBCR709, + COLOR_SPACE_XV_YCC_709, + COLOR_SPACE_XV_YCC_601, COLOR_SPACE_YCBCR601_LIMITED, COLOR_SPACE_YCBCR709_LIMITED, COLOR_SPACE_2020_RGB_FULLRANGE, COLOR_SPACE_2020_RGB_LIMITEDRANGE, COLOR_SPACE_2020_YCBCR, COLOR_SPACE_ADOBERGB, + COLOR_SPACE_DCIP3, + COLOR_SPACE_DISPLAYNATIVE, + COLOR_SPACE_DOLBYVISION, + COLOR_SPACE_APPCTRL, + COLOR_SPACE_CUSTOMPOINTS, }; enum dc_dither_option { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index e42b6eb1c1f0..4748975fd47e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -437,10 +437,19 @@ static void dce110_stream_encoder_dp_set_stream_attribute( case COLOR_SPACE_2020_RGB_FULLRANGE: case COLOR_SPACE_2020_RGB_LIMITEDRANGE: case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_XR_RGB: + case COLOR_SPACE_MSREF_SCRGB: case COLOR_SPACE_ADOBERGB: - case COLOR_SPACE_UNKNOWN: + case COLOR_SPACE_DCIP3: + case COLOR_SPACE_XV_YCC_709: + case COLOR_SPACE_XV_YCC_601: case COLOR_SPACE_YCBCR601_LIMITED: case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_DISPLAYNATIVE: + case COLOR_SPACE_DOLBYVISION: + case COLOR_SPACE_APPCTRL: + case COLOR_SPACE_CUSTOMPOINTS: + case COLOR_SPACE_UNKNOWN: /* do nothing */ break; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 61e11a1161bb..58d019cacaa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2279,8 +2279,7 @@ static void set_plane_config( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment - == true) { + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = pipe_ctx->stream->output_color_space; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index cf594fb44328..adabd2ad5594 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1556,8 +1556,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, int i; struct out_csc_color_matrix tbl_entry; - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment - == true) { + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { enum dc_color_space color_space = pipe_ctx->stream->output_color_space; -- cgit v1.2.3-59-g8ed1b From fa2123dbccdc881fae02aaf8b05758db53d62955 Mon Sep 17 00:00:00 2001 From: Mikita Lipski Date: Tue, 17 Oct 2017 15:29:22 -0400 Subject: drm/amd/display: Multi display synchronization logic This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by: Mikita Lipski Reviewed-by: Mikita Lipski Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 54 ++++- drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +- drivers/gpu/drm/amd/display/dc/dc.h | 3 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 16 ++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 46 +++- .../display/dc/dce110/dce110_timing_generator.c | 265 +++++++++++++++++---- .../display/dc/dce110/dce110_timing_generator.h | 6 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 29 ++- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 66 ++++- .../drm/amd/display/dc/inc/hw/timing_generator.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 + 11 files changed, 456 insertions(+), 66 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3bc314872304..8360d17125ae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2298,6 +2298,56 @@ static int create_fake_sink(struct amdgpu_dm_connector *aconnector) return 0; } +static void set_multisync_trigger_params( + struct dc_stream_state *stream) +{ + if (stream->triggered_crtc_reset.enabled) { + stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; + stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; + } +} + +static void set_master_stream(struct dc_stream_state *stream_set[], + int stream_count) +{ + int j, highest_rfr = 0, master_stream = 0; + + for (j = 0; j < stream_count; j++) { + if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { + int refresh_rate = 0; + + refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ + (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); + if (refresh_rate > highest_rfr) { + highest_rfr = refresh_rate; + master_stream = j; + } + } + } + for (j = 0; j < stream_count; j++) { + if (stream_set[j] && j != master_stream) + stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; + } +} + +static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) +{ + int i = 0; + + if (context->stream_count < 2) + return; + for (i = 0; i < context->stream_count ; i++) { + if (!context->streams[i]) + continue; + /* TODO: add a function to read AMD VSDB bits and will set + * crtc_sync_master.multi_sync_enabled flag + * For now its set to false + */ + set_multisync_trigger_params(context->streams[i]); + } + set_master_stream(context->streams, context->stream_count); +} + static struct dc_stream_state * create_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, @@ -4132,8 +4182,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } } - if (dm_state->context) + if (dm_state->context) { + dm_enable_per_frame_crtc_master_sync(dm_state->context); WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); + } for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 55317c029d44..507b1171d65f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -713,6 +713,28 @@ void dc_destroy(struct dc **dc) *dc = NULL; } +static void enable_timing_multisync( + struct dc *dc, + struct dc_state *ctx) +{ + int i = 0, multisync_count = 0; + int pipe_count = dc->res_pool->pipe_count; + struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL }; + + for (i = 0; i < pipe_count; i++) { + if (!ctx->res_ctx.pipe_ctx[i].stream || + !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) + continue; + multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i]; + multisync_count++; + } + + if (multisync_count > 1) { + dc->hwss.enable_per_frame_crtc_position_reset( + dc, multisync_count, multisync_pipes); + } +} + static void program_timing_sync( struct dc *dc, struct dc_state *ctx) @@ -891,7 +913,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c } result = dc->hwss.apply_ctx_to_hw(dc, context); - program_timing_sync(dc, context); + if (context->stream_count > 1) + enable_timing_multisync(dc, context); + program_timing_sync(dc, context); dc_enable_stereo(dc, context, dc_streams, context->stream_count); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4019e7417c88..a51a9c748c1a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -607,6 +607,9 @@ struct dc_stream_state { /* from stream struct */ struct kref refcount; + + struct crtc_trigger_info triggered_crtc_reset; + }; struct dc_stream_update { diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index ea58d106fb55..587c0bb3d4ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -673,6 +673,22 @@ enum dc_timing_3d_format { TIMING_3D_FORMAT_MAX, }; +enum trigger_delay { + TRIGGER_DELAY_NEXT_PIXEL = 0, + TRIGGER_DELAY_NEXT_LINE, +}; + +enum crtc_event { + CRTC_EVENT_VSYNC_RISING = 0, + CRTC_EVENT_VSYNC_FALLING +}; + +struct crtc_trigger_info { + bool enabled; + struct dc_stream_state *event_source; + enum crtc_event event; + enum trigger_delay delay; +}; struct dc_crtc_timing { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 58d019cacaa2..868040a4f7ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2457,20 +2457,16 @@ static void dce110_enable_timing_synchronization( for (i = 1 /* skip the master */; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( - grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group); - - + grouped_pipes[i]->stream_res.tg, + gsl_params.gsl_group); for (i = 1 /* skip the master */; i < group_size; i++) { DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); - /* Regardless of success of the wait above, remove the reset or - * the driver will start timing out on Display requests. */ - DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); - grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg); + grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( + grouped_pipes[i]->stream_res.tg); } - /* GSL Vblank synchronization is a one time sync mechanism, assumption * is that the sync'ed displays will not drift out of sync over time*/ DC_SYNC_INFO("GSL: Restoring register states.\n"); @@ -2480,6 +2476,39 @@ static void dce110_enable_timing_synchronization( DC_SYNC_INFO("GSL: Set-up complete.\n"); } +static void dce110_enable_per_frame_crtc_position_reset( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + struct dcp_gsl_params gsl_params = { 0 }; + int i; + + gsl_params.gsl_group = 0; + gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst; + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( + grouped_pipes[i]->stream_res.tg, &gsl_params); + + DC_SYNC_INFO("GSL: enabling trigger-reset\n"); + + for (i = 1; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( + grouped_pipes[i]->stream_res.tg, + gsl_params.gsl_master, + &grouped_pipes[i]->stream->triggered_crtc_reset); + + DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); + for (i = 1; i < group_size; i++) + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); + +} + static void init_hw(struct dc *dc) { int i; @@ -2976,6 +3005,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dce110_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .enable_stream = dce110_enable_stream, .disable_stream = dce110_disable_stream, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 4befce6cd87a..25ca72139e5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1224,26 +1224,46 @@ void dce110_timing_generator_setup_global_swap_lock( /* This pipe will belong to GSL Group zero. */ set_reg_field_value(value, - 1, - DCP_GSL_CONTROL, - DCP_GSL0_EN); + 1, + DCP_GSL_CONTROL, + DCP_GSL0_EN); set_reg_field_value(value, - gsl_params->gsl_master == tg->inst, - DCP_GSL_CONTROL, - DCP_GSL_MASTER_EN); + gsl_params->gsl_master == tg->inst, + DCP_GSL_CONTROL, + DCP_GSL_MASTER_EN); set_reg_field_value(value, - HFLIP_READY_DELAY, - DCP_GSL_CONTROL, - DCP_GSL_HSYNC_FLIP_FORCE_DELAY); + HFLIP_READY_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_FORCE_DELAY); /* Keep signal low (pending high) during 6 lines. * Also defines minimum interval before re-checking signal. */ set_reg_field_value(value, - HFLIP_CHECK_DELAY, - DCP_GSL_CONTROL, - DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + HFLIP_CHECK_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + + dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value); + value = 0; + + set_reg_field_value(value, + gsl_params->gsl_master, + DCIO_GSL0_CNTL, + DCIO_GSL0_VSYNC_SEL); + + set_reg_field_value(value, + 0, + DCIO_GSL0_CNTL, + DCIO_GSL0_TIMING_SYNC_SEL); + + set_reg_field_value(value, + 0, + DCIO_GSL0_CNTL, + DCIO_GSL0_GLOBAL_UNLOCK_SEL); + + dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value); { @@ -1253,38 +1273,38 @@ void dce110_timing_generator_setup_global_swap_lock( CRTC_REG(mmCRTC_V_TOTAL)); set_reg_field_value(value, - 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ - DCP_GSL_CONTROL, - DCP_GSL_SYNC_SOURCE); + 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ + DCP_GSL_CONTROL, + DCP_GSL_SYNC_SOURCE); /* Checkpoint relative to end of frame */ check_point = get_reg_field_value(value_crtc_vtotal, - CRTC_V_TOTAL, - CRTC_V_TOTAL); + CRTC_V_TOTAL, + CRTC_V_TOTAL); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0); } set_reg_field_value(value, - 1, - DCP_GSL_CONTROL, - DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); + 1, + DCP_GSL_CONTROL, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); dm_write_reg(tg->ctx, address, value); /********************************************************************/ address = CRTC_REG(mmCRTC_GSL_CONTROL); - value = 0; + value = dm_read_reg(tg->ctx, address); set_reg_field_value(value, - check_point - FLIP_READY_BACK_LOOKUP, - CRTC_GSL_CONTROL, - CRTC_GSL_CHECK_LINE_NUM); + check_point - FLIP_READY_BACK_LOOKUP, + CRTC_GSL_CONTROL, + CRTC_GSL_CHECK_LINE_NUM); set_reg_field_value(value, - VFLIP_READY_DELAY, - CRTC_GSL_CONTROL, - CRTC_GSL_FORCE_DELAY); + VFLIP_READY_DELAY, + CRTC_GSL_CONTROL, + CRTC_GSL_FORCE_DELAY); dm_write_reg(tg->ctx, address, value); } @@ -1555,6 +1575,138 @@ void dce110_timing_generator_enable_reset_trigger( dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); } +void dce110_timing_generator_enable_crtc_reset( + struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp) +{ + uint32_t value = 0; + uint32_t rising_edge = 0; + uint32_t falling_edge = 0; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + /* Setup trigger edge */ + switch (crtc_tp->event) { + case CRTC_EVENT_VSYNC_RISING: + rising_edge = 1; + break; + + case CRTC_EVENT_VSYNC_FALLING: + falling_edge = 1; + break; + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); + + set_reg_field_value(value, + source_tg_inst, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); + + set_reg_field_value(value, + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); + + set_reg_field_value(value, + rising_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_RISING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + falling_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); + + /**************************************************************/ + + switch (crtc_tp->delay) { + case TRIGGER_DELAY_NEXT_LINE: + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 0, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 0, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 2, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + break; + + case TRIGGER_DELAY_NEXT_PIXEL: + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 0, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 2, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 1, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + break; + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE)); + + set_reg_field_value(value, + 2, + CRTC_MASTER_UPDATE_MODE, + MASTER_UPDATE_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); +} void dce110_timing_generator_disable_reset_trigger( struct timing_generator *tg) { @@ -1564,34 +1716,48 @@ void dce110_timing_generator_disable_reset_trigger( value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); set_reg_field_value(value, - 0, /* force counter now mode is disabled */ - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_MODE); + 0, /* force counter now mode is disabled */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); set_reg_field_value(value, - 1, /* clear trigger status */ - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_CLEAR); + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 0, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value); + /********************************************************************/ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); set_reg_field_value(value, - TRIGGER_SOURCE_SELECT_LOGIC_ZERO, - CRTC_TRIGB_CNTL, - CRTC_TRIGB_SOURCE_SELECT); + TRIGGER_SOURCE_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); set_reg_field_value(value, - TRIGGER_POLARITY_SELECT_LOGIC_ZERO, - CRTC_TRIGB_CNTL, - CRTC_TRIGB_POLARITY_SELECT); + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); set_reg_field_value(value, - 1, /* clear trigger status */ - CRTC_TRIGB_CNTL, - CRTC_TRIGB_CLEAR); + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); } @@ -1611,10 +1777,16 @@ bool dce110_timing_generator_did_triggered_reset_occur( struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); - - return get_reg_field_value(value, - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; + uint32_t value1 = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + bool force = get_reg_field_value(value, + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; + bool vert_sync = get_reg_field_value(value1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED) != 0; + + return (force || vert_sync); } /** @@ -1928,6 +2100,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = { .setup_global_swap_lock = dce110_timing_generator_setup_global_swap_lock, .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, + .enable_crtc_reset = dce110_timing_generator_enable_crtc_reset, .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, .tear_down_global_swap_lock = dce110_timing_generator_tear_down_global_swap_lock, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 82737dea6984..232747c7c60b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -174,6 +174,12 @@ void dce110_timing_generator_setup_global_swap_lock( void dce110_timing_generator_tear_down_global_swap_lock( struct timing_generator *tg); +/* Reset crtc position on master VSync */ +void dce110_timing_generator_enable_crtc_reset( + struct timing_generator *tg, + int source, + struct crtc_trigger_info *crtc_tp); + /* Reset slave controllers on master VSync */ void dce110_timing_generator_enable_reset_trigger( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index adabd2ad5594..762af17485e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1304,14 +1304,15 @@ static void dcn10_enable_timing_synchronization( for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( - grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst); - + grouped_pipes[i]->stream_res.tg, + grouped_pipes[0]->stream_res.tg->inst); DC_SYNC_INFO("Waiting for trigger\n"); /* Need to get only check 1 pipe for having reset as all the others are * synchronized. Look at last pipe programmed to reset. */ + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg); for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( @@ -1320,6 +1321,29 @@ static void dcn10_enable_timing_synchronization( DC_SYNC_INFO("Sync complete\n"); } +static void dcn10_enable_per_frame_crtc_position_reset( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + int i; + + DC_SYNC_INFO("Setting up\n"); + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( + grouped_pipes[i]->stream_res.tg, + grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst, + &grouped_pipes[i]->stream->triggered_crtc_reset); + + DC_SYNC_INFO("Waiting for trigger\n"); + + for (i = 1; i < group_size; i++) + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); + + DC_SYNC_INFO("Multi-display sync is complete\n"); +} + static void print_rq_dlg_ttu( struct dc *core_dc, struct pipe_ctx *pipe_ctx) @@ -2485,6 +2509,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .enable_stream = dce110_enable_stream, .disable_stream = dce110_disable_stream, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index fced178c8c79..c178cc0bd426 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -610,12 +610,28 @@ static bool tgn10_did_triggered_reset_occur( struct timing_generator *tg) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); - uint32_t occurred; + uint32_t occurred_force, occurred_vsync; REG_GET(OTG_FORCE_COUNT_NOW_CNTL, - OTG_FORCE_COUNT_NOW_OCCURRED, &occurred); + OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); - return occurred != 0; + REG_GET(OTG_VERT_SYNC_CONTROL, + OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); + + return occurred_vsync != 0 || occurred_force != 0; +} + +static void tgn10_disable_reset_trigger(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + REG_WRITE(OTG_TRIGA_CNTL, 0); + + REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, + OTG_FORCE_COUNT_NOW_CLEAR, 1); + + REG_SET(OTG_VERT_SYNC_CONTROL, 0, + OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); } static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst) @@ -652,14 +668,49 @@ static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_t OTG_FORCE_COUNT_NOW_MODE, 2); } -static void tgn10_disable_reset_trigger(struct timing_generator *tg) +void tgn10_enable_crtc_reset( + struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + uint32_t falling_edge = 0; + uint32_t rising_edge = 0; - REG_WRITE(OTG_TRIGA_CNTL, 0); + switch (crtc_tp->event) { - REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, - OTG_FORCE_COUNT_NOW_CLEAR, 1); + case CRTC_EVENT_VSYNC_RISING: + rising_edge = 1; + break; + + case CRTC_EVENT_VSYNC_FALLING: + falling_edge = 1; + break; + } + + REG_SET_4(OTG_TRIGA_CNTL, 0, + /* vsync signal from selected OTG pipe based + * on OTG_TRIG_SOURCE_PIPE_SELECT setting + */ + OTG_TRIGA_SOURCE_SELECT, 20, + OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, + /* always detect falling edge */ + OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, + OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); + + switch (crtc_tp->delay) { + case TRIGGER_DELAY_NEXT_LINE: + REG_SET(OTG_VERT_SYNC_CONTROL, 0, + OTG_AUTO_FORCE_VSYNC_MODE, 1); + break; + case TRIGGER_DELAY_NEXT_PIXEL: + REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, + /* force H count to H_TOTAL and V count to V_TOTAL in + * progressive mode and V_TOTAL-1 in interlaced mode + */ + OTG_FORCE_COUNT_NOW_MODE, 2); + break; + } } static void tgn10_wait_for_state(struct timing_generator *tg, @@ -1174,6 +1225,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_blank_color = tgn10_program_blank_color, .did_triggered_reset_occur = tgn10_did_triggered_reset_occur, .enable_reset_trigger = tgn10_enable_reset_trigger, + .enable_crtc_reset = tgn10_enable_crtc_reset, .disable_reset_trigger = tgn10_disable_reset_trigger, .lock = tgn10_lock, .unlock = tgn10_unlock, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index c6ab38c5b2be..75f7a01b9175 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -158,7 +158,11 @@ struct timing_generator_funcs { const struct dcp_gsl_params *gsl_params); void (*unlock)(struct timing_generator *tg); void (*lock)(struct timing_generator *tg); - void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst); + void (*enable_reset_trigger)(struct timing_generator *tg, + int source_tg_inst); + void (*enable_crtc_reset)(struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); void (*disable_reset_trigger)(struct timing_generator *tg); void (*tear_down_global_swap_lock)(struct timing_generator *tg); void (*enable_advanced_request)(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 8734689a9245..cebbba345889 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -114,6 +114,11 @@ struct hw_sequencer_funcs { int group_size, struct pipe_ctx *grouped_pipes[]); + void (*enable_per_frame_crtc_position_reset)( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]); + void (*enable_display_pipe_clock_gating)( struct dc_context *ctx, bool clock_gating); -- cgit v1.2.3-59-g8ed1b From 069d418f412ec4b33056dc7d84b63c80c2e50abf Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Tue, 26 Sep 2017 19:45:43 -0400 Subject: drm/amd/display: Don't use dc_link in link_encoder dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 +++--- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 34 +++++++--------- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 5 +-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 46 ++++++++++++---------- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 3 +- 10 files changed, 57 insertions(+), 55 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 80d9153334dc..7b0e43c0685c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1798,7 +1798,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) else dp_disable_link_phy_mst(link, signal); } else - link->link_enc->funcs->disable_output(link->link_enc, signal, link); + link->link_enc->funcs->disable_output(link->link_enc, signal); } bool dp_active_dongle_validate_timing( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 9a33b471270a..f2902569be2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -89,7 +89,7 @@ void dp_enable_link_phy( if (dc_is_dp_sst_signal(signal)) { if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_power_control(link->link_enc, true); + link->dc->hwss.edp_power_control(link, true); link_enc->funcs->enable_dp_output( link_enc, link_settings, @@ -140,10 +140,10 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) if (signal == SIGNAL_TYPE_EDP) { link->dc->hwss.edp_backlight_control(link, false); edp_receiver_ready_T9(link); - link->link_enc->funcs->disable_output(link->link_enc, signal, link); - link->dc->hwss.edp_power_control(link->link_enc, false); + link->link_enc->funcs->disable_output(link->link_enc, signal); + link->dc->hwss.edp_power_control(link, false); } else - link->link_enc->funcs->disable_output(link->link_enc, signal, link); + link->link_enc->funcs->disable_output(link->link_enc, signal); /* Clear current link setting.*/ memset(&link->cur_link_settings, 0, @@ -286,8 +286,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, link->link_enc->funcs->disable_output( link->link_enc, - SIGNAL_TYPE_DISPLAY_PORT, - link); + SIGNAL_TYPE_DISPLAY_PORT); /* Clear current link setting. */ memset(&link->cur_link_settings, 0, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index fe88852b4774..bad70c6b3aad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -845,8 +845,6 @@ void dce110_link_encoder_hw_init( ASSERT(result == BP_RESULT_OK); - } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - ctx->dc->hwss.edp_power_control(enc, true); } aux_initialize(enc110); @@ -1033,8 +1031,7 @@ void dce110_link_encoder_enable_dp_mst_output( */ void dce110_link_encoder_disable_output( struct link_encoder *enc, - enum signal_type signal, - struct dc_link *link) + enum signal_type signal) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); struct dc_context *ctx = enc110->base.ctx; @@ -1045,8 +1042,6 @@ void dce110_link_encoder_disable_output( /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ return; } - if (enc110->base.connector.id == CONNECTOR_ID_EDP) - ctx->dc->hwss.edp_backlight_control(link, false); /* Power-down RX and disable GPU PHY should be paired. * Disabling PHY without powering down RX may cause * symbol lock loss, on which we will get DP Sink interrupt. */ @@ -1078,19 +1073,20 @@ void dce110_link_encoder_disable_output( if (dc_is_dp_signal(signal)) link_encoder_disable(enc110); - if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - /* power down eDP panel */ - /* TODO: Power control cause regression, we should implement - * it properly, for now just comment it. - * - * link_encoder_edp_wait_for_hpd_ready( - link_enc, - link_enc->connector, - false); - - * link_encoder_edp_power_control( - link_enc, false); */ - } + /* + * TODO: Power control cause regression, we should implement + * it properly, for now just comment it. + */ +// if (enc110->base.connector.id == CONNECTOR_ID_EDP) { +// /* power down eDP panel */ +// link_encoder_edp_wait_for_hpd_ready( +// enc, +// enc->connector, +// false); +// +// link_encoder_edp_power_control( +// enc, false); +// } } void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 494067dedd03..8ca9afe47a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -228,9 +228,8 @@ void dce110_link_encoder_enable_dp_mst_output( /* disable PHY output */ void dce110_link_encoder_disable_output( - struct link_encoder *link_enc, - enum signal_type signal, - struct dc_link *link); + struct link_encoder *enc, + enum signal_type signal); /* set DP lane settings */ void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 868040a4f7ff..44315aef445b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -814,11 +814,11 @@ static enum bp_result link_transmitter_control( * eDP only. */ void hwss_edp_wait_for_hpd_ready( - struct link_encoder *enc, - bool power_up) + struct dc_link *link, + bool power_up) { - struct dc_context *ctx = enc->ctx; - struct graphics_object_id connector = enc->connector; + struct dc_context *ctx = link->ctx; + struct graphics_object_id connector = link->link_enc->connector; struct gpio *hpd; bool edp_hpd_high = false; uint32_t time_elapsed = 0; @@ -882,16 +882,16 @@ void hwss_edp_wait_for_hpd_ready( } void hwss_edp_power_control( - struct link_encoder *enc, - bool power_up) + struct dc_link *link, + bool power_up) { - struct dc_context *ctx = enc->ctx; + struct dc_context *ctx = link->ctx; struct dce_hwseq *hwseq = ctx->dc->hwseq; struct bp_transmitter_control cntl = { 0 }; enum bp_result bp_result; - if (dal_graphics_object_id_get_connector_id(enc->connector) + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); return; @@ -907,11 +907,11 @@ void hwss_edp_power_control( cntl.action = power_up ? TRANSMITTER_CONTROL_POWER_ON : TRANSMITTER_CONTROL_POWER_OFF; - cntl.transmitter = enc->transmitter; - cntl.connector_obj_id = enc->connector; + cntl.transmitter = link->link_enc->transmitter; + cntl.connector_obj_id = link->link_enc->connector; cntl.coherent = false; cntl.lanes_number = LANE_COUNT_FOUR; - cntl.hpd_sel = enc->hpd_source; + cntl.hpd_sel = link->link_enc->hpd_source; bp_result = link_transmitter_control(ctx->dc_bios, &cntl); @@ -925,7 +925,7 @@ void hwss_edp_power_control( __func__, (power_up ? "On":"Off")); } - hwss_edp_wait_for_hpd_ready(enc, true); + hwss_edp_wait_for_hpd_ready(link, true); } /*todo: cloned in stream enc, fix*/ @@ -934,14 +934,14 @@ void hwss_edp_power_control( * eDP only. Control the backlight of the eDP panel */ void hwss_edp_backlight_control( - struct dc_link *link, - bool enable) + struct dc_link *link, + bool enable) { - struct dce_hwseq *hws = link->dc->hwseq; - struct dc_context *ctx = link->dc->ctx; + struct dc_context *ctx = link->ctx; + struct dce_hwseq *hws = ctx->dc->hwseq; struct bp_transmitter_control cntl = { 0 }; - if (dal_graphics_object_id_get_connector_id(link->link_id) + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); return; @@ -982,7 +982,7 @@ void hwss_edp_backlight_control( * Enable it in the future if necessary. */ /* dc_service_sleep_in_milliseconds(50); */ - link_transmitter_control(link->dc->ctx->dc_bios, &cntl); + link_transmitter_control(ctx->dc_bios, &cntl); } void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) @@ -1396,12 +1396,14 @@ static void power_down_encoders(struct dc *dc) if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(dc->links[i], false); - if (connector_id == CONNECTOR_ID_EDP) + if (connector_id == CONNECTOR_ID_EDP) { signal = SIGNAL_TYPE_EDP; + hwss_edp_backlight_control(dc->links[i], false); + } } dc->links[i]->link_enc->funcs->disable_output( - dc->links[i]->link_enc, signal, dc->links[i]); + dc->links[i]->link_enc, signal); } } @@ -2541,6 +2543,10 @@ static void init_hw(struct dc *dc) * required signal (which may be different from the * default signal on connector). */ struct dc_link *link = dc->links[i]; + + if (link->link_enc->connector.id == CONNECTOR_ID_EDP) + dc->hwss.edp_power_control(link, true); + link->link_enc->funcs->hw_init(link->link_enc); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 4d72bb99be93..2dd6ac637572 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -70,8 +70,8 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); void hwss_edp_power_control( - struct link_encoder *enc, - bool power_up); + struct dc_link *link, + bool power_up); void hwss_edp_backlight_control( struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index bb4446eecb39..43d4bfd47ec8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -723,6 +723,9 @@ static void dcn10_init_hw(struct dc *dc) */ struct dc_link *link = dc->links[i]; + if (link->link_enc->connector.id == CONNECTOR_ID_EDP) + dc->hwss.edp_power_control(link, true); + link->link_enc->funcs->hw_init(link->link_enc); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 3d33bcda7059..8a08f0a97f94 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -111,7 +111,7 @@ struct link_encoder_funcs { const struct dc_link_settings *link_settings, enum clock_source_id clock_source); void (*disable_output)(struct link_encoder *link_enc, - enum signal_type signal, struct dc_link *link); + enum signal_type signal); void (*dp_set_lane_settings)(struct link_encoder *enc, const struct link_training_settings *link_settings); void (*dp_set_phy_pattern)(struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index cebbba345889..f3c5468854bd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -184,7 +184,7 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); void (*edp_power_control)( - struct link_encoder *enc, + struct dc_link *link, bool enable); void (*edp_backlight_control)( struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 88c2bde3f039..57a54a7b89e5 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -58,8 +58,7 @@ static void virtual_link_encoder_enable_dp_mst_output( static void virtual_link_encoder_disable_output( struct link_encoder *link_enc, - enum signal_type signal, - struct dc_link *link) {} + enum signal_type signal) {} static void virtual_link_encoder_dp_set_lane_settings( struct link_encoder *enc, -- cgit v1.2.3-59-g8ed1b From e6c258cb4e6fbc7500c493df22f52e1046c575b0 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 30 Oct 2017 17:32:14 -0400 Subject: drm/amd/display: Refactor disable front end pipes. There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 3 + drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 262 +++++++++++---------- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- 5 files changed, 154 insertions(+), 138 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6d64a069648e..88a004cc2690 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1064,6 +1064,9 @@ bool dcn_validate_bandwidth( hsplit_pipe->stream = NULL; hsplit_pipe->top_pipe = NULL; hsplit_pipe->bottom_pipe = NULL; + /* Clear plane_res and stream_res */ + memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); + memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); resource_build_scaling_params(pipe); } /* for now important to do this after pipe split for building e2e params */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f3496881caf4..39431bd8d77e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -963,9 +963,11 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) post_surface_trace(dc); for (i = 0; i < dc->res_pool->pipe_count; i++) - if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].plane_state == NULL) - dc->hwss.power_down_front_end(dc, i); + if (context->res_ctx.pipe_ctx[i].stream == NULL || + context->res_ctx.pipe_ctx[i].plane_state == NULL) { + context->res_ctx.pipe_ctx[i].pipe_idx = i; + dc->hwss.power_down_front_end(dc, &context->res_ctx.pipe_ctx[i]); + } /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -1339,8 +1341,11 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; - if (!pipe_ctx->top_pipe && pipe_ctx->stream) { - struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); + if (!pipe_ctx->top_pipe && + pipe_ctx->stream && + pipe_ctx->stream == stream) { + struct dc_stream_status *stream_status = + stream_get_status(context, pipe_ctx->stream); dc->hwss.apply_ctx_for_surface( dc, pipe_ctx->stream, stream_status->plane_count, context); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 44315aef445b..73c38c93f5df 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1464,7 +1464,9 @@ static void disable_vga_and_power_gate_all_controllers( enable_display_pipe_clock_gating(ctx, true); - dc->hwss.power_down_front_end(dc, i); + dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; + dc->hwss.power_down_front_end(dc, + &dc->current_state->res_ctx.pipe_ctx[i]); } } @@ -1890,7 +1892,7 @@ static void dce110_reset_hw_ctx_wrap( if (old_clk) old_clk->funcs->cs_power_down(old_clk); - dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); + dc->hwss.power_down_front_end(dc, pipe_ctx_old); pipe_ctx_old->stream = NULL; } @@ -2950,8 +2952,10 @@ static void dce110_apply_ctx_for_surface( } } -static void dce110_power_down_fe(struct dc *dc, int fe_idx) +static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; + /* Do not power down fe when stream is active on dce*/ if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) return; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 680aabda3277..1c536884c080 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -558,13 +558,15 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc) } /* trigger HW to start disconnect plane from stream on the next vsync */ -static void plane_atomic_disconnect(struct dc *dc, - int fe_idx) +static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id, z_idx; int mpcc_id = -1; + struct timing_generator *tg = pipe_ctx->stream_res.tg; + struct dce_hwseq *hws = dc->hwseq; /* look at tree rather than mi here to know if we already reset */ for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) { @@ -583,29 +585,56 @@ static void plane_atomic_disconnect(struct dc *dc, if (opp_id == dc->res_pool->pipe_count) return; - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - hubp->funcs->dcc_control(hubp, false, false); + mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), + dc->res_pool->opps[opp_id]->inst, fe_idx); + + if (hubp->funcs->hubp_disconnect) + hubp->funcs->hubp_disconnect(hubp); + if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), - dc->res_pool->opps[opp_id]->inst, fe_idx); + if (pipe_ctx->top_pipe) { + pipe_ctx->top_pipe->bottom_pipe = NULL; + pipe_ctx->top_pipe = NULL; + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + } + + if (pipe_ctx->bottom_pipe) { + pipe_ctx->bottom_pipe->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; + } + pipe_ctx->plane_state = NULL; + + /* TODO: Move to tg. */ + REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], + VUPDATE_NO_LOCK_EVENT_CLEAR, 1); } /* disable HW used by plane. * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct dc *dc, - int fe_idx) +static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id = hubp->opp_id; + struct timing_generator *tg = pipe_ctx->stream_res.tg; + + if (tg == NULL) + return; if (opp_id == 0xf) return; + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], + VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, + 1, 100000); + mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; /*dm_logger_write(dc->ctx->logger, LOG_ERROR, @@ -630,62 +659,52 @@ static void plane_atomic_disable(struct dc *dc, dcn10_verify_allow_pstate_change_high(dc); } -static void reset_front_end( - struct dc *dc, - int fe_idx) +/* kill power to plane hw + * note: cannot power down until plane is disable + */ +static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; - struct timing_generator *tg; - int opp_id = dc->res_pool->hubps[fe_idx]->opp_id; + struct dpp *dpp = dc->res_pool->dpps[fe_idx]; - /*Already reset*/ - if (opp_id == 0xf) - return; + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 1); + dpp_pg_control(hws, fe_idx, false); + hubp_pg_control(hws, fe_idx, false); + dpp->funcs->dpp_reset(dpp); + REG_SET(DC_IP_REQUEST_CNTL, 0, + IP_REQUEST_EN, 0); + dm_logger_write(dc->ctx->logger, LOG_DEBUG, + "Power gated front end %d\n", fe_idx); + } +} - tg = dc->res_pool->timing_generators[opp_id]; - tg->funcs->lock(tg); +static void dcn10_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + int fe_idx = pipe_ctx->pipe_idx; + struct timing_generator *tg = pipe_ctx->stream_res.tg; - plane_atomic_disconnect(dc, fe_idx); + if (tg != NULL) { + tg->funcs->lock(tg); - REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); - tg->funcs->unlock(tg); + plane_atomic_disconnect(dc, pipe_ctx); - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); + tg->funcs->unlock(tg); - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], - VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, - 1, 100000); + if (dc->debug.sanity_checks) + dcn10_verify_allow_pstate_change_high(dc); - plane_atomic_disable(dc, fe_idx); + plane_atomic_disable(dc, pipe_ctx); + } + + plane_atomic_power_down(dc, fe_idx); dm_logger_write(dc->ctx->logger, LOG_DC, "Reset front end %d\n", fe_idx); } -static void dcn10_power_down_fe(struct dc *dc, int fe_idx) -{ - struct dce_hwseq *hws = dc->hwseq; - struct dpp *dpp = dc->res_pool->dpps[fe_idx]; - - reset_front_end(dc, fe_idx); - - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 1); - dpp_pg_control(hws, fe_idx, false); - hubp_pg_control(hws, fe_idx, false); - dpp->funcs->dpp_reset(dpp); - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 0); - dm_logger_write(dc->ctx->logger, LOG_DEBUG, - "Power gated front end %d\n", fe_idx); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); -} - static void dcn10_init_hw(struct dc *dc) { int i; @@ -744,7 +763,7 @@ static void dcn10_init_hw(struct dc *dc) tg->funcs->set_blank(tg, true); hwss_wait_for_blank_complete(tg); - dcn10_power_down_fe(dc, i); + plane_atomic_power_down(dc, i); tg->funcs->tg_init(tg); } @@ -1988,8 +2007,6 @@ static void program_all_pipe_in_tree( dcn10_verify_allow_pstate_change_high(dc); } - pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); - pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; @@ -2097,62 +2114,75 @@ static void ready_shared_resources(struct dc *dc, struct dc_state *context) dcn10_pplib_apply_display_requirements(dc, context); } +static struct pipe_ctx *find_top_pipe_for_stream( + struct dc *dc, + struct dc_state *context, + const struct dc_stream_state *stream) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) + continue; + + if (pipe_ctx->stream != stream) + continue; + + if (!pipe_ctx->top_pipe) + return pipe_ctx; + } + return NULL; +} + static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct dc_state *context) { - int i, be_idx; + int i; + struct timing_generator *tg; + bool removed_pipe[4] = { false }; + + struct pipe_ctx *top_pipe_to_program = + find_top_pipe_for_stream(dc, context, stream); + + if (!top_pipe_to_program) + return; + + tg = top_pipe_to_program->stream_res.tg; if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - be_idx = -1; - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; - break; - } - } - - ASSERT(be_idx != -1); + tg->funcs->lock(tg); if (num_planes == 0) { - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { - old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); - dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx); - } - } - return; + /* OTG blank before remove all front end */ + tg->funcs->set_blank(tg, true); } - /* reset unused mpcc */ + /* Disconnect unused mpcc */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - struct hubp *hubp = dc->res_pool->hubps[i]; - - if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) - continue; - - if (pipe_ctx->stream_res.tg && - pipe_ctx->stream_res.tg->inst == be_idx && - !pipe_ctx->top_pipe) - pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); - /* * Powergate reused pipes that are not powergated * fairly hacky right now, using opp_id as indicator + * TODO: After move dc_post to dc_update, this will + * be removed. */ - if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { - if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) { - dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); + if (old_pipe_ctx->stream_res.tg == tg && + old_pipe_ctx->plane_res.hubp && + old_pipe_ctx->plane_res.hubp->opp_id != 0xf) { + dcn10_power_down_fe(dc, pipe_ctx); /* * power down fe will unlock when calling reset, need * to lock it back here. Messy, need rework. @@ -2161,39 +2191,12 @@ static void dcn10_apply_ctx_for_surface( } } + if (!pipe_ctx->plane_state && + old_pipe_ctx->plane_state && + old_pipe_ctx->stream_res.tg == tg) { - if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) - || (!pipe_ctx->stream && old_pipe_ctx->stream)) { - if (old_pipe_ctx->stream_res.tg->inst != be_idx) - continue; - - if (!old_pipe_ctx->top_pipe) { - ASSERT(0); - continue; - } - - /* reset mpc */ - dc->res_pool->mpc->funcs->remove( - dc->res_pool->mpc, - &(old_pipe_ctx->stream_res.opp->mpc_tree), - old_pipe_ctx->stream_res.opp->inst, - old_pipe_ctx->pipe_idx); - old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true; - - /*dm_logger_write(dc->ctx->logger, LOG_ERROR, - "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", - old_pipe_ctx->mpcc->inst);*/ - - if (hubp->funcs->hubp_disconnect) - hubp->funcs->hubp_disconnect(hubp); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - - old_pipe_ctx->top_pipe = NULL; - old_pipe_ctx->bottom_pipe = NULL; - old_pipe_ctx->plane_state = NULL; - old_pipe_ctx->stream = NULL; + plane_atomic_disconnect(dc, old_pipe_ctx); + removed_pipe[i] = true; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset mpcc for pipe %d\n", @@ -2201,23 +2204,24 @@ static void dcn10_apply_ctx_for_surface( } } - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (num_planes > 0) + program_all_pipe_in_tree(dc, top_pipe_to_program, context); + + tg->funcs->unlock(tg); - if (pipe_ctx->stream != stream) - continue; - /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) { - program_all_pipe_in_tree(dc, pipe_ctx, context); - if (pipe_ctx->stream_res.tg && - pipe_ctx->stream_res.tg->inst == be_idx && - (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) - pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *old_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[i]; + + if (removed_pipe[i]) { + plane_atomic_disable(dc, old_pipe_ctx); + if (num_planes == 0) + plane_atomic_power_down(dc, i); } } + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index f3c5468854bd..19cfca91bb4e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -129,7 +129,7 @@ struct hw_sequencer_funcs { struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct dc *dc, int fe_idx); + void (*power_down_front_end)(struct dc *dc, struct pipe_ctx *pipe_ctx); void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, -- cgit v1.2.3-59-g8ed1b From efd5220405df0acd43eb7e16948e92eec87ce2cb Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 14:34:13 -0400 Subject: drm/amd/display: Bunch of indentation cleanups in color stuff Trying to align with kernel coding style and make it a bit more readable. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 170 ++++++++------------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +- 2 files changed, 68 insertions(+), 112 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index ae32af31eff1..4ff874a43f7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1260,124 +1260,87 @@ static void program_pwl( REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); } -static void regamma_config_regions_and_segments( - struct dce_transform *xfm_dce, - const struct pwl_params *params) +static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, + const struct pwl_params *params) { const struct gamma_curve *curve; - { - REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, - REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - } - { - REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); - - } - { - REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, - REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - } - { - REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, - REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); - } - - curve = params->arr_curve_points; + REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - { - REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } + REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); - curve += 2; + REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, + REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - { - REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, + REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); - } + curve = params->arr_curve_points; + REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } + REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + curve += 2; + REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } + REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); } -void dce110_opp_program_regamma_pwl( - struct transform *xfm, - const struct pwl_params *params) +void dce110_opp_program_regamma_pwl(struct transform *xfm, + const struct pwl_params *params) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); @@ -1388,9 +1351,8 @@ void dce110_opp_program_regamma_pwl( program_pwl(xfm_dce, params); } -void dce110_opp_power_on_regamma_lut( - struct transform *xfm, - bool power_on) +void dce110_opp_power_on_regamma_lut(struct transform *xfm, + bool power_on) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); @@ -1406,29 +1368,25 @@ void dce110_opp_power_on_regamma_lut( } void dce110_opp_set_regamma_mode(struct transform *xfm, - enum opp_regamma mode) + enum opp_regamma mode) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); REG_SET(REGAMMA_CONTROL, 0, - GRPH_REGAMMA_MODE, mode); + GRPH_REGAMMA_MODE, mode); } static const struct transform_funcs dce_transform_funcs = { .transform_reset = dce_transform_reset, - .transform_set_scaler = - dce_transform_set_scaler, - .transform_set_gamut_remap = - dce_transform_set_gamut_remap, + .transform_set_scaler = dce_transform_set_scaler, + .transform_set_gamut_remap = dce_transform_set_gamut_remap, .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, .opp_set_csc_default = dce110_opp_set_csc_default, .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, .opp_set_regamma_mode = dce110_opp_set_regamma_mode, - .transform_set_pixel_storage_depth = - dce_transform_set_pixel_storage_depth, - .transform_get_optimal_number_of_taps = - dce_transform_get_optimal_number_of_taps + .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth, + .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 73c38c93f5df..3002978c860e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -650,13 +650,11 @@ static bool dce110_set_output_transfer_func( xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && - stream->out_transfer_func->type == - TF_TYPE_PREDEFINED && - stream->out_transfer_func->tf == - TRANSFER_FUNCTION_SRGB) { + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); - } else if (dce110_translate_regamma_to_hw_format( - stream->out_transfer_func, &xfm->regamma_params)) { + } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, + &xfm->regamma_params)) { xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { -- cgit v1.2.3-59-g8ed1b From a6114e854c55c928b9b8bcf7014eb205bd112c68 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 16:27:59 -0400 Subject: drm/amd/display: Fix some more color indentations Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++---- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 35 +++++++---------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 44 ++++++++-------------- 4 files changed, 36 insertions(+), 61 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8360d17125ae..80567aa1968e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2142,6 +2142,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, const struct drm_connector *connector) { struct dc_crtc_timing *timing_out = &stream->timing; + struct dc_transfer_func *tf = dc_create_transfer_func(); memset(timing_out, 0, sizeof(struct dc_crtc_timing)); @@ -2185,13 +2186,9 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, stream->output_color_space = get_output_color_space(timing_out); - { - struct dc_transfer_func *tf = dc_create_transfer_func(); - - tf->type = TF_TYPE_PREDEFINED; - tf->tf = TRANSFER_FUNCTION_SRGB; - stream->out_transfer_func = tf; - } + tf->type = TF_TYPE_PREDEFINED; + tf->tf = TRANSFER_FUNCTION_SRGB; + stream->out_transfer_func = tf; } static void fill_audio_info(struct audio_info *audio_info, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 39431bd8d77e..f3397ff17345 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1376,10 +1376,9 @@ static void commit_planes_for_stream(struct dc *dc, continue; /* work around to program degamma regs for split pipe after set mode. */ - if (srf_updates[i].in_transfer_func || (pipe_ctx->top_pipe && - pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); + if (srf_updates[i].in_transfer_func || + (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3002978c860e..1ec008404784 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -257,9 +257,9 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } -static bool dce110_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) +static bool +dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; const struct dc_transfer_func *tf = NULL; @@ -280,25 +280,19 @@ static bool dce110_set_input_transfer_func( if (tf == NULL) { /* Default case if no input transfer function specified */ - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_sRGB); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); } else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_sRGB); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_xvYCC); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_BYPASS); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: - result = false; - break; default: result = false; break; @@ -640,9 +634,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func return true; } -static bool dce110_set_output_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream) +static bool +dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->plane_res.xfm; @@ -2756,8 +2750,7 @@ static void dce110_program_front_end_for_pipe( struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; - struct pipe_ctx *cur_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; unsigned int i; memset(&tbl_entry, 0, sizeof(tbl_entry)); @@ -2850,10 +2843,8 @@ static void dce110_program_front_end_for_pipe( /* Moved programming gamma from dc to hwss */ if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } dm_logger_write(dc->ctx->logger, LOG_SURFACE, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1c536884c080..99f478c52421 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -874,8 +874,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; } -static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) +static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { struct dpp *dpp_base = pipe_ctx->plane_res.dpp; const struct dc_transfer_func *tf = NULL; @@ -888,28 +888,22 @@ static bool dcn10_set_input_transfer_func( tf = plane_state->in_transfer_func; if (plane_state->gamma_correction && dce_use_lut(plane_state)) - dpp_base->funcs->dpp_program_input_lut(dpp_base, - plane_state->gamma_correction); + dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); if (tf == NULL) dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - dpp_base->funcs->dpp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_HW_sRGB); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - dpp_base->funcs->dpp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_HW_xvYCC); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - dpp_base->funcs->dpp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: - result = false; - break; default: result = false; break; @@ -1238,9 +1232,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func return true; } -static bool dcn10_set_output_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream) +static bool +dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) { struct dpp *dpp = pipe_ctx->plane_res.dpp; @@ -1250,17 +1244,13 @@ static bool dcn10_set_output_transfer_func( dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && - stream->out_transfer_func->type == - TF_TYPE_PREDEFINED && - stream->out_transfer_func->tf == - TRANSFER_FUNCTION_SRGB) { + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); - } else if (dcn10_translate_regamma_to_hw_format( - stream->out_transfer_func, &dpp->regamma_params)) { - dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); - } else { + else if (dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, &dpp->regamma_params)) + dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER); + else dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); - } return true; } @@ -2047,10 +2037,8 @@ static void program_all_pipe_in_tree( } if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } } -- cgit v1.2.3-59-g8ed1b From 631aaa0af4be3de8f0184095075650afaa023334 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Tue, 31 Oct 2017 15:55:15 -0400 Subject: drm/amd/display: send display_count msg so SMU can enter S0i2 SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++++++++++-- drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ++++ 5 files changed, 23 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e59e7028ad57..5745304b5af5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -389,11 +389,19 @@ void set_dpms( if (stream->dpms_off != dpms_off) { stream->dpms_off = dpms_off; - if (dpms_off) + + if (dpms_off) { core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE); - else + + dc->hwss.pplib_apply_display_requirements( + dc, dc->current_state); + } else { + dc->hwss.pplib_apply_display_requirements( + dc, dc->current_state); + core_link_enable_stream(dc->current_state, pipe_ctx); + } } } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index e7a694835e3e..469af0587604 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -148,5 +148,7 @@ void dce100_hw_sequencer_construct(struct dc *dc) dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.set_bandwidth = dce100_set_bandwidth; + dc->hwss.pplib_apply_display_requirements = + dce100_pplib_apply_display_requirements; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1ec008404784..d22745e6dff0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2595,6 +2595,10 @@ void dce110_fill_display_configs( ASSERT(pipe_ctx != NULL); + /* only notify active stream */ + if (stream->dpms_off) + continue; + num_cfgs++; cfg->signal = pipe_ctx->stream->signal; cfg->pipe_idx = pipe_ctx->pipe_idx; @@ -3024,6 +3028,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .pplib_apply_display_requirements = pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 5d1fb1c297a3..73e7afb360b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2567,6 +2567,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .pplib_apply_display_requirements = + dcn10_pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 19cfca91bb4e..1d8852683f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -183,12 +183,16 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); + void (*pplib_apply_display_requirements)( + struct dc *dc, + struct dc_state *context); void (*edp_power_control)( struct dc_link *link, bool enable); void (*edp_backlight_control)( struct dc_link *link, bool enable); + }; void color_space_to_black_color( -- cgit v1.2.3-59-g8ed1b From 97110c98a0fa2091190dc3068734ef9f1c12b588 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 14:41:41 -0400 Subject: drm/amd/display: Remove extra arr_points element arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by: Harry Wentland Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ------- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ------- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 +- 5 files changed, 3 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 4ff874a43f7a..543b4901e987 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1277,7 +1277,7 @@ static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope); curve = params->arr_curve_points; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index d22745e6dff0..6b3ab4320b0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -539,8 +539,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), dal_fixed31_32_from_int(segment_end)); - arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -563,10 +561,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); arr_points[1].y = y3_max; - arr_points[2].y = y3_max; arr_points[1].slope = dal_fixed31_32_zero; - arr_points[2].slope = dal_fixed31_32_zero; if (output_tf->tf == TRANSFER_FUNCTION_PQ) { /* for PQ, we want to have a straight line from last HW X point, @@ -578,9 +574,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func arr_points[1].slope = dal_fixed31_32_div( dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), dal_fixed31_32_sub(end_value, arr_points[1].x)); - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index e98ed3058ea2..9b65b77e8823 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -175,7 +175,7 @@ static void regamma_config_regions_and_segments( value = 0; set_reg_field_value( value, - params->arr_points[2].custom_float_slope, + params->arr_points[1].custom_float_slope, GAMMA_CORR_CNTLA_END_CNTL2, GAMMA_CORR_CNTLA_EXP_REGION_END_BASE); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 666c6c0f882a..c4a6ad3f7e25 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1158,8 +1158,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), dal_fixed31_32_from_int(segment_end)); - arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -1181,10 +1179,8 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); arr_points[1].y = y3_max; - arr_points[2].y = y3_max; arr_points[1].slope = dal_fixed31_32_zero; - arr_points[2].slope = dal_fixed31_32_zero; if (output_tf->tf == TRANSFER_FUNCTION_PQ) { /* for PQ, we want to have a straight line from last HW X point, @@ -1196,9 +1192,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func arr_points[1].slope = dal_fixed31_32_div( dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), dal_fixed31_32_sub(end_value, arr_points[1].x)); - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index fa3d100de264..a650ede413d1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -73,7 +73,7 @@ struct pwl_result_data { struct pwl_params { struct gamma_curve arr_curve_points[34]; - struct curve_points arr_points[3]; + struct curve_points arr_points[2]; struct pwl_result_data rgb_resulted[256 + 3]; uint32_t hw_points_num; }; -- cgit v1.2.3-59-g8ed1b From b310b081ad744dca288af33ef8331796840a1da2 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 31 Oct 2017 15:16:56 -0400 Subject: drm/amd/display: Bunch more color indentation cleanups Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 104 ++++++++++----------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 54 ++++------- 2 files changed, 69 insertions(+), 89 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 543b4901e987..97414abbc69d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1183,81 +1183,75 @@ static void program_pwl( { uint32_t value; int retval; + uint8_t max_tries = 10; + uint8_t counter = 0; + uint32_t i = 0; + const struct pwl_result_data *rgb = params->rgb_resulted; - { - uint8_t max_tries = 10; - uint8_t counter = 0; + /* Power on LUT memory */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 1); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - /* Power on LUT memory */ - if (REG(DCFE_MEM_PWR_CTRL)) - REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 1); - else - REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - - while (counter < max_tries) { - if (REG(DCFE_MEM_PWR_STATUS)) { - value = REG_READ(DCFE_MEM_PWR_STATUS); - REG_GET(DCFE_MEM_PWR_STATUS, - DCP_REGAMMA_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } else { - value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); - REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } + while (counter < max_tries) { + if (REG(DCFE_MEM_PWR_STATUS)) { + value = REG_READ(DCFE_MEM_PWR_STATUS); + REG_GET(DCFE_MEM_PWR_STATUS, + DCP_REGAMMA_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } else { + value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); + REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; } + } - if (counter == max_tries) { - dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, + if (counter == max_tries) { + dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, "%s: regamma lut was not powered on " "in a timely manner," " programming still proceeds\n", __func__); - } } REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, - REGAMMA_LUT_WRITE_EN_MASK, 7); + REGAMMA_LUT_WRITE_EN_MASK, 7); REG_WRITE(REGAMMA_LUT_INDEX, 0); /* Program REGAMMA_LUT_DATA */ - { - uint32_t i = 0; - const struct pwl_result_data *rgb = params->rgb_resulted; + while (i != params->hw_points_num) { - while (i != params->hw_points_num) { + REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); - - ++rgb; - ++i; - } + ++rgb; + ++i; } /* we are done with DCP LUT memory; re-enable low power mode */ if (REG(DCFE_MEM_PWR_CTRL)) REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 0); + DCP_REGAMMA_MEM_PWR_DIS, 0); else REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); + REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); } static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, @@ -1358,12 +1352,12 @@ void dce110_opp_power_on_regamma_lut(struct transform *xfm, if (REG(DCFE_MEM_PWR_CTRL)) REG_UPDATE_2(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, power_on, - DCP_LUT_MEM_PWR_DIS, power_on); + DCP_REGAMMA_MEM_PWR_DIS, power_on, + DCP_LUT_MEM_PWR_DIS, power_on); else REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, - DCP_LUT_LIGHT_SLEEP_DIS, power_on); + REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, + DCP_LUT_LIGHT_SLEEP_DIS, power_on); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6b3ab4320b0c..97630fcd230f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -432,8 +432,9 @@ static bool convert_to_custom_float( return true; } -static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params) +static bool +dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, + struct pwl_params *regamma_params) { struct curve_points *arr_points; struct pwl_result_data *rgb_resulted; @@ -448,8 +449,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t segment_start, segment_end; uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL || - output_tf->type == TF_TYPE_BYPASS) + if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; arr_points = regamma_params->arr_points; @@ -528,17 +528,14 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func /* last point */ start_index = (segment_end + 25) * 32; - rgb_resulted[hw_points - 1].red = - output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = - output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = - output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); + dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); + dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -547,9 +544,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, + arr_points[0].x); y_r = rgb_resulted[hw_points - 1].red; y_g = rgb_resulted[hw_points - 1].green; @@ -568,12 +564,11 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func /* for PQ, we want to have a straight line from last HW X point, * and the slope to be such that we hit 1.0 at 10000 nits. */ - const struct fixed31_32 end_value = - dal_fixed31_32_from_int(125); + const struct fixed31_32 end_value = dal_fixed31_32_from_int(125); arr_points[1].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); + dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), + dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; @@ -581,18 +576,15 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func i = 1; for (k = 0; k < 16 && i < 16; k++) { if (seg_distr[k] != -1) { - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k]. - offset + (1 << seg_distr[k]); + regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); } i++; } if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; @@ -607,15 +599,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) rgb_plus_1->blue = rgb->blue; - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); ++rgb_plus_1; ++rgb; -- cgit v1.2.3-59-g8ed1b From bd1be8e894e4963595a35ebeff512dc63d3ee328 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 1 Nov 2017 14:31:58 -0400 Subject: drm/amd/display: A few more color indentation changes Signed-off-by: Harry Wentland Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 33 +++--- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 5 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 79 +++++--------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 25 ++--- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 115 +++++++-------------- 6 files changed, 96 insertions(+), 165 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index d618fdd0cc82..d737e911971b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -135,36 +135,34 @@ static void dce_ipp_cursor_set_attributes( } -static void dce_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params) +static void dce_ipp_program_prescale(struct input_pixel_processor *ipp, + struct ipp_prescale_params *params) { struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); /* set to bypass mode first before change */ REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, - 1); + GRPH_PRESCALE_BYPASS, 1); REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, - GRPH_PRESCALE_SCALE_R, params->scale, - GRPH_PRESCALE_BIAS_R, params->bias); + GRPH_PRESCALE_SCALE_R, params->scale, + GRPH_PRESCALE_BIAS_R, params->bias); REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, - GRPH_PRESCALE_SCALE_G, params->scale, - GRPH_PRESCALE_BIAS_G, params->bias); + GRPH_PRESCALE_SCALE_G, params->scale, + GRPH_PRESCALE_BIAS_G, params->bias); REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, - GRPH_PRESCALE_SCALE_B, params->scale, - GRPH_PRESCALE_BIAS_B, params->bias); + GRPH_PRESCALE_SCALE_B, params->scale, + GRPH_PRESCALE_BIAS_B, params->bias); if (params->mode != IPP_PRESCALE_MODE_BYPASS) { REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, 0); + GRPH_PRESCALE_BYPASS, 0); /* If prescale is in use, then legacy lut should be bypassed */ REG_UPDATE(INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE, 1); + GRPH_INPUT_GAMMA_MODE, 1); } } @@ -223,13 +221,12 @@ static void dce_ipp_set_degamma( struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; - ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || - mode == IPP_DEGAMMA_MODE_HW_sRGB); + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); REG_SET_3(DEGAMMA_CONTROL, 0, - GRPH_DEGAMMA_MODE, degamma_type, - CURSOR_DEGAMMA_MODE, degamma_type, - CURSOR2_DEGAMMA_MODE, degamma_type); + GRPH_DEGAMMA_MODE, degamma_type, + CURSOR_DEGAMMA_MODE, degamma_type, + CURSOR2_DEGAMMA_MODE, degamma_type); } static const struct ipp_funcs dce_ipp_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 330dbe9989d4..0f662e6ee9bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1177,9 +1177,8 @@ void dce110_opp_set_csc_default( default_adjust->out_color_space); } -static void program_pwl( - struct dce_transform *xfm_dce, - const struct pwl_params *params) +static void program_pwl(struct dce_transform *xfm_dce, + const struct pwl_params *params) { int retval; uint8_t max_tries = 10; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 97630fcd230f..4f321507ba06 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -307,10 +307,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, return result; } -static bool convert_to_custom_float( - struct pwl_result_data *rgb_resulted, - struct curve_points *arr_points, - uint32_t hw_points_num) +static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, + struct curve_points *arr_points, + uint32_t hw_points_num) { struct custom_float_format fmt; @@ -322,26 +321,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 12; fmt.sign = true; - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -349,26 +342,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 10; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[2].slope, - &fmt, - &arr_points[2].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[2].slope, &fmt, + &arr_points[2].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -377,50 +364,38 @@ static bool convert_to_custom_float( fmt.sign = true; while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { BREAK_TO_DEBUGGER(); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index d8929b31e5ba..8df3945370cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -213,8 +213,8 @@ static void dpp1_cm_set_regamma_pwl( else dpp1_cm_program_regamma_lutb_settings(dpp_base, params); - dpp1_cm_program_regamma_lut( - dpp_base, params->rgb_resulted, params->hw_points_num); + dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, + params->hw_points_num); dpp->pwl_data = *params; re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index bb430c0ec1b6..b4892f43cd77 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -365,34 +365,31 @@ void dpp1_cm_set_output_csc_adjustment( dpp1_cm_program_color_matrix(dpp, tbl_entry); } -void dpp1_cm_power_on_regamma_lut( - struct dpp *dpp_base, - bool power_on) +void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, + bool power_on) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + REG_SET(CM_MEM_PWR_CTRL, 0, - RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); + RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); } -void dpp1_cm_program_regamma_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) +void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, + const struct pwl_result_data *rgb, + uint32_t num) { uint32_t i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + for (i = 0 ; i < num; i++) { REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c4a6ad3f7e25..cb73d25aca4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -953,26 +953,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 12; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -980,26 +974,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 10; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].slope, - &fmt, - &arr_points[1].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, + &arr_points[1].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -1008,50 +996,38 @@ static bool convert_to_custom_float( fmt.sign = true; while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { BREAK_TO_DEBUGGER(); return false; } @@ -1066,8 +1042,9 @@ static bool convert_to_custom_float( #define MAX_LOW_POINT 25 #define NUMBER_SEGMENTS 32 -static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params) +static bool +dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, + struct pwl_params *regamma_params) { struct curve_points *arr_points; struct pwl_result_data *rgb_resulted; @@ -1083,8 +1060,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t i; uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL || - output_tf->type == TF_TYPE_BYPASS) + if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; arr_points = regamma_params->arr_points; @@ -1147,17 +1123,14 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func /* last point */ start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS; - rgb_resulted[hw_points - 1].red = - output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = - output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = - output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); + dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); + dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -1166,9 +1139,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x); y_r = rgb_resulted[hw_points - 1].red; y_g = rgb_resulted[hw_points - 1].green; y_b = rgb_resulted[hw_points - 1].blue; @@ -1202,15 +1173,13 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k]. - offset + (1 << seg_distr[k]); + regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); } i++; } if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; @@ -1225,15 +1194,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) rgb_plus_1->blue = rgb->blue; - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); ++rgb_plus_1; ++rgb; -- cgit v1.2.3-59-g8ed1b From 7f914a62c94fb29b96a88d72c9a2688db95275cf Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Mon, 6 Nov 2017 14:40:31 -0500 Subject: drm/amd/display: Apply work around for stutter. Power on one plane after disable all the planes, for a hw bug work around to resolve stutter efficiency issue. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 153 +++++++++------------ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 10 +- 6 files changed, 84 insertions(+), 95 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4c078c284f90..7578b4a9ee5b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -974,7 +974,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) if (context->res_ctx.pipe_ctx[i].stream == NULL || context->res_ctx.pipe_ctx[i].plane_state == NULL) { context->res_ctx.pipe_ctx[i].pipe_idx = i; - dc->hwss.power_down_front_end(dc, &context->res_ctx.pipe_ctx[i]); + dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); } /* 3rd param should be true, temp w/a for RV*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 4f321507ba06..750bbe9edf5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1411,7 +1411,7 @@ static void disable_vga_and_power_gate_all_controllers( true); dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; - dc->hwss.power_down_front_end(dc, + dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); } } @@ -1838,7 +1838,7 @@ static void dce110_reset_hw_ctx_wrap( if (old_clk) old_clk->funcs->cs_power_down(old_clk); - dc->hwss.power_down_front_end(dc, pipe_ctx_old); + dc->hwss.disable_plane(dc, pipe_ctx_old); pipe_ctx_old->stream = NULL; } @@ -2063,8 +2063,8 @@ enum dc_status dce110_apply_ctx_to_hw( context, dc); - if (dc->hwss.power_on_front_end) - dc->hwss.power_on_front_end(dc, pipe_ctx, context); + if (dc->hwss.enable_plane) + dc->hwss.enable_plane(dc, pipe_ctx, context); if (DC_OK != status) return status; @@ -2969,7 +2969,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .unblank_stream = dce110_unblank_stream, .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, .enable_display_power_gating = dce110_enable_display_power_gating, - .power_down_front_end = dce110_power_down_fe, + .disable_plane = dce110_power_down_fe, .pipe_control_lock = dce_pipe_control_lock, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index cb73d25aca4c..7d1821fb3607 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -363,11 +363,8 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; - int pwr_status = 0; - REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status); - /* Don't need to blank if hubp is power gated*/ - if (pwr_status == 2) + if (!hws->wa_state.DEGVIDCN10_253_applied) return; hubp->funcs->set_blank(hubp, true); @@ -378,16 +375,29 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) hubp_pg_control(hws, 0, false); REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); + + hws->wa_state.DEGVIDCN10_253_applied = false; } static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; + int i; if (dc->debug.disable_stutter) return; + if (!hws->wa.DEGVIDCN10_253) + return; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!dc->res_pool->hubps[i]->power_gated) + return; + } + + /* all pipe power gated, apply work around to enable stutter. */ + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); @@ -396,6 +406,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) IP_REQUEST_EN, 0); hubp->funcs->set_hubp_blank_en(hubp, false); + hws->wa_state.DEGVIDCN10_253_applied = true; } static void bios_golden_init(struct dc *dc) @@ -592,61 +603,14 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) if (dc->debug.sanity_checks) dcn10_verify_allow_pstate_change_high(dc); - if (pipe_ctx->top_pipe) { - pipe_ctx->top_pipe->bottom_pipe = NULL; - pipe_ctx->top_pipe = NULL; - pipe_ctx->stream = NULL; - memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); - memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); - } - - if (pipe_ctx->bottom_pipe) { - pipe_ctx->bottom_pipe->top_pipe = NULL; - pipe_ctx->bottom_pipe = NULL; - } + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + pipe_ctx->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; pipe_ctx->plane_state = NULL; } -/* disable HW used by plane. - * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) -{ - int fe_idx = pipe_ctx->pipe_idx; - struct dce_hwseq *hws = dc->hwseq; - struct hubp *hubp = dc->res_pool->hubps[fe_idx]; - struct mpc *mpc = dc->res_pool->mpc; - int opp_id = hubp->opp_id; - - if (opp_id == 0xf) - return; - - mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); - dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; - /*dm_logger_write(dc->ctx->logger, LOG_ERROR, - "[debug_mpo: atomic disable finished on mpcc %d]\n", - fe_idx);*/ - - hubp->funcs->set_blank(hubp, true); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); - - REG_UPDATE(HUBP_CLK_CNTL[fe_idx], - HUBP_CLOCK_ENABLE, 0); - REG_UPDATE(DPP_CONTROL[fe_idx], - DPP_CLOCK_ENABLE, 0); - - if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 0); - - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); -} - -/* kill power to plane hw - * note: cannot power down until plane is disable - */ static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -665,29 +629,51 @@ static void plane_atomic_power_down(struct dc *dc, int fe_idx) } } -static void dcn10_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) +/* disable HW used by plane. + * note: cannot disable until disconnect is complete + */ +static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { int fe_idx = pipe_ctx->pipe_idx; - struct timing_generator *tg = pipe_ctx->stream_res.tg; - - if (tg != NULL) { - tg->funcs->lock(tg); + struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = dc->res_pool->hubps[fe_idx]; + struct mpc *mpc = dc->res_pool->mpc; + int opp_id = hubp->opp_id; + struct output_pixel_processor *opp; - plane_atomic_disconnect(dc, pipe_ctx); + if (opp_id != 0xf) { + mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); + opp = dc->res_pool->opps[hubp->opp_id]; + opp->mpcc_disconnect_pending[hubp->mpcc_id] = false; + hubp->funcs->set_blank(hubp, true); + } - tg->funcs->unlock(tg); + REG_UPDATE(HUBP_CLK_CNTL[fe_idx], + HUBP_CLOCK_ENABLE, 0); + REG_UPDATE(DPP_CONTROL[fe_idx], + DPP_CLOCK_ENABLE, 0); - if (dc->debug.sanity_checks) - dcn10_verify_allow_pstate_change_high(dc); + if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], + OPP_PIPE_CLOCK_EN, 0); - plane_atomic_disable(dc, pipe_ctx); - } + hubp->power_gated = true; plane_atomic_power_down(dc, fe_idx); +} + +static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated) + return; + + plane_atomic_disable(dc, pipe_ctx); + + apply_DEGVIDCN10_253_wa(dc); dm_logger_write(dc->ctx->logger, LOG_DC, - "Reset front end %d\n", - fe_idx); + "Power down front end %d\n", + pipe_ctx->pipe_idx); } static void dcn10_init_hw(struct dc *dc) @@ -780,8 +766,7 @@ static void dcn10_init_hw(struct dc *dc) struct timing_generator *tg = dc->res_pool->timing_generators[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - plane_atomic_disable(dc, pipe_ctx); - plane_atomic_power_down(dc, i); + dcn10_disable_plane(dc, pipe_ctx); pipe_ctx->stream_res.tg = NULL; pipe_ctx->plane_res.hubp = NULL; @@ -1468,7 +1453,7 @@ static void print_rq_dlg_ttu( ); } -static void dcn10_power_on_fe( +static void dcn10_enable_plane( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) @@ -1480,6 +1465,8 @@ static void dcn10_power_on_fe( dcn10_verify_allow_pstate_change_high(dc); } + undo_DEGVIDCN10_253_wa(dc); + power_on_plane(dc->hwseq, pipe_ctx->pipe_idx); @@ -1946,6 +1933,8 @@ static void update_dchubp_dpp( &plane_state->dcc, plane_state->horizontal_mirror); + hubp->power_gated = false; + dc->hwss.update_plane_addr(dc, pipe_ctx); if (is_pipe_tree_visible(pipe_ctx)) @@ -1988,7 +1977,7 @@ static void program_all_pipe_in_tree( struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - dcn10_power_on_fe(dc, pipe_ctx, context); + dcn10_enable_plane(dc, pipe_ctx, context); /* temporary dcn1 wa: * watermark update requires toggle after a/b/c/d sets are programmed @@ -2063,7 +2052,6 @@ static void dcn10_pplib_apply_display_requirements( static void optimize_shared_resources(struct dc *dc) { if (dc->current_state->stream_count == 0) { - apply_DEGVIDCN10_253_wa(dc); /* S0i2 message */ dcn10_pplib_apply_display_requirements(dc, dc->current_state); } @@ -2074,10 +2062,6 @@ static void optimize_shared_resources(struct dc *dc) static void ready_shared_resources(struct dc *dc, struct dc_state *context) { - if (dc->current_state->stream_count == 0 && - !dc->debug.disable_stutter) - undo_DEGVIDCN10_253_wa(dc); - /* S0i2 message */ if (dc->current_state->stream_count == 0 && context->stream_count != 0) @@ -2152,7 +2136,7 @@ static void dcn10_apply_ctx_for_surface( if (old_pipe_ctx->stream_res.tg == tg && old_pipe_ctx->plane_res.hubp && old_pipe_ctx->plane_res.hubp->opp_id != 0xf) { - dcn10_power_down_fe(dc, pipe_ctx); + dcn10_disable_plane(dc, pipe_ctx); /* * power down fe will unlock when calling reset, need * to lock it back here. Messy, need rework. @@ -2184,14 +2168,10 @@ static void dcn10_apply_ctx_for_surface( struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - if (removed_pipe[i]) { - plane_atomic_disable(dc, old_pipe_ctx); - if (num_planes == 0) - plane_atomic_power_down(dc, i); - } + if (removed_pipe[i] && num_planes == 0) + dcn10_disable_plane(dc, old_pipe_ctx); } - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" @@ -2514,8 +2494,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .disable_stream = dce110_disable_stream, .unblank_stream = dce110_unblank_stream, .enable_display_power_gating = dcn10_dummy_display_power_gating, - .power_down_front_end = dcn10_power_down_fe, - .power_on_front_end = dcn10_power_on_fe, + .disable_plane = dcn10_disable_plane, .pipe_control_lock = dcn10_pipe_control_lock, .set_bandwidth = dcn10_set_bandwidth, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 531402a50c2c..209499e5f53b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -677,6 +677,7 @@ static struct dce_hwseq *dcn10_hwseq_create( hws->regs = &hwseq_reg; hws->shifts = &hwseq_shift; hws->masks = &hwseq_mask; + hws->wa.DEGVIDCN10_253 = true; } return hws; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 3286585bd6cd..49b12f602e79 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -34,9 +34,12 @@ struct hubp { struct dc_plane_address request_address; struct dc_plane_address current_address; int inst; + + /* run time states */ int opp_id; int mpcc_id; struct dc_cursor_attributes curs_attr; + bool power_gated; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 1d8852683f1f..5dc4ecf618ff 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -39,6 +39,11 @@ enum pipe_gating_control { struct dce_hwseq_wa { bool blnd_crtc_trigger; + bool DEGVIDCN10_253; +}; + +struct hwseq_wa_state { + bool DEGVIDCN10_253_applied; }; struct dce_hwseq { @@ -47,6 +52,7 @@ struct dce_hwseq { const struct dce_hwseq_shift *shifts; const struct dce_hwseq_mask *masks; struct dce_hwseq_wa wa; + struct hwseq_wa_state wa_state; }; struct pipe_ctx; @@ -129,9 +135,9 @@ struct hw_sequencer_funcs { struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*power_on_front_end)(struct dc *dc, + void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe, struct dc_state *context); -- cgit v1.2.3-59-g8ed1b From 2194e3ae902a89579141d860d010d78d422cbc4f Mon Sep 17 00:00:00 2001 From: Roman Li Date: Tue, 7 Nov 2017 10:58:40 -0500 Subject: drm/amd/display: Fix unbalanced locking in surface apply also simplifying syntax and removing unused variable in dce110_apply_ctx_for_surface() Signed-off-by: Roman Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 750bbe9edf5c..09051dfe1844 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2849,22 +2849,19 @@ static void dce110_apply_ctx_for_surface( int num_planes, struct dc_state *context) { - int i, be_idx; + int i; if (num_planes == 0) return; - be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; + if (stream == pipe_ctx->stream) { if (!pipe_ctx->top_pipe && (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) dc->hwss.pipe_control_lock(dc, pipe_ctx, true); - break; } } -- cgit v1.2.3-59-g8ed1b From 8aa111e34deedded58cd8576755f31659ba676f5 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 10 Nov 2017 16:31:09 -0600 Subject: drm/amd/display/dc/dce110/dce110_mem_input_v: use swap macro in program_size_and_rotation Make use of the swap macro instead of _manually_ swapping values and remove unnecessary variable swap. This makes the code easier to read and maintain. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 28 +++++++--------------- 1 file changed, 8 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index a06c6024deb4..7bab8c6d2a73 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -237,26 +237,14 @@ static void program_size_and_rotation( if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) { - uint32_t swap; - swap = local_size.video.luma_size.x; - local_size.video.luma_size.x = - local_size.video.luma_size.y; - local_size.video.luma_size.y = swap; - - swap = local_size.video.luma_size.width; - local_size.video.luma_size.width = - local_size.video.luma_size.height; - local_size.video.luma_size.height = swap; - - swap = local_size.video.chroma_size.x; - local_size.video.chroma_size.x = - local_size.video.chroma_size.y; - local_size.video.chroma_size.y = swap; - - swap = local_size.video.chroma_size.width; - local_size.video.chroma_size.width = - local_size.video.chroma_size.height; - local_size.video.chroma_size.height = swap; + swap(local_size.video.luma_size.x, + local_size.video.luma_size.y); + swap(local_size.video.luma_size.width, + local_size.video.luma_size.height); + swap(local_size.video.chroma_size.x, + local_size.video.chroma_size.y); + swap(local_size.video.chroma_size.width, + local_size.video.chroma_size.height); } value = 0; -- cgit v1.2.3-59-g8ed1b From 4f804817d5cfb4bd1abf59a29721446af4b4cfd4 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 9 Nov 2017 13:55:46 -0500 Subject: drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for dce. Move update_plane_addr to apply_ctx_for_surface, address update will just be called once, not twice for updat type is full and medium. This will reduce some reg access and duration time. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f8cbc4f0b1a3..fb33556eeac6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1314,8 +1314,8 @@ static void commit_planes_for_stream(struct dc *dc, if (pipe_ctx->plane_state != plane_state) continue; - if (srf_updates[i].flip_addr) - dc->hwss.update_plane_addr(dc, pipe_ctx); + if (update_type == UPDATE_TYPE_FAST && srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 09051dfe1844..e650bdcd9423 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2881,6 +2881,9 @@ static void dce110_apply_ctx_for_surface( context->stream_count); dce110_program_front_end_for_pipe(dc, pipe_ctx); + + dc->hwss.update_plane_addr(dc, pipe_ctx); + program_surface_visibility(dc, pipe_ctx); } -- cgit v1.2.3-59-g8ed1b From 1a09120f83a0f55a5a159b785104a5c8fa13c9ef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:15:50 -0500 Subject: drm/amdgpu: add license to Makefiles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Was missing license text. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/acp/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/Makefile | 22 ++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/Makefile | 22 ++++++++++++++++++++- drivers/gpu/drm/amd/display/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/basics/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/bios/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce100/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce110/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce112/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce120/Makefile | 23 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dce80/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dml/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/gpio/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/irq/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/virtual/Makefile | 21 ++++++++++++++++++++ .../gpu/drm/amd/display/modules/freesync/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/lib/Makefile | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/powerplay/Makefile | 22 ++++++++++++++++++++- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 22 ++++++++++++++++++++- drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 22 ++++++++++++++++++++- 26 files changed, 547 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/acp/Makefile b/drivers/gpu/drm/amd/acp/Makefile index 8a08e81ee90d..d4176a3fb706 100644 --- a/drivers/gpu/drm/amd/acp/Makefile +++ b/drivers/gpu/drm/amd/acp/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the ACP, which is a sub-component # of AMDSOC/AMDGPU drm driver. # It provides the HW control for ACP related functionalities. diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 78d609123420..90202cf4cd1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 7bb0bc0ca3d6..342c2d937b17 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for Heterogenous System Architecture support for AMD GPU devices # diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile index 8ba37dd9cf7f..c27c81cdeed3 100644 --- a/drivers/gpu/drm/amd/display/Makefile +++ b/drivers/gpu/drm/amd/display/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the DAL (Display Abstract Layer), which is a sub-component # of the AMDGPU drm driver. # It provides the HW control for display related functionalities. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile index 4699e47aa76b..2b72009844f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'dm' sub-component of DAL. # It provides the control and status of dm blocks. diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 4f83e3011743..aed538a4d1ba 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for Display Core (dc) component. # diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile index 43c5ccdeeb72..6af8c8a9ad80 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/Makefile +++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 6ec815dce9cc..239e86bbec5a 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'bios' sub-component of DAL. # It provides the parsing and executing controls for atom bios image. diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 41ef35995b02..7959e382ed28 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'calcs' sub-component of DAL. # It calculates Bandwidth and Watermarks values for HW programming # diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 8abec0bed379..11401fd8e535 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for common 'dce' logic # HW object file under this folder follow similar pattern for HW programming # - register offset and/or shift + mask stored in the dec_hw struct diff --git a/drivers/gpu/drm/amd/display/dc/dce100/Makefile b/drivers/gpu/drm/amd/display/dc/dce100/Makefile index ea40870624b3..a822d4e2a169 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce100/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index 98d956e2f218..d564c0eb8b04 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile index 265ac4310d85..8e090446d511 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile index 1779b963525c..37db1f8d45ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. @@ -8,4 +29,4 @@ dce120_hw_sequencer.o AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) -AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) \ No newline at end of file +AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile index c1105895e5fa..bc388aa4b2f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index a6ca1f97f748..9eac228315b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for DCN. DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 87bab8e8139f..3488af2b5786 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 70d01a9e9676..562ee189d780 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'gpio' sub-component of DAL. # It provides the control and status of HW GPIO pins. diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 55603400acd9..352885cb4d07 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'i2c' sub-component of DAL. # It provides the control and status of HW i2c engine of the adapter. diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index c7e93f7223bd..498515aad4a5 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'audio' sub-component of DAL. # It provides the control and status of HW adapter resources, # that are global for the ASIC and sharable between pipes. diff --git a/drivers/gpu/drm/amd/display/dc/virtual/Makefile b/drivers/gpu/drm/amd/display/dc/virtual/Makefile index fc0b7318d9cc..07326d244d50 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/Makefile +++ b/drivers/gpu/drm/amd/display/dc/virtual/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the virtual sub-component of DAL. # It provides the control and status of HW CRTC block. diff --git a/drivers/gpu/drm/amd/display/modules/freesync/Makefile b/drivers/gpu/drm/amd/display/modules/freesync/Makefile index db8e0ff6d7a9..fb9a499780e8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/Makefile +++ b/drivers/gpu/drm/amd/display/modules/freesync/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for the 'freesync' sub-module of DAL. # diff --git a/drivers/gpu/drm/amd/lib/Makefile b/drivers/gpu/drm/amd/lib/Makefile index 87cd7009e80f..690243001e1a 100644 --- a/drivers/gpu/drm/amd/lib/Makefile +++ b/drivers/gpu/drm/amd/lib/Makefile @@ -1,4 +1,25 @@ # +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# # Makefile for AMD library routines, which are used by AMD driver # components. # diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile index 8c55c6e254d9..231785a9e24c 100644 --- a/drivers/gpu/drm/amd/powerplay/Makefile +++ b/drivers/gpu/drm/amd/powerplay/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/powerplay/inc/ \ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 824fb6fe54ae..a212c27f2e17 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the 'hw manager' sub-component of powerplay. # It provides the hardware management services for the driver. diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 30d3089d7dba..98e701e4f553 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -1,4 +1,24 @@ -# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# # # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -- cgit v1.2.3-59-g8ed1b From 9ce6aae12c66adf87b5861f8fa5705ea11d0b6ee Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Nov 2017 21:29:47 -0500 Subject: drm/amdgpu: add license to files where it was missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These files were missing it before. Acked-by: Harry Wentland Acked-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 22 ++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_helper.c | 22 ++++++++++++++++++++ .../drm/amd/display/dc/dce100/dce100_resource.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.h | 23 +++++++++++++++++++++ .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../display/dc/dce110/dce110_timing_generator_v.c | 23 +++++++++++++++++++++ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 22 ++++++++++++++++++++ .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 22 ++++++++++++++++++++ .../gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/powerplay/inc/smu72.h | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h | 24 +++++++++++++++++++++- drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h | 24 +++++++++++++++++++++- 15 files changed, 254 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6f56ff606e43..83205b93e62d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1,4 +1,6 @@ /* + * Copyright 2017 Advanced Micro Devices, Inc. + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index f337c316ec2c..06525f2c36c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _AMDGPU_TRACE_H_ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 2e509382935f..1babac07bcc9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_debug.c * diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9c5e879f18b3..ad28eba017f2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index c584252669fd..48e1fcf53d43 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * dc_helper.c * diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 90911258bdb3..3ea43e2a9450 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index de8fdf438f9b..2f366d66635d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ /* * dce100_resource.h * diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 5228ee78f7e6..7c4779578fb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1,5 +1,5 @@ /* -* Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index 07d9303d5477..59b4cd329715 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -1,3 +1,26 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "dm_services.h" /* include DCE11 register header files */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 8a08f0a97f94..0fd329deacd8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * link_encoder.h * diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 3050afe8e8a9..b5db1692393c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -1,3 +1,25 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ /* * stream_encoder.h * diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c index 67fae834bc67..8de384bf9a8f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c @@ -1,4 +1,26 @@ -// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "pp_overdriver.h" #include diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h index 08cd70c75d8b..9ad1cefff79f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_H #define SMU72_H diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h index b2edbc0c3c4d..2aefbb85f620 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #ifndef SMU72_DISCRETE_H #define SMU72_DISCRETE_H diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index eebe323c7159..b42a78922505 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -1,4 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + #if !defined(_GPU_SCHED_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) #define _GPU_SCHED_TRACE_H_ -- cgit v1.2.3-59-g8ed1b From ede569844a1b11b368a88269545a9d83cf98063c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:00:41 -0500 Subject: drm/amd/display: Remove plane_res.mi check in dce110_apply_ctx_for_surface plane_res.mi (memory interface) can never be NULL for DCE110 Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2881 dce110_apply_ctx_for_surface() error: we previously assumed 'pipe_ctx->plane_res.mi' could be null (see line 2873) Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e650bdcd9423..da2e44058cc2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2872,13 +2872,12 @@ static void dce110_apply_ctx_for_surface( continue; /* Need to allocate mem before program front end for Fiji */ - if (pipe_ctx->plane_res.mi != NULL) - pipe_ctx->plane_res.mi->funcs->allocate_mem_input( - pipe_ctx->plane_res.mi, - pipe_ctx->stream->timing.h_total, - pipe_ctx->stream->timing.v_total, - pipe_ctx->stream->timing.pix_clk_khz, - context->stream_count); + pipe_ctx->plane_res.mi->funcs->allocate_mem_input( + pipe_ctx->plane_res.mi, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, + pipe_ctx->stream->timing.pix_clk_khz, + context->stream_count); dce110_program_front_end_for_pipe(dc, pipe_ctx); -- cgit v1.2.3-59-g8ed1b From 34996173c88ca69f276eb2979586016fbbaa34ca Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:08:13 -0500 Subject: drm/amd/display: Remove redundant checks in set_default_colors pipe_ctx->stream and pipe_ctx->plane_state are never NULL Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2111 set_default_colors() error: we previously assumed 'pipe_ctx->stream' could be null (see line 2101) Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index da2e44058cc2..981bcd291602 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2095,16 +2095,8 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) struct default_adjustment default_adjust = { 0 }; default_adjust.force_hw_default = false; - if (pipe_ctx->plane_state == NULL) - default_adjust.in_color_space = COLOR_SPACE_SRGB; - else - default_adjust.in_color_space = - pipe_ctx->plane_state->color_space; - if (pipe_ctx->stream == NULL) - default_adjust.out_color_space = COLOR_SPACE_SRGB; - else - default_adjust.out_color_space = - pipe_ctx->stream->output_color_space; + default_adjust.in_color_space = pipe_ctx->plane_state->color_space; + default_adjust.out_color_space = pipe_ctx->stream->output_color_space; default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; -- cgit v1.2.3-59-g8ed1b From 4d06ccd0af1ea5f3a3b74ca421b9cd9840d5e5c6 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 10 Nov 2017 12:12:40 -0500 Subject: drm/amd/display: Fix access of wrong array element TF format conversion Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:357 convert_to_custom_float() error: buffer overflow 'arr_points' 2 <= 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:358 convert_to_custom_float() warn: buffer overflow 'arr_points' 2 <= 2 Regression: drm/amd/display: Remove extra arr_points element Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 981bcd291602..21fc27aab909 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -354,8 +354,8 @@ static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, return false; } - if (!convert_to_custom_float_format(arr_points[2].slope, &fmt, - &arr_points[2].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, + &arr_points[1].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } -- cgit v1.2.3-59-g8ed1b From 904623ee5936e2226009b2f238f28781aecd2565 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 24 Nov 2017 16:31:03 -0500 Subject: drm/amd/display: Move wait for hpd ready out from edp power control. It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by: Yongqiang Sun Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 25 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 +--------- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 15 ------------- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 ++++---------- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 4 ++++ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 + 7 files changed, 36 insertions(+), 39 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 13995893cac5..00130152f366 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1271,6 +1271,24 @@ static enum dc_status enable_link_dp( return status; } +static enum dc_status enable_link_edp( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) +{ + enum dc_status status; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->sink->link; + + link->dc->hwss.edp_power_control(link, true); + link->dc->hwss.edp_wait_for_hpd_ready(link, true); + + status = enable_link_dp(state, pipe_ctx); + + link->dc->hwss.edp_backlight_control(link, true); + + return status; +} + static enum dc_status enable_link_dp_mst( struct dc_state *state, struct pipe_ctx *pipe_ctx) @@ -1746,9 +1764,11 @@ static enum dc_status enable_link( enum dc_status status = DC_ERROR_UNEXPECTED; switch (pipe_ctx->stream->signal) { case SIGNAL_TYPE_DISPLAY_PORT: - case SIGNAL_TYPE_EDP: status = enable_link_dp(state, pipe_ctx); break; + case SIGNAL_TYPE_EDP: + status = enable_link_edp(state, pipe_ctx); + break; case SIGNAL_TYPE_DISPLAY_PORT_MST: status = enable_link_dp_mst(state, pipe_ctx); msleep(200); @@ -2282,6 +2302,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); + if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) + core_dc->hwss.edp_backlight_control(pipe_ctx->stream->sink->link, false); + core_dc->hwss.disable_stream(pipe_ctx, option); disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index f2902569be2e..2096f2a179f2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -88,15 +88,7 @@ void dp_enable_link_phy( } if (dc_is_dp_sst_signal(signal)) { - if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_power_control(link, true); - link_enc->funcs->enable_dp_output( - link_enc, - link_settings, - clock_source); - link->dc->hwss.edp_backlight_control(link, true); - } else - link_enc->funcs->enable_dp_output( + link_enc->funcs->enable_dp_output( link_enc, link_settings, clock_source); @@ -138,7 +130,6 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) dp_receiver_power_ctrl(link, false); if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_backlight_control(link, false); edp_receiver_ready_T9(link); link->link_enc->funcs->disable_output(link->link_enc, signal); link->dc->hwss.edp_power_control(link, false); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index bad70c6b3aad..a266e3f5e75f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1072,21 +1072,6 @@ void dce110_link_encoder_disable_output( /* disable encoder */ if (dc_is_dp_signal(signal)) link_encoder_disable(enc110); - - /* - * TODO: Power control cause regression, we should implement - * it properly, for now just comment it. - */ -// if (enc110->base.connector.id == CONNECTOR_ID_EDP) { -// /* power down eDP panel */ -// link_encoder_edp_wait_for_hpd_ready( -// enc, -// enc->connector, -// false); -// -// link_encoder_edp_power_control( -// enc, false); -// } } void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 21fc27aab909..dd8386778361 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -870,8 +870,6 @@ void hwss_edp_power_control( "%s: Skipping Panel Power action: %s\n", __func__, (power_up ? "On":"Off")); } - - hwss_edp_wait_for_hpd_ready(link, true); } /*todo: cloned in stream enc, fix*/ @@ -972,11 +970,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) } /* blank at encoder level */ - if (dc_is_dp_signal(pipe_ctx->stream->signal)) { - if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP) - hwss_edp_backlight_control(link, false); + if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); - } + link->link_enc->funcs->connect_dig_be_to_fe( link->link_enc, pipe_ctx->stream_res.stream_enc->id, @@ -988,15 +984,12 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings) { struct encoder_unblank_param params = { { 0 } }; - struct dc_link *link = pipe_ctx->stream->sink->link; /* only 3 items below are used by unblank */ params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); - if (link->connector_signal == SIGNAL_TYPE_EDP) - hwss_edp_backlight_control(link, true); } @@ -1342,10 +1335,8 @@ static void power_down_encoders(struct dc *dc) if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(dc->links[i], false); - if (connector_id == CONNECTOR_ID_EDP) { + if (connector_id == CONNECTOR_ID_EDP) signal = SIGNAL_TYPE_EDP; - hwss_edp_backlight_control(dc->links[i], false); - } } dc->links[i]->link_enc->funcs->disable_output( @@ -2976,6 +2967,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .pplib_apply_display_requirements = pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control, + .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, }; void dce110_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 2dd6ac637572..fc637647f643 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -77,5 +77,9 @@ void hwss_edp_backlight_control( struct dc_link *link, bool enable); +void hwss_edp_wait_for_hpd_ready( + struct dc_link *link, + bool power_up); + #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index f0be2b872668..31fd6ae8f61f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2368,7 +2368,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .pplib_apply_display_requirements = dcn10_pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, - .edp_power_control = hwss_edp_power_control + .edp_power_control = hwss_edp_power_control, + .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 03431134c088..b6215ba514d8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -199,6 +199,7 @@ struct hw_sequencer_funcs { void (*edp_backlight_control)( struct dc_link *link, bool enable); + void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); }; -- cgit v1.2.3-59-g8ed1b From 5b92d9d409e742ca09a4cb924e3f781eddbf7d81 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 22 Nov 2017 21:05:55 -0500 Subject: drm/amd/display: Remove redundant NULL check in DCE11 HWSS We already check this a couple lines earlier. Signed-off-by: Harry Wentland Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index dd8386778361..80d36610c302 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2017,8 +2017,7 @@ enum dc_status dce110_apply_ctx_to_hw( if (pipe_ctx->stream == pipe_ctx_old->stream) continue; - if (pipe_ctx->stream && pipe_ctx_old->stream - && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) + if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) continue; if (pipe_ctx->top_pipe) -- cgit v1.2.3-59-g8ed1b From 4486c3fcdff71381871f418b7bcd3a496cd632b1 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 27 Nov 2017 09:30:48 -0500 Subject: drm/amd/display: Remove dead enable_plane function definition and call Signed-off-by: Harry Wentland Reviewed-by: Jordan Lazare Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 --- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ---- 2 files changed, 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 80d36610c302..f0002d63eb63 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2053,9 +2053,6 @@ enum dc_status dce110_apply_ctx_to_hw( context, dc); - if (dc->hwss.enable_plane) - dc->hwss.enable_plane(dc, pipe_ctx, context); - if (DC_OK != status) return status; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b6215ba514d8..5d2b05b93e76 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -138,10 +138,6 @@ struct hw_sequencer_funcs { void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*enable_plane)(struct dc *dc, - struct pipe_ctx *pipe, - struct dc_state *context); - void (*update_info_frame)(struct pipe_ctx *pipe_ctx); void (*enable_stream)(struct pipe_ctx *pipe_ctx); -- cgit v1.2.3-59-g8ed1b From 9c6569dea07cd730d424b84c8348d19bb4bb2ff0 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 1 Dec 2017 09:49:46 -0500 Subject: drm/amd/display: Call validate_fbc should_enable_fbc validate_fbc never fails a modeset. It's simply used to decide whether to use FBC or not. Calling it validate_fbc might be confusing to some so rename it to should_enable_fbc. With that let's also remove the DC_STATUS return code and return bool and make enable_fbc a void function since we never check it's return value and probably never want to anyways. Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 39 +++++++++------------- 1 file changed, 16 insertions(+), 23 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce110') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index f0002d63eb63..86cdd7b4811f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1689,60 +1689,54 @@ static void apply_min_clocks( /* * Check if FBC can be enabled */ -static enum dc_status validate_fbc(struct dc *dc, - struct dc_state *context) +static bool should_enable_fbc(struct dc *dc, + struct dc_state *context) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[0]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; ASSERT(dc->fbc_compressor); /* FBC memory should be allocated */ if (!dc->ctx->fbc_gpu_addr) - return DC_ERROR_UNEXPECTED; + return false; /* Only supports single display */ if (context->stream_count != 1) - return DC_ERROR_UNEXPECTED; + return false; /* Only supports eDP */ if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) - return DC_ERROR_UNEXPECTED; + return false; /* PSR should not be enabled */ if (pipe_ctx->stream->sink->link->psr_enabled) - return DC_ERROR_UNEXPECTED; + return false; /* Nothing to compress */ if (!pipe_ctx->plane_state) - return DC_ERROR_UNEXPECTED; + return false; /* Only for non-linear tiling */ if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) - return DC_ERROR_UNEXPECTED; + return false; - return DC_OK; + return true; } /* * Enable FBC */ -static enum dc_status enable_fbc(struct dc *dc, - struct dc_state *context) +static void enable_fbc(struct dc *dc, + struct dc_state *context) { - enum dc_status status = validate_fbc(dc, context); - - if (status == DC_OK) { + if (should_enable_fbc(dc, context)) { /* Program GRPH COMPRESSED ADDRESS and PITCH */ struct compr_addr_and_pitch_params params = {0, 0, 0}; struct compressor *compr = dc->fbc_compressor; - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[0]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; - params.source_view_width = - pipe_ctx->stream->timing.h_addressable; - params.source_view_height = - pipe_ctx->stream->timing.v_addressable; + params.source_view_width = pipe_ctx->stream->timing.h_addressable; + params.source_view_height = pipe_ctx->stream->timing.v_addressable; compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; @@ -1751,7 +1745,6 @@ static enum dc_status enable_fbc(struct dc *dc, compr->funcs->enable_fbc(compr, ¶ms); } - return status; } #endif -- cgit v1.2.3-59-g8ed1b