From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 74 +++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h new file mode 100644 index 000000000000..3b0e616f7066 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -0,0 +1,74 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HW_SHARED_H__ +#define __DAL_HW_SHARED_H__ + +/****************************************************************************** + * Data types shared between different Virtual HW blocks + ******************************************************************************/ +struct gamma_curve { + uint32_t offset; + uint32_t segments_num; +}; + +struct curve_points { + struct fixed31_32 x; + struct fixed31_32 y; + struct fixed31_32 offset; + struct fixed31_32 slope; + + uint32_t custom_float_x; + uint32_t custom_float_y; + uint32_t custom_float_offset; + uint32_t custom_float_slope; +}; + +struct pwl_result_data { + struct fixed31_32 red; + struct fixed31_32 green; + struct fixed31_32 blue; + + struct fixed31_32 delta_red; + struct fixed31_32 delta_green; + struct fixed31_32 delta_blue; + + uint32_t red_reg; + uint32_t green_reg; + uint32_t blue_reg; + + uint32_t delta_red_reg; + uint32_t delta_green_reg; + uint32_t delta_blue_reg; +}; + +struct pwl_params { + uint32_t *data; + struct gamma_curve arr_curve_points[16]; + struct curve_points arr_points[3]; + struct pwl_result_data rgb_resulted[256 + 3]; + uint32_t hw_points_num; +}; +#endif /* __DAL_HW_SHARED_H__ */ -- cgit v1.2.3-59-g8ed1b From cc0cb445ae56890a322abe2cc8df63b1ccab74fb Mon Sep 17 00:00:00 2001 From: Leon Elazar Date: Wed, 11 Jan 2017 14:33:36 -0500 Subject: drm/amd/display: Fixing some fallout from dc_target removal Also avoid allocating memory dce110_set_output_transfer_func if not needed Signed-off-by: Leon Elazar Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +++-- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 7 +++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 30 +++++----------------- .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 7 +++++ .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 6 ++++- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 4 +++ .../drm/amd/display/dc/dce110/dce110_resource.c | 17 +++++++++--- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 1 - drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + 9 files changed, 49 insertions(+), 30 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index bc1f387d1992..47816c5ee0e0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -192,7 +192,8 @@ bool dc_stream_set_cursor_attributes( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if (pipe_ctx->stream == stream) { + if ((pipe_ctx->stream == stream) && + (pipe_ctx->ipp != NULL)) { struct input_pixel_processor *ipp = pipe_ctx->ipp; if (ipp->funcs->ipp_cursor_set_attributes( @@ -231,7 +232,8 @@ bool dc_stream_set_cursor_position( for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; - if (pipe_ctx->stream == stream) { + if ((pipe_ctx->stream == stream) && + (pipe_ctx->ipp != NULL)) { struct input_pixel_processor *ipp = pipe_ctx->ipp; struct dc_cursor_mi_param param = { .pixel_clk_khz = dc_stream->timing.pix_clk_khz, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 167f523df657..061de9e8249d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -973,6 +973,10 @@ bool dce110_opp_construct(struct dce110_opp *opp110, opp110->base.inst = inst; + opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params)); + if (opp110->base.regamma_params == NULL) + return false; + opp110->regs = regs; opp110->opp_shift = opp_shift; opp110->opp_mask = opp_mask; @@ -982,6 +986,9 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp) { + dm_free((*opp)->regamma_params); + (*opp)->regamma_params = NULL; + dm_free(FROM_DCE11_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6e70cf7b99ef..1a9ba127b781 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -721,43 +721,27 @@ static bool dce110_set_output_transfer_func( const struct core_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; - const struct core_gamma *ramp = NULL; - struct pwl_params *regamma_params; - bool result = false; - - if (surface->public.gamma_correction) - ramp = DC_GAMMA_TO_CORE(surface->public.gamma_correction); - - regamma_params = dm_alloc(sizeof(struct pwl_params)); - if (regamma_params == NULL) - goto regamma_alloc_fail; - - regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; opp->funcs->opp_power_on_regamma_lut(opp, true); + opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + stream->public.out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->public.out_transfer_func, regamma_params)) { - opp->funcs->opp_program_regamma_pwl(opp, regamma_params); - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); + stream->public.out_transfer_func, opp->regamma_params)) { + opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params); + opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); } opp->funcs->opp_power_on_regamma_lut(opp, false); - result = true; - - dm_free(regamma_params); - -regamma_alloc_fail: - return result; + return true; } static enum dc_status bios_parser_crtc_source_select( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index 8164aa6bcb00..876445f14c85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -548,3 +548,10 @@ void dce110_opp_power_on_regamma_lut_v( dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value); } + +void dce110_opp_set_regamma_mode_v( + struct output_pixel_processor *opp, + enum opp_regamma mode) +{ + // TODO: need to implement the function +} diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c index 0a9b384303d0..95b3d2eb8428 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c @@ -42,7 +42,7 @@ static const struct opp_funcs funcs = { .opp_set_csc_default = dce110_opp_v_set_csc_default, .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment, .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, - .opp_set_regamma_mode = dce110_opp_set_regamma_mode, + .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v, .opp_destroy = dce110_opp_destroy, .opp_program_fmt = dce110_opp_program_fmt, .opp_program_bit_depth_reduction = @@ -56,6 +56,10 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110, opp110->base.ctx = ctx; + opp110->base.regamma_params = dm_alloc(sizeof(struct pwl_params)); + if (opp110->base.regamma_params == NULL) + return false; + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h index ac5937786ce3..cb26c515d30f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h @@ -49,4 +49,8 @@ void dce110_opp_power_on_regamma_lut_v( struct output_pixel_processor *opp, bool power_on); +void dce110_opp_set_regamma_mode_v( + struct output_pixel_processor *opp, + enum opp_regamma mode); + #endif /* __DC_OPP_DCE110_V_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index cfbb4ef21f8b..82cddb6425a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1114,14 +1114,22 @@ static const struct resource_funcs dce110_res_pool_funcs = { dce110_resource_build_bit_depth_reduction_params }; -static void underlay_create(struct dc_context *ctx, struct resource_pool *pool) +static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) { struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); - dce110_opp_v_construct(dce110_oppv, ctx); + if ((dce110_tgv == NULL) || + (dce110_xfmv == NULL) || + (dce110_miv == NULL) || + (dce110_oppv == NULL)) + return false; + + if (!dce110_opp_v_construct(dce110_oppv, ctx)) + return false; + dce110_timing_generator_v_construct(dce110_tgv, ctx); dce110_mem_input_v_construct(dce110_miv, ctx); dce110_transform_v_construct(dce110_xfmv, ctx); @@ -1135,6 +1143,8 @@ static void underlay_create(struct dc_context *ctx, struct resource_pool *pool) /* update the public caps to indicate an underlay is available */ ctx->dc->caps.max_slave_planes = 1; ctx->dc->caps.max_slave_planes = 1; + + return true; } static void bw_calcs_data_update_from_pplib(struct core_dc *dc) @@ -1334,7 +1344,8 @@ static bool construct( } } - underlay_create(ctx, &pool->base); + if (!underlay_create(ctx, &pool->base)) + goto res_create_fail; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 3b0e616f7066..b8735b27e9bc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -65,7 +65,6 @@ struct pwl_result_data { }; struct pwl_params { - uint32_t *data; struct gamma_curve arr_curve_points[16]; struct curve_points arr_points[3]; struct pwl_result_data rgb_resulted[256 + 3]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index bef5e2cacbe3..a10c4e296960 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -202,6 +202,7 @@ enum opp_regamma { struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; + struct pwl_params *regamma_params; const struct opp_funcs *funcs; }; -- cgit v1.2.3-59-g8ed1b From 94cd1f79b05994b712a2cf0563ac73be0323978b Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 2 Feb 2017 15:21:45 -0500 Subject: drm/amd/display: Fixed color temperature corruption. Signed-off-by: Yongqiang Sun Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index b8735b27e9bc..dfe590198a33 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -65,7 +65,7 @@ struct pwl_result_data { }; struct pwl_params { - struct gamma_curve arr_curve_points[16]; + struct gamma_curve arr_curve_points[34]; struct curve_points arr_points[3]; struct pwl_result_data rgb_resulted[256 + 3]; uint32_t hw_points_num; -- cgit v1.2.3-59-g8ed1b From 86b6a203b966ea54e3225b49e53769cf4c116905 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 24 Apr 2017 15:20:24 -0400 Subject: drm/amd/display: dce120 to dce ipp refactor Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 252 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h | 226 ++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 2 +- .../drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 4 +- drivers/gpu/drm/amd/display/dc/dce120/Makefile | 1 - drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 ----- drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 ----- .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 193 ---------------- .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 -------------- .../drm/amd/display/dc/dce120/dce120_resource.c | 69 +++--- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 3 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 5 +- 14 files changed, 521 insertions(+), 525 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index 05562553b656..8abec0bed379 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -7,7 +7,7 @@ DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ -dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o +dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c new file mode 100644 index 000000000000..d6bf6067a309 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -0,0 +1,252 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce_ipp.h" +#include "reg_helper.h" +#include "dm_services.h" + +#define REG(reg) \ + (ipp_dce->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name + +#define CTX \ + ipp_dce->base.ctx + +static void dce_ipp_cursor_set_position( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position, + const struct dc_cursor_mi_param *param) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + + /* lock cursor registers */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); + + /* Flag passed in structure differentiates cursor enable/disable. */ + /* Update if it differs from cached state. */ + REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); + + REG_SET_2(CUR_POSITION, 0, + CURSOR_X_POSITION, position->x, + CURSOR_Y_POSITION, position->y); + + REG_SET_2(CUR_HOT_SPOT, 0, + CURSOR_HOT_SPOT_X, position->x_hotspot, + CURSOR_HOT_SPOT_Y, position->y_hotspot); + + /* unlock cursor registers */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); +} + +static void dce_ipp_cursor_set_attributes( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + int mode; + + /* Lock cursor registers */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); + + /* Program cursor control */ + switch (attributes->color_format) { + case CURSOR_MODE_MONO: + mode = 0; + break; + case CURSOR_MODE_COLOR_1BIT_AND: + mode = 1; + break; + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: + mode = 2; + break; + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: + mode = 3; + break; + default: + BREAK_TO_DEBUGGER(); /* unsupported */ + mode = 0; + } + + REG_UPDATE_3(CUR_CONTROL, + CURSOR_MODE, mode, + CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, + CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); + + if (attributes->color_format == CURSOR_MODE_MONO) { + REG_SET_3(CUR_COLOR1, 0, + CUR_COLOR1_BLUE, 0, + CUR_COLOR1_GREEN, 0, + CUR_COLOR1_RED, 0); + + REG_SET_3(CUR_COLOR2, 0, + CUR_COLOR2_BLUE, 0xff, + CUR_COLOR2_GREEN, 0xff, + CUR_COLOR2_RED, 0xff); + } + + /* + * Program cursor size -- NOTE: HW spec specifies that HW register + * stores size as (height - 1, width - 1) + */ + REG_SET_2(CUR_SIZE, 0, + CURSOR_WIDTH, attributes->width-1, + CURSOR_HEIGHT, attributes->height-1); + + /* Program cursor surface address */ + /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor + * surface base address in byte. It is 4K byte aligned. + * The correct way to program cursor surface address is to first write + * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS + */ + REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, + CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part); + + REG_SET(CUR_SURFACE_ADDRESS, 0, + CURSOR_SURFACE_ADDRESS, attributes->address.low_part); + + /* Unlock Cursor registers. */ + REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); +} + +static void dce_ipp_program_prescale( + struct input_pixel_processor *ipp, + struct ipp_prescale_params *params) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + + /* set to bypass mode first before change */ + REG_UPDATE(PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS, + 1); + + REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, + GRPH_PRESCALE_SCALE_R, params->scale, + GRPH_PRESCALE_BIAS_R, params->bias); + + REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, + GRPH_PRESCALE_SCALE_G, params->scale, + GRPH_PRESCALE_BIAS_G, params->bias); + + REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, + GRPH_PRESCALE_SCALE_B, params->scale, + GRPH_PRESCALE_BIAS_B, params->bias); + + if (params->mode != IPP_PRESCALE_MODE_BYPASS) { + REG_UPDATE(PRESCALE_GRPH_CONTROL, + GRPH_PRESCALE_BYPASS, 0); + + /* If prescale is in use, then legacy lut should be bypassed */ + REG_UPDATE(INPUT_GAMMA_CONTROL, + GRPH_INPUT_GAMMA_MODE, 1); + } +} + +static void dce_ipp_program_input_lut( + struct input_pixel_processor *ipp, + const struct dc_gamma *gamma) +{ + int i; + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + + /* power on LUT memory */ + REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); + + /* enable all */ + REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); + + /* 256 entry mode */ + REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); + + /* LUT-256, unsigned, integer, new u0.12 format */ + REG_SET_3(DC_LUT_CONTROL, 0, + DC_LUT_DATA_R_FORMAT, 3, + DC_LUT_DATA_G_FORMAT, 3, + DC_LUT_DATA_B_FORMAT, 3); + + /* start from index 0 */ + REG_SET(DC_LUT_RW_INDEX, 0, + DC_LUT_RW_INDEX, 0); + + for (i = 0; i < INPUT_LUT_ENTRIES; i++) { + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->red[i]); + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->green[i]); + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->blue[i]); + } + + /* power off LUT memory */ + REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); + + /* bypass prescale, enable legacy LUT */ + REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); + REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); +} + +static void dce_ipp_set_degamma( + struct input_pixel_processor *ipp, + enum ipp_degamma_mode mode) +{ + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); + uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; + + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || + mode == IPP_DEGAMMA_MODE_HW_sRGB); + + REG_SET_3(DEGAMMA_CONTROL, 0, + GRPH_DEGAMMA_MODE, degamma_type, + CURSOR_DEGAMMA_MODE, degamma_type, + CURSOR2_DEGAMMA_MODE, degamma_type); +} + +static const struct ipp_funcs dce_ipp_funcs = { + .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, + .ipp_cursor_set_position = dce_ipp_cursor_set_position, + .ipp_program_prescale = dce_ipp_program_prescale, + .ipp_program_input_lut = dce_ipp_program_input_lut, + .ipp_set_degamma = dce_ipp_set_degamma +}; + +/*****************************************/ +/* Constructor, Destructor */ +/*****************************************/ + +void dce_ipp_construct( + struct dce_ipp *ipp_dce, + struct dc_context *ctx, + int inst, + const struct dce_ipp_registers *regs, + const struct dce_ipp_shift *ipp_shift, + const struct dce_ipp_mask *ipp_mask) +{ + ipp_dce->base.ctx = ctx; + ipp_dce->base.inst = inst; + ipp_dce->base.funcs = &dce_ipp_funcs; + + ipp_dce->regs = regs; + ipp_dce->ipp_shift = ipp_shift; + ipp_dce->ipp_mask = ipp_mask; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h new file mode 100644 index 000000000000..23f25b1b0e64 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h @@ -0,0 +1,226 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCE_DCE_IPP_H_ +#define _DCE_DCE_IPP_H_ + +#include "ipp.h" + +#define TO_DCE_IPP(ipp)\ + container_of(ipp, struct dce_ipp, base) + +#define IPP_COMMON_REG_LIST_DCE_BASE(id) \ + SRI(CUR_UPDATE, DCP, id), \ + SRI(CUR_CONTROL, DCP, id), \ + SRI(CUR_POSITION, DCP, id), \ + SRI(CUR_HOT_SPOT, DCP, id), \ + SRI(CUR_COLOR1, DCP, id), \ + SRI(CUR_COLOR2, DCP, id), \ + SRI(CUR_SIZE, DCP, id), \ + SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \ + SRI(CUR_SURFACE_ADDRESS, DCP, id), \ + SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ + SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \ + SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ + SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ + SRI(INPUT_GAMMA_CONTROL, DCP, id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ + SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ + SRI(DC_LUT_RW_MODE, DCP, id), \ + SRI(DC_LUT_CONTROL, DCP, id), \ + SRI(DC_LUT_RW_INDEX, DCP, id), \ + SRI(DC_LUT_SEQ_COLOR, DCP, id), \ + SRI(DEGAMMA_CONTROL, DCP, id) + +#define IPP_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ + IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ + IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ + IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ + IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ + IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ + IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ + IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ + IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ + IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ + IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ + IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \ + IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ + IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ + IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ + IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ + IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ + IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ + IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ + IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ + IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ + IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ + IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ + IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ + IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) + +#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ + IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ + IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ + IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ + IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ + IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \ + IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ + IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ + IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ + IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ + IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ + IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ + IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ + IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ + IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ + IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ + IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ + IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ + IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ + IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) + +#define IPP_REG_FIELD_LIST(type) \ + type CURSOR_UPDATE_LOCK; \ + type CURSOR_EN; \ + type CURSOR_X_POSITION; \ + type CURSOR_Y_POSITION; \ + type CURSOR_HOT_SPOT_X; \ + type CURSOR_HOT_SPOT_Y; \ + type CURSOR_MODE; \ + type CURSOR_2X_MAGNIFY; \ + type CUR_INV_TRANS_CLAMP; \ + type CUR_COLOR1_BLUE; \ + type CUR_COLOR1_GREEN; \ + type CUR_COLOR1_RED; \ + type CUR_COLOR2_BLUE; \ + type CUR_COLOR2_GREEN; \ + type CUR_COLOR2_RED; \ + type CURSOR_WIDTH; \ + type CURSOR_HEIGHT; \ + type CURSOR_SURFACE_ADDRESS_HIGH; \ + type CURSOR_SURFACE_ADDRESS; \ + type GRPH_PRESCALE_BYPASS; \ + type GRPH_PRESCALE_SCALE_R; \ + type GRPH_PRESCALE_BIAS_R; \ + type GRPH_PRESCALE_SCALE_G; \ + type GRPH_PRESCALE_BIAS_G; \ + type GRPH_PRESCALE_SCALE_B; \ + type GRPH_PRESCALE_BIAS_B; \ + type GRPH_INPUT_GAMMA_MODE; \ + type DCP_LUT_MEM_PWR_DIS; \ + type DC_LUT_WRITE_EN_MASK; \ + type DC_LUT_RW_MODE; \ + type DC_LUT_DATA_R_FORMAT; \ + type DC_LUT_DATA_G_FORMAT; \ + type DC_LUT_DATA_B_FORMAT; \ + type DC_LUT_RW_INDEX; \ + type DC_LUT_SEQ_COLOR; \ + type GRPH_DEGAMMA_MODE; \ + type CURSOR_DEGAMMA_MODE; \ + type CURSOR2_DEGAMMA_MODE + +struct dce_ipp_shift { + IPP_REG_FIELD_LIST(uint8_t); +}; + +struct dce_ipp_mask { + IPP_REG_FIELD_LIST(uint32_t); +}; + +struct dce_ipp_registers { + uint32_t CUR_UPDATE; + uint32_t CUR_CONTROL; + uint32_t CUR_POSITION; + uint32_t CUR_HOT_SPOT; + uint32_t CUR_COLOR1; + uint32_t CUR_COLOR2; + uint32_t CUR_SIZE; + uint32_t CUR_SURFACE_ADDRESS_HIGH; + uint32_t CUR_SURFACE_ADDRESS; + uint32_t PRESCALE_GRPH_CONTROL; + uint32_t PRESCALE_VALUES_GRPH_R; + uint32_t PRESCALE_VALUES_GRPH_G; + uint32_t PRESCALE_VALUES_GRPH_B; + uint32_t INPUT_GAMMA_CONTROL; + uint32_t DCFE_MEM_PWR_CTRL; + uint32_t DC_LUT_WRITE_EN_MASK; + uint32_t DC_LUT_RW_MODE; + uint32_t DC_LUT_CONTROL; + uint32_t DC_LUT_RW_INDEX; + uint32_t DC_LUT_SEQ_COLOR; + uint32_t DEGAMMA_CONTROL; +}; + +struct dce_ipp { + struct input_pixel_processor base; + const struct dce_ipp_registers *regs; + const struct dce_ipp_shift *ipp_shift; + const struct dce_ipp_mask *ipp_mask; +}; + +void dce_ipp_construct(struct dce_ipp *ipp_dce, + struct dc_context *ctx, + int inst, + const struct dce_ipp_registers *regs, + const struct dce_ipp_shift *ipp_shift, + const struct dce_ipp_mask *ipp_mask); + +#endif /* _DCE_DCE_IPP_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index da2a02434665..ca6c621151b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -369,7 +369,7 @@ struct dce_transform { bool prescaler_on; }; -bool dce_transform_construct(struct dce_transform *xfm110, +bool dce_transform_construct(struct dce_transform *xfm_dce, struct dc_context *ctx, uint32_t inst, const struct dce_transform_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h index 434fe2f5a9d7..8684e6a0ef4b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h @@ -59,7 +59,7 @@ void dce110_ipp_cursor_set_attributes( const struct dc_cursor_attributes *attributes); /* DEGAMMA RELATED */ -bool dce110_ipp_set_degamma( +void dce110_ipp_set_degamma( struct input_pixel_processor *ipp, enum ipp_degamma_mode mode); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c index f05cc9e981f3..0bcd8a68d5e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c @@ -66,7 +66,7 @@ -bool dce110_ipp_set_degamma( +void dce110_ipp_set_degamma( struct input_pixel_processor *ipp, enum ipp_degamma_mode mode) { @@ -82,8 +82,6 @@ bool dce110_ipp_set_degamma( GRPH_DEGAMMA_MODE, degamma_type, CURSOR_DEGAMMA_MODE, degamma_type, CURSOR2_DEGAMMA_MODE, degamma_type); - - return true; } void dce110_ipp_program_prescale( diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile index 3c6b3fa98ddc..826c12ee368c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -4,7 +4,6 @@ DCE120 = dce120_resource.o dce120_timing_generator.o \ -dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \ dce120_mem_input.o dce120_hw_sequencer.o AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c deleted file mode 100644 index f4505690e01a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#include "dce120_ipp.h" - -static const struct ipp_funcs funcs = { - .ipp_cursor_set_attributes = dce120_ipp_cursor_set_attributes, - .ipp_cursor_set_position = dce120_ipp_cursor_set_position, - .ipp_program_prescale = dce120_ipp_program_prescale, - .ipp_program_input_lut = dce120_ipp_program_input_lut, - .ipp_set_degamma = dce120_ipp_set_degamma, -}; - -bool dce120_ipp_construct( - struct dce110_ipp *ipp, - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) -{ - if (!dce110_ipp_construct(ipp, ctx, inst, offset)) { - ASSERT_CRITICAL(false); - return false; - } - - ipp->base.funcs = &funcs; - - return true; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h deleted file mode 100644 index 7f645fde7064..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_IPP_DCE120_H__ -#define __DC_IPP_DCE120_H__ - -#include "ipp.h" -#include "../dce110/dce110_ipp.h" - - -bool dce120_ipp_construct( - struct dce110_ipp *ipp, - struct dc_context *ctx, - enum controller_id id, - const struct dce110_ipp_reg_offsets *offset); - -/* CURSOR RELATED */ -void dce120_ipp_cursor_set_position( - struct input_pixel_processor *ipp, - const struct dc_cursor_position *position, - const struct dc_cursor_mi_param *param); - -void dce120_ipp_cursor_set_attributes( - struct input_pixel_processor *ipp, - const struct dc_cursor_attributes *attributes); - -/* DEGAMMA RELATED */ -bool dce120_ipp_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode); - -void dce120_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params); - -void dce120_ipp_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma); - -#endif /*__DC_IPP_DCE120_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c deleted file mode 100644 index dc81d320f6e5..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#include "../dce110/dce110_ipp.h" - - -#define DCP_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_UPDATE(reg, field, val) \ - DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define DCP_REG_SET(reg, field, val) \ - DCP_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ - DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -/* TODO: DAL3 does not implement cursor memory control - * MCIF_MEM_CONTROL, DMIF_CURSOR_MEM_CONTROL - */ -static void lock( - struct dce110_ipp *ipp110, bool lock) -{ - DCP_REG_UPDATE(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, lock); -} - -static bool program_control( - struct dce110_ipp *ipp110, - enum dc_cursor_color_format color_format, - bool enable_magnification, - bool inverse_transparent_clamping) -{ - uint32_t mode = 0; - - switch (color_format) { - case CURSOR_MODE_MONO: - mode = 0; - break; - case CURSOR_MODE_COLOR_1BIT_AND: - mode = 1; - break; - case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: - mode = 2; - break; - case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: - mode = 3; - break; - default: - return false; - } - - DCP_REG_UPDATE_3( - DCP0_CUR_CONTROL, - CURSOR_MODE, mode, - CURSOR_2X_MAGNIFY, enable_magnification, - CUR_INV_TRANS_CLAMP, inverse_transparent_clamping); - - if (color_format == CURSOR_MODE_MONO) { - DCP_REG_SET_3( - DCP0_CUR_COLOR1, - CUR_COLOR1_BLUE, 0, - CUR_COLOR1_GREEN, 0, - CUR_COLOR1_RED, 0); - - DCP_REG_SET_3( - DCP0_CUR_COLOR2, - CUR_COLOR2_BLUE, 0xff, - CUR_COLOR2_GREEN, 0xff, - CUR_COLOR2_RED, 0xff); - } - return true; -} - -static void program_address( - struct dce110_ipp *ipp110, - PHYSICAL_ADDRESS_LOC address) -{ - /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor - * surface base address in byte. It is 4K byte aligned. - * The correct way to program cursor surface address is to first write - * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS - */ - - DCP_REG_SET( - DCP0_CUR_SURFACE_ADDRESS_HIGH, - CURSOR_SURFACE_ADDRESS_HIGH, address.high_part); - - DCP_REG_SET( - DCP0_CUR_SURFACE_ADDRESS, - CURSOR_SURFACE_ADDRESS, address.low_part); -} - -void dce120_ipp_cursor_set_position( - struct input_pixel_processor *ipp, - const struct dc_cursor_position *position, - const struct dc_cursor_mi_param *param) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* lock cursor registers */ - lock(ipp110, true); - - /* Flag passed in structure differentiates cursor enable/disable. */ - /* Update if it differs from cached state. */ - DCP_REG_UPDATE(DCP0_CUR_CONTROL, CURSOR_EN, position->enable); - - DCP_REG_SET_2( - DCP0_CUR_POSITION, - CURSOR_X_POSITION, position->x, - CURSOR_Y_POSITION, position->y); - - DCP_REG_SET_2( - DCP0_CUR_HOT_SPOT, - CURSOR_HOT_SPOT_X, position->x_hotspot, - CURSOR_HOT_SPOT_Y, position->y_hotspot); - - /* unlock cursor registers */ - lock(ipp110, false); -} - -void dce120_ipp_cursor_set_attributes( - struct input_pixel_processor *ipp, - const struct dc_cursor_attributes *attributes) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - /* Lock cursor registers */ - lock(ipp110, true); - - /* Program cursor control */ - program_control( - ipp110, - attributes->color_format, - attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, - attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); - - /* - * Program cursor size -- NOTE: HW spec specifies that HW register - * stores size as (height - 1, width - 1) - */ - DCP_REG_SET_2( - DCP0_CUR_SIZE, - CURSOR_WIDTH, attributes->width-1, - CURSOR_HEIGHT, attributes->height-1); - - /* Program cursor surface address */ - program_address(ipp110, attributes->address); - - /* Unlock Cursor registers. */ - lock(ipp110, false); -} - diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c deleted file mode 100644 index 7aa5a49c01e2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "include/logger_interface.h" -#include "include/fixed31_32.h" -#include "basics/conversion.h" - -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" - -#include "../dce110/dce110_ipp.h" - -#define DCP_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_SET_N(reg_name, n, ...) \ - generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__) - -#define DCP_REG_UPDATE(reg, field, val) \ - DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \ - DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - -#define DCP_REG_SET(reg, field, val) \ - DCP_REG_SET_N(reg, 1, FD(reg##__##field), val) - -#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ - DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) - -#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ - DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) - - -bool dce120_ipp_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; - - ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || - mode == IPP_DEGAMMA_MODE_HW_sRGB); - - DCP_REG_SET_3( - DCP0_DEGAMMA_CONTROL, - GRPH_DEGAMMA_MODE, degamma_type, - CURSOR_DEGAMMA_MODE, degamma_type, - CURSOR2_DEGAMMA_MODE, degamma_type); - - return true; -} - -void dce120_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params) -{ - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* set to bypass mode first before change */ - DCP_REG_UPDATE( - DCP0_PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, - 1); - - DCP_REG_SET_2( - DCP0_PRESCALE_VALUES_GRPH_R, - GRPH_PRESCALE_SCALE_R, params->scale, - GRPH_PRESCALE_BIAS_R, params->bias); - - DCP_REG_SET_2( - DCP0_PRESCALE_VALUES_GRPH_G, - GRPH_PRESCALE_SCALE_G, params->scale, - GRPH_PRESCALE_BIAS_G, params->bias); - - DCP_REG_SET_2( - DCP0_PRESCALE_VALUES_GRPH_B, - GRPH_PRESCALE_SCALE_B, params->scale, - GRPH_PRESCALE_BIAS_B, params->bias); - - if (params->mode != IPP_PRESCALE_MODE_BYPASS) { - DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, 0); - - /* If prescale is in use, then legacy lut should be bypassed */ - DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE, 1); - } -} - -static void dce120_helper_select_lut(struct dce110_ipp *ipp110) -{ - /* enable all */ - DCP_REG_SET( - DCP0_DC_LUT_WRITE_EN_MASK, - DC_LUT_WRITE_EN_MASK, - 0x7); - - /* 256 entry mode */ - DCP_REG_UPDATE(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); - - /* LUT-256, unsigned, integer, new u0.12 format */ - DCP_REG_SET_3( - DCP0_DC_LUT_CONTROL, - DC_LUT_DATA_R_FORMAT, 3, - DC_LUT_DATA_G_FORMAT, 3, - DC_LUT_DATA_B_FORMAT, 3); - - /* start from index 0 */ - DCP_REG_SET( - DCP0_DC_LUT_RW_INDEX, - DC_LUT_RW_INDEX, - 0); -} - -void dce120_ipp_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma) -{ - int i; - struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); - - /* power on LUT memory */ - DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1); - - dce120_helper_select_lut(ipp110); - - for (i = 0; i < INPUT_LUT_ENTRIES; i++) { - DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]); - DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]); - DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]); - } - - /* power off LUT memory */ - DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0); - - /* bypass prescale, enable legacy LUT */ - DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); - DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); -} diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index f677a77ca6e0..207d07b29e81 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -40,7 +40,7 @@ #include "dce/dce_opp.h" #include "dce/dce_clock_source.h" #include "dce/dce_clocks.h" -#include "dce120_ipp.h" +#include "dce/dce_ipp.h" #include "dce110/dce110_mem_input.h" #include "dce120/dce120_mem_input.h" @@ -174,6 +174,28 @@ static const struct dce_abm_mask abm_mask = { ABM_MASK_SH_LIST_DCE110(_MASK) }; +#define ipp_regs(id)\ +[id] = {\ + IPP_COMMON_REG_LIST_DCE_BASE(id)\ +} + +static const struct dce_ipp_registers ipp_regs[] = { + ipp_regs(0), + ipp_regs(1), + ipp_regs(2), + ipp_regs(3), + ipp_regs(4), + ipp_regs(5) +}; + +static const struct dce_ipp_shift ipp_shift = { + IPP_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) +}; + +static const struct dce_ipp_mask ipp_mask = { + IPP_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) +}; + #define transform_regs(id)\ [id] = {\ XFM_COMMON_REG_LIST_DCE110(id)\ @@ -354,27 +376,6 @@ struct output_pixel_processor *dce120_opp_create( return NULL; } -static const struct dce110_ipp_reg_offsets dce120_ipp_reg_offsets[] = { - { - .dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL), - }, - { - .dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL), - } -}; - static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = { { .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), @@ -498,7 +499,7 @@ static struct timing_generator *dce120_timing_generator_create( static void dce120_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCE110_IPP(*ipp)); + dm_free(TO_DCE_IPP(*ipp)); *ipp = NULL; } @@ -622,21 +623,18 @@ struct link_encoder *dce120_link_encoder_create( } static struct input_pixel_processor *dce120_ipp_create( - struct dc_context *ctx, - uint32_t inst, - const struct dce110_ipp_reg_offsets *offset) + struct dc_context *ctx, uint32_t inst) { - struct dce110_ipp *ipp = dm_alloc(sizeof(struct dce110_ipp)); + struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - if (!ipp) + if (!ipp) { + BREAK_TO_DEBUGGER(); return NULL; + } - if (dce120_ipp_construct(ipp, ctx, inst, offset)) - return &ipp->base; - - BREAK_TO_DEBUGGER(); - dm_free(ipp); - return NULL; + dce_ipp_construct(ipp, ctx, inst, + &ipp_regs[inst], &ipp_shift, &ipp_mask); + return &ipp->base; } static struct stream_encoder *dce120_stream_encoder_create( @@ -1025,8 +1023,7 @@ static bool construct( goto controller_create_fail; } - pool->base.ipps[i] = dce120_ipp_create(ctx, i, - &dce120_ipp_reg_offsets[i]); + pool->base.ipps[i] = dce120_ipp_create(ctx, i); if (pool->base.ipps[i] == NULL) { BREAK_TO_DEBUGGER(); dm_error( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index dfe590198a33..907e0a9a8474 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -26,6 +26,9 @@ #ifndef __DAL_HW_SHARED_H__ #define __DAL_HW_SHARED_H__ +#include "os_types.h" +#include "fixed31_32.h" + /****************************************************************************** * Data types shared between different Virtual HW blocks ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 7928e230eefb..2f3dc2e7f17a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,6 +27,7 @@ #define __DAL_IPP_H__ #include "hw_shared.h" +#include "dc_hw_types.h" #define MAXTRIX_COEFFICIENTS_NUMBER 12 #define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4) @@ -113,7 +114,7 @@ struct ipp_funcs { const struct dc_gamma *gamma); /*** DEGAMMA RELATED ***/ - bool (*ipp_set_degamma)( + void (*ipp_set_degamma)( struct input_pixel_processor *ipp, enum ipp_degamma_mode mode); -- cgit v1.2.3-59-g8ed1b From 8748068764e7a50ac787c1c17f402f3fbbe97ccc Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Sun, 23 Jul 2017 15:18:57 -0400 Subject: drm/amd/display: add idle wait for passive surface update and modeset Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++++++++++++++++ .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 18 +++++++++++++++++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 4 ++++ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 -- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 3 +++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 ++ 7 files changed, 46 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index de05ad09599f..9ef671735125 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -934,6 +934,10 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c if (!dcb->funcs->is_accelerated_mode(dcb)) core_dc->hwss.enable_accelerated_mode(core_dc); + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe); + } result = core_dc->hwss.apply_ctx_to_hw(core_dc, context); program_timing_sync(core_dc, context); @@ -1537,6 +1541,21 @@ void dc_update_surfaces_and_stream(struct dc *dc, } } + if (update_type > UPDATE_TYPE_FAST) { + for (i = 0; i < surface_count; i++) { + struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); + + for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + + if (pipe_ctx->surface != surface) + continue; + + core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe_ctx); + } + } + } + if (surface_count == 0) core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 64f2fd0d539e..633d858caf6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1739,6 +1739,7 @@ static void dcn10_apply_ctx_for_surface( mpcc_cfg.bot_mpcc_id = 0xf; mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe; old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg); + old_pipe_ctx->top_pipe->opp->mpcc_disconnect_pending[old_pipe_ctx->mpcc->inst] = true; if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); @@ -2012,6 +2013,20 @@ static void dcn10_log_hw_state(struct core_dc *dc) */ } +static void dcn10_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) +{ + int i; + for (i = 0; i < MAX_PIPES; i++) { + if (!pipe_ctx->opp || !pipe_ctx->mpcc) + continue; + + if (pipe_ctx->opp->mpcc_disconnect_pending[i]) { + pipe_ctx->mpcc->funcs->wait_for_idle(res_pool->mpcc[i]); + pipe_ctx->opp->mpcc_disconnect_pending[i] = false; + } + } +} + static bool dcn10_dummy_display_power_gating( struct core_dc *dc, uint8_t controller_id, @@ -2085,7 +2100,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .set_static_screen_control = set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dce110_set_avmute, - .log_hw_state = dcn10_log_hw_state + .log_hw_state = dcn10_log_hw_state, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 669ac4b67ea9..c2aa69deecc2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -907,10 +907,14 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask) { + int i; oppn10->base.ctx = ctx; oppn10->base.inst = inst; oppn10->base.funcs = &dcn10_opp_funcs; + for (i = 0; i < MAX_PIPES; i++) + oppn10->base.mpcc_disconnect_pending[i] = false; + oppn10->regs = regs; oppn10->opp_shift = opp_shift; oppn10->opp_mask = opp_mask; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 30177f839b8a..cc65cfdea66f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -38,10 +38,8 @@ struct core_stream; -#define MAX_PIPES 6 #define MAX_CLOCK_SOURCES 7 - /********* core_surface **********/ #define DC_SURFACE_TO_CORE(dc_surface) \ container_of(dc_surface, struct core_surface, public) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 907e0a9a8474..0212618a36be 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -32,6 +32,9 @@ /****************************************************************************** * Data types shared between different Virtual HW blocks ******************************************************************************/ + +#define MAX_PIPES 6 + struct gamma_curve { uint32_t offset; uint32_t segments_num; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 4b0c28eef352..57bdd6c8f955 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -207,6 +207,7 @@ struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; struct pwl_params regamma_params; + bool mpcc_disconnect_pending[MAX_PIPES]; const struct opp_funcs *funcs; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 4c027a98cfd3..22aca5a375ae 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -156,6 +156,8 @@ struct hw_sequencer_funcs { void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); void (*log_hw_state)(struct core_dc *dc); + + void (*wait_for_mpcc_disconnect)(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( -- cgit v1.2.3-59-g8ed1b From 7db90a6b58761577596499ddd90f3c5ace2b716d Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Sat, 22 Jul 2017 21:58:08 -0400 Subject: drm/amd/display: move ocsc programming from opp to dpp Signed-off-by: Tony Cheng Reviewed-by: Yuehin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 148 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 46 ++++++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 147 -------------------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 40 ------ drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 37 ++++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 21 --- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 26 ++-- 8 files changed, 242 insertions(+), 225 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index fff81a14b21c..0f3f1a31f10b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -988,11 +988,159 @@ static void dcn_dpp_set_gamut_remap( } } +static void oppn10_set_output_csc_default( + struct transform *xfm_base, + const struct default_adjustment *default_adjust) +{ + + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + uint32_t ocsc_mode = 0; + + if (default_adjust != NULL) { + switch (default_adjust->out_color_space) { + case COLOR_SPACE_SRGB: + case COLOR_SPACE_2020_RGB_FULLRANGE: + ocsc_mode = 0; + break; + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + ocsc_mode = 1; + break; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: + ocsc_mode = 2; + break; + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_2020_YCBCR: + ocsc_mode = 3; + break; + case COLOR_SPACE_UNKNOWN: + default: + break; + } + } + + REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); + +} + +static void oppn10_program_color_matrix( + struct dcn10_dpp *xfm, + const struct out_csc_color_matrix *tbl_entry) +{ + uint32_t mode; + + REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode); + + if (tbl_entry == NULL) { + BREAK_TO_DEBUGGER(); + return; + } + + if (mode == 4) { + /*R*/ + REG_SET_2(CM_OCSC_C11_C12, 0, + CM_OCSC_C11, tbl_entry->regval[0], + CM_OCSC_C12, tbl_entry->regval[1]); + + REG_SET_2(CM_OCSC_C13_C14, 0, + CM_OCSC_C13, tbl_entry->regval[2], + CM_OCSC_C14, tbl_entry->regval[3]); + + /*G*/ + REG_SET_2(CM_OCSC_C21_C22, 0, + CM_OCSC_C21, tbl_entry->regval[4], + CM_OCSC_C22, tbl_entry->regval[5]); + + REG_SET_2(CM_OCSC_C23_C24, 0, + CM_OCSC_C23, tbl_entry->regval[6], + CM_OCSC_C24, tbl_entry->regval[7]); + + /*B*/ + REG_SET_2(CM_OCSC_C31_C32, 0, + CM_OCSC_C31, tbl_entry->regval[8], + CM_OCSC_C32, tbl_entry->regval[9]); + + REG_SET_2(CM_OCSC_C33_C34, 0, + CM_OCSC_C33, tbl_entry->regval[10], + CM_OCSC_C34, tbl_entry->regval[11]); + } else { + /*R*/ + REG_SET_2(CM_COMB_C11_C12, 0, + CM_COMB_C11, tbl_entry->regval[0], + CM_COMB_C12, tbl_entry->regval[1]); + + REG_SET_2(CM_COMB_C13_C14, 0, + CM_COMB_C13, tbl_entry->regval[2], + CM_COMB_C14, tbl_entry->regval[3]); + + /*G*/ + REG_SET_2(CM_COMB_C21_C22, 0, + CM_COMB_C21, tbl_entry->regval[4], + CM_COMB_C22, tbl_entry->regval[5]); + + REG_SET_2(CM_COMB_C23_C24, 0, + CM_COMB_C23, tbl_entry->regval[6], + CM_COMB_C24, tbl_entry->regval[7]); + + /*B*/ + REG_SET_2(CM_COMB_C31_C32, 0, + CM_COMB_C31, tbl_entry->regval[8], + CM_COMB_C32, tbl_entry->regval[9]); + + REG_SET_2(CM_COMB_C33_C34, 0, + CM_COMB_C33, tbl_entry->regval[10], + CM_COMB_C34, tbl_entry->regval[11]); + } +} + +static void oppn10_set_output_csc_adjustment( + struct transform *xfm_base, + const struct out_csc_color_matrix *tbl_entry) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; + uint32_t ocsc_mode = 4; + + /** + *if (tbl_entry != NULL) { + * switch (tbl_entry->color_space) { + * case COLOR_SPACE_SRGB: + * case COLOR_SPACE_2020_RGB_FULLRANGE: + * ocsc_mode = 0; + * break; + * case COLOR_SPACE_SRGB_LIMITED: + * case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + * ocsc_mode = 1; + * break; + * case COLOR_SPACE_YCBCR601: + * case COLOR_SPACE_YCBCR601_LIMITED: + * ocsc_mode = 2; + * break; + * case COLOR_SPACE_YCBCR709: + * case COLOR_SPACE_YCBCR709_LIMITED: + * case COLOR_SPACE_2020_YCBCR: + * ocsc_mode = 3; + * break; + * case COLOR_SPACE_UNKNOWN: + * default: + * break; + * } + *} + */ + + REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); + oppn10_program_color_matrix(xfm, tbl_entry); +} + static struct transform_funcs dcn10_dpp_funcs = { .transform_reset = dpp_reset, .transform_set_scaler = dpp_set_scaler_manual_scale, .transform_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, .transform_set_gamut_remap = dcn_dpp_set_gamut_remap, + .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment, + .opp_set_csc_default = oppn10_set_output_csc_default, }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index c1124e962d0e..693060e79d21 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -86,7 +86,14 @@ SRI(CM_COMB_C21_C22, CM, id),\ SRI(CM_COMB_C23_C24, CM, id),\ SRI(CM_COMB_C31_C32, CM, id),\ - SRI(CM_COMB_C33_C34, CM, id) + SRI(CM_COMB_C33_C34, CM, id),\ + SRI(CM_OCSC_CONTROL, CM, id), \ + SRI(CM_OCSC_C11_C12, CM, id), \ + SRI(CM_OCSC_C13_C14, CM, id), \ + SRI(CM_OCSC_C21_C22, CM, id), \ + SRI(CM_OCSC_C23_C24, CM, id), \ + SRI(CM_OCSC_C31_C32, CM, id), \ + SRI(CM_OCSC_C33_C34, CM, id) #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ @@ -194,7 +201,20 @@ TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh),\ TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\ TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh),\ - TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh) + TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\ + TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ + TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ + TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ + TF_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \ + TF_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \ + TF_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \ + TF_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \ + TF_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \ + TF_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \ + TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \ + TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \ + TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ + TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh) #define TF_REG_FIELD_LIST(type) \ @@ -300,7 +320,20 @@ type CM_COMB_C31; \ type CM_COMB_C32; \ type CM_COMB_C33; \ - type CM_COMB_C34 + type CM_COMB_C34; \ + type CM_OCSC_MODE; \ + type CM_OCSC_C11; \ + type CM_OCSC_C12; \ + type CM_OCSC_C13; \ + type CM_OCSC_C14; \ + type CM_OCSC_C21; \ + type CM_OCSC_C22; \ + type CM_OCSC_C23; \ + type CM_OCSC_C24; \ + type CM_OCSC_C31; \ + type CM_OCSC_C32; \ + type CM_OCSC_C33; \ + type CM_OCSC_C34 struct dcn_dpp_shift { TF_REG_FIELD_LIST(uint8_t); @@ -357,6 +390,13 @@ struct dcn_dpp_registers { uint32_t CM_COMB_C23_C24; uint32_t CM_COMB_C31_C32; uint32_t CM_COMB_C33_C34; + uint32_t CM_OCSC_CONTROL; + uint32_t CM_OCSC_C11_C12; + uint32_t CM_OCSC_C13_C14; + uint32_t CM_OCSC_C21_C22; + uint32_t CM_OCSC_C23_C24; + uint32_t CM_OCSC_C31_C32; + uint32_t CM_OCSC_C33_C34; }; struct dcn10_dpp { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 633d858caf6f..4cbca15e1cc5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1588,7 +1588,7 @@ static void update_dchubp_dpp( /*TODO add adjustments parameters*/ ocsc.out_color_space = pipe_ctx->stream->public.output_color_space; - pipe_ctx->opp->funcs->opp_set_csc_default(pipe_ctx->opp, &ocsc); + pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc); mi->funcs->mem_input_program_surface_config( mi, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index c2aa69deecc2..5cf985e4ffa9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -327,42 +327,7 @@ static void oppn10_program_fmt( return; } -static void oppn10_set_output_csc_default( - struct output_pixel_processor *opp, - const struct default_adjustment *default_adjust) -{ - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - uint32_t ocsc_mode = 0; - - if (default_adjust != NULL) { - switch (default_adjust->out_color_space) { - case COLOR_SPACE_SRGB: - case COLOR_SPACE_2020_RGB_FULLRANGE: - ocsc_mode = 0; - break; - case COLOR_SPACE_SRGB_LIMITED: - case COLOR_SPACE_2020_RGB_LIMITEDRANGE: - ocsc_mode = 1; - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR601_LIMITED: - ocsc_mode = 2; - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YCBCR709_LIMITED: - case COLOR_SPACE_2020_YCBCR: - ocsc_mode = 3; - break; - case COLOR_SPACE_UNKNOWN: - default: - break; - } - } - - REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); - -} /*program re gamma RAM B*/ static void opp_program_regamma_lutb_settings( struct output_pixel_processor *opp, @@ -714,117 +679,7 @@ static void oppn10_power_on_regamma_lut( } -static void oppn10_program_color_matrix(struct dcn10_opp *oppn10, - const struct out_csc_color_matrix *tbl_entry) -{ - uint32_t mode; - - REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode); - - if (tbl_entry == NULL) { - BREAK_TO_DEBUGGER(); - return; - } - - - if (mode == 4) { - /*R*/ - REG_SET_2(CM_OCSC_C11_C12, 0, - CM_OCSC_C11, tbl_entry->regval[0], - CM_OCSC_C12, tbl_entry->regval[1]); - - REG_SET_2(CM_OCSC_C13_C14, 0, - CM_OCSC_C13, tbl_entry->regval[2], - CM_OCSC_C14, tbl_entry->regval[3]); - /*G*/ - REG_SET_2(CM_OCSC_C21_C22, 0, - CM_OCSC_C21, tbl_entry->regval[4], - CM_OCSC_C22, tbl_entry->regval[5]); - - REG_SET_2(CM_OCSC_C23_C24, 0, - CM_OCSC_C23, tbl_entry->regval[6], - CM_OCSC_C24, tbl_entry->regval[7]); - - /*B*/ - REG_SET_2(CM_OCSC_C31_C32, 0, - CM_OCSC_C31, tbl_entry->regval[8], - CM_OCSC_C32, tbl_entry->regval[9]); - - REG_SET_2(CM_OCSC_C33_C34, 0, - CM_OCSC_C33, tbl_entry->regval[10], - CM_OCSC_C34, tbl_entry->regval[11]); - } else { - /*R*/ - REG_SET_2(CM_COMB_C11_C12, 0, - CM_COMB_C11, tbl_entry->regval[0], - CM_COMB_C12, tbl_entry->regval[1]); - - REG_SET_2(CM_COMB_C13_C14, 0, - CM_COMB_C13, tbl_entry->regval[2], - CM_COMB_C14, tbl_entry->regval[3]); - - /*G*/ - REG_SET_2(CM_COMB_C21_C22, 0, - CM_COMB_C21, tbl_entry->regval[4], - CM_COMB_C22, tbl_entry->regval[5]); - - REG_SET_2(CM_COMB_C23_C24, 0, - CM_COMB_C23, tbl_entry->regval[6], - CM_COMB_C24, tbl_entry->regval[7]); - - /*B*/ - REG_SET_2(CM_COMB_C31_C32, 0, - CM_COMB_C31, tbl_entry->regval[8], - CM_COMB_C32, tbl_entry->regval[9]); - - REG_SET_2(CM_COMB_C33_C34, 0, - CM_COMB_C33, tbl_entry->regval[10], - CM_COMB_C34, tbl_entry->regval[11]); - } -} - -static void oppn10_set_output_csc_adjustment( - struct output_pixel_processor *opp, - const struct out_csc_color_matrix *tbl_entry) -{ - - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; - - - uint32_t ocsc_mode = 4; - - /** - *if (tbl_entry != NULL) { - * switch (tbl_entry->color_space) { - * case COLOR_SPACE_SRGB: - * case COLOR_SPACE_2020_RGB_FULLRANGE: - * ocsc_mode = 0; - * break; - * case COLOR_SPACE_SRGB_LIMITED: - * case COLOR_SPACE_2020_RGB_LIMITEDRANGE: - * ocsc_mode = 1; - * break; - * case COLOR_SPACE_YCBCR601: - * case COLOR_SPACE_YCBCR601_LIMITED: - * ocsc_mode = 2; - * break; - * case COLOR_SPACE_YCBCR709: - * case COLOR_SPACE_YCBCR709_LIMITED: - * case COLOR_SPACE_2020_YCBCR: - * ocsc_mode = 3; - * break; - * case COLOR_SPACE_UNKNOWN: - * default: - * break; - * } - *} - */ - - REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); - oppn10_program_color_matrix(oppn10, tbl_entry); -} static void opp_program_regamma_lut( struct output_pixel_processor *opp, @@ -889,8 +744,6 @@ static void dcn10_opp_destroy(struct output_pixel_processor **opp) static struct opp_funcs dcn10_opp_funcs = { .opp_power_on_regamma_lut = oppn10_power_on_regamma_lut, - .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment, - .opp_set_csc_default = oppn10_set_output_csc_default, .opp_set_dyn_expansion = oppn10_set_dyn_expansion, .opp_program_regamma_pwl = oppn10_set_regamma_pwl, .opp_set_regamma_mode = oppn10_set_regamma_mode, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index d9d66a4afb19..900298d6e5b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -46,21 +46,8 @@ #define OPP_REG_LIST_DCN10(id) \ OPP_REG_LIST_DCN(id), \ - SRI(CM_OCSC_C11_C12, CM, id), \ - SRI(CM_OCSC_C13_C14, CM, id), \ - SRI(CM_OCSC_C21_C22, CM, id), \ - SRI(CM_OCSC_C23_C24, CM, id), \ - SRI(CM_OCSC_C31_C32, CM, id), \ - SRI(CM_OCSC_C33_C34, CM, id), \ - SRI(CM_COMB_C11_C12, CM, id), \ - SRI(CM_COMB_C13_C14, CM, id), \ - SRI(CM_COMB_C21_C22, CM, id), \ - SRI(CM_COMB_C23_C24, CM, id), \ - SRI(CM_COMB_C31_C32, CM, id), \ - SRI(CM_COMB_C33_C34, CM, id), \ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \ SRI(CM_RGAM_CONTROL, CM, id), \ - SRI(CM_OCSC_CONTROL, CM, id), \ SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ @@ -151,32 +138,7 @@ #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ OPP_MASK_SH_LIST_DCN(mask_sh), \ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ - OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh), \ - OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh), \ - OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh), \ - OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh), \ - OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh), \ - OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh), \ - OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh), \ - OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh), \ - OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh), \ - OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh), \ - OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh), \ - OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh), \ OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ - OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ @@ -414,7 +376,6 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type CM_OCSC_MODE; \ type CM_RGAM_RAMB_EXP_REGION_START_B; \ type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ type CM_RGAM_RAMB_EXP_REGION_START_G; \ @@ -630,7 +591,6 @@ struct dcn10_opp_registers { uint32_t FMT_CLAMP_CNTL; uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t FMT_MAP420_MEMORY_CONTROL; - uint32_t CM_OCSC_CONTROL; uint32_t CM_RGAM_RAMB_START_CNTL_B; uint32_t CM_RGAM_RAMB_START_CNTL_G; uint32_t CM_RGAM_RAMB_START_CNTL_R; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 0212618a36be..137b4c8dc9d5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -28,6 +28,7 @@ #include "os_types.h" #include "fixed31_32.h" +#include "dc_hw_types.h" /****************************************************************************** * Data types shared between different Virtual HW blocks @@ -76,4 +77,40 @@ struct pwl_params { struct pwl_result_data rgb_resulted[256 + 3]; uint32_t hw_points_num; }; + +/* move to dpp + * while we are moving functionality out of opp to dpp to align + * HW programming to HW IP, we define these struct in hw_shared + * so we can still compile while refactoring + */ + +enum lb_pixel_depth { + /* do not change the values because it is used as bit vector */ + LB_PIXEL_DEPTH_18BPP = 1, + LB_PIXEL_DEPTH_24BPP = 2, + LB_PIXEL_DEPTH_30BPP = 4, + LB_PIXEL_DEPTH_36BPP = 8 +}; + +enum graphics_csc_adjust_type { + GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ +}; + +struct default_adjustment { + enum lb_pixel_depth lb_color_depth; + enum dc_color_space out_color_space; + enum dc_color_space in_color_space; + enum dc_color_depth color_depth; + enum pixel_format surface_pixel_format; + enum graphics_csc_adjust_type csc_adjust_type; + bool force_hw_default; +}; + +struct out_csc_color_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + #endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 57bdd6c8f955..ef36ffdf2a68 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -217,22 +217,6 @@ enum fmt_stereo_action { FMT_STEREO_ACTION_UPDATE_POLARITY }; -enum graphics_csc_adjust_type { - GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, - GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ - GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ -}; - -struct default_adjustment { - enum lb_pixel_depth lb_color_depth; - enum dc_color_space out_color_space; - enum dc_color_space in_color_space; - enum dc_color_depth color_depth; - enum pixel_format surface_pixel_format; - enum graphics_csc_adjust_type csc_adjust_type; - bool force_hw_default; -}; - enum grph_color_adjust_option { GRPH_COLOR_MATRIX_HW_DEFAULT = 1, GRPH_COLOR_MATRIX_SW @@ -250,11 +234,6 @@ struct opp_grph_csc_adjustment { int32_t grph_hue; }; -struct out_csc_color_matrix { - enum dc_color_space color_space; - uint16_t regval[12]; -}; - /* Underlay related types */ struct hw_adjustment_range { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index b4862c376b41..132c5db07456 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -26,6 +26,7 @@ #ifndef __DAL_TRANSFORM_H__ #define __DAL_TRANSFORM_H__ +#include "hw_shared.h" #include "dc_hw_types.h" #include "fixed31_32.h" @@ -112,14 +113,6 @@ struct xfm_grph_csc_adjustment { enum graphics_gamut_adjust_type gamut_adjust_type; }; -enum lb_pixel_depth { - /* do not change the values because it is used as bit vector */ - LB_PIXEL_DEPTH_18BPP = 1, - LB_PIXEL_DEPTH_24BPP = 2, - LB_PIXEL_DEPTH_30BPP = 4, - LB_PIXEL_DEPTH_36BPP = 8 -}; - struct overscan_info { int left; int right; @@ -176,11 +169,6 @@ struct transform_funcs { void (*transform_set_scaler)(struct transform *xfm, const struct scaler_data *scl_data); - void (*transform_set_gamut_remap)( - struct transform *xfm, - const struct xfm_grph_csc_adjustment *adjust); - - void (*transform_set_pixel_storage_depth)( struct transform *xfm, enum lb_pixel_depth depth, @@ -190,6 +178,18 @@ struct transform_funcs { struct transform *xfm, struct scaler_data *scl_data, const struct scaling_taps *in_taps); + + void (*transform_set_gamut_remap)( + struct transform *xfm, + const struct xfm_grph_csc_adjustment *adjust); + + void (*opp_set_csc_default)( + struct transform *xfm, + const struct default_adjustment *default_adjust); + + void (*opp_set_csc_adjustment)( + struct transform *xfm, + const struct out_csc_color_matrix *tbl_entry); }; extern const uint16_t filter_2tap_16p[18]; -- cgit v1.2.3-59-g8ed1b From c8d7bd8bd0c08aa9115589d264e274ed7fdf4c2e Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Sun, 23 Jul 2017 12:13:37 -0400 Subject: drm/amd/display: move RGAM programming from opp to dpp Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 432 ++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 499 ++++++++++++++++++++- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 428 ------------------ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 492 +------------------- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 7 + drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 7 - drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 29 ++ 8 files changed, 972 insertions(+), 938 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 0f3f1a31f10b..b6aaa95d442b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -1134,6 +1134,431 @@ static void oppn10_set_output_csc_adjustment( oppn10_program_color_matrix(xfm, tbl_entry); } +static void oppn10_power_on_regamma_lut( + struct transform *xfm_base, + bool power_on) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + REG_SET(CM_MEM_PWR_CTRL, 0, + RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); + +} + +static void opp_program_regamma_lut( + struct transform *xfm_base, + const struct pwl_result_data *rgb, + uint32_t num) +{ + uint32_t i; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + for (i = 0 ; i < num; i++) { + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); + + REG_SET(CM_RGAM_LUT_DATA, 0, + CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, + CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, + CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); + + } + +} + +static void opp_configure_regamma_lut( + struct transform *xfm_base, + bool is_ram_a) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, + CM_RGAM_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, + CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0); +} + +/*program re gamma RAM A*/ +static void opp_program_regamma_luta_settings( + struct transform *xfm_base, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_SET_2(CM_RGAM_RAMA_START_CNTL_B, 0, + CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x, + CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(CM_RGAM_RAMA_START_CNTL_G, 0, + CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x, + CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0); + REG_SET_2(CM_RGAM_RAMA_START_CNTL_R, 0, + CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x, + CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0); + + REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_B, 0, + CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); + REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_G, 0, + CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); + REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_R, 0, + CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); + + REG_SET(CM_RGAM_RAMA_END_CNTL1_B, 0, + CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x); + REG_SET_2(CM_RGAM_RAMA_END_CNTL2_B, 0, + CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope, + CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y); + + REG_SET(CM_RGAM_RAMA_END_CNTL1_G, 0, + CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x); + REG_SET_2(CM_RGAM_RAMA_END_CNTL2_G, 0, + CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope, + CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y); + + REG_SET(CM_RGAM_RAMA_END_CNTL1_R, 0, + CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x); + REG_SET_2(CM_RGAM_RAMA_END_CNTL2_R, 0, + CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope, + CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y); + + curve = params->arr_curve_points; + REG_SET_4(CM_RGAM_RAMA_REGION_0_1, 0, + CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_2_3, 0, + CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_4_5, 0, + CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_6_7, 0, + CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_8_9, 0, + CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_10_11, 0, + CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_12_13, 0, + CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_14_15, 0, + CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_16_17, 0, + CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_18_19, 0, + CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_20_21, 0, + CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_22_23, 0, + CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_24_25, 0, + CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_26_27, 0, + CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_28_29, 0, + CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_30_31, 0, + CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMA_REGION_32_33, 0, + CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); +} + +/*program re gamma RAM B*/ +static void opp_program_regamma_lutb_settings( + struct transform *xfm_base, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_SET_2(CM_RGAM_RAMB_START_CNTL_B, 0, + CM_RGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x, + CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(CM_RGAM_RAMB_START_CNTL_G, 0, + CM_RGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x, + CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0); + REG_SET_2(CM_RGAM_RAMB_START_CNTL_R, 0, + CM_RGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x, + CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0); + + REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_B, 0, + CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); + REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_G, 0, + CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); + REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_R, 0, + CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); + + REG_SET(CM_RGAM_RAMB_END_CNTL1_B, 0, + CM_RGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x); + REG_SET_2(CM_RGAM_RAMB_END_CNTL2_B, 0, + CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope, + CM_RGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y); + + REG_SET(CM_RGAM_RAMB_END_CNTL1_G, 0, + CM_RGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x); + REG_SET_2(CM_RGAM_RAMB_END_CNTL2_G, 0, + CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope, + CM_RGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y); + + REG_SET(CM_RGAM_RAMB_END_CNTL1_R, 0, + CM_RGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x); + REG_SET_2(CM_RGAM_RAMB_END_CNTL2_R, 0, + CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope, + CM_RGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y); + + curve = params->arr_curve_points; + REG_SET_4(CM_RGAM_RAMB_REGION_0_1, 0, + CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_2_3, 0, + CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_4_5, 0, + CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_6_7, 0, + CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_8_9, 0, + CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_10_11, 0, + CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_12_13, 0, + CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_14_15, 0, + CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_16_17, 0, + CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_18_19, 0, + CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_20_21, 0, + CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_22_23, 0, + CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_24_25, 0, + CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_26_27, 0, + CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_28_29, 0, + CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_30_31, 0, + CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_RGAM_RAMB_REGION_32_33, 0, + CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, + CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, + CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, + CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); + +} + +static bool oppn10_set_regamma_pwl( + struct transform *xfm_base, const struct pwl_params *params) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + oppn10_power_on_regamma_lut(xfm_base, true); + opp_configure_regamma_lut(xfm_base, xfm->is_write_to_ram_a_safe); + + if (xfm->is_write_to_ram_a_safe) + opp_program_regamma_luta_settings(xfm_base, params); + else + opp_program_regamma_lutb_settings(xfm_base, params); + + opp_program_regamma_lut( + xfm_base, params->rgb_resulted, params->hw_points_num); + + return true; +} + +static void oppn10_set_regamma_mode( + struct transform *xfm_base, + enum opp_regamma mode) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + uint32_t re_mode = 0; + uint32_t obuf_bypass = 0; /* need for pipe split */ + uint32_t obuf_hupscale = 0; + + switch (mode) { + case OPP_REGAMMA_BYPASS: + re_mode = 0; + break; + case OPP_REGAMMA_SRGB: + re_mode = 1; + break; + case OPP_REGAMMA_3_6: + re_mode = 2; + break; + case OPP_REGAMMA_USER: + re_mode = xfm->is_write_to_ram_a_safe ? 3 : 4; + xfm->is_write_to_ram_a_safe = !xfm->is_write_to_ram_a_safe; + break; + default: + break; + } + + REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); + REG_UPDATE_2(OBUF_CONTROL, + OBUF_BYPASS, obuf_bypass, + OBUF_H_2X_UPSCALE_EN, obuf_hupscale); +} + static struct transform_funcs dcn10_dpp_funcs = { .transform_reset = dpp_reset, .transform_set_scaler = dpp_set_scaler_manual_scale, @@ -1141,6 +1566,13 @@ static struct transform_funcs dcn10_dpp_funcs = { .transform_set_gamut_remap = dcn_dpp_set_gamut_remap, .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment, .opp_set_csc_default = oppn10_set_output_csc_default, + .opp_power_on_regamma_lut = oppn10_power_on_regamma_lut, + .opp_program_regamma_lut = opp_program_regamma_lut, + .opp_configure_regamma_lut = opp_configure_regamma_lut, + .opp_program_regamma_lutb_settings = opp_program_regamma_lutb_settings, + .opp_program_regamma_luta_settings = opp_program_regamma_luta_settings, + .opp_program_regamma_pwl = oppn10_set_regamma_pwl, + .opp_set_regamma_mode = oppn10_set_regamma_mode }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 693060e79d21..34085c0818e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -71,7 +71,8 @@ SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \ SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ SRI(RECOUT_START, DSCL, id), \ - SRI(RECOUT_SIZE, DSCL, id) + SRI(RECOUT_SIZE, DSCL, id), \ + SRI(OBUF_CONTROL, DSCL, id) #define TF_REG_LIST_DCN10(id) \ TF_REG_LIST_DCN(id), \ @@ -93,7 +94,70 @@ SRI(CM_OCSC_C21_C22, CM, id), \ SRI(CM_OCSC_C23_C24, CM, id), \ SRI(CM_OCSC_C31_C32, CM, id), \ - SRI(CM_OCSC_C33_C34, CM, id) + SRI(CM_OCSC_C33_C34, CM, id), \ + SRI(CM_MEM_PWR_CTRL, CM, id), \ + SRI(CM_RGAM_LUT_DATA, CM, id), \ + SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ + SRI(CM_RGAM_LUT_INDEX, CM, id), \ + SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_2_3, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_4_5, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_6_7, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_8_9, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_10_11, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_12_13, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_14_15, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_16_17, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_18_19, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_20_21, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_22_23, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_24_25, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_26_27, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_28_29, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_30_31, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \ + SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_2_3, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_4_5, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_6_7, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_8_9, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_10_11, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_12_13, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_14_15, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_16_17, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_18_19, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_20_21, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_22_23, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_24_25, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_26_27, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ + SRI(CM_RGAM_CONTROL, CM, id) #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ @@ -169,7 +233,8 @@ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ - TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh) + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ + TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh) #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\ TF_REG_LIST_SH_MASK_DCN(mask_sh),\ @@ -214,7 +279,186 @@ TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \ TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ - TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh) + TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ + TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ + TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh) #define TF_REG_FIELD_LIST(type) \ @@ -333,7 +577,187 @@ type CM_OCSC_C31; \ type CM_OCSC_C32; \ type CM_OCSC_C33; \ - type CM_OCSC_C34 + type CM_OCSC_C34; \ + type RGAM_MEM_PWR_FORCE; \ + type CM_RGAM_LUT_DATA; \ + type CM_RGAM_LUT_WRITE_EN_MASK; \ + type CM_RGAM_LUT_WRITE_SEL; \ + type CM_RGAM_LUT_INDEX; \ + type CM_RGAM_RAMB_EXP_REGION_START_B; \ + type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ + type CM_RGAM_RAMB_EXP_REGION_START_G; \ + type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ + type CM_RGAM_RAMB_EXP_REGION_START_R; \ + type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ + type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ + type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ + type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ + type CM_RGAM_RAMB_EXP_REGION_END_B; \ + type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \ + type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \ + type CM_RGAM_RAMB_EXP_REGION_END_G; \ + type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \ + type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \ + type CM_RGAM_RAMB_EXP_REGION_END_R; \ + type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \ + type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \ + type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION_START_B; \ + type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ + type CM_RGAM_RAMA_EXP_REGION_START_G; \ + type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ + type CM_RGAM_RAMA_EXP_REGION_START_R; \ + type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ + type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ + type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ + type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ + type CM_RGAM_RAMA_EXP_REGION_END_B; \ + type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \ + type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \ + type CM_RGAM_RAMA_EXP_REGION_END_G; \ + type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \ + type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \ + type CM_RGAM_RAMA_EXP_REGION_END_R; \ + type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \ + type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \ + type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type CM_RGAM_LUT_MODE; \ + type OBUF_BYPASS; \ + type OBUF_H_2X_UPSCALE_EN struct dcn_dpp_shift { TF_REG_FIELD_LIST(uint8_t); @@ -397,6 +821,70 @@ struct dcn_dpp_registers { uint32_t CM_OCSC_C23_C24; uint32_t CM_OCSC_C31_C32; uint32_t CM_OCSC_C33_C34; + uint32_t CM_MEM_PWR_CTRL; + uint32_t CM_RGAM_LUT_DATA; + uint32_t CM_RGAM_LUT_WRITE_EN_MASK; + uint32_t CM_RGAM_LUT_INDEX; + uint32_t CM_RGAM_RAMB_START_CNTL_B; + uint32_t CM_RGAM_RAMB_START_CNTL_G; + uint32_t CM_RGAM_RAMB_START_CNTL_R; + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; + uint32_t CM_RGAM_RAMB_END_CNTL1_B; + uint32_t CM_RGAM_RAMB_END_CNTL2_B; + uint32_t CM_RGAM_RAMB_END_CNTL1_G; + uint32_t CM_RGAM_RAMB_END_CNTL2_G; + uint32_t CM_RGAM_RAMB_END_CNTL1_R; + uint32_t CM_RGAM_RAMB_END_CNTL2_R; + uint32_t CM_RGAM_RAMB_REGION_0_1; + uint32_t CM_RGAM_RAMB_REGION_2_3; + uint32_t CM_RGAM_RAMB_REGION_4_5; + uint32_t CM_RGAM_RAMB_REGION_6_7; + uint32_t CM_RGAM_RAMB_REGION_8_9; + uint32_t CM_RGAM_RAMB_REGION_10_11; + uint32_t CM_RGAM_RAMB_REGION_12_13; + uint32_t CM_RGAM_RAMB_REGION_14_15; + uint32_t CM_RGAM_RAMB_REGION_16_17; + uint32_t CM_RGAM_RAMB_REGION_18_19; + uint32_t CM_RGAM_RAMB_REGION_20_21; + uint32_t CM_RGAM_RAMB_REGION_22_23; + uint32_t CM_RGAM_RAMB_REGION_24_25; + uint32_t CM_RGAM_RAMB_REGION_26_27; + uint32_t CM_RGAM_RAMB_REGION_28_29; + uint32_t CM_RGAM_RAMB_REGION_30_31; + uint32_t CM_RGAM_RAMB_REGION_32_33; + uint32_t CM_RGAM_RAMA_START_CNTL_B; + uint32_t CM_RGAM_RAMA_START_CNTL_G; + uint32_t CM_RGAM_RAMA_START_CNTL_R; + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; + uint32_t CM_RGAM_RAMA_END_CNTL1_B; + uint32_t CM_RGAM_RAMA_END_CNTL2_B; + uint32_t CM_RGAM_RAMA_END_CNTL1_G; + uint32_t CM_RGAM_RAMA_END_CNTL2_G; + uint32_t CM_RGAM_RAMA_END_CNTL1_R; + uint32_t CM_RGAM_RAMA_END_CNTL2_R; + uint32_t CM_RGAM_RAMA_REGION_0_1; + uint32_t CM_RGAM_RAMA_REGION_2_3; + uint32_t CM_RGAM_RAMA_REGION_4_5; + uint32_t CM_RGAM_RAMA_REGION_6_7; + uint32_t CM_RGAM_RAMA_REGION_8_9; + uint32_t CM_RGAM_RAMA_REGION_10_11; + uint32_t CM_RGAM_RAMA_REGION_12_13; + uint32_t CM_RGAM_RAMA_REGION_14_15; + uint32_t CM_RGAM_RAMA_REGION_16_17; + uint32_t CM_RGAM_RAMA_REGION_18_19; + uint32_t CM_RGAM_RAMA_REGION_20_21; + uint32_t CM_RGAM_RAMA_REGION_22_23; + uint32_t CM_RGAM_RAMA_REGION_24_25; + uint32_t CM_RGAM_RAMA_REGION_26_27; + uint32_t CM_RGAM_RAMA_REGION_28_29; + uint32_t CM_RGAM_RAMA_REGION_30_31; + uint32_t CM_RGAM_RAMA_REGION_32_33; + uint32_t CM_RGAM_CONTROL; + uint32_t OBUF_CONTROL; }; struct dcn10_dpp { @@ -413,6 +901,7 @@ struct dcn10_dpp { int lb_pixel_depth_supported; int lb_memory_size; int lb_bits_per_entry; + bool is_write_to_ram_a_safe; }; bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 4cbca15e1cc5..d61b63df16b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1054,25 +1054,25 @@ static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, const struct core_stream *stream) { - struct output_pixel_processor *opp = pipe_ctx->opp; + struct transform *xfm = pipe_ctx->xfm; - if (opp == NULL) + if (xfm == NULL) return false; - opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; + xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->public.out_transfer_func && stream->public.out_transfer_func->type == TF_TYPE_PREDEFINED && stream->public.out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); + xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); } else if (dcn10_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &opp->regamma_params)) { - opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); + stream->public.out_transfer_func, &xfm->regamma_params)) { + xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); + xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { - opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); + xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); } return true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 5cf985e4ffa9..f8e4724a629d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -37,38 +37,7 @@ #define CTX \ oppn10->base.ctx -static void oppn10_set_regamma_mode( - struct output_pixel_processor *opp, - enum opp_regamma mode) -{ - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - uint32_t re_mode = 0; - uint32_t obuf_bypass = 0; /* need for pipe split */ - uint32_t obuf_hupscale = 0; - - switch (mode) { - case OPP_REGAMMA_BYPASS: - re_mode = 0; - break; - case OPP_REGAMMA_SRGB: - re_mode = 1; - break; - case OPP_REGAMMA_3_6: - re_mode = 2; - break; - case OPP_REGAMMA_USER: - re_mode = oppn10->is_write_to_ram_a_safe ? 3 : 4; - oppn10->is_write_to_ram_a_safe = !oppn10->is_write_to_ram_a_safe; - break; - default: - break; - } - REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); - REG_UPDATE_2(OBUF_CONTROL, - OBUF_BYPASS, obuf_bypass, - OBUF_H_2X_UPSCALE_EN, obuf_hupscale); -} /************* FORMATTER ************/ @@ -328,400 +297,6 @@ static void oppn10_program_fmt( } -/*program re gamma RAM B*/ -static void opp_program_regamma_lutb_settings( - struct output_pixel_processor *opp, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - - REG_SET_2(CM_RGAM_RAMB_START_CNTL_B, 0, - CM_RGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x, - CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0); - REG_SET_2(CM_RGAM_RAMB_START_CNTL_G, 0, - CM_RGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x, - CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0); - REG_SET_2(CM_RGAM_RAMB_START_CNTL_R, 0, - CM_RGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x, - CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_B, 0, - CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); - REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_G, 0, - CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); - REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_R, 0, - CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); - - REG_SET(CM_RGAM_RAMB_END_CNTL1_B, 0, - CM_RGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x); - REG_SET_2(CM_RGAM_RAMB_END_CNTL2_B, 0, - CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope, - CM_RGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y); - - REG_SET(CM_RGAM_RAMB_END_CNTL1_G, 0, - CM_RGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x); - REG_SET_2(CM_RGAM_RAMB_END_CNTL2_G, 0, - CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope, - CM_RGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y); - - REG_SET(CM_RGAM_RAMB_END_CNTL1_R, 0, - CM_RGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x); - REG_SET_2(CM_RGAM_RAMB_END_CNTL2_R, 0, - CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope, - CM_RGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y); - - curve = params->arr_curve_points; - REG_SET_4(CM_RGAM_RAMB_REGION_0_1, 0, - CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_2_3, 0, - CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_4_5, 0, - CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_6_7, 0, - CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_8_9, 0, - CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_10_11, 0, - CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_12_13, 0, - CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_14_15, 0, - CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_16_17, 0, - CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_18_19, 0, - CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_20_21, 0, - CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_22_23, 0, - CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_24_25, 0, - CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_26_27, 0, - CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_28_29, 0, - CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_30_31, 0, - CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMB_REGION_32_33, 0, - CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); - -} - -/*program re gamma RAM A*/ -static void opp_program_regamma_luta_settings( - struct output_pixel_processor *opp, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - - REG_SET_2(CM_RGAM_RAMA_START_CNTL_B, 0, - CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x, - CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0); - REG_SET_2(CM_RGAM_RAMA_START_CNTL_G, 0, - CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x, - CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0); - REG_SET_2(CM_RGAM_RAMA_START_CNTL_R, 0, - CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x, - CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_B, 0, - CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); - REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_G, 0, - CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); - REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_R, 0, - CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); - - REG_SET(CM_RGAM_RAMA_END_CNTL1_B, 0, - CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x); - REG_SET_2(CM_RGAM_RAMA_END_CNTL2_B, 0, - CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope, - CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y); - - REG_SET(CM_RGAM_RAMA_END_CNTL1_G, 0, - CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x); - REG_SET_2(CM_RGAM_RAMA_END_CNTL2_G, 0, - CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope, - CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y); - - REG_SET(CM_RGAM_RAMA_END_CNTL1_R, 0, - CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x); - REG_SET_2(CM_RGAM_RAMA_END_CNTL2_R, 0, - CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope, - CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y); - - curve = params->arr_curve_points; - REG_SET_4(CM_RGAM_RAMA_REGION_0_1, 0, - CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_2_3, 0, - CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_4_5, 0, - CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_6_7, 0, - CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_8_9, 0, - CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_10_11, 0, - CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_12_13, 0, - CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_14_15, 0, - CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_16_17, 0, - CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_18_19, 0, - CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_20_21, 0, - CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_22_23, 0, - CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_24_25, 0, - CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_26_27, 0, - CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_28_29, 0, - CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_30_31, 0, - CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_RGAM_RAMA_REGION_32_33, 0, - CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, - CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, - CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, - CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); -} - -static void opp_configure_regamma_lut( - struct output_pixel_processor *opp, - bool is_ram_a) -{ - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - - REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, - CM_RGAM_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, - CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); - REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0); -} - -static void oppn10_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on) -{ - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - REG_SET(CM_MEM_PWR_CTRL, 0, - RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); - -} - - - - -static void opp_program_regamma_lut( - struct output_pixel_processor *opp, - const struct pwl_result_data *rgb, - uint32_t num) -{ - uint32_t i; - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - for (i = 0 ; i < num; i++) { - REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); - - } - -} - -static bool oppn10_set_regamma_pwl( - struct output_pixel_processor *opp, const struct pwl_params *params) -{ - struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - - oppn10_power_on_regamma_lut(opp, true); - opp_configure_regamma_lut(opp, oppn10->is_write_to_ram_a_safe); - - if (oppn10->is_write_to_ram_a_safe) - opp_program_regamma_luta_settings(opp, params); - else - opp_program_regamma_lutb_settings(opp, params); - - opp_program_regamma_lut( - opp, params->rgb_resulted, params->hw_points_num); - - return true; -} static void oppn10_set_stereo_polarity( struct output_pixel_processor *opp, @@ -743,10 +318,7 @@ static void dcn10_opp_destroy(struct output_pixel_processor **opp) } static struct opp_funcs dcn10_opp_funcs = { - .opp_power_on_regamma_lut = oppn10_power_on_regamma_lut, .opp_set_dyn_expansion = oppn10_set_dyn_expansion, - .opp_program_regamma_pwl = oppn10_set_regamma_pwl, - .opp_set_regamma_mode = oppn10_set_regamma_mode, .opp_program_fmt = oppn10_program_fmt, .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction, .opp_set_stereo_polarity = oppn10_set_stereo_polarity, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 900298d6e5b5..790ce6014832 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -34,7 +34,6 @@ .field_name = reg_name ## __ ## field_name ## post_fix #define OPP_REG_LIST_DCN(id) \ - SRI(OBUF_CONTROL, DSCL, id), \ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ SRI(FMT_CONTROL, FMT, id), \ SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ @@ -45,73 +44,9 @@ SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id) #define OPP_REG_LIST_DCN10(id) \ - OPP_REG_LIST_DCN(id), \ - SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \ - SRI(CM_RGAM_CONTROL, CM, id), \ - SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ - SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ - SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ - SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \ - SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \ - SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \ - SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \ - SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \ - SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \ - SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \ - SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \ - SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_2_3, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_4_5, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_6_7, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_8_9, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_10_11, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_12_13, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_14_15, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_16_17, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_18_19, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_20_21, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_22_23, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_24_25, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_26_27, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_28_29, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_30_31, CM, id), \ - SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \ - SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \ - SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \ - SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \ - SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \ - SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \ - SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \ - SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \ - SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \ - SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \ - SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \ - SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \ - SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_2_3, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_4_5, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_6_7, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_8_9, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_10_11, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_12_13, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_14_15, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_16_17, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_18_19, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_20_21, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_22_23, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_24_25, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_26_27, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \ - SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ - SRI(CM_RGAM_LUT_INDEX, CM, id), \ - SRI(CM_MEM_PWR_CTRL, CM, id), \ - SRI(CM_RGAM_LUT_DATA, CM, id) + OPP_REG_LIST_DCN(id) #define OPP_MASK_SH_LIST_DCN(mask_sh) \ - OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ @@ -136,186 +71,7 @@ OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh) #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ - OPP_MASK_SH_LIST_DCN(mask_sh), \ - OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ - OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ - OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ - OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ - OPP_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ - OPP_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ - OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh) + OPP_MASK_SH_LIST_DCN(mask_sh) #define OPP_DCN10_REG_FIELD_LIST(type) \ type DPG_EN; \ @@ -352,9 +108,6 @@ type CM_COMB_C32; \ type CM_COMB_C33; \ type CM_COMB_C34; \ - type CM_RGAM_LUT_MODE; \ - type OBUF_BYPASS; \ - type OBUF_H_2X_UPSCALE_EN; \ type FMT_TRUNCATE_EN; \ type FMT_TRUNCATE_DEPTH; \ type FMT_TRUNCATE_MODE; \ @@ -376,183 +129,6 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type CM_RGAM_RAMB_EXP_REGION_START_B; \ - type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ - type CM_RGAM_RAMB_EXP_REGION_START_G; \ - type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ - type CM_RGAM_RAMB_EXP_REGION_START_R; \ - type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ - type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ - type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ - type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ - type CM_RGAM_RAMB_EXP_REGION_END_B; \ - type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \ - type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \ - type CM_RGAM_RAMB_EXP_REGION_END_G; \ - type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \ - type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \ - type CM_RGAM_RAMB_EXP_REGION_END_R; \ - type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \ - type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \ - type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ - type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ - type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION_START_B; \ - type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ - type CM_RGAM_RAMA_EXP_REGION_START_G; \ - type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ - type CM_RGAM_RAMA_EXP_REGION_START_R; \ - type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ - type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ - type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ - type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ - type CM_RGAM_RAMA_EXP_REGION_END_B; \ - type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \ - type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \ - type CM_RGAM_RAMA_EXP_REGION_END_G; \ - type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \ - type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \ - type CM_RGAM_RAMA_EXP_REGION_END_R; \ - type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \ - type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \ - type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ - type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ - type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ - type CM_RGAM_LUT_WRITE_EN_MASK; \ - type CM_RGAM_LUT_WRITE_SEL; \ - type CM_RGAM_LUT_INDEX; \ - type RGAM_MEM_PWR_FORCE; \ - type CM_RGAM_LUT_DATA; \ type FMT_STEREOSYNC_OVERRIDE struct dcn10_opp_shift { @@ -580,9 +156,6 @@ struct dcn10_opp_registers { uint32_t CM_COMB_C23_C24; uint32_t CM_COMB_C31_C32; uint32_t CM_COMB_C33_C34; - uint32_t CM_RGAM_LUT_WRITE_EN_MASK; - uint32_t CM_RGAM_CONTROL; - uint32_t OBUF_CONTROL; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; uint32_t FMT_DITHER_RAND_R_SEED; @@ -591,67 +164,6 @@ struct dcn10_opp_registers { uint32_t FMT_CLAMP_CNTL; uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t FMT_MAP420_MEMORY_CONTROL; - uint32_t CM_RGAM_RAMB_START_CNTL_B; - uint32_t CM_RGAM_RAMB_START_CNTL_G; - uint32_t CM_RGAM_RAMB_START_CNTL_R; - uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; - uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; - uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; - uint32_t CM_RGAM_RAMB_END_CNTL1_B; - uint32_t CM_RGAM_RAMB_END_CNTL2_B; - uint32_t CM_RGAM_RAMB_END_CNTL1_G; - uint32_t CM_RGAM_RAMB_END_CNTL2_G; - uint32_t CM_RGAM_RAMB_END_CNTL1_R; - uint32_t CM_RGAM_RAMB_END_CNTL2_R; - uint32_t CM_RGAM_RAMB_REGION_0_1; - uint32_t CM_RGAM_RAMB_REGION_2_3; - uint32_t CM_RGAM_RAMB_REGION_4_5; - uint32_t CM_RGAM_RAMB_REGION_6_7; - uint32_t CM_RGAM_RAMB_REGION_8_9; - uint32_t CM_RGAM_RAMB_REGION_10_11; - uint32_t CM_RGAM_RAMB_REGION_12_13; - uint32_t CM_RGAM_RAMB_REGION_14_15; - uint32_t CM_RGAM_RAMB_REGION_16_17; - uint32_t CM_RGAM_RAMB_REGION_18_19; - uint32_t CM_RGAM_RAMB_REGION_20_21; - uint32_t CM_RGAM_RAMB_REGION_22_23; - uint32_t CM_RGAM_RAMB_REGION_24_25; - uint32_t CM_RGAM_RAMB_REGION_26_27; - uint32_t CM_RGAM_RAMB_REGION_28_29; - uint32_t CM_RGAM_RAMB_REGION_30_31; - uint32_t CM_RGAM_RAMB_REGION_32_33; - uint32_t CM_RGAM_RAMA_START_CNTL_B; - uint32_t CM_RGAM_RAMA_START_CNTL_G; - uint32_t CM_RGAM_RAMA_START_CNTL_R; - uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; - uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; - uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; - uint32_t CM_RGAM_RAMA_END_CNTL1_B; - uint32_t CM_RGAM_RAMA_END_CNTL2_B; - uint32_t CM_RGAM_RAMA_END_CNTL1_G; - uint32_t CM_RGAM_RAMA_END_CNTL2_G; - uint32_t CM_RGAM_RAMA_END_CNTL1_R; - uint32_t CM_RGAM_RAMA_END_CNTL2_R; - uint32_t CM_RGAM_RAMA_REGION_0_1; - uint32_t CM_RGAM_RAMA_REGION_2_3; - uint32_t CM_RGAM_RAMA_REGION_4_5; - uint32_t CM_RGAM_RAMA_REGION_6_7; - uint32_t CM_RGAM_RAMA_REGION_8_9; - uint32_t CM_RGAM_RAMA_REGION_10_11; - uint32_t CM_RGAM_RAMA_REGION_12_13; - uint32_t CM_RGAM_RAMA_REGION_14_15; - uint32_t CM_RGAM_RAMA_REGION_16_17; - uint32_t CM_RGAM_RAMA_REGION_18_19; - uint32_t CM_RGAM_RAMA_REGION_20_21; - uint32_t CM_RGAM_RAMA_REGION_22_23; - uint32_t CM_RGAM_RAMA_REGION_24_25; - uint32_t CM_RGAM_RAMA_REGION_26_27; - uint32_t CM_RGAM_RAMA_REGION_28_29; - uint32_t CM_RGAM_RAMA_REGION_30_31; - uint32_t CM_RGAM_RAMA_REGION_32_33; - uint32_t CM_RGAM_LUT_INDEX; - uint32_t CM_MEM_PWR_CTRL; - uint32_t CM_RGAM_LUT_DATA; }; struct dcn10_opp { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 137b4c8dc9d5..589bddad7e66 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -113,4 +113,11 @@ struct out_csc_color_matrix { uint16_t regval[12]; }; +enum opp_regamma { + OPP_REGAMMA_BYPASS = 0, + OPP_REGAMMA_SRGB, + OPP_REGAMMA_3_6, + OPP_REGAMMA_USER +}; + #endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index ef36ffdf2a68..a43a09b3f414 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -196,13 +196,6 @@ struct pwl_float_data { struct fixed31_32 b; }; -enum opp_regamma { - OPP_REGAMMA_BYPASS = 0, - OPP_REGAMMA_SRGB, - OPP_REGAMMA_3_6, - OPP_REGAMMA_USER, -}; - struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 132c5db07456..f3d66752ed90 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -38,6 +38,7 @@ struct transform { const struct transform_funcs *funcs; struct dc_context *ctx; int inst; + struct pwl_params regamma_params; }; /* Colorimetry */ @@ -190,6 +191,34 @@ struct transform_funcs { void (*opp_set_csc_adjustment)( struct transform *xfm, const struct out_csc_color_matrix *tbl_entry); + + void (*opp_power_on_regamma_lut)( + struct transform *xfm, + bool power_on); + + void (*opp_program_regamma_lut)( + struct transform *xfm, + const struct pwl_result_data *rgb, + uint32_t num); + + void (*opp_configure_regamma_lut)( + struct transform *xfm, + bool is_ram_a); + + void (*opp_program_regamma_lutb_settings)( + struct transform *xfm, + const struct pwl_params *params); + + void (*opp_program_regamma_luta_settings)( + struct transform *xfm, + const struct pwl_params *params); + + bool (*opp_program_regamma_pwl)( + struct transform *xfm, const struct pwl_params *params); + + void (*opp_set_regamma_mode)( + struct transform *xfm_base, + enum opp_regamma mode); }; extern const uint16_t filter_2tap_16p[18]; -- cgit v1.2.3-59-g8ed1b From b3c340fad4643b7351a4777fae37e58925db04c9 Mon Sep 17 00:00:00 2001 From: Yue Hin Lau Date: Sat, 19 Aug 2017 16:34:36 -0400 Subject: drm/amd/display: move cm registers from ipp to dpp_cm Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 150 +++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 489 ++++++++++++++- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 555 +++++++++++++++++ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 676 +-------------------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 416 ------------- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 18 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 17 +- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 20 + 10 files changed, 1239 insertions(+), 1125 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h') diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 30722495de0a..20163668e2a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -52,6 +52,12 @@ #define FN(reg_name, field_name) \ xfm->tf_shift->field_name, xfm->tf_mask->field_name +enum pixel_format_description { + PIXEL_FORMAT_FIXED = 0, + PIXEL_FORMAT_FIXED16, + PIXEL_FORMAT_FLOAT + +}; enum dcn10_coef_filter_type_sel { SCL_COEF_LUMA_VERT_FILTER = 0, @@ -249,6 +255,145 @@ static void dcn10_dpp_cm_set_regamma_mode( OBUF_H_2X_UPSCALE_EN, obuf_hupscale); } +static void ippn10_setup_format_flags(enum surface_pixel_format input_format,\ + enum pixel_format_description *fmt) +{ + + if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || + input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) + *fmt = PIXEL_FORMAT_FLOAT; + else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) + *fmt = PIXEL_FORMAT_FIXED16; + else + *fmt = PIXEL_FORMAT_FIXED; +} + +static void ippn10_set_degamma_format_float( + struct transform *xfm_base, + bool is_float) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + if (is_float) { + REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); + REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); + } else { + REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); + REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); + } +} + +void ippn10_cnv_setup ( + struct transform *xfm_base, + enum surface_pixel_format input_format, + enum expansion_mode mode, + enum ipp_output_format cnv_out_format) +{ + uint32_t pixel_format; + uint32_t alpha_en; + enum pixel_format_description fmt ; + enum dc_color_space color_space; + enum dcn10_input_csc_select select; + bool is_float; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + bool force_disable_cursor = false; + + ippn10_setup_format_flags(input_format, &fmt); + alpha_en = 1; + pixel_format = 0; + color_space = COLOR_SPACE_SRGB; + select = INPUT_CSC_SELECT_BYPASS; + is_float = false; + + switch (fmt) { + case PIXEL_FORMAT_FIXED: + case PIXEL_FORMAT_FIXED16: + /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ + REG_SET_3(FORMAT_CONTROL, 0, + CNVC_BYPASS, 0, + FORMAT_EXPANSION_MODE, mode, + OUTPUT_FP, 0); + break; + case PIXEL_FORMAT_FLOAT: + REG_SET_3(FORMAT_CONTROL, 0, + CNVC_BYPASS, 0, + FORMAT_EXPANSION_MODE, mode, + OUTPUT_FP, 1); + is_float = true; + break; + default: + + break; + } + + ippn10_set_degamma_format_float(xfm_base, is_float); + + switch (input_format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + pixel_format = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + pixel_format = 3; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + pixel_format = 8; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + pixel_format = 10; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + force_disable_cursor = false; + pixel_format = 65; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + force_disable_cursor = true; + pixel_format = 64; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + force_disable_cursor = true; + pixel_format = 67; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + force_disable_cursor = true; + pixel_format = 66; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + pixel_format = 22; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + pixel_format = 24; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + pixel_format = 25; + break; + default: + break; + } + REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, + CNVC_SURFACE_PIXEL_FORMAT, pixel_format); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); + + ippn10_program_input_csc(xfm_base, color_space, select); + + if (force_disable_cursor) { + REG_UPDATE(CURSOR_CONTROL, + CURSOR_ENABLE, 0); + REG_UPDATE(CURSOR0_CONTROL, + CUR0_ENABLE, 0); + } +} + static struct transform_funcs dcn10_dpp_funcs = { .transform_reset = dpp_reset, .transform_set_scaler = dcn10_dpp_dscl_set_scaler_manual_scale, @@ -263,6 +408,11 @@ static struct transform_funcs dcn10_dpp_funcs = { .opp_program_regamma_luta_settings = dcn10_dpp_cm_program_regamma_luta_settings, .opp_program_regamma_pwl = dcn10_dpp_cm_set_regamma_pwl, .opp_set_regamma_mode = dcn10_dpp_cm_set_regamma_mode, + .ipp_set_degamma = ippn10_set_degamma, + .ipp_program_input_lut = ippn10_program_input_lut, + .ipp_program_degamma_pwl = ippn10_set_degamma_pwl, + .ipp_setup = ippn10_cnv_setup, + .ipp_full_bypass = ippn10_full_bypass, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 18ee338f6b28..9a678dcaa908 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -37,6 +37,10 @@ #define TF_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix +//Used to resolve corner case +#define TF2_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## _ ## field_name ## post_fix + #define TF_REG_LIST_DCN(id) \ SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\ SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\ @@ -72,7 +76,65 @@ SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ SRI(RECOUT_START, DSCL, id), \ SRI(RECOUT_SIZE, DSCL, id), \ - SRI(OBUF_CONTROL, DSCL, id) + SRI(OBUF_CONTROL, DSCL, id), \ + SRI(CM_ICSC_CONTROL, CM, id), \ + SRI(CM_ICSC_C11_C12, CM, id), \ + SRI(CM_ICSC_C13_C14, CM, id), \ + SRI(CM_ICSC_C21_C22, CM, id), \ + SRI(CM_ICSC_C23_C24, CM, id), \ + SRI(CM_ICSC_C31_C32, CM, id), \ + SRI(CM_ICSC_C33_C34, CM, id), \ + SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ + SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ + SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ + SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \ + SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \ + SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \ + SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \ + SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \ + SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \ + SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \ + SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \ + SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_2_3, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_4_5, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_6_7, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_8_9, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_10_11, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_12_13, CM, id), \ + SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \ + SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \ + SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \ + SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \ + SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \ + SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \ + SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \ + SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \ + SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \ + SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \ + SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \ + SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \ + SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_2_3, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_4_5, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_6_7, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_8_9, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_10_11, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \ + SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ + SRI(CM_MEM_PWR_CTRL, CM, id), \ + SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ + SRI(CM_DGAM_LUT_INDEX, CM, id), \ + SRI(CM_DGAM_LUT_DATA, CM, id), \ + SRI(CM_CONTROL, CM, id), \ + SRI(CM_DGAM_CONTROL, CM, id), \ + SRI(FORMAT_CONTROL, CNVC_CFG, id), \ + SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ + SRI(CURSOR0_CONTROL, CNVC_CUR, id) + + #define TF_REG_LIST_DCN10(id) \ TF_REG_LIST_DCN(id), \ @@ -157,7 +219,12 @@ SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \ SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \ SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ - SRI(CM_RGAM_CONTROL, CM, id) + SRI(CM_RGAM_CONTROL, CM, id), \ + SRI(CM_IGAM_CONTROL, CM, id), \ + SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ + SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ + SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ + SRI(CURSOR_CONTROL, CURSOR, id) #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ @@ -183,7 +250,7 @@ TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ - TF_SF(DSCL0_LB_DATA_FORMAT, ALPHA_EN, mask_sh),\ + TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\ TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ @@ -235,7 +302,133 @@ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ - TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh) + TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ + TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ + TF_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C13, mask_sh), \ + TF_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C14, mask_sh), \ + TF_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C21, mask_sh), \ + TF_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C22, mask_sh), \ + TF_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C23, mask_sh), \ + TF_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C24, mask_sh), \ + TF_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C31, mask_sh), \ + TF_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ + TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ + TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ + TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ + TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ + TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ + TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ + TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ + TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ + TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh) #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\ TF_REG_LIST_SH_MASK_DCN(mask_sh),\ @@ -459,8 +652,25 @@ TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ - TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh) - + TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ + TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ + TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ + TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ + TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ + TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ + TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ + TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \ + TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ + TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ + TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ + TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh) #define TF_REG_FIELD_LIST(type) \ type EXT_OVERSCAN_LEFT; \ @@ -477,7 +687,7 @@ type DYNAMIC_PIXEL_DEPTH; \ type DITHER_EN; \ type INTERLEAVE_EN; \ - type ALPHA_EN; \ + type LB_DATA_FORMAT__ALPHA_EN; \ type MEMORY_CONFIG; \ type LB_MAX_PARTITIONS; \ type AUTOCAL_MODE; \ @@ -1123,7 +1333,154 @@ type CM_SHAPER_LUT_WRITE_EN_MASK; \ type CM_SHAPER_LUT_WRITE_SEL; \ type CM_SHAPER_LUT_INDEX; \ - type CM_SHAPER_LUT_DATA + type CM_SHAPER_LUT_DATA; \ + type CM_DGAM_CONFIG_STATUS; \ + type CM_ICSC_MODE; \ + type CM_ICSC_C11; \ + type CM_ICSC_C12; \ + type CM_ICSC_C13; \ + type CM_ICSC_C14; \ + type CM_ICSC_C21; \ + type CM_ICSC_C22; \ + type CM_ICSC_C23; \ + type CM_ICSC_C24; \ + type CM_ICSC_C31; \ + type CM_ICSC_C32; \ + type CM_ICSC_C33; \ + type CM_ICSC_C34; \ + type CM_DGAM_RAMB_EXP_REGION_START_B; \ + type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ + type CM_DGAM_RAMB_EXP_REGION_START_G; \ + type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ + type CM_DGAM_RAMB_EXP_REGION_START_R; \ + type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ + type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ + type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ + type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ + type CM_DGAM_RAMB_EXP_REGION_END_B; \ + type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \ + type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \ + type CM_DGAM_RAMB_EXP_REGION_END_G; \ + type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \ + type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \ + type CM_DGAM_RAMB_EXP_REGION_END_R; \ + type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \ + type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \ + type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ + type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ + type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION_START_B; \ + type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ + type CM_DGAM_RAMA_EXP_REGION_START_G; \ + type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ + type CM_DGAM_RAMA_EXP_REGION_START_R; \ + type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ + type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ + type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ + type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ + type CM_DGAM_RAMA_EXP_REGION_END_B; \ + type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \ + type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \ + type CM_DGAM_RAMA_EXP_REGION_END_G; \ + type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \ + type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \ + type CM_DGAM_RAMA_EXP_REGION_END_R; \ + type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \ + type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \ + type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ + type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type SHARED_MEM_PWR_DIS; \ + type CM_IGAM_LUT_FORMAT_R; \ + type CM_IGAM_LUT_FORMAT_G; \ + type CM_IGAM_LUT_FORMAT_B; \ + type CM_IGAM_LUT_HOST_EN; \ + type CM_IGAM_LUT_RW_MODE; \ + type CM_IGAM_LUT_WRITE_EN_MASK; \ + type CM_IGAM_LUT_SEL; \ + type CM_IGAM_LUT_SEQ_COLOR; \ + type CM_IGAM_DGAM_CONFIG_STATUS; \ + type CM_DGAM_LUT_WRITE_EN_MASK; \ + type CM_DGAM_LUT_WRITE_SEL; \ + type CM_DGAM_LUT_INDEX; \ + type CM_DGAM_LUT_DATA; \ + type CM_DGAM_LUT_MODE; \ + type CM_IGAM_LUT_MODE; \ + type CM_IGAM_INPUT_FORMAT; \ + type CM_IGAM_LUT_RW_INDEX; \ + type CM_BYPASS_EN; \ + type FORMAT_EXPANSION_MODE; \ + type CNVC_BYPASS; \ + type OUTPUT_FP; \ + type CNVC_SURFACE_PIXEL_FORMAT; \ + type CURSOR_MODE; \ + type CURSOR_PITCH; \ + type CURSOR_LINES_PER_CHUNK; \ + type CURSOR_ENABLE; \ + type CUR0_MODE; \ + type CUR0_EXPANSION_MODE; \ + type CUR0_ENABLE; \ + type CM_BYPASS; \ + type FORMAT_CONTROL__ALPHA_EN + struct dcn_dpp_shift { @@ -1366,8 +1723,66 @@ struct dcn_dpp_registers { uint32_t CM_SHAPER_RAMA_REGION_32_33; uint32_t CM_SHAPER_LUT_INDEX; uint32_t CM_SHAPER_LUT_DATA; - - + uint32_t CM_ICSC_CONTROL; + uint32_t CM_ICSC_C11_C12; + uint32_t CM_ICSC_C13_C14; + uint32_t CM_ICSC_C21_C22; + uint32_t CM_ICSC_C23_C24; + uint32_t CM_ICSC_C31_C32; + uint32_t CM_ICSC_C33_C34; + uint32_t CM_DGAM_RAMB_START_CNTL_B; + uint32_t CM_DGAM_RAMB_START_CNTL_G; + uint32_t CM_DGAM_RAMB_START_CNTL_R; + uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; + uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; + uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; + uint32_t CM_DGAM_RAMB_END_CNTL1_B; + uint32_t CM_DGAM_RAMB_END_CNTL2_B; + uint32_t CM_DGAM_RAMB_END_CNTL1_G; + uint32_t CM_DGAM_RAMB_END_CNTL2_G; + uint32_t CM_DGAM_RAMB_END_CNTL1_R; + uint32_t CM_DGAM_RAMB_END_CNTL2_R; + uint32_t CM_DGAM_RAMB_REGION_0_1; + uint32_t CM_DGAM_RAMB_REGION_2_3; + uint32_t CM_DGAM_RAMB_REGION_4_5; + uint32_t CM_DGAM_RAMB_REGION_6_7; + uint32_t CM_DGAM_RAMB_REGION_8_9; + uint32_t CM_DGAM_RAMB_REGION_10_11; + uint32_t CM_DGAM_RAMB_REGION_12_13; + uint32_t CM_DGAM_RAMB_REGION_14_15; + uint32_t CM_DGAM_RAMA_START_CNTL_B; + uint32_t CM_DGAM_RAMA_START_CNTL_G; + uint32_t CM_DGAM_RAMA_START_CNTL_R; + uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; + uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; + uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; + uint32_t CM_DGAM_RAMA_END_CNTL1_B; + uint32_t CM_DGAM_RAMA_END_CNTL2_B; + uint32_t CM_DGAM_RAMA_END_CNTL1_G; + uint32_t CM_DGAM_RAMA_END_CNTL2_G; + uint32_t CM_DGAM_RAMA_END_CNTL1_R; + uint32_t CM_DGAM_RAMA_END_CNTL2_R; + uint32_t CM_DGAM_RAMA_REGION_0_1; + uint32_t CM_DGAM_RAMA_REGION_2_3; + uint32_t CM_DGAM_RAMA_REGION_4_5; + uint32_t CM_DGAM_RAMA_REGION_6_7; + uint32_t CM_DGAM_RAMA_REGION_8_9; + uint32_t CM_DGAM_RAMA_REGION_10_11; + uint32_t CM_DGAM_RAMA_REGION_12_13; + uint32_t CM_DGAM_RAMA_REGION_14_15; + uint32_t CM_DGAM_LUT_WRITE_EN_MASK; + uint32_t CM_DGAM_LUT_INDEX; + uint32_t CM_DGAM_LUT_DATA; + uint32_t CM_CONTROL; + uint32_t CM_DGAM_CONTROL; + uint32_t CM_IGAM_CONTROL; + uint32_t CM_IGAM_LUT_RW_CONTROL; + uint32_t CM_IGAM_LUT_RW_INDEX; + uint32_t CM_IGAM_LUT_SEQ_COLOR; + uint32_t FORMAT_CONTROL; + uint32_t CNVC_SURFACE_PIXEL_FORMAT; + uint32_t CURSOR_CONTROL; + uint32_t CURSOR0_CONTROL; }; struct dcn10_dpp { @@ -1387,6 +1802,52 @@ struct dcn10_dpp { bool is_write_to_ram_a_safe; }; +enum dcn10_input_csc_select { + INPUT_CSC_SELECT_BYPASS = 0, + INPUT_CSC_SELECT_ICSC, + INPUT_CSC_SELECT_COMA +}; + +void ippn10_degamma_ram_select( + struct transform *xfm_base, + bool use_ram_a); + +void ippn10_program_degamma_luta_settings( + struct transform *xfm_base, + const struct pwl_params *params); + +void ippn10_program_degamma_lutb_settings( + struct transform *xfm_base, + const struct pwl_params *params); + +void ippn10_program_degamma_lut( + struct transform *xfm_base, + const struct pwl_result_data *rgb, + uint32_t num, + bool is_ram_a); + +void ippn10_power_on_degamma_lut( + struct transform *xfm_base, + bool power_on); + +void ippn10_program_input_csc( + struct transform *xfm_base, + enum dc_color_space color_space, + enum dcn10_input_csc_select select); + +void ippn10_program_input_lut( + struct transform *xfm_base, + const struct dc_gamma *gamma); + +void ippn10_full_bypass(struct transform *xfm_base); + +void ippn10_set_degamma( + struct transform *xfm_base, + enum ipp_degamma_mode mode); + +void ippn10_set_degamma_pwl(struct transform *xfm_base, + const struct pwl_params *params); + bool dpp_get_optimal_number_of_taps( struct transform *xfm, struct scaler_data *scl_data, @@ -1432,6 +1893,14 @@ void dcn10_dpp_dscl_set_scaler_manual_scale( struct transform *xfm_base, const struct scaler_data *scl_data); +void ippn10_cnv_setup ( + struct transform *xfm_base, + enum surface_pixel_format input_format, + enum expansion_mode mode, + enum ipp_output_format cnv_out_format); + +void ippn10_full_bypass(struct transform *xfm_base); + bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, struct dc_context *ctx, uint32_t inst, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 9ff283bff007..409462f29f54 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -52,6 +52,11 @@ #define FN(reg_name, field_name) \ xfm->tf_shift->field_name, xfm->tf_mask->field_name +struct dcn10_input_csc_matrix { + enum dc_color_space color_space; + uint32_t regval[12]; +}; + enum dcn10_coef_filter_type_sel { SCL_COEF_LUMA_VERT_FILTER = 0, SCL_COEF_LUMA_HORZ_FILTER = 1, @@ -111,6 +116,26 @@ enum gamut_remap_select { GAMUT_REMAP_COMB_COEFF }; +static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = { + {COLOR_SPACE_SRGB, + {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + {COLOR_SPACE_SRGB_LIMITED, + {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + {COLOR_SPACE_YCBCR601, + {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef, + 0, 0x2000, 0x38b4, 0xe3a6} }, + {COLOR_SPACE_YCBCR601_LIMITED, + {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108, + 0, 0x2568, 0x40de, 0xdd3a} }, + {COLOR_SPACE_YCBCR709, + {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0, + 0x2000, 0x3b61, 0xe24f} }, + + {COLOR_SPACE_YCBCR709_LIMITED, + {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0, + 0x2568, 0x43ee, 0xdbb2} } +}; + static void program_gamut_remap( struct dcn10_dpp *xfm, const uint16_t *regval, @@ -774,3 +799,533 @@ void dcn10_dpp_cm_program_regamma_lutb_settings( CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); } + +void ippn10_program_input_csc( + struct transform *xfm_base, + enum dc_color_space color_space, + enum dcn10_input_csc_select select) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + int i; + int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix); + const uint32_t *regval = NULL; + uint32_t selection = 1; + + if (select == INPUT_CSC_SELECT_BYPASS) { + REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); + return; + } + + for (i = 0; i < arr_size; i++) + if (dcn10_input_csc_matrix[i].color_space == color_space) { + regval = dcn10_input_csc_matrix[i].regval; + break; + } + + if (regval == NULL) { + BREAK_TO_DEBUGGER(); + return; + } + + if (select == INPUT_CSC_SELECT_COMA) + selection = 2; + REG_SET(CM_ICSC_CONTROL, 0, + CM_ICSC_MODE, selection); + + if (select == INPUT_CSC_SELECT_ICSC) { + /*R*/ + REG_SET_2(CM_ICSC_C11_C12, 0, + CM_ICSC_C11, regval[0], + CM_ICSC_C12, regval[1]); + regval += 2; + REG_SET_2(CM_ICSC_C13_C14, 0, + CM_ICSC_C13, regval[0], + CM_ICSC_C14, regval[1]); + /*G*/ + regval += 2; + REG_SET_2(CM_ICSC_C21_C22, 0, + CM_ICSC_C21, regval[0], + CM_ICSC_C22, regval[1]); + regval += 2; + REG_SET_2(CM_ICSC_C23_C24, 0, + CM_ICSC_C23, regval[0], + CM_ICSC_C24, regval[1]); + /*B*/ + regval += 2; + REG_SET_2(CM_ICSC_C31_C32, 0, + CM_ICSC_C31, regval[0], + CM_ICSC_C32, regval[1]); + regval += 2; + REG_SET_2(CM_ICSC_C33_C34, 0, + CM_ICSC_C33, regval[0], + CM_ICSC_C34, regval[1]); + } else { + /*R*/ + REG_SET_2(CM_COMA_C11_C12, 0, + CM_COMA_C11, regval[0], + CM_COMA_C12, regval[1]); + regval += 2; + REG_SET_2(CM_COMA_C13_C14, 0, + CM_COMA_C13, regval[0], + CM_COMA_C14, regval[1]); + /*G*/ + regval += 2; + REG_SET_2(CM_COMA_C21_C22, 0, + CM_COMA_C21, regval[0], + CM_COMA_C22, regval[1]); + regval += 2; + REG_SET_2(CM_COMA_C23_C24, 0, + CM_COMA_C23, regval[0], + CM_COMA_C24, regval[1]); + /*B*/ + regval += 2; + REG_SET_2(CM_COMA_C31_C32, 0, + CM_COMA_C31, regval[0], + CM_COMA_C32, regval[1]); + regval += 2; + REG_SET_2(CM_COMA_C33_C34, 0, + CM_COMA_C33, regval[0], + CM_COMA_C34, regval[1]); + } +} + +/*program de gamma RAM B*/ +void ippn10_program_degamma_lutb_settings( + struct transform *xfm_base, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_SET_2(CM_DGAM_RAMB_START_CNTL_B, 0, + CM_DGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x, + CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(CM_DGAM_RAMB_START_CNTL_G, 0, + CM_DGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x, + CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0); + + REG_SET_2(CM_DGAM_RAMB_START_CNTL_R, 0, + CM_DGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x, + CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0); + + REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_B, 0, + CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); + + REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_G, 0, + CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); + + REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_R, 0, + CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); + + REG_SET(CM_DGAM_RAMB_END_CNTL1_B, 0, + CM_DGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x); + + REG_SET_2(CM_DGAM_RAMB_END_CNTL2_B, 0, + CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y, + CM_DGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope); + + REG_SET(CM_DGAM_RAMB_END_CNTL1_G, 0, + CM_DGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x); + + REG_SET_2(CM_DGAM_RAMB_END_CNTL2_G, 0, + CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y, + CM_DGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope); + + REG_SET(CM_DGAM_RAMB_END_CNTL1_R, 0, + CM_DGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x); + + REG_SET_2(CM_DGAM_RAMB_END_CNTL2_R, 0, + CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y, + CM_DGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope); + + curve = params->arr_curve_points; + REG_SET_4(CM_DGAM_RAMB_REGION_0_1, 0, + CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_2_3, 0, + CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_4_5, 0, + CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_6_7, 0, + CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_8_9, 0, + CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_10_11, 0, + CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_12_13, 0, + CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMB_REGION_14_15, 0, + CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); +} + +/*program de gamma RAM A*/ +void ippn10_program_degamma_luta_settings( + struct transform *xfm_base, + const struct pwl_params *params) +{ + const struct gamma_curve *curve; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_SET_2(CM_DGAM_RAMA_START_CNTL_B, 0, + CM_DGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x, + CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(CM_DGAM_RAMA_START_CNTL_G, 0, + CM_DGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x, + CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0); + + REG_SET_2(CM_DGAM_RAMA_START_CNTL_R, 0, + CM_DGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x, + CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0); + + REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_B, 0, + CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); + + REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_G, 0, + CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); + + REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_R, 0, + CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); + + REG_SET(CM_DGAM_RAMA_END_CNTL1_B, 0, + CM_DGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x); + + REG_SET_2(CM_DGAM_RAMA_END_CNTL2_B, 0, + CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y, + CM_DGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope); + + REG_SET(CM_DGAM_RAMA_END_CNTL1_G, 0, + CM_DGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x); + + REG_SET_2(CM_DGAM_RAMA_END_CNTL2_G, 0, + CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y, + CM_DGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope); + + REG_SET(CM_DGAM_RAMA_END_CNTL1_R, 0, + CM_DGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x); + + REG_SET_2(CM_DGAM_RAMA_END_CNTL2_R, 0, + CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y, + CM_DGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope); + + curve = params->arr_curve_points; + REG_SET_4(CM_DGAM_RAMA_REGION_0_1, 0, + CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_2_3, 0, + CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_4_5, 0, + CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_6_7, 0, + CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_8_9, 0, + CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_10_11, 0, + CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_12_13, 0, + CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(CM_DGAM_RAMA_REGION_14_15, 0, + CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, + CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, + CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, + CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); +} + +void ippn10_power_on_degamma_lut( + struct transform *xfm_base, + bool power_on) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_SET(CM_MEM_PWR_CTRL, 0, + SHARED_MEM_PWR_DIS, power_on == true ? 0:1); + +} + +static void ippn10_enable_cm_block( + struct transform *xfm_base) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); +} + +void ippn10_set_degamma( + struct transform *xfm_base, + enum ipp_degamma_mode mode) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + ippn10_enable_cm_block(xfm_base); + + switch (mode) { + case IPP_DEGAMMA_MODE_BYPASS: + /* Setting de gamma bypass for now */ + REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); + break; + case IPP_DEGAMMA_MODE_HW_sRGB: + REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); + break; + case IPP_DEGAMMA_MODE_HW_xvYCC: + REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } +} + +void ippn10_degamma_ram_select( + struct transform *xfm_base, + bool use_ram_a) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + if (use_ram_a) + REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); + else + REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4); + +} + +static bool ippn10_degamma_ram_inuse( + struct transform *xfm_base, + bool *ram_a_inuse) +{ + bool ret = false; + uint32_t status_reg = 0; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, + &status_reg); + + if (status_reg == 9) { + *ram_a_inuse = true; + ret = true; + } else if (status_reg == 10) { + *ram_a_inuse = false; + ret = true; + } + return ret; +} + +void ippn10_program_degamma_lut( + struct transform *xfm_base, + const struct pwl_result_data *rgb, + uint32_t num, + bool is_ram_a) +{ + uint32_t i; + + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0); + REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, + CM_DGAM_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, + is_ram_a == true ? 0:1); + + REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); + for (i = 0 ; i < num; i++) { + REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); + REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); + REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); + + REG_SET(CM_DGAM_LUT_DATA, 0, + CM_DGAM_LUT_DATA, rgb[i].delta_red_reg); + REG_SET(CM_DGAM_LUT_DATA, 0, + CM_DGAM_LUT_DATA, rgb[i].delta_green_reg); + REG_SET(CM_DGAM_LUT_DATA, 0, + CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg); + } +} + +void ippn10_set_degamma_pwl(struct transform *xfm_base, + const struct pwl_params *params) +{ + bool is_ram_a = true; + + ippn10_power_on_degamma_lut(xfm_base, true); + ippn10_enable_cm_block(xfm_base); + ippn10_degamma_ram_inuse(xfm_base, &is_ram_a); + if (is_ram_a == true) + ippn10_program_degamma_lutb_settings(xfm_base, params); + else + ippn10_program_degamma_luta_settings(xfm_base, params); + + ippn10_program_degamma_lut(xfm_base, params->rgb_resulted, + params->hw_points_num, !is_ram_a); + ippn10_degamma_ram_select(xfm_base, !is_ram_a); +} + +void ippn10_full_bypass(struct transform *xfm_base) +{ + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + /* Input pixel format: ARGB8888 */ + REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, + CNVC_SURFACE_PIXEL_FORMAT, 0x8); + + /* Zero expansion */ + REG_SET_3(FORMAT_CONTROL, 0, + CNVC_BYPASS, 0, + FORMAT_CONTROL__ALPHA_EN, 0, + FORMAT_EXPANSION_MODE, 0); + + /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ + REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); + + /* Setting degamma bypass for now */ + REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); + REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0); +} + +static bool ippn10_ingamma_ram_inuse(struct transform *xfm_base, + bool *ram_a_inuse) +{ + bool in_use = false; + uint32_t status_reg = 0; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + + REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, + &status_reg); + + // 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB + if (status_reg == 1 || status_reg == 3 || status_reg == 4) { + *ram_a_inuse = true; + in_use = true; + // 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB + } else if (status_reg == 2 || status_reg == 5 || status_reg == 6) { + *ram_a_inuse = false; + in_use = true; + } + return in_use; +} + +/* + * Input gamma LUT currently supports 256 values only. This means input color + * can have a maximum of 8 bits per channel (= 256 possible values) in order to + * have a one-to-one mapping with the LUT. Truncation will occur with color + * values greater than 8 bits. + * + * In the future, this function should support additional input gamma methods, + * such as piecewise linear mapping, and input gamma bypass. + */ +void ippn10_program_input_lut( + struct transform *xfm_base, + const struct dc_gamma *gamma) +{ + int i; + struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); + bool rama_occupied = false; + uint32_t ram_num; + // Power on LUT memory. + REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1); + ippn10_enable_cm_block(xfm_base); + // Determine whether to use RAM A or RAM B + ippn10_ingamma_ram_inuse(xfm_base, &rama_occupied); + if (!rama_occupied) + REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0); + else + REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1); + // RW mode is 256-entry LUT + REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0); + // IGAM Input format should be 8 bits per channel. + REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0); + // Do not mask any R,G,B values + REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7); + // LUT-256, unsigned, integer, new u0.12 format + REG_UPDATE_3( + CM_IGAM_CONTROL, + CM_IGAM_LUT_FORMAT_R, 3, + CM_IGAM_LUT_FORMAT_G, 3, + CM_IGAM_LUT_FORMAT_B, 3); + // Start at index 0 of IGAM LUT + REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0); + for (i = 0; i < gamma->num_entries; i++) { + REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, + dal_fixed31_32_round( + gamma->entries.red[i])); + REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, + dal_fixed31_32_round( + gamma->entries.green[i])); + REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, + dal_fixed31_32_round( + gamma->entries.blue[i])); + } + // Power off LUT memory + REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0); + // Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB + REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2); + REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index 33830639e210..14c3b330b27b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -225,7 +225,7 @@ static void dpp_set_lb( DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */ DITHER_EN, 0, /* Dithering enable: Disabled */ INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ - ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ } REG_SET_2(LB_MEMORY_CTRL, 0, @@ -716,4 +716,3 @@ void dcn10_dpp_dscl_set_scaler_manual_scale( dpp_set_scl_filter(xfm, scl_data, ycbcr); } - diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 498680a9b996..4a24893486e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1294,34 +1294,34 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c static bool dcn10_set_input_transfer_func( struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { - struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; + struct transform *xfm_base = pipe_ctx->plane_res.xfm; const struct dc_transfer_func *tf = NULL; bool result = true; - if (ipp == NULL) + if (xfm_base == NULL) return false; if (plane_state->in_transfer_func) tf = plane_state->in_transfer_func; if (plane_state->gamma_correction && dce_use_lut(plane_state)) - ipp->funcs->ipp_program_input_lut(ipp, + xfm_base->funcs->ipp_program_input_lut(xfm_base, plane_state->gamma_correction); if (tf == NULL) - ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); + xfm_base->funcs->ipp_set_degamma(xfm_base, IPP_DEGAMMA_MODE_BYPASS); else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - ipp->funcs->ipp_set_degamma(ipp, + xfm_base->funcs->ipp_set_degamma(xfm_base, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - ipp->funcs->ipp_set_degamma(ipp, + xfm_base->funcs->ipp_set_degamma(xfm_base, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - ipp->funcs->ipp_set_degamma(ipp, + xfm_base->funcs->ipp_set_degamma(xfm_base, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: @@ -1332,7 +1332,7 @@ static bool dcn10_set_input_transfer_func( break; } } else if (tf->type == TF_TYPE_BYPASS) { - ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); + xfm_base->funcs->ipp_set_degamma(xfm_base, IPP_DEGAMMA_MODE_BYPASS); } else { /*TF_TYPE_DISTRIBUTED_POINTS*/ result = false; @@ -2204,7 +2204,7 @@ static void update_dchubp_dpp( { struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->plane_res.mi; - struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; + struct transform *xfm = pipe_ctx->plane_res.xfm; struct dc_plane_state *plane_state = pipe_ctx->plane_state; union plane_size size = plane_state->plane_size; struct default_adjustment ocsc = {0}; @@ -2249,7 +2249,7 @@ static void update_dchubp_dpp( hws ); - ipp->funcs->ipp_setup(ipp, + xfm->funcs->ipp_setup(xfm, plane_state->format, 1, IPP_OUTPUT_FORMAT_12_BIT_FIX); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 8ee830522148..bc9827967535 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -69,403 +69,7 @@ enum dcn10_input_csc_select { INPUT_CSC_SELECT_COMA }; -static void ippn10_program_input_csc( - struct input_pixel_processor *ipp, - enum dc_color_space color_space, - enum dcn10_input_csc_select select) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - int i; - int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix); - const uint32_t *regval = NULL; - uint32_t selection = 1; - - if (select == INPUT_CSC_SELECT_BYPASS) { - REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); - return; - } - - for (i = 0; i < arr_size; i++) - if (dcn10_input_csc_matrix[i].color_space == color_space) { - regval = dcn10_input_csc_matrix[i].regval; - break; - } - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; - } - - if (select == INPUT_CSC_SELECT_COMA) - selection = 2; - REG_SET(CM_ICSC_CONTROL, 0, - CM_ICSC_MODE, selection); - - if (select == INPUT_CSC_SELECT_ICSC) { - /*R*/ - REG_SET_2(CM_ICSC_C11_C12, 0, - CM_ICSC_C11, regval[0], - CM_ICSC_C12, regval[1]); - regval += 2; - REG_SET_2(CM_ICSC_C13_C14, 0, - CM_ICSC_C13, regval[0], - CM_ICSC_C14, regval[1]); - /*G*/ - regval += 2; - REG_SET_2(CM_ICSC_C21_C22, 0, - CM_ICSC_C21, regval[0], - CM_ICSC_C22, regval[1]); - regval += 2; - REG_SET_2(CM_ICSC_C23_C24, 0, - CM_ICSC_C23, regval[0], - CM_ICSC_C24, regval[1]); - /*B*/ - regval += 2; - REG_SET_2(CM_ICSC_C31_C32, 0, - CM_ICSC_C31, regval[0], - CM_ICSC_C32, regval[1]); - regval += 2; - REG_SET_2(CM_ICSC_C33_C34, 0, - CM_ICSC_C33, regval[0], - CM_ICSC_C34, regval[1]); - } else { - /*R*/ - REG_SET_2(CM_COMA_C11_C12, 0, - CM_COMA_C11, regval[0], - CM_COMA_C12, regval[1]); - regval += 2; - REG_SET_2(CM_COMA_C13_C14, 0, - CM_COMA_C13, regval[0], - CM_COMA_C14, regval[1]); - /*G*/ - regval += 2; - REG_SET_2(CM_COMA_C21_C22, 0, - CM_COMA_C21, regval[0], - CM_COMA_C22, regval[1]); - regval += 2; - REG_SET_2(CM_COMA_C23_C24, 0, - CM_COMA_C23, regval[0], - CM_COMA_C24, regval[1]); - /*B*/ - regval += 2; - REG_SET_2(CM_COMA_C31_C32, 0, - CM_COMA_C31, regval[0], - CM_COMA_C32, regval[1]); - regval += 2; - REG_SET_2(CM_COMA_C33_C34, 0, - CM_COMA_C33, regval[0], - CM_COMA_C34, regval[1]); - } -} - -/*program de gamma RAM B*/ -static void ippn10_program_degamma_lutb_settings( - struct input_pixel_processor *ipp, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - REG_SET_2(CM_DGAM_RAMB_START_CNTL_B, 0, - CM_DGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x, - CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0); - - REG_SET_2(CM_DGAM_RAMB_START_CNTL_G, 0, - CM_DGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x, - CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0); - - REG_SET_2(CM_DGAM_RAMB_START_CNTL_R, 0, - CM_DGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x, - CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_B, 0, - CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); - - REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_G, 0, - CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); - - REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_R, 0, - CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); - - REG_SET(CM_DGAM_RAMB_END_CNTL1_B, 0, - CM_DGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x); - - REG_SET_2(CM_DGAM_RAMB_END_CNTL2_B, 0, - CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y, - CM_DGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope); - - REG_SET(CM_DGAM_RAMB_END_CNTL1_G, 0, - CM_DGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x); - - REG_SET_2(CM_DGAM_RAMB_END_CNTL2_G, 0, - CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y, - CM_DGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope); - - REG_SET(CM_DGAM_RAMB_END_CNTL1_R, 0, - CM_DGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x); - - REG_SET_2(CM_DGAM_RAMB_END_CNTL2_R, 0, - CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y, - CM_DGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope); - - curve = params->arr_curve_points; - REG_SET_4(CM_DGAM_RAMB_REGION_0_1, 0, - CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_2_3, 0, - CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_4_5, 0, - CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_6_7, 0, - CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_8_9, 0, - CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_10_11, 0, - CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_12_13, 0, - CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMB_REGION_14_15, 0, - CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); -} - -/*program de gamma RAM A*/ -static void ippn10_program_degamma_luta_settings( - struct input_pixel_processor *ipp, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - REG_SET_2(CM_DGAM_RAMA_START_CNTL_B, 0, - CM_DGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x, - CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0); - - REG_SET_2(CM_DGAM_RAMA_START_CNTL_G, 0, - CM_DGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x, - CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0); - - REG_SET_2(CM_DGAM_RAMA_START_CNTL_R, 0, - CM_DGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x, - CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_B, 0, - CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); - - REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_G, 0, - CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); - - REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_R, 0, - CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); - - REG_SET(CM_DGAM_RAMA_END_CNTL1_B, 0, - CM_DGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x); - - REG_SET_2(CM_DGAM_RAMA_END_CNTL2_B, 0, - CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y, - CM_DGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope); - - REG_SET(CM_DGAM_RAMA_END_CNTL1_G, 0, - CM_DGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x); - - REG_SET_2(CM_DGAM_RAMA_END_CNTL2_G, 0, - CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y, - CM_DGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope); - - REG_SET(CM_DGAM_RAMA_END_CNTL1_R, 0, - CM_DGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x); - - REG_SET_2(CM_DGAM_RAMA_END_CNTL2_R, 0, - CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y, - CM_DGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope); - - curve = params->arr_curve_points; - REG_SET_4(CM_DGAM_RAMA_REGION_0_1, 0, - CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_2_3, 0, - CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_4_5, 0, - CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_6_7, 0, - CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_8_9, 0, - CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_10_11, 0, - CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_12_13, 0, - CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_DGAM_RAMA_REGION_14_15, 0, - CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); -} - -static void ippn10_power_on_degamma_lut( - struct input_pixel_processor *ipp, - bool power_on) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - REG_SET(CM_MEM_PWR_CTRL, 0, - SHARED_MEM_PWR_DIS, power_on == true ? 0:1); -} - -static void ippn10_program_degamma_lut( - struct input_pixel_processor *ipp, - const struct pwl_result_data *rgb, - uint32_t num, - bool is_ram_a) -{ - uint32_t i; - - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0); - REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, - CM_DGAM_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, - is_ram_a == true ? 0:1); - - REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); - for (i = 0 ; i < num; i++) { - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg); - } -} - -static void ippn10_enable_cm_block( - struct input_pixel_processor *ipp) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); -} - -static void ippn10_full_bypass(struct input_pixel_processor *ipp) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - /* Input pixel format: ARGB8888 */ - REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, - CNVC_SURFACE_PIXEL_FORMAT, 0x8); - - /* Zero expansion */ - REG_SET_3(FORMAT_CONTROL, 0, - CNVC_BYPASS, 0, - ALPHA_EN, 0, - FORMAT_EXPANSION_MODE, 0); - - /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ - REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); - - /* Setting degamma bypass for now */ - REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); - REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0); -} - -static void ippn10_set_degamma( - struct input_pixel_processor *ipp, - enum ipp_degamma_mode mode) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - ippn10_enable_cm_block(ipp); - - switch (mode) { - case IPP_DEGAMMA_MODE_BYPASS: - /* Setting de gamma bypass for now */ - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); - break; - case IPP_DEGAMMA_MODE_HW_sRGB: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); - break; - case IPP_DEGAMMA_MODE_HW_xvYCC: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } -} static bool ippn10_cursor_program_control( struct dcn10_ipp *ippn10, @@ -658,276 +262,6 @@ enum pixel_format_description { }; -static void ippn10_setup_format_flags(enum surface_pixel_format input_format,\ - enum pixel_format_description *fmt) -{ - - if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || - input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) - *fmt = PIXEL_FORMAT_FLOAT; - else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) - *fmt = PIXEL_FORMAT_FIXED16; - else - *fmt = PIXEL_FORMAT_FIXED; -} - -static void ippn10_set_degamma_format_float(struct input_pixel_processor *ipp, - bool is_float) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - if (is_float) { - REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); - REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); - } else { - REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); - REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); - } -} - - -static void ippn10_cnv_setup ( - struct input_pixel_processor *ipp, - enum surface_pixel_format input_format, - enum expansion_mode mode, - enum ipp_output_format cnv_out_format) -{ - uint32_t pixel_format; - uint32_t alpha_en; - enum pixel_format_description fmt ; - enum dc_color_space color_space; - enum dcn10_input_csc_select select; - bool is_float; - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - bool force_disable_cursor = false; - - ippn10_setup_format_flags(input_format, &fmt); - alpha_en = 1; - pixel_format = 0; - color_space = COLOR_SPACE_SRGB; - select = INPUT_CSC_SELECT_BYPASS; - is_float = false; - - switch (fmt) { - case PIXEL_FORMAT_FIXED: - case PIXEL_FORMAT_FIXED16: - /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ - REG_SET_3(FORMAT_CONTROL, 0, - CNVC_BYPASS, 0, - FORMAT_EXPANSION_MODE, mode, - OUTPUT_FP, 0); - break; - case PIXEL_FORMAT_FLOAT: - REG_SET_3(FORMAT_CONTROL, 0, - CNVC_BYPASS, 0, - FORMAT_EXPANSION_MODE, mode, - OUTPUT_FP, 1); - is_float = true; - break; - default: - - break; - } - - ippn10_set_degamma_format_float(ipp, is_float); - - switch (input_format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - pixel_format = 1; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - pixel_format = 3; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - pixel_format = 8; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - pixel_format = 10; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - force_disable_cursor = false; - pixel_format = 65; - color_space = COLOR_SPACE_YCBCR709; - select = INPUT_CSC_SELECT_ICSC; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - force_disable_cursor = true; - pixel_format = 64; - color_space = COLOR_SPACE_YCBCR709; - select = INPUT_CSC_SELECT_ICSC; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - force_disable_cursor = true; - pixel_format = 67; - color_space = COLOR_SPACE_YCBCR709; - select = INPUT_CSC_SELECT_ICSC; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - force_disable_cursor = true; - pixel_format = 66; - color_space = COLOR_SPACE_YCBCR709; - select = INPUT_CSC_SELECT_ICSC; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - pixel_format = 22; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - pixel_format = 24; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: - pixel_format = 25; - break; - default: - break; - } - REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, - CNVC_SURFACE_PIXEL_FORMAT, pixel_format); - REG_UPDATE(FORMAT_CONTROL, ALPHA_EN, alpha_en); - - ippn10_program_input_csc(ipp, color_space, select); - - if (force_disable_cursor) { - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, 0); - REG_UPDATE(CURSOR0_CONTROL, - CUR0_ENABLE, 0); - } -} - - -static bool ippn10_degamma_ram_inuse(struct input_pixel_processor *ipp, - bool *ram_a_inuse) -{ - bool ret = false; - uint32_t status_reg = 0; - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, - &status_reg); - - if (status_reg == 9) { - *ram_a_inuse = true; - ret = true; - } else if (status_reg == 10) { - *ram_a_inuse = false; - ret = true; - } - return ret; -} - -static bool ippn10_ingamma_ram_inuse(struct input_pixel_processor *ipp, - bool *ram_a_inuse) -{ - bool in_use = false; - uint32_t status_reg = 0; - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, - &status_reg); - - // 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB - if (status_reg == 1 || status_reg == 3 || status_reg == 4) { - *ram_a_inuse = true; - in_use = true; - // 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB - } else if (status_reg == 2 || status_reg == 5 || status_reg == 6) { - *ram_a_inuse = false; - in_use = true; - } - return in_use; -} - -static void ippn10_degamma_ram_select(struct input_pixel_processor *ipp, - bool use_ram_a) -{ - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - - if (use_ram_a) - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); - else - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4); - -} - -static void ippn10_set_degamma_pwl(struct input_pixel_processor *ipp, - const struct pwl_params *params) -{ - bool is_ram_a = true; - - ippn10_power_on_degamma_lut(ipp, true); - ippn10_enable_cm_block(ipp); - ippn10_degamma_ram_inuse(ipp, &is_ram_a); - if (is_ram_a == true) - ippn10_program_degamma_lutb_settings(ipp, params); - else - ippn10_program_degamma_luta_settings(ipp, params); - - ippn10_program_degamma_lut(ipp, params->rgb_resulted, - params->hw_points_num, !is_ram_a); - ippn10_degamma_ram_select(ipp, !is_ram_a); -} - -/* - * Input gamma LUT currently supports 256 values only. This means input color - * can have a maximum of 8 bits per channel (= 256 possible values) in order to - * have a one-to-one mapping with the LUT. Truncation will occur with color - * values greater than 8 bits. - * - * In the future, this function should support additional input gamma methods, - * such as piecewise linear mapping, and input gamma bypass. - */ -static void ippn10_program_input_lut( - struct input_pixel_processor *ipp, - const struct dc_gamma *gamma) -{ - int i; - struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp); - bool rama_occupied = false; - uint32_t ram_num; - // Power on LUT memory. - REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1); - ippn10_enable_cm_block(ipp); - // Determine whether to use RAM A or RAM B - ippn10_ingamma_ram_inuse(ipp, &rama_occupied); - if (!rama_occupied) - REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0); - else - REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1); - // RW mode is 256-entry LUT - REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0); - // IGAM Input format should be 8 bits per channel. - REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0); - // Do not mask any R,G,B values - REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7); - // LUT-256, unsigned, integer, new u0.12 format - REG_UPDATE_3( - CM_IGAM_CONTROL, - CM_IGAM_LUT_FORMAT_R, 3, - CM_IGAM_LUT_FORMAT_G, 3, - CM_IGAM_LUT_FORMAT_B, 3); - // Start at index 0 of IGAM LUT - REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0); - for (i = 0; i < gamma->num_entries; i++) { - REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - dal_fixed31_32_round( - gamma->entries.red[i])); - REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - dal_fixed31_32_round( - gamma->entries.green[i])); - REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - dal_fixed31_32_round( - gamma->entries.blue[i])); - } - // Power off LUT memory - REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0); - // Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB - REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2); - REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); -} - /*****************************************/ /* Constructor, Destructor */ /*****************************************/ @@ -941,11 +275,11 @@ static void dcn10_ipp_destroy(struct input_pixel_processor **ipp) static const struct ipp_funcs dcn10_ipp_funcs = { .ipp_cursor_set_attributes = ippn10_cursor_set_attributes, .ipp_cursor_set_position = ippn10_cursor_set_position, - .ipp_set_degamma = ippn10_set_degamma, - .ipp_program_input_lut = ippn10_program_input_lut, - .ipp_full_bypass = ippn10_full_bypass, - .ipp_setup = ippn10_cnv_setup, - .ipp_program_degamma_pwl = ippn10_set_degamma_pwl, + .ipp_set_degamma = NULL, + .ipp_program_input_lut = NULL, + .ipp_full_bypass = NULL, + .ipp_setup = NULL, + .ipp_program_degamma_pwl = NULL, .ipp_destroy = dcn10_ipp_destroy }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index 69db441e78c4..e4f292822975 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -32,59 +32,6 @@ container_of(ipp, struct dcn10_ipp, base) #define IPP_REG_LIST_DCN(id) \ - SRI(CM_ICSC_CONTROL, CM, id), \ - SRI(CM_ICSC_C11_C12, CM, id), \ - SRI(CM_ICSC_C13_C14, CM, id), \ - SRI(CM_ICSC_C21_C22, CM, id), \ - SRI(CM_ICSC_C23_C24, CM, id), \ - SRI(CM_ICSC_C31_C32, CM, id), \ - SRI(CM_ICSC_C33_C34, CM, id), \ - SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ - SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ - SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ - SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \ - SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \ - SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \ - SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \ - SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \ - SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \ - SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \ - SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \ - SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_2_3, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_4_5, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_6_7, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_8_9, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_10_11, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_12_13, CM, id), \ - SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \ - SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \ - SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \ - SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \ - SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \ - SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \ - SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \ - SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \ - SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \ - SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \ - SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \ - SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \ - SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_2_3, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_4_5, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_6_7, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_8_9, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_10_11, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \ - SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ - SRI(CM_MEM_PWR_CTRL, CM, id), \ - SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ - SRI(CM_DGAM_LUT_INDEX, CM, id), \ - SRI(CM_DGAM_LUT_DATA, CM, id), \ - SRI(CM_CONTROL, CM, id), \ - SRI(CM_DGAM_CONTROL, CM, id), \ SRI(FORMAT_CONTROL, CNVC_CFG, id), \ SRI(DPP_CONTROL, DPP_TOP, id), \ SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ @@ -95,16 +42,6 @@ #define IPP_REG_LIST_DCN10(id) \ IPP_REG_LIST_DCN(id), \ SRI(CURSOR_SETTINS, HUBPREQ, id), \ - SRI(CM_IGAM_CONTROL, CM, id), \ - SRI(CM_COMA_C11_C12, CM, id), \ - SRI(CM_COMA_C13_C14, CM, id), \ - SRI(CM_COMA_C21_C22, CM, id), \ - SRI(CM_COMA_C23_C24, CM, id), \ - SRI(CM_COMA_C31_C32, CM, id), \ - SRI(CM_COMA_C33_C34, CM, id), \ - SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ - SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ - SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ SRI(CURSOR_SIZE, CURSOR, id), \ @@ -117,129 +54,10 @@ .field_name = reg_name ## __ ## field_name ## post_fix #define IPP_MASK_SH_LIST_DCN(mask_sh) \ - IPP_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C13, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C14, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C21, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C22, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C23, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C24, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C31, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ - IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ - IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ - IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ - IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ - IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ - IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ @@ -250,26 +68,6 @@ IPP_MASK_SH_LIST_DCN(mask_sh),\ IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ - IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \ - IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \ - IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \ - IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh), \ - IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh), \ - IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh), \ - IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh), \ - IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh), \ - IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh), \ - IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh), \ - IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh), \ - IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ - IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ - IPP_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ @@ -283,163 +81,13 @@ IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ - IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ - IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ - IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ - IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ - IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh) #define IPP_DCN10_REG_FIELD_LIST(type) \ - type CM_DGAM_CONFIG_STATUS; \ - type CM_ICSC_MODE; \ - type CM_ICSC_C11; \ - type CM_ICSC_C12; \ - type CM_ICSC_C13; \ - type CM_ICSC_C14; \ - type CM_ICSC_C21; \ - type CM_ICSC_C22; \ - type CM_ICSC_C23; \ - type CM_ICSC_C24; \ - type CM_ICSC_C31; \ - type CM_ICSC_C32; \ - type CM_ICSC_C33; \ - type CM_ICSC_C34; \ - type CM_COMA_C11; \ - type CM_COMA_C12; \ - type CM_COMA_C13; \ - type CM_COMA_C14; \ - type CM_COMA_C21; \ - type CM_COMA_C22; \ - type CM_COMA_C23; \ - type CM_COMA_C24; \ - type CM_COMA_C31; \ - type CM_COMA_C32; \ - type CM_COMA_C33; \ - type CM_COMA_C34; \ - type CM_DGAM_RAMB_EXP_REGION_START_B; \ - type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ - type CM_DGAM_RAMB_EXP_REGION_START_G; \ - type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ - type CM_DGAM_RAMB_EXP_REGION_START_R; \ - type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ - type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ - type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ - type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ - type CM_DGAM_RAMB_EXP_REGION_END_B; \ - type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \ - type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \ - type CM_DGAM_RAMB_EXP_REGION_END_G; \ - type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \ - type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \ - type CM_DGAM_RAMB_EXP_REGION_END_R; \ - type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \ - type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \ - type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ - type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ - type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION_START_B; \ - type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ - type CM_DGAM_RAMA_EXP_REGION_START_G; \ - type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ - type CM_DGAM_RAMA_EXP_REGION_START_R; \ - type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ - type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ - type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ - type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ - type CM_DGAM_RAMA_EXP_REGION_END_B; \ - type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \ - type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \ - type CM_DGAM_RAMA_EXP_REGION_END_G; \ - type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \ - type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \ - type CM_DGAM_RAMA_EXP_REGION_END_R; \ - type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \ - type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \ - type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ - type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ - type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ - type SHARED_MEM_PWR_DIS; \ - type CM_IGAM_LUT_FORMAT_R; \ - type CM_IGAM_LUT_FORMAT_G; \ - type CM_IGAM_LUT_FORMAT_B; \ - type CM_IGAM_LUT_HOST_EN; \ - type CM_IGAM_LUT_RW_INDEX; \ - type CM_IGAM_LUT_RW_MODE; \ - type CM_IGAM_LUT_WRITE_EN_MASK; \ - type CM_IGAM_LUT_SEL; \ - type CM_IGAM_LUT_SEQ_COLOR; \ - type CM_IGAM_DGAM_CONFIG_STATUS; \ - type CM_DGAM_LUT_WRITE_EN_MASK; \ - type CM_DGAM_LUT_WRITE_SEL; \ - type CM_DGAM_LUT_INDEX; \ - type CM_DGAM_LUT_DATA; \ - type CM_BYPASS_EN; \ - type CM_BYPASS; \ type CNVC_SURFACE_PIXEL_FORMAT; \ type CNVC_BYPASS; \ type ALPHA_EN; \ type FORMAT_EXPANSION_MODE; \ - type CM_DGAM_LUT_MODE; \ - type CM_IGAM_LUT_MODE; \ type CURSOR0_DST_Y_OFFSET; \ type CURSOR0_CHUNK_HDL_ADJUST; \ type CUR0_MODE; \ @@ -460,7 +108,6 @@ type CURSOR_HOT_SPOT_X; \ type CURSOR_HOT_SPOT_Y; \ type CURSOR_DST_X_OFFSET; \ - type CM_IGAM_INPUT_FORMAT; \ type OUTPUT_FP struct dcn10_ipp_shift { @@ -472,69 +119,6 @@ struct dcn10_ipp_mask { }; struct dcn10_ipp_registers { - uint32_t CM_ICSC_CONTROL; - uint32_t CM_ICSC_C11_C12; - uint32_t CM_ICSC_C13_C14; - uint32_t CM_ICSC_C21_C22; - uint32_t CM_ICSC_C23_C24; - uint32_t CM_ICSC_C31_C32; - uint32_t CM_ICSC_C33_C34; - uint32_t CM_COMA_C11_C12; - uint32_t CM_COMA_C13_C14; - uint32_t CM_COMA_C21_C22; - uint32_t CM_COMA_C23_C24; - uint32_t CM_COMA_C31_C32; - uint32_t CM_COMA_C33_C34; - uint32_t CM_DGAM_RAMB_START_CNTL_B; - uint32_t CM_DGAM_RAMB_START_CNTL_G; - uint32_t CM_DGAM_RAMB_START_CNTL_R; - uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; - uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; - uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; - uint32_t CM_DGAM_RAMB_END_CNTL1_B; - uint32_t CM_DGAM_RAMB_END_CNTL2_B; - uint32_t CM_DGAM_RAMB_END_CNTL1_G; - uint32_t CM_DGAM_RAMB_END_CNTL2_G; - uint32_t CM_DGAM_RAMB_END_CNTL1_R; - uint32_t CM_DGAM_RAMB_END_CNTL2_R; - uint32_t CM_DGAM_RAMB_REGION_0_1; - uint32_t CM_DGAM_RAMB_REGION_2_3; - uint32_t CM_DGAM_RAMB_REGION_4_5; - uint32_t CM_DGAM_RAMB_REGION_6_7; - uint32_t CM_DGAM_RAMB_REGION_8_9; - uint32_t CM_DGAM_RAMB_REGION_10_11; - uint32_t CM_DGAM_RAMB_REGION_12_13; - uint32_t CM_DGAM_RAMB_REGION_14_15; - uint32_t CM_DGAM_RAMA_START_CNTL_B; - uint32_t CM_DGAM_RAMA_START_CNTL_G; - uint32_t CM_DGAM_RAMA_START_CNTL_R; - uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; - uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; - uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; - uint32_t CM_DGAM_RAMA_END_CNTL1_B; - uint32_t CM_DGAM_RAMA_END_CNTL2_B; - uint32_t CM_DGAM_RAMA_END_CNTL1_G; - uint32_t CM_DGAM_RAMA_END_CNTL2_G; - uint32_t CM_DGAM_RAMA_END_CNTL1_R; - uint32_t CM_DGAM_RAMA_END_CNTL2_R; - uint32_t CM_DGAM_RAMA_REGION_0_1; - uint32_t CM_DGAM_RAMA_REGION_2_3; - uint32_t CM_DGAM_RAMA_REGION_4_5; - uint32_t CM_DGAM_RAMA_REGION_6_7; - uint32_t CM_DGAM_RAMA_REGION_8_9; - uint32_t CM_DGAM_RAMA_REGION_10_11; - uint32_t CM_DGAM_RAMA_REGION_12_13; - uint32_t CM_DGAM_RAMA_REGION_14_15; - uint32_t CM_MEM_PWR_CTRL; - uint32_t CM_IGAM_LUT_RW_CONTROL; - uint32_t CM_IGAM_LUT_RW_INDEX; - uint32_t CM_IGAM_LUT_SEQ_COLOR; - uint32_t CM_DGAM_LUT_WRITE_EN_MASK; - uint32_t CM_DGAM_LUT_INDEX; - uint32_t CM_DGAM_LUT_DATA; - uint32_t CM_CONTROL; - uint32_t CM_DGAM_CONTROL; - uint32_t CM_IGAM_CONTROL; uint32_t DPP_CONTROL; uint32_t CURSOR_SETTINS; uint32_t CURSOR_SETTINGS; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 589bddad7e66..9602f261b614 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -98,6 +98,24 @@ enum graphics_csc_adjust_type { GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ }; +enum ipp_degamma_mode { + IPP_DEGAMMA_MODE_BYPASS, + IPP_DEGAMMA_MODE_HW_sRGB, + IPP_DEGAMMA_MODE_HW_xvYCC, + IPP_DEGAMMA_MODE_USER_PWL +}; + +enum ipp_output_format { + IPP_OUTPUT_FORMAT_12_BIT_FIX, + IPP_OUTPUT_FORMAT_16_BIT_BYPASS, + IPP_OUTPUT_FORMAT_FLOAT +}; + +enum expansion_mode { + EXPANSION_MODE_DYNAMIC, + EXPANSION_MODE_ZERO +}; + struct default_adjustment { enum lb_pixel_depth lb_color_depth; enum dc_color_space out_color_space; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 0f952e5b3ae8..7ebfdc1c19c1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -54,12 +54,7 @@ struct ipp_prescale_params { uint16_t scale; }; -enum ipp_degamma_mode { - IPP_DEGAMMA_MODE_BYPASS, - IPP_DEGAMMA_MODE_HW_sRGB, - IPP_DEGAMMA_MODE_HW_xvYCC, - IPP_DEGAMMA_MODE_USER_PWL -}; + enum ovl_color_space { OVL_COLOR_SPACE_UNKNOWN = 0, @@ -68,16 +63,6 @@ enum ovl_color_space { OVL_COLOR_SPACE_YUV709 }; -enum expansion_mode { - EXPANSION_MODE_DYNAMIC, - EXPANSION_MODE_ZERO -}; - -enum ipp_output_format { - IPP_OUTPUT_FORMAT_12_BIT_FIX, - IPP_OUTPUT_FORMAT_16_BIT_BYPASS, - IPP_OUTPUT_FORMAT_FLOAT -}; struct ipp_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index f3d66752ed90..623042d2c272 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -219,6 +219,26 @@ struct transform_funcs { void (*opp_set_regamma_mode)( struct transform *xfm_base, enum opp_regamma mode); + + void (*ipp_set_degamma)( + struct transform *xfm_base, + enum ipp_degamma_mode mode); + + void (*ipp_program_input_lut)( + struct transform *xfm_base, + const struct dc_gamma *gamma); + + void (*ipp_program_degamma_pwl)(struct transform *xfm_base, + const struct pwl_params *params); + + void (*ipp_setup)( + struct transform *xfm_base, + enum surface_pixel_format input_format, + enum expansion_mode mode, + enum ipp_output_format cnv_out_format); + + void (*ipp_full_bypass)(struct transform *xfm_base); + }; extern const uint16_t filter_2tap_16p[18]; -- cgit v1.2.3-59-g8ed1b