From 846c87a068f4b72e200357b899ca4dcc92ef42c4 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Wed, 29 Mar 2017 17:42:34 +0100 Subject: drm: mali-dp: Add support for writeback on DP550/DP650 Mali-DP display processors are able to write the composition result to a memory buffer via the SE. Add entry points in the HAL for enabling/disabling this feature, and implement support for it on DP650 and DP550. DP500 acts differently and so is omitted from this change. Changes since v3: - Fix missing vsync interrupt for DP550 Signed-off-by: Liviu Dudau Signed-off-by: Brian Starkey [rebased and fixed conflicts] Signed-off-by: Mihail Atanassov --- drivers/gpu/drm/arm/malidp_hw.c | 55 +++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/arm/malidp_hw.h | 17 ++++++++++++ drivers/gpu/drm/arm/malidp_regs.h | 15 +++++++++++ 3 files changed, 85 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 069783e715f1..461e62653a36 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -588,6 +588,49 @@ static long malidp550_se_calc_mclk(struct malidp_hw_device *hwdev, return ret; } +static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, + dma_addr_t *addrs, s32 *pitches, + int num_planes, u16 w, u16 h, u32 fmt_id) +{ + u32 base = MALIDP550_SE_MEMWRITE_BASE; + u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); + + /* enable the scaling engine block */ + malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); + + malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); + switch (num_planes) { + case 2: + malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); + malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); + malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); + /* fall through */ + case 1: + malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); + malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); + malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); + break; + default: + WARN(1, "Invalid number of planes"); + } + + malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), + MALIDP550_SE_MEMWRITE_OUT_SIZE); + malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, + MALIDP550_SE_CONTROL); + + return 0; +} + +static void malidp550_disable_memwrite(struct malidp_hw_device *hwdev) +{ + u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); + + malidp_hw_clearbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, + MALIDP550_SE_CONTROL); + malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); +} + static int malidp650_query_hw(struct malidp_hw_device *hwdev) { u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); @@ -674,9 +717,11 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { .se_irq_map = { .irq_mask = MALIDP550_SE_IRQ_EOW | MALIDP550_SE_IRQ_AXI_ERR, + .vsync_irq = MALIDP550_SE_IRQ_EOW, }, .dc_irq_map = { - .irq_mask = MALIDP550_DC_IRQ_CONF_VALID, + .irq_mask = MALIDP550_DC_IRQ_CONF_VALID | + MALIDP550_DC_IRQ_SE, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, }, .pixel_formats = malidp550_de_formats, @@ -692,6 +737,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { .rotmem_required = malidp550_rotmem_required, .se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs, .se_calc_mclk = malidp550_se_calc_mclk, + .enable_memwrite = malidp550_enable_memwrite, + .disable_memwrite = malidp550_disable_memwrite, .features = 0, }, [MALIDP_650] = { @@ -712,9 +759,11 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { .se_irq_map = { .irq_mask = MALIDP550_SE_IRQ_EOW | MALIDP550_SE_IRQ_AXI_ERR, + .vsync_irq = MALIDP550_SE_IRQ_EOW, }, .dc_irq_map = { - .irq_mask = MALIDP550_DC_IRQ_CONF_VALID, + .irq_mask = MALIDP550_DC_IRQ_CONF_VALID | + MALIDP550_DC_IRQ_SE, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, }, .pixel_formats = malidp550_de_formats, @@ -730,6 +779,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { .rotmem_required = malidp550_rotmem_required, .se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs, .se_calc_mclk = malidp550_se_calc_mclk, + .enable_memwrite = malidp550_enable_memwrite, + .disable_memwrite = malidp550_disable_memwrite, .features = 0, }, }; diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index b5dd6c73ec9f..72cc22f82836 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -177,6 +177,23 @@ struct malidp_hw { long (*se_calc_mclk)(struct malidp_hw_device *hwdev, struct malidp_se_config *se_config, struct videomode *vm); + /** + * Enable writing to memory the content of the next frame + * @param hwdev - malidp_hw_device structure containing the HW description + * @param addrs - array of addresses for each plane + * @param pitches - array of pitches for each plane + * @param num_planes - number of planes to be written + * @param w - width of the output frame + * @param h - height of the output frame + * @param fmt_id - internal format ID of output buffer + */ + int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, + s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id); + + /* + * Disable the writing to memory of the next frame's content. + */ + void (*disable_memwrite)(struct malidp_hw_device *hwdev); u8 features; }; diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 149024fb4432..e2b2c496225e 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -66,6 +66,8 @@ #define MALIDP_DISP_FUNC_GAMMA (1 << 0) #define MALIDP_DISP_FUNC_CADJ (1 << 4) #define MALIDP_DISP_FUNC_ILACED (1 << 8) +#define MALIDP_SCALE_ENGINE_EN (1 << 16) +#define MALIDP_SE_MEMWRITE_EN (2 << 5) /* register offsets for IRQ management */ #define MALIDP_REG_STATUS 0x00000 @@ -153,6 +155,16 @@ (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) #define MALIDP_SE_ENH_COEFF0 0x04 + +/* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ +#define MALIDP_MW_FORMAT 0x00000 +#define MALIDP_MW_P1_STRIDE 0x00004 +#define MALIDP_MW_P2_STRIDE 0x00008 +#define MALIDP_MW_P1_PTR_LOW 0x0000c +#define MALIDP_MW_P1_PTR_HIGH 0x00010 +#define MALIDP_MW_P2_PTR_LOW 0x0002c +#define MALIDP_MW_P2_PTR_HIGH 0x00030 + /* register offsets and bits specific to DP500 */ #define MALIDP500_ADDR_SPACE_SIZE 0x01000 #define MALIDP500_DC_BASE 0x00000 @@ -217,6 +229,9 @@ #define MALIDP550_DE_PERF_BASE 0x00500 #define MALIDP550_SE_BASE 0x08000 #define MALIDP550_SE_CONTROL 0x08010 +#define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7) +#define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030 +#define MALIDP550_SE_MEMWRITE_BASE 0x08100 #define MALIDP550_DC_BASE 0x0c000 #define MALIDP550_DC_CONTROL 0x0c010 #define MALIDP550_DC_CONFIG_REQ (1 << 16) -- cgit v1.2.3-59-g8ed1b From a67bbbe225c281f441533d55cd9dce5c2ae207a5 Mon Sep 17 00:00:00 2001 From: Brian Starkey Date: Wed, 29 Mar 2017 17:42:35 +0100 Subject: drm: mali-dp: Add RGB writeback formats for DP550/DP650 Add a layer bit for the SE memory-write, and add it to the pixel format matrix for DP550/DP650. Signed-off-by: Brian Starkey [rebased and fixed conflicts] Signed-off-by: Mihail Atanassov Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_hw.c | 22 +++++++++++----------- drivers/gpu/drm/arm/malidp_hw.h | 1 + 2 files changed, 12 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 461e62653a36..c98b3e02dd54 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -47,27 +47,27 @@ static const struct malidp_format_id malidp500_de_formats[] = { #define MALIDP_COMMON_FORMATS \ /* fourcc, layers supporting the format, internal id */ \ - { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \ - { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \ - { DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \ - { DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \ + { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 0) }, \ + { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 1) }, \ + { DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 2) }, \ + { DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 3) }, \ { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \ { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \ { DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \ { DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \ - { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \ - { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \ - { DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \ - { DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \ - { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \ - { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \ + { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 0) }, \ + { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 1) }, \ + { DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 2) }, \ + { DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 3) }, \ + { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(3, 0) }, \ + { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(3, 1) }, \ { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \ { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \ { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \ { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \ { DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \ { DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \ - { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \ + { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(5, 6) }, \ { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) } static const struct malidp_format_id malidp550_de_formats[] = { diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index 72cc22f82836..a242e97cf642 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -33,6 +33,7 @@ enum { DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ DE_VIDEO2 = BIT(3), DE_SMART = BIT(4), + SE_MEMWRITE = BIT(5), }; struct malidp_format_id { -- cgit v1.2.3-59-g8ed1b From 1cb3cbe732d9bedd4046bbeb2726d1699cdfabce Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Tue, 10 Apr 2018 17:25:57 +0100 Subject: drm/mali-dp: Add writeback support for DP500. Mali DP500 behaves differently from the rest of the Mali DP IP, in that it does not have a one-shot mode and keeps writing the content of the current frame to the provided memory area until stopped. As a way of emulating the one-shot behaviour, we are going to use the CVAL interrupt that is being raised at the start of each frame, during prefetch phase, to act as End-of-Write signal, but with a twist: we are going to disable the memory write engine right after we're notified that it has been enabled, using the knowledge that the bit controlling the enabling will only be acted upon on the next vblank/prefetch. CVAL interrupt will fire durint the next prefetch phase every time the global CVAL bit gets set, so we need a state byte to track the memory write enabling. We also need to pay attention during the disabling of the memory write engine as that requires the CVAL bit to be set in the control register, but we don't want to do that during an atomic commit, as it will write into the hardware a partial state. Reviewed-by: Brian Starkey Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 16 ++++++-- drivers/gpu/drm/arm/malidp_drv.h | 4 ++ drivers/gpu/drm/arm/malidp_hw.c | 82 +++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/arm/malidp_hw.h | 5 ++- drivers/gpu/drm/arm/malidp_regs.h | 3 +- 5 files changed, 101 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 0a788d76ed5f..ab2d27e8bdd9 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -170,14 +170,15 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm) struct malidp_hw_device *hwdev = malidp->dev; int ret; - atomic_set(&malidp->config_valid, 0); hwdev->hw->set_config_valid(hwdev); /* don't wait for config_valid flag if we are in config mode */ - if (hwdev->hw->in_config_mode(hwdev)) + if (hwdev->hw->in_config_mode(hwdev)) { + atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE); return 0; + } ret = wait_event_interruptible_timeout(malidp->wq, - atomic_read(&malidp->config_valid) == 1, + atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE, msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT)); return (ret > 0) ? 0 : -ETIMEDOUT; @@ -216,12 +217,19 @@ static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) static void malidp_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *drm = state->dev; + struct malidp_drm *malidp = drm->dev_private; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; int i; pm_runtime_get_sync(drm->dev); + /* + * set config_valid to a special value to let IRQ handlers + * know that we are updating registers + */ + atomic_set(&malidp->config_valid, MALIDP_CONFIG_START); + drm_atomic_helper_commit_modeset_disables(drm, state); for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { @@ -588,7 +596,7 @@ static int malidp_bind(struct device *dev) out_depth = (out_depth << 8) | (output_width[i] & 0xf); malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base); - atomic_set(&malidp->config_valid, 0); + atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT); init_waitqueue_head(&malidp->wq); ret = malidp_init(drm); diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h index c70989b93387..e8c41cf1b5bd 100644 --- a/drivers/gpu/drm/arm/malidp_drv.h +++ b/drivers/gpu/drm/arm/malidp_drv.h @@ -18,6 +18,10 @@ #include #include "malidp_hw.h" +#define MALIDP_CONFIG_VALID_INIT 0 +#define MALIDP_CONFIG_VALID_DONE 1 +#define MALIDP_CONFIG_START 0xd0 + struct malidp_drm { struct malidp_hw_device *dev; struct drm_crtc crtc; diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index c98b3e02dd54..0f6290b2f768 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -22,6 +22,13 @@ #include "malidp_drv.h" #include "malidp_hw.h" +enum { + MW_NOT_ENABLED = 0, /* SE writeback not enabled */ + MW_ONESHOT, /* SE in one-shot mode for writeback */ + MW_START, /* SE started writeback */ + MW_STOP, /* SE finished writeback */ +}; + static const struct malidp_format_id malidp500_de_formats[] = { /* fourcc, layers supporting the format, internal id */ { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 }, @@ -368,6 +375,51 @@ static long malidp500_se_calc_mclk(struct malidp_hw_device *hwdev, return ret; } +static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev, + dma_addr_t *addrs, s32 *pitches, + int num_planes, u16 w, u16 h, u32 fmt_id) +{ + u32 base = MALIDP500_SE_MEMWRITE_BASE; + u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); + + /* enable the scaling engine block */ + malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); + + hwdev->mw_state = MW_START; + + malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); + switch (num_planes) { + case 2: + malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); + malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); + malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); + /* fall through */ + case 1: + malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); + malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); + malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); + break; + default: + WARN(1, "Invalid number of planes"); + } + + malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), + MALIDP500_SE_MEMWRITE_OUT_SIZE); + malidp_hw_setbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL); + + return 0; +} + +static void malidp500_disable_memwrite(struct malidp_hw_device *hwdev) +{ + u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); + + if (hwdev->mw_state == MW_START) + hwdev->mw_state = MW_STOP; + malidp_hw_clearbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL); + malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); +} + static int malidp550_query_hw(struct malidp_hw_device *hwdev) { u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); @@ -598,6 +650,8 @@ static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, /* enable the scaling engine block */ malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); + hwdev->mw_state = MW_ONESHOT; + malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); switch (num_planes) { case 2: @@ -678,8 +732,9 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { }, .se_irq_map = { .irq_mask = MALIDP500_SE_IRQ_CONF_MODE | + MALIDP500_SE_IRQ_CONF_VALID | MALIDP500_SE_IRQ_GLOBAL, - .vsync_irq = 0, + .vsync_irq = MALIDP500_SE_IRQ_CONF_VALID, }, .dc_irq_map = { .irq_mask = MALIDP500_DE_IRQ_CONF_VALID, @@ -698,6 +753,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { .rotmem_required = malidp500_rotmem_required, .se_set_scaling_coeffs = malidp500_se_set_scaling_coeffs, .se_calc_mclk = malidp500_se_calc_mclk, + .enable_memwrite = malidp500_enable_memwrite, + .disable_memwrite = malidp500_disable_memwrite, .features = MALIDP_DEVICE_LV_HAS_3_STRIDES, }, [MALIDP_550] = { @@ -842,7 +899,7 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) malidp->event = NULL; spin_unlock(&drm->event_lock); } - atomic_set(&malidp->config_valid, 1); + atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE); ret = IRQ_WAKE_THREAD; } @@ -936,7 +993,25 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ); status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS); status &= mask; - /* ToDo: status decoding and firing up of VSYNC and page flip events */ + + if (status & se->vsync_irq) { + switch (hwdev->mw_state) { + case MW_STOP: + /* disable writeback after stop */ + hwdev->mw_state = MW_NOT_ENABLED; + break; + case MW_START: + /* writeback started, need to emulate one-shot mode */ + hw->disable_memwrite(hwdev); + /* + * only set config_valid HW bit if there is no + * other update in progress + */ + if (atomic_read(&malidp->config_valid) != MALIDP_CONFIG_START) + hw->set_config_valid(hwdev); + break; + } + } malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status); @@ -966,6 +1041,7 @@ int malidp_se_irq_init(struct drm_device *drm, int irq) return ret; } + hwdev->mw_state = MW_NOT_ENABLED; malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, hwdev->hw->map.se_irq_map.irq_mask); diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index a242e97cf642..c479738b81af 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -178,7 +178,7 @@ struct malidp_hw { long (*se_calc_mclk)(struct malidp_hw_device *hwdev, struct malidp_se_config *se_config, struct videomode *vm); - /** + /* * Enable writing to memory the content of the next frame * @param hwdev - malidp_hw_device structure containing the HW description * @param addrs - array of addresses for each plane @@ -232,6 +232,9 @@ struct malidp_hw_device { /* track the device PM state */ bool pm_suspended; + /* track the SE memory writeback state */ + u8 mw_state; + /* size of memory used for rotating layers, up to two banks available */ u32 rotation_memory[2]; }; diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index e2b2c496225e..93b198f3af86 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -198,7 +198,8 @@ #define MALIDP500_DE_LG2_PTR_BASE 0x0031c #define MALIDP500_SE_BASE 0x00c00 #define MALIDP500_SE_CONTROL 0x00c0c -#define MALIDP500_SE_PTR_BASE 0x00e0c +#define MALIDP500_SE_MEMWRITE_OUT_SIZE 0x00c2c +#define MALIDP500_SE_MEMWRITE_BASE 0x00e00 #define MALIDP500_DC_IRQ_BASE 0x00f00 #define MALIDP500_CONFIG_VALID 0x00f00 #define MALIDP500_CONFIG_ID 0x00fd4 -- cgit v1.2.3-59-g8ed1b From 09368e32a97587d4e118b800c206b4c86b4db845 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Thu, 12 Apr 2018 18:13:26 +0100 Subject: drm/mali-dp: Add RGB writeback formats for DP500. Annotate the pixel format matrix for DP500 with the memory-write flag for formats that are supported by the SE memwrite engine. Reviewed-by: Brian Starkey Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_hw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 0f6290b2f768..36c7e910069a 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -31,12 +31,12 @@ enum { static const struct malidp_format_id malidp500_de_formats[] = { /* fourcc, layers supporting the format, internal id */ - { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 }, - { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 }, + { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 0 }, + { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 1 }, { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 }, { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 }, - { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 4 }, - { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 5 }, + { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 4 }, + { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 5 }, { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 }, { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 }, { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 }, @@ -45,7 +45,7 @@ static const struct malidp_format_id malidp500_de_formats[] = { { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 }, { DRM_FORMAT_UYVY, DE_VIDEO1, 12 }, { DRM_FORMAT_YUYV, DE_VIDEO1, 13 }, - { DRM_FORMAT_NV12, DE_VIDEO1, 14 }, + { DRM_FORMAT_NV12, DE_VIDEO1 | SE_MEMWRITE, 14 }, { DRM_FORMAT_YUV420, DE_VIDEO1, 15 }, }; -- cgit v1.2.3-59-g8ed1b From 8cbc5caf36ef7a299b5cbedf55f27fd898d700bf Mon Sep 17 00:00:00 2001 From: Brian Starkey Date: Thu, 2 Nov 2017 16:49:51 +0000 Subject: drm: mali-dp: Add writeback connector Mali-DP has a memory writeback engine which can be used to write the composition result to a memory buffer. Expose this functionality as a DRM writeback connector on supported hardware. Changes since v1: Daniel Vetter: - Don't require a modeset when writeback routing changes - Make writeback connector always disconnected Changes since v2: - Rebase onto new drm_writeback_connector - Add reset callback, allocating subclassed state Daniel Vetter: - Squash out-fence support into this commit Gustavo Padovan: - Don't signal fence directly from driver (and drop malidp_mw_job) Changes since v3: - Modifications to fit with Mali-DP commit tail changes Signed-off-by: Brian Starkey [rebased and fixed conflicts] Signed-off-by: Mihail Atanassov Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/Makefile | 1 + drivers/gpu/drm/arm/malidp_crtc.c | 10 ++ drivers/gpu/drm/arm/malidp_drv.c | 19 ++- drivers/gpu/drm/arm/malidp_drv.h | 3 + drivers/gpu/drm/arm/malidp_hw.c | 5 + drivers/gpu/drm/arm/malidp_mw.c | 250 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/arm/malidp_mw.h | 14 +++ drivers/gpu/drm/drm_atomic.c | 4 + 8 files changed, 301 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/arm/malidp_mw.c create mode 100644 drivers/gpu/drm/arm/malidp_mw.h (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/Makefile b/drivers/gpu/drm/arm/Makefile index bb8b158ff90d..3bf31d1a4722 100644 --- a/drivers/gpu/drm/arm/Makefile +++ b/drivers/gpu/drm/arm/Makefile @@ -1,4 +1,5 @@ hdlcd-y := hdlcd_drv.o hdlcd_crtc.o obj-$(CONFIG_DRM_HDLCD) += hdlcd.o mali-dp-y := malidp_drv.o malidp_hw.o malidp_planes.o malidp_crtc.o +mali-dp-y += malidp_mw.o obj-$(CONFIG_DRM_MALI_DISPLAY) += mali-dp.o diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index fcc62bc60f6a..ef44202fb43f 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -411,6 +411,16 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc, } } + /* If only the writeback routing has changed, we don't need a modeset */ + if (state->connectors_changed) { + u32 old_mask = crtc->state->connector_mask; + u32 new_mask = state->connector_mask; + + if ((old_mask ^ new_mask) == + (1 << drm_connector_index(&malidp->mw_connector.base))) + state->connectors_changed = false; + } + ret = malidp_crtc_atomic_check_gamma(crtc, state); ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state); ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state); diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index ab2d27e8bdd9..e58a759fd3be 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -31,6 +31,7 @@ #include #include "malidp_drv.h" +#include "malidp_mw.h" #include "malidp_regs.h" #include "malidp_hw.h" @@ -238,7 +239,9 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state) malidp_atomic_commit_se_config(crtc, old_crtc_state); } - drm_atomic_helper_commit_planes(drm, state, 0); + drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY); + + malidp_mw_atomic_commit(drm, state); drm_atomic_helper_commit_modeset_enables(drm, state); @@ -276,12 +279,18 @@ static int malidp_init(struct drm_device *drm) drm->mode_config.helper_private = &malidp_mode_config_helpers; ret = malidp_crtc_init(drm); - if (ret) { - drm_mode_config_cleanup(drm); - return ret; - } + if (ret) + goto crtc_fail; + + ret = malidp_mw_connector_init(drm); + if (ret) + goto crtc_fail; return 0; + +crtc_fail: + drm_mode_config_cleanup(drm); + return ret; } static void malidp_fini(struct drm_device *drm) diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h index e8c41cf1b5bd..5febd4b43e05 100644 --- a/drivers/gpu/drm/arm/malidp_drv.h +++ b/drivers/gpu/drm/arm/malidp_drv.h @@ -13,6 +13,8 @@ #ifndef __MALIDP_DRV_H__ #define __MALIDP_DRV_H__ +#include +#include #include #include #include @@ -25,6 +27,7 @@ struct malidp_drm { struct malidp_hw_device *dev; struct drm_crtc crtc; + struct drm_writeback_connector mw_connector; wait_queue_head_t wq; struct drm_pending_vblank_event *event; atomic_t config_valid; diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 36c7e910069a..449b7ef0a77f 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -21,6 +21,7 @@ #include "malidp_drv.h" #include "malidp_hw.h" +#include "malidp_mw.h" enum { MW_NOT_ENABLED = 0, /* SE writeback not enabled */ @@ -996,7 +997,11 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) if (status & se->vsync_irq) { switch (hwdev->mw_state) { + case MW_ONESHOT: + drm_writeback_signal_completion(&malidp->mw_connector, 0); + break; case MW_STOP: + drm_writeback_signal_completion(&malidp->mw_connector, 0); /* disable writeback after stop */ hwdev->mw_state = MW_NOT_ENABLED; break; diff --git a/drivers/gpu/drm/arm/malidp_mw.c b/drivers/gpu/drm/arm/malidp_mw.c new file mode 100644 index 000000000000..cfd718e7e97c --- /dev/null +++ b/drivers/gpu/drm/arm/malidp_mw.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. + * Author: Brian Starkey + * + * ARM Mali DP Writeback connector implementation + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "malidp_drv.h" +#include "malidp_hw.h" +#include "malidp_mw.h" + +#define to_mw_state(_state) (struct malidp_mw_connector_state *)(_state) + +struct malidp_mw_connector_state { + struct drm_connector_state base; + dma_addr_t addrs[2]; + s32 pitches[2]; + u8 format; + u8 n_planes; +}; + +static int malidp_mw_connector_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + + return drm_add_modes_noedid(connector, dev->mode_config.max_width, + dev->mode_config.max_height); +} + +static enum drm_mode_status +malidp_mw_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct drm_device *dev = connector->dev; + struct drm_mode_config *mode_config = &dev->mode_config; + int w = mode->hdisplay, h = mode->vdisplay; + + if ((w < mode_config->min_width) || (w > mode_config->max_width)) + return MODE_BAD_HVALUE; + + if ((h < mode_config->min_height) || (h > mode_config->max_height)) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + +const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = { + .get_modes = malidp_mw_connector_get_modes, + .mode_valid = malidp_mw_connector_mode_valid, +}; + +static void malidp_mw_connector_reset(struct drm_connector *connector) +{ + struct malidp_mw_connector_state *mw_state = + kzalloc(sizeof(*mw_state), GFP_KERNEL); + + if (connector->state) + __drm_atomic_helper_connector_destroy_state(connector->state); + + kfree(connector->state); + __drm_atomic_helper_connector_reset(connector, &mw_state->base); +} + +static enum drm_connector_status +malidp_mw_connector_detect(struct drm_connector *connector, bool force) +{ + return connector_status_disconnected; +} + +static void malidp_mw_connector_destroy(struct drm_connector *connector) +{ + drm_connector_cleanup(connector); +} + +static struct drm_connector_state * +malidp_mw_connector_duplicate_state(struct drm_connector *connector) +{ + struct malidp_mw_connector_state *mw_state; + + if (WARN_ON(!connector->state)) + return NULL; + + mw_state = kzalloc(sizeof(*mw_state), GFP_KERNEL); + if (!mw_state) + return NULL; + + /* No need to preserve any of our driver-local data */ + __drm_atomic_helper_connector_duplicate_state(connector, &mw_state->base); + + return &mw_state->base; +} + +static const struct drm_connector_funcs malidp_mw_connector_funcs = { + .reset = malidp_mw_connector_reset, + .detect = malidp_mw_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = malidp_mw_connector_destroy, + .atomic_duplicate_state = malidp_mw_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int +malidp_mw_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct malidp_mw_connector_state *mw_state = to_mw_state(conn_state); + struct malidp_drm *malidp = encoder->dev->dev_private; + struct drm_framebuffer *fb; + int i, n_planes; + + if (!conn_state->writeback_job || !conn_state->writeback_job->fb) + return 0; + + fb = conn_state->writeback_job->fb; + if ((fb->width != crtc_state->mode.hdisplay) || + (fb->height != crtc_state->mode.vdisplay)) { + DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", + fb->width, fb->height); + return -EINVAL; + } + + mw_state->format = + malidp_hw_get_format_id(&malidp->dev->hw->map, SE_MEMWRITE, + fb->format->format); + if (mw_state->format == MALIDP_INVALID_FORMAT_ID) { + struct drm_format_name_buf format_name; + + DRM_DEBUG_KMS("Invalid pixel format %s\n", + drm_get_format_name(fb->format->format, + &format_name)); + return -EINVAL; + } + + n_planes = drm_format_num_planes(fb->format->format); + for (i = 0; i < n_planes; i++) { + struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, i); + /* memory write buffers are never rotated */ + u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 0); + + if (fb->pitches[i] & (alignment - 1)) { + DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", + fb->pitches[i], i); + return -EINVAL; + } + mw_state->pitches[i] = fb->pitches[i]; + mw_state->addrs[i] = obj->paddr + fb->offsets[i]; + } + mw_state->n_planes = n_planes; + + return 0; +} + +static const struct drm_encoder_helper_funcs malidp_mw_encoder_helper_funcs = { + .atomic_check = malidp_mw_encoder_atomic_check, +}; + +static u32 *get_writeback_formats(struct malidp_drm *malidp, int *n_formats) +{ + const struct malidp_hw_regmap *map = &malidp->dev->hw->map; + u32 *formats; + int n, i; + + formats = kcalloc(map->n_pixel_formats, sizeof(*formats), + GFP_KERNEL); + if (!formats) + return NULL; + + for (n = 0, i = 0; i < map->n_pixel_formats; i++) { + if (map->pixel_formats[i].layer & SE_MEMWRITE) + formats[n++] = map->pixel_formats[i].format; + } + + *n_formats = n; + + return formats; +} + +int malidp_mw_connector_init(struct drm_device *drm) +{ + struct malidp_drm *malidp = drm->dev_private; + u32 *formats; + int ret, n_formats; + + if (!malidp->dev->hw->enable_memwrite) + return 0; + + malidp->mw_connector.encoder.possible_crtcs = 1 << drm_crtc_index(&malidp->crtc); + drm_connector_helper_add(&malidp->mw_connector.base, + &malidp_mw_connector_helper_funcs); + + formats = get_writeback_formats(malidp, &n_formats); + if (!formats) + return -ENOMEM; + + ret = drm_writeback_connector_init(drm, &malidp->mw_connector, + &malidp_mw_connector_funcs, + &malidp_mw_encoder_helper_funcs, + formats, n_formats); + kfree(formats); + if (ret) + return ret; + + return 0; +} + +void malidp_mw_atomic_commit(struct drm_device *drm, + struct drm_atomic_state *old_state) +{ + struct malidp_drm *malidp = drm->dev_private; + struct drm_writeback_connector *mw_conn = &malidp->mw_connector; + struct drm_connector_state *conn_state = mw_conn->base.state; + struct malidp_hw_device *hwdev = malidp->dev; + struct malidp_mw_connector_state *mw_state; + + if (!conn_state) + return; + + mw_state = to_mw_state(conn_state); + + if (conn_state->writeback_job && conn_state->writeback_job->fb) { + struct drm_framebuffer *fb = conn_state->writeback_job->fb; + + DRM_DEV_DEBUG_DRIVER(drm->dev, + "Enable memwrite %ux%u:%d %pad fmt: %u\n", + fb->width, fb->height, + mw_state->pitches[0], + &mw_state->addrs[0], + mw_state->format); + + drm_writeback_queue_job(mw_conn, conn_state->writeback_job); + conn_state->writeback_job = NULL; + + hwdev->hw->enable_memwrite(hwdev, mw_state->addrs, + mw_state->pitches, mw_state->n_planes, + fb->width, fb->height, mw_state->format); + } else { + DRM_DEV_DEBUG_DRIVER(drm->dev, "Disable memwrite\n"); + hwdev->hw->disable_memwrite(hwdev); + } +} diff --git a/drivers/gpu/drm/arm/malidp_mw.h b/drivers/gpu/drm/arm/malidp_mw.h new file mode 100644 index 000000000000..19a007676a1d --- /dev/null +++ b/drivers/gpu/drm/arm/malidp_mw.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. + * Author: Brian Starkey + * + */ + +#ifndef __MALIDP_MW_H__ +#define __MALIDP_MW_H__ + +int malidp_mw_connector_init(struct drm_device *drm); +void malidp_mw_atomic_commit(struct drm_device *drm, + struct drm_atomic_state *old_state); +#endif diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 178842380f75..965be21b8280 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -1436,6 +1436,10 @@ static void drm_atomic_connector_print_state(struct drm_printer *p, drm_printf(p, "connector[%u]: %s\n", connector->base.id, connector->name); drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name : "(null)"); + if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) + if (state->writeback_job && state->writeback_job->fb) + drm_printf(p, "\tfb=%d\n", state->writeback_job->fb->base.id); + if (connector->funcs->atomic_print_state) connector->funcs->atomic_print_state(p, state); } -- cgit v1.2.3-59-g8ed1b From 0735cfdf0af4d4ffc3743fb75b9ad929dfd37206 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Fri, 15 Jun 2018 16:56:09 +0100 Subject: drm/mali-dp: Improve writeback handling for DP500. Mali DP500 operates in continuous writeback mode (writes frame content until stopped) and it needs special handling in order to behave like a one-shot writeback engine. The original state machine added for DP500 was a bit fragile, as it did not handle correctly cases where a new atomic commit was in progress when the SE IRQ happens and it would commit some partial updates. Improve the handling by adding a parameter to the set_config_valid() function to clear the config valid bit in hardware before starting a new commit and by introducing a MW_RESTART state in the writeback state machine to cater for the case where a new writeback commit gets submitted while the last one is still being active. Reported-by: Brian Starkey Reviewed-by: Brian Starkey Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 3 ++- drivers/gpu/drm/arm/malidp_hw.c | 39 ++++++++++++++++++++++++++++----------- drivers/gpu/drm/arm/malidp_hw.h | 11 ++++++----- 3 files changed, 36 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index e58a759fd3be..078b232c91ab 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -171,7 +171,7 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm) struct malidp_hw_device *hwdev = malidp->dev; int ret; - hwdev->hw->set_config_valid(hwdev); + hwdev->hw->set_config_valid(hwdev, 1); /* don't wait for config_valid flag if we are in config mode */ if (hwdev->hw->in_config_mode(hwdev)) { atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE); @@ -230,6 +230,7 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state) * know that we are updating registers */ atomic_set(&malidp->config_valid, MALIDP_CONFIG_START); + malidp->dev->hw->set_config_valid(malidp->dev, 0); drm_atomic_helper_commit_modeset_disables(drm, state); diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 449b7ef0a77f..b5c645cf4d1c 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -27,7 +27,8 @@ enum { MW_NOT_ENABLED = 0, /* SE writeback not enabled */ MW_ONESHOT, /* SE in one-shot mode for writeback */ MW_START, /* SE started writeback */ - MW_STOP, /* SE finished writeback */ + MW_RESTART, /* SE will start another writeback after this one */ + MW_STOP, /* SE needs to stop after this writeback */ }; static const struct malidp_format_id malidp500_de_formats[] = { @@ -231,9 +232,12 @@ static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev) return false; } -static void malidp500_set_config_valid(struct malidp_hw_device *hwdev) +static void malidp500_set_config_valid(struct malidp_hw_device *hwdev, u8 value) { - malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); + if (value) + malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); + else + malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); } static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode) @@ -386,7 +390,11 @@ static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev, /* enable the scaling engine block */ malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); - hwdev->mw_state = MW_START; + /* restart the writeback if already enabled */ + if (hwdev->mw_state != MW_NOT_ENABLED) + hwdev->mw_state = MW_RESTART; + else + hwdev->mw_state = MW_START; malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); switch (num_planes) { @@ -415,7 +423,7 @@ static void malidp500_disable_memwrite(struct malidp_hw_device *hwdev) { u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); - if (hwdev->mw_state == MW_START) + if (hwdev->mw_state == MW_START || hwdev->mw_state == MW_RESTART) hwdev->mw_state = MW_STOP; malidp_hw_clearbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL); malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); @@ -500,9 +508,12 @@ static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev) return false; } -static void malidp550_set_config_valid(struct malidp_hw_device *hwdev) +static void malidp550_set_config_valid(struct malidp_hw_device *hwdev, u8 value) { - malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); + if (value) + malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); + else + malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); } static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode) @@ -1005,15 +1016,21 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) /* disable writeback after stop */ hwdev->mw_state = MW_NOT_ENABLED; break; + case MW_RESTART: + drm_writeback_signal_completion(&malidp->mw_connector, 0); + /* fall through to a new start */ case MW_START: /* writeback started, need to emulate one-shot mode */ hw->disable_memwrite(hwdev); /* - * only set config_valid HW bit if there is no - * other update in progress + * only set config_valid HW bit if there is no other update + * in progress or if we raced ahead of the DE IRQ handler + * and config_valid flag will not be update until later */ - if (atomic_read(&malidp->config_valid) != MALIDP_CONFIG_START) - hw->set_config_valid(hwdev); + status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS); + if ((atomic_read(&malidp->config_valid) != MALIDP_CONFIG_START) || + (status & hw->map.dc_irq_map.vsync_irq)) + hw->set_config_valid(hwdev, 1); break; } } diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index c479738b81af..bd41aa6974a0 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -152,12 +152,13 @@ struct malidp_hw { bool (*in_config_mode)(struct malidp_hw_device *hwdev); /* - * Set configuration valid flag for hardware parameters that can - * be changed outside the configuration mode. Hardware will use - * the new settings when config valid is set after the end of the - * current buffer scanout + * Set/clear configuration valid flag for hardware parameters that can + * be changed outside the configuration mode to the given value. + * Hardware will use the new settings when config valid is set, + * after the end of the current buffer scanout, and will ignore + * any new values for those parameters if config valid flag is cleared */ - void (*set_config_valid)(struct malidp_hw_device *hwdev); + void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value); /* * Set a new mode in hardware. Requires the hardware to be in -- cgit v1.2.3-59-g8ed1b From 613c5c7fc8152866a798c52a5944e4b437b526f5 Mon Sep 17 00:00:00 2001 From: Alexandru Gheorghe Date: Tue, 15 May 2018 11:18:50 +0100 Subject: drm: mali-dp: Add debugfs file for reporting internal errors Status register contains a lot of bits for reporting internal errors inside Mali DP. Currently, we just silently ignore all of the errors, that doesn't help when we are investigating different bugs, especially on the FPGA models which have a lot of constraints, so we could easily end up in AXI or underrun errors. Add a new file called debug that contains an aggregate of the errors reported by the Mali DP hardware. E.g: [root@alarm ~]# cat /sys/kernel/debug/dri/1/debug [DE] num_errors : 167 [DE] last_error_status : 0x00000001 [DE] last_error_vblank : 385 [SE] num_errors : 3 [SE] last_error_status : 0x00e23001 [SE] last_error_vblank : 201 Changes since v2: - Add lock to protect the errors stats. - Add possibility to reset the error stats by writing anything to the debug file. Signed-off-by: Alexandru Gheorghe Acked-by: Liviu Dudau Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 104 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/arm/malidp_drv.h | 19 +++++++ drivers/gpu/drm/arm/malidp_hw.c | 46 ++++++++++++++--- drivers/gpu/drm/arm/malidp_hw.h | 1 + drivers/gpu/drm/arm/malidp_regs.h | 6 +++ 5 files changed, 169 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 078b232c91ab..9b710f6999ed 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -344,6 +345,106 @@ static int malidp_dumb_create(struct drm_file *file_priv, return drm_gem_cma_dumb_create_internal(file_priv, drm, args); } +#ifdef CONFIG_DEBUG_FS + +static void malidp_error_stats_init(struct malidp_error_stats *error_stats) +{ + error_stats->num_errors = 0; + error_stats->last_error_status = 0; + error_stats->last_error_vblank = -1; +} + +void malidp_error(struct malidp_drm *malidp, + struct malidp_error_stats *error_stats, u32 status, + u64 vblank) +{ + unsigned long irqflags; + + spin_lock_irqsave(&malidp->errors_lock, irqflags); + error_stats->last_error_status = status; + error_stats->last_error_vblank = vblank; + error_stats->num_errors++; + spin_unlock_irqrestore(&malidp->errors_lock, irqflags); +} + +void malidp_error_stats_dump(const char *prefix, + struct malidp_error_stats error_stats, + struct seq_file *m) +{ + seq_printf(m, "[%s] num_errors : %d\n", prefix, + error_stats.num_errors); + seq_printf(m, "[%s] last_error_status : 0x%08x\n", prefix, + error_stats.last_error_status); + seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix, + error_stats.last_error_vblank); +} + +static int malidp_show_stats(struct seq_file *m, void *arg) +{ + struct drm_device *drm = m->private; + struct malidp_drm *malidp = drm->dev_private; + unsigned long irqflags; + struct malidp_error_stats de_errors, se_errors; + + spin_lock_irqsave(&malidp->errors_lock, irqflags); + de_errors = malidp->de_errors; + se_errors = malidp->se_errors; + spin_unlock_irqrestore(&malidp->errors_lock, irqflags); + malidp_error_stats_dump("DE", de_errors, m); + malidp_error_stats_dump("SE", se_errors, m); + return 0; +} + +static int malidp_debugfs_open(struct inode *inode, struct file *file) +{ + return single_open(file, malidp_show_stats, inode->i_private); +} + +static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_device *drm = m->private; + struct malidp_drm *malidp = drm->dev_private; + unsigned long irqflags; + + spin_lock_irqsave(&malidp->errors_lock, irqflags); + malidp_error_stats_init(&malidp->de_errors); + malidp_error_stats_init(&malidp->se_errors); + spin_unlock_irqrestore(&malidp->errors_lock, irqflags); + return len; +} + +static const struct file_operations malidp_debugfs_fops = { + .owner = THIS_MODULE, + .open = malidp_debugfs_open, + .read = seq_read, + .write = malidp_debugfs_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int malidp_debugfs_init(struct drm_minor *minor) +{ + struct malidp_drm *malidp = minor->dev->dev_private; + struct dentry *dentry = NULL; + + malidp_error_stats_init(&malidp->de_errors); + malidp_error_stats_init(&malidp->se_errors); + spin_lock_init(&malidp->errors_lock); + dentry = debugfs_create_file("debug", + S_IRUGO | S_IWUSR, + minor->debugfs_root, minor->dev, + &malidp_debugfs_fops); + if (!dentry) { + DRM_ERROR("Cannot create debug file\n"); + return -ENOMEM; + } + return 0; +} + +#endif //CONFIG_DEBUG_FS + static struct drm_driver malidp_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_PRIME, @@ -360,6 +461,9 @@ static struct drm_driver malidp_driver = { .gem_prime_vmap = drm_gem_cma_prime_vmap, .gem_prime_vunmap = drm_gem_cma_prime_vunmap, .gem_prime_mmap = drm_gem_cma_prime_mmap, +#ifdef CONFIG_DEBUG_FS + .debugfs_init = malidp_debugfs_init, +#endif .fops = &fops, .name = "mali-dp", .desc = "ARM Mali Display Processor driver", diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h index 5febd4b43e05..e3eb0cb1f385 100644 --- a/drivers/gpu/drm/arm/malidp_drv.h +++ b/drivers/gpu/drm/arm/malidp_drv.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "malidp_hw.h" @@ -24,6 +25,12 @@ #define MALIDP_CONFIG_VALID_DONE 1 #define MALIDP_CONFIG_START 0xd0 +struct malidp_error_stats { + s32 num_errors; + u32 last_error_status; + s64 last_error_vblank; +}; + struct malidp_drm { struct malidp_hw_device *dev; struct drm_crtc crtc; @@ -32,6 +39,12 @@ struct malidp_drm { struct drm_pending_vblank_event *event; atomic_t config_valid; u32 core_id; +#ifdef CONFIG_DEBUG_FS + struct malidp_error_stats de_errors; + struct malidp_error_stats se_errors; + /* Protects errors stats */ + spinlock_t errors_lock; +#endif }; #define crtc_to_malidp_device(x) container_of(x, struct malidp_drm, crtc) @@ -69,6 +82,12 @@ struct malidp_crtc_state { int malidp_de_planes_init(struct drm_device *drm); int malidp_crtc_init(struct drm_device *drm); +#ifdef CONFIG_DEBUG_FS +void malidp_error(struct malidp_drm *malidp, + struct malidp_error_stats *error_stats, u32 status, + u64 vblank); +#endif + /* often used combination of rotational bits */ #define MALIDP_ROTATED_MASK (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270) diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index b5c645cf4d1c..3dfad2f97c2a 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -741,12 +741,18 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { MALIDP500_DE_IRQ_VSYNC | MALIDP500_DE_IRQ_GLOBAL, .vsync_irq = MALIDP500_DE_IRQ_VSYNC, + .err_mask = MALIDP_DE_IRQ_UNDERRUN | + MALIDP500_DE_IRQ_AXI_ERR | + MALIDP500_DE_IRQ_SATURATION, }, .se_irq_map = { .irq_mask = MALIDP500_SE_IRQ_CONF_MODE | MALIDP500_SE_IRQ_CONF_VALID | MALIDP500_SE_IRQ_GLOBAL, .vsync_irq = MALIDP500_SE_IRQ_CONF_VALID, + .err_mask = MALIDP500_SE_IRQ_INIT_BUSY | + MALIDP500_SE_IRQ_AXI_ERROR | + MALIDP500_SE_IRQ_OVERRUN, }, .dc_irq_map = { .irq_mask = MALIDP500_DE_IRQ_CONF_VALID, @@ -782,11 +788,16 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { .irq_mask = MALIDP_DE_IRQ_UNDERRUN | MALIDP550_DE_IRQ_VSYNC, .vsync_irq = MALIDP550_DE_IRQ_VSYNC, + .err_mask = MALIDP_DE_IRQ_UNDERRUN | + MALIDP550_DE_IRQ_SATURATION | + MALIDP550_DE_IRQ_AXI_ERR, }, .se_irq_map = { - .irq_mask = MALIDP550_SE_IRQ_EOW | - MALIDP550_SE_IRQ_AXI_ERR, + .irq_mask = MALIDP550_SE_IRQ_EOW, .vsync_irq = MALIDP550_SE_IRQ_EOW, + .err_mask = MALIDP550_SE_IRQ_AXI_ERR | + MALIDP550_SE_IRQ_OVR | + MALIDP550_SE_IRQ_IBSY, }, .dc_irq_map = { .irq_mask = MALIDP550_DC_IRQ_CONF_VALID | @@ -824,11 +835,21 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { MALIDP650_DE_IRQ_DRIFT | MALIDP550_DE_IRQ_VSYNC, .vsync_irq = MALIDP550_DE_IRQ_VSYNC, + .err_mask = MALIDP_DE_IRQ_UNDERRUN | + MALIDP650_DE_IRQ_DRIFT | + MALIDP550_DE_IRQ_SATURATION | + MALIDP550_DE_IRQ_AXI_ERR | + MALIDP650_DE_IRQ_ACEV1 | + MALIDP650_DE_IRQ_ACEV2 | + MALIDP650_DE_IRQ_ACEG | + MALIDP650_DE_IRQ_AXIEP, }, .se_irq_map = { - .irq_mask = MALIDP550_SE_IRQ_EOW | - MALIDP550_SE_IRQ_AXI_ERR, + .irq_mask = MALIDP550_SE_IRQ_EOW, .vsync_irq = MALIDP550_SE_IRQ_EOW, + .err_mask = MALIDP550_SE_IRQ_AXI_ERR | + MALIDP550_SE_IRQ_OVR | + MALIDP550_SE_IRQ_IBSY, }, .dc_irq_map = { .irq_mask = MALIDP550_DC_IRQ_CONF_VALID | @@ -920,10 +941,17 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) return ret; mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ); - status &= mask; + /* keep the status of the enabled interrupts, plus the error bits */ + status &= (mask | de->err_mask); if ((status & de->vsync_irq) && malidp->crtc.enabled) drm_crtc_handle_vblank(&malidp->crtc); +#ifdef CONFIG_DEBUG_FS + if (status & de->err_mask) { + malidp_error(malidp, &malidp->de_errors, status, + drm_crtc_vblank_count(&malidp->crtc)); + } +#endif malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status); return (ret == IRQ_NONE) ? IRQ_HANDLED : ret; @@ -999,11 +1027,15 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) return IRQ_NONE; status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS); - if (!(status & se->irq_mask)) + if (!(status & (se->irq_mask | se->err_mask))) return IRQ_NONE; +#ifdef CONFIG_DEBUG_FS + if (status & se->err_mask) + malidp_error(malidp, &malidp->se_errors, status, + drm_crtc_vblank_count(&malidp->crtc)); +#endif mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ); - status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS); status &= mask; if (status & se->vsync_irq) { diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index bd41aa6974a0..5b99445433a2 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -53,6 +53,7 @@ struct malidp_format_id { struct malidp_irq_map { u32 irq_mask; /* mask of IRQs that can be enabled in the block */ u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ + u32 err_mask; /* mask of bits that represent errors */ }; struct malidp_layer { diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 93b198f3af86..3579d36b2a71 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -53,6 +53,8 @@ #define MALIDP550_DE_IRQ_AXI_ERR (1 << 16) #define MALIDP550_SE_IRQ_EOW (1 << 0) #define MALIDP550_SE_IRQ_AXI_ERR (1 << 16) +#define MALIDP550_SE_IRQ_OVR (1 << 17) +#define MALIDP550_SE_IRQ_IBSY (1 << 18) #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0) #define MALIDP550_DC_IRQ_CONF_MODE (1 << 4) #define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16) @@ -60,6 +62,10 @@ #define MALIDP550_DC_IRQ_SE (1 << 24) #define MALIDP650_DE_IRQ_DRIFT (1 << 4) +#define MALIDP650_DE_IRQ_ACEV1 (1 << 17) +#define MALIDP650_DE_IRQ_ACEV2 (1 << 18) +#define MALIDP650_DE_IRQ_ACEG (1 << 19) +#define MALIDP650_DE_IRQ_AXIEP (1 << 28) /* bit masks that are common between products */ #define MALIDP_CFG_VALID (1 << 0) -- cgit v1.2.3-59-g8ed1b From 62862cfbb18d10c5f8409f4c8e49c4bbaaf18d3a Mon Sep 17 00:00:00 2001 From: Ayan Kumar Halder Date: Tue, 15 May 2018 17:04:15 +0100 Subject: drm/arm/malidp: Modified the prototype of malidp irq de-initializers Malidp uses two interrupts ie 1. se_irq - used for memory writeback. and 2. de_irq - used for display output. 'struct drm_device' is being replaced with 'struct malidp_hw_device' as the function argument. The reason being the dependency of malidp_de_irq_fini on 'struct drm_device' needs to be removed so as to enable it to call from functions which receives 'struct malidp_hw_device' as argument. Furthermore, there is no way to retrieve 'struct drm_device' from 'struct malidp_hw_device'. Signed-off-by: Ayan Kumar Halder Acked-by: Liviu Dudau Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 13 ++++++++----- drivers/gpu/drm/arm/malidp_hw.c | 10 ++-------- drivers/gpu/drm/arm/malidp_hw.h | 4 ++-- 3 files changed, 12 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 9b710f6999ed..16fa089fa8be 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -304,6 +304,8 @@ static int malidp_irq_init(struct platform_device *pdev) { int irq_de, irq_se, ret = 0; struct drm_device *drm = dev_get_drvdata(&pdev->dev); + struct malidp_drm *malidp = drm->dev_private; + struct malidp_hw_device *hwdev = malidp->dev; /* fetch the interrupts from DT */ irq_de = platform_get_irq_byname(pdev, "DE"); @@ -323,7 +325,7 @@ static int malidp_irq_init(struct platform_device *pdev) ret = malidp_se_irq_init(drm, irq_se); if (ret) { - malidp_de_irq_fini(drm); + malidp_de_irq_fini(hwdev); return ret; } @@ -763,8 +765,8 @@ register_fail: fbdev_fail: pm_runtime_get_sync(dev); vblank_fail: - malidp_se_irq_fini(drm); - malidp_de_irq_fini(drm); + malidp_se_irq_fini(hwdev); + malidp_de_irq_fini(hwdev); drm->irq_enabled = false; irq_init_fail: drm_atomic_helper_shutdown(drm); @@ -794,14 +796,15 @@ static void malidp_unbind(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); struct malidp_drm *malidp = drm->dev_private; + struct malidp_hw_device *hwdev = malidp->dev; drm_dev_unregister(drm); drm_fb_cma_fbdev_fini(drm); drm_kms_helper_poll_fini(drm); pm_runtime_get_sync(dev); drm_crtc_vblank_off(&malidp->crtc); - malidp_se_irq_fini(drm); - malidp_de_irq_fini(drm); + malidp_se_irq_fini(hwdev); + malidp_de_irq_fini(hwdev); drm->irq_enabled = false; drm_atomic_helper_shutdown(drm); component_unbind_all(dev, drm); diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 3dfad2f97c2a..e30a25ceea2c 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -998,11 +998,8 @@ int malidp_de_irq_init(struct drm_device *drm, int irq) return 0; } -void malidp_de_irq_fini(struct drm_device *drm) +void malidp_de_irq_fini(struct malidp_hw_device *hwdev) { - struct malidp_drm *malidp = drm->dev_private; - struct malidp_hw_device *hwdev = malidp->dev; - malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, hwdev->hw->map.de_irq_map.irq_mask); malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, @@ -1102,11 +1099,8 @@ int malidp_se_irq_init(struct drm_device *drm, int irq) return 0; } -void malidp_se_irq_fini(struct drm_device *drm) +void malidp_se_irq_fini(struct malidp_hw_device *hwdev) { - struct malidp_drm *malidp = drm->dev_private; - struct malidp_hw_device *hwdev = malidp->dev; - malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, hwdev->hw->map.se_irq_map.irq_mask); } diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index 5b99445433a2..8304d7763b8d 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -302,9 +302,9 @@ static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, } int malidp_de_irq_init(struct drm_device *drm, int irq); -void malidp_de_irq_fini(struct drm_device *drm); +void malidp_de_irq_fini(struct malidp_hw_device *hwdev); int malidp_se_irq_init(struct drm_device *drm, int irq); -void malidp_se_irq_fini(struct drm_device *drm); +void malidp_se_irq_fini(struct malidp_hw_device *hwdev); u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, u8 layer_id, u32 format); -- cgit v1.2.3-59-g8ed1b From ff8fc26a764acdf5e0a2f86430bcb96c7b4eebec Mon Sep 17 00:00:00 2001 From: Ayan Kumar Halder Date: Tue, 15 May 2018 17:04:16 +0100 Subject: drm/arm/malidp: Split malidp interrupt initialization functions. Malidp uses two interrupts ie 1. se_irq - used for memory writeback. and 2. de_irq - used for display output. Extract the hardware initialization part from malidp interrupt registration ie (malidp_de_irq_init()/ malidp_se_irq_init()) into a separate function (ie malidp_de_irq_hw_init()/malidp_se_irq_hw_init()) which will be later invoked from runtime_pm_resume function when it needs to re-enable the interrupts. Signed-off-by: Ayan Kumar Halder Acked-by: Liviu Dudau Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_hw.c | 38 +++++++++++++++++++++++++++++--------- drivers/gpu/drm/arm/malidp_hw.h | 2 ++ 2 files changed, 31 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index e30a25ceea2c..47fc112ee32e 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -967,6 +967,23 @@ static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg) return IRQ_HANDLED; } +void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev) +{ + /* ensure interrupts are disabled */ + malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); + malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); + malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); + malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); + + /* first enable the DC block IRQs */ + malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK, + hwdev->hw->map.dc_irq_map.irq_mask); + + /* now enable the DE block IRQs */ + malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK, + hwdev->hw->map.de_irq_map.irq_mask); +} + int malidp_de_irq_init(struct drm_device *drm, int irq) { struct malidp_drm *malidp = drm->dev_private; @@ -987,13 +1004,7 @@ int malidp_de_irq_init(struct drm_device *drm, int irq) return ret; } - /* first enable the DC block IRQs */ - malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK, - hwdev->hw->map.dc_irq_map.irq_mask); - - /* now enable the DE block IRQs */ - malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK, - hwdev->hw->map.de_irq_map.irq_mask); + malidp_de_irq_hw_init(hwdev); return 0; } @@ -1069,6 +1080,16 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) return IRQ_HANDLED; } +void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev) +{ + /* ensure interrupts are disabled */ + malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); + malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); + + malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, + hwdev->hw->map.se_irq_map.irq_mask); +} + static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg) { return IRQ_HANDLED; @@ -1093,8 +1114,7 @@ int malidp_se_irq_init(struct drm_device *drm, int irq) } hwdev->mw_state = MW_NOT_ENABLED; - malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, - hwdev->hw->map.se_irq_map.irq_mask); + malidp_se_irq_hw_init(hwdev); return 0; } diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index 8304d7763b8d..f5b3eab8398b 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -302,6 +302,8 @@ static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, } int malidp_de_irq_init(struct drm_device *drm, int irq); +void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev); +void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev); void malidp_de_irq_fini(struct malidp_hw_device *hwdev); int malidp_se_irq_init(struct drm_device *drm, int irq); void malidp_se_irq_fini(struct malidp_hw_device *hwdev); -- cgit v1.2.3-59-g8ed1b From fbcc454e8a350b929cb04fbcfdfa72fab37acf38 Mon Sep 17 00:00:00 2001 From: Ayan Kumar Halder Date: Tue, 15 May 2018 17:04:17 +0100 Subject: drm/arm/malidp: Enable/disable interrupts in runtime pm Display and scaling engine interrupts need to be disabled when the runtime pm invokes malidp_runtime_pm_suspend(). Conversely, they need to be enabled in malidp_runtime_pm_resume(). This patch depends on: https://lkml.org/lkml/2017/5/15/695 Reported-by: Alexandru-Cosmin Gheorghe Signed-off-by: Alexandru-Cosmin Gheorghe Signed-off-by: Ayan Kumar Halder Acked-by: Liviu Dudau Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 16fa089fa8be..125be226bf6c 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -582,6 +582,8 @@ static int malidp_runtime_pm_suspend(struct device *dev) /* we can only suspend if the hardware is in config mode */ WARN_ON(!hwdev->hw->in_config_mode(hwdev)); + malidp_se_irq_fini(hwdev); + malidp_de_irq_fini(hwdev); hwdev->pm_suspended = true; clk_disable_unprepare(hwdev->mclk); clk_disable_unprepare(hwdev->aclk); @@ -600,6 +602,8 @@ static int malidp_runtime_pm_resume(struct device *dev) clk_prepare_enable(hwdev->aclk); clk_prepare_enable(hwdev->mclk); hwdev->pm_suspended = false; + malidp_de_irq_hw_init(hwdev); + malidp_se_irq_hw_init(hwdev); return 0; } -- cgit v1.2.3-59-g8ed1b From f877006d5db49f3615fcee4bd5eb1a56c053d419 Mon Sep 17 00:00:00 2001 From: Ayan Kumar Halder Date: Tue, 15 May 2018 17:04:18 +0100 Subject: drm/arm/malidp: Set the output_depth register in modeset One needs to store the value of the OUTPUT_DEPTH that one has parsed from device tree, so that it can be restored on system resume. This value is set in the modeset function as this gets reset when the system suspends. Signed-off-by: Ayan Kumar Halder Acked-by: Liviu Dudau Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 1 + drivers/gpu/drm/arm/malidp_hw.c | 4 ++++ drivers/gpu/drm/arm/malidp_hw.h | 1 + 3 files changed, 6 insertions(+) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 125be226bf6c..7237b98be5eb 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -715,6 +715,7 @@ static int malidp_bind(struct device *dev) for (i = 0; i < MAX_OUTPUT_CHANNELS; i++) out_depth = (out_depth << 8) | (output_width[i] & 0xf); malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base); + hwdev->output_color_depth = out_depth; atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT); init_waitqueue_head(&malidp->wq); diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 47fc112ee32e..c94a4422e0e9 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -244,6 +244,8 @@ static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode * { u32 val = 0; + malidp_hw_write(hwdev, hwdev->output_color_depth, + hwdev->hw->map.out_depth_base); malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL); if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= MALIDP500_HSYNCPOL; @@ -520,6 +522,8 @@ static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode * { u32 val = MALIDP_DE_DEFAULT_PREFETCH_START; + malidp_hw_write(hwdev, hwdev->output_color_depth, + hwdev->hw->map.out_depth_base); malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL); /* * Mali-DP550 and Mali-DP650 encode the background color like this: diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index f5b3eab8398b..ad2e96915d44 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -230,6 +230,7 @@ struct malidp_hw_device { u8 min_line_size; u16 max_line_size; + u32 output_color_depth; /* track the device PM state */ bool pm_suspended; -- cgit v1.2.3-59-g8ed1b From e368fc75c190a4ad5853e4ec5a0c8acf86bd5119 Mon Sep 17 00:00:00 2001 From: Ayan Kumar Halder Date: Tue, 15 May 2018 17:04:19 +0100 Subject: drm/arm/malidp: Added the late system pm functions malidp_pm_suspend_late checks if the runtime status is not suspended and if so, invokes malidp_runtime_pm_suspend which disables the display engine/core interrupts and the clocks. It sets the runtime status as suspended. The difference between suspend() and suspend_late() is as follows:- 1. suspend() makes the device quiescent. In our case, we invoke the DRM helper which disables the CRTC. This would have invoked runtime pm suspend but the system suspend process disables runtime pm. 2. suspend_late() It continues the suspend operations of the drm device which was started by suspend(). In our case, it performs the same functionality as runtime_suspend(). The complimentary functions are resume() and resume_early(). In the case of resume_early(), we invoke malidp_runtime_pm_resume() which enables the clocks and the interrupts. It sets the runtime status as active. If the device was in runtime suspend mode before system suspend was called, pm_runtime_work() will put the device back in runtime suspended mode( after the complete system has been resumed). Signed-off-by: Ayan Kumar Halder Acked-by: Liviu Dudau Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/gpu/drm/arm') diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 7237b98be5eb..5b7260557391 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -882,8 +882,25 @@ static int __maybe_unused malidp_pm_resume(struct device *dev) return 0; } +static int __maybe_unused malidp_pm_suspend_late(struct device *dev) +{ + if (!pm_runtime_status_suspended(dev)) { + malidp_runtime_pm_suspend(dev); + pm_runtime_set_suspended(dev); + } + return 0; +} + +static int __maybe_unused malidp_pm_resume_early(struct device *dev) +{ + malidp_runtime_pm_resume(dev); + pm_runtime_set_active(dev); + return 0; +} + static const struct dev_pm_ops malidp_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \ + SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \ SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL) }; -- cgit v1.2.3-59-g8ed1b