From 8c209f42cb3a209c366bae2956c98d8ed0514773 Mon Sep 17 00:00:00 2001 From: Clint Taylor Date: Tue, 8 Jun 2021 10:47:21 -0700 Subject: drm/i915/adl_p: Add initial ADL_P Workarounds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the context WA are already implemented. Adding adl_p platform tag to reflect so. v2: adjust comments for clarity (MattR) BSpec: 54369 Cc: Matt Roper Cc: Aditya Swarup Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Signed-off-by: Anusha Srivatsa Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: José Roberto de Souza Signed-off-by: Swathi Dhanavanthri Signed-off-by: Clint Taylor Link: https://patchwork.freedesktop.org/patch/msgid/20210608174721.17593-1-clinton.a.taylor@intel.com --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.c') diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 71ac57670043..882bfd499e55 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2667,7 +2667,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) } /* - * Display WA #22010492432: ehl, tgl + * Display WA #22010492432: ehl, tgl, adl-p * Program half of the nominal DCO divider fraction value. */ static bool @@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) { return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) || - IS_TIGERLAKE(i915)) && + IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) && i915->dpll.ref_clks.nssc == 38400; } -- cgit v1.2.3-59-g8ed1b