From 1db27a7291195057e3a20fb9998e2d365ee897f9 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Thu, 11 Jul 2019 10:31:03 -0700 Subject: drm/i915/tgl: Add power well to support 4th pipe Add power well 5 to support 4th pipe and transcoder on TGL. Cc: James Ausmus Cc: Imre Deak Signed-off-by: Mika Kahola Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-10-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/i915/i915_reg.h') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7df1584e7ff1..ca70be40a467 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9148,6 +9148,7 @@ enum { #define SKL_PW_CTL_IDX_MISC_IO 0 /* ICL/TGL - power wells */ +#define TGL_PW_CTL_IDX_PW_5 4 #define ICL_PW_CTL_IDX_PW_4 3 #define ICL_PW_CTL_IDX_PW_3 2 #define ICL_PW_CTL_IDX_PW_2 1 -- cgit v1.2.3-59-g8ed1b