From 6fa7aec1db07f43d3ad94122c3bd52647c81619e Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Fri, 13 Feb 2015 15:33:01 +0530 Subject: drm/i915: Support for RR switching on VLV Definition of VLV RR switch bit and corresponding toggling in set_drrs function. Signed-off-by: Vandana Kannan Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula Reviewed-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/i915/i915_reg.h') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c2124119692d..55143cb36e74 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3916,6 +3916,7 @@ enum skl_disp_power_wells { #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) #define PIPECONF_CXSR_DOWNCLOCK (1<<16) +#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) #define PIPECONF_BPC_MASK (0x7 << 5) #define PIPECONF_8BPC (0<<5) -- cgit v1.2.3-59-g8ed1b