From c39f472e9f14e49a9bc091977ced0ec45fc00c57 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 13 Jan 2015 22:13:14 +1000 Subject: drm/nouveau: remove symlinks, move core/ to nvkm/ (no code changes) The symlinks were annoying some people, and they're not used anywhere else in the kernel tree. The include directory structure has been changed so that symlinks aren't needed anymore. NVKM has been moved from core/ to nvkm/ to make it more obvious as to what the directory is for, and as some minor prep for when NVKM gets split out into its own module (virt) at a later date. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 204 ++++++++++++++++++++++ 1 file changed, 204 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c new file mode 100644 index 000000000000..183a85a6204e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -0,0 +1,204 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +int +nv10_identify(struct nouveau_device *device) +{ + switch (device->chipset) { + case 0x10: + device->cname = "NV10"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x15: + device->cname = "NV15"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x16: + device->cname = "NV16"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x1a: + device->cname = "nForce"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x11: + device->cname = "NV11"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x17: + device->cname = "NV17"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x1f: + device->cname = "nForce2"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + case 0x18: + device->cname = "NV18"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; + device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; + break; + default: + nv_fatal(device, "unknown Celsius chipset\n"); + return -EINVAL; + } + + return 0; +} -- cgit v1.2.3-59-g8ed1b From f3867f439fd610db0cbcf1bb739001e95b7b25c6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 13 Jan 2015 23:37:38 +1000 Subject: drm/nouveau/clk: rename from clock (no binary change) Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 +- drivers/gpu/drm/nouveau/dispnv04/hw.c | 4 +- drivers/gpu/drm/nouveau/include/nvif/device.h | 4 +- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h | 166 +++++ .../gpu/drm/nouveau/include/nvkm/subdev/clock.h | 166 ----- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c | 16 +- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild | 12 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 600 ++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 680 +++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c | 105 ++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c | 240 ++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c | 559 +++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h | 31 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c | 48 ++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c | 534 ++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h | 20 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c | 435 +++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c | 462 ++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c | 500 +++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h | 9 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c | 246 ++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c | 89 +++ drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h | 17 + drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild | 12 - drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c | 600 ------------------ drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c | 680 --------------------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c | 105 ---- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c | 240 -------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c | 559 ----------------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h | 31 - drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c | 48 -- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c | 534 ---------------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h | 20 - drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c | 435 ------------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c | 462 -------------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c | 500 --------------- drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h | 9 - .../gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c | 246 -------- .../gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c | 89 --- drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h | 17 - drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c | 18 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c | 12 +- 60 files changed, 4873 insertions(+), 4873 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c') diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 38402ade6835..f8ddae26dfbf 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -41,7 +41,7 @@ #include "disp.h" #include -#include +#include static int nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, @@ -113,7 +113,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod struct drm_device *dev = crtc->dev; struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_bios *bios = nvkm_bios(&drm->device); - struct nouveau_clock *clk = nvkm_clock(&drm->device); + struct nouveau_clk *clk = nvkm_clk(&drm->device); struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 3d4c19300768..f9491f926c14 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -253,7 +253,7 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nouveau_clock *clk = nvkm_clock(device); + struct nouveau_clk *clk = nvkm_clk(device); struct nouveau_bios *bios = nvkm_bios(device); struct nvbios_pll pll_lim; struct nouveau_pll_vals pv; @@ -463,7 +463,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head, struct nv04_mode_state *state) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_clock *clk = nvkm_clock(&drm->device); + struct nouveau_clk *clk = nvkm_clk(&drm->device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; int i; diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 4aa1b93a8cd4..e73a16dd97fa 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -32,7 +32,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); #include #include #include -#include +#include #include #include #include @@ -43,7 +43,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); #define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a)) #define nvkm_bar(a) nouveau_bar(nvkm_device(a)) #define nvkm_gpio(a) nouveau_gpio(nvkm_device(a)) -#define nvkm_clock(a) nouveau_clock(nvkm_device(a)) +#define nvkm_clk(a) nouveau_clk(nvkm_device(a)) #define nvkm_i2c(a) nouveau_i2c(nvkm_device(a)) #define nvkm_timer(a) nouveau_timer(nvkm_device(a)) #define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d)) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 21a055aca513..87ecf6d23d9e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -38,7 +38,7 @@ enum nv_subdev_type { NVDEV_SUBDEV_PWR, NVDEV_SUBDEV_VOLT, NVDEV_SUBDEV_THERM, - NVDEV_SUBDEV_CLOCK, + NVDEV_SUBDEV_CLK, NVDEV_ENGINE_FIRST, NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h new file mode 100644 index 000000000000..4524d4eea2f1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h @@ -0,0 +1,166 @@ +#ifndef __NOUVEAU_CLK_H__ +#define __NOUVEAU_CLK_H__ + +#include +#include + +struct nouveau_pll_vals; +struct nvbios_pll; + +enum nv_clk_src { + nv_clk_src_crystal, + nv_clk_src_href, + + nv_clk_src_hclk, + nv_clk_src_hclkm3, + nv_clk_src_hclkm3d2, + nv_clk_src_hclkm2d3, /* NVAA */ + nv_clk_src_hclkm4, /* NVAA */ + nv_clk_src_cclk, /* NVAA */ + + nv_clk_src_host, + + nv_clk_src_sppll0, + nv_clk_src_sppll1, + + nv_clk_src_mpllsrcref, + nv_clk_src_mpllsrc, + nv_clk_src_mpll, + nv_clk_src_mdiv, + + nv_clk_src_core, + nv_clk_src_core_intm, + nv_clk_src_shader, + + nv_clk_src_mem, + + nv_clk_src_gpc, + nv_clk_src_rop, + nv_clk_src_hubk01, + nv_clk_src_hubk06, + nv_clk_src_hubk07, + nv_clk_src_copy, + nv_clk_src_daemon, + nv_clk_src_disp, + nv_clk_src_vdec, + + nv_clk_src_dom6, + + nv_clk_src_max, +}; + +struct nouveau_cstate { + struct list_head head; + u8 voltage; + u32 domain[nv_clk_src_max]; +}; + +struct nouveau_pstate { + struct list_head head; + struct list_head list; /* c-states */ + struct nouveau_cstate base; + u8 pstate; + u8 fanspeed; +}; + +struct nouveau_clk { + struct nouveau_subdev base; + + struct nouveau_domain *domains; + struct nouveau_pstate bstate; + + struct list_head states; + int state_nr; + + struct work_struct work; + wait_queue_head_t wait; + atomic_t waiting; + + struct nvkm_notify pwrsrc_ntfy; + int pwrsrc; + int pstate; /* current */ + int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ + int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ + int astate; /* perfmon adjustment (base) */ + int tstate; /* thermal adjustment (max-) */ + int dstate; /* display adjustment (min+) */ + + bool allow_reclock; + + int (*read)(struct nouveau_clk *, enum nv_clk_src); + int (*calc)(struct nouveau_clk *, struct nouveau_cstate *); + int (*prog)(struct nouveau_clk *); + void (*tidy)(struct nouveau_clk *); + + /*XXX: die, these are here *only* to support the completely + * bat-shit insane what-was-nouveau_hw.c code + */ + int (*pll_calc)(struct nouveau_clk *, struct nvbios_pll *, + int clk, struct nouveau_pll_vals *pv); + int (*pll_prog)(struct nouveau_clk *, u32 reg1, + struct nouveau_pll_vals *pv); +}; + +static inline struct nouveau_clk * +nouveau_clk(void *obj) +{ + return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLK); +} + +struct nouveau_domain { + enum nv_clk_src name; + u8 bios; /* 0xff for none */ +#define NVKM_CLK_DOM_FLAG_CORE 0x01 + u8 flags; + const char *mname; + int mdiv; +}; + +#define nouveau_clk_create(p,e,o,i,r,s,n,d) \ + nouveau_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \ + (void **)d) +#define nouveau_clk_destroy(p) ({ \ + struct nouveau_clk *clk = (p); \ + _nouveau_clk_dtor(nv_object(clk)); \ +}) +#define nouveau_clk_init(p) ({ \ + struct nouveau_clk *clk = (p); \ + _nouveau_clk_init(nv_object(clk)); \ +}) +#define nouveau_clk_fini(p,s) ({ \ + struct nouveau_clk *clk = (p); \ + _nouveau_clk_fini(nv_object(clk), (s)); \ +}) + +int nouveau_clk_create_(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, + struct nouveau_domain *, struct nouveau_pstate *, + int, bool, int, void **); +void _nouveau_clk_dtor(struct nouveau_object *); +int _nouveau_clk_init(struct nouveau_object *); +int _nouveau_clk_fini(struct nouveau_object *, bool); + +extern struct nouveau_oclass nv04_clk_oclass; +extern struct nouveau_oclass nv40_clk_oclass; +extern struct nouveau_oclass *nv50_clk_oclass; +extern struct nouveau_oclass *nv84_clk_oclass; +extern struct nouveau_oclass *nvaa_clk_oclass; +extern struct nouveau_oclass nva3_clk_oclass; +extern struct nouveau_oclass nvc0_clk_oclass; +extern struct nouveau_oclass nve0_clk_oclass; +extern struct nouveau_oclass gk20a_clk_oclass; + +int nv04_clk_pll_set(struct nouveau_clk *, u32 type, u32 freq); +int nv04_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *, + int clk, struct nouveau_pll_vals *); +int nv04_clk_pll_prog(struct nouveau_clk *, u32 reg1, + struct nouveau_pll_vals *); +int nva3_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *, + int clk, struct nouveau_pll_vals *); + +int nouveau_clk_ustate(struct nouveau_clk *, int req, int pwr); +int nouveau_clk_astate(struct nouveau_clk *, int req, int rel, bool wait); +int nouveau_clk_dstate(struct nouveau_clk *, int req, int rel); +int nouveau_clk_tstate(struct nouveau_clk *, int req, int rel); + +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h deleted file mode 100644 index 39ad2d2cee2a..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h +++ /dev/null @@ -1,166 +0,0 @@ -#ifndef __NOUVEAU_CLOCK_H__ -#define __NOUVEAU_CLOCK_H__ - -#include -#include - -struct nouveau_pll_vals; -struct nvbios_pll; - -enum nv_clk_src { - nv_clk_src_crystal, - nv_clk_src_href, - - nv_clk_src_hclk, - nv_clk_src_hclkm3, - nv_clk_src_hclkm3d2, - nv_clk_src_hclkm2d3, /* NVAA */ - nv_clk_src_hclkm4, /* NVAA */ - nv_clk_src_cclk, /* NVAA */ - - nv_clk_src_host, - - nv_clk_src_sppll0, - nv_clk_src_sppll1, - - nv_clk_src_mpllsrcref, - nv_clk_src_mpllsrc, - nv_clk_src_mpll, - nv_clk_src_mdiv, - - nv_clk_src_core, - nv_clk_src_core_intm, - nv_clk_src_shader, - - nv_clk_src_mem, - - nv_clk_src_gpc, - nv_clk_src_rop, - nv_clk_src_hubk01, - nv_clk_src_hubk06, - nv_clk_src_hubk07, - nv_clk_src_copy, - nv_clk_src_daemon, - nv_clk_src_disp, - nv_clk_src_vdec, - - nv_clk_src_dom6, - - nv_clk_src_max, -}; - -struct nouveau_cstate { - struct list_head head; - u8 voltage; - u32 domain[nv_clk_src_max]; -}; - -struct nouveau_pstate { - struct list_head head; - struct list_head list; /* c-states */ - struct nouveau_cstate base; - u8 pstate; - u8 fanspeed; -}; - -struct nouveau_clock { - struct nouveau_subdev base; - - struct nouveau_clocks *domains; - struct nouveau_pstate bstate; - - struct list_head states; - int state_nr; - - struct work_struct work; - wait_queue_head_t wait; - atomic_t waiting; - - struct nvkm_notify pwrsrc_ntfy; - int pwrsrc; - int pstate; /* current */ - int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ - int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ - int astate; /* perfmon adjustment (base) */ - int tstate; /* thermal adjustment (max-) */ - int dstate; /* display adjustment (min+) */ - - bool allow_reclock; - - int (*read)(struct nouveau_clock *, enum nv_clk_src); - int (*calc)(struct nouveau_clock *, struct nouveau_cstate *); - int (*prog)(struct nouveau_clock *); - void (*tidy)(struct nouveau_clock *); - - /*XXX: die, these are here *only* to support the completely - * bat-shit insane what-was-nouveau_hw.c code - */ - int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *pv); - int (*pll_prog)(struct nouveau_clock *, u32 reg1, - struct nouveau_pll_vals *pv); -}; - -static inline struct nouveau_clock * -nouveau_clock(void *obj) -{ - return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLOCK); -} - -struct nouveau_clocks { - enum nv_clk_src name; - u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 - u8 flags; - const char *mname; - int mdiv; -}; - -#define nouveau_clock_create(p,e,o,i,r,s,n,d) \ - nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \ - (void **)d) -#define nouveau_clock_destroy(p) ({ \ - struct nouveau_clock *clk = (p); \ - _nouveau_clock_dtor(nv_object(clk)); \ -}) -#define nouveau_clock_init(p) ({ \ - struct nouveau_clock *clk = (p); \ - _nouveau_clock_init(nv_object(clk)); \ -}) -#define nouveau_clock_fini(p,s) ({ \ - struct nouveau_clock *clk = (p); \ - _nouveau_clock_fini(nv_object(clk), (s)); \ -}) - -int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, - struct nouveau_clocks *, struct nouveau_pstate *, - int, bool, int, void **); -void _nouveau_clock_dtor(struct nouveau_object *); -int _nouveau_clock_init(struct nouveau_object *); -int _nouveau_clock_fini(struct nouveau_object *, bool); - -extern struct nouveau_oclass nv04_clock_oclass; -extern struct nouveau_oclass nv40_clock_oclass; -extern struct nouveau_oclass *nv50_clock_oclass; -extern struct nouveau_oclass *nv84_clock_oclass; -extern struct nouveau_oclass *nvaa_clock_oclass; -extern struct nouveau_oclass nva3_clock_oclass; -extern struct nouveau_oclass nvc0_clock_oclass; -extern struct nouveau_oclass nve0_clock_oclass; -extern struct nouveau_oclass gk20a_clock_oclass; - -int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq); -int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *); -int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, - struct nouveau_pll_vals *); -int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *); - -int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr); -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait); -int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel); -int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index f74f9cbbf3d8..f9589e8935d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -209,7 +209,7 @@ static const u64 disable_map[] = { [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_SUBDEV_CLK ] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c index e34101a3490e..7a7632e65c77 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include "priv.h" @@ -39,7 +39,7 @@ nouveau_control_mthd_pstate_info(struct nouveau_object *object, union { struct nvif_control_pstate_info_v0 v0; } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); + struct nouveau_clk *clk = nouveau_clk(object); int ret; nv_ioctl(object, "control pstate info size %d\n", size); @@ -73,8 +73,8 @@ nouveau_control_mthd_pstate_attr(struct nouveau_object *object, union { struct nvif_control_pstate_attr_v0 v0; } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); - struct nouveau_clocks *domain; + struct nouveau_clk *clk = nouveau_clk(object); + struct nouveau_domain *domain; struct nouveau_pstate *pstate; struct nouveau_cstate *cstate; int i = 0, j = -1; @@ -147,7 +147,7 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object, union { struct nvif_control_pstate_user_v0 v0; } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); + struct nouveau_clk *clk = nouveau_clk(object); int ret; nv_ioctl(object, "control pstate user size %d\n", size); @@ -161,10 +161,10 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object, return ret; if (args->v0.pwrsrc >= 0) { - ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc); + ret |= nouveau_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc); } else { - ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0); - ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1); + ret |= nouveau_clk_ustate(clk, args->v0.ustate, 0); + ret |= nouveau_clk_ustate(clk, args->v0.ustate, 1); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 4e74a3376de8..e453a52135d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -64,7 +64,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass; @@ -106,7 +106,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; #if 0 /* looks to be some non-trivial changes */ - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; /* priv ring says no to 0x10eb14 writes */ device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 573b55f5c2f9..dff51984ea94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -48,7 +48,7 @@ nv04_identify(struct nouveau_device *device) device->cname = "NV04"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -66,7 +66,7 @@ nv04_identify(struct nouveau_device *device) device->cname = "NV05"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 183a85a6204e..af63f5b95f01 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -50,7 +50,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -67,7 +67,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -86,7 +86,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -105,7 +105,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -124,7 +124,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -143,7 +143,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -162,7 +162,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -181,7 +181,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index aa564c68a920..eddeb126c7ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -51,7 +51,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -70,7 +70,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -89,7 +89,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -108,7 +108,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 11bd31da82ab..6fe2d130a2ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -51,7 +51,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -70,7 +70,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; @@ -89,7 +89,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; @@ -109,7 +109,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; @@ -129,7 +129,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index e96c223cb797..d85edd87cec8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -55,7 +55,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -78,7 +78,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -101,7 +101,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -124,7 +124,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -147,7 +147,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -170,7 +170,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -193,7 +193,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -216,7 +216,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -239,7 +239,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; @@ -262,7 +262,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; @@ -285,7 +285,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; @@ -308,7 +308,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -331,7 +331,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -354,7 +354,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -377,7 +377,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -400,7 +400,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 96f568d1321b..ccf82ab16881 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -64,7 +64,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; @@ -90,7 +90,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; @@ -119,7 +119,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; @@ -148,7 +148,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; @@ -177,7 +177,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; @@ -206,7 +206,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; @@ -235,7 +235,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; @@ -264,7 +264,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; @@ -293,7 +293,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; @@ -322,7 +322,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; @@ -351,7 +351,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; @@ -382,7 +382,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; @@ -412,7 +412,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; @@ -442,7 +442,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 72a40f95d048..ff5b2ab674bd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -64,7 +64,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -97,7 +97,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -130,7 +130,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -162,7 +162,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -195,7 +195,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -227,7 +227,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -259,7 +259,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -292,7 +292,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -324,7 +324,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index d308aee028f0..7c02ff5b13ed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -64,7 +64,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -98,7 +98,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -132,7 +132,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -162,7 +162,7 @@ nve0_identify(struct nouveau_device *device) break; case 0xea: device->cname = "GK20A"; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; @@ -188,7 +188,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -222,7 +222,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -256,7 +256,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; @@ -289,7 +289,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c index 63013812f7c9..3a9359e29179 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild index 10ef07cf3f91..39f800a6f1e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild @@ -1,7 +1,7 @@ include $(src)/nvkm/subdev/bar/Kbuild include $(src)/nvkm/subdev/bios/Kbuild include $(src)/nvkm/subdev/bus/Kbuild -include $(src)/nvkm/subdev/clock/Kbuild +include $(src)/nvkm/subdev/clk/Kbuild include $(src)/nvkm/subdev/devinit/Kbuild include $(src)/nvkm/subdev/fb/Kbuild include $(src)/nvkm/subdev/fuse/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild new file mode 100644 index 000000000000..94d10a9e637a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild @@ -0,0 +1,12 @@ +nvkm-y += nvkm/subdev/clk/base.o +nvkm-y += nvkm/subdev/clk/nv04.o +nvkm-y += nvkm/subdev/clk/nv40.o +nvkm-y += nvkm/subdev/clk/nv50.o +nvkm-y += nvkm/subdev/clk/nv84.o +nvkm-y += nvkm/subdev/clk/nva3.o +nvkm-y += nvkm/subdev/clk/nvaa.o +nvkm-y += nvkm/subdev/clk/nvc0.o +nvkm-y += nvkm/subdev/clk/nve0.o +nvkm-y += nvkm/subdev/clk/gk20a.o +nvkm-y += nvkm/subdev/clk/pllnv04.o +nvkm-y += nvkm/subdev/clk/pllnva3.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c new file mode 100644 index 000000000000..a0c21ec3f61d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -0,0 +1,600 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +/****************************************************************************** + * misc + *****************************************************************************/ +static u32 +nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust, + u8 pstate, u8 domain, u32 input) +{ + struct nouveau_bios *bios = nouveau_bios(clk); + struct nvbios_boostE boostE; + u8 ver, hdr, cnt, len; + u16 data; + + data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE); + if (data) { + struct nvbios_boostS boostS; + u8 idx = 0, sver, shdr; + u16 subd; + + input = max(boostE.min, input); + input = min(boostE.max, input); + do { + sver = ver; + shdr = hdr; + subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr, + cnt, len, &boostS); + if (subd && boostS.domain == domain) { + if (adjust) + input = input * boostS.percent / 100; + input = max(boostS.min, input); + input = min(boostS.max, input); + break; + } + } while (subd); + } + + return input; +} + +/****************************************************************************** + * C-States + *****************************************************************************/ +static int +nouveau_cstate_prog(struct nouveau_clk *clk, + struct nouveau_pstate *pstate, int cstatei) +{ + struct nouveau_therm *ptherm = nouveau_therm(clk); + struct nouveau_volt *volt = nouveau_volt(clk); + struct nouveau_cstate *cstate; + int ret; + + if (!list_empty(&pstate->list)) { + cstate = list_entry(pstate->list.prev, typeof(*cstate), head); + } else { + cstate = &pstate->base; + } + + if (ptherm) { + ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); + if (ret && ret != -ENODEV) { + nv_error(clk, "failed to raise fan speed: %d\n", ret); + return ret; + } + } + + if (volt) { + ret = volt->set_id(volt, cstate->voltage, +1); + if (ret && ret != -ENODEV) { + nv_error(clk, "failed to raise voltage: %d\n", ret); + return ret; + } + } + + ret = clk->calc(clk, cstate); + if (ret == 0) { + ret = clk->prog(clk); + clk->tidy(clk); + } + + if (volt) { + ret = volt->set_id(volt, cstate->voltage, -1); + if (ret && ret != -ENODEV) + nv_error(clk, "failed to lower voltage: %d\n", ret); + } + + if (ptherm) { + ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); + if (ret && ret != -ENODEV) + nv_error(clk, "failed to lower fan speed: %d\n", ret); + } + + return 0; +} + +static void +nouveau_cstate_del(struct nouveau_cstate *cstate) +{ + list_del(&cstate->head); + kfree(cstate); +} + +static int +nouveau_cstate_new(struct nouveau_clk *clk, int idx, + struct nouveau_pstate *pstate) +{ + struct nouveau_bios *bios = nouveau_bios(clk); + struct nouveau_domain *domain = clk->domains; + struct nouveau_cstate *cstate = NULL; + struct nvbios_cstepX cstepX; + u8 ver, hdr; + u16 data; + + data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX); + if (!data) + return -ENOENT; + + cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); + if (!cstate) + return -ENOMEM; + + *cstate = pstate->base; + cstate->voltage = cstepX.voltage; + + while (domain && domain->name != nv_clk_src_max) { + if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { + u32 freq = nouveau_clk_adjust(clk, true, + pstate->pstate, + domain->bios, + cstepX.freq); + cstate->domain[domain->name] = freq; + } + domain++; + } + + list_add(&cstate->head, &pstate->list); + return 0; +} + +/****************************************************************************** + * P-States + *****************************************************************************/ +static int +nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei) +{ + struct nouveau_fb *pfb = nouveau_fb(clk); + struct nouveau_pstate *pstate; + int ret, idx = 0; + + list_for_each_entry(pstate, &clk->states, head) { + if (idx++ == pstatei) + break; + } + + nv_debug(clk, "setting performance state %d\n", pstatei); + clk->pstate = pstatei; + + if (pfb->ram->calc) { + int khz = pstate->base.domain[nv_clk_src_mem]; + do { + ret = pfb->ram->calc(pfb, khz); + if (ret == 0) + ret = pfb->ram->prog(pfb); + } while (ret > 0); + pfb->ram->tidy(pfb); + } + + return nouveau_cstate_prog(clk, pstate, 0); +} + +static void +nouveau_pstate_work(struct work_struct *work) +{ + struct nouveau_clk *clk = container_of(work, typeof(*clk), work); + int pstate; + + if (!atomic_xchg(&clk->waiting, 0)) + return; + clk->pwrsrc = power_supply_is_system_supplied(); + + nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", + clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, + clk->astate, clk->tstate, clk->dstate); + + pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; + if (clk->state_nr && pstate != -1) { + pstate = (pstate < 0) ? clk->astate : pstate; + pstate = min(pstate, clk->state_nr - 1 - clk->tstate); + pstate = max(pstate, clk->dstate); + } else { + pstate = clk->pstate = -1; + } + + nv_trace(clk, "-> %d\n", pstate); + if (pstate != clk->pstate) { + int ret = nouveau_pstate_prog(clk, pstate); + if (ret) { + nv_error(clk, "error setting pstate %d: %d\n", + pstate, ret); + } + } + + wake_up_all(&clk->wait); + nvkm_notify_get(&clk->pwrsrc_ntfy); +} + +static int +nouveau_pstate_calc(struct nouveau_clk *clk, bool wait) +{ + atomic_set(&clk->waiting, 1); + schedule_work(&clk->work); + if (wait) + wait_event(clk->wait, !atomic_read(&clk->waiting)); + return 0; +} + +static void +nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate) +{ + struct nouveau_domain *clock = clk->domains - 1; + struct nouveau_cstate *cstate; + char info[3][32] = { "", "", "" }; + char name[4] = "--"; + int i = -1; + + if (pstate->pstate != 0xff) + snprintf(name, sizeof(name), "%02x", pstate->pstate); + + while ((++clock)->name != nv_clk_src_max) { + u32 lo = pstate->base.domain[clock->name]; + u32 hi = lo; + if (hi == 0) + continue; + + nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); + list_for_each_entry(cstate, &pstate->list, head) { + u32 freq = cstate->domain[clock->name]; + lo = min(lo, freq); + hi = max(hi, freq); + nv_debug(clk, "%10d KHz\n", freq); + } + + if (clock->mname && ++i < ARRAY_SIZE(info)) { + lo /= clock->mdiv; + hi /= clock->mdiv; + if (lo == hi) { + snprintf(info[i], sizeof(info[i]), "%s %d MHz", + clock->mname, lo); + } else { + snprintf(info[i], sizeof(info[i]), + "%s %d-%d MHz", clock->mname, lo, hi); + } + } + } + + nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); +} + +static void +nouveau_pstate_del(struct nouveau_pstate *pstate) +{ + struct nouveau_cstate *cstate, *temp; + + list_for_each_entry_safe(cstate, temp, &pstate->list, head) { + nouveau_cstate_del(cstate); + } + + list_del(&pstate->head); + kfree(pstate); +} + +static int +nouveau_pstate_new(struct nouveau_clk *clk, int idx) +{ + struct nouveau_bios *bios = nouveau_bios(clk); + struct nouveau_domain *domain = clk->domains - 1; + struct nouveau_pstate *pstate; + struct nouveau_cstate *cstate; + struct nvbios_cstepE cstepE; + struct nvbios_perfE perfE; + u8 ver, hdr, cnt, len; + u16 data; + + data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE); + if (!data) + return -EINVAL; + if (perfE.pstate == 0xff) + return 0; + + pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); + cstate = &pstate->base; + if (!pstate) + return -ENOMEM; + + INIT_LIST_HEAD(&pstate->list); + + pstate->pstate = perfE.pstate; + pstate->fanspeed = perfE.fanspeed; + cstate->voltage = perfE.voltage; + cstate->domain[nv_clk_src_core] = perfE.core; + cstate->domain[nv_clk_src_shader] = perfE.shader; + cstate->domain[nv_clk_src_mem] = perfE.memory; + cstate->domain[nv_clk_src_vdec] = perfE.vdec; + cstate->domain[nv_clk_src_dom6] = perfE.disp; + + while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) { + struct nvbios_perfS perfS; + u8 sver = ver, shdr = hdr; + u32 perfSe = nvbios_perfSp(bios, data, domain->bios, + &sver, &shdr, cnt, len, &perfS); + if (perfSe == 0 || sver != 0x40) + continue; + + if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { + perfS.v40.freq = nouveau_clk_adjust(clk, false, + pstate->pstate, + domain->bios, + perfS.v40.freq); + } + + cstate->domain[domain->name] = perfS.v40.freq; + } + + data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE); + if (data) { + int idx = cstepE.index; + do { + nouveau_cstate_new(clk, idx, pstate); + } while(idx--); + } + + nouveau_pstate_info(clk, pstate); + list_add_tail(&pstate->head, &clk->states); + clk->state_nr++; + return 0; +} + +/****************************************************************************** + * Adjustment triggers + *****************************************************************************/ +static int +nouveau_clk_ustate_update(struct nouveau_clk *clk, int req) +{ + struct nouveau_pstate *pstate; + int i = 0; + + if (!clk->allow_reclock) + return -ENOSYS; + + if (req != -1 && req != -2) { + list_for_each_entry(pstate, &clk->states, head) { + if (pstate->pstate == req) + break; + i++; + } + + if (pstate->pstate != req) + return -EINVAL; + req = i; + } + + return req + 2; +} + +static int +nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen) +{ + int ret = 1; + + if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) + return -2; + + if (strncasecmpz(mode, "disabled", arglen)) { + char save = mode[arglen]; + long v; + + ((char *)mode)[arglen] = '\0'; + if (!kstrtol(mode, 0, &v)) { + ret = nouveau_clk_ustate_update(clk, v); + if (ret < 0) + ret = 1; + } + ((char *)mode)[arglen] = save; + } + + return ret - 2; +} + +int +nouveau_clk_ustate(struct nouveau_clk *clk, int req, int pwr) +{ + int ret = nouveau_clk_ustate_update(clk, req); + if (ret >= 0) { + if (ret -= 2, pwr) clk->ustate_ac = ret; + else clk->ustate_dc = ret; + return nouveau_pstate_calc(clk, true); + } + return ret; +} + +int +nouveau_clk_astate(struct nouveau_clk *clk, int req, int rel, bool wait) +{ + if (!rel) clk->astate = req; + if ( rel) clk->astate += rel; + clk->astate = min(clk->astate, clk->state_nr - 1); + clk->astate = max(clk->astate, 0); + return nouveau_pstate_calc(clk, wait); +} + +int +nouveau_clk_tstate(struct nouveau_clk *clk, int req, int rel) +{ + if (!rel) clk->tstate = req; + if ( rel) clk->tstate += rel; + clk->tstate = min(clk->tstate, 0); + clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); + return nouveau_pstate_calc(clk, true); +} + +int +nouveau_clk_dstate(struct nouveau_clk *clk, int req, int rel) +{ + if (!rel) clk->dstate = req; + if ( rel) clk->dstate += rel; + clk->dstate = min(clk->dstate, clk->state_nr - 1); + clk->dstate = max(clk->dstate, 0); + return nouveau_pstate_calc(clk, true); +} + +static int +nouveau_clk_pwrsrc(struct nvkm_notify *notify) +{ + struct nouveau_clk *clk = + container_of(notify, typeof(*clk), pwrsrc_ntfy); + nouveau_pstate_calc(clk, false); + return NVKM_NOTIFY_DROP; +} + +/****************************************************************************** + * subdev base class implementation + *****************************************************************************/ + +int +_nouveau_clk_fini(struct nouveau_object *object, bool suspend) +{ + struct nouveau_clk *clk = (void *)object; + nvkm_notify_put(&clk->pwrsrc_ntfy); + return nouveau_subdev_fini(&clk->base, suspend); +} + +int +_nouveau_clk_init(struct nouveau_object *object) +{ + struct nouveau_clk *clk = (void *)object; + struct nouveau_domain *clock = clk->domains; + int ret; + + ret = nouveau_subdev_init(&clk->base); + if (ret) + return ret; + + memset(&clk->bstate, 0x00, sizeof(clk->bstate)); + INIT_LIST_HEAD(&clk->bstate.list); + clk->bstate.pstate = 0xff; + + while (clock->name != nv_clk_src_max) { + ret = clk->read(clk, clock->name); + if (ret < 0) { + nv_error(clk, "%02x freq unknown\n", clock->name); + return ret; + } + clk->bstate.base.domain[clock->name] = ret; + clock++; + } + + nouveau_pstate_info(clk, &clk->bstate); + + clk->astate = clk->state_nr - 1; + clk->tstate = 0; + clk->dstate = 0; + clk->pstate = -1; + nouveau_pstate_calc(clk, true); + return 0; +} + +void +_nouveau_clk_dtor(struct nouveau_object *object) +{ + struct nouveau_clk *clk = (void *)object; + struct nouveau_pstate *pstate, *temp; + + nvkm_notify_fini(&clk->pwrsrc_ntfy); + + list_for_each_entry_safe(pstate, temp, &clk->states, head) { + nouveau_pstate_del(pstate); + } + + nouveau_subdev_destroy(&clk->base); +} + +int +nouveau_clk_create_(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, + struct nouveau_domain *clocks, + struct nouveau_pstate *pstates, int nb_pstates, + bool allow_reclock, + int length, void **object) +{ + struct nouveau_device *device = nv_device(parent); + struct nouveau_clk *clk; + int ret, idx, arglen; + const char *mode; + + ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK", + "clock", length, object); + clk = *object; + if (ret) + return ret; + + INIT_LIST_HEAD(&clk->states); + clk->domains = clocks; + clk->ustate_ac = -1; + clk->ustate_dc = -1; + + INIT_WORK(&clk->work, nouveau_pstate_work); + init_waitqueue_head(&clk->wait); + atomic_set(&clk->waiting, 0); + + /* If no pstates are provided, try and fetch them from the BIOS */ + if (!pstates) { + idx = 0; + do { + ret = nouveau_pstate_new(clk, idx++); + } while (ret == 0); + } else { + for (idx = 0; idx < nb_pstates; idx++) + list_add_tail(&pstates[idx].head, &clk->states); + clk->state_nr = nb_pstates; + } + + clk->allow_reclock = allow_reclock; + + ret = nvkm_notify_init(NULL, &device->event, nouveau_clk_pwrsrc, true, + NULL, 0, 0, &clk->pwrsrc_ntfy); + if (ret) + return ret; + + mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); + if (mode) { + clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen); + clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen); + } + + mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen); + if (mode) + clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen); + + mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen); + if (mode) + clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen); + + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c new file mode 100644 index 000000000000..4529ba20af5e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -0,0 +1,680 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c + * + */ + +#define MHZ (1000 * 1000) + +#define MASK(w) ((1 << w) - 1) + +#define SYS_GPCPLL_CFG_BASE 0x00137000 +#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 + +#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) +#define GPCPLL_CFG_ENABLE BIT(0) +#define GPCPLL_CFG_IDDQ BIT(1) +#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) +#define GPCPLL_CFG_LOCK BIT(17) + +#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) +#define GPCPLL_COEFF_M_SHIFT 0 +#define GPCPLL_COEFF_M_WIDTH 8 +#define GPCPLL_COEFF_N_SHIFT 8 +#define GPCPLL_COEFF_N_WIDTH 8 +#define GPCPLL_COEFF_P_SHIFT 16 +#define GPCPLL_COEFF_P_WIDTH 6 + +#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) +#define GPCPLL_CFG2_SETUP2_SHIFT 16 +#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 + +#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) +#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 + +#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) +#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 +#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 +#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 +#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 +#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 + +#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) +#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 + +#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) +#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 +#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 +#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define GPC2CLK_OUT_VCODIV_WIDTH 6 +#define GPC2CLK_OUT_VCODIV_SHIFT 8 +#define GPC2CLK_OUT_VCODIV1 0 +#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ + GPC2CLK_OUT_VCODIV_SHIFT) +#define GPC2CLK_OUT_BYPDIV_WIDTH 6 +#define GPC2CLK_OUT_BYPDIV_SHIFT 0 +#define GPC2CLK_OUT_BYPDIV31 0x3c +#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ + | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ + | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) +#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ + | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ + | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) + +#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) +#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 +#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ + (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) + +#include +#include + +#ifdef __KERNEL__ +#include +#endif + +static const u8 pl_to_div[] = { +/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ +/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, +}; + +/* All frequencies in Mhz */ +struct gk20a_clk_pllg_params { + u32 min_vco, max_vco; + u32 min_u, max_u; + u32 min_m, max_m; + u32 min_n, max_n; + u32 min_pl, max_pl; +}; + +static const struct gk20a_clk_pllg_params gk20a_pllg_params = { + .min_vco = 1000, .max_vco = 2064, + .min_u = 12, .max_u = 38, + .min_m = 1, .max_m = 255, + .min_n = 8, .max_n = 255, + .min_pl = 1, .max_pl = 32, +}; + +struct gk20a_clk_priv { + struct nouveau_clk base; + const struct gk20a_clk_pllg_params *params; + u32 m, n, pl; + u32 parent_rate; +}; +#define to_gk20a_clk(base) container_of(base, struct gk20a_clk_priv, base) + +static void +gk20a_pllg_read_mnp(struct gk20a_clk_priv *priv) +{ + u32 val; + + val = nv_rd32(priv, GPCPLL_COEFF); + priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); + priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); +} + +static u32 +gk20a_pllg_calc_rate(struct gk20a_clk_priv *priv) +{ + u32 rate; + u32 divider; + + rate = priv->parent_rate * priv->n; + divider = priv->m * pl_to_div[priv->pl]; + do_div(rate, divider); + + return rate / 2; +} + +static int +gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate) +{ + u32 target_clk_f, ref_clk_f, target_freq; + u32 min_vco_f, max_vco_f; + u32 low_pl, high_pl, best_pl; + u32 target_vco_f, vco_f; + u32 best_m, best_n; + u32 u_f; + u32 m, n, n2; + u32 delta, lwv, best_delta = ~0; + u32 pl; + + target_clk_f = rate * 2 / MHZ; + ref_clk_f = priv->parent_rate / MHZ; + + max_vco_f = priv->params->max_vco; + min_vco_f = priv->params->min_vco; + best_m = priv->params->max_m; + best_n = priv->params->min_n; + best_pl = priv->params->min_pl; + + target_vco_f = target_clk_f + target_clk_f / 50; + if (max_vco_f < target_vco_f) + max_vco_f = target_vco_f; + + /* min_pl <= high_pl <= max_pl */ + high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; + high_pl = min(high_pl, priv->params->max_pl); + high_pl = max(high_pl, priv->params->min_pl); + + /* min_pl <= low_pl <= max_pl */ + low_pl = min_vco_f / target_vco_f; + low_pl = min(low_pl, priv->params->max_pl); + low_pl = max(low_pl, priv->params->min_pl); + + /* Find Indices of high_pl and low_pl */ + for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { + if (pl_to_div[pl] >= low_pl) { + low_pl = pl; + break; + } + } + for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { + if (pl_to_div[pl] >= high_pl) { + high_pl = pl; + break; + } + } + + nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, + pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); + + /* Select lowest possible VCO */ + for (pl = low_pl; pl <= high_pl; pl++) { + target_vco_f = target_clk_f * pl_to_div[pl]; + for (m = priv->params->min_m; m <= priv->params->max_m; m++) { + u_f = ref_clk_f / m; + + if (u_f < priv->params->min_u) + break; + if (u_f > priv->params->max_u) + continue; + + n = (target_vco_f * m) / ref_clk_f; + n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; + + if (n > priv->params->max_n) + break; + + for (; n <= n2; n++) { + if (n < priv->params->min_n) + continue; + if (n > priv->params->max_n) + break; + + vco_f = ref_clk_f * n / m; + + if (vco_f >= min_vco_f && vco_f <= max_vco_f) { + lwv = (vco_f + (pl_to_div[pl] / 2)) + / pl_to_div[pl]; + delta = abs(lwv - target_clk_f); + + if (delta < best_delta) { + best_delta = delta; + best_m = m; + best_n = n; + best_pl = pl; + + if (best_delta == 0) + goto found_match; + } + } + } + } + } + +found_match: + WARN_ON(best_delta == ~0); + + if (best_delta != 0) + nv_debug(priv, "no best match for target @ %dMHz on gpc_pll", + target_clk_f); + + priv->m = best_m; + priv->n = best_n; + priv->pl = best_pl; + + target_freq = gk20a_pllg_calc_rate(priv) / MHZ; + + nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", + target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); + + return 0; +} + +static int +gk20a_pllg_slide(struct gk20a_clk_priv *priv, u32 n) +{ + u32 val; + int ramp_timeout; + + /* get old coefficients */ + val = nv_rd32(priv, GPCPLL_COEFF); + /* do nothing if NDIV is the same */ + if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) + return 0; + + /* setup */ + nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, + 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); + nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, + 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); + + /* pll slowdown mode */ + nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, + BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), + BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); + + /* new ndiv ready for ramp */ + val = nv_rd32(priv, GPCPLL_COEFF); + val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); + val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; + udelay(1); + nv_wr32(priv, GPCPLL_COEFF, val); + + /* dynamic ramp to new ndiv */ + val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); + val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; + udelay(1); + nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); + + for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { + udelay(1); + val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); + if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) + break; + } + + /* exit slowdown mode */ + nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, + BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | + BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); + nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); + + if (ramp_timeout <= 0) { + nv_error(priv, "gpcpll dynamic ramp timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void +_gk20a_pllg_enable(struct gk20a_clk_priv *priv) +{ + nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); + nv_rd32(priv, GPCPLL_CFG); +} + +static void +_gk20a_pllg_disable(struct gk20a_clk_priv *priv) +{ + nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); + nv_rd32(priv, GPCPLL_CFG); +} + +static int +_gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide) +{ + u32 val, cfg; + u32 m_old, pl_old, n_lo; + + /* get old coefficients */ + val = nv_rd32(priv, GPCPLL_COEFF); + m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); + + /* do NDIV slide if there is no change in M and PL */ + cfg = nv_rd32(priv, GPCPLL_CFG); + if (allow_slide && priv->m == m_old && priv->pl == pl_old && + (cfg & GPCPLL_CFG_ENABLE)) { + return gk20a_pllg_slide(priv, priv->n); + } + + /* slide down to NDIV_LO */ + n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco, + priv->parent_rate / MHZ); + if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { + int ret = gk20a_pllg_slide(priv, n_lo); + + if (ret) + return ret; + } + + /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ + nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, + 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); + + /* put PLL in bypass before programming it */ + val = nv_rd32(priv, SEL_VCO); + val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); + udelay(2); + nv_wr32(priv, SEL_VCO, val); + + /* get out from IDDQ */ + val = nv_rd32(priv, GPCPLL_CFG); + if (val & GPCPLL_CFG_IDDQ) { + val &= ~GPCPLL_CFG_IDDQ; + nv_wr32(priv, GPCPLL_CFG, val); + nv_rd32(priv, GPCPLL_CFG); + udelay(2); + } + + _gk20a_pllg_disable(priv); + + nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n, + priv->pl); + + n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco, + priv->parent_rate / MHZ); + val = priv->m << GPCPLL_COEFF_M_SHIFT; + val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT; + val |= priv->pl << GPCPLL_COEFF_P_SHIFT; + nv_wr32(priv, GPCPLL_COEFF, val); + + _gk20a_pllg_enable(priv); + + val = nv_rd32(priv, GPCPLL_CFG); + if (val & GPCPLL_CFG_LOCK_DET_OFF) { + val &= ~GPCPLL_CFG_LOCK_DET_OFF; + nv_wr32(priv, GPCPLL_CFG, val); + } + + if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, + GPCPLL_CFG_LOCK)) { + nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); + return -ETIMEDOUT; + } + + /* switch to VCO mode */ + nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); + + /* restore out divider 1:1 */ + val = nv_rd32(priv, GPC2CLK_OUT); + val &= ~GPC2CLK_OUT_VCODIV_MASK; + udelay(2); + nv_wr32(priv, GPC2CLK_OUT, val); + + /* slide up to new NDIV */ + return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0; +} + +static int +gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv) +{ + int err; + + err = _gk20a_pllg_program_mnp(priv, true); + if (err) + err = _gk20a_pllg_program_mnp(priv, false); + + return err; +} + +static void +gk20a_pllg_disable(struct gk20a_clk_priv *priv) +{ + u32 val; + + /* slide to VCO min */ + val = nv_rd32(priv, GPCPLL_CFG); + if (val & GPCPLL_CFG_ENABLE) { + u32 coeff, m, n_lo; + + coeff = nv_rd32(priv, GPCPLL_COEFF); + m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + n_lo = DIV_ROUND_UP(m * priv->params->min_vco, + priv->parent_rate / MHZ); + gk20a_pllg_slide(priv, n_lo); + } + + /* put PLL in bypass before disabling it */ + nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); + + _gk20a_pllg_disable(priv); +} + +#define GK20A_CLK_GPC_MDIV 1000 + +static struct nouveau_domain +gk20a_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, + { nv_clk_src_max } +}; + +static struct nouveau_pstate +gk20a_pstates[] = { + { + .base = { + .domain[nv_clk_src_gpc] = 72000, + .voltage = 0, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 108000, + .voltage = 1, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 180000, + .voltage = 2, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 252000, + .voltage = 3, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 324000, + .voltage = 4, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 396000, + .voltage = 5, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 468000, + .voltage = 6, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 540000, + .voltage = 7, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 612000, + .voltage = 8, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 648000, + .voltage = 9, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 684000, + .voltage = 10, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 708000, + .voltage = 11, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 756000, + .voltage = 12, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 804000, + .voltage = 13, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 852000, + .voltage = 14, + }, + }, +}; + +static int +gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct gk20a_clk_priv *priv = (void *)clk; + + switch (src) { + case nv_clk_src_crystal: + return nv_device(clk)->crystal; + case nv_clk_src_gpc: + gk20a_pllg_read_mnp(priv); + return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV; + default: + nv_error(clk, "invalid clock source %d\n", src); + return -EINVAL; + } +} + +static int +gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct gk20a_clk_priv *priv = (void *)clk; + + return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * + GK20A_CLK_GPC_MDIV); +} + +static int +gk20a_clk_prog(struct nouveau_clk *clk) +{ + struct gk20a_clk_priv *priv = (void *)clk; + + return gk20a_pllg_program_mnp(priv); +} + +static void +gk20a_clk_tidy(struct nouveau_clk *clk) +{ +} + +static int +gk20a_clk_fini(struct nouveau_object *object, bool suspend) +{ + struct gk20a_clk_priv *priv = (void *)object; + int ret; + + ret = nouveau_clk_fini(&priv->base, false); + + gk20a_pllg_disable(priv); + + return ret; +} + +static int +gk20a_clk_init(struct nouveau_object *object) +{ + struct gk20a_clk_priv *priv = (void *)object; + int ret; + + nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); + + ret = nouveau_clk_init(&priv->base); + if (ret) + return ret; + + ret = gk20a_clk_prog(&priv->base); + if (ret) { + nv_error(priv, "cannot initialize clock\n"); + return ret; + } + + return 0; +} + +static int +gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct gk20a_clk_priv *priv; + struct nouveau_platform_device *plat; + int ret; + int i; + + /* Finish initializing the pstates */ + for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { + INIT_LIST_HEAD(&gk20a_pstates[i].list); + gk20a_pstates[i].pstate = i + 1; + } + + ret = nouveau_clk_create(parent, engine, oclass, gk20a_domains, + gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->params = &gk20a_pllg_params; + + plat = nv_device_to_platform(nv_device(parent)); + priv->parent_rate = clk_get_rate(plat->gpu->clk); + nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); + + priv->base.read = gk20a_clk_read; + priv->base.calc = gk20a_clk_calc; + priv->base.prog = gk20a_clk_prog; + priv->base.tidy = gk20a_clk_tidy; + + return 0; +} + +struct nouveau_oclass +gk20a_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xea), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = gk20a_clk_ctor, + .dtor = _nouveau_subdev_dtor, + .init = gk20a_clk_init, + .fini = gk20a_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c new file mode 100644 index 000000000000..de68f2f53204 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c @@ -0,0 +1,105 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include + +#include "pll.h" + +struct nv04_clk_priv { + struct nouveau_clk base; +}; + +int +nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info, + int clk, struct nouveau_pll_vals *pv) +{ + int N1, M1, N2, M2, P; + int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); + if (ret) { + pv->refclk = info->refclk; + pv->N1 = N1; + pv->M1 = M1; + pv->N2 = N2; + pv->M2 = M2; + pv->log2P = P; + } + return ret; +} + +int +nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1, + struct nouveau_pll_vals *pv) +{ + struct nouveau_devinit *devinit = nouveau_devinit(clk); + int cv = nouveau_bios(clk)->version.chip; + + if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || + cv >= 0x40) { + if (reg1 > 0x405c) + setPLL_double_highregs(devinit, reg1, pv); + else + setPLL_double_lowregs(devinit, reg1, pv); + } else + setPLL_single(devinit, reg1, pv); + + return 0; +} + +static struct nouveau_domain +nv04_domain[] = { + { nv_clk_src_max } +}; + +static int +nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv04_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, nv04_domain, NULL, 0, + false, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.pll_calc = nv04_clk_pll_calc; + priv->base.pll_prog = nv04_clk_pll_prog; + return 0; +} + +struct nouveau_oclass +nv04_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c new file mode 100644 index 000000000000..460ca4ab603b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c @@ -0,0 +1,240 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include + +#include "pll.h" + +struct nv40_clk_priv { + struct nouveau_clk base; + u32 ctrl; + u32 npll_ctrl; + u32 npll_coef; + u32 spll; +}; + +static struct nouveau_domain +nv40_domain[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_href , 0xff }, + { nv_clk_src_core , 0xff, 0, "core", 1000 }, + { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, + { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, + { nv_clk_src_max } +}; + +static u32 +read_pll_1(struct nv40_clk_priv *priv, u32 reg) +{ + u32 ctrl = nv_rd32(priv, reg + 0x00); + int P = (ctrl & 0x00070000) >> 16; + int N = (ctrl & 0x0000ff00) >> 8; + int M = (ctrl & 0x000000ff) >> 0; + u32 ref = 27000, clk = 0; + + if (ctrl & 0x80000000) + clk = ref * N / M; + + return clk >> P; +} + +static u32 +read_pll_2(struct nv40_clk_priv *priv, u32 reg) +{ + u32 ctrl = nv_rd32(priv, reg + 0x00); + u32 coef = nv_rd32(priv, reg + 0x04); + int N2 = (coef & 0xff000000) >> 24; + int M2 = (coef & 0x00ff0000) >> 16; + int N1 = (coef & 0x0000ff00) >> 8; + int M1 = (coef & 0x000000ff) >> 0; + int P = (ctrl & 0x00070000) >> 16; + u32 ref = 27000, clk = 0; + + if ((ctrl & 0x80000000) && M1) { + clk = ref * N1 / M1; + if ((ctrl & 0x40000100) == 0x40000000) { + if (M2) + clk = clk * N2 / M2; + else + clk = 0; + } + } + + return clk >> P; +} + +static u32 +read_clk(struct nv40_clk_priv *priv, u32 src) +{ + switch (src) { + case 3: + return read_pll_2(priv, 0x004000); + case 2: + return read_pll_1(priv, 0x004008); + default: + break; + } + + return 0; +} + +static int +nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct nv40_clk_priv *priv = (void *)clk; + u32 mast = nv_rd32(priv, 0x00c040); + + switch (src) { + case nv_clk_src_crystal: + return nv_device(priv)->crystal; + case nv_clk_src_href: + return 100000; /*XXX: PCIE/AGP differ*/ + case nv_clk_src_core: + return read_clk(priv, (mast & 0x00000003) >> 0); + case nv_clk_src_shader: + return read_clk(priv, (mast & 0x00000030) >> 4); + case nv_clk_src_mem: + return read_pll_2(priv, 0x4020); + default: + break; + } + + nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); + return -EINVAL; +} + +static int +nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk, + int *N1, int *M1, int *N2, int *M2, int *log2P) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll pll; + int ret; + + ret = nvbios_pll_parse(bios, reg, &pll); + if (ret) + return ret; + + if (clk < pll.vco1.max_freq) + pll.vco2.max_freq = 0; + + ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); + if (ret == 0) + return -ERANGE; + return ret; +} + +static int +nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct nv40_clk_priv *priv = (void *)clk; + int gclk = cstate->domain[nv_clk_src_core]; + int sclk = cstate->domain[nv_clk_src_shader]; + int N1, M1, N2, M2, log2P; + int ret; + + /* core/geometric clock */ + ret = nv40_clk_calc_pll(priv, 0x004000, gclk, + &N1, &M1, &N2, &M2, &log2P); + if (ret < 0) + return ret; + + if (N2 == M2) { + priv->npll_ctrl = 0x80000100 | (log2P << 16); + priv->npll_coef = (N1 << 8) | M1; + } else { + priv->npll_ctrl = 0xc0000000 | (log2P << 16); + priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; + } + + /* use the second pll for shader/rop clock, if it differs from core */ + if (sclk && sclk != gclk) { + ret = nv40_clk_calc_pll(priv, 0x004008, sclk, + &N1, &M1, NULL, NULL, &log2P); + if (ret < 0) + return ret; + + priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; + priv->ctrl = 0x00000223; + } else { + priv->spll = 0x00000000; + priv->ctrl = 0x00000333; + } + + return 0; +} + +static int +nv40_clk_prog(struct nouveau_clk *clk) +{ + struct nv40_clk_priv *priv = (void *)clk; + nv_mask(priv, 0x00c040, 0x00000333, 0x00000000); + nv_wr32(priv, 0x004004, priv->npll_coef); + nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl); + nv_mask(priv, 0x004008, 0xc007ffff, priv->spll); + mdelay(5); + nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl); + return 0; +} + +static void +nv40_clk_tidy(struct nouveau_clk *clk) +{ +} + +static int +nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv40_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, nv40_domain, NULL, 0, + true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.pll_calc = nv04_clk_pll_calc; + priv->base.pll_prog = nv04_clk_pll_prog; + priv->base.read = nv40_clk_read; + priv->base.calc = nv40_clk_calc; + priv->base.prog = nv40_clk_prog; + priv->base.tidy = nv40_clk_tidy; + return 0; +} + +struct nouveau_oclass +nv40_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0x40), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv40_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c new file mode 100644 index 000000000000..3c462a24922c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -0,0 +1,559 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include "nv50.h" +#include "pll.h" +#include "seq.h" + +static u32 +read_div(struct nv50_clk_priv *priv) +{ + switch (nv_device(priv)->chipset) { + case 0x50: /* it exists, but only has bit 31, not the dividers.. */ + case 0x84: + case 0x86: + case 0x98: + case 0xa0: + return nv_rd32(priv, 0x004700); + case 0x92: + case 0x94: + case 0x96: + return nv_rd32(priv, 0x004800); + default: + return 0x00000000; + } +} + +static u32 +read_pll_src(struct nv50_clk_priv *priv, u32 base) +{ + struct nouveau_clk *clk = &priv->base; + u32 coef, ref = clk->read(clk, nv_clk_src_crystal); + u32 rsel = nv_rd32(priv, 0x00e18c); + int P, N, M, id; + + switch (nv_device(priv)->chipset) { + case 0x50: + case 0xa0: + switch (base) { + case 0x4020: + case 0x4028: id = !!(rsel & 0x00000004); break; + case 0x4008: id = !!(rsel & 0x00000008); break; + case 0x4030: id = 0; break; + default: + nv_error(priv, "ref: bad pll 0x%06x\n", base); + return 0; + } + + coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); + ref *= (coef & 0x01000000) ? 2 : 4; + P = (coef & 0x00070000) >> 16; + N = ((coef & 0x0000ff00) >> 8) + 1; + M = ((coef & 0x000000ff) >> 0) + 1; + break; + case 0x84: + case 0x86: + case 0x92: + coef = nv_rd32(priv, 0x00e81c); + P = (coef & 0x00070000) >> 16; + N = (coef & 0x0000ff00) >> 8; + M = (coef & 0x000000ff) >> 0; + break; + case 0x94: + case 0x96: + case 0x98: + rsel = nv_rd32(priv, 0x00c050); + switch (base) { + case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; + case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; + case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; + case 0x4030: rsel = 3; break; + default: + nv_error(priv, "ref: bad pll 0x%06x\n", base); + return 0; + } + + switch (rsel) { + case 0: id = 1; break; + case 1: return clk->read(clk, nv_clk_src_crystal); + case 2: return clk->read(clk, nv_clk_src_href); + case 3: id = 0; break; + } + + coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); + P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; + P += (coef & 0x00070000) >> 16; + N = (coef & 0x0000ff00) >> 8; + M = (coef & 0x000000ff) >> 0; + break; + default: + BUG_ON(1); + } + + if (M) + return (ref * N / M) >> P; + return 0; +} + +static u32 +read_pll_ref(struct nv50_clk_priv *priv, u32 base) +{ + struct nouveau_clk *clk = &priv->base; + u32 src, mast = nv_rd32(priv, 0x00c040); + + switch (base) { + case 0x004028: + src = !!(mast & 0x00200000); + break; + case 0x004020: + src = !!(mast & 0x00400000); + break; + case 0x004008: + src = !!(mast & 0x00010000); + break; + case 0x004030: + src = !!(mast & 0x02000000); + break; + case 0x00e810: + return clk->read(clk, nv_clk_src_crystal); + default: + nv_error(priv, "bad pll 0x%06x\n", base); + return 0; + } + + if (src) + return clk->read(clk, nv_clk_src_href); + return read_pll_src(priv, base); +} + +static u32 +read_pll(struct nv50_clk_priv *priv, u32 base) +{ + struct nouveau_clk *clk = &priv->base; + u32 mast = nv_rd32(priv, 0x00c040); + u32 ctrl = nv_rd32(priv, base + 0); + u32 coef = nv_rd32(priv, base + 4); + u32 ref = read_pll_ref(priv, base); + u32 freq = 0; + int N1, N2, M1, M2; + + if (base == 0x004028 && (mast & 0x00100000)) { + /* wtf, appears to only disable post-divider on nva0 */ + if (nv_device(priv)->chipset != 0xa0) + return clk->read(clk, nv_clk_src_dom6); + } + + N2 = (coef & 0xff000000) >> 24; + M2 = (coef & 0x00ff0000) >> 16; + N1 = (coef & 0x0000ff00) >> 8; + M1 = (coef & 0x000000ff); + if ((ctrl & 0x80000000) && M1) { + freq = ref * N1 / M1; + if ((ctrl & 0x40000100) == 0x40000000) { + if (M2) + freq = freq * N2 / M2; + else + freq = 0; + } + } + + return freq; +} + +static int +nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct nv50_clk_priv *priv = (void *)clk; + u32 mast = nv_rd32(priv, 0x00c040); + u32 P = 0; + + switch (src) { + case nv_clk_src_crystal: + return nv_device(priv)->crystal; + case nv_clk_src_href: + return 100000; /* PCIE reference clock */ + case nv_clk_src_hclk: + return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); + case nv_clk_src_hclkm3: + return clk->read(clk, nv_clk_src_hclk) * 3; + case nv_clk_src_hclkm3d2: + return clk->read(clk, nv_clk_src_hclk) * 3 / 2; + case nv_clk_src_host: + switch (mast & 0x30000000) { + case 0x00000000: return clk->read(clk, nv_clk_src_href); + case 0x10000000: break; + case 0x20000000: /* !0x50 */ + case 0x30000000: return clk->read(clk, nv_clk_src_hclk); + } + break; + case nv_clk_src_core: + if (!(mast & 0x00100000)) + P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16; + switch (mast & 0x00000003) { + case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; + case 0x00000001: return clk->read(clk, nv_clk_src_dom6); + case 0x00000002: return read_pll(priv, 0x004020) >> P; + case 0x00000003: return read_pll(priv, 0x004028) >> P; + } + break; + case nv_clk_src_shader: + P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16; + switch (mast & 0x00000030) { + case 0x00000000: + if (mast & 0x00000080) + return clk->read(clk, nv_clk_src_host) >> P; + return clk->read(clk, nv_clk_src_crystal) >> P; + case 0x00000010: break; + case 0x00000020: return read_pll(priv, 0x004028) >> P; + case 0x00000030: return read_pll(priv, 0x004020) >> P; + } + break; + case nv_clk_src_mem: + P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16; + if (nv_rd32(priv, 0x004008) & 0x00000200) { + switch (mast & 0x0000c000) { + case 0x00000000: + return clk->read(clk, nv_clk_src_crystal) >> P; + case 0x00008000: + case 0x0000c000: + return clk->read(clk, nv_clk_src_href) >> P; + } + } else { + return read_pll(priv, 0x004008) >> P; + } + break; + case nv_clk_src_vdec: + P = (read_div(priv) & 0x00000700) >> 8; + switch (nv_device(priv)->chipset) { + case 0x84: + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0xa0: + switch (mast & 0x00000c00) { + case 0x00000000: + if (nv_device(priv)->chipset == 0xa0) /* wtf?? */ + return clk->read(clk, nv_clk_src_core) >> P; + return clk->read(clk, nv_clk_src_crystal) >> P; + case 0x00000400: + return 0; + case 0x00000800: + if (mast & 0x01000000) + return read_pll(priv, 0x004028) >> P; + return read_pll(priv, 0x004030) >> P; + case 0x00000c00: + return clk->read(clk, nv_clk_src_core) >> P; + } + break; + case 0x98: + switch (mast & 0x00000c00) { + case 0x00000000: + return clk->read(clk, nv_clk_src_core) >> P; + case 0x00000400: + return 0; + case 0x00000800: + return clk->read(clk, nv_clk_src_hclkm3d2) >> P; + case 0x00000c00: + return clk->read(clk, nv_clk_src_mem) >> P; + } + break; + } + break; + case nv_clk_src_dom6: + switch (nv_device(priv)->chipset) { + case 0x50: + case 0xa0: + return read_pll(priv, 0x00e810) >> 2; + case 0x84: + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0x98: + P = (read_div(priv) & 0x00000007) >> 0; + switch (mast & 0x0c000000) { + case 0x00000000: return clk->read(clk, nv_clk_src_href); + case 0x04000000: break; + case 0x08000000: return clk->read(clk, nv_clk_src_hclk); + case 0x0c000000: + return clk->read(clk, nv_clk_src_hclkm3) >> P; + } + break; + default: + break; + } + default: + break; + } + + nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); + return -EINVAL; +} + +static u32 +calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll pll; + int ret; + + ret = nvbios_pll_parse(bios, reg, &pll); + if (ret) + return 0; + + pll.vco2.max_freq = 0; + pll.refclk = read_pll_ref(priv, reg); + if (!pll.refclk) + return 0; + + return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); +} + +static inline u32 +calc_div(u32 src, u32 target, int *div) +{ + u32 clk0 = src, clk1 = src; + for (*div = 0; *div <= 7; (*div)++) { + if (clk0 <= target) { + clk1 = clk0 << (*div ? 1 : 0); + break; + } + clk0 >>= 1; + } + + if (target - clk0 <= clk1 - target) + return clk0; + (*div)--; + return clk1; +} + +static inline u32 +clk_same(u32 a, u32 b) +{ + return ((a / 1000) == (b / 1000)); +} + +static int +nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct nv50_clk_priv *priv = (void *)clk; + struct nv50_clk_hwsq *hwsq = &priv->hwsq; + const int shader = cstate->domain[nv_clk_src_shader]; + const int core = cstate->domain[nv_clk_src_core]; + const int vdec = cstate->domain[nv_clk_src_vdec]; + const int dom6 = cstate->domain[nv_clk_src_dom6]; + u32 mastm = 0, mastv = 0; + u32 divsm = 0, divsv = 0; + int N, M, P1, P2; + int freq, out; + + /* prepare a hwsq script from which we'll perform the reclock */ + out = clk_init(hwsq, nv_subdev(clk)); + if (out) + return out; + + clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ + clk_nsec(hwsq, 8000); + clk_setf(hwsq, 0x10, 0x00); /* disable fb */ + clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ + + /* vdec: avoid modifying xpll until we know exactly how the other + * clock domains work, i suspect at least some of them can also be + * tied to xpll... + */ + if (vdec) { + /* see how close we can get using nvclk as a source */ + freq = calc_div(core, vdec, &P1); + + /* see how close we can get using xpll/hclk as a source */ + if (nv_device(priv)->chipset != 0x98) + out = read_pll(priv, 0x004030); + else + out = clk->read(clk, nv_clk_src_hclkm3d2); + out = calc_div(out, vdec, &P2); + + /* select whichever gets us closest */ + if (abs(vdec - freq) <= abs(vdec - out)) { + if (nv_device(priv)->chipset != 0x98) + mastv |= 0x00000c00; + divsv |= P1 << 8; + } else { + mastv |= 0x00000800; + divsv |= P2 << 8; + } + + mastm |= 0x00000c00; + divsm |= 0x00000700; + } + + /* dom6: nfi what this is, but we're limited to various combinations + * of the host clock frequency + */ + if (dom6) { + if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { + mastv |= 0x00000000; + } else + if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { + mastv |= 0x08000000; + } else { + freq = clk->read(clk, nv_clk_src_hclk) * 3; + freq = calc_div(freq, dom6, &P1); + + mastv |= 0x0c000000; + divsv |= P1; + } + + mastm |= 0x0c000000; + divsm |= 0x00000007; + } + + /* vdec/dom6: switch to "safe" clocks temporarily, update dividers + * and then switch to target clocks + */ + clk_mask(hwsq, mast, mastm, 0x00000000); + clk_mask(hwsq, divs, divsm, divsv); + clk_mask(hwsq, mast, mastm, mastv); + + /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, + * sclk to hclk) before reprogramming + */ + if (nv_device(priv)->chipset < 0x92) + clk_mask(hwsq, mast, 0x001000b0, 0x00100080); + else + clk_mask(hwsq, mast, 0x000000b3, 0x00000081); + + /* core: for the moment at least, always use nvpll */ + freq = calc_pll(priv, 0x4028, core, &N, &M, &P1); + if (freq == 0) + return -ERANGE; + + clk_mask(hwsq, nvpll[0], 0xc03f0100, + 0x80000000 | (P1 << 19) | (P1 << 16)); + clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); + + /* shader: tie to nvclk if possible, otherwise use spll. have to be + * very careful that the shader clock is at least twice the core, or + * some chipsets will be very unhappy. i expect most or all of these + * cases will be handled by tying to nvclk, but it's possible there's + * corners + */ + if (P1-- && shader == (core << 1)) { + clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); + clk_mask(hwsq, mast, 0x00100033, 0x00000023); + } else { + freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1); + if (freq == 0) + return -ERANGE; + + clk_mask(hwsq, spll[0], 0xc03f0100, + 0x80000000 | (P1 << 19) | (P1 << 16)); + clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); + clk_mask(hwsq, mast, 0x00100033, 0x00000033); + } + + /* restore normal operation */ + clk_setf(hwsq, 0x10, 0x01); /* enable fb */ + clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ + clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ + return 0; +} + +static int +nv50_clk_prog(struct nouveau_clk *clk) +{ + struct nv50_clk_priv *priv = (void *)clk; + return clk_exec(&priv->hwsq, true); +} + +static void +nv50_clk_tidy(struct nouveau_clk *clk) +{ + struct nv50_clk_priv *priv = (void *)clk; + clk_exec(&priv->hwsq, false); +} + +int +nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_clk_oclass *pclass = (void *)oclass; + struct nv50_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, pclass->domains, + NULL, 0, false, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->hwsq.r_fifo = hwsq_reg(0x002504); + priv->hwsq.r_spll[0] = hwsq_reg(0x004020); + priv->hwsq.r_spll[1] = hwsq_reg(0x004024); + priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028); + priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); + switch (nv_device(priv)->chipset) { + case 0x92: + case 0x94: + case 0x96: + priv->hwsq.r_divs = hwsq_reg(0x004800); + break; + default: + priv->hwsq.r_divs = hwsq_reg(0x004700); + break; + } + priv->hwsq.r_mast = hwsq_reg(0x00c040); + + priv->base.read = nv50_clk_read; + priv->base.calc = nv50_clk_calc; + priv->base.prog = nv50_clk_prog; + priv->base.tidy = nv50_clk_tidy; + return 0; +} + +static struct nouveau_domain +nv50_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_href , 0xff }, + { nv_clk_src_core , 0xff, 0, "core", 1000 }, + { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, + { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, + { nv_clk_src_max } +}; + +struct nouveau_oclass * +nv50_clk_oclass = &(struct nv50_clk_oclass) { + .base.handle = NV_SUBDEV(CLK, 0x50), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, + .domains = nv50_domains, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h new file mode 100644 index 000000000000..ae6421fd28f4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h @@ -0,0 +1,31 @@ +#ifndef __NVKM_CLK_NV50_H__ +#define __NVKM_CLK_NV50_H__ + +#include +#include +#include + +struct nv50_clk_hwsq { + struct hwsq base; + struct hwsq_reg r_fifo; + struct hwsq_reg r_spll[2]; + struct hwsq_reg r_nvpll[2]; + struct hwsq_reg r_divs; + struct hwsq_reg r_mast; +}; + +struct nv50_clk_priv { + struct nouveau_clk base; + struct nv50_clk_hwsq hwsq; +}; + +int nv50_clk_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); + +struct nv50_clk_oclass { + struct nouveau_oclass base; + struct nouveau_domain *domains; +}; + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c new file mode 100644 index 000000000000..b5b00b3df6c4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c @@ -0,0 +1,48 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nv50.h" + +static struct nouveau_domain +nv84_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_href , 0xff }, + { nv_clk_src_core , 0xff, 0, "core", 1000 }, + { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, + { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, + { nv_clk_src_vdec , 0xff }, + { nv_clk_src_max } +}; + +struct nouveau_oclass * +nv84_clk_oclass = &(struct nv50_clk_oclass) { + .base.handle = NV_SUBDEV(CLK, 0x84), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, + .domains = nv84_domains, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c new file mode 100644 index 000000000000..3002c60a3993 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c @@ -0,0 +1,534 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + * Roy Spliet + */ + +#include +#include +#include +#include + +#include "pll.h" + +#include "nva3.h" + +struct nva3_clk_priv { + struct nouveau_clk base; + struct nva3_clk_info eng[nv_clk_src_max]; +}; + +static u32 read_clk(struct nva3_clk_priv *, int, bool); +static u32 read_pll(struct nva3_clk_priv *, int, u32); + +static u32 +read_vco(struct nva3_clk_priv *priv, int clk) +{ + u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); + + switch (sctl & 0x00000030) { + case 0x00000000: + return nv_device(priv)->crystal; + case 0x00000020: + return read_pll(priv, 0x41, 0x00e820); + case 0x00000030: + return read_pll(priv, 0x42, 0x00e8a0); + default: + return 0; + } +} + +static u32 +read_clk(struct nva3_clk_priv *priv, int clk, bool ignore_en) +{ + u32 sctl, sdiv, sclk; + + /* refclk for the 0xe8xx plls is a fixed frequency */ + if (clk >= 0x40) { + if (nv_device(priv)->chipset == 0xaf) { + /* no joke.. seriously.. sigh.. */ + return nv_rd32(priv, 0x00471c) * 1000; + } + + return nv_device(priv)->crystal; + } + + sctl = nv_rd32(priv, 0x4120 + (clk * 4)); + if (!ignore_en && !(sctl & 0x00000100)) + return 0; + + /* out_alt */ + if (sctl & 0x00000400) + return 108000; + + /* vco_out */ + switch (sctl & 0x00003000) { + case 0x00000000: + if (!(sctl & 0x00000200)) + return nv_device(priv)->crystal; + return 0; + case 0x00002000: + if (sctl & 0x00000040) + return 108000; + return 100000; + case 0x00003000: + /* vco_enable */ + if (!(sctl & 0x00000001)) + return 0; + + sclk = read_vco(priv, clk); + sdiv = ((sctl & 0x003f0000) >> 16) + 2; + return (sclk * 2) / sdiv; + default: + return 0; + } +} + +static u32 +read_pll(struct nva3_clk_priv *priv, int clk, u32 pll) +{ + u32 ctrl = nv_rd32(priv, pll + 0); + u32 sclk = 0, P = 1, N = 1, M = 1; + + if (!(ctrl & 0x00000008)) { + if (ctrl & 0x00000001) { + u32 coef = nv_rd32(priv, pll + 4); + M = (coef & 0x000000ff) >> 0; + N = (coef & 0x0000ff00) >> 8; + P = (coef & 0x003f0000) >> 16; + + /* no post-divider on these.. + * XXX: it looks more like two post-"dividers" that + * cross each other out in the default RPLL config */ + if ((pll & 0x00ff00) == 0x00e800) + P = 1; + + sclk = read_clk(priv, 0x00 + clk, false); + } + } else { + sclk = read_clk(priv, 0x10 + clk, false); + } + + if (M * P) + return sclk * N / (M * P); + return 0; +} + +static int +nva3_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct nva3_clk_priv *priv = (void *)clk; + u32 hsrc; + + switch (src) { + case nv_clk_src_crystal: + return nv_device(priv)->crystal; + case nv_clk_src_core: + case nv_clk_src_core_intm: + return read_pll(priv, 0x00, 0x4200); + case nv_clk_src_shader: + return read_pll(priv, 0x01, 0x4220); + case nv_clk_src_mem: + return read_pll(priv, 0x02, 0x4000); + case nv_clk_src_disp: + return read_clk(priv, 0x20, false); + case nv_clk_src_vdec: + return read_clk(priv, 0x21, false); + case nv_clk_src_daemon: + return read_clk(priv, 0x25, false); + case nv_clk_src_host: + hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; + switch (hsrc) { + case 0: + return read_clk(priv, 0x1d, false); + case 2: + case 3: + return 277000; + default: + nv_error(clk, "unknown HOST clock source %d\n", hsrc); + return -EINVAL; + } + default: + nv_error(clk, "invalid clock source %d\n", src); + return -EINVAL; + } + + return 0; +} + +int +nva3_clk_info(struct nouveau_clk *clock, int clk, u32 khz, + struct nva3_clk_info *info) +{ + struct nva3_clk_priv *priv = (void *)clock; + u32 oclk, sclk, sdiv, diff; + + info->clk = 0; + + switch (khz) { + case 27000: + info->clk = 0x00000100; + return khz; + case 100000: + info->clk = 0x00002100; + return khz; + case 108000: + info->clk = 0x00002140; + return khz; + default: + sclk = read_vco(priv, clk); + sdiv = min((sclk * 2) / khz, (u32)65); + oclk = (sclk * 2) / sdiv; + diff = ((khz + 3000) - oclk); + + /* When imprecise, play it safe and aim for a clock lower than + * desired rather than higher */ + if (diff < 0) { + sdiv++; + oclk = (sclk * 2) / sdiv; + } + + /* divider can go as low as 2, limited here because NVIDIA + * and the VBIOS on my NVA8 seem to prefer using the PLL + * for 810MHz - is there a good reason? + * XXX: PLLs with refclk 810MHz? */ + if (sdiv > 4) { + info->clk = (((sdiv - 2) << 16) | 0x00003100); + return oclk; + } + + break; + } + + return -ERANGE; +} + +int +nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz, + struct nva3_clk_info *info) +{ + struct nouveau_bios *bios = nouveau_bios(clock); + struct nva3_clk_priv *priv = (void *)clock; + struct nvbios_pll limits; + int P, N, M, diff; + int ret; + + info->pll = 0; + + /* If we can get a within [-2, 3) MHz of a divider, we'll disable the + * PLL and use the divider instead. */ + ret = nva3_clk_info(clock, clk, khz, info); + diff = khz - ret; + if (!pll || (diff >= -2000 && diff < 3000)) { + goto out; + } + + /* Try with PLL */ + ret = nvbios_pll_parse(bios, pll, &limits); + if (ret) + return ret; + + ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); + if (ret != limits.refclk) + return -EINVAL; + + ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); + if (ret >= 0) { + info->pll = (P << 16) | (N << 8) | M; + } + +out: + info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); + + return ret ? ret : -ERANGE; +} + +static int +calc_clk(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate, + int clk, u32 pll, int idx) +{ + int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], + &priv->eng[idx]); + if (ret >= 0) + return 0; + return ret; +} + +static int +calc_host(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate) +{ + int ret = 0; + u32 kHz = cstate->domain[nv_clk_src_host]; + struct nva3_clk_info *info = &priv->eng[nv_clk_src_host]; + + if (kHz == 277000) { + info->clk = 0; + info->host_out = NVA3_HOST_277; + return 0; + } + + info->host_out = NVA3_HOST_CLK; + + ret = nva3_clk_info(&priv->base, 0x1d, kHz, info); + if (ret >= 0) + return 0; + return ret; +} + +int +nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(clk); + + /* halt and idle execution engines */ + nv_mask(clk, 0x020060, 0x00070000, 0x00000000); + nv_mask(clk, 0x002504, 0x00000001, 0x00000001); + /* Wait until the interrupt handler is finished */ + if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) + return -EBUSY; + + if (pfifo) + pfifo->pause(pfifo, flags); + + if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) + return -EIO; + if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) + return -EIO; + + return 0; +} + +void +nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(clk); + + if (pfifo && flags) + pfifo->start(pfifo, flags); + + nv_mask(clk, 0x002504, 0x00000001, 0x00000000); + nv_mask(clk, 0x020060, 0x00070000, 0x00040000); +} + +static void +disable_clk_src(struct nva3_clk_priv *priv, u32 src) +{ + nv_mask(priv, src, 0x00000100, 0x00000000); + nv_mask(priv, src, 0x00000001, 0x00000000); +} + +static void +prog_pll(struct nva3_clk_priv *priv, int clk, u32 pll, int idx) +{ + struct nva3_clk_info *info = &priv->eng[idx]; + const u32 src0 = 0x004120 + (clk * 4); + const u32 src1 = 0x004160 + (clk * 4); + const u32 ctrl = pll + 0; + const u32 coef = pll + 4; + u32 bypass; + + if (info->pll) { + /* Always start from a non-PLL clock */ + bypass = nv_rd32(priv, ctrl) & 0x00000008; + if (!bypass) { + nv_mask(priv, src1, 0x00000101, 0x00000101); + nv_mask(priv, ctrl, 0x00000008, 0x00000008); + udelay(20); + } + + nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); + nv_wr32(priv, coef, info->pll); + nv_mask(priv, ctrl, 0x00000015, 0x00000015); + nv_mask(priv, ctrl, 0x00000010, 0x00000000); + if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { + nv_mask(priv, ctrl, 0x00000010, 0x00000010); + nv_mask(priv, src0, 0x00000101, 0x00000000); + return; + } + nv_mask(priv, ctrl, 0x00000010, 0x00000010); + nv_mask(priv, ctrl, 0x00000008, 0x00000000); + disable_clk_src(priv, src1); + } else { + nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); + nv_mask(priv, ctrl, 0x00000018, 0x00000018); + udelay(20); + nv_mask(priv, ctrl, 0x00000001, 0x00000000); + disable_clk_src(priv, src0); + } +} + +static void +prog_clk(struct nva3_clk_priv *priv, int clk, int idx) +{ + struct nva3_clk_info *info = &priv->eng[idx]; + nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); +} + +static void +prog_host(struct nva3_clk_priv *priv) +{ + struct nva3_clk_info *info = &priv->eng[nv_clk_src_host]; + u32 hsrc = (nv_rd32(priv, 0xc040)); + + switch (info->host_out) { + case NVA3_HOST_277: + if ((hsrc & 0x30000000) == 0) { + nv_wr32(priv, 0xc040, hsrc | 0x20000000); + disable_clk_src(priv, 0x4194); + } + break; + case NVA3_HOST_CLK: + prog_clk(priv, 0x1d, nv_clk_src_host); + if ((hsrc & 0x30000000) >= 0x20000000) { + nv_wr32(priv, 0xc040, hsrc & ~0x30000000); + } + break; + default: + break; + } + + /* This seems to be a clock gating factor on idle, always set to 64 */ + nv_wr32(priv, 0xc044, 0x3e); +} + +static void +prog_core(struct nva3_clk_priv *priv, int idx) +{ + struct nva3_clk_info *info = &priv->eng[idx]; + u32 fb_delay = nv_rd32(priv, 0x10002c); + + if (fb_delay < info->fb_delay) + nv_wr32(priv, 0x10002c, info->fb_delay); + + prog_pll(priv, 0x00, 0x004200, idx); + + if (fb_delay > info->fb_delay) + nv_wr32(priv, 0x10002c, info->fb_delay); +} + +static int +nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct nva3_clk_priv *priv = (void *)clk; + struct nva3_clk_info *core = &priv->eng[nv_clk_src_core]; + int ret; + + if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || + (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || + (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || + (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || + (ret = calc_host(priv, cstate))) + return ret; + + /* XXX: Should be reading the highest bit in the VBIOS clock to decide + * whether to use a PLL or not... but using a PLL defeats the purpose */ + if (core->pll) { + ret = nva3_clk_info(clk, 0x10, + cstate->domain[nv_clk_src_core_intm], + &priv->eng[nv_clk_src_core_intm]); + if (ret < 0) + return ret; + } + + return 0; +} + +static int +nva3_clk_prog(struct nouveau_clk *clk) +{ + struct nva3_clk_priv *priv = (void *)clk; + struct nva3_clk_info *core = &priv->eng[nv_clk_src_core]; + int ret = 0; + unsigned long flags; + unsigned long *f = &flags; + + ret = nva3_clk_pre(clk, f); + if (ret) + goto out; + + if (core->pll) + prog_core(priv, nv_clk_src_core_intm); + + prog_core(priv, nv_clk_src_core); + prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); + prog_clk(priv, 0x20, nv_clk_src_disp); + prog_clk(priv, 0x21, nv_clk_src_vdec); + prog_host(priv); + +out: + if (ret == -EBUSY) + f = NULL; + + nva3_clk_post(clk, f); + + return ret; +} + +static void +nva3_clk_tidy(struct nouveau_clk *clk) +{ +} + +static struct nouveau_domain +nva3_domain[] = { + { nv_clk_src_crystal , 0xff }, + { nv_clk_src_core , 0x00, 0, "core", 1000 }, + { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, + { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, + { nv_clk_src_vdec , 0x03 }, + { nv_clk_src_disp , 0x04 }, + { nv_clk_src_host , 0x05 }, + { nv_clk_src_core_intm, 0x06 }, + { nv_clk_src_max } +}; + +static int +nva3_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nva3_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, nva3_domain, NULL, 0, + true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.read = nva3_clk_read; + priv->base.calc = nva3_clk_calc; + priv->base.prog = nva3_clk_prog; + priv->base.tidy = nva3_clk_tidy; + return 0; +} + +struct nouveau_oclass +nva3_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xa3), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nva3_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h new file mode 100644 index 000000000000..ce0fc83345e3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h @@ -0,0 +1,20 @@ +#ifndef __NVKM_CLK_NVA3_H__ +#define __NVKM_CLK_NVA3_H__ + +#include + +struct nva3_clk_info { + u32 clk; + u32 pll; + enum { + NVA3_HOST_277, + NVA3_HOST_CLK, + } host_out; + u32 fb_delay; +}; + +int nva3_pll_info(struct nouveau_clk *, int, u32, u32, + struct nva3_clk_info *); +int nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags); +void nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c new file mode 100644 index 000000000000..d6d2bd190144 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c @@ -0,0 +1,435 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include +#include + +#include "nva3.h" +#include "pll.h" + +struct nvaa_clk_priv { + struct nouveau_clk base; + enum nv_clk_src csrc, ssrc, vsrc; + u32 cctrl, sctrl; + u32 ccoef, scoef; + u32 cpost, spost; + u32 vdiv; +}; + +static u32 +read_div(struct nouveau_clk *clk) +{ + return nv_rd32(clk, 0x004600); +} + +static u32 +read_pll(struct nouveau_clk *clk, u32 base) +{ + u32 ctrl = nv_rd32(clk, base + 0); + u32 coef = nv_rd32(clk, base + 4); + u32 ref = clk->read(clk, nv_clk_src_href); + u32 post_div = 0; + u32 clock = 0; + int N1, M1; + + switch (base){ + case 0x4020: + post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); + break; + case 0x4028: + post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; + break; + default: + break; + } + + N1 = (coef & 0x0000ff00) >> 8; + M1 = (coef & 0x000000ff); + if ((ctrl & 0x80000000) && M1) { + clock = ref * N1 / M1; + clock = clock / post_div; + } + + return clock; +} + +static int +nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct nvaa_clk_priv *priv = (void *)clk; + u32 mast = nv_rd32(clk, 0x00c054); + u32 P = 0; + + switch (src) { + case nv_clk_src_crystal: + return nv_device(priv)->crystal; + case nv_clk_src_href: + return 100000; /* PCIE reference clock */ + case nv_clk_src_hclkm4: + return clk->read(clk, nv_clk_src_href) * 4; + case nv_clk_src_hclkm2d3: + return clk->read(clk, nv_clk_src_href) * 2 / 3; + case nv_clk_src_host: + switch (mast & 0x000c0000) { + case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3); + case 0x00040000: break; + case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4); + case 0x000c0000: return clk->read(clk, nv_clk_src_cclk); + } + break; + case nv_clk_src_core: + P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; + + switch (mast & 0x00000003) { + case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; + case 0x00000001: return 0; + case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P; + case 0x00000003: return read_pll(clk, 0x004028) >> P; + } + break; + case nv_clk_src_cclk: + if ((mast & 0x03000000) != 0x03000000) + return clk->read(clk, nv_clk_src_core); + + if ((mast & 0x00000200) == 0x00000000) + return clk->read(clk, nv_clk_src_core); + + switch (mast & 0x00000c00) { + case 0x00000000: return clk->read(clk, nv_clk_src_href); + case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4); + case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3); + default: return 0; + } + case nv_clk_src_shader: + P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; + switch (mast & 0x00000030) { + case 0x00000000: + if (mast & 0x00000040) + return clk->read(clk, nv_clk_src_href) >> P; + return clk->read(clk, nv_clk_src_crystal) >> P; + case 0x00000010: break; + case 0x00000020: return read_pll(clk, 0x004028) >> P; + case 0x00000030: return read_pll(clk, 0x004020) >> P; + } + break; + case nv_clk_src_mem: + return 0; + break; + case nv_clk_src_vdec: + P = (read_div(clk) & 0x00000700) >> 8; + + switch (mast & 0x00400000) { + case 0x00400000: + return clk->read(clk, nv_clk_src_core) >> P; + break; + default: + return 500000 >> P; + break; + } + break; + default: + break; + } + + nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); + return 0; +} + +static u32 +calc_pll(struct nvaa_clk_priv *priv, u32 reg, + u32 clock, int *N, int *M, int *P) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll pll; + struct nouveau_clk *clk = &priv->base; + int ret; + + ret = nvbios_pll_parse(bios, reg, &pll); + if (ret) + return 0; + + pll.vco2.max_freq = 0; + pll.refclk = clk->read(clk, nv_clk_src_href); + if (!pll.refclk) + return 0; + + return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); +} + +static inline u32 +calc_P(u32 src, u32 target, int *div) +{ + u32 clk0 = src, clk1 = src; + for (*div = 0; *div <= 7; (*div)++) { + if (clk0 <= target) { + clk1 = clk0 << (*div ? 1 : 0); + break; + } + clk0 >>= 1; + } + + if (target - clk0 <= clk1 - target) + return clk0; + (*div)--; + return clk1; +} + +static int +nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct nvaa_clk_priv *priv = (void *)clk; + const int shader = cstate->domain[nv_clk_src_shader]; + const int core = cstate->domain[nv_clk_src_core]; + const int vdec = cstate->domain[nv_clk_src_vdec]; + u32 out = 0, clock = 0; + int N, M, P1, P2 = 0; + int divs = 0; + + /* cclk: find suitable source, disable PLL if we can */ + if (core < clk->read(clk, nv_clk_src_hclkm4)) + out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs); + + /* Calculate clock * 2, so shader clock can use it too */ + clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1); + + if (abs(core - out) <= + abs(core - (clock >> 1))) { + priv->csrc = nv_clk_src_hclkm4; + priv->cctrl = divs << 16; + } else { + /* NVCTRL is actually used _after_ NVPOST, and after what we + * call NVPLL. To make matters worse, NVPOST is an integer + * divider instead of a right-shift number. */ + if(P1 > 2) { + P2 = P1 - 2; + P1 = 2; + } + + priv->csrc = nv_clk_src_core; + priv->ccoef = (N << 8) | M; + + priv->cctrl = (P2 + 1) << 16; + priv->cpost = (1 << P1) << 16; + } + + /* sclk: nvpll + divisor, href or spll */ + out = 0; + if (shader == clk->read(clk, nv_clk_src_href)) { + priv->ssrc = nv_clk_src_href; + } else { + clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1); + if (priv->csrc == nv_clk_src_core) { + out = calc_P((core << 1), shader, &divs); + } + + if (abs(shader - out) <= + abs(shader - clock) && + (divs + P2) <= 7) { + priv->ssrc = nv_clk_src_core; + priv->sctrl = (divs + P2) << 16; + } else { + priv->ssrc = nv_clk_src_shader; + priv->scoef = (N << 8) | M; + priv->sctrl = P1 << 16; + } + } + + /* vclk */ + out = calc_P(core, vdec, &divs); + clock = calc_P(500000, vdec, &P1); + if(abs(vdec - out) <= + abs(vdec - clock)) { + priv->vsrc = nv_clk_src_cclk; + priv->vdiv = divs << 16; + } else { + priv->vsrc = nv_clk_src_vdec; + priv->vdiv = P1 << 16; + } + + /* Print strategy! */ + nv_debug(priv, "nvpll: %08x %08x %08x\n", + priv->ccoef, priv->cpost, priv->cctrl); + nv_debug(priv, " spll: %08x %08x %08x\n", + priv->scoef, priv->spost, priv->sctrl); + nv_debug(priv, " vdiv: %08x\n", priv->vdiv); + if (priv->csrc == nv_clk_src_hclkm4) + nv_debug(priv, "core: hrefm4\n"); + else + nv_debug(priv, "core: nvpll\n"); + + if (priv->ssrc == nv_clk_src_hclkm4) + nv_debug(priv, "shader: hrefm4\n"); + else if (priv->ssrc == nv_clk_src_core) + nv_debug(priv, "shader: nvpll\n"); + else + nv_debug(priv, "shader: spll\n"); + + if (priv->vsrc == nv_clk_src_hclkm4) + nv_debug(priv, "vdec: 500MHz\n"); + else + nv_debug(priv, "vdec: core\n"); + + return 0; +} + +static int +nvaa_clk_prog(struct nouveau_clk *clk) +{ + struct nvaa_clk_priv *priv = (void *)clk; + u32 pllmask = 0, mast; + unsigned long flags; + unsigned long *f = &flags; + int ret = 0; + + ret = nva3_clk_pre(clk, f); + if (ret) + goto out; + + /* First switch to safe clocks: href */ + mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); + mast &= ~0x00400e73; + mast |= 0x03000000; + + switch (priv->csrc) { + case nv_clk_src_hclkm4: + nv_mask(clk, 0x4028, 0x00070000, priv->cctrl); + mast |= 0x00000002; + break; + case nv_clk_src_core: + nv_wr32(clk, 0x402c, priv->ccoef); + nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl); + nv_wr32(clk, 0x4040, priv->cpost); + pllmask |= (0x3 << 8); + mast |= 0x00000003; + break; + default: + nv_warn(priv,"Reclocking failed: unknown core clock\n"); + goto resume; + } + + switch (priv->ssrc) { + case nv_clk_src_href: + nv_mask(clk, 0x4020, 0x00070000, 0x00000000); + /* mast |= 0x00000000; */ + break; + case nv_clk_src_core: + nv_mask(clk, 0x4020, 0x00070000, priv->sctrl); + mast |= 0x00000020; + break; + case nv_clk_src_shader: + nv_wr32(clk, 0x4024, priv->scoef); + nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl); + nv_wr32(clk, 0x4070, priv->spost); + pllmask |= (0x3 << 12); + mast |= 0x00000030; + break; + default: + nv_warn(priv,"Reclocking failed: unknown sclk clock\n"); + goto resume; + } + + if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { + nv_warn(priv,"Reclocking failed: unstable PLLs\n"); + goto resume; + } + + switch (priv->vsrc) { + case nv_clk_src_cclk: + mast |= 0x00400000; + default: + nv_wr32(clk, 0x4600, priv->vdiv); + } + + nv_wr32(clk, 0xc054, mast); + +resume: + /* Disable some PLLs and dividers when unused */ + if (priv->csrc != nv_clk_src_core) { + nv_wr32(clk, 0x4040, 0x00000000); + nv_mask(clk, 0x4028, 0x80000000, 0x00000000); + } + + if (priv->ssrc != nv_clk_src_shader) { + nv_wr32(clk, 0x4070, 0x00000000); + nv_mask(clk, 0x4020, 0x80000000, 0x00000000); + } + +out: + if (ret == -EBUSY) + f = NULL; + + nva3_clk_post(clk, f); + + return ret; +} + +static void +nvaa_clk_tidy(struct nouveau_clk *clk) +{ +} + +static struct nouveau_domain +nvaa_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_href , 0xff }, + { nv_clk_src_core , 0xff, 0, "core", 1000 }, + { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, + { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 }, + { nv_clk_src_max } +}; + +static int +nvaa_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvaa_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, nvaa_domains, NULL, + 0, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.read = nvaa_clk_read; + priv->base.calc = nvaa_clk_calc; + priv->base.prog = nvaa_clk_prog; + priv->base.tidy = nvaa_clk_tidy; + return 0; +} + +struct nouveau_oclass * +nvaa_clk_oclass = &(struct nouveau_oclass) { + .handle = NV_SUBDEV(CLK, 0xaa), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvaa_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c new file mode 100644 index 000000000000..791a9f5198eb --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c @@ -0,0 +1,462 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include + +#include "pll.h" + +struct nvc0_clk_info { + u32 freq; + u32 ssel; + u32 mdiv; + u32 dsrc; + u32 ddiv; + u32 coef; +}; + +struct nvc0_clk_priv { + struct nouveau_clk base; + struct nvc0_clk_info eng[16]; +}; + +static u32 read_div(struct nvc0_clk_priv *, int, u32, u32); + +static u32 +read_vco(struct nvc0_clk_priv *priv, u32 dsrc) +{ + struct nouveau_clk *clk = &priv->base; + u32 ssrc = nv_rd32(priv, dsrc); + if (!(ssrc & 0x00000100)) + return clk->read(clk, nv_clk_src_sppll0); + return clk->read(clk, nv_clk_src_sppll1); +} + +static u32 +read_pll(struct nvc0_clk_priv *priv, u32 pll) +{ + struct nouveau_clk *clk = &priv->base; + u32 ctrl = nv_rd32(priv, pll + 0x00); + u32 coef = nv_rd32(priv, pll + 0x04); + u32 P = (coef & 0x003f0000) >> 16; + u32 N = (coef & 0x0000ff00) >> 8; + u32 M = (coef & 0x000000ff) >> 0; + u32 sclk; + + if (!(ctrl & 0x00000001)) + return 0; + + switch (pll) { + case 0x00e800: + case 0x00e820: + sclk = nv_device(priv)->crystal; + P = 1; + break; + case 0x132000: + sclk = clk->read(clk, nv_clk_src_mpllsrc); + break; + case 0x132020: + sclk = clk->read(clk, nv_clk_src_mpllsrcref); + break; + case 0x137000: + case 0x137020: + case 0x137040: + case 0x1370e0: + sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); + break; + default: + return 0; + } + + return sclk * N / M / P; +} + +static u32 +read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl) +{ + u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); + u32 sctl = nv_rd32(priv, dctl + (doff * 4)); + + switch (ssrc & 0x00000003) { + case 0: + if ((ssrc & 0x00030000) != 0x00030000) + return nv_device(priv)->crystal; + return 108000; + case 2: + return 100000; + case 3: + if (sctl & 0x80000000) { + u32 sclk = read_vco(priv, dsrc + (doff * 4)); + u32 sdiv = (sctl & 0x0000003f) + 2; + return (sclk * 2) / sdiv; + } + + return read_vco(priv, dsrc + (doff * 4)); + default: + return 0; + } +} + +static u32 +read_clk(struct nvc0_clk_priv *priv, int clk) +{ + u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); + u32 ssel = nv_rd32(priv, 0x137100); + u32 sclk, sdiv; + + if (ssel & (1 << clk)) { + if (clk < 7) + sclk = read_pll(priv, 0x137000 + (clk * 0x20)); + else + sclk = read_pll(priv, 0x1370e0); + sdiv = ((sctl & 0x00003f00) >> 8) + 2; + } else { + sclk = read_div(priv, clk, 0x137160, 0x1371d0); + sdiv = ((sctl & 0x0000003f) >> 0) + 2; + } + + if (sctl & 0x80000000) + return (sclk * 2) / sdiv; + + return sclk; +} + +static int +nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct nouveau_device *device = nv_device(clk); + struct nvc0_clk_priv *priv = (void *)clk; + + switch (src) { + case nv_clk_src_crystal: + return device->crystal; + case nv_clk_src_href: + return 100000; + case nv_clk_src_sppll0: + return read_pll(priv, 0x00e800); + case nv_clk_src_sppll1: + return read_pll(priv, 0x00e820); + + case nv_clk_src_mpllsrcref: + return read_div(priv, 0, 0x137320, 0x137330); + case nv_clk_src_mpllsrc: + return read_pll(priv, 0x132020); + case nv_clk_src_mpll: + return read_pll(priv, 0x132000); + case nv_clk_src_mdiv: + return read_div(priv, 0, 0x137300, 0x137310); + case nv_clk_src_mem: + if (nv_rd32(priv, 0x1373f0) & 0x00000002) + return clk->read(clk, nv_clk_src_mpll); + return clk->read(clk, nv_clk_src_mdiv); + + case nv_clk_src_gpc: + return read_clk(priv, 0x00); + case nv_clk_src_rop: + return read_clk(priv, 0x01); + case nv_clk_src_hubk07: + return read_clk(priv, 0x02); + case nv_clk_src_hubk06: + return read_clk(priv, 0x07); + case nv_clk_src_hubk01: + return read_clk(priv, 0x08); + case nv_clk_src_copy: + return read_clk(priv, 0x09); + case nv_clk_src_daemon: + return read_clk(priv, 0x0c); + case nv_clk_src_vdec: + return read_clk(priv, 0x0e); + default: + nv_error(clk, "invalid clock source %d\n", src); + return -EINVAL; + } +} + +static u32 +calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) +{ + u32 div = min((ref * 2) / freq, (u32)65); + if (div < 2) + div = 2; + + *ddiv = div - 2; + return (ref * 2) / div; +} + +static u32 +calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) +{ + u32 sclk; + + /* use one of the fixed frequencies if possible */ + *ddiv = 0x00000000; + switch (freq) { + case 27000: + case 108000: + *dsrc = 0x00000000; + if (freq == 108000) + *dsrc |= 0x00030000; + return freq; + case 100000: + *dsrc = 0x00000002; + return freq; + default: + *dsrc = 0x00000003; + break; + } + + /* otherwise, calculate the closest divider */ + sclk = read_vco(priv, 0x137160 + (clk * 4)); + if (clk < 7) + sclk = calc_div(priv, clk, sclk, freq, ddiv); + return sclk; +} + +static u32 +calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll limits; + int N, M, P, ret; + + ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); + if (ret) + return 0; + + limits.refclk = read_div(priv, clk, 0x137120, 0x137140); + if (!limits.refclk) + return 0; + + ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); + if (ret <= 0) + return 0; + + *coef = (P << 16) | (N << 8) | M; + return ret; +} + +static int +calc_clk(struct nvc0_clk_priv *priv, + struct nouveau_cstate *cstate, int clk, int dom) +{ + struct nvc0_clk_info *info = &priv->eng[clk]; + u32 freq = cstate->domain[dom]; + u32 src0, div0, div1D, div1P = 0; + u32 clk0, clk1 = 0; + + /* invalid clock domain */ + if (!freq) + return 0; + + /* first possible path, using only dividers */ + clk0 = calc_src(priv, clk, freq, &src0, &div0); + clk0 = calc_div(priv, clk, clk0, freq, &div1D); + + /* see if we can get any closer using PLLs */ + if (clk0 != freq && (0x00004387 & (1 << clk))) { + if (clk <= 7) + clk1 = calc_pll(priv, clk, freq, &info->coef); + else + clk1 = cstate->domain[nv_clk_src_hubk06]; + clk1 = calc_div(priv, clk, clk1, freq, &div1P); + } + + /* select the method which gets closest to target freq */ + if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { + info->dsrc = src0; + if (div0) { + info->ddiv |= 0x80000000; + info->ddiv |= div0 << 8; + info->ddiv |= div0; + } + if (div1D) { + info->mdiv |= 0x80000000; + info->mdiv |= div1D; + } + info->ssel = info->coef = 0; + info->freq = clk0; + } else { + if (div1P) { + info->mdiv |= 0x80000000; + info->mdiv |= div1P << 8; + } + info->ssel = (1 << clk); + info->freq = clk1; + } + + return 0; +} + +static int +nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct nvc0_clk_priv *priv = (void *)clk; + int ret; + + if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || + (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || + (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || + (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || + (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || + (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) || + (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || + (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) + return ret; + + return 0; +} + +static void +nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk) +{ + struct nvc0_clk_info *info = &priv->eng[clk]; + if (clk < 7 && !info->ssel) { + nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); + nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); + } +} + +static void +nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk) +{ + nv_mask(priv, 0x137100, (1 << clk), 0x00000000); + nv_wait(priv, 0x137100, (1 << clk), 0x00000000); +} + +static void +nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk) +{ + struct nvc0_clk_info *info = &priv->eng[clk]; + const u32 addr = 0x137000 + (clk * 0x20); + if (clk <= 7) { + nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); + nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); + if (info->coef) { + nv_wr32(priv, addr + 0x04, info->coef); + nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); + nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); + nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); + } + } +} + +static void +nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk) +{ + struct nvc0_clk_info *info = &priv->eng[clk]; + if (info->ssel) { + nv_mask(priv, 0x137100, (1 << clk), info->ssel); + nv_wait(priv, 0x137100, (1 << clk), info->ssel); + } +} + +static void +nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk) +{ + struct nvc0_clk_info *info = &priv->eng[clk]; + nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); +} + +static int +nvc0_clk_prog(struct nouveau_clk *clk) +{ + struct nvc0_clk_priv *priv = (void *)clk; + struct { + void (*exec)(struct nvc0_clk_priv *, int); + } stage[] = { + { nvc0_clk_prog_0 }, /* div programming */ + { nvc0_clk_prog_1 }, /* select div mode */ + { nvc0_clk_prog_2 }, /* (maybe) program pll */ + { nvc0_clk_prog_3 }, /* (maybe) select pll mode */ + { nvc0_clk_prog_4 }, /* final divider */ + }; + int i, j; + + for (i = 0; i < ARRAY_SIZE(stage); i++) { + for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { + if (!priv->eng[j].freq) + continue; + stage[i].exec(priv, j); + } + } + + return 0; +} + +static void +nvc0_clk_tidy(struct nouveau_clk *clk) +{ + struct nvc0_clk_priv *priv = (void *)clk; + memset(priv->eng, 0x00, sizeof(priv->eng)); +} + +static struct nouveau_domain +nvc0_domain[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_href , 0xff }, + { nv_clk_src_hubk06 , 0x00 }, + { nv_clk_src_hubk01 , 0x01 }, + { nv_clk_src_copy , 0x02 }, + { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, + { nv_clk_src_rop , 0x04 }, + { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, + { nv_clk_src_vdec , 0x06 }, + { nv_clk_src_daemon , 0x0a }, + { nv_clk_src_hubk07 , 0x0b }, + { nv_clk_src_max } +}; + +static int +nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0, + false, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.read = nvc0_clk_read; + priv->base.calc = nvc0_clk_calc; + priv->base.prog = nvc0_clk_prog; + priv->base.tidy = nvc0_clk_tidy; + return 0; +} + +struct nouveau_oclass +nvc0_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xc0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c new file mode 100644 index 000000000000..ffd2139e0a49 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c @@ -0,0 +1,500 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include + +#include "pll.h" + +struct nve0_clk_info { + u32 freq; + u32 ssel; + u32 mdiv; + u32 dsrc; + u32 ddiv; + u32 coef; +}; + +struct nve0_clk_priv { + struct nouveau_clk base; + struct nve0_clk_info eng[16]; +}; + +static u32 read_div(struct nve0_clk_priv *, int, u32, u32); +static u32 read_pll(struct nve0_clk_priv *, u32); + +static u32 +read_vco(struct nve0_clk_priv *priv, u32 dsrc) +{ + u32 ssrc = nv_rd32(priv, dsrc); + if (!(ssrc & 0x00000100)) + return read_pll(priv, 0x00e800); + return read_pll(priv, 0x00e820); +} + +static u32 +read_pll(struct nve0_clk_priv *priv, u32 pll) +{ + u32 ctrl = nv_rd32(priv, pll + 0x00); + u32 coef = nv_rd32(priv, pll + 0x04); + u32 P = (coef & 0x003f0000) >> 16; + u32 N = (coef & 0x0000ff00) >> 8; + u32 M = (coef & 0x000000ff) >> 0; + u32 sclk; + u16 fN = 0xf000; + + if (!(ctrl & 0x00000001)) + return 0; + + switch (pll) { + case 0x00e800: + case 0x00e820: + sclk = nv_device(priv)->crystal; + P = 1; + break; + case 0x132000: + sclk = read_pll(priv, 0x132020); + P = (coef & 0x10000000) ? 2 : 1; + break; + case 0x132020: + sclk = read_div(priv, 0, 0x137320, 0x137330); + fN = nv_rd32(priv, pll + 0x10) >> 16; + break; + case 0x137000: + case 0x137020: + case 0x137040: + case 0x1370e0: + sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); + break; + default: + return 0; + } + + if (P == 0) + P = 1; + + sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); + return sclk / (M * P); +} + +static u32 +read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl) +{ + u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); + u32 sctl = nv_rd32(priv, dctl + (doff * 4)); + + switch (ssrc & 0x00000003) { + case 0: + if ((ssrc & 0x00030000) != 0x00030000) + return nv_device(priv)->crystal; + return 108000; + case 2: + return 100000; + case 3: + if (sctl & 0x80000000) { + u32 sclk = read_vco(priv, dsrc + (doff * 4)); + u32 sdiv = (sctl & 0x0000003f) + 2; + return (sclk * 2) / sdiv; + } + + return read_vco(priv, dsrc + (doff * 4)); + default: + return 0; + } +} + +static u32 +read_mem(struct nve0_clk_priv *priv) +{ + switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { + case 1: return read_pll(priv, 0x132020); + case 2: return read_pll(priv, 0x132000); + default: + return 0; + } +} + +static u32 +read_clk(struct nve0_clk_priv *priv, int clk) +{ + u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); + u32 sclk, sdiv; + + if (clk < 7) { + u32 ssel = nv_rd32(priv, 0x137100); + if (ssel & (1 << clk)) { + sclk = read_pll(priv, 0x137000 + (clk * 0x20)); + sdiv = 1; + } else { + sclk = read_div(priv, clk, 0x137160, 0x1371d0); + sdiv = 0; + } + } else { + u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); + if ((ssrc & 0x00000003) == 0x00000003) { + sclk = read_div(priv, clk, 0x137160, 0x1371d0); + if (ssrc & 0x00000100) { + if (ssrc & 0x40000000) + sclk = read_pll(priv, 0x1370e0); + sdiv = 1; + } else { + sdiv = 0; + } + } else { + sclk = read_div(priv, clk, 0x137160, 0x1371d0); + sdiv = 0; + } + } + + if (sctl & 0x80000000) { + if (sdiv) + sdiv = ((sctl & 0x00003f00) >> 8) + 2; + else + sdiv = ((sctl & 0x0000003f) >> 0) + 2; + return (sclk * 2) / sdiv; + } + + return sclk; +} + +static int +nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src) +{ + struct nouveau_device *device = nv_device(clk); + struct nve0_clk_priv *priv = (void *)clk; + + switch (src) { + case nv_clk_src_crystal: + return device->crystal; + case nv_clk_src_href: + return 100000; + case nv_clk_src_mem: + return read_mem(priv); + case nv_clk_src_gpc: + return read_clk(priv, 0x00); + case nv_clk_src_rop: + return read_clk(priv, 0x01); + case nv_clk_src_hubk07: + return read_clk(priv, 0x02); + case nv_clk_src_hubk06: + return read_clk(priv, 0x07); + case nv_clk_src_hubk01: + return read_clk(priv, 0x08); + case nv_clk_src_daemon: + return read_clk(priv, 0x0c); + case nv_clk_src_vdec: + return read_clk(priv, 0x0e); + default: + nv_error(clk, "invalid clock source %d\n", src); + return -EINVAL; + } +} + +static u32 +calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) +{ + u32 div = min((ref * 2) / freq, (u32)65); + if (div < 2) + div = 2; + + *ddiv = div - 2; + return (ref * 2) / div; +} + +static u32 +calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) +{ + u32 sclk; + + /* use one of the fixed frequencies if possible */ + *ddiv = 0x00000000; + switch (freq) { + case 27000: + case 108000: + *dsrc = 0x00000000; + if (freq == 108000) + *dsrc |= 0x00030000; + return freq; + case 100000: + *dsrc = 0x00000002; + return freq; + default: + *dsrc = 0x00000003; + break; + } + + /* otherwise, calculate the closest divider */ + sclk = read_vco(priv, 0x137160 + (clk * 4)); + if (clk < 7) + sclk = calc_div(priv, clk, sclk, freq, ddiv); + return sclk; +} + +static u32 +calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll limits; + int N, M, P, ret; + + ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); + if (ret) + return 0; + + limits.refclk = read_div(priv, clk, 0x137120, 0x137140); + if (!limits.refclk) + return 0; + + ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); + if (ret <= 0) + return 0; + + *coef = (P << 16) | (N << 8) | M; + return ret; +} + +static int +calc_clk(struct nve0_clk_priv *priv, + struct nouveau_cstate *cstate, int clk, int dom) +{ + struct nve0_clk_info *info = &priv->eng[clk]; + u32 freq = cstate->domain[dom]; + u32 src0, div0, div1D, div1P = 0; + u32 clk0, clk1 = 0; + + /* invalid clock domain */ + if (!freq) + return 0; + + /* first possible path, using only dividers */ + clk0 = calc_src(priv, clk, freq, &src0, &div0); + clk0 = calc_div(priv, clk, clk0, freq, &div1D); + + /* see if we can get any closer using PLLs */ + if (clk0 != freq && (0x0000ff87 & (1 << clk))) { + if (clk <= 7) + clk1 = calc_pll(priv, clk, freq, &info->coef); + else + clk1 = cstate->domain[nv_clk_src_hubk06]; + clk1 = calc_div(priv, clk, clk1, freq, &div1P); + } + + /* select the method which gets closest to target freq */ + if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { + info->dsrc = src0; + if (div0) { + info->ddiv |= 0x80000000; + info->ddiv |= div0; + } + if (div1D) { + info->mdiv |= 0x80000000; + info->mdiv |= div1D; + } + info->ssel = 0; + info->freq = clk0; + } else { + if (div1P) { + info->mdiv |= 0x80000000; + info->mdiv |= div1P << 8; + } + info->ssel = (1 << clk); + info->dsrc = 0x40000100; + info->freq = clk1; + } + + return 0; +} + +static int +nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate) +{ + struct nve0_clk_priv *priv = (void *)clk; + int ret; + + if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || + (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || + (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || + (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || + (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || + (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || + (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) + return ret; + + return 0; +} + +static void +nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk) +{ + struct nve0_clk_info *info = &priv->eng[clk]; + if (!info->ssel) { + nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); + nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); + } +} + +static void +nve0_clk_prog_1_0(struct nve0_clk_priv *priv, int clk) +{ + nv_mask(priv, 0x137100, (1 << clk), 0x00000000); + nv_wait(priv, 0x137100, (1 << clk), 0x00000000); +} + +static void +nve0_clk_prog_1_1(struct nve0_clk_priv *priv, int clk) +{ + nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); +} + +static void +nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk) +{ + struct nve0_clk_info *info = &priv->eng[clk]; + const u32 addr = 0x137000 + (clk * 0x20); + nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); + nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); + if (info->coef) { + nv_wr32(priv, addr + 0x04, info->coef); + nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); + nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); + nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); + } +} + +static void +nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk) +{ + struct nve0_clk_info *info = &priv->eng[clk]; + if (info->ssel) + nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); + else + nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); +} + +static void +nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk) +{ + struct nve0_clk_info *info = &priv->eng[clk]; + if (info->ssel) { + nv_mask(priv, 0x137100, (1 << clk), info->ssel); + nv_wait(priv, 0x137100, (1 << clk), info->ssel); + } +} + +static void +nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk) +{ + struct nve0_clk_info *info = &priv->eng[clk]; + if (info->ssel) { + nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); + nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); + } +} + +static int +nve0_clk_prog(struct nouveau_clk *clk) +{ + struct nve0_clk_priv *priv = (void *)clk; + struct { + u32 mask; + void (*exec)(struct nve0_clk_priv *, int); + } stage[] = { + { 0x007f, nve0_clk_prog_0 }, /* div programming */ + { 0x007f, nve0_clk_prog_1_0 }, /* select div mode */ + { 0xff80, nve0_clk_prog_1_1 }, + { 0x00ff, nve0_clk_prog_2 }, /* (maybe) program pll */ + { 0xff80, nve0_clk_prog_3 }, /* final divider */ + { 0x007f, nve0_clk_prog_4_0 }, /* (maybe) select pll mode */ + { 0xff80, nve0_clk_prog_4_1 }, + }; + int i, j; + + for (i = 0; i < ARRAY_SIZE(stage); i++) { + for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { + if (!(stage[i].mask & (1 << j))) + continue; + if (!priv->eng[j].freq) + continue; + stage[i].exec(priv, j); + } + } + + return 0; +} + +static void +nve0_clk_tidy(struct nouveau_clk *clk) +{ + struct nve0_clk_priv *priv = (void *)clk; + memset(priv->eng, 0x00, sizeof(priv->eng)); +} + +static struct nouveau_domain +nve0_domain[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_href , 0xff }, + { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 }, + { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE }, + { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE }, + { nv_clk_src_mem , 0x03, 0, "memory", 500 }, + { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, + { nv_clk_src_hubk01 , 0x05 }, + { nv_clk_src_vdec , 0x06 }, + { nv_clk_src_daemon , 0x07 }, + { nv_clk_src_max } +}; + +static int +nve0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nve0_clk_priv *priv; + int ret; + + ret = nouveau_clk_create(parent, engine, oclass, nve0_domain, NULL, 0, + true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.read = nve0_clk_read; + priv->base.calc = nve0_clk_calc; + priv->base.prog = nve0_clk_prog; + priv->base.tidy = nve0_clk_tidy; + return 0; +} + +struct nouveau_oclass +nve0_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xe0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nve0_clk_ctor, + .dtor = _nouveau_clk_dtor, + .init = _nouveau_clk_init, + .fini = _nouveau_clk_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h new file mode 100644 index 000000000000..445b14c33a98 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h @@ -0,0 +1,9 @@ +#ifndef __NOUVEAU_PLL_H__ +#define __NOUVEAU_PLL_H__ + +int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, + int *N1, int *M1, int *N2, int *M2, int *P); +int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, + int *N, int *fN, int *M, int *P); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c new file mode 100644 index 000000000000..b47d543ab2e3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c @@ -0,0 +1,246 @@ +/* + * Copyright 1993-2003 NVIDIA, Corporation + * Copyright 2007-2009 Stuart Bennett + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +#include "pll.h" + +static int +getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, + int *pN, int *pM, int *pP) +{ + /* Find M, N and P for a single stage PLL + * + * Note that some bioses (NV3x) have lookup tables of precomputed MNP + * values, but we're too lazy to use those atm + * + * "clk" parameter in kHz + * returns calculated clock + */ + struct nouveau_bios *bios = nouveau_bios(subdev); + int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; + int minM = info->vco1.min_m, maxM = info->vco1.max_m; + int minN = info->vco1.min_n, maxN = info->vco1.max_n; + int minU = info->vco1.min_inputfreq; + int maxU = info->vco1.max_inputfreq; + int minP = info->min_p; + int maxP = info->max_p_usable; + int crystal = info->refclk; + int M, N, thisP, P; + int clkP, calcclk; + int delta, bestdelta = INT_MAX; + int bestclk = 0; + + /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */ + /* possibly correlated with introduction of 27MHz crystal */ + if (bios->version.major < 0x60) { + int cv = bios->version.chip; + if (cv < 0x17 || cv == 0x1a || cv == 0x20) { + if (clk > 250000) + maxM = 6; + if (clk > 340000) + maxM = 2; + } else if (cv < 0x40) { + if (clk > 150000) + maxM = 6; + if (clk > 200000) + maxM = 4; + if (clk > 340000) + maxM = 2; + } + } + + P = 1 << maxP; + if ((clk * P) < minvco) { + minvco = clk * maxP; + maxvco = minvco * 2; + } + + if (clk + clk/200 > maxvco) /* +0.5% */ + maxvco = clk + clk/200; + + /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */ + for (thisP = minP; thisP <= maxP; thisP++) { + P = 1 << thisP; + clkP = clk * P; + + if (clkP < minvco) + continue; + if (clkP > maxvco) + return bestclk; + + for (M = minM; M <= maxM; M++) { + if (crystal/M < minU) + return bestclk; + if (crystal/M > maxU) + continue; + + /* add crystal/2 to round better */ + N = (clkP * M + crystal/2) / crystal; + + if (N < minN) + continue; + if (N > maxN) + break; + + /* more rounding additions */ + calcclk = ((N * crystal + P/2) / P + M/2) / M; + delta = abs(calcclk - clk); + /* we do an exhaustive search rather than terminating + * on an optimality condition... + */ + if (delta < bestdelta) { + bestdelta = delta; + bestclk = calcclk; + *pN = N; + *pM = M; + *pP = thisP; + if (delta == 0) /* except this one */ + return bestclk; + } + } + } + + return bestclk; +} + +static int +getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, + int *pN1, int *pM1, int *pN2, int *pM2, int *pP) +{ + /* Find M, N and P for a two stage PLL + * + * Note that some bioses (NV30+) have lookup tables of precomputed MNP + * values, but we're too lazy to use those atm + * + * "clk" parameter in kHz + * returns calculated clock + */ + int chip_version = nouveau_bios(subdev)->version.chip; + int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq; + int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq; + int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq; + int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq; + int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m; + int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n; + int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m; + int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n; + int maxlog2P = info->max_p_usable; + int crystal = info->refclk; + bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2); + int M1, N1, M2, N2, log2P; + int clkP, calcclk1, calcclk2, calcclkout; + int delta, bestdelta = INT_MAX; + int bestclk = 0; + + int vco2 = (maxvco2 - maxvco2/200) / 2; + for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++) + ; + clkP = clk << log2P; + + if (maxvco2 < clk + clk/200) /* +0.5% */ + maxvco2 = clk + clk/200; + + for (M1 = minM1; M1 <= maxM1; M1++) { + if (crystal/M1 < minU1) + return bestclk; + if (crystal/M1 > maxU1) + continue; + + for (N1 = minN1; N1 <= maxN1; N1++) { + calcclk1 = crystal * N1 / M1; + if (calcclk1 < minvco1) + continue; + if (calcclk1 > maxvco1) + break; + + for (M2 = minM2; M2 <= maxM2; M2++) { + if (calcclk1/M2 < minU2) + break; + if (calcclk1/M2 > maxU2) + continue; + + /* add calcclk1/2 to round better */ + N2 = (clkP * M2 + calcclk1/2) / calcclk1; + if (N2 < minN2) + continue; + if (N2 > maxN2) + break; + + if (!fixedgain2) { + if (chip_version < 0x60) + if (N2/M2 < 4 || N2/M2 > 10) + continue; + + calcclk2 = calcclk1 * N2 / M2; + if (calcclk2 < minvco2) + break; + if (calcclk2 > maxvco2) + continue; + } else + calcclk2 = calcclk1; + + calcclkout = calcclk2 >> log2P; + delta = abs(calcclkout - clk); + /* we do an exhaustive search rather than terminating + * on an optimality condition... + */ + if (delta < bestdelta) { + bestdelta = delta; + bestclk = calcclkout; + *pN1 = N1; + *pM1 = M1; + *pN2 = N2; + *pM2 = M2; + *pP = log2P; + if (delta == 0) /* except this one */ + return bestclk; + } + } + } + } + + return bestclk; +} + +int +nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq, + int *N1, int *M1, int *N2, int *M2, int *P) +{ + int ret; + + if (!info->vco2.max_freq || !N2) { + ret = getMNP_single(subdev, info, freq, N1, M1, P); + if (N2) { + *N2 = 1; + *M2 = 1; + } + } else { + ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); + } + + if (!ret) + nv_error(subdev, "unable to compute acceptable pll values\n"); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c new file mode 100644 index 000000000000..bc17fcc83bfe --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c @@ -0,0 +1,89 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include + +#include "pll.h" + +int +nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, + u32 freq, int *pN, int *pfN, int *pM, int *P) +{ + u32 best_err = ~0, err; + int M, lM, hM, N, fN; + + *P = info->vco1.max_freq / freq; + if (*P > info->max_p) + *P = info->max_p; + if (*P < info->min_p) + *P = info->min_p; + + lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; + lM = max(lM, (int)info->vco1.min_m); + hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; + hM = min(hM, (int)info->vco1.max_m); + lM = min(lM, hM); + + for (M = lM; M <= hM; M++) { + u32 tmp = freq * *P * M; + N = tmp / info->refclk; + fN = tmp % info->refclk; + + if (!pfN) { + if (fN >= info->refclk / 2) + N++; + } else { + if (fN < info->refclk / 2) + N--; + fN = tmp - (N * info->refclk); + } + + if (N < info->vco1.min_n) + continue; + if (N > info->vco1.max_n) + break; + + err = abs(freq - (info->refclk * N / M / *P)); + if (err < best_err) { + best_err = err; + *pN = N; + *pM = M; + } + + if (pfN) { + *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; + *pfN = (*pfN - 4096) & 0xffff; + return freq; + } + } + + if (unlikely(best_err == ~0)) { + nv_error(subdev, "unable to find matching pll values\n"); + return -EINVAL; + } + + return info->refclk * *pN / *pM / *P; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h new file mode 100644 index 000000000000..fb33f06ebd59 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h @@ -0,0 +1,17 @@ +#ifndef __NVKM_CLK_SEQ_H__ +#define __NVKM_CLK_SEQ_H__ + +#include +#include + +#define clk_init(s,p) hwsq_init(&(s)->base, (p)) +#define clk_exec(s,e) hwsq_exec(&(s)->base, (e)) +#define clk_have(s,r) ((s)->r_##r.addr != 0x000000) +#define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) +#define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) +#define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) +#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) +#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) +#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n)) + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild deleted file mode 100644 index f0a86021fbb1..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild +++ /dev/null @@ -1,12 +0,0 @@ -nvkm-y += nvkm/subdev/clock/base.o -nvkm-y += nvkm/subdev/clock/nv04.o -nvkm-y += nvkm/subdev/clock/nv40.o -nvkm-y += nvkm/subdev/clock/nv50.o -nvkm-y += nvkm/subdev/clock/nv84.o -nvkm-y += nvkm/subdev/clock/nva3.o -nvkm-y += nvkm/subdev/clock/nvaa.o -nvkm-y += nvkm/subdev/clock/nvc0.o -nvkm-y += nvkm/subdev/clock/nve0.o -nvkm-y += nvkm/subdev/clock/gk20a.o -nvkm-y += nvkm/subdev/clock/pllnv04.o -nvkm-y += nvkm/subdev/clock/pllnva3.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c deleted file mode 100644 index bc095b470121..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -/****************************************************************************** - * misc - *****************************************************************************/ -static u32 -nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust, - u8 pstate, u8 domain, u32 input) -{ - struct nouveau_bios *bios = nouveau_bios(clk); - struct nvbios_boostE boostE; - u8 ver, hdr, cnt, len; - u16 data; - - data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE); - if (data) { - struct nvbios_boostS boostS; - u8 idx = 0, sver, shdr; - u16 subd; - - input = max(boostE.min, input); - input = min(boostE.max, input); - do { - sver = ver; - shdr = hdr; - subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr, - cnt, len, &boostS); - if (subd && boostS.domain == domain) { - if (adjust) - input = input * boostS.percent / 100; - input = max(boostS.min, input); - input = min(boostS.max, input); - break; - } - } while (subd); - } - - return input; -} - -/****************************************************************************** - * C-States - *****************************************************************************/ -static int -nouveau_cstate_prog(struct nouveau_clock *clk, - struct nouveau_pstate *pstate, int cstatei) -{ - struct nouveau_therm *ptherm = nouveau_therm(clk); - struct nouveau_volt *volt = nouveau_volt(clk); - struct nouveau_cstate *cstate; - int ret; - - if (!list_empty(&pstate->list)) { - cstate = list_entry(pstate->list.prev, typeof(*cstate), head); - } else { - cstate = &pstate->base; - } - - if (ptherm) { - ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); - if (ret && ret != -ENODEV) { - nv_error(clk, "failed to raise fan speed: %d\n", ret); - return ret; - } - } - - if (volt) { - ret = volt->set_id(volt, cstate->voltage, +1); - if (ret && ret != -ENODEV) { - nv_error(clk, "failed to raise voltage: %d\n", ret); - return ret; - } - } - - ret = clk->calc(clk, cstate); - if (ret == 0) { - ret = clk->prog(clk); - clk->tidy(clk); - } - - if (volt) { - ret = volt->set_id(volt, cstate->voltage, -1); - if (ret && ret != -ENODEV) - nv_error(clk, "failed to lower voltage: %d\n", ret); - } - - if (ptherm) { - ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); - if (ret && ret != -ENODEV) - nv_error(clk, "failed to lower fan speed: %d\n", ret); - } - - return 0; -} - -static void -nouveau_cstate_del(struct nouveau_cstate *cstate) -{ - list_del(&cstate->head); - kfree(cstate); -} - -static int -nouveau_cstate_new(struct nouveau_clock *clk, int idx, - struct nouveau_pstate *pstate) -{ - struct nouveau_bios *bios = nouveau_bios(clk); - struct nouveau_clocks *domain = clk->domains; - struct nouveau_cstate *cstate = NULL; - struct nvbios_cstepX cstepX; - u8 ver, hdr; - u16 data; - - data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX); - if (!data) - return -ENOENT; - - cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); - if (!cstate) - return -ENOMEM; - - *cstate = pstate->base; - cstate->voltage = cstepX.voltage; - - while (domain && domain->name != nv_clk_src_max) { - if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { - u32 freq = nouveau_clock_adjust(clk, true, - pstate->pstate, - domain->bios, - cstepX.freq); - cstate->domain[domain->name] = freq; - } - domain++; - } - - list_add(&cstate->head, &pstate->list); - return 0; -} - -/****************************************************************************** - * P-States - *****************************************************************************/ -static int -nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) -{ - struct nouveau_fb *pfb = nouveau_fb(clk); - struct nouveau_pstate *pstate; - int ret, idx = 0; - - list_for_each_entry(pstate, &clk->states, head) { - if (idx++ == pstatei) - break; - } - - nv_debug(clk, "setting performance state %d\n", pstatei); - clk->pstate = pstatei; - - if (pfb->ram->calc) { - int khz = pstate->base.domain[nv_clk_src_mem]; - do { - ret = pfb->ram->calc(pfb, khz); - if (ret == 0) - ret = pfb->ram->prog(pfb); - } while (ret > 0); - pfb->ram->tidy(pfb); - } - - return nouveau_cstate_prog(clk, pstate, 0); -} - -static void -nouveau_pstate_work(struct work_struct *work) -{ - struct nouveau_clock *clk = container_of(work, typeof(*clk), work); - int pstate; - - if (!atomic_xchg(&clk->waiting, 0)) - return; - clk->pwrsrc = power_supply_is_system_supplied(); - - nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", - clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, - clk->astate, clk->tstate, clk->dstate); - - pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; - if (clk->state_nr && pstate != -1) { - pstate = (pstate < 0) ? clk->astate : pstate; - pstate = min(pstate, clk->state_nr - 1 - clk->tstate); - pstate = max(pstate, clk->dstate); - } else { - pstate = clk->pstate = -1; - } - - nv_trace(clk, "-> %d\n", pstate); - if (pstate != clk->pstate) { - int ret = nouveau_pstate_prog(clk, pstate); - if (ret) { - nv_error(clk, "error setting pstate %d: %d\n", - pstate, ret); - } - } - - wake_up_all(&clk->wait); - nvkm_notify_get(&clk->pwrsrc_ntfy); -} - -static int -nouveau_pstate_calc(struct nouveau_clock *clk, bool wait) -{ - atomic_set(&clk->waiting, 1); - schedule_work(&clk->work); - if (wait) - wait_event(clk->wait, !atomic_read(&clk->waiting)); - return 0; -} - -static void -nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate) -{ - struct nouveau_clocks *clock = clk->domains - 1; - struct nouveau_cstate *cstate; - char info[3][32] = { "", "", "" }; - char name[4] = "--"; - int i = -1; - - if (pstate->pstate != 0xff) - snprintf(name, sizeof(name), "%02x", pstate->pstate); - - while ((++clock)->name != nv_clk_src_max) { - u32 lo = pstate->base.domain[clock->name]; - u32 hi = lo; - if (hi == 0) - continue; - - nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); - list_for_each_entry(cstate, &pstate->list, head) { - u32 freq = cstate->domain[clock->name]; - lo = min(lo, freq); - hi = max(hi, freq); - nv_debug(clk, "%10d KHz\n", freq); - } - - if (clock->mname && ++i < ARRAY_SIZE(info)) { - lo /= clock->mdiv; - hi /= clock->mdiv; - if (lo == hi) { - snprintf(info[i], sizeof(info[i]), "%s %d MHz", - clock->mname, lo); - } else { - snprintf(info[i], sizeof(info[i]), - "%s %d-%d MHz", clock->mname, lo, hi); - } - } - } - - nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); -} - -static void -nouveau_pstate_del(struct nouveau_pstate *pstate) -{ - struct nouveau_cstate *cstate, *temp; - - list_for_each_entry_safe(cstate, temp, &pstate->list, head) { - nouveau_cstate_del(cstate); - } - - list_del(&pstate->head); - kfree(pstate); -} - -static int -nouveau_pstate_new(struct nouveau_clock *clk, int idx) -{ - struct nouveau_bios *bios = nouveau_bios(clk); - struct nouveau_clocks *domain = clk->domains - 1; - struct nouveau_pstate *pstate; - struct nouveau_cstate *cstate; - struct nvbios_cstepE cstepE; - struct nvbios_perfE perfE; - u8 ver, hdr, cnt, len; - u16 data; - - data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE); - if (!data) - return -EINVAL; - if (perfE.pstate == 0xff) - return 0; - - pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); - cstate = &pstate->base; - if (!pstate) - return -ENOMEM; - - INIT_LIST_HEAD(&pstate->list); - - pstate->pstate = perfE.pstate; - pstate->fanspeed = perfE.fanspeed; - cstate->voltage = perfE.voltage; - cstate->domain[nv_clk_src_core] = perfE.core; - cstate->domain[nv_clk_src_shader] = perfE.shader; - cstate->domain[nv_clk_src_mem] = perfE.memory; - cstate->domain[nv_clk_src_vdec] = perfE.vdec; - cstate->domain[nv_clk_src_dom6] = perfE.disp; - - while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) { - struct nvbios_perfS perfS; - u8 sver = ver, shdr = hdr; - u32 perfSe = nvbios_perfSp(bios, data, domain->bios, - &sver, &shdr, cnt, len, &perfS); - if (perfSe == 0 || sver != 0x40) - continue; - - if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { - perfS.v40.freq = nouveau_clock_adjust(clk, false, - pstate->pstate, - domain->bios, - perfS.v40.freq); - } - - cstate->domain[domain->name] = perfS.v40.freq; - } - - data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE); - if (data) { - int idx = cstepE.index; - do { - nouveau_cstate_new(clk, idx, pstate); - } while(idx--); - } - - nouveau_pstate_info(clk, pstate); - list_add_tail(&pstate->head, &clk->states); - clk->state_nr++; - return 0; -} - -/****************************************************************************** - * Adjustment triggers - *****************************************************************************/ -static int -nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) -{ - struct nouveau_pstate *pstate; - int i = 0; - - if (!clk->allow_reclock) - return -ENOSYS; - - if (req != -1 && req != -2) { - list_for_each_entry(pstate, &clk->states, head) { - if (pstate->pstate == req) - break; - i++; - } - - if (pstate->pstate != req) - return -EINVAL; - req = i; - } - - return req + 2; -} - -static int -nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen) -{ - int ret = 1; - - if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) - return -2; - - if (strncasecmpz(mode, "disabled", arglen)) { - char save = mode[arglen]; - long v; - - ((char *)mode)[arglen] = '\0'; - if (!kstrtol(mode, 0, &v)) { - ret = nouveau_clock_ustate_update(clk, v); - if (ret < 0) - ret = 1; - } - ((char *)mode)[arglen] = save; - } - - return ret - 2; -} - -int -nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr) -{ - int ret = nouveau_clock_ustate_update(clk, req); - if (ret >= 0) { - if (ret -= 2, pwr) clk->ustate_ac = ret; - else clk->ustate_dc = ret; - return nouveau_pstate_calc(clk, true); - } - return ret; -} - -int -nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait) -{ - if (!rel) clk->astate = req; - if ( rel) clk->astate += rel; - clk->astate = min(clk->astate, clk->state_nr - 1); - clk->astate = max(clk->astate, 0); - return nouveau_pstate_calc(clk, wait); -} - -int -nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel) -{ - if (!rel) clk->tstate = req; - if ( rel) clk->tstate += rel; - clk->tstate = min(clk->tstate, 0); - clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); - return nouveau_pstate_calc(clk, true); -} - -int -nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel) -{ - if (!rel) clk->dstate = req; - if ( rel) clk->dstate += rel; - clk->dstate = min(clk->dstate, clk->state_nr - 1); - clk->dstate = max(clk->dstate, 0); - return nouveau_pstate_calc(clk, true); -} - -static int -nouveau_clock_pwrsrc(struct nvkm_notify *notify) -{ - struct nouveau_clock *clk = - container_of(notify, typeof(*clk), pwrsrc_ntfy); - nouveau_pstate_calc(clk, false); - return NVKM_NOTIFY_DROP; -} - -/****************************************************************************** - * subdev base class implementation - *****************************************************************************/ - -int -_nouveau_clock_fini(struct nouveau_object *object, bool suspend) -{ - struct nouveau_clock *clk = (void *)object; - nvkm_notify_put(&clk->pwrsrc_ntfy); - return nouveau_subdev_fini(&clk->base, suspend); -} - -int -_nouveau_clock_init(struct nouveau_object *object) -{ - struct nouveau_clock *clk = (void *)object; - struct nouveau_clocks *clock = clk->domains; - int ret; - - ret = nouveau_subdev_init(&clk->base); - if (ret) - return ret; - - memset(&clk->bstate, 0x00, sizeof(clk->bstate)); - INIT_LIST_HEAD(&clk->bstate.list); - clk->bstate.pstate = 0xff; - - while (clock->name != nv_clk_src_max) { - ret = clk->read(clk, clock->name); - if (ret < 0) { - nv_error(clk, "%02x freq unknown\n", clock->name); - return ret; - } - clk->bstate.base.domain[clock->name] = ret; - clock++; - } - - nouveau_pstate_info(clk, &clk->bstate); - - clk->astate = clk->state_nr - 1; - clk->tstate = 0; - clk->dstate = 0; - clk->pstate = -1; - nouveau_pstate_calc(clk, true); - return 0; -} - -void -_nouveau_clock_dtor(struct nouveau_object *object) -{ - struct nouveau_clock *clk = (void *)object; - struct nouveau_pstate *pstate, *temp; - - nvkm_notify_fini(&clk->pwrsrc_ntfy); - - list_for_each_entry_safe(pstate, temp, &clk->states, head) { - nouveau_pstate_del(pstate); - } - - nouveau_subdev_destroy(&clk->base); -} - -int -nouveau_clock_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - struct nouveau_clocks *clocks, - struct nouveau_pstate *pstates, int nb_pstates, - bool allow_reclock, - int length, void **object) -{ - struct nouveau_device *device = nv_device(parent); - struct nouveau_clock *clk; - int ret, idx, arglen; - const char *mode; - - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK", - "clock", length, object); - clk = *object; - if (ret) - return ret; - - INIT_LIST_HEAD(&clk->states); - clk->domains = clocks; - clk->ustate_ac = -1; - clk->ustate_dc = -1; - - INIT_WORK(&clk->work, nouveau_pstate_work); - init_waitqueue_head(&clk->wait); - atomic_set(&clk->waiting, 0); - - /* If no pstates are provided, try and fetch them from the BIOS */ - if (!pstates) { - idx = 0; - do { - ret = nouveau_pstate_new(clk, idx++); - } while (ret == 0); - } else { - for (idx = 0; idx < nb_pstates; idx++) - list_add_tail(&pstates[idx].head, &clk->states); - clk->state_nr = nb_pstates; - } - - clk->allow_reclock = allow_reclock; - - ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true, - NULL, 0, 0, &clk->pwrsrc_ntfy); - if (ret) - return ret; - - mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); - if (mode) { - clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); - clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); - } - - mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen); - if (mode) - clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); - - mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen); - if (mode) - clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); - - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c deleted file mode 100644 index fb4fad374bdd..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c +++ /dev/null @@ -1,680 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c - * - */ - -#define MHZ (1000 * 1000) - -#define MASK(w) ((1 << w) - 1) - -#define SYS_GPCPLL_CFG_BASE 0x00137000 -#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 - -#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) -#define GPCPLL_CFG_ENABLE BIT(0) -#define GPCPLL_CFG_IDDQ BIT(1) -#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) -#define GPCPLL_CFG_LOCK BIT(17) - -#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) -#define GPCPLL_COEFF_M_SHIFT 0 -#define GPCPLL_COEFF_M_WIDTH 8 -#define GPCPLL_COEFF_N_SHIFT 8 -#define GPCPLL_COEFF_N_WIDTH 8 -#define GPCPLL_COEFF_P_SHIFT 16 -#define GPCPLL_COEFF_P_WIDTH 6 - -#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) -#define GPCPLL_CFG2_SETUP2_SHIFT 16 -#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 - -#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) -#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 - -#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) -#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 -#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 -#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 -#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 -#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 - -#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) -#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 - -#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) -#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 -#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 -#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 -#define GPC2CLK_OUT_VCODIV_WIDTH 6 -#define GPC2CLK_OUT_VCODIV_SHIFT 8 -#define GPC2CLK_OUT_VCODIV1 0 -#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ - GPC2CLK_OUT_VCODIV_SHIFT) -#define GPC2CLK_OUT_BYPDIV_WIDTH 6 -#define GPC2CLK_OUT_BYPDIV_SHIFT 0 -#define GPC2CLK_OUT_BYPDIV31 0x3c -#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ - GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ - | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ - | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) -#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ - GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ - | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ - | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) - -#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) -#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 -#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ - (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) - -#include -#include - -#ifdef __KERNEL__ -#include -#endif - -static const u8 pl_to_div[] = { -/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ -/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, -}; - -/* All frequencies in Mhz */ -struct gk20a_clk_pllg_params { - u32 min_vco, max_vco; - u32 min_u, max_u; - u32 min_m, max_m; - u32 min_n, max_n; - u32 min_pl, max_pl; -}; - -static const struct gk20a_clk_pllg_params gk20a_pllg_params = { - .min_vco = 1000, .max_vco = 2064, - .min_u = 12, .max_u = 38, - .min_m = 1, .max_m = 255, - .min_n = 8, .max_n = 255, - .min_pl = 1, .max_pl = 32, -}; - -struct gk20a_clock_priv { - struct nouveau_clock base; - const struct gk20a_clk_pllg_params *params; - u32 m, n, pl; - u32 parent_rate; -}; -#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base) - -static void -gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) -{ - u32 val; - - val = nv_rd32(priv, GPCPLL_COEFF); - priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); - priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); - priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); -} - -static u32 -gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) -{ - u32 rate; - u32 divider; - - rate = priv->parent_rate * priv->n; - divider = priv->m * pl_to_div[priv->pl]; - do_div(rate, divider); - - return rate / 2; -} - -static int -gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate) -{ - u32 target_clk_f, ref_clk_f, target_freq; - u32 min_vco_f, max_vco_f; - u32 low_pl, high_pl, best_pl; - u32 target_vco_f, vco_f; - u32 best_m, best_n; - u32 u_f; - u32 m, n, n2; - u32 delta, lwv, best_delta = ~0; - u32 pl; - - target_clk_f = rate * 2 / MHZ; - ref_clk_f = priv->parent_rate / MHZ; - - max_vco_f = priv->params->max_vco; - min_vco_f = priv->params->min_vco; - best_m = priv->params->max_m; - best_n = priv->params->min_n; - best_pl = priv->params->min_pl; - - target_vco_f = target_clk_f + target_clk_f / 50; - if (max_vco_f < target_vco_f) - max_vco_f = target_vco_f; - - /* min_pl <= high_pl <= max_pl */ - high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; - high_pl = min(high_pl, priv->params->max_pl); - high_pl = max(high_pl, priv->params->min_pl); - - /* min_pl <= low_pl <= max_pl */ - low_pl = min_vco_f / target_vco_f; - low_pl = min(low_pl, priv->params->max_pl); - low_pl = max(low_pl, priv->params->min_pl); - - /* Find Indices of high_pl and low_pl */ - for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { - if (pl_to_div[pl] >= low_pl) { - low_pl = pl; - break; - } - } - for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { - if (pl_to_div[pl] >= high_pl) { - high_pl = pl; - break; - } - } - - nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, - pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); - - /* Select lowest possible VCO */ - for (pl = low_pl; pl <= high_pl; pl++) { - target_vco_f = target_clk_f * pl_to_div[pl]; - for (m = priv->params->min_m; m <= priv->params->max_m; m++) { - u_f = ref_clk_f / m; - - if (u_f < priv->params->min_u) - break; - if (u_f > priv->params->max_u) - continue; - - n = (target_vco_f * m) / ref_clk_f; - n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; - - if (n > priv->params->max_n) - break; - - for (; n <= n2; n++) { - if (n < priv->params->min_n) - continue; - if (n > priv->params->max_n) - break; - - vco_f = ref_clk_f * n / m; - - if (vco_f >= min_vco_f && vco_f <= max_vco_f) { - lwv = (vco_f + (pl_to_div[pl] / 2)) - / pl_to_div[pl]; - delta = abs(lwv - target_clk_f); - - if (delta < best_delta) { - best_delta = delta; - best_m = m; - best_n = n; - best_pl = pl; - - if (best_delta == 0) - goto found_match; - } - } - } - } - } - -found_match: - WARN_ON(best_delta == ~0); - - if (best_delta != 0) - nv_debug(priv, "no best match for target @ %dMHz on gpc_pll", - target_clk_f); - - priv->m = best_m; - priv->n = best_n; - priv->pl = best_pl; - - target_freq = gk20a_pllg_calc_rate(priv) / MHZ; - - nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", - target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); - - return 0; -} - -static int -gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) -{ - u32 val; - int ramp_timeout; - - /* get old coefficients */ - val = nv_rd32(priv, GPCPLL_COEFF); - /* do nothing if NDIV is the same */ - if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) - return 0; - - /* setup */ - nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, - 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); - nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, - 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); - - /* pll slowdown mode */ - nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, - BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), - BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); - - /* new ndiv ready for ramp */ - val = nv_rd32(priv, GPCPLL_COEFF); - val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); - val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; - udelay(1); - nv_wr32(priv, GPCPLL_COEFF, val); - - /* dynamic ramp to new ndiv */ - val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); - val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; - udelay(1); - nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); - - for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { - udelay(1); - val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); - if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) - break; - } - - /* exit slowdown mode */ - nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, - BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | - BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); - nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); - - if (ramp_timeout <= 0) { - nv_error(priv, "gpcpll dynamic ramp timeout\n"); - return -ETIMEDOUT; - } - - return 0; -} - -static void -_gk20a_pllg_enable(struct gk20a_clock_priv *priv) -{ - nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); - nv_rd32(priv, GPCPLL_CFG); -} - -static void -_gk20a_pllg_disable(struct gk20a_clock_priv *priv) -{ - nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); - nv_rd32(priv, GPCPLL_CFG); -} - -static int -_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) -{ - u32 val, cfg; - u32 m_old, pl_old, n_lo; - - /* get old coefficients */ - val = nv_rd32(priv, GPCPLL_COEFF); - m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); - pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); - - /* do NDIV slide if there is no change in M and PL */ - cfg = nv_rd32(priv, GPCPLL_CFG); - if (allow_slide && priv->m == m_old && priv->pl == pl_old && - (cfg & GPCPLL_CFG_ENABLE)) { - return gk20a_pllg_slide(priv, priv->n); - } - - /* slide down to NDIV_LO */ - n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco, - priv->parent_rate / MHZ); - if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { - int ret = gk20a_pllg_slide(priv, n_lo); - - if (ret) - return ret; - } - - /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ - nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, - 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); - - /* put PLL in bypass before programming it */ - val = nv_rd32(priv, SEL_VCO); - val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); - udelay(2); - nv_wr32(priv, SEL_VCO, val); - - /* get out from IDDQ */ - val = nv_rd32(priv, GPCPLL_CFG); - if (val & GPCPLL_CFG_IDDQ) { - val &= ~GPCPLL_CFG_IDDQ; - nv_wr32(priv, GPCPLL_CFG, val); - nv_rd32(priv, GPCPLL_CFG); - udelay(2); - } - - _gk20a_pllg_disable(priv); - - nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n, - priv->pl); - - n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco, - priv->parent_rate / MHZ); - val = priv->m << GPCPLL_COEFF_M_SHIFT; - val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT; - val |= priv->pl << GPCPLL_COEFF_P_SHIFT; - nv_wr32(priv, GPCPLL_COEFF, val); - - _gk20a_pllg_enable(priv); - - val = nv_rd32(priv, GPCPLL_CFG); - if (val & GPCPLL_CFG_LOCK_DET_OFF) { - val &= ~GPCPLL_CFG_LOCK_DET_OFF; - nv_wr32(priv, GPCPLL_CFG, val); - } - - if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, - GPCPLL_CFG_LOCK)) { - nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); - return -ETIMEDOUT; - } - - /* switch to VCO mode */ - nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); - - /* restore out divider 1:1 */ - val = nv_rd32(priv, GPC2CLK_OUT); - val &= ~GPC2CLK_OUT_VCODIV_MASK; - udelay(2); - nv_wr32(priv, GPC2CLK_OUT, val); - - /* slide up to new NDIV */ - return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0; -} - -static int -gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) -{ - int err; - - err = _gk20a_pllg_program_mnp(priv, true); - if (err) - err = _gk20a_pllg_program_mnp(priv, false); - - return err; -} - -static void -gk20a_pllg_disable(struct gk20a_clock_priv *priv) -{ - u32 val; - - /* slide to VCO min */ - val = nv_rd32(priv, GPCPLL_CFG); - if (val & GPCPLL_CFG_ENABLE) { - u32 coeff, m, n_lo; - - coeff = nv_rd32(priv, GPCPLL_COEFF); - m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); - n_lo = DIV_ROUND_UP(m * priv->params->min_vco, - priv->parent_rate / MHZ); - gk20a_pllg_slide(priv, n_lo); - } - - /* put PLL in bypass before disabling it */ - nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); - - _gk20a_pllg_disable(priv); -} - -#define GK20A_CLK_GPC_MDIV 1000 - -static struct nouveau_clocks -gk20a_domains[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, - { nv_clk_src_max } -}; - -static struct nouveau_pstate -gk20a_pstates[] = { - { - .base = { - .domain[nv_clk_src_gpc] = 72000, - .voltage = 0, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 108000, - .voltage = 1, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 180000, - .voltage = 2, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 252000, - .voltage = 3, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 324000, - .voltage = 4, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 396000, - .voltage = 5, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 468000, - .voltage = 6, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 540000, - .voltage = 7, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 612000, - .voltage = 8, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 648000, - .voltage = 9, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 684000, - .voltage = 10, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 708000, - .voltage = 11, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 756000, - .voltage = 12, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 804000, - .voltage = 13, - }, - }, - { - .base = { - .domain[nv_clk_src_gpc] = 852000, - .voltage = 14, - }, - }, -}; - -static int -gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct gk20a_clock_priv *priv = (void *)clk; - - switch (src) { - case nv_clk_src_crystal: - return nv_device(clk)->crystal; - case nv_clk_src_gpc: - gk20a_pllg_read_mnp(priv); - return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV; - default: - nv_error(clk, "invalid clock source %d\n", src); - return -EINVAL; - } -} - -static int -gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct gk20a_clock_priv *priv = (void *)clk; - - return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * - GK20A_CLK_GPC_MDIV); -} - -static int -gk20a_clock_prog(struct nouveau_clock *clk) -{ - struct gk20a_clock_priv *priv = (void *)clk; - - return gk20a_pllg_program_mnp(priv); -} - -static void -gk20a_clock_tidy(struct nouveau_clock *clk) -{ -} - -static int -gk20a_clock_fini(struct nouveau_object *object, bool suspend) -{ - struct gk20a_clock_priv *priv = (void *)object; - int ret; - - ret = nouveau_clock_fini(&priv->base, false); - - gk20a_pllg_disable(priv); - - return ret; -} - -static int -gk20a_clock_init(struct nouveau_object *object) -{ - struct gk20a_clock_priv *priv = (void *)object; - int ret; - - nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); - - ret = nouveau_clock_init(&priv->base); - if (ret) - return ret; - - ret = gk20a_clock_prog(&priv->base); - if (ret) { - nv_error(priv, "cannot initialize clock\n"); - return ret; - } - - return 0; -} - -static int -gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct gk20a_clock_priv *priv; - struct nouveau_platform_device *plat; - int ret; - int i; - - /* Finish initializing the pstates */ - for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { - INIT_LIST_HEAD(&gk20a_pstates[i].list); - gk20a_pstates[i].pstate = i + 1; - } - - ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains, - gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->params = &gk20a_pllg_params; - - plat = nv_device_to_platform(nv_device(parent)); - priv->parent_rate = clk_get_rate(plat->gpu->clk); - nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); - - priv->base.read = gk20a_clock_read; - priv->base.calc = gk20a_clock_calc; - priv->base.prog = gk20a_clock_prog; - priv->base.tidy = gk20a_clock_tidy; - - return 0; -} - -struct nouveau_oclass -gk20a_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xea), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = gk20a_clock_ctor, - .dtor = _nouveau_subdev_dtor, - .init = gk20a_clock_init, - .fini = gk20a_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c deleted file mode 100644 index 4c48232686be..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include - -#include "pll.h" - -struct nv04_clock_priv { - struct nouveau_clock base; -}; - -int -nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, - int clk, struct nouveau_pll_vals *pv) -{ - int N1, M1, N2, M2, P; - int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); - if (ret) { - pv->refclk = info->refclk; - pv->N1 = N1; - pv->M1 = M1; - pv->N2 = N2; - pv->M2 = M2; - pv->log2P = P; - } - return ret; -} - -int -nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1, - struct nouveau_pll_vals *pv) -{ - struct nouveau_devinit *devinit = nouveau_devinit(clk); - int cv = nouveau_bios(clk)->version.chip; - - if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || - cv >= 0x40) { - if (reg1 > 0x405c) - setPLL_double_highregs(devinit, reg1, pv); - else - setPLL_double_lowregs(devinit, reg1, pv); - } else - setPLL_single(devinit, reg1, pv); - - return 0; -} - -static struct nouveau_clocks -nv04_domain[] = { - { nv_clk_src_max } -}; - -static int -nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv04_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0, - false, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.pll_calc = nv04_clock_pll_calc; - priv->base.pll_prog = nv04_clock_pll_prog; - return 0; -} - -struct nouveau_oclass -nv04_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c deleted file mode 100644 index 08368fe97029..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include "pll.h" - -struct nv40_clock_priv { - struct nouveau_clock base; - u32 ctrl; - u32 npll_ctrl; - u32 npll_coef; - u32 spll; -}; - -static struct nouveau_clocks -nv40_domain[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_core , 0xff, 0, "core", 1000 }, - { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, - { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, - { nv_clk_src_max } -}; - -static u32 -read_pll_1(struct nv40_clock_priv *priv, u32 reg) -{ - u32 ctrl = nv_rd32(priv, reg + 0x00); - int P = (ctrl & 0x00070000) >> 16; - int N = (ctrl & 0x0000ff00) >> 8; - int M = (ctrl & 0x000000ff) >> 0; - u32 ref = 27000, clk = 0; - - if (ctrl & 0x80000000) - clk = ref * N / M; - - return clk >> P; -} - -static u32 -read_pll_2(struct nv40_clock_priv *priv, u32 reg) -{ - u32 ctrl = nv_rd32(priv, reg + 0x00); - u32 coef = nv_rd32(priv, reg + 0x04); - int N2 = (coef & 0xff000000) >> 24; - int M2 = (coef & 0x00ff0000) >> 16; - int N1 = (coef & 0x0000ff00) >> 8; - int M1 = (coef & 0x000000ff) >> 0; - int P = (ctrl & 0x00070000) >> 16; - u32 ref = 27000, clk = 0; - - if ((ctrl & 0x80000000) && M1) { - clk = ref * N1 / M1; - if ((ctrl & 0x40000100) == 0x40000000) { - if (M2) - clk = clk * N2 / M2; - else - clk = 0; - } - } - - return clk >> P; -} - -static u32 -read_clk(struct nv40_clock_priv *priv, u32 src) -{ - switch (src) { - case 3: - return read_pll_2(priv, 0x004000); - case 2: - return read_pll_1(priv, 0x004008); - default: - break; - } - - return 0; -} - -static int -nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct nv40_clock_priv *priv = (void *)clk; - u32 mast = nv_rd32(priv, 0x00c040); - - switch (src) { - case nv_clk_src_crystal: - return nv_device(priv)->crystal; - case nv_clk_src_href: - return 100000; /*XXX: PCIE/AGP differ*/ - case nv_clk_src_core: - return read_clk(priv, (mast & 0x00000003) >> 0); - case nv_clk_src_shader: - return read_clk(priv, (mast & 0x00000030) >> 4); - case nv_clk_src_mem: - return read_pll_2(priv, 0x4020); - default: - break; - } - - nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); - return -EINVAL; -} - -static int -nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk, - int *N1, int *M1, int *N2, int *M2, int *log2P) -{ - struct nouveau_bios *bios = nouveau_bios(priv); - struct nvbios_pll pll; - int ret; - - ret = nvbios_pll_parse(bios, reg, &pll); - if (ret) - return ret; - - if (clk < pll.vco1.max_freq) - pll.vco2.max_freq = 0; - - ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); - if (ret == 0) - return -ERANGE; - return ret; -} - -static int -nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct nv40_clock_priv *priv = (void *)clk; - int gclk = cstate->domain[nv_clk_src_core]; - int sclk = cstate->domain[nv_clk_src_shader]; - int N1, M1, N2, M2, log2P; - int ret; - - /* core/geometric clock */ - ret = nv40_clock_calc_pll(priv, 0x004000, gclk, - &N1, &M1, &N2, &M2, &log2P); - if (ret < 0) - return ret; - - if (N2 == M2) { - priv->npll_ctrl = 0x80000100 | (log2P << 16); - priv->npll_coef = (N1 << 8) | M1; - } else { - priv->npll_ctrl = 0xc0000000 | (log2P << 16); - priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; - } - - /* use the second pll for shader/rop clock, if it differs from core */ - if (sclk && sclk != gclk) { - ret = nv40_clock_calc_pll(priv, 0x004008, sclk, - &N1, &M1, NULL, NULL, &log2P); - if (ret < 0) - return ret; - - priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; - priv->ctrl = 0x00000223; - } else { - priv->spll = 0x00000000; - priv->ctrl = 0x00000333; - } - - return 0; -} - -static int -nv40_clock_prog(struct nouveau_clock *clk) -{ - struct nv40_clock_priv *priv = (void *)clk; - nv_mask(priv, 0x00c040, 0x00000333, 0x00000000); - nv_wr32(priv, 0x004004, priv->npll_coef); - nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl); - nv_mask(priv, 0x004008, 0xc007ffff, priv->spll); - mdelay(5); - nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl); - return 0; -} - -static void -nv40_clock_tidy(struct nouveau_clock *clk) -{ -} - -static int -nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv40_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0, - true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.pll_calc = nv04_clock_pll_calc; - priv->base.pll_prog = nv04_clock_pll_prog; - priv->base.read = nv40_clock_read; - priv->base.calc = nv40_clock_calc; - priv->base.prog = nv40_clock_prog; - priv->base.tidy = nv40_clock_tidy; - return 0; -} - -struct nouveau_oclass -nv40_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c deleted file mode 100644 index 5070ebc260f8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include "nv50.h" -#include "pll.h" -#include "seq.h" - -static u32 -read_div(struct nv50_clock_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0x50: /* it exists, but only has bit 31, not the dividers.. */ - case 0x84: - case 0x86: - case 0x98: - case 0xa0: - return nv_rd32(priv, 0x004700); - case 0x92: - case 0x94: - case 0x96: - return nv_rd32(priv, 0x004800); - default: - return 0x00000000; - } -} - -static u32 -read_pll_src(struct nv50_clock_priv *priv, u32 base) -{ - struct nouveau_clock *clk = &priv->base; - u32 coef, ref = clk->read(clk, nv_clk_src_crystal); - u32 rsel = nv_rd32(priv, 0x00e18c); - int P, N, M, id; - - switch (nv_device(priv)->chipset) { - case 0x50: - case 0xa0: - switch (base) { - case 0x4020: - case 0x4028: id = !!(rsel & 0x00000004); break; - case 0x4008: id = !!(rsel & 0x00000008); break; - case 0x4030: id = 0; break; - default: - nv_error(priv, "ref: bad pll 0x%06x\n", base); - return 0; - } - - coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); - ref *= (coef & 0x01000000) ? 2 : 4; - P = (coef & 0x00070000) >> 16; - N = ((coef & 0x0000ff00) >> 8) + 1; - M = ((coef & 0x000000ff) >> 0) + 1; - break; - case 0x84: - case 0x86: - case 0x92: - coef = nv_rd32(priv, 0x00e81c); - P = (coef & 0x00070000) >> 16; - N = (coef & 0x0000ff00) >> 8; - M = (coef & 0x000000ff) >> 0; - break; - case 0x94: - case 0x96: - case 0x98: - rsel = nv_rd32(priv, 0x00c050); - switch (base) { - case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; - case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; - case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; - case 0x4030: rsel = 3; break; - default: - nv_error(priv, "ref: bad pll 0x%06x\n", base); - return 0; - } - - switch (rsel) { - case 0: id = 1; break; - case 1: return clk->read(clk, nv_clk_src_crystal); - case 2: return clk->read(clk, nv_clk_src_href); - case 3: id = 0; break; - } - - coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); - P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; - P += (coef & 0x00070000) >> 16; - N = (coef & 0x0000ff00) >> 8; - M = (coef & 0x000000ff) >> 0; - break; - default: - BUG_ON(1); - } - - if (M) - return (ref * N / M) >> P; - return 0; -} - -static u32 -read_pll_ref(struct nv50_clock_priv *priv, u32 base) -{ - struct nouveau_clock *clk = &priv->base; - u32 src, mast = nv_rd32(priv, 0x00c040); - - switch (base) { - case 0x004028: - src = !!(mast & 0x00200000); - break; - case 0x004020: - src = !!(mast & 0x00400000); - break; - case 0x004008: - src = !!(mast & 0x00010000); - break; - case 0x004030: - src = !!(mast & 0x02000000); - break; - case 0x00e810: - return clk->read(clk, nv_clk_src_crystal); - default: - nv_error(priv, "bad pll 0x%06x\n", base); - return 0; - } - - if (src) - return clk->read(clk, nv_clk_src_href); - return read_pll_src(priv, base); -} - -static u32 -read_pll(struct nv50_clock_priv *priv, u32 base) -{ - struct nouveau_clock *clk = &priv->base; - u32 mast = nv_rd32(priv, 0x00c040); - u32 ctrl = nv_rd32(priv, base + 0); - u32 coef = nv_rd32(priv, base + 4); - u32 ref = read_pll_ref(priv, base); - u32 freq = 0; - int N1, N2, M1, M2; - - if (base == 0x004028 && (mast & 0x00100000)) { - /* wtf, appears to only disable post-divider on nva0 */ - if (nv_device(priv)->chipset != 0xa0) - return clk->read(clk, nv_clk_src_dom6); - } - - N2 = (coef & 0xff000000) >> 24; - M2 = (coef & 0x00ff0000) >> 16; - N1 = (coef & 0x0000ff00) >> 8; - M1 = (coef & 0x000000ff); - if ((ctrl & 0x80000000) && M1) { - freq = ref * N1 / M1; - if ((ctrl & 0x40000100) == 0x40000000) { - if (M2) - freq = freq * N2 / M2; - else - freq = 0; - } - } - - return freq; -} - -static int -nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct nv50_clock_priv *priv = (void *)clk; - u32 mast = nv_rd32(priv, 0x00c040); - u32 P = 0; - - switch (src) { - case nv_clk_src_crystal: - return nv_device(priv)->crystal; - case nv_clk_src_href: - return 100000; /* PCIE reference clock */ - case nv_clk_src_hclk: - return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); - case nv_clk_src_hclkm3: - return clk->read(clk, nv_clk_src_hclk) * 3; - case nv_clk_src_hclkm3d2: - return clk->read(clk, nv_clk_src_hclk) * 3 / 2; - case nv_clk_src_host: - switch (mast & 0x30000000) { - case 0x00000000: return clk->read(clk, nv_clk_src_href); - case 0x10000000: break; - case 0x20000000: /* !0x50 */ - case 0x30000000: return clk->read(clk, nv_clk_src_hclk); - } - break; - case nv_clk_src_core: - if (!(mast & 0x00100000)) - P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16; - switch (mast & 0x00000003) { - case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; - case 0x00000001: return clk->read(clk, nv_clk_src_dom6); - case 0x00000002: return read_pll(priv, 0x004020) >> P; - case 0x00000003: return read_pll(priv, 0x004028) >> P; - } - break; - case nv_clk_src_shader: - P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16; - switch (mast & 0x00000030) { - case 0x00000000: - if (mast & 0x00000080) - return clk->read(clk, nv_clk_src_host) >> P; - return clk->read(clk, nv_clk_src_crystal) >> P; - case 0x00000010: break; - case 0x00000020: return read_pll(priv, 0x004028) >> P; - case 0x00000030: return read_pll(priv, 0x004020) >> P; - } - break; - case nv_clk_src_mem: - P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16; - if (nv_rd32(priv, 0x004008) & 0x00000200) { - switch (mast & 0x0000c000) { - case 0x00000000: - return clk->read(clk, nv_clk_src_crystal) >> P; - case 0x00008000: - case 0x0000c000: - return clk->read(clk, nv_clk_src_href) >> P; - } - } else { - return read_pll(priv, 0x004008) >> P; - } - break; - case nv_clk_src_vdec: - P = (read_div(priv) & 0x00000700) >> 8; - switch (nv_device(priv)->chipset) { - case 0x84: - case 0x86: - case 0x92: - case 0x94: - case 0x96: - case 0xa0: - switch (mast & 0x00000c00) { - case 0x00000000: - if (nv_device(priv)->chipset == 0xa0) /* wtf?? */ - return clk->read(clk, nv_clk_src_core) >> P; - return clk->read(clk, nv_clk_src_crystal) >> P; - case 0x00000400: - return 0; - case 0x00000800: - if (mast & 0x01000000) - return read_pll(priv, 0x004028) >> P; - return read_pll(priv, 0x004030) >> P; - case 0x00000c00: - return clk->read(clk, nv_clk_src_core) >> P; - } - break; - case 0x98: - switch (mast & 0x00000c00) { - case 0x00000000: - return clk->read(clk, nv_clk_src_core) >> P; - case 0x00000400: - return 0; - case 0x00000800: - return clk->read(clk, nv_clk_src_hclkm3d2) >> P; - case 0x00000c00: - return clk->read(clk, nv_clk_src_mem) >> P; - } - break; - } - break; - case nv_clk_src_dom6: - switch (nv_device(priv)->chipset) { - case 0x50: - case 0xa0: - return read_pll(priv, 0x00e810) >> 2; - case 0x84: - case 0x86: - case 0x92: - case 0x94: - case 0x96: - case 0x98: - P = (read_div(priv) & 0x00000007) >> 0; - switch (mast & 0x0c000000) { - case 0x00000000: return clk->read(clk, nv_clk_src_href); - case 0x04000000: break; - case 0x08000000: return clk->read(clk, nv_clk_src_hclk); - case 0x0c000000: - return clk->read(clk, nv_clk_src_hclkm3) >> P; - } - break; - default: - break; - } - default: - break; - } - - nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); - return -EINVAL; -} - -static u32 -calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) -{ - struct nouveau_bios *bios = nouveau_bios(priv); - struct nvbios_pll pll; - int ret; - - ret = nvbios_pll_parse(bios, reg, &pll); - if (ret) - return 0; - - pll.vco2.max_freq = 0; - pll.refclk = read_pll_ref(priv, reg); - if (!pll.refclk) - return 0; - - return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); -} - -static inline u32 -calc_div(u32 src, u32 target, int *div) -{ - u32 clk0 = src, clk1 = src; - for (*div = 0; *div <= 7; (*div)++) { - if (clk0 <= target) { - clk1 = clk0 << (*div ? 1 : 0); - break; - } - clk0 >>= 1; - } - - if (target - clk0 <= clk1 - target) - return clk0; - (*div)--; - return clk1; -} - -static inline u32 -clk_same(u32 a, u32 b) -{ - return ((a / 1000) == (b / 1000)); -} - -static int -nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct nv50_clock_priv *priv = (void *)clk; - struct nv50_clock_hwsq *hwsq = &priv->hwsq; - const int shader = cstate->domain[nv_clk_src_shader]; - const int core = cstate->domain[nv_clk_src_core]; - const int vdec = cstate->domain[nv_clk_src_vdec]; - const int dom6 = cstate->domain[nv_clk_src_dom6]; - u32 mastm = 0, mastv = 0; - u32 divsm = 0, divsv = 0; - int N, M, P1, P2; - int freq, out; - - /* prepare a hwsq script from which we'll perform the reclock */ - out = clk_init(hwsq, nv_subdev(clk)); - if (out) - return out; - - clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ - clk_nsec(hwsq, 8000); - clk_setf(hwsq, 0x10, 0x00); /* disable fb */ - clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ - - /* vdec: avoid modifying xpll until we know exactly how the other - * clock domains work, i suspect at least some of them can also be - * tied to xpll... - */ - if (vdec) { - /* see how close we can get using nvclk as a source */ - freq = calc_div(core, vdec, &P1); - - /* see how close we can get using xpll/hclk as a source */ - if (nv_device(priv)->chipset != 0x98) - out = read_pll(priv, 0x004030); - else - out = clk->read(clk, nv_clk_src_hclkm3d2); - out = calc_div(out, vdec, &P2); - - /* select whichever gets us closest */ - if (abs(vdec - freq) <= abs(vdec - out)) { - if (nv_device(priv)->chipset != 0x98) - mastv |= 0x00000c00; - divsv |= P1 << 8; - } else { - mastv |= 0x00000800; - divsv |= P2 << 8; - } - - mastm |= 0x00000c00; - divsm |= 0x00000700; - } - - /* dom6: nfi what this is, but we're limited to various combinations - * of the host clock frequency - */ - if (dom6) { - if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { - mastv |= 0x00000000; - } else - if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { - mastv |= 0x08000000; - } else { - freq = clk->read(clk, nv_clk_src_hclk) * 3; - freq = calc_div(freq, dom6, &P1); - - mastv |= 0x0c000000; - divsv |= P1; - } - - mastm |= 0x0c000000; - divsm |= 0x00000007; - } - - /* vdec/dom6: switch to "safe" clocks temporarily, update dividers - * and then switch to target clocks - */ - clk_mask(hwsq, mast, mastm, 0x00000000); - clk_mask(hwsq, divs, divsm, divsv); - clk_mask(hwsq, mast, mastm, mastv); - - /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, - * sclk to hclk) before reprogramming - */ - if (nv_device(priv)->chipset < 0x92) - clk_mask(hwsq, mast, 0x001000b0, 0x00100080); - else - clk_mask(hwsq, mast, 0x000000b3, 0x00000081); - - /* core: for the moment at least, always use nvpll */ - freq = calc_pll(priv, 0x4028, core, &N, &M, &P1); - if (freq == 0) - return -ERANGE; - - clk_mask(hwsq, nvpll[0], 0xc03f0100, - 0x80000000 | (P1 << 19) | (P1 << 16)); - clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); - - /* shader: tie to nvclk if possible, otherwise use spll. have to be - * very careful that the shader clock is at least twice the core, or - * some chipsets will be very unhappy. i expect most or all of these - * cases will be handled by tying to nvclk, but it's possible there's - * corners - */ - if (P1-- && shader == (core << 1)) { - clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); - clk_mask(hwsq, mast, 0x00100033, 0x00000023); - } else { - freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1); - if (freq == 0) - return -ERANGE; - - clk_mask(hwsq, spll[0], 0xc03f0100, - 0x80000000 | (P1 << 19) | (P1 << 16)); - clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); - clk_mask(hwsq, mast, 0x00100033, 0x00000033); - } - - /* restore normal operation */ - clk_setf(hwsq, 0x10, 0x01); /* enable fb */ - clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ - clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ - return 0; -} - -static int -nv50_clock_prog(struct nouveau_clock *clk) -{ - struct nv50_clock_priv *priv = (void *)clk; - return clk_exec(&priv->hwsq, true); -} - -static void -nv50_clock_tidy(struct nouveau_clock *clk) -{ - struct nv50_clock_priv *priv = (void *)clk; - clk_exec(&priv->hwsq, false); -} - -int -nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv50_clock_oclass *pclass = (void *)oclass; - struct nv50_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, pclass->domains, - NULL, 0, false, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->hwsq.r_fifo = hwsq_reg(0x002504); - priv->hwsq.r_spll[0] = hwsq_reg(0x004020); - priv->hwsq.r_spll[1] = hwsq_reg(0x004024); - priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028); - priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); - switch (nv_device(priv)->chipset) { - case 0x92: - case 0x94: - case 0x96: - priv->hwsq.r_divs = hwsq_reg(0x004800); - break; - default: - priv->hwsq.r_divs = hwsq_reg(0x004700); - break; - } - priv->hwsq.r_mast = hwsq_reg(0x00c040); - - priv->base.read = nv50_clock_read; - priv->base.calc = nv50_clock_calc; - priv->base.prog = nv50_clock_prog; - priv->base.tidy = nv50_clock_tidy; - return 0; -} - -static struct nouveau_clocks -nv50_domains[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_core , 0xff, 0, "core", 1000 }, - { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, - { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, - { nv_clk_src_max } -}; - -struct nouveau_oclass * -nv50_clock_oclass = &(struct nv50_clock_oclass) { - .base.handle = NV_SUBDEV(CLOCK, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, - .domains = nv50_domains, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h deleted file mode 100644 index f10917d789e8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NVKM_CLK_NV50_H__ -#define __NVKM_CLK_NV50_H__ - -#include -#include -#include - -struct nv50_clock_hwsq { - struct hwsq base; - struct hwsq_reg r_fifo; - struct hwsq_reg r_spll[2]; - struct hwsq_reg r_nvpll[2]; - struct hwsq_reg r_divs; - struct hwsq_reg r_mast; -}; - -struct nv50_clock_priv { - struct nouveau_clock base; - struct nv50_clock_hwsq hwsq; -}; - -int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -struct nv50_clock_oclass { - struct nouveau_oclass base; - struct nouveau_clocks *domains; -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c deleted file mode 100644 index b0b7c1437f10..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv50.h" - -static struct nouveau_clocks -nv84_domains[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_core , 0xff, 0, "core", 1000 }, - { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, - { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, - { nv_clk_src_vdec , 0xff }, - { nv_clk_src_max } -}; - -struct nouveau_oclass * -nv84_clock_oclass = &(struct nv50_clock_oclass) { - .base.handle = NV_SUBDEV(CLOCK, 0x84), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, - .domains = nv84_domains, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c deleted file mode 100644 index 07ad01247675..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c +++ /dev/null @@ -1,534 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - * Roy Spliet - */ - -#include -#include -#include -#include - -#include "pll.h" - -#include "nva3.h" - -struct nva3_clock_priv { - struct nouveau_clock base; - struct nva3_clock_info eng[nv_clk_src_max]; -}; - -static u32 read_clk(struct nva3_clock_priv *, int, bool); -static u32 read_pll(struct nva3_clock_priv *, int, u32); - -static u32 -read_vco(struct nva3_clock_priv *priv, int clk) -{ - u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); - - switch (sctl & 0x00000030) { - case 0x00000000: - return nv_device(priv)->crystal; - case 0x00000020: - return read_pll(priv, 0x41, 0x00e820); - case 0x00000030: - return read_pll(priv, 0x42, 0x00e8a0); - default: - return 0; - } -} - -static u32 -read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) -{ - u32 sctl, sdiv, sclk; - - /* refclk for the 0xe8xx plls is a fixed frequency */ - if (clk >= 0x40) { - if (nv_device(priv)->chipset == 0xaf) { - /* no joke.. seriously.. sigh.. */ - return nv_rd32(priv, 0x00471c) * 1000; - } - - return nv_device(priv)->crystal; - } - - sctl = nv_rd32(priv, 0x4120 + (clk * 4)); - if (!ignore_en && !(sctl & 0x00000100)) - return 0; - - /* out_alt */ - if (sctl & 0x00000400) - return 108000; - - /* vco_out */ - switch (sctl & 0x00003000) { - case 0x00000000: - if (!(sctl & 0x00000200)) - return nv_device(priv)->crystal; - return 0; - case 0x00002000: - if (sctl & 0x00000040) - return 108000; - return 100000; - case 0x00003000: - /* vco_enable */ - if (!(sctl & 0x00000001)) - return 0; - - sclk = read_vco(priv, clk); - sdiv = ((sctl & 0x003f0000) >> 16) + 2; - return (sclk * 2) / sdiv; - default: - return 0; - } -} - -static u32 -read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) -{ - u32 ctrl = nv_rd32(priv, pll + 0); - u32 sclk = 0, P = 1, N = 1, M = 1; - - if (!(ctrl & 0x00000008)) { - if (ctrl & 0x00000001) { - u32 coef = nv_rd32(priv, pll + 4); - M = (coef & 0x000000ff) >> 0; - N = (coef & 0x0000ff00) >> 8; - P = (coef & 0x003f0000) >> 16; - - /* no post-divider on these.. - * XXX: it looks more like two post-"dividers" that - * cross each other out in the default RPLL config */ - if ((pll & 0x00ff00) == 0x00e800) - P = 1; - - sclk = read_clk(priv, 0x00 + clk, false); - } - } else { - sclk = read_clk(priv, 0x10 + clk, false); - } - - if (M * P) - return sclk * N / (M * P); - return 0; -} - -static int -nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct nva3_clock_priv *priv = (void *)clk; - u32 hsrc; - - switch (src) { - case nv_clk_src_crystal: - return nv_device(priv)->crystal; - case nv_clk_src_core: - case nv_clk_src_core_intm: - return read_pll(priv, 0x00, 0x4200); - case nv_clk_src_shader: - return read_pll(priv, 0x01, 0x4220); - case nv_clk_src_mem: - return read_pll(priv, 0x02, 0x4000); - case nv_clk_src_disp: - return read_clk(priv, 0x20, false); - case nv_clk_src_vdec: - return read_clk(priv, 0x21, false); - case nv_clk_src_daemon: - return read_clk(priv, 0x25, false); - case nv_clk_src_host: - hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; - switch (hsrc) { - case 0: - return read_clk(priv, 0x1d, false); - case 2: - case 3: - return 277000; - default: - nv_error(clk, "unknown HOST clock source %d\n", hsrc); - return -EINVAL; - } - default: - nv_error(clk, "invalid clock source %d\n", src); - return -EINVAL; - } - - return 0; -} - -int -nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, - struct nva3_clock_info *info) -{ - struct nva3_clock_priv *priv = (void *)clock; - u32 oclk, sclk, sdiv, diff; - - info->clk = 0; - - switch (khz) { - case 27000: - info->clk = 0x00000100; - return khz; - case 100000: - info->clk = 0x00002100; - return khz; - case 108000: - info->clk = 0x00002140; - return khz; - default: - sclk = read_vco(priv, clk); - sdiv = min((sclk * 2) / khz, (u32)65); - oclk = (sclk * 2) / sdiv; - diff = ((khz + 3000) - oclk); - - /* When imprecise, play it safe and aim for a clock lower than - * desired rather than higher */ - if (diff < 0) { - sdiv++; - oclk = (sclk * 2) / sdiv; - } - - /* divider can go as low as 2, limited here because NVIDIA - * and the VBIOS on my NVA8 seem to prefer using the PLL - * for 810MHz - is there a good reason? - * XXX: PLLs with refclk 810MHz? */ - if (sdiv > 4) { - info->clk = (((sdiv - 2) << 16) | 0x00003100); - return oclk; - } - - break; - } - - return -ERANGE; -} - -int -nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, - struct nva3_clock_info *info) -{ - struct nouveau_bios *bios = nouveau_bios(clock); - struct nva3_clock_priv *priv = (void *)clock; - struct nvbios_pll limits; - int P, N, M, diff; - int ret; - - info->pll = 0; - - /* If we can get a within [-2, 3) MHz of a divider, we'll disable the - * PLL and use the divider instead. */ - ret = nva3_clk_info(clock, clk, khz, info); - diff = khz - ret; - if (!pll || (diff >= -2000 && diff < 3000)) { - goto out; - } - - /* Try with PLL */ - ret = nvbios_pll_parse(bios, pll, &limits); - if (ret) - return ret; - - ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); - if (ret != limits.refclk) - return -EINVAL; - - ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); - if (ret >= 0) { - info->pll = (P << 16) | (N << 8) | M; - } - -out: - info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); - - return ret ? ret : -ERANGE; -} - -static int -calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, - int clk, u32 pll, int idx) -{ - int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], - &priv->eng[idx]); - if (ret >= 0) - return 0; - return ret; -} - -static int -calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) -{ - int ret = 0; - u32 kHz = cstate->domain[nv_clk_src_host]; - struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; - - if (kHz == 277000) { - info->clk = 0; - info->host_out = NVA3_HOST_277; - return 0; - } - - info->host_out = NVA3_HOST_CLK; - - ret = nva3_clk_info(&priv->base, 0x1d, kHz, info); - if (ret >= 0) - return 0; - return ret; -} - -int -nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(clk); - - /* halt and idle execution engines */ - nv_mask(clk, 0x020060, 0x00070000, 0x00000000); - nv_mask(clk, 0x002504, 0x00000001, 0x00000001); - /* Wait until the interrupt handler is finished */ - if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) - return -EBUSY; - - if (pfifo) - pfifo->pause(pfifo, flags); - - if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) - return -EIO; - if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) - return -EIO; - - return 0; -} - -void -nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(clk); - - if (pfifo && flags) - pfifo->start(pfifo, flags); - - nv_mask(clk, 0x002504, 0x00000001, 0x00000000); - nv_mask(clk, 0x020060, 0x00070000, 0x00040000); -} - -static void -disable_clk_src(struct nva3_clock_priv *priv, u32 src) -{ - nv_mask(priv, src, 0x00000100, 0x00000000); - nv_mask(priv, src, 0x00000001, 0x00000000); -} - -static void -prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) -{ - struct nva3_clock_info *info = &priv->eng[idx]; - const u32 src0 = 0x004120 + (clk * 4); - const u32 src1 = 0x004160 + (clk * 4); - const u32 ctrl = pll + 0; - const u32 coef = pll + 4; - u32 bypass; - - if (info->pll) { - /* Always start from a non-PLL clock */ - bypass = nv_rd32(priv, ctrl) & 0x00000008; - if (!bypass) { - nv_mask(priv, src1, 0x00000101, 0x00000101); - nv_mask(priv, ctrl, 0x00000008, 0x00000008); - udelay(20); - } - - nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); - nv_wr32(priv, coef, info->pll); - nv_mask(priv, ctrl, 0x00000015, 0x00000015); - nv_mask(priv, ctrl, 0x00000010, 0x00000000); - if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { - nv_mask(priv, ctrl, 0x00000010, 0x00000010); - nv_mask(priv, src0, 0x00000101, 0x00000000); - return; - } - nv_mask(priv, ctrl, 0x00000010, 0x00000010); - nv_mask(priv, ctrl, 0x00000008, 0x00000000); - disable_clk_src(priv, src1); - } else { - nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); - nv_mask(priv, ctrl, 0x00000018, 0x00000018); - udelay(20); - nv_mask(priv, ctrl, 0x00000001, 0x00000000); - disable_clk_src(priv, src0); - } -} - -static void -prog_clk(struct nva3_clock_priv *priv, int clk, int idx) -{ - struct nva3_clock_info *info = &priv->eng[idx]; - nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); -} - -static void -prog_host(struct nva3_clock_priv *priv) -{ - struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; - u32 hsrc = (nv_rd32(priv, 0xc040)); - - switch (info->host_out) { - case NVA3_HOST_277: - if ((hsrc & 0x30000000) == 0) { - nv_wr32(priv, 0xc040, hsrc | 0x20000000); - disable_clk_src(priv, 0x4194); - } - break; - case NVA3_HOST_CLK: - prog_clk(priv, 0x1d, nv_clk_src_host); - if ((hsrc & 0x30000000) >= 0x20000000) { - nv_wr32(priv, 0xc040, hsrc & ~0x30000000); - } - break; - default: - break; - } - - /* This seems to be a clock gating factor on idle, always set to 64 */ - nv_wr32(priv, 0xc044, 0x3e); -} - -static void -prog_core(struct nva3_clock_priv *priv, int idx) -{ - struct nva3_clock_info *info = &priv->eng[idx]; - u32 fb_delay = nv_rd32(priv, 0x10002c); - - if (fb_delay < info->fb_delay) - nv_wr32(priv, 0x10002c, info->fb_delay); - - prog_pll(priv, 0x00, 0x004200, idx); - - if (fb_delay > info->fb_delay) - nv_wr32(priv, 0x10002c, info->fb_delay); -} - -static int -nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct nva3_clock_priv *priv = (void *)clk; - struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; - int ret; - - if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || - (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || - (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || - (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || - (ret = calc_host(priv, cstate))) - return ret; - - /* XXX: Should be reading the highest bit in the VBIOS clock to decide - * whether to use a PLL or not... but using a PLL defeats the purpose */ - if (core->pll) { - ret = nva3_clk_info(clk, 0x10, - cstate->domain[nv_clk_src_core_intm], - &priv->eng[nv_clk_src_core_intm]); - if (ret < 0) - return ret; - } - - return 0; -} - -static int -nva3_clock_prog(struct nouveau_clock *clk) -{ - struct nva3_clock_priv *priv = (void *)clk; - struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; - int ret = 0; - unsigned long flags; - unsigned long *f = &flags; - - ret = nva3_clock_pre(clk, f); - if (ret) - goto out; - - if (core->pll) - prog_core(priv, nv_clk_src_core_intm); - - prog_core(priv, nv_clk_src_core); - prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); - prog_clk(priv, 0x20, nv_clk_src_disp); - prog_clk(priv, 0x21, nv_clk_src_vdec); - prog_host(priv); - -out: - if (ret == -EBUSY) - f = NULL; - - nva3_clock_post(clk, f); - - return ret; -} - -static void -nva3_clock_tidy(struct nouveau_clock *clk) -{ -} - -static struct nouveau_clocks -nva3_domain[] = { - { nv_clk_src_crystal , 0xff }, - { nv_clk_src_core , 0x00, 0, "core", 1000 }, - { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, - { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, - { nv_clk_src_vdec , 0x03 }, - { nv_clk_src_disp , 0x04 }, - { nv_clk_src_host , 0x05 }, - { nv_clk_src_core_intm, 0x06 }, - { nv_clk_src_max } -}; - -static int -nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nva3_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0, - true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.read = nva3_clock_read; - priv->base.calc = nva3_clock_calc; - priv->base.prog = nva3_clock_prog; - priv->base.tidy = nva3_clock_tidy; - return 0; -} - -struct nouveau_oclass -nva3_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h deleted file mode 100644 index a45a1038b12f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __NVKM_CLK_NVA3_H__ -#define __NVKM_CLK_NVA3_H__ - -#include - -struct nva3_clock_info { - u32 clk; - u32 pll; - enum { - NVA3_HOST_277, - NVA3_HOST_CLK, - } host_out; - u32 fb_delay; -}; - -int nva3_pll_info(struct nouveau_clock *, int, u32, u32, - struct nva3_clock_info *); -int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags); -void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c deleted file mode 100644 index 54aeab8005a0..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include -#include - -#include "nva3.h" -#include "pll.h" - -struct nvaa_clock_priv { - struct nouveau_clock base; - enum nv_clk_src csrc, ssrc, vsrc; - u32 cctrl, sctrl; - u32 ccoef, scoef; - u32 cpost, spost; - u32 vdiv; -}; - -static u32 -read_div(struct nouveau_clock *clk) -{ - return nv_rd32(clk, 0x004600); -} - -static u32 -read_pll(struct nouveau_clock *clk, u32 base) -{ - u32 ctrl = nv_rd32(clk, base + 0); - u32 coef = nv_rd32(clk, base + 4); - u32 ref = clk->read(clk, nv_clk_src_href); - u32 post_div = 0; - u32 clock = 0; - int N1, M1; - - switch (base){ - case 0x4020: - post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); - break; - case 0x4028: - post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; - break; - default: - break; - } - - N1 = (coef & 0x0000ff00) >> 8; - M1 = (coef & 0x000000ff); - if ((ctrl & 0x80000000) && M1) { - clock = ref * N1 / M1; - clock = clock / post_div; - } - - return clock; -} - -static int -nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct nvaa_clock_priv *priv = (void *)clk; - u32 mast = nv_rd32(clk, 0x00c054); - u32 P = 0; - - switch (src) { - case nv_clk_src_crystal: - return nv_device(priv)->crystal; - case nv_clk_src_href: - return 100000; /* PCIE reference clock */ - case nv_clk_src_hclkm4: - return clk->read(clk, nv_clk_src_href) * 4; - case nv_clk_src_hclkm2d3: - return clk->read(clk, nv_clk_src_href) * 2 / 3; - case nv_clk_src_host: - switch (mast & 0x000c0000) { - case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3); - case 0x00040000: break; - case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4); - case 0x000c0000: return clk->read(clk, nv_clk_src_cclk); - } - break; - case nv_clk_src_core: - P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; - - switch (mast & 0x00000003) { - case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; - case 0x00000001: return 0; - case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P; - case 0x00000003: return read_pll(clk, 0x004028) >> P; - } - break; - case nv_clk_src_cclk: - if ((mast & 0x03000000) != 0x03000000) - return clk->read(clk, nv_clk_src_core); - - if ((mast & 0x00000200) == 0x00000000) - return clk->read(clk, nv_clk_src_core); - - switch (mast & 0x00000c00) { - case 0x00000000: return clk->read(clk, nv_clk_src_href); - case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4); - case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3); - default: return 0; - } - case nv_clk_src_shader: - P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; - switch (mast & 0x00000030) { - case 0x00000000: - if (mast & 0x00000040) - return clk->read(clk, nv_clk_src_href) >> P; - return clk->read(clk, nv_clk_src_crystal) >> P; - case 0x00000010: break; - case 0x00000020: return read_pll(clk, 0x004028) >> P; - case 0x00000030: return read_pll(clk, 0x004020) >> P; - } - break; - case nv_clk_src_mem: - return 0; - break; - case nv_clk_src_vdec: - P = (read_div(clk) & 0x00000700) >> 8; - - switch (mast & 0x00400000) { - case 0x00400000: - return clk->read(clk, nv_clk_src_core) >> P; - break; - default: - return 500000 >> P; - break; - } - break; - default: - break; - } - - nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); - return 0; -} - -static u32 -calc_pll(struct nvaa_clock_priv *priv, u32 reg, - u32 clock, int *N, int *M, int *P) -{ - struct nouveau_bios *bios = nouveau_bios(priv); - struct nvbios_pll pll; - struct nouveau_clock *clk = &priv->base; - int ret; - - ret = nvbios_pll_parse(bios, reg, &pll); - if (ret) - return 0; - - pll.vco2.max_freq = 0; - pll.refclk = clk->read(clk, nv_clk_src_href); - if (!pll.refclk) - return 0; - - return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); -} - -static inline u32 -calc_P(u32 src, u32 target, int *div) -{ - u32 clk0 = src, clk1 = src; - for (*div = 0; *div <= 7; (*div)++) { - if (clk0 <= target) { - clk1 = clk0 << (*div ? 1 : 0); - break; - } - clk0 >>= 1; - } - - if (target - clk0 <= clk1 - target) - return clk0; - (*div)--; - return clk1; -} - -static int -nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct nvaa_clock_priv *priv = (void *)clk; - const int shader = cstate->domain[nv_clk_src_shader]; - const int core = cstate->domain[nv_clk_src_core]; - const int vdec = cstate->domain[nv_clk_src_vdec]; - u32 out = 0, clock = 0; - int N, M, P1, P2 = 0; - int divs = 0; - - /* cclk: find suitable source, disable PLL if we can */ - if (core < clk->read(clk, nv_clk_src_hclkm4)) - out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs); - - /* Calculate clock * 2, so shader clock can use it too */ - clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1); - - if (abs(core - out) <= - abs(core - (clock >> 1))) { - priv->csrc = nv_clk_src_hclkm4; - priv->cctrl = divs << 16; - } else { - /* NVCTRL is actually used _after_ NVPOST, and after what we - * call NVPLL. To make matters worse, NVPOST is an integer - * divider instead of a right-shift number. */ - if(P1 > 2) { - P2 = P1 - 2; - P1 = 2; - } - - priv->csrc = nv_clk_src_core; - priv->ccoef = (N << 8) | M; - - priv->cctrl = (P2 + 1) << 16; - priv->cpost = (1 << P1) << 16; - } - - /* sclk: nvpll + divisor, href or spll */ - out = 0; - if (shader == clk->read(clk, nv_clk_src_href)) { - priv->ssrc = nv_clk_src_href; - } else { - clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1); - if (priv->csrc == nv_clk_src_core) { - out = calc_P((core << 1), shader, &divs); - } - - if (abs(shader - out) <= - abs(shader - clock) && - (divs + P2) <= 7) { - priv->ssrc = nv_clk_src_core; - priv->sctrl = (divs + P2) << 16; - } else { - priv->ssrc = nv_clk_src_shader; - priv->scoef = (N << 8) | M; - priv->sctrl = P1 << 16; - } - } - - /* vclk */ - out = calc_P(core, vdec, &divs); - clock = calc_P(500000, vdec, &P1); - if(abs(vdec - out) <= - abs(vdec - clock)) { - priv->vsrc = nv_clk_src_cclk; - priv->vdiv = divs << 16; - } else { - priv->vsrc = nv_clk_src_vdec; - priv->vdiv = P1 << 16; - } - - /* Print strategy! */ - nv_debug(priv, "nvpll: %08x %08x %08x\n", - priv->ccoef, priv->cpost, priv->cctrl); - nv_debug(priv, " spll: %08x %08x %08x\n", - priv->scoef, priv->spost, priv->sctrl); - nv_debug(priv, " vdiv: %08x\n", priv->vdiv); - if (priv->csrc == nv_clk_src_hclkm4) - nv_debug(priv, "core: hrefm4\n"); - else - nv_debug(priv, "core: nvpll\n"); - - if (priv->ssrc == nv_clk_src_hclkm4) - nv_debug(priv, "shader: hrefm4\n"); - else if (priv->ssrc == nv_clk_src_core) - nv_debug(priv, "shader: nvpll\n"); - else - nv_debug(priv, "shader: spll\n"); - - if (priv->vsrc == nv_clk_src_hclkm4) - nv_debug(priv, "vdec: 500MHz\n"); - else - nv_debug(priv, "vdec: core\n"); - - return 0; -} - -static int -nvaa_clock_prog(struct nouveau_clock *clk) -{ - struct nvaa_clock_priv *priv = (void *)clk; - u32 pllmask = 0, mast; - unsigned long flags; - unsigned long *f = &flags; - int ret = 0; - - ret = nva3_clock_pre(clk, f); - if (ret) - goto out; - - /* First switch to safe clocks: href */ - mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); - mast &= ~0x00400e73; - mast |= 0x03000000; - - switch (priv->csrc) { - case nv_clk_src_hclkm4: - nv_mask(clk, 0x4028, 0x00070000, priv->cctrl); - mast |= 0x00000002; - break; - case nv_clk_src_core: - nv_wr32(clk, 0x402c, priv->ccoef); - nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl); - nv_wr32(clk, 0x4040, priv->cpost); - pllmask |= (0x3 << 8); - mast |= 0x00000003; - break; - default: - nv_warn(priv,"Reclocking failed: unknown core clock\n"); - goto resume; - } - - switch (priv->ssrc) { - case nv_clk_src_href: - nv_mask(clk, 0x4020, 0x00070000, 0x00000000); - /* mast |= 0x00000000; */ - break; - case nv_clk_src_core: - nv_mask(clk, 0x4020, 0x00070000, priv->sctrl); - mast |= 0x00000020; - break; - case nv_clk_src_shader: - nv_wr32(clk, 0x4024, priv->scoef); - nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl); - nv_wr32(clk, 0x4070, priv->spost); - pllmask |= (0x3 << 12); - mast |= 0x00000030; - break; - default: - nv_warn(priv,"Reclocking failed: unknown sclk clock\n"); - goto resume; - } - - if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { - nv_warn(priv,"Reclocking failed: unstable PLLs\n"); - goto resume; - } - - switch (priv->vsrc) { - case nv_clk_src_cclk: - mast |= 0x00400000; - default: - nv_wr32(clk, 0x4600, priv->vdiv); - } - - nv_wr32(clk, 0xc054, mast); - -resume: - /* Disable some PLLs and dividers when unused */ - if (priv->csrc != nv_clk_src_core) { - nv_wr32(clk, 0x4040, 0x00000000); - nv_mask(clk, 0x4028, 0x80000000, 0x00000000); - } - - if (priv->ssrc != nv_clk_src_shader) { - nv_wr32(clk, 0x4070, 0x00000000); - nv_mask(clk, 0x4020, 0x80000000, 0x00000000); - } - -out: - if (ret == -EBUSY) - f = NULL; - - nva3_clock_post(clk, f); - - return ret; -} - -static void -nvaa_clock_tidy(struct nouveau_clock *clk) -{ -} - -static struct nouveau_clocks -nvaa_domains[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_core , 0xff, 0, "core", 1000 }, - { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, - { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 }, - { nv_clk_src_max } -}; - -static int -nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvaa_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL, - 0, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.read = nvaa_clock_read; - priv->base.calc = nvaa_clock_calc; - priv->base.prog = nvaa_clock_prog; - priv->base.tidy = nvaa_clock_tidy; - return 0; -} - -struct nouveau_oclass * -nvaa_clock_oclass = &(struct nouveau_oclass) { - .handle = NV_SUBDEV(CLOCK, 0xaa), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvaa_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c deleted file mode 100644 index 1234abaab2db..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include - -#include "pll.h" - -struct nvc0_clock_info { - u32 freq; - u32 ssel; - u32 mdiv; - u32 dsrc; - u32 ddiv; - u32 coef; -}; - -struct nvc0_clock_priv { - struct nouveau_clock base; - struct nvc0_clock_info eng[16]; -}; - -static u32 read_div(struct nvc0_clock_priv *, int, u32, u32); - -static u32 -read_vco(struct nvc0_clock_priv *priv, u32 dsrc) -{ - struct nouveau_clock *clk = &priv->base; - u32 ssrc = nv_rd32(priv, dsrc); - if (!(ssrc & 0x00000100)) - return clk->read(clk, nv_clk_src_sppll0); - return clk->read(clk, nv_clk_src_sppll1); -} - -static u32 -read_pll(struct nvc0_clock_priv *priv, u32 pll) -{ - struct nouveau_clock *clk = &priv->base; - u32 ctrl = nv_rd32(priv, pll + 0x00); - u32 coef = nv_rd32(priv, pll + 0x04); - u32 P = (coef & 0x003f0000) >> 16; - u32 N = (coef & 0x0000ff00) >> 8; - u32 M = (coef & 0x000000ff) >> 0; - u32 sclk; - - if (!(ctrl & 0x00000001)) - return 0; - - switch (pll) { - case 0x00e800: - case 0x00e820: - sclk = nv_device(priv)->crystal; - P = 1; - break; - case 0x132000: - sclk = clk->read(clk, nv_clk_src_mpllsrc); - break; - case 0x132020: - sclk = clk->read(clk, nv_clk_src_mpllsrcref); - break; - case 0x137000: - case 0x137020: - case 0x137040: - case 0x1370e0: - sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); - break; - default: - return 0; - } - - return sclk * N / M / P; -} - -static u32 -read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) -{ - u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); - u32 sctl = nv_rd32(priv, dctl + (doff * 4)); - - switch (ssrc & 0x00000003) { - case 0: - if ((ssrc & 0x00030000) != 0x00030000) - return nv_device(priv)->crystal; - return 108000; - case 2: - return 100000; - case 3: - if (sctl & 0x80000000) { - u32 sclk = read_vco(priv, dsrc + (doff * 4)); - u32 sdiv = (sctl & 0x0000003f) + 2; - return (sclk * 2) / sdiv; - } - - return read_vco(priv, dsrc + (doff * 4)); - default: - return 0; - } -} - -static u32 -read_clk(struct nvc0_clock_priv *priv, int clk) -{ - u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); - u32 ssel = nv_rd32(priv, 0x137100); - u32 sclk, sdiv; - - if (ssel & (1 << clk)) { - if (clk < 7) - sclk = read_pll(priv, 0x137000 + (clk * 0x20)); - else - sclk = read_pll(priv, 0x1370e0); - sdiv = ((sctl & 0x00003f00) >> 8) + 2; - } else { - sclk = read_div(priv, clk, 0x137160, 0x1371d0); - sdiv = ((sctl & 0x0000003f) >> 0) + 2; - } - - if (sctl & 0x80000000) - return (sclk * 2) / sdiv; - - return sclk; -} - -static int -nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct nouveau_device *device = nv_device(clk); - struct nvc0_clock_priv *priv = (void *)clk; - - switch (src) { - case nv_clk_src_crystal: - return device->crystal; - case nv_clk_src_href: - return 100000; - case nv_clk_src_sppll0: - return read_pll(priv, 0x00e800); - case nv_clk_src_sppll1: - return read_pll(priv, 0x00e820); - - case nv_clk_src_mpllsrcref: - return read_div(priv, 0, 0x137320, 0x137330); - case nv_clk_src_mpllsrc: - return read_pll(priv, 0x132020); - case nv_clk_src_mpll: - return read_pll(priv, 0x132000); - case nv_clk_src_mdiv: - return read_div(priv, 0, 0x137300, 0x137310); - case nv_clk_src_mem: - if (nv_rd32(priv, 0x1373f0) & 0x00000002) - return clk->read(clk, nv_clk_src_mpll); - return clk->read(clk, nv_clk_src_mdiv); - - case nv_clk_src_gpc: - return read_clk(priv, 0x00); - case nv_clk_src_rop: - return read_clk(priv, 0x01); - case nv_clk_src_hubk07: - return read_clk(priv, 0x02); - case nv_clk_src_hubk06: - return read_clk(priv, 0x07); - case nv_clk_src_hubk01: - return read_clk(priv, 0x08); - case nv_clk_src_copy: - return read_clk(priv, 0x09); - case nv_clk_src_daemon: - return read_clk(priv, 0x0c); - case nv_clk_src_vdec: - return read_clk(priv, 0x0e); - default: - nv_error(clk, "invalid clock source %d\n", src); - return -EINVAL; - } -} - -static u32 -calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) -{ - u32 div = min((ref * 2) / freq, (u32)65); - if (div < 2) - div = 2; - - *ddiv = div - 2; - return (ref * 2) / div; -} - -static u32 -calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) -{ - u32 sclk; - - /* use one of the fixed frequencies if possible */ - *ddiv = 0x00000000; - switch (freq) { - case 27000: - case 108000: - *dsrc = 0x00000000; - if (freq == 108000) - *dsrc |= 0x00030000; - return freq; - case 100000: - *dsrc = 0x00000002; - return freq; - default: - *dsrc = 0x00000003; - break; - } - - /* otherwise, calculate the closest divider */ - sclk = read_vco(priv, 0x137160 + (clk * 4)); - if (clk < 7) - sclk = calc_div(priv, clk, sclk, freq, ddiv); - return sclk; -} - -static u32 -calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) -{ - struct nouveau_bios *bios = nouveau_bios(priv); - struct nvbios_pll limits; - int N, M, P, ret; - - ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); - if (ret) - return 0; - - limits.refclk = read_div(priv, clk, 0x137120, 0x137140); - if (!limits.refclk) - return 0; - - ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); - if (ret <= 0) - return 0; - - *coef = (P << 16) | (N << 8) | M; - return ret; -} - -static int -calc_clk(struct nvc0_clock_priv *priv, - struct nouveau_cstate *cstate, int clk, int dom) -{ - struct nvc0_clock_info *info = &priv->eng[clk]; - u32 freq = cstate->domain[dom]; - u32 src0, div0, div1D, div1P = 0; - u32 clk0, clk1 = 0; - - /* invalid clock domain */ - if (!freq) - return 0; - - /* first possible path, using only dividers */ - clk0 = calc_src(priv, clk, freq, &src0, &div0); - clk0 = calc_div(priv, clk, clk0, freq, &div1D); - - /* see if we can get any closer using PLLs */ - if (clk0 != freq && (0x00004387 & (1 << clk))) { - if (clk <= 7) - clk1 = calc_pll(priv, clk, freq, &info->coef); - else - clk1 = cstate->domain[nv_clk_src_hubk06]; - clk1 = calc_div(priv, clk, clk1, freq, &div1P); - } - - /* select the method which gets closest to target freq */ - if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { - info->dsrc = src0; - if (div0) { - info->ddiv |= 0x80000000; - info->ddiv |= div0 << 8; - info->ddiv |= div0; - } - if (div1D) { - info->mdiv |= 0x80000000; - info->mdiv |= div1D; - } - info->ssel = info->coef = 0; - info->freq = clk0; - } else { - if (div1P) { - info->mdiv |= 0x80000000; - info->mdiv |= div1P << 8; - } - info->ssel = (1 << clk); - info->freq = clk1; - } - - return 0; -} - -static int -nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct nvc0_clock_priv *priv = (void *)clk; - int ret; - - if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || - (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || - (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || - (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || - (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || - (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) || - (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || - (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) - return ret; - - return 0; -} - -static void -nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk) -{ - struct nvc0_clock_info *info = &priv->eng[clk]; - if (clk < 7 && !info->ssel) { - nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); - nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); - } -} - -static void -nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk) -{ - nv_mask(priv, 0x137100, (1 << clk), 0x00000000); - nv_wait(priv, 0x137100, (1 << clk), 0x00000000); -} - -static void -nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk) -{ - struct nvc0_clock_info *info = &priv->eng[clk]; - const u32 addr = 0x137000 + (clk * 0x20); - if (clk <= 7) { - nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); - nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); - if (info->coef) { - nv_wr32(priv, addr + 0x04, info->coef); - nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); - nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); - nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); - } - } -} - -static void -nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk) -{ - struct nvc0_clock_info *info = &priv->eng[clk]; - if (info->ssel) { - nv_mask(priv, 0x137100, (1 << clk), info->ssel); - nv_wait(priv, 0x137100, (1 << clk), info->ssel); - } -} - -static void -nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk) -{ - struct nvc0_clock_info *info = &priv->eng[clk]; - nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); -} - -static int -nvc0_clock_prog(struct nouveau_clock *clk) -{ - struct nvc0_clock_priv *priv = (void *)clk; - struct { - void (*exec)(struct nvc0_clock_priv *, int); - } stage[] = { - { nvc0_clock_prog_0 }, /* div programming */ - { nvc0_clock_prog_1 }, /* select div mode */ - { nvc0_clock_prog_2 }, /* (maybe) program pll */ - { nvc0_clock_prog_3 }, /* (maybe) select pll mode */ - { nvc0_clock_prog_4 }, /* final divider */ - }; - int i, j; - - for (i = 0; i < ARRAY_SIZE(stage); i++) { - for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { - if (!priv->eng[j].freq) - continue; - stage[i].exec(priv, j); - } - } - - return 0; -} - -static void -nvc0_clock_tidy(struct nouveau_clock *clk) -{ - struct nvc0_clock_priv *priv = (void *)clk; - memset(priv->eng, 0x00, sizeof(priv->eng)); -} - -static struct nouveau_clocks -nvc0_domain[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_hubk06 , 0x00 }, - { nv_clk_src_hubk01 , 0x01 }, - { nv_clk_src_copy , 0x02 }, - { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, - { nv_clk_src_rop , 0x04 }, - { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, - { nv_clk_src_vdec , 0x06 }, - { nv_clk_src_daemon , 0x0a }, - { nv_clk_src_hubk07 , 0x0b }, - { nv_clk_src_max } -}; - -static int -nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0, - false, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.read = nvc0_clock_read; - priv->base.calc = nvc0_clock_calc; - priv->base.prog = nvc0_clock_prog; - priv->base.tidy = nvc0_clock_tidy; - return 0; -} - -struct nouveau_oclass -nvc0_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c deleted file mode 100644 index 7eccad57512e..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c +++ /dev/null @@ -1,500 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include - -#include "pll.h" - -struct nve0_clock_info { - u32 freq; - u32 ssel; - u32 mdiv; - u32 dsrc; - u32 ddiv; - u32 coef; -}; - -struct nve0_clock_priv { - struct nouveau_clock base; - struct nve0_clock_info eng[16]; -}; - -static u32 read_div(struct nve0_clock_priv *, int, u32, u32); -static u32 read_pll(struct nve0_clock_priv *, u32); - -static u32 -read_vco(struct nve0_clock_priv *priv, u32 dsrc) -{ - u32 ssrc = nv_rd32(priv, dsrc); - if (!(ssrc & 0x00000100)) - return read_pll(priv, 0x00e800); - return read_pll(priv, 0x00e820); -} - -static u32 -read_pll(struct nve0_clock_priv *priv, u32 pll) -{ - u32 ctrl = nv_rd32(priv, pll + 0x00); - u32 coef = nv_rd32(priv, pll + 0x04); - u32 P = (coef & 0x003f0000) >> 16; - u32 N = (coef & 0x0000ff00) >> 8; - u32 M = (coef & 0x000000ff) >> 0; - u32 sclk; - u16 fN = 0xf000; - - if (!(ctrl & 0x00000001)) - return 0; - - switch (pll) { - case 0x00e800: - case 0x00e820: - sclk = nv_device(priv)->crystal; - P = 1; - break; - case 0x132000: - sclk = read_pll(priv, 0x132020); - P = (coef & 0x10000000) ? 2 : 1; - break; - case 0x132020: - sclk = read_div(priv, 0, 0x137320, 0x137330); - fN = nv_rd32(priv, pll + 0x10) >> 16; - break; - case 0x137000: - case 0x137020: - case 0x137040: - case 0x1370e0: - sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); - break; - default: - return 0; - } - - if (P == 0) - P = 1; - - sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); - return sclk / (M * P); -} - -static u32 -read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) -{ - u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); - u32 sctl = nv_rd32(priv, dctl + (doff * 4)); - - switch (ssrc & 0x00000003) { - case 0: - if ((ssrc & 0x00030000) != 0x00030000) - return nv_device(priv)->crystal; - return 108000; - case 2: - return 100000; - case 3: - if (sctl & 0x80000000) { - u32 sclk = read_vco(priv, dsrc + (doff * 4)); - u32 sdiv = (sctl & 0x0000003f) + 2; - return (sclk * 2) / sdiv; - } - - return read_vco(priv, dsrc + (doff * 4)); - default: - return 0; - } -} - -static u32 -read_mem(struct nve0_clock_priv *priv) -{ - switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { - case 1: return read_pll(priv, 0x132020); - case 2: return read_pll(priv, 0x132000); - default: - return 0; - } -} - -static u32 -read_clk(struct nve0_clock_priv *priv, int clk) -{ - u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); - u32 sclk, sdiv; - - if (clk < 7) { - u32 ssel = nv_rd32(priv, 0x137100); - if (ssel & (1 << clk)) { - sclk = read_pll(priv, 0x137000 + (clk * 0x20)); - sdiv = 1; - } else { - sclk = read_div(priv, clk, 0x137160, 0x1371d0); - sdiv = 0; - } - } else { - u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); - if ((ssrc & 0x00000003) == 0x00000003) { - sclk = read_div(priv, clk, 0x137160, 0x1371d0); - if (ssrc & 0x00000100) { - if (ssrc & 0x40000000) - sclk = read_pll(priv, 0x1370e0); - sdiv = 1; - } else { - sdiv = 0; - } - } else { - sclk = read_div(priv, clk, 0x137160, 0x1371d0); - sdiv = 0; - } - } - - if (sctl & 0x80000000) { - if (sdiv) - sdiv = ((sctl & 0x00003f00) >> 8) + 2; - else - sdiv = ((sctl & 0x0000003f) >> 0) + 2; - return (sclk * 2) / sdiv; - } - - return sclk; -} - -static int -nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) -{ - struct nouveau_device *device = nv_device(clk); - struct nve0_clock_priv *priv = (void *)clk; - - switch (src) { - case nv_clk_src_crystal: - return device->crystal; - case nv_clk_src_href: - return 100000; - case nv_clk_src_mem: - return read_mem(priv); - case nv_clk_src_gpc: - return read_clk(priv, 0x00); - case nv_clk_src_rop: - return read_clk(priv, 0x01); - case nv_clk_src_hubk07: - return read_clk(priv, 0x02); - case nv_clk_src_hubk06: - return read_clk(priv, 0x07); - case nv_clk_src_hubk01: - return read_clk(priv, 0x08); - case nv_clk_src_daemon: - return read_clk(priv, 0x0c); - case nv_clk_src_vdec: - return read_clk(priv, 0x0e); - default: - nv_error(clk, "invalid clock source %d\n", src); - return -EINVAL; - } -} - -static u32 -calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) -{ - u32 div = min((ref * 2) / freq, (u32)65); - if (div < 2) - div = 2; - - *ddiv = div - 2; - return (ref * 2) / div; -} - -static u32 -calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) -{ - u32 sclk; - - /* use one of the fixed frequencies if possible */ - *ddiv = 0x00000000; - switch (freq) { - case 27000: - case 108000: - *dsrc = 0x00000000; - if (freq == 108000) - *dsrc |= 0x00030000; - return freq; - case 100000: - *dsrc = 0x00000002; - return freq; - default: - *dsrc = 0x00000003; - break; - } - - /* otherwise, calculate the closest divider */ - sclk = read_vco(priv, 0x137160 + (clk * 4)); - if (clk < 7) - sclk = calc_div(priv, clk, sclk, freq, ddiv); - return sclk; -} - -static u32 -calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) -{ - struct nouveau_bios *bios = nouveau_bios(priv); - struct nvbios_pll limits; - int N, M, P, ret; - - ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); - if (ret) - return 0; - - limits.refclk = read_div(priv, clk, 0x137120, 0x137140); - if (!limits.refclk) - return 0; - - ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); - if (ret <= 0) - return 0; - - *coef = (P << 16) | (N << 8) | M; - return ret; -} - -static int -calc_clk(struct nve0_clock_priv *priv, - struct nouveau_cstate *cstate, int clk, int dom) -{ - struct nve0_clock_info *info = &priv->eng[clk]; - u32 freq = cstate->domain[dom]; - u32 src0, div0, div1D, div1P = 0; - u32 clk0, clk1 = 0; - - /* invalid clock domain */ - if (!freq) - return 0; - - /* first possible path, using only dividers */ - clk0 = calc_src(priv, clk, freq, &src0, &div0); - clk0 = calc_div(priv, clk, clk0, freq, &div1D); - - /* see if we can get any closer using PLLs */ - if (clk0 != freq && (0x0000ff87 & (1 << clk))) { - if (clk <= 7) - clk1 = calc_pll(priv, clk, freq, &info->coef); - else - clk1 = cstate->domain[nv_clk_src_hubk06]; - clk1 = calc_div(priv, clk, clk1, freq, &div1P); - } - - /* select the method which gets closest to target freq */ - if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { - info->dsrc = src0; - if (div0) { - info->ddiv |= 0x80000000; - info->ddiv |= div0; - } - if (div1D) { - info->mdiv |= 0x80000000; - info->mdiv |= div1D; - } - info->ssel = 0; - info->freq = clk0; - } else { - if (div1P) { - info->mdiv |= 0x80000000; - info->mdiv |= div1P << 8; - } - info->ssel = (1 << clk); - info->dsrc = 0x40000100; - info->freq = clk1; - } - - return 0; -} - -static int -nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) -{ - struct nve0_clock_priv *priv = (void *)clk; - int ret; - - if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || - (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || - (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || - (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || - (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || - (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || - (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) - return ret; - - return 0; -} - -static void -nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) -{ - struct nve0_clock_info *info = &priv->eng[clk]; - if (!info->ssel) { - nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); - nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); - } -} - -static void -nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk) -{ - nv_mask(priv, 0x137100, (1 << clk), 0x00000000); - nv_wait(priv, 0x137100, (1 << clk), 0x00000000); -} - -static void -nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk) -{ - nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); -} - -static void -nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk) -{ - struct nve0_clock_info *info = &priv->eng[clk]; - const u32 addr = 0x137000 + (clk * 0x20); - nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); - nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); - if (info->coef) { - nv_wr32(priv, addr + 0x04, info->coef); - nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); - nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); - nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); - } -} - -static void -nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) -{ - struct nve0_clock_info *info = &priv->eng[clk]; - if (info->ssel) - nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); - else - nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); -} - -static void -nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk) -{ - struct nve0_clock_info *info = &priv->eng[clk]; - if (info->ssel) { - nv_mask(priv, 0x137100, (1 << clk), info->ssel); - nv_wait(priv, 0x137100, (1 << clk), info->ssel); - } -} - -static void -nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk) -{ - struct nve0_clock_info *info = &priv->eng[clk]; - if (info->ssel) { - nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); - nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); - } -} - -static int -nve0_clock_prog(struct nouveau_clock *clk) -{ - struct nve0_clock_priv *priv = (void *)clk; - struct { - u32 mask; - void (*exec)(struct nve0_clock_priv *, int); - } stage[] = { - { 0x007f, nve0_clock_prog_0 }, /* div programming */ - { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */ - { 0xff80, nve0_clock_prog_1_1 }, - { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */ - { 0xff80, nve0_clock_prog_3 }, /* final divider */ - { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */ - { 0xff80, nve0_clock_prog_4_1 }, - }; - int i, j; - - for (i = 0; i < ARRAY_SIZE(stage); i++) { - for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { - if (!(stage[i].mask & (1 << j))) - continue; - if (!priv->eng[j].freq) - continue; - stage[i].exec(priv, j); - } - } - - return 0; -} - -static void -nve0_clock_tidy(struct nouveau_clock *clk) -{ - struct nve0_clock_priv *priv = (void *)clk; - memset(priv->eng, 0x00, sizeof(priv->eng)); -} - -static struct nouveau_clocks -nve0_domain[] = { - { nv_clk_src_crystal, 0xff }, - { nv_clk_src_href , 0xff }, - { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 }, - { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE }, - { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE }, - { nv_clk_src_mem , 0x03, 0, "memory", 500 }, - { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, - { nv_clk_src_hubk01 , 0x05 }, - { nv_clk_src_vdec , 0x06 }, - { nv_clk_src_daemon , 0x07 }, - { nv_clk_src_max } -}; - -static int -nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_clock_priv *priv; - int ret; - - ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0, - true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.read = nve0_clock_read; - priv->base.calc = nve0_clock_calc; - priv->base.prog = nve0_clock_prog; - priv->base.tidy = nve0_clock_tidy; - return 0; -} - -struct nouveau_oclass -nve0_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h deleted file mode 100644 index 445b14c33a98..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NOUVEAU_PLL_H__ -#define __NOUVEAU_PLL_H__ - -int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, - int *N1, int *M1, int *N2, int *M2, int *P); -int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, - int *N, int *fN, int *M, int *P); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c deleted file mode 100644 index b47d543ab2e3..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright 1993-2003 NVIDIA, Corporation - * Copyright 2007-2009 Stuart Bennett - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include -#include - -#include "pll.h" - -static int -getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, - int *pN, int *pM, int *pP) -{ - /* Find M, N and P for a single stage PLL - * - * Note that some bioses (NV3x) have lookup tables of precomputed MNP - * values, but we're too lazy to use those atm - * - * "clk" parameter in kHz - * returns calculated clock - */ - struct nouveau_bios *bios = nouveau_bios(subdev); - int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; - int minM = info->vco1.min_m, maxM = info->vco1.max_m; - int minN = info->vco1.min_n, maxN = info->vco1.max_n; - int minU = info->vco1.min_inputfreq; - int maxU = info->vco1.max_inputfreq; - int minP = info->min_p; - int maxP = info->max_p_usable; - int crystal = info->refclk; - int M, N, thisP, P; - int clkP, calcclk; - int delta, bestdelta = INT_MAX; - int bestclk = 0; - - /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */ - /* possibly correlated with introduction of 27MHz crystal */ - if (bios->version.major < 0x60) { - int cv = bios->version.chip; - if (cv < 0x17 || cv == 0x1a || cv == 0x20) { - if (clk > 250000) - maxM = 6; - if (clk > 340000) - maxM = 2; - } else if (cv < 0x40) { - if (clk > 150000) - maxM = 6; - if (clk > 200000) - maxM = 4; - if (clk > 340000) - maxM = 2; - } - } - - P = 1 << maxP; - if ((clk * P) < minvco) { - minvco = clk * maxP; - maxvco = minvco * 2; - } - - if (clk + clk/200 > maxvco) /* +0.5% */ - maxvco = clk + clk/200; - - /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */ - for (thisP = minP; thisP <= maxP; thisP++) { - P = 1 << thisP; - clkP = clk * P; - - if (clkP < minvco) - continue; - if (clkP > maxvco) - return bestclk; - - for (M = minM; M <= maxM; M++) { - if (crystal/M < minU) - return bestclk; - if (crystal/M > maxU) - continue; - - /* add crystal/2 to round better */ - N = (clkP * M + crystal/2) / crystal; - - if (N < minN) - continue; - if (N > maxN) - break; - - /* more rounding additions */ - calcclk = ((N * crystal + P/2) / P + M/2) / M; - delta = abs(calcclk - clk); - /* we do an exhaustive search rather than terminating - * on an optimality condition... - */ - if (delta < bestdelta) { - bestdelta = delta; - bestclk = calcclk; - *pN = N; - *pM = M; - *pP = thisP; - if (delta == 0) /* except this one */ - return bestclk; - } - } - } - - return bestclk; -} - -static int -getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, - int *pN1, int *pM1, int *pN2, int *pM2, int *pP) -{ - /* Find M, N and P for a two stage PLL - * - * Note that some bioses (NV30+) have lookup tables of precomputed MNP - * values, but we're too lazy to use those atm - * - * "clk" parameter in kHz - * returns calculated clock - */ - int chip_version = nouveau_bios(subdev)->version.chip; - int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq; - int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq; - int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq; - int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq; - int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m; - int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n; - int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m; - int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n; - int maxlog2P = info->max_p_usable; - int crystal = info->refclk; - bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2); - int M1, N1, M2, N2, log2P; - int clkP, calcclk1, calcclk2, calcclkout; - int delta, bestdelta = INT_MAX; - int bestclk = 0; - - int vco2 = (maxvco2 - maxvco2/200) / 2; - for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++) - ; - clkP = clk << log2P; - - if (maxvco2 < clk + clk/200) /* +0.5% */ - maxvco2 = clk + clk/200; - - for (M1 = minM1; M1 <= maxM1; M1++) { - if (crystal/M1 < minU1) - return bestclk; - if (crystal/M1 > maxU1) - continue; - - for (N1 = minN1; N1 <= maxN1; N1++) { - calcclk1 = crystal * N1 / M1; - if (calcclk1 < minvco1) - continue; - if (calcclk1 > maxvco1) - break; - - for (M2 = minM2; M2 <= maxM2; M2++) { - if (calcclk1/M2 < minU2) - break; - if (calcclk1/M2 > maxU2) - continue; - - /* add calcclk1/2 to round better */ - N2 = (clkP * M2 + calcclk1/2) / calcclk1; - if (N2 < minN2) - continue; - if (N2 > maxN2) - break; - - if (!fixedgain2) { - if (chip_version < 0x60) - if (N2/M2 < 4 || N2/M2 > 10) - continue; - - calcclk2 = calcclk1 * N2 / M2; - if (calcclk2 < minvco2) - break; - if (calcclk2 > maxvco2) - continue; - } else - calcclk2 = calcclk1; - - calcclkout = calcclk2 >> log2P; - delta = abs(calcclkout - clk); - /* we do an exhaustive search rather than terminating - * on an optimality condition... - */ - if (delta < bestdelta) { - bestdelta = delta; - bestclk = calcclkout; - *pN1 = N1; - *pM1 = M1; - *pN2 = N2; - *pM2 = M2; - *pP = log2P; - if (delta == 0) /* except this one */ - return bestclk; - } - } - } - } - - return bestclk; -} - -int -nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq, - int *N1, int *M1, int *N2, int *M2, int *P) -{ - int ret; - - if (!info->vco2.max_freq || !N2) { - ret = getMNP_single(subdev, info, freq, N1, M1, P); - if (N2) { - *N2 = 1; - *M2 = 1; - } - } else { - ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); - } - - if (!ret) - nv_error(subdev, "unable to compute acceptable pll values\n"); - return ret; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c deleted file mode 100644 index 8eca457c2814..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include "pll.h" - -int -nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, - u32 freq, int *pN, int *pfN, int *pM, int *P) -{ - u32 best_err = ~0, err; - int M, lM, hM, N, fN; - - *P = info->vco1.max_freq / freq; - if (*P > info->max_p) - *P = info->max_p; - if (*P < info->min_p) - *P = info->min_p; - - lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; - lM = max(lM, (int)info->vco1.min_m); - hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; - hM = min(hM, (int)info->vco1.max_m); - lM = min(lM, hM); - - for (M = lM; M <= hM; M++) { - u32 tmp = freq * *P * M; - N = tmp / info->refclk; - fN = tmp % info->refclk; - - if (!pfN) { - if (fN >= info->refclk / 2) - N++; - } else { - if (fN < info->refclk / 2) - N--; - fN = tmp - (N * info->refclk); - } - - if (N < info->vco1.min_n) - continue; - if (N > info->vco1.max_n) - break; - - err = abs(freq - (info->refclk * N / M / *P)); - if (err < best_err) { - best_err = err; - *pN = N; - *pM = M; - } - - if (pfN) { - *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; - *pfN = (*pfN - 4096) & 0xffff; - return freq; - } - } - - if (unlikely(best_err == ~0)) { - nv_error(subdev, "unable to find matching pll values\n"); - return -EINVAL; - } - - return info->refclk * *pN / *pM / *P; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h deleted file mode 100644 index fb33f06ebd59..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __NVKM_CLK_SEQ_H__ -#define __NVKM_CLK_SEQ_H__ - -#include -#include - -#define clk_init(s,p) hwsq_init(&(s)->base, (p)) -#define clk_exec(s,e) hwsq_exec(&(s)->base, (e)) -#define clk_have(s,r) ((s)->r_##r.addr != 0x000000) -#define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) -#define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) -#define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) -#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) -#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) -#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n)) - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h index cbcd51852472..7a768afba813 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include struct nouveau_devinit_impl { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 7648beb11199..50cbc3804eaf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -26,8 +26,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 64a983c96625..8d2970c27715 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c index 3b38a538845d..50e8dee513cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c @@ -30,8 +30,8 @@ #include #include -#include -#include +#include +#include #include @@ -168,7 +168,7 @@ nva3_link_train(struct nouveau_fb *pfb) { struct nouveau_bios *bios = nouveau_bios(pfb); struct nva3_ram *ram = (void *)pfb->ram; - struct nouveau_clock *clk = nouveau_clock(pfb); + struct nouveau_clk *clk = nouveau_clk(pfb); struct nva3_ltrain *train = &ram->ltrain; struct nouveau_device *device = nv_device(pfb); struct nva3_ramfuc *fuc = &ram->fuc; @@ -197,7 +197,7 @@ nva3_link_train(struct nouveau_fb *pfb) clk_current = clk->read(clk, nv_clk_src_mem); - ret = nva3_clock_pre(clk, f); + ret = nva3_clk_pre(clk, f); if (ret) goto out; @@ -252,7 +252,7 @@ nva3_link_train(struct nouveau_fb *pfb) nv_mask(pfb, 0x616308, 0x10, 0x10); nv_mask(pfb, 0x616b08, 0x10, 0x10); - nva3_clock_post(clk, f); + nva3_clk_post(clk, f); ram_train_result(pfb, result, 64); for (i = 0; i < 64; i++) @@ -274,7 +274,7 @@ out: train->state = NVA3_TRAIN_UNSUPPORTED; - nva3_clock_post(clk, f); + nva3_clk_post(clk, f); return ret; } @@ -465,7 +465,7 @@ nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) } static void -nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk) +nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk) { ram_wr32(fuc, 0x004004, mclk->pll); ram_mask(fuc, 0x004000, 0x00000001, 0x00000001); @@ -504,7 +504,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) struct nva3_ram *ram = (void *)pfb->ram; struct nva3_ramfuc *fuc = &ram->fuc; struct nva3_ltrain *train = &ram->ltrain; - struct nva3_clock_info mclk; + struct nva3_clk_info mclk; struct nouveau_ram_data *next; u8 ver, hdr, cnt, len, strap; u32 data; @@ -555,7 +555,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) } } - ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); + ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk); if (ret < 0) { nv_error(pfb, "failed mclk calculation\n"); return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c index 735cb9580abe..d08eacd580d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c @@ -28,8 +28,8 @@ #include #include -#include -#include +#include +#include #include @@ -129,7 +129,7 @@ nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic) static int nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) { - struct nouveau_clock *clk = nouveau_clock(pfb); + struct nouveau_clk *clk = nouveau_clk(pfb); struct nouveau_bios *bios = nouveau_bios(pfb); struct nvc0_ram *ram = (void *)pfb->ram; struct nvc0_ramfuc *fuc = &ram->fuc; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c index 6bae474abb44..60050aab84b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c @@ -32,8 +32,8 @@ #include #include -#include -#include +#include +#include #include @@ -1033,7 +1033,7 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) static int nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) { - struct nouveau_clock *clk = nouveau_clock(pfb); + struct nouveau_clk *clk = nouveau_clk(pfb); struct nve0_ram *ram = (void *)pfb->ram; struct nouveau_ram_data *xits = &ram->base.xition; struct nouveau_ram_data *copy; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c index f6b7df1b1686..a4e3a9b57306 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c @@ -21,7 +21,7 @@ */ #include "priv.h" -#include +#include #include #include @@ -50,15 +50,15 @@ struct gk20a_pwr_dvfs_dev_status { static int gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state) { - struct nouveau_clock *clk = nouveau_clock(priv); + struct nouveau_clk *clk = nouveau_clk(priv); - return nouveau_clock_astate(clk, *state, 0, false); + return nouveau_clk_astate(clk, *state, 0, false); } static int gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state) { - struct nouveau_clock *clk = nouveau_clock(priv); + struct nouveau_clk *clk = nouveau_clk(priv); *state = clk->pstate; return 0; @@ -69,7 +69,7 @@ gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv, int *state, int load) { struct gk20a_pwr_dvfs_data *data = priv->data; - struct nouveau_clock *clk = nouveau_clock(priv); + struct nouveau_clk *clk = nouveau_clk(priv); int cur_level, level; /* For GK20A, the performance level is directly mapped to pstate */ @@ -117,7 +117,7 @@ gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm) struct gk20a_pwr_priv, alarm); struct gk20a_pwr_dvfs_data *data = priv->data; struct gk20a_pwr_dvfs_dev_status status; - struct nouveau_clock *clk = nouveau_clock(priv); + struct nouveau_clk *clk = nouveau_clk(priv); struct nouveau_volt *volt = nouveau_volt(priv); u32 utilization = 0; int state, ret; -- cgit v1.2.3-59-g8ed1b From 5ce3bf3c72436c49fbd9a5b71d7d278665f4bf55 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 09:57:36 +1000 Subject: drm/nouveau/mmu: rename from vmmgr (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 4 +- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h | 135 ++++++ drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h | 135 ------ drivers/gpu/drm/nouveau/nouveau_bo.c | 8 +- drivers/gpu/drm/nouveau/nouveau_chan.c | 14 +- drivers/gpu/drm/nouveau/nouveau_display.h | 2 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 10 +- drivers/gpu/drm/nouveau/nvkm/core/engctx.c | 2 +- drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 36 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild | 6 + drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 483 +++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c | 151 +++++++ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h | 19 + drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 159 +++++++ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 249 +++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 240 ++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c | 241 ++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild | 6 - drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c | 483 --------------------- drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c | 151 ------- drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h | 19 - drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c | 159 ------- drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c | 249 ----------- drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c | 240 ---------- drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c | 241 ---------- 50 files changed, 1802 insertions(+), 1802 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index e73a16dd97fa..93acd5153bee 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -29,7 +29,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); /*XXX*/ #include #include -#include +#include #include #include #include @@ -40,7 +40,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); #define nvkm_device(a) nv_device(nvkm_object((a))) #define nvkm_bios(a) nouveau_bios(nvkm_device(a)) #define nvkm_fb(a) nouveau_fb(nvkm_device(a)) -#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a)) +#define nvkm_mmu(a) nouveau_mmu(nvkm_device(a)) #define nvkm_bar(a) nouveau_bar(nvkm_device(a)) #define nvkm_gpio(a) nouveau_gpio(nvkm_device(a)) #define nvkm_clk(a) nouveau_clk(nvkm_device(a)) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index a2828ac6a65e..82625c5d68d7 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -33,7 +33,7 @@ enum nv_subdev_type { NVDEV_SUBDEV_FB, NVDEV_SUBDEV_LTC, NVDEV_SUBDEV_INSTMEM, - NVDEV_SUBDEV_VM, + NVDEV_SUBDEV_MMU, NVDEV_SUBDEV_BAR, NVDEV_SUBDEV_PMU, NVDEV_SUBDEV_VOLT, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h index dbc6a3e6dd44..9d696e4747e7 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h @@ -4,7 +4,7 @@ #include #include -#include +#include #define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng)) #define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var)) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 889603fbb0cf..0277585c9067 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -5,7 +5,7 @@ #include #include -#include +#include /* memory type/access flags, do not match hardware values */ #define NV_MEM_ACCESS_RO 1 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h new file mode 100644 index 000000000000..2c3b29967ea4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -0,0 +1,135 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifndef __NOUVEAU_MMU_H__ +#define __NOUVEAU_MMU_H__ + +#include +#include +#include +#include + +struct nouveau_vm_pgt { + struct nouveau_gpuobj *obj[2]; + u32 refcount[2]; +}; + +struct nouveau_vm_pgd { + struct list_head head; + struct nouveau_gpuobj *obj; +}; + +struct nouveau_gpuobj; +struct nouveau_mem; + +struct nouveau_vma { + struct list_head head; + int refcount; + struct nouveau_vm *vm; + struct nouveau_mm_node *node; + u64 offset; + u32 access; +}; + +struct nouveau_vm { + struct nouveau_mmu *mmu; + struct nouveau_mm mm; + struct kref refcount; + + struct list_head pgd_list; + atomic_t engref[NVDEV_SUBDEV_NR]; + + struct nouveau_vm_pgt *pgt; + u32 fpde; + u32 lpde; +}; + +struct nouveau_mmu { + struct nouveau_subdev base; + + u64 limit; + u8 dma_bits; + u32 pgt_bits; + u8 spg_shift; + u8 lpg_shift; + + int (*create)(struct nouveau_mmu *, u64 offset, u64 length, + u64 mm_offset, struct nouveau_vm **); + + void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, + struct nouveau_gpuobj *pgt[2]); + void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, + struct nouveau_mem *, u32 pte, u32 cnt, + u64 phys, u64 delta); + void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, + struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); + void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); + void (*flush)(struct nouveau_vm *); +}; + +static inline struct nouveau_mmu * +nouveau_mmu(void *obj) +{ + return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU); +} + +#define nouveau_mmu_create(p,e,o,i,f,d) \ + nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) +#define nouveau_mmu_destroy(p) \ + nouveau_subdev_destroy(&(p)->base) +#define nouveau_mmu_init(p) \ + nouveau_subdev_init(&(p)->base) +#define nouveau_mmu_fini(p,s) \ + nouveau_subdev_fini(&(p)->base, (s)) + +#define _nouveau_mmu_dtor _nouveau_subdev_dtor +#define _nouveau_mmu_init _nouveau_subdev_init +#define _nouveau_mmu_fini _nouveau_subdev_fini + +extern struct nouveau_oclass nv04_mmu_oclass; +extern struct nouveau_oclass nv41_mmu_oclass; +extern struct nouveau_oclass nv44_mmu_oclass; +extern struct nouveau_oclass nv50_mmu_oclass; +extern struct nouveau_oclass nvc0_mmu_oclass; + +int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64, + struct nouveau_vm **); +void nv04_mmu_dtor(struct nouveau_object *); + +/* nouveau_vm.c */ +int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length, + u64 mm_offset, u32 block, struct nouveau_vm **); +int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, + u64 mm_offset, struct nouveau_vm **); +int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, + struct nouveau_gpuobj *pgd); +int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, + u32 access, struct nouveau_vma *); +void nouveau_vm_put(struct nouveau_vma *); +void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); +void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); +void nouveau_vm_unmap(struct nouveau_vma *); +void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); + +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h deleted file mode 100644 index d56585f1cd8c..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifndef __NOUVEAU_VM_H__ -#define __NOUVEAU_VM_H__ - -#include -#include -#include -#include - -struct nouveau_vm_pgt { - struct nouveau_gpuobj *obj[2]; - u32 refcount[2]; -}; - -struct nouveau_vm_pgd { - struct list_head head; - struct nouveau_gpuobj *obj; -}; - -struct nouveau_gpuobj; -struct nouveau_mem; - -struct nouveau_vma { - struct list_head head; - int refcount; - struct nouveau_vm *vm; - struct nouveau_mm_node *node; - u64 offset; - u32 access; -}; - -struct nouveau_vm { - struct nouveau_vmmgr *vmm; - struct nouveau_mm mm; - struct kref refcount; - - struct list_head pgd_list; - atomic_t engref[NVDEV_SUBDEV_NR]; - - struct nouveau_vm_pgt *pgt; - u32 fpde; - u32 lpde; -}; - -struct nouveau_vmmgr { - struct nouveau_subdev base; - - u64 limit; - u8 dma_bits; - u32 pgt_bits; - u8 spg_shift; - u8 lpg_shift; - - int (*create)(struct nouveau_vmmgr *, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **); - - void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, - struct nouveau_gpuobj *pgt[2]); - void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, - struct nouveau_mem *, u32 pte, u32 cnt, - u64 phys, u64 delta); - void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, - struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); - void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); - void (*flush)(struct nouveau_vm *); -}; - -static inline struct nouveau_vmmgr * -nouveau_vmmgr(void *obj) -{ - return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VM); -} - -#define nouveau_vmmgr_create(p,e,o,i,f,d) \ - nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) -#define nouveau_vmmgr_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_vmmgr_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_vmmgr_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor -#define _nouveau_vmmgr_init _nouveau_subdev_init -#define _nouveau_vmmgr_fini _nouveau_subdev_fini - -extern struct nouveau_oclass nv04_vmmgr_oclass; -extern struct nouveau_oclass nv41_vmmgr_oclass; -extern struct nouveau_oclass nv44_vmmgr_oclass; -extern struct nouveau_oclass nv50_vmmgr_oclass; -extern struct nouveau_oclass nvc0_vmmgr_oclass; - -int nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64, - struct nouveau_vm **); -void nv04_vmmgr_dtor(struct nouveau_object *); - -/* nouveau_vm.c */ -int nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length, - u64 mm_offset, u32 block, struct nouveau_vm **); -int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **); -int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, - struct nouveau_gpuobj *pgd); -int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, - u32 access, struct nouveau_vma *); -void nouveau_vm_put(struct nouveau_vma *); -void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); -void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); -void nouveau_vm_unmap(struct nouveau_vma *); -void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); - -#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index d96fe3524dbd..d2f0929c2d73 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -193,7 +193,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, int max_size; if (drm->client.vm) - lpg_shift = drm->client.vm->vmm->lpg_shift; + lpg_shift = drm->client.vm->mmu->lpg_shift; max_size = INT_MAX & ~((1 << lpg_shift) - 1); if (size <= 0 || size > max_size) { @@ -220,7 +220,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, nvbo->page_shift = 12; if (drm->client.vm) { if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) - nvbo->page_shift = drm->client.vm->vmm->lpg_shift; + nvbo->page_shift = drm->client.vm->mmu->lpg_shift; } nouveau_bo_fixup_align(nvbo, flags, &align, &size); @@ -1240,7 +1240,7 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) list_for_each_entry(vma, &nvbo->vma_list, head) { if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && (new_mem->mem_type == TTM_PL_VRAM || - nvbo->page_shift != vma->vm->vmm->lpg_shift)) { + nvbo->page_shift != vma->vm->mmu->lpg_shift)) { nouveau_vm_map(vma, new_mem->mm_node); } else { nouveau_vm_unmap(vma); @@ -1639,7 +1639,7 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && (nvbo->bo.mem.mem_type == TTM_PL_VRAM || - nvbo->page_shift != vma->vm->vmm->lpg_shift)) + nvbo->page_shift != vma->vm->mmu->lpg_shift)) nouveau_vm_map(vma, nvbo->bo.mem.mm_node); list_add_tail(&vma->head, &nvbo->vma_list); diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index aff9099aae6c..80302530ead7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, u32 handle, u32 size, struct nouveau_channel **pchan) { struct nouveau_cli *cli = (void *)nvif_client(&device->base); - struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); + struct nouveau_mmu *mmu = nvkm_mmu(device); struct nv_dma_v0 args = {}; struct nouveau_channel *chan; u32 target; @@ -136,7 +136,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_VM; args.start = 0; - args.limit = cli->vm->vmm->limit - 1; + args.limit = cli->vm->mmu->limit - 1; } else if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { if (device->info.family == NV_DEVICE_INFO_V0_TNT) { @@ -165,7 +165,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_RDWR; args.start = 0; - args.limit = vmm->limit - 1; + args.limit = mmu->limit - 1; } } @@ -281,7 +281,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) { struct nvif_device *device = chan->device; struct nouveau_cli *cli = (void *)nvif_client(&device->base); - struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); + struct nouveau_mmu *mmu = nvkm_mmu(device); struct nouveau_software_chan *swch; struct nv_dma_v0 args = {}; int ret, i; @@ -294,7 +294,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_VM; args.start = 0; - args.limit = cli->vm->vmm->limit - 1; + args.limit = cli->vm->mmu->limit - 1; } else { args.target = NV_DMA_V0_TARGET_VRAM; args.access = NV_DMA_V0_ACCESS_RDWR; @@ -312,7 +312,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_VM; args.start = 0; - args.limit = cli->vm->vmm->limit - 1; + args.limit = cli->vm->mmu->limit - 1; } else if (chan->drm->agp.stat == ENABLED) { args.target = NV_DMA_V0_TARGET_AGP; @@ -324,7 +324,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_RDWR; args.start = 0; - args.limit = vmm->limit - 1; + args.limit = mmu->limit - 1; } ret = nvif_object_init(chan->object, NULL, gart, diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index be3d5947c6be..a94dcdaccf59 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -1,7 +1,7 @@ #ifndef __NOUVEAU_DISPLAY_H__ #define __NOUVEAU_DISPLAY_H__ -#include +#include #include "nouveau_drm.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 2e0d1d998ca6..aa8321706103 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -203,13 +203,13 @@ const struct ttm_mem_type_manager_func nouveau_gart_manager = { }; /*XXX*/ -#include +#include static int nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nouveau_vmmgr *vmm = nvkm_vmmgr(&drm->device); - struct nv04_vmmgr_priv *priv = (void *)vmm; + struct nouveau_mmu *mmu = nvkm_mmu(&drm->device); + struct nv04_mmu_priv *priv = (void *)mmu; struct nouveau_vm *vm = NULL; nouveau_vm_ref(priv->vm, &vm, NULL); man->priv = vm; @@ -354,7 +354,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) u32 bits; int ret; - bits = nvkm_vmmgr(&drm->device)->dma_bits; + bits = nvkm_mmu(&drm->device)->dma_bits; if (nv_device_is_pci(nvkm_device(&drm->device))) { if (drm->agp.stat == ENABLED || !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) @@ -401,7 +401,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) /* GART init */ if (drm->agp.stat != ENABLED) { - drm->gem.gart_available = nvkm_vmmgr(&drm->device)->limit; + drm->gem.gart_available = nvkm_mmu(&drm->device)->limit; } else { drm->gem.gart_available = drm->agp.size; } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c index 16f09b1280dc..892baa461575 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c @@ -28,7 +28,7 @@ #include #include -#include +#include static inline int nouveau_engctx_exists(struct nouveau_object *parent, diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index 0fa64576b8d6..68a4232d35cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -27,7 +27,7 @@ #include #include -#include +#include void nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c index 13c05e09ff87..6ae64969e2e5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index e141dff31553..eb9f387d7356 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -218,7 +218,7 @@ static const u64 disable_map[] = { [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_SUBDEV_MMU] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 763572fcb7d4..130d225377ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -75,7 +75,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; @@ -119,7 +119,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; #if 0 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index dff51984ea94..7f98385acec7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include @@ -55,7 +55,7 @@ nv04_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; @@ -73,7 +73,7 @@ nv04_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index af63f5b95f01..6a7ece0fc789 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include @@ -57,7 +57,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -74,7 +74,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -93,7 +93,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -112,7 +112,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -131,7 +131,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -150,7 +150,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -169,7 +169,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -188,7 +188,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index eddeb126c7ec..e3b17fde89e6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include @@ -58,7 +58,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -77,7 +77,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -96,7 +96,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -115,7 +115,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 6fe2d130a2ce..8f67f4d402d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include @@ -58,7 +58,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -77,7 +77,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -96,7 +96,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -116,7 +116,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; @@ -136,7 +136,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index d85edd87cec8..49c68d7c093c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include #include @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include @@ -63,7 +63,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -86,7 +86,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -109,7 +109,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -132,7 +132,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -155,7 +155,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -178,7 +178,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -201,7 +201,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -224,7 +224,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -247,7 +247,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -270,7 +270,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -293,7 +293,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -316,7 +316,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -339,7 +339,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -362,7 +362,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -385,7 +385,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -408,7 +408,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 867b79a0679a..f9afee4f844d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include @@ -73,7 +73,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -99,7 +99,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -128,7 +128,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -157,7 +157,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -186,7 +186,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -215,7 +215,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -244,7 +244,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -273,7 +273,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -302,7 +302,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -331,7 +331,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -360,7 +360,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -391,7 +391,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -421,7 +421,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -451,7 +451,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index d54d6ac4cea5..0db51092732a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -108,7 +108,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -141,7 +141,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -173,7 +173,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -206,7 +206,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -238,7 +238,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -270,7 +270,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -303,7 +303,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -335,7 +335,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 39b3fe32b9fb..a565bc8b6636 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -109,7 +109,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -143,7 +143,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -171,7 +171,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; @@ -199,7 +199,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -233,7 +233,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -267,7 +267,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -300,7 +300,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c index 20c9dbfe3b2e..8089310f1157 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include "priv.h" @@ -62,8 +62,8 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } if (priv->clone) { - struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj); - struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; + struct nv04_mmu_priv *mmu = nv04_mmu(dmaobj); + struct nouveau_gpuobj *pgt = mmu->vm->pgt[0].obj[0]; if (!dmaobj->start) return nouveau_gpuobj_dup(parent, pgt, pgpuobj); offset = nv_ro32(pgt, 8 + (offset >> 10)); @@ -88,7 +88,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_object **pobject) { struct nouveau_dmaeng *dmaeng = (void *)engine; - struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine); + struct nv04_mmu_priv *mmu = nv04_mmu(engine); struct nv04_dmaobj_priv *priv; int ret; @@ -98,7 +98,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; if (priv->base.target == NV_MEM_TARGET_VM) { - if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) + if (nv_object(mmu)->oclass == &nv04_mmu_oclass) priv->clone = true; priv->base.target = NV_MEM_TARGET_PCI; priv->base.access = NV_MEM_ACCESS_RW; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c index e8ef8cb058cd..e5d1e969945e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c index c9c168035b4d..bf2b9e2df3d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c index 38e0aa26f1cd..896e17b56f45 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c @@ -29,7 +29,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h index 7ed9e89c3435..86b7735242e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h @@ -34,7 +34,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c index cae33f86b11a..b62c301b31a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c index e9cc8b116a24..97c8343e1a08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild index 55090f73bab4..dbcea4930a1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild @@ -15,5 +15,5 @@ include $(src)/nvkm/subdev/mxm/Kbuild include $(src)/nvkm/subdev/pmu/Kbuild include $(src)/nvkm/subdev/therm/Kbuild include $(src)/nvkm/subdev/timer/Kbuild -include $(src)/nvkm/subdev/vm/Kbuild +include $(src)/nvkm/subdev/mmu/Kbuild include $(src)/nvkm/subdev/volt/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 188c638411b2..1b37afe4a4ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index f748ba49dfc8..6d0dd6a01e64 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c index 8320ee0509c3..c7ac57ba8e35 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild new file mode 100644 index 000000000000..729e27f2cbd4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild @@ -0,0 +1,6 @@ +nvkm-y += nvkm/subdev/mmu/base.o +nvkm-y += nvkm/subdev/mmu/nv04.o +nvkm-y += nvkm/subdev/mmu/nv41.o +nvkm-y += nvkm/subdev/mmu/nv44.o +nvkm-y += nvkm/subdev/mmu/nv50.o +nvkm-y += nvkm/subdev/mmu/nvc0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c new file mode 100644 index 000000000000..e3cb186c440b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -0,0 +1,483 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include +#include + +void +nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) +{ + struct nouveau_vm *vm = vma->vm; + struct nouveau_mmu *mmu = vm->mmu; + struct nouveau_mm_node *r; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + u32 end, len; + + delta = 0; + list_for_each_entry(r, &node->regions, rl_entry) { + u64 phys = (u64)r->offset << 12; + u32 num = r->length >> bits; + + while (num) { + struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + + end = (pte + num); + if (unlikely(end >= max)) + end = max; + len = end - pte; + + mmu->map(vma, pgt, node, pte, len, phys, delta); + + num -= len; + pte += len; + if (unlikely(end >= max)) { + phys += len << (bits + 12); + pde++; + pte = 0; + } + + delta += (u64)len << vma->node->type; + } + } + + mmu->flush(vm); +} + +static void +nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, + struct nouveau_mem *mem) +{ + struct nouveau_vm *vm = vma->vm; + struct nouveau_mmu *mmu = vm->mmu; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 num = length >> vma->node->type; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + unsigned m, sglen; + u32 end, len; + int i; + struct scatterlist *sg; + + for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { + struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + sglen = sg_dma_len(sg) >> PAGE_SHIFT; + + end = pte + sglen; + if (unlikely(end >= max)) + end = max; + len = end - pte; + + for (m = 0; m < len; m++) { + dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); + + mmu->map_sg(vma, pgt, mem, pte, 1, &addr); + num--; + pte++; + + if (num == 0) + goto finish; + } + if (unlikely(end >= max)) { + pde++; + pte = 0; + } + if (m < sglen) { + for (; m < sglen; m++) { + dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); + + mmu->map_sg(vma, pgt, mem, pte, 1, &addr); + num--; + pte++; + if (num == 0) + goto finish; + } + } + + } +finish: + mmu->flush(vm); +} + +static void +nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, + struct nouveau_mem *mem) +{ + struct nouveau_vm *vm = vma->vm; + struct nouveau_mmu *mmu = vm->mmu; + dma_addr_t *list = mem->pages; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 num = length >> vma->node->type; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + u32 end, len; + + while (num) { + struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + + end = (pte + num); + if (unlikely(end >= max)) + end = max; + len = end - pte; + + mmu->map_sg(vma, pgt, mem, pte, len, list); + + num -= len; + pte += len; + list += len; + if (unlikely(end >= max)) { + pde++; + pte = 0; + } + } + + mmu->flush(vm); +} + +void +nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) +{ + if (node->sg) + nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); + else + if (node->pages) + nouveau_vm_map_sg(vma, 0, node->size << 12, node); + else + nouveau_vm_map_at(vma, 0, node); +} + +void +nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) +{ + struct nouveau_vm *vm = vma->vm; + struct nouveau_mmu *mmu = vm->mmu; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 num = length >> vma->node->type; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + u32 end, len; + + while (num) { + struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + + end = (pte + num); + if (unlikely(end >= max)) + end = max; + len = end - pte; + + mmu->unmap(pgt, pte, len); + + num -= len; + pte += len; + if (unlikely(end >= max)) { + pde++; + pte = 0; + } + } + + mmu->flush(vm); +} + +void +nouveau_vm_unmap(struct nouveau_vma *vma) +{ + nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); +} + +static void +nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) +{ + struct nouveau_mmu *mmu = vm->mmu; + struct nouveau_vm_pgd *vpgd; + struct nouveau_vm_pgt *vpgt; + struct nouveau_gpuobj *pgt; + u32 pde; + + for (pde = fpde; pde <= lpde; pde++) { + vpgt = &vm->pgt[pde - vm->fpde]; + if (--vpgt->refcount[big]) + continue; + + pgt = vpgt->obj[big]; + vpgt->obj[big] = NULL; + + list_for_each_entry(vpgd, &vm->pgd_list, head) { + mmu->map_pgt(vpgd->obj, pde, vpgt->obj); + } + + mutex_unlock(&nv_subdev(mmu)->mutex); + nouveau_gpuobj_ref(NULL, &pgt); + mutex_lock(&nv_subdev(mmu)->mutex); + } +} + +static int +nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) +{ + struct nouveau_mmu *mmu = vm->mmu; + struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; + struct nouveau_vm_pgd *vpgd; + struct nouveau_gpuobj *pgt; + int big = (type != mmu->spg_shift); + u32 pgt_size; + int ret; + + pgt_size = (1 << (mmu->pgt_bits + 12)) >> type; + pgt_size *= 8; + + mutex_unlock(&nv_subdev(mmu)->mutex); + ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &pgt); + mutex_lock(&nv_subdev(mmu)->mutex); + if (unlikely(ret)) + return ret; + + /* someone beat us to filling the PDE while we didn't have the lock */ + if (unlikely(vpgt->refcount[big]++)) { + mutex_unlock(&nv_subdev(mmu)->mutex); + nouveau_gpuobj_ref(NULL, &pgt); + mutex_lock(&nv_subdev(mmu)->mutex); + return 0; + } + + vpgt->obj[big] = pgt; + list_for_each_entry(vpgd, &vm->pgd_list, head) { + mmu->map_pgt(vpgd->obj, pde, vpgt->obj); + } + + return 0; +} + +int +nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, + u32 access, struct nouveau_vma *vma) +{ + struct nouveau_mmu *mmu = vm->mmu; + u32 align = (1 << page_shift) >> 12; + u32 msize = size >> 12; + u32 fpde, lpde, pde; + int ret; + + mutex_lock(&nv_subdev(mmu)->mutex); + ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, + &vma->node); + if (unlikely(ret != 0)) { + mutex_unlock(&nv_subdev(mmu)->mutex); + return ret; + } + + fpde = (vma->node->offset >> mmu->pgt_bits); + lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; + + for (pde = fpde; pde <= lpde; pde++) { + struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; + int big = (vma->node->type != mmu->spg_shift); + + if (likely(vpgt->refcount[big])) { + vpgt->refcount[big]++; + continue; + } + + ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); + if (ret) { + if (pde != fpde) + nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); + nouveau_mm_free(&vm->mm, &vma->node); + mutex_unlock(&nv_subdev(mmu)->mutex); + return ret; + } + } + mutex_unlock(&nv_subdev(mmu)->mutex); + + vma->vm = NULL; + nouveau_vm_ref(vm, &vma->vm, NULL); + vma->offset = (u64)vma->node->offset << 12; + vma->access = access; + return 0; +} + +void +nouveau_vm_put(struct nouveau_vma *vma) +{ + struct nouveau_vm *vm = vma->vm; + struct nouveau_mmu *mmu = vm->mmu; + u32 fpde, lpde; + + if (unlikely(vma->node == NULL)) + return; + fpde = (vma->node->offset >> mmu->pgt_bits); + lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; + + mutex_lock(&nv_subdev(mmu)->mutex); + nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde); + nouveau_mm_free(&vm->mm, &vma->node); + mutex_unlock(&nv_subdev(mmu)->mutex); + + nouveau_vm_ref(NULL, &vma->vm, NULL); +} + +int +nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, + u64 mm_offset, u32 block, struct nouveau_vm **pvm) +{ + struct nouveau_vm *vm; + u64 mm_length = (offset + length) - mm_offset; + int ret; + + vm = kzalloc(sizeof(*vm), GFP_KERNEL); + if (!vm) + return -ENOMEM; + + INIT_LIST_HEAD(&vm->pgd_list); + vm->mmu = mmu; + kref_init(&vm->refcount); + vm->fpde = offset >> (mmu->pgt_bits + 12); + vm->lpde = (offset + length - 1) >> (mmu->pgt_bits + 12); + + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); + if (!vm->pgt) { + kfree(vm); + return -ENOMEM; + } + + ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, + block >> 12); + if (ret) { + vfree(vm->pgt); + kfree(vm); + return ret; + } + + *pvm = vm; + + return 0; +} + +int +nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, + u64 mm_offset, struct nouveau_vm **pvm) +{ + struct nouveau_mmu *mmu = nouveau_mmu(device); + return mmu->create(mmu, offset, length, mm_offset, pvm); +} + +static int +nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) +{ + struct nouveau_mmu *mmu = vm->mmu; + struct nouveau_vm_pgd *vpgd; + int i; + + if (!pgd) + return 0; + + vpgd = kzalloc(sizeof(*vpgd), GFP_KERNEL); + if (!vpgd) + return -ENOMEM; + + nouveau_gpuobj_ref(pgd, &vpgd->obj); + + mutex_lock(&nv_subdev(mmu)->mutex); + for (i = vm->fpde; i <= vm->lpde; i++) + mmu->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); + list_add(&vpgd->head, &vm->pgd_list); + mutex_unlock(&nv_subdev(mmu)->mutex); + return 0; +} + +static void +nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) +{ + struct nouveau_mmu *mmu = vm->mmu; + struct nouveau_vm_pgd *vpgd, *tmp; + struct nouveau_gpuobj *pgd = NULL; + + if (!mpgd) + return; + + mutex_lock(&nv_subdev(mmu)->mutex); + list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { + if (vpgd->obj == mpgd) { + pgd = vpgd->obj; + list_del(&vpgd->head); + kfree(vpgd); + break; + } + } + mutex_unlock(&nv_subdev(mmu)->mutex); + + nouveau_gpuobj_ref(NULL, &pgd); +} + +static void +nouveau_vm_del(struct kref *kref) +{ + struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount); + struct nouveau_vm_pgd *vpgd, *tmp; + + list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { + nouveau_vm_unlink(vm, vpgd->obj); + } + + nouveau_mm_fini(&vm->mm); + vfree(vm->pgt); + kfree(vm); +} + +int +nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, + struct nouveau_gpuobj *pgd) +{ + if (ref) { + int ret = nouveau_vm_link(ref, pgd); + if (ret) + return ret; + + kref_get(&ref->refcount); + } + + if (*ptr) { + nouveau_vm_unlink(*ptr, pgd); + kref_put(&(*ptr)->refcount, nouveau_vm_del); + } + + *ptr = ref; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c new file mode 100644 index 000000000000..a317d8f13570 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -0,0 +1,151 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include + +#include "nv04.h" + +#define NV04_PDMA_SIZE (128 * 1024 * 1024) +#define NV04_PDMA_PAGE ( 4 * 1024) + +/******************************************************************************* + * VM map/unmap callbacks + ******************************************************************************/ + +static void +nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +{ + pte = 0x00008 + (pte * 4); + while (cnt) { + u32 page = PAGE_SIZE / NV04_PDMA_PAGE; + u32 phys = (u32)*list++; + while (cnt && page--) { + nv_wo32(pgt, pte, phys | 3); + phys += NV04_PDMA_PAGE; + pte += 4; + cnt -= 1; + } + } +} + +static void +nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +{ + pte = 0x00008 + (pte * 4); + while (cnt--) { + nv_wo32(pgt, pte, 0x00000000); + pte += 4; + } +} + +static void +nv04_vm_flush(struct nouveau_vm *vm) +{ +} + +/******************************************************************************* + * VM object + ******************************************************************************/ + +int +nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart, + struct nouveau_vm **pvm) +{ + return -EINVAL; +} + +/******************************************************************************* + * MMU subdev + ******************************************************************************/ + +static int +nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv04_mmu_priv *priv; + struct nouveau_gpuobj *dma; + int ret; + + ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART", + "pcigart", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.create = nv04_vm_create; + priv->base.limit = NV04_PDMA_SIZE; + priv->base.dma_bits = 32; + priv->base.pgt_bits = 32 - 12; + priv->base.spg_shift = 12; + priv->base.lpg_shift = 12; + priv->base.map_sg = nv04_vm_map_sg; + priv->base.unmap = nv04_vm_unmap; + priv->base.flush = nv04_vm_flush; + + ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, + &priv->vm); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, + (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + + 8, 16, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); + dma = priv->vm->pgt[0].obj[0]; + priv->vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + + nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ + nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); + return 0; +} + +void +nv04_mmu_dtor(struct nouveau_object *object) +{ + struct nv04_mmu_priv *priv = (void *)object; + if (priv->vm) { + nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); + nouveau_vm_ref(NULL, &priv->vm, NULL); + } + if (priv->nullp) { + pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, + priv->nullp, priv->null); + } + nouveau_mmu_destroy(&priv->base); +} + +struct nouveau_oclass +nv04_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_mmu_ctor, + .dtor = nv04_mmu_dtor, + .init = _nouveau_mmu_init, + .fini = _nouveau_mmu_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h new file mode 100644 index 000000000000..919b254ef6a1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h @@ -0,0 +1,19 @@ +#ifndef __NV04_MMU_PRIV__ +#define __NV04_MMU_PRIV__ + +#include + +struct nv04_mmu_priv { + struct nouveau_mmu base; + struct nouveau_vm *vm; + dma_addr_t null; + void *nullp; +}; + +static inline struct nv04_mmu_priv * +nv04_mmu(void *obj) +{ + return (void *)nouveau_mmu(obj); +} + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c new file mode 100644 index 000000000000..61af036f1252 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -0,0 +1,159 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include +#include + +#include "nv04.h" + +#define NV41_GART_SIZE (512 * 1024 * 1024) +#define NV41_GART_PAGE ( 4 * 1024) + +/******************************************************************************* + * VM map/unmap callbacks + ******************************************************************************/ + +static void +nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +{ + pte = pte * 4; + while (cnt) { + u32 page = PAGE_SIZE / NV41_GART_PAGE; + u64 phys = (u64)*list++; + while (cnt && page--) { + nv_wo32(pgt, pte, (phys >> 7) | 1); + phys += NV41_GART_PAGE; + pte += 4; + cnt -= 1; + } + } +} + +static void +nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +{ + pte = pte * 4; + while (cnt--) { + nv_wo32(pgt, pte, 0x00000000); + pte += 4; + } +} + +static void +nv41_vm_flush(struct nouveau_vm *vm) +{ + struct nv04_mmu_priv *priv = (void *)vm->mmu; + + mutex_lock(&nv_subdev(priv)->mutex); + nv_wr32(priv, 0x100810, 0x00000022); + if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) { + nv_warn(priv, "flush timeout, 0x%08x\n", + nv_rd32(priv, 0x100810)); + } + nv_wr32(priv, 0x100810, 0x00000000); + mutex_unlock(&nv_subdev(priv)->mutex); +} + +/******************************************************************************* + * MMU subdev + ******************************************************************************/ + +static int +nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_device *device = nv_device(parent); + struct nv04_mmu_priv *priv; + int ret; + + if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || + !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { + return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, + data, size, pobject); + } + + ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", + "pciegart", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.create = nv04_vm_create; + priv->base.limit = NV41_GART_SIZE; + priv->base.dma_bits = 39; + priv->base.pgt_bits = 32 - 12; + priv->base.spg_shift = 12; + priv->base.lpg_shift = 12; + priv->base.map_sg = nv41_vm_map_sg; + priv->base.unmap = nv41_vm_unmap; + priv->base.flush = nv41_vm_flush; + + ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, + &priv->vm); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, + (NV41_GART_SIZE / NV41_GART_PAGE) * 4, + 16, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); + priv->vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + + return 0; +} + +static int +nv41_mmu_init(struct nouveau_object *object) +{ + struct nv04_mmu_priv *priv = (void *)object; + struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; + int ret; + + ret = nouveau_mmu_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, 0x100800, dma->addr | 0x00000002); + nv_mask(priv, 0x10008c, 0x00000100, 0x00000100); + nv_wr32(priv, 0x100820, 0x00000000); + return 0; +} + +struct nouveau_oclass +nv41_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x41), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv41_mmu_ctor, + .dtor = nv04_mmu_dtor, + .init = nv41_mmu_init, + .fini = _nouveau_mmu_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c new file mode 100644 index 000000000000..f5319e3e7fe5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -0,0 +1,249 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include +#include + +#include "nv04.h" + +#define NV44_GART_SIZE (512 * 1024 * 1024) +#define NV44_GART_PAGE ( 4 * 1024) + +/******************************************************************************* + * VM map/unmap callbacks + ******************************************************************************/ + +static void +nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, + dma_addr_t *list, u32 pte, u32 cnt) +{ + u32 base = (pte << 2) & ~0x0000000f; + u32 tmp[4]; + + tmp[0] = nv_ro32(pgt, base + 0x0); + tmp[1] = nv_ro32(pgt, base + 0x4); + tmp[2] = nv_ro32(pgt, base + 0x8); + tmp[3] = nv_ro32(pgt, base + 0xc); + + while (cnt--) { + u32 addr = list ? (*list++ >> 12) : (null >> 12); + switch (pte++ & 0x3) { + case 0: + tmp[0] &= ~0x07ffffff; + tmp[0] |= addr; + break; + case 1: + tmp[0] &= ~0xf8000000; + tmp[0] |= addr << 27; + tmp[1] &= ~0x003fffff; + tmp[1] |= addr >> 5; + break; + case 2: + tmp[1] &= ~0xffc00000; + tmp[1] |= addr << 22; + tmp[2] &= ~0x0001ffff; + tmp[2] |= addr >> 10; + break; + case 3: + tmp[2] &= ~0xfffe0000; + tmp[2] |= addr << 17; + tmp[3] &= ~0x00000fff; + tmp[3] |= addr >> 15; + break; + } + } + + nv_wo32(pgt, base + 0x0, tmp[0]); + nv_wo32(pgt, base + 0x4, tmp[1]); + nv_wo32(pgt, base + 0x8, tmp[2]); + nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000); +} + +static void +nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +{ + struct nv04_mmu_priv *priv = (void *)vma->vm->mmu; + u32 tmp[4]; + int i; + + if (pte & 3) { + u32 max = 4 - (pte & 3); + u32 part = (cnt > max) ? max : cnt; + nv44_vm_fill(pgt, priv->null, list, pte, part); + pte += part; + list += part; + cnt -= part; + } + + while (cnt >= 4) { + for (i = 0; i < 4; i++) + tmp[i] = *list++ >> 12; + nv_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); + nv_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); + nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); + nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); + cnt -= 4; + } + + if (cnt) + nv44_vm_fill(pgt, priv->null, list, pte, cnt); +} + +static void +nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +{ + struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt); + + if (pte & 3) { + u32 max = 4 - (pte & 3); + u32 part = (cnt > max) ? max : cnt; + nv44_vm_fill(pgt, priv->null, NULL, pte, part); + pte += part; + cnt -= part; + } + + while (cnt >= 4) { + nv_wo32(pgt, pte++ * 4, 0x00000000); + nv_wo32(pgt, pte++ * 4, 0x00000000); + nv_wo32(pgt, pte++ * 4, 0x00000000); + nv_wo32(pgt, pte++ * 4, 0x00000000); + cnt -= 4; + } + + if (cnt) + nv44_vm_fill(pgt, priv->null, NULL, pte, cnt); +} + +static void +nv44_vm_flush(struct nouveau_vm *vm) +{ + struct nv04_mmu_priv *priv = (void *)vm->mmu; + nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); + nv_wr32(priv, 0x100808, 0x00000020); + if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001)) + nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808)); + nv_wr32(priv, 0x100808, 0x00000000); +} + +/******************************************************************************* + * MMU subdev + ******************************************************************************/ + +static int +nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_device *device = nv_device(parent); + struct nv04_mmu_priv *priv; + int ret; + + if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || + !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { + return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, + data, size, pobject); + } + + ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", + "pciegart", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.create = nv04_vm_create; + priv->base.limit = NV44_GART_SIZE; + priv->base.dma_bits = 39; + priv->base.pgt_bits = 32 - 12; + priv->base.spg_shift = 12; + priv->base.lpg_shift = 12; + priv->base.map_sg = nv44_vm_map_sg; + priv->base.unmap = nv44_vm_unmap; + priv->base.flush = nv44_vm_flush; + + priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null); + if (!priv->nullp) { + nv_error(priv, "unable to allocate dummy pages\n"); + return -ENOMEM; + } + + ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, + &priv->vm); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, + (NV44_GART_SIZE / NV44_GART_PAGE) * 4, + 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); + priv->vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + + return 0; +} + +static int +nv44_mmu_init(struct nouveau_object *object) +{ + struct nv04_mmu_priv *priv = (void *)object; + struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; + u32 addr; + int ret; + + ret = nouveau_mmu_init(&priv->base); + if (ret) + return ret; + + /* calculate vram address of this PRAMIN block, object must be + * allocated on 512KiB alignment, and not exceed a total size + * of 512KiB for this to work correctly + */ + addr = nv_rd32(priv, 0x10020c); + addr -= ((gart->addr >> 19) + 1) << 19; + + nv_wr32(priv, 0x100850, 0x80000000); + nv_wr32(priv, 0x100818, priv->null); + nv_wr32(priv, 0x100804, NV44_GART_SIZE); + nv_wr32(priv, 0x100850, 0x00008000); + nv_mask(priv, 0x10008c, 0x00000200, 0x00000200); + nv_wr32(priv, 0x100820, 0x00000000); + nv_wr32(priv, 0x10082c, 0x00000001); + nv_wr32(priv, 0x100800, addr | 0x00000010); + return 0; +} + +struct nouveau_oclass +nv44_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x44), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv44_mmu_ctor, + .dtor = nv04_mmu_dtor, + .init = nv44_mmu_init, + .fini = _nouveau_mmu_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c new file mode 100644 index 000000000000..6ddc65dc684d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -0,0 +1,240 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include +#include +#include +#include + +struct nv50_mmu_priv { + struct nouveau_mmu base; +}; + +static void +nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, + struct nouveau_gpuobj *pgt[2]) +{ + u64 phys = 0xdeadcafe00000000ULL; + u32 coverage = 0; + + if (pgt[0]) { + phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ + coverage = (pgt[0]->size >> 3) << 12; + } else + if (pgt[1]) { + phys = 0x00000001 | pgt[1]->addr; /* present */ + coverage = (pgt[1]->size >> 3) << 16; + } + + if (phys & 1) { + if (coverage <= 32 * 1024 * 1024) + phys |= 0x60; + else if (coverage <= 64 * 1024 * 1024) + phys |= 0x40; + else if (coverage <= 128 * 1024 * 1024) + phys |= 0x20; + } + + nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); + nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); +} + +static inline u64 +vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +{ + phys |= 1; /* present */ + phys |= (u64)memtype << 40; + phys |= target << 4; + if (vma->access & NV_MEM_ACCESS_SYS) + phys |= (1 << 6); + if (!(vma->access & NV_MEM_ACCESS_WO)) + phys |= (1 << 3); + return phys; +} + +static void +nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +{ + u32 comp = (mem->memtype & 0x180) >> 7; + u32 block, target; + int i; + + /* IGPs don't have real VRAM, re-target to stolen system memory */ + target = 0; + if (nouveau_fb(vma->vm->mmu)->ram->stolen) { + phys += nouveau_fb(vma->vm->mmu)->ram->stolen; + target = 3; + } + + phys = vm_addr(vma, phys, mem->memtype, target); + pte <<= 3; + cnt <<= 3; + + while (cnt) { + u32 offset_h = upper_32_bits(phys); + u32 offset_l = lower_32_bits(phys); + + for (i = 7; i >= 0; i--) { + block = 1 << (i + 3); + if (cnt >= block && !(pte & (block - 1))) + break; + } + offset_l |= (i << 7); + + phys += block << (vma->node->type - 3); + cnt -= block; + if (comp) { + u32 tag = mem->tag->offset + ((delta >> 16) * comp); + offset_h |= (tag << 17); + delta += block << (vma->node->type - 3); + } + + while (block) { + nv_wo32(pgt, pte + 0, offset_l); + nv_wo32(pgt, pte + 4, offset_h); + pte += 8; + block -= 8; + } + } +} + +static void +nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +{ + u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; + pte <<= 3; + while (cnt--) { + u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); + nv_wo32(pgt, pte + 0, lower_32_bits(phys)); + nv_wo32(pgt, pte + 4, upper_32_bits(phys)); + pte += 8; + } +} + +static void +nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +{ + pte <<= 3; + while (cnt--) { + nv_wo32(pgt, pte + 0, 0x00000000); + nv_wo32(pgt, pte + 4, 0x00000000); + pte += 8; + } +} + +static void +nv50_vm_flush(struct nouveau_vm *vm) +{ + struct nv50_mmu_priv *priv = (void *)vm->mmu; + struct nouveau_bar *bar = nouveau_bar(priv); + struct nouveau_engine *engine; + int i, vme; + + bar->flush(bar); + + mutex_lock(&nv_subdev(priv)->mutex); + for (i = 0; i < NVDEV_SUBDEV_NR; i++) { + if (!atomic_read(&vm->engref[i])) + continue; + + /* unfortunate hw bug workaround... */ + engine = nouveau_engine(priv, i); + if (engine && engine->tlb_flush) { + engine->tlb_flush(engine); + continue; + } + + switch (i) { + case NVDEV_ENGINE_GR : vme = 0x00; break; + case NVDEV_ENGINE_VP : vme = 0x01; break; + case NVDEV_SUBDEV_BAR : vme = 0x06; break; + case NVDEV_ENGINE_PPP : + case NVDEV_ENGINE_MPEG : vme = 0x08; break; + case NVDEV_ENGINE_BSP : vme = 0x09; break; + case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; + case NVDEV_ENGINE_COPY0: vme = 0x0d; break; + default: + continue; + } + + nv_wr32(priv, 0x100c80, (vme << 16) | 1); + if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) + nv_error(priv, "vm flush timeout: engine %d\n", vme); + } + mutex_unlock(&nv_subdev(priv)->mutex); +} + +static int +nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, + u64 mm_offset, struct nouveau_vm **pvm) +{ + u32 block = (1 << (mmu->pgt_bits + 12)); + if (block > length) + block = length; + + return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm); +} + +static int +nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_mmu_priv *priv; + int ret; + + ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.limit = 1ULL << 40; + priv->base.dma_bits = 40; + priv->base.pgt_bits = 29 - 12; + priv->base.spg_shift = 12; + priv->base.lpg_shift = 16; + priv->base.create = nv50_vm_create; + priv->base.map_pgt = nv50_vm_map_pgt; + priv->base.map = nv50_vm_map; + priv->base.map_sg = nv50_vm_map_sg; + priv->base.unmap = nv50_vm_unmap; + priv->base.flush = nv50_vm_flush; + return 0; +} + +struct nouveau_oclass +nv50_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x50), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_mmu_ctor, + .dtor = _nouveau_mmu_dtor, + .init = _nouveau_mmu_init, + .fini = _nouveau_mmu_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c new file mode 100644 index 000000000000..bd695c59aac7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c @@ -0,0 +1,241 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include +#include +#include +#include +#include + +struct nvc0_mmu_priv { + struct nouveau_mmu base; +}; + + +/* Map from compressed to corresponding uncompressed storage type. + * The value 0xff represents an invalid storage type. + */ +const u8 nvc0_pte_storage_type_map[256] = +{ + 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ + 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 0x11, /* 0x10 */ + 0x11, 0x11, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x26, 0x27, /* 0x20 */ + 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 */ + 0xff, 0xff, 0x26, 0x27, 0x28, 0x29, 0x26, 0x27, + 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0x46, 0xff, /* 0x40 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x46, 0x46, 0x46, 0x46, 0xff, 0xff, 0xff, /* 0x50 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x60 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x70 */ + 0xff, 0xff, 0xff, 0x7b, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x7b, /* 0x80 */ + 0x7b, 0x7b, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x90 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xa7, /* 0xa0 */ + 0xa8, 0xa9, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, + 0xa8, 0xa9, 0xaa, 0xc3, 0xff, 0xff, 0xff, 0xff, /* 0xc0 */ + 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe, 0xc3, 0xc3, + 0xc3, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xd0 */ + 0xfe, 0xff, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, + 0xfe, 0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xff, /* 0xe0 */ + 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xfe, 0xff, + 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, /* 0xf0 */ + 0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff +}; + + +static void +nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, + struct nouveau_gpuobj *pgt[2]) +{ + u32 pde[2] = { 0, 0 }; + + if (pgt[0]) + pde[1] = 0x00000001 | (pgt[0]->addr >> 8); + if (pgt[1]) + pde[0] = 0x00000001 | (pgt[1]->addr >> 8); + + nv_wo32(pgd, (index * 8) + 0, pde[0]); + nv_wo32(pgd, (index * 8) + 4, pde[1]); +} + +static inline u64 +nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +{ + phys >>= 8; + + phys |= 0x00000001; /* present */ + if (vma->access & NV_MEM_ACCESS_SYS) + phys |= 0x00000002; + + phys |= ((u64)target << 32); + phys |= ((u64)memtype << 36); + + return phys; +} + +static void +nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +{ + u64 next = 1 << (vma->node->type - 8); + + phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); + pte <<= 3; + + if (mem->tag) { + struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu); + u32 tag = mem->tag->offset + (delta >> 17); + phys |= (u64)tag << (32 + 12); + next |= (u64)1 << (32 + 12); + ltc->tags_clear(ltc, tag, cnt); + } + + while (cnt--) { + nv_wo32(pgt, pte + 0, lower_32_bits(phys)); + nv_wo32(pgt, pte + 4, upper_32_bits(phys)); + phys += next; + pte += 8; + } +} + +static void +nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, + struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +{ + u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; + /* compressed storage types are invalid for system memory */ + u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; + + pte <<= 3; + while (cnt--) { + u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); + nv_wo32(pgt, pte + 0, lower_32_bits(phys)); + nv_wo32(pgt, pte + 4, upper_32_bits(phys)); + pte += 8; + } +} + +static void +nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +{ + pte <<= 3; + while (cnt--) { + nv_wo32(pgt, pte + 0, 0x00000000); + nv_wo32(pgt, pte + 4, 0x00000000); + pte += 8; + } +} + +static void +nvc0_vm_flush(struct nouveau_vm *vm) +{ + struct nvc0_mmu_priv *priv = (void *)vm->mmu; + struct nouveau_bar *bar = nouveau_bar(priv); + struct nouveau_vm_pgd *vpgd; + u32 type; + + bar->flush(bar); + + type = 0x00000001; /* PAGE_ALL */ + if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR])) + type |= 0x00000004; /* HUB_ONLY */ + + mutex_lock(&nv_subdev(priv)->mutex); + list_for_each_entry(vpgd, &vm->pgd_list, head) { + /* looks like maybe a "free flush slots" counter, the + * faster you write to 0x100cbc to more it decreases + */ + if (!nv_wait_ne(priv, 0x100c80, 0x00ff0000, 0x00000000)) { + nv_error(priv, "vm timeout 0: 0x%08x %d\n", + nv_rd32(priv, 0x100c80), type); + } + + nv_wr32(priv, 0x100cb8, vpgd->obj->addr >> 8); + nv_wr32(priv, 0x100cbc, 0x80000000 | type); + + /* wait for flush to be queued? */ + if (!nv_wait(priv, 0x100c80, 0x00008000, 0x00008000)) { + nv_error(priv, "vm timeout 1: 0x%08x %d\n", + nv_rd32(priv, 0x100c80), type); + } + } + mutex_unlock(&nv_subdev(priv)->mutex); +} + +static int +nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, + u64 mm_offset, struct nouveau_vm **pvm) +{ + return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm); +} + +static int +nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_mmu_priv *priv; + int ret; + + ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.limit = 1ULL << 40; + priv->base.dma_bits = 40; + priv->base.pgt_bits = 27 - 12; + priv->base.spg_shift = 12; + priv->base.lpg_shift = 17; + priv->base.create = nvc0_vm_create; + priv->base.map_pgt = nvc0_vm_map_pgt; + priv->base.map = nvc0_vm_map; + priv->base.map_sg = nvc0_vm_map_sg; + priv->base.unmap = nvc0_vm_unmap; + priv->base.flush = nvc0_vm_flush; + return 0; +} + +struct nouveau_oclass +nvc0_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0xc0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_mmu_ctor, + .dtor = _nouveau_mmu_dtor, + .init = _nouveau_mmu_init, + .fini = _nouveau_mmu_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild deleted file mode 100644 index b0290c056630..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild +++ /dev/null @@ -1,6 +0,0 @@ -nvkm-y += nvkm/subdev/vm/base.o -nvkm-y += nvkm/subdev/vm/nv04.o -nvkm-y += nvkm/subdev/vm/nv41.o -nvkm-y += nvkm/subdev/vm/nv44.o -nvkm-y += nvkm/subdev/vm/nv50.o -nvkm-y += nvkm/subdev/vm/nvc0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c deleted file mode 100644 index f75a683bd47a..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include -#include - -void -nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_mm_node *r; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - u32 end, len; - - delta = 0; - list_for_each_entry(r, &node->regions, rl_entry) { - u64 phys = (u64)r->offset << 12; - u32 num = r->length >> bits; - - while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - - end = (pte + num); - if (unlikely(end >= max)) - end = max; - len = end - pte; - - vmm->map(vma, pgt, node, pte, len, phys, delta); - - num -= len; - pte += len; - if (unlikely(end >= max)) { - phys += len << (bits + 12); - pde++; - pte = 0; - } - - delta += (u64)len << vma->node->type; - } - } - - vmm->flush(vm); -} - -static void -nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, - struct nouveau_mem *mem) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - unsigned m, sglen; - u32 end, len; - int i; - struct scatterlist *sg; - - for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - sglen = sg_dma_len(sg) >> PAGE_SHIFT; - - end = pte + sglen; - if (unlikely(end >= max)) - end = max; - len = end - pte; - - for (m = 0; m < len; m++) { - dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); - - vmm->map_sg(vma, pgt, mem, pte, 1, &addr); - num--; - pte++; - - if (num == 0) - goto finish; - } - if (unlikely(end >= max)) { - pde++; - pte = 0; - } - if (m < sglen) { - for (; m < sglen; m++) { - dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); - - vmm->map_sg(vma, pgt, mem, pte, 1, &addr); - num--; - pte++; - if (num == 0) - goto finish; - } - } - - } -finish: - vmm->flush(vm); -} - -static void -nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, - struct nouveau_mem *mem) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - dma_addr_t *list = mem->pages; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - u32 end, len; - - while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - - end = (pte + num); - if (unlikely(end >= max)) - end = max; - len = end - pte; - - vmm->map_sg(vma, pgt, mem, pte, len, list); - - num -= len; - pte += len; - list += len; - if (unlikely(end >= max)) { - pde++; - pte = 0; - } - } - - vmm->flush(vm); -} - -void -nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) -{ - if (node->sg) - nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); - else - if (node->pages) - nouveau_vm_map_sg(vma, 0, node->size << 12, node); - else - nouveau_vm_map_at(vma, 0, node); -} - -void -nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - u32 end, len; - - while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - - end = (pte + num); - if (unlikely(end >= max)) - end = max; - len = end - pte; - - vmm->unmap(pgt, pte, len); - - num -= len; - pte += len; - if (unlikely(end >= max)) { - pde++; - pte = 0; - } - } - - vmm->flush(vm); -} - -void -nouveau_vm_unmap(struct nouveau_vma *vma) -{ - nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); -} - -static void -nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgd *vpgd; - struct nouveau_vm_pgt *vpgt; - struct nouveau_gpuobj *pgt; - u32 pde; - - for (pde = fpde; pde <= lpde; pde++) { - vpgt = &vm->pgt[pde - vm->fpde]; - if (--vpgt->refcount[big]) - continue; - - pgt = vpgt->obj[big]; - vpgt->obj[big] = NULL; - - list_for_each_entry(vpgd, &vm->pgd_list, head) { - vmm->map_pgt(vpgd->obj, pde, vpgt->obj); - } - - mutex_unlock(&nv_subdev(vmm)->mutex); - nouveau_gpuobj_ref(NULL, &pgt); - mutex_lock(&nv_subdev(vmm)->mutex); - } -} - -static int -nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; - struct nouveau_vm_pgd *vpgd; - struct nouveau_gpuobj *pgt; - int big = (type != vmm->spg_shift); - u32 pgt_size; - int ret; - - pgt_size = (1 << (vmm->pgt_bits + 12)) >> type; - pgt_size *= 8; - - mutex_unlock(&nv_subdev(vmm)->mutex); - ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &pgt); - mutex_lock(&nv_subdev(vmm)->mutex); - if (unlikely(ret)) - return ret; - - /* someone beat us to filling the PDE while we didn't have the lock */ - if (unlikely(vpgt->refcount[big]++)) { - mutex_unlock(&nv_subdev(vmm)->mutex); - nouveau_gpuobj_ref(NULL, &pgt); - mutex_lock(&nv_subdev(vmm)->mutex); - return 0; - } - - vpgt->obj[big] = pgt; - list_for_each_entry(vpgd, &vm->pgd_list, head) { - vmm->map_pgt(vpgd->obj, pde, vpgt->obj); - } - - return 0; -} - -int -nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, - u32 access, struct nouveau_vma *vma) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - u32 align = (1 << page_shift) >> 12; - u32 msize = size >> 12; - u32 fpde, lpde, pde; - int ret; - - mutex_lock(&nv_subdev(vmm)->mutex); - ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, - &vma->node); - if (unlikely(ret != 0)) { - mutex_unlock(&nv_subdev(vmm)->mutex); - return ret; - } - - fpde = (vma->node->offset >> vmm->pgt_bits); - lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; - - for (pde = fpde; pde <= lpde; pde++) { - struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; - int big = (vma->node->type != vmm->spg_shift); - - if (likely(vpgt->refcount[big])) { - vpgt->refcount[big]++; - continue; - } - - ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); - if (ret) { - if (pde != fpde) - nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); - nouveau_mm_free(&vm->mm, &vma->node); - mutex_unlock(&nv_subdev(vmm)->mutex); - return ret; - } - } - mutex_unlock(&nv_subdev(vmm)->mutex); - - vma->vm = NULL; - nouveau_vm_ref(vm, &vma->vm, NULL); - vma->offset = (u64)vma->node->offset << 12; - vma->access = access; - return 0; -} - -void -nouveau_vm_put(struct nouveau_vma *vma) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - u32 fpde, lpde; - - if (unlikely(vma->node == NULL)) - return; - fpde = (vma->node->offset >> vmm->pgt_bits); - lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; - - mutex_lock(&nv_subdev(vmm)->mutex); - nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde); - nouveau_mm_free(&vm->mm, &vma->node); - mutex_unlock(&nv_subdev(vmm)->mutex); - - nouveau_vm_ref(NULL, &vma->vm, NULL); -} - -int -nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, - u64 mm_offset, u32 block, struct nouveau_vm **pvm) -{ - struct nouveau_vm *vm; - u64 mm_length = (offset + length) - mm_offset; - int ret; - - vm = kzalloc(sizeof(*vm), GFP_KERNEL); - if (!vm) - return -ENOMEM; - - INIT_LIST_HEAD(&vm->pgd_list); - vm->vmm = vmm; - kref_init(&vm->refcount); - vm->fpde = offset >> (vmm->pgt_bits + 12); - vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); - - vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); - if (!vm->pgt) { - kfree(vm); - return -ENOMEM; - } - - ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, - block >> 12); - if (ret) { - vfree(vm->pgt); - kfree(vm); - return ret; - } - - *pvm = vm; - - return 0; -} - -int -nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) -{ - struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); - return vmm->create(vmm, offset, length, mm_offset, pvm); -} - -static int -nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgd *vpgd; - int i; - - if (!pgd) - return 0; - - vpgd = kzalloc(sizeof(*vpgd), GFP_KERNEL); - if (!vpgd) - return -ENOMEM; - - nouveau_gpuobj_ref(pgd, &vpgd->obj); - - mutex_lock(&nv_subdev(vmm)->mutex); - for (i = vm->fpde; i <= vm->lpde; i++) - vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); - list_add(&vpgd->head, &vm->pgd_list); - mutex_unlock(&nv_subdev(vmm)->mutex); - return 0; -} - -static void -nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgd *vpgd, *tmp; - struct nouveau_gpuobj *pgd = NULL; - - if (!mpgd) - return; - - mutex_lock(&nv_subdev(vmm)->mutex); - list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { - if (vpgd->obj == mpgd) { - pgd = vpgd->obj; - list_del(&vpgd->head); - kfree(vpgd); - break; - } - } - mutex_unlock(&nv_subdev(vmm)->mutex); - - nouveau_gpuobj_ref(NULL, &pgd); -} - -static void -nouveau_vm_del(struct kref *kref) -{ - struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount); - struct nouveau_vm_pgd *vpgd, *tmp; - - list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { - nouveau_vm_unlink(vm, vpgd->obj); - } - - nouveau_mm_fini(&vm->mm); - vfree(vm->pgt); - kfree(vm); -} - -int -nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, - struct nouveau_gpuobj *pgd) -{ - if (ref) { - int ret = nouveau_vm_link(ref, pgd); - if (ret) - return ret; - - kref_get(&ref->refcount); - } - - if (*ptr) { - nouveau_vm_unlink(*ptr, pgd); - kref_put(&(*ptr)->refcount, nouveau_vm_del); - } - - *ptr = ref; - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c deleted file mode 100644 index ed45437167f2..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include - -#include "nv04.h" - -#define NV04_PDMA_SIZE (128 * 1024 * 1024) -#define NV04_PDMA_PAGE ( 4 * 1024) - -/******************************************************************************* - * VM map/unmap callbacks - ******************************************************************************/ - -static void -nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) -{ - pte = 0x00008 + (pte * 4); - while (cnt) { - u32 page = PAGE_SIZE / NV04_PDMA_PAGE; - u32 phys = (u32)*list++; - while (cnt && page--) { - nv_wo32(pgt, pte, phys | 3); - phys += NV04_PDMA_PAGE; - pte += 4; - cnt -= 1; - } - } -} - -static void -nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) -{ - pte = 0x00008 + (pte * 4); - while (cnt--) { - nv_wo32(pgt, pte, 0x00000000); - pte += 4; - } -} - -static void -nv04_vm_flush(struct nouveau_vm *vm) -{ -} - -/******************************************************************************* - * VM object - ******************************************************************************/ - -int -nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart, - struct nouveau_vm **pvm) -{ - return -EINVAL; -} - -/******************************************************************************* - * VMMGR subdev - ******************************************************************************/ - -static int -nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv04_vmmgr_priv *priv; - struct nouveau_gpuobj *dma; - int ret; - - ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART", - "pcigart", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.create = nv04_vm_create; - priv->base.limit = NV04_PDMA_SIZE; - priv->base.dma_bits = 32; - priv->base.pgt_bits = 32 - 12; - priv->base.spg_shift = 12; - priv->base.lpg_shift = 12; - priv->base.map_sg = nv04_vm_map_sg; - priv->base.unmap = nv04_vm_unmap; - priv->base.flush = nv04_vm_flush; - - ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, - &priv->vm); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + - 8, 16, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); - dma = priv->vm->pgt[0].obj[0]; - priv->vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; - - nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ - nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); - return 0; -} - -void -nv04_vmmgr_dtor(struct nouveau_object *object) -{ - struct nv04_vmmgr_priv *priv = (void *)object; - if (priv->vm) { - nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->vm, NULL); - } - if (priv->nullp) { - pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, - priv->nullp, priv->null); - } - nouveau_vmmgr_destroy(&priv->base); -} - -struct nouveau_oclass -nv04_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_vmmgr_ctor, - .dtor = nv04_vmmgr_dtor, - .init = _nouveau_vmmgr_init, - .fini = _nouveau_vmmgr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h deleted file mode 100644 index ec42d4bc86a6..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __NV04_VMMGR_PRIV__ -#define __NV04_VMMGR_PRIV__ - -#include - -struct nv04_vmmgr_priv { - struct nouveau_vmmgr base; - struct nouveau_vm *vm; - dma_addr_t null; - void *nullp; -}; - -static inline struct nv04_vmmgr_priv * -nv04_vmmgr(void *obj) -{ - return (void *)nouveau_vmmgr(obj); -} - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c deleted file mode 100644 index 064c76262876..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include -#include - -#include "nv04.h" - -#define NV41_GART_SIZE (512 * 1024 * 1024) -#define NV41_GART_PAGE ( 4 * 1024) - -/******************************************************************************* - * VM map/unmap callbacks - ******************************************************************************/ - -static void -nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) -{ - pte = pte * 4; - while (cnt) { - u32 page = PAGE_SIZE / NV41_GART_PAGE; - u64 phys = (u64)*list++; - while (cnt && page--) { - nv_wo32(pgt, pte, (phys >> 7) | 1); - phys += NV41_GART_PAGE; - pte += 4; - cnt -= 1; - } - } -} - -static void -nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) -{ - pte = pte * 4; - while (cnt--) { - nv_wo32(pgt, pte, 0x00000000); - pte += 4; - } -} - -static void -nv41_vm_flush(struct nouveau_vm *vm) -{ - struct nv04_vmmgr_priv *priv = (void *)vm->vmm; - - mutex_lock(&nv_subdev(priv)->mutex); - nv_wr32(priv, 0x100810, 0x00000022); - if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) { - nv_warn(priv, "flush timeout, 0x%08x\n", - nv_rd32(priv, 0x100810)); - } - nv_wr32(priv, 0x100810, 0x00000000); - mutex_unlock(&nv_subdev(priv)->mutex); -} - -/******************************************************************************* - * VMMGR subdev - ******************************************************************************/ - -static int -nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nv04_vmmgr_priv *priv; - int ret; - - if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || - !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { - return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, - data, size, pobject); - } - - ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", - "pciegart", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.create = nv04_vm_create; - priv->base.limit = NV41_GART_SIZE; - priv->base.dma_bits = 39; - priv->base.pgt_bits = 32 - 12; - priv->base.spg_shift = 12; - priv->base.lpg_shift = 12; - priv->base.map_sg = nv41_vm_map_sg; - priv->base.unmap = nv41_vm_unmap; - priv->base.flush = nv41_vm_flush; - - ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, - &priv->vm); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV41_GART_SIZE / NV41_GART_PAGE) * 4, - 16, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); - priv->vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; - - return 0; -} - -static int -nv41_vmmgr_init(struct nouveau_object *object) -{ - struct nv04_vmmgr_priv *priv = (void *)object; - struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; - int ret; - - ret = nouveau_vmmgr_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, 0x100800, dma->addr | 0x00000002); - nv_mask(priv, 0x10008c, 0x00000100, 0x00000100); - nv_wr32(priv, 0x100820, 0x00000000); - return 0; -} - -struct nouveau_oclass -nv41_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x41), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv41_vmmgr_ctor, - .dtor = nv04_vmmgr_dtor, - .init = nv41_vmmgr_init, - .fini = _nouveau_vmmgr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c deleted file mode 100644 index fae1f67d5948..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include -#include - -#include "nv04.h" - -#define NV44_GART_SIZE (512 * 1024 * 1024) -#define NV44_GART_PAGE ( 4 * 1024) - -/******************************************************************************* - * VM map/unmap callbacks - ******************************************************************************/ - -static void -nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, - dma_addr_t *list, u32 pte, u32 cnt) -{ - u32 base = (pte << 2) & ~0x0000000f; - u32 tmp[4]; - - tmp[0] = nv_ro32(pgt, base + 0x0); - tmp[1] = nv_ro32(pgt, base + 0x4); - tmp[2] = nv_ro32(pgt, base + 0x8); - tmp[3] = nv_ro32(pgt, base + 0xc); - - while (cnt--) { - u32 addr = list ? (*list++ >> 12) : (null >> 12); - switch (pte++ & 0x3) { - case 0: - tmp[0] &= ~0x07ffffff; - tmp[0] |= addr; - break; - case 1: - tmp[0] &= ~0xf8000000; - tmp[0] |= addr << 27; - tmp[1] &= ~0x003fffff; - tmp[1] |= addr >> 5; - break; - case 2: - tmp[1] &= ~0xffc00000; - tmp[1] |= addr << 22; - tmp[2] &= ~0x0001ffff; - tmp[2] |= addr >> 10; - break; - case 3: - tmp[2] &= ~0xfffe0000; - tmp[2] |= addr << 17; - tmp[3] &= ~0x00000fff; - tmp[3] |= addr >> 15; - break; - } - } - - nv_wo32(pgt, base + 0x0, tmp[0]); - nv_wo32(pgt, base + 0x4, tmp[1]); - nv_wo32(pgt, base + 0x8, tmp[2]); - nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000); -} - -static void -nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) -{ - struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm; - u32 tmp[4]; - int i; - - if (pte & 3) { - u32 max = 4 - (pte & 3); - u32 part = (cnt > max) ? max : cnt; - nv44_vm_fill(pgt, priv->null, list, pte, part); - pte += part; - list += part; - cnt -= part; - } - - while (cnt >= 4) { - for (i = 0; i < 4; i++) - tmp[i] = *list++ >> 12; - nv_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); - nv_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); - nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); - nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); - cnt -= 4; - } - - if (cnt) - nv44_vm_fill(pgt, priv->null, list, pte, cnt); -} - -static void -nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) -{ - struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt); - - if (pte & 3) { - u32 max = 4 - (pte & 3); - u32 part = (cnt > max) ? max : cnt; - nv44_vm_fill(pgt, priv->null, NULL, pte, part); - pte += part; - cnt -= part; - } - - while (cnt >= 4) { - nv_wo32(pgt, pte++ * 4, 0x00000000); - nv_wo32(pgt, pte++ * 4, 0x00000000); - nv_wo32(pgt, pte++ * 4, 0x00000000); - nv_wo32(pgt, pte++ * 4, 0x00000000); - cnt -= 4; - } - - if (cnt) - nv44_vm_fill(pgt, priv->null, NULL, pte, cnt); -} - -static void -nv44_vm_flush(struct nouveau_vm *vm) -{ - struct nv04_vmmgr_priv *priv = (void *)vm->vmm; - nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); - nv_wr32(priv, 0x100808, 0x00000020); - if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001)) - nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808)); - nv_wr32(priv, 0x100808, 0x00000000); -} - -/******************************************************************************* - * VMMGR subdev - ******************************************************************************/ - -static int -nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nv04_vmmgr_priv *priv; - int ret; - - if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || - !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { - return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, - data, size, pobject); - } - - ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", - "pciegart", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.create = nv04_vm_create; - priv->base.limit = NV44_GART_SIZE; - priv->base.dma_bits = 39; - priv->base.pgt_bits = 32 - 12; - priv->base.spg_shift = 12; - priv->base.lpg_shift = 12; - priv->base.map_sg = nv44_vm_map_sg; - priv->base.unmap = nv44_vm_unmap; - priv->base.flush = nv44_vm_flush; - - priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null); - if (!priv->nullp) { - nv_error(priv, "unable to allocate dummy pages\n"); - return -ENOMEM; - } - - ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, - &priv->vm); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV44_GART_SIZE / NV44_GART_PAGE) * 4, - 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); - priv->vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; - - return 0; -} - -static int -nv44_vmmgr_init(struct nouveau_object *object) -{ - struct nv04_vmmgr_priv *priv = (void *)object; - struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; - u32 addr; - int ret; - - ret = nouveau_vmmgr_init(&priv->base); - if (ret) - return ret; - - /* calculate vram address of this PRAMIN block, object must be - * allocated on 512KiB alignment, and not exceed a total size - * of 512KiB for this to work correctly - */ - addr = nv_rd32(priv, 0x10020c); - addr -= ((gart->addr >> 19) + 1) << 19; - - nv_wr32(priv, 0x100850, 0x80000000); - nv_wr32(priv, 0x100818, priv->null); - nv_wr32(priv, 0x100804, NV44_GART_SIZE); - nv_wr32(priv, 0x100850, 0x00008000); - nv_mask(priv, 0x10008c, 0x00000200, 0x00000200); - nv_wr32(priv, 0x100820, 0x00000000); - nv_wr32(priv, 0x10082c, 0x00000001); - nv_wr32(priv, 0x100800, addr | 0x00000010); - return 0; -} - -struct nouveau_oclass -nv44_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x44), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv44_vmmgr_ctor, - .dtor = nv04_vmmgr_dtor, - .init = nv44_vmmgr_init, - .fini = _nouveau_vmmgr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c deleted file mode 100644 index a4aa81a2173b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include -#include -#include -#include - -struct nv50_vmmgr_priv { - struct nouveau_vmmgr base; -}; - -static void -nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, - struct nouveau_gpuobj *pgt[2]) -{ - u64 phys = 0xdeadcafe00000000ULL; - u32 coverage = 0; - - if (pgt[0]) { - phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ - coverage = (pgt[0]->size >> 3) << 12; - } else - if (pgt[1]) { - phys = 0x00000001 | pgt[1]->addr; /* present */ - coverage = (pgt[1]->size >> 3) << 16; - } - - if (phys & 1) { - if (coverage <= 32 * 1024 * 1024) - phys |= 0x60; - else if (coverage <= 64 * 1024 * 1024) - phys |= 0x40; - else if (coverage <= 128 * 1024 * 1024) - phys |= 0x20; - } - - nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); - nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); -} - -static inline u64 -vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) -{ - phys |= 1; /* present */ - phys |= (u64)memtype << 40; - phys |= target << 4; - if (vma->access & NV_MEM_ACCESS_SYS) - phys |= (1 << 6); - if (!(vma->access & NV_MEM_ACCESS_WO)) - phys |= (1 << 3); - return phys; -} - -static void -nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) -{ - u32 comp = (mem->memtype & 0x180) >> 7; - u32 block, target; - int i; - - /* IGPs don't have real VRAM, re-target to stolen system memory */ - target = 0; - if (nouveau_fb(vma->vm->vmm)->ram->stolen) { - phys += nouveau_fb(vma->vm->vmm)->ram->stolen; - target = 3; - } - - phys = vm_addr(vma, phys, mem->memtype, target); - pte <<= 3; - cnt <<= 3; - - while (cnt) { - u32 offset_h = upper_32_bits(phys); - u32 offset_l = lower_32_bits(phys); - - for (i = 7; i >= 0; i--) { - block = 1 << (i + 3); - if (cnt >= block && !(pte & (block - 1))) - break; - } - offset_l |= (i << 7); - - phys += block << (vma->node->type - 3); - cnt -= block; - if (comp) { - u32 tag = mem->tag->offset + ((delta >> 16) * comp); - offset_h |= (tag << 17); - delta += block << (vma->node->type - 3); - } - - while (block) { - nv_wo32(pgt, pte + 0, offset_l); - nv_wo32(pgt, pte + 4, offset_h); - pte += 8; - block -= 8; - } - } -} - -static void -nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) -{ - u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; - pte <<= 3; - while (cnt--) { - u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); - nv_wo32(pgt, pte + 0, lower_32_bits(phys)); - nv_wo32(pgt, pte + 4, upper_32_bits(phys)); - pte += 8; - } -} - -static void -nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) -{ - pte <<= 3; - while (cnt--) { - nv_wo32(pgt, pte + 0, 0x00000000); - nv_wo32(pgt, pte + 4, 0x00000000); - pte += 8; - } -} - -static void -nv50_vm_flush(struct nouveau_vm *vm) -{ - struct nv50_vmmgr_priv *priv = (void *)vm->vmm; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_engine *engine; - int i, vme; - - bar->flush(bar); - - mutex_lock(&nv_subdev(priv)->mutex); - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { - if (!atomic_read(&vm->engref[i])) - continue; - - /* unfortunate hw bug workaround... */ - engine = nouveau_engine(priv, i); - if (engine && engine->tlb_flush) { - engine->tlb_flush(engine); - continue; - } - - switch (i) { - case NVDEV_ENGINE_GR : vme = 0x00; break; - case NVDEV_ENGINE_VP : vme = 0x01; break; - case NVDEV_SUBDEV_BAR : vme = 0x06; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : vme = 0x08; break; - case NVDEV_ENGINE_BSP : vme = 0x09; break; - case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; - case NVDEV_ENGINE_COPY0: vme = 0x0d; break; - default: - continue; - } - - nv_wr32(priv, 0x100c80, (vme << 16) | 1); - if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) - nv_error(priv, "vm flush timeout: engine %d\n", vme); - } - mutex_unlock(&nv_subdev(priv)->mutex); -} - -static int -nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) -{ - u32 block = (1 << (vmm->pgt_bits + 12)); - if (block > length) - block = length; - - return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm); -} - -static int -nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv50_vmmgr_priv *priv; - int ret; - - ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.limit = 1ULL << 40; - priv->base.dma_bits = 40; - priv->base.pgt_bits = 29 - 12; - priv->base.spg_shift = 12; - priv->base.lpg_shift = 16; - priv->base.create = nv50_vm_create; - priv->base.map_pgt = nv50_vm_map_pgt; - priv->base.map = nv50_vm_map; - priv->base.map_sg = nv50_vm_map_sg; - priv->base.unmap = nv50_vm_unmap; - priv->base.flush = nv50_vm_flush; - return 0; -} - -struct nouveau_oclass -nv50_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_vmmgr_ctor, - .dtor = _nouveau_vmmgr_dtor, - .init = _nouveau_vmmgr_init, - .fini = _nouveau_vmmgr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c deleted file mode 100644 index c0a3389204fa..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include -#include -#include -#include -#include - -struct nvc0_vmmgr_priv { - struct nouveau_vmmgr base; -}; - - -/* Map from compressed to corresponding uncompressed storage type. - * The value 0xff represents an invalid storage type. - */ -const u8 nvc0_pte_storage_type_map[256] = -{ - 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ - 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 0x11, /* 0x10 */ - 0x11, 0x11, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x26, 0x27, /* 0x20 */ - 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 */ - 0xff, 0xff, 0x26, 0x27, 0x28, 0x29, 0x26, 0x27, - 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0x46, 0xff, /* 0x40 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x46, 0x46, 0x46, 0x46, 0xff, 0xff, 0xff, /* 0x50 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x60 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x70 */ - 0xff, 0xff, 0xff, 0x7b, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x7b, /* 0x80 */ - 0x7b, 0x7b, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x90 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xa7, /* 0xa0 */ - 0xa8, 0xa9, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, - 0xa8, 0xa9, 0xaa, 0xc3, 0xff, 0xff, 0xff, 0xff, /* 0xc0 */ - 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe, 0xc3, 0xc3, - 0xc3, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xd0 */ - 0xfe, 0xff, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, - 0xfe, 0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xff, /* 0xe0 */ - 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xfe, 0xff, - 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, /* 0xf0 */ - 0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff -}; - - -static void -nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, - struct nouveau_gpuobj *pgt[2]) -{ - u32 pde[2] = { 0, 0 }; - - if (pgt[0]) - pde[1] = 0x00000001 | (pgt[0]->addr >> 8); - if (pgt[1]) - pde[0] = 0x00000001 | (pgt[1]->addr >> 8); - - nv_wo32(pgd, (index * 8) + 0, pde[0]); - nv_wo32(pgd, (index * 8) + 4, pde[1]); -} - -static inline u64 -nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) -{ - phys >>= 8; - - phys |= 0x00000001; /* present */ - if (vma->access & NV_MEM_ACCESS_SYS) - phys |= 0x00000002; - - phys |= ((u64)target << 32); - phys |= ((u64)memtype << 36); - - return phys; -} - -static void -nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) -{ - u64 next = 1 << (vma->node->type - 8); - - phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); - pte <<= 3; - - if (mem->tag) { - struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->vmm); - u32 tag = mem->tag->offset + (delta >> 17); - phys |= (u64)tag << (32 + 12); - next |= (u64)1 << (32 + 12); - ltc->tags_clear(ltc, tag, cnt); - } - - while (cnt--) { - nv_wo32(pgt, pte + 0, lower_32_bits(phys)); - nv_wo32(pgt, pte + 4, upper_32_bits(phys)); - phys += next; - pte += 8; - } -} - -static void -nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) -{ - u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; - /* compressed storage types are invalid for system memory */ - u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; - - pte <<= 3; - while (cnt--) { - u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); - nv_wo32(pgt, pte + 0, lower_32_bits(phys)); - nv_wo32(pgt, pte + 4, upper_32_bits(phys)); - pte += 8; - } -} - -static void -nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) -{ - pte <<= 3; - while (cnt--) { - nv_wo32(pgt, pte + 0, 0x00000000); - nv_wo32(pgt, pte + 4, 0x00000000); - pte += 8; - } -} - -static void -nvc0_vm_flush(struct nouveau_vm *vm) -{ - struct nvc0_vmmgr_priv *priv = (void *)vm->vmm; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_vm_pgd *vpgd; - u32 type; - - bar->flush(bar); - - type = 0x00000001; /* PAGE_ALL */ - if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR])) - type |= 0x00000004; /* HUB_ONLY */ - - mutex_lock(&nv_subdev(priv)->mutex); - list_for_each_entry(vpgd, &vm->pgd_list, head) { - /* looks like maybe a "free flush slots" counter, the - * faster you write to 0x100cbc to more it decreases - */ - if (!nv_wait_ne(priv, 0x100c80, 0x00ff0000, 0x00000000)) { - nv_error(priv, "vm timeout 0: 0x%08x %d\n", - nv_rd32(priv, 0x100c80), type); - } - - nv_wr32(priv, 0x100cb8, vpgd->obj->addr >> 8); - nv_wr32(priv, 0x100cbc, 0x80000000 | type); - - /* wait for flush to be queued? */ - if (!nv_wait(priv, 0x100c80, 0x00008000, 0x00008000)) { - nv_error(priv, "vm timeout 1: 0x%08x %d\n", - nv_rd32(priv, 0x100c80), type); - } - } - mutex_unlock(&nv_subdev(priv)->mutex); -} - -static int -nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) -{ - return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm); -} - -static int -nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_vmmgr_priv *priv; - int ret; - - ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - priv->base.limit = 1ULL << 40; - priv->base.dma_bits = 40; - priv->base.pgt_bits = 27 - 12; - priv->base.spg_shift = 12; - priv->base.lpg_shift = 17; - priv->base.create = nvc0_vm_create; - priv->base.map_pgt = nvc0_vm_map_pgt; - priv->base.map = nvc0_vm_map; - priv->base.map_sg = nvc0_vm_map_sg; - priv->base.unmap = nvc0_vm_unmap; - priv->base.flush = nvc0_vm_flush; - return 0; -} - -struct nouveau_oclass -nvc0_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_vmmgr_ctor, - .dtor = _nouveau_vmmgr_dtor, - .init = _nouveau_vmmgr_init, - .fini = _nouveau_vmmgr_fini, - }, -}; -- cgit v1.2.3-59-g8ed1b From b8bf04e1fd3aba5cdd81ec766fc0372c7894497c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 12:02:28 +1000 Subject: drm/nouveau/gr: rename from graph (no binary change) Shorter device name, match Tegra and our existing enums. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/class.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/device.h | 4 +- drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 86 + .../gpu/drm/nouveau/include/nvkm/engine/graph.h | 86 - drivers/gpu/drm/nouveau/nouveau_abi16.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 36 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h | 129 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c | 104 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 63 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 1032 ++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c | 565 ++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 695 ++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 3347 ++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c | 1386 ++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h | 202 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c | 805 +++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c | 109 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c | 360 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c | 282 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c | 530 ++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c | 1020 ++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c | 843 +++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc | 335 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc | 378 +++ .../drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 | 42 + .../drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h | 473 +++ .../drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 | 42 + .../drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h | 473 +++ .../drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 | 42 + .../drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h | 530 ++++ .../drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 | 42 + .../drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h | 537 ++++ .../drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 | 42 + .../drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h | 537 ++++ .../drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 | 42 + .../drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h | 537 ++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc | 696 ++++ .../drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 | 40 + .../drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h | 916 ++++++ .../drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 | 40 + .../drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h | 916 ++++++ .../drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 | 40 + .../drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h | 1047 ++++++ .../drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 | 40 + .../drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h | 1047 ++++++ .../drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 | 40 + .../drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h | 1044 ++++++ .../drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 | 40 + .../drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h | 1044 ++++++ .../gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc | 229 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h | 8 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 117 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 48 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 469 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 1388 ++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 1319 ++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c | 224 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 383 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 31 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 166 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 133 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 237 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 167 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 165 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 536 ++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 24 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 1009 ++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h | 7 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c | 1667 ++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h | 270 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c | 133 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c | 128 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c | 115 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c | 137 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c | 191 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c | 347 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c | 245 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h | 274 ++ drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild | 36 - drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h | 129 - .../gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c | 104 - .../gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c | 63 - .../gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c | 1032 ------ .../gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c | 565 ---- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c | 695 ---- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c | 3347 -------------------- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c | 1386 -------- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h | 202 -- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c | 805 ----- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c | 109 - .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c | 360 --- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c | 282 -- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c | 530 ---- .../gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c | 1020 ------ .../gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c | 843 ----- .../gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc | 335 -- .../gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc | 378 --- .../nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5 | 42 - .../nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h | 473 --- .../nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5 | 42 - .../nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h | 473 --- .../drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3 | 42 - .../nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h | 530 ---- .../drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3 | 42 - .../nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h | 537 ---- .../drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3 | 42 - .../nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h | 537 ---- .../drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3 | 42 - .../nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h | 537 ---- .../gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc | 696 ---- .../nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5 | 40 - .../nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h | 916 ------ .../nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5 | 40 - .../nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h | 916 ------ .../drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3 | 40 - .../nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h | 1047 ------ .../drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3 | 40 - .../nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h | 1047 ------ .../drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3 | 40 - .../nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h | 1044 ------ .../drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3 | 40 - .../nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h | 1044 ------ .../drm/nouveau/nvkm/engine/graph/fuc/macros.fuc | 229 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h | 8 - drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c | 117 - drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c | 48 - drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c | 469 --- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c | 1388 -------- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c | 1319 -------- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c | 224 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c | 383 --- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h | 31 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c | 166 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c | 133 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c | 237 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c | 167 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c | 165 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c | 536 ---- drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h | 24 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c | 1009 ------ drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h | 7 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c | 1667 ---------- drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h | 270 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c | 133 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c | 128 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c | 115 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c | 137 - drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c | 191 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c | 347 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c | 245 -- drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h | 274 -- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c | 6 +- 163 files changed, 32850 insertions(+), 32850 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c') diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 0fe20917e05d..c88bb7c1010e 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -122,7 +122,7 @@ struct nv_device_v0 { #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL -#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL +#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 93acd5153bee..7f1770beff21 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -52,11 +52,11 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); #include #include -#include +#include #include #define nvkm_fifo(a) nouveau_fifo(nvkm_device(a)) #define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a)) -#define nvkm_gr(a) ((struct nouveau_graph *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR)) +#define nvkm_gr(a) ((struct nouveau_gr *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR)) #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h new file mode 100644 index 000000000000..9985adca0fda --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -0,0 +1,86 @@ +#ifndef __NOUVEAU_GR_H__ +#define __NOUVEAU_GR_H__ + +#include +#include +#include + +struct nouveau_gr_chan { + struct nouveau_engctx base; +}; + +#define nouveau_gr_context_create(p,e,c,g,s,a,f,d) \ + nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +#define nouveau_gr_context_destroy(d) \ + nouveau_engctx_destroy(&(d)->base) +#define nouveau_gr_context_init(d) \ + nouveau_engctx_init(&(d)->base) +#define nouveau_gr_context_fini(d,s) \ + nouveau_engctx_fini(&(d)->base, (s)) + +#define _nouveau_gr_context_dtor _nouveau_engctx_dtor +#define _nouveau_gr_context_init _nouveau_engctx_init +#define _nouveau_gr_context_fini _nouveau_engctx_fini +#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32 +#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32 + +struct nouveau_gr { + struct nouveau_engine base; + + /* Returns chipset-specific counts of units packed into an u64. + */ + u64 (*units)(struct nouveau_gr *); +}; + +static inline struct nouveau_gr * +nouveau_gr(void *obj) +{ + return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR); +} + +#define nouveau_gr_create(p,e,c,y,d) \ + nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d)) +#define nouveau_gr_destroy(d) \ + nouveau_engine_destroy(&(d)->base) +#define nouveau_gr_init(d) \ + nouveau_engine_init(&(d)->base) +#define nouveau_gr_fini(d,s) \ + nouveau_engine_fini(&(d)->base, (s)) + +#define _nouveau_gr_dtor _nouveau_engine_dtor +#define _nouveau_gr_init _nouveau_engine_init +#define _nouveau_gr_fini _nouveau_engine_fini + +extern struct nouveau_oclass nv04_gr_oclass; +extern struct nouveau_oclass nv10_gr_oclass; +extern struct nouveau_oclass nv20_gr_oclass; +extern struct nouveau_oclass nv25_gr_oclass; +extern struct nouveau_oclass nv2a_gr_oclass; +extern struct nouveau_oclass nv30_gr_oclass; +extern struct nouveau_oclass nv34_gr_oclass; +extern struct nouveau_oclass nv35_gr_oclass; +extern struct nouveau_oclass nv40_gr_oclass; +extern struct nouveau_oclass nv50_gr_oclass; +extern struct nouveau_oclass *nvc0_gr_oclass; +extern struct nouveau_oclass *nvc1_gr_oclass; +extern struct nouveau_oclass *nvc4_gr_oclass; +extern struct nouveau_oclass *nvc8_gr_oclass; +extern struct nouveau_oclass *nvd7_gr_oclass; +extern struct nouveau_oclass *nvd9_gr_oclass; +extern struct nouveau_oclass *nve4_gr_oclass; +extern struct nouveau_oclass *gk20a_gr_oclass; +extern struct nouveau_oclass *nvf0_gr_oclass; +extern struct nouveau_oclass *gk110b_gr_oclass; +extern struct nouveau_oclass *nv108_gr_oclass; +extern struct nouveau_oclass *gm107_gr_oclass; + +extern const struct nouveau_bitfield nv04_gr_nsource[]; +extern struct nouveau_ofuncs nv04_gr_ofuncs; +bool nv04_gr_idle(void *obj); + +extern const struct nouveau_bitfield nv10_gr_intr_name[]; +extern const struct nouveau_bitfield nv10_gr_nstatus[]; + +extern const struct nouveau_enum nv50_data_error_names[]; + +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h deleted file mode 100644 index d61dcb7d6d5f..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef __NOUVEAU_GRAPH_H__ -#define __NOUVEAU_GRAPH_H__ - -#include -#include -#include - -struct nouveau_graph_chan { - struct nouveau_engctx base; -}; - -#define nouveau_graph_context_create(p,e,c,g,s,a,f,d) \ - nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) -#define nouveau_graph_context_destroy(d) \ - nouveau_engctx_destroy(&(d)->base) -#define nouveau_graph_context_init(d) \ - nouveau_engctx_init(&(d)->base) -#define nouveau_graph_context_fini(d,s) \ - nouveau_engctx_fini(&(d)->base, (s)) - -#define _nouveau_graph_context_dtor _nouveau_engctx_dtor -#define _nouveau_graph_context_init _nouveau_engctx_init -#define _nouveau_graph_context_fini _nouveau_engctx_fini -#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32 -#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32 - -struct nouveau_graph { - struct nouveau_engine base; - - /* Returns chipset-specific counts of units packed into an u64. - */ - u64 (*units)(struct nouveau_graph *); -}; - -static inline struct nouveau_graph * -nouveau_graph(void *obj) -{ - return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR); -} - -#define nouveau_graph_create(p,e,c,y,d) \ - nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d)) -#define nouveau_graph_destroy(d) \ - nouveau_engine_destroy(&(d)->base) -#define nouveau_graph_init(d) \ - nouveau_engine_init(&(d)->base) -#define nouveau_graph_fini(d,s) \ - nouveau_engine_fini(&(d)->base, (s)) - -#define _nouveau_graph_dtor _nouveau_engine_dtor -#define _nouveau_graph_init _nouveau_engine_init -#define _nouveau_graph_fini _nouveau_engine_fini - -extern struct nouveau_oclass nv04_graph_oclass; -extern struct nouveau_oclass nv10_graph_oclass; -extern struct nouveau_oclass nv20_graph_oclass; -extern struct nouveau_oclass nv25_graph_oclass; -extern struct nouveau_oclass nv2a_graph_oclass; -extern struct nouveau_oclass nv30_graph_oclass; -extern struct nouveau_oclass nv34_graph_oclass; -extern struct nouveau_oclass nv35_graph_oclass; -extern struct nouveau_oclass nv40_graph_oclass; -extern struct nouveau_oclass nv50_graph_oclass; -extern struct nouveau_oclass *nvc0_graph_oclass; -extern struct nouveau_oclass *nvc1_graph_oclass; -extern struct nouveau_oclass *nvc4_graph_oclass; -extern struct nouveau_oclass *nvc8_graph_oclass; -extern struct nouveau_oclass *nvd7_graph_oclass; -extern struct nouveau_oclass *nvd9_graph_oclass; -extern struct nouveau_oclass *nve4_graph_oclass; -extern struct nouveau_oclass *gk20a_graph_oclass; -extern struct nouveau_oclass *nvf0_graph_oclass; -extern struct nouveau_oclass *gk110b_graph_oclass; -extern struct nouveau_oclass *nv108_graph_oclass; -extern struct nouveau_oclass *gm107_graph_oclass; - -extern const struct nouveau_bitfield nv04_graph_nsource[]; -extern struct nouveau_ofuncs nv04_graph_ofuncs; -bool nv04_graph_idle(void *obj); - -extern const struct nouveau_bitfield nv10_graph_intr_name[]; -extern const struct nouveau_bitfield nv10_graph_nstatus[]; - -extern const struct nouveau_enum nv50_data_error_names[]; - -#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index d39a15000068..16ab6b187a52 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -165,7 +165,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; struct nouveau_timer *ptimer = nvkm_timer(device); - struct nouveau_graph *graph = nvkm_gr(device); + struct nouveau_gr *gr = nvkm_gr(device); struct drm_nouveau_getparam *getparam = data; switch (getparam->param) { @@ -215,7 +215,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) getparam->value = 1; break; case NOUVEAU_GETPARAM_GRAPH_UNITS: - getparam->value = graph->units ? graph->units(graph) : 0; + getparam->value = gr->units ? gr->units(gr) : 0; break; default: NV_PRINTK(debug, cli, "unknown parameter %lld\n", getparam->param); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index 71d6542147a2..183475e2a924 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -8,7 +8,7 @@ include $(src)/nvkm/engine/device/Kbuild include $(src)/nvkm/engine/disp/Kbuild include $(src)/nvkm/engine/dmaobj/Kbuild include $(src)/nvkm/engine/fifo/Kbuild -include $(src)/nvkm/engine/graph/Kbuild +include $(src)/nvkm/engine/gr/Kbuild include $(src)/nvkm/engine/mpeg/Kbuild include $(src)/nvkm/engine/msvld/Kbuild include $(src)/nvkm/engine/perfmon/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 96050a487226..baad4ad22058 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -228,7 +228,7 @@ static const u64 disable_map[] = { [NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO, [NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO, - [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GRAPH, + [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GR, [NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG, [NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME, [NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index c9c18dc6f216..e7289fd2da9b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -46,7 +46,7 @@ #include #include #include -#include +#include #include #include #include @@ -86,7 +86,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; #if 0 @@ -130,7 +130,7 @@ gm100_identify(struct nouveau_device *device) #if 0 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #endif device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; #if 0 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 7f98385acec7..dcb53917b5e0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include int @@ -59,7 +59,7 @@ nv04_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: @@ -77,7 +77,7 @@ nv04_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 6a7ece0fc789..f292e7b88628 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include int @@ -59,7 +59,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: @@ -78,7 +78,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: @@ -97,7 +97,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: @@ -116,7 +116,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: @@ -135,7 +135,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: @@ -154,7 +154,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: @@ -173,7 +173,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: @@ -192,7 +192,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index e3b17fde89e6..a03420ca82b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -39,7 +39,7 @@ #include #include #include -#include +#include #include int @@ -62,7 +62,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: @@ -81,7 +81,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: @@ -100,7 +100,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: @@ -119,7 +119,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 8f67f4d402d7..59b6baa64b4c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include #include @@ -62,7 +62,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: @@ -81,7 +81,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: @@ -100,7 +100,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -120,7 +120,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -140,7 +140,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 49c68d7c093c..3b16fdc4c95e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include #include @@ -68,7 +68,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -91,7 +91,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -114,7 +114,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -137,7 +137,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -160,7 +160,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -183,7 +183,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -206,7 +206,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -229,7 +229,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -252,7 +252,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -275,7 +275,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -298,7 +298,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -321,7 +321,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -344,7 +344,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -367,7 +367,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -390,7 +390,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; @@ -413,7 +413,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index cb978023d472..a9788b4999c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -44,7 +44,7 @@ #include #include #include -#include +#include #include #include #include @@ -81,7 +81,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; @@ -107,7 +107,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; @@ -136,7 +136,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; @@ -165,7 +165,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; @@ -194,7 +194,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; @@ -223,7 +223,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; @@ -252,7 +252,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; @@ -281,7 +281,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; @@ -310,7 +310,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; @@ -339,7 +339,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; @@ -369,7 +369,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; @@ -400,7 +400,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; @@ -430,7 +430,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; @@ -460,7 +460,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 39bf7d115bc6..1f93c9611f37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -46,7 +46,7 @@ #include #include #include -#include +#include #include #include #include @@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 1f6d515fb641..c18f5821c3cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -46,7 +46,7 @@ #include #include #include -#include +#include #include #include #include @@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; @@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; @@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; @@ -177,7 +177,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; @@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; @@ -241,7 +241,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; @@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; @@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild new file mode 100644 index 000000000000..ce508e85b8f0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -0,0 +1,36 @@ +nvkm-y += nvkm/engine/gr/ctxnv40.o +nvkm-y += nvkm/engine/gr/ctxnv50.o +nvkm-y += nvkm/engine/gr/ctxnvc0.o +nvkm-y += nvkm/engine/gr/ctxnvc1.o +nvkm-y += nvkm/engine/gr/ctxnvc4.o +nvkm-y += nvkm/engine/gr/ctxnvc8.o +nvkm-y += nvkm/engine/gr/ctxnvd7.o +nvkm-y += nvkm/engine/gr/ctxnvd9.o +nvkm-y += nvkm/engine/gr/ctxnve4.o +nvkm-y += nvkm/engine/gr/ctxgk20a.o +nvkm-y += nvkm/engine/gr/ctxnvf0.o +nvkm-y += nvkm/engine/gr/ctxgk110b.o +nvkm-y += nvkm/engine/gr/ctxnv108.o +nvkm-y += nvkm/engine/gr/ctxgm107.o +nvkm-y += nvkm/engine/gr/nv04.o +nvkm-y += nvkm/engine/gr/nv10.o +nvkm-y += nvkm/engine/gr/nv20.o +nvkm-y += nvkm/engine/gr/nv25.o +nvkm-y += nvkm/engine/gr/nv2a.o +nvkm-y += nvkm/engine/gr/nv30.o +nvkm-y += nvkm/engine/gr/nv34.o +nvkm-y += nvkm/engine/gr/nv35.o +nvkm-y += nvkm/engine/gr/nv40.o +nvkm-y += nvkm/engine/gr/nv50.o +nvkm-y += nvkm/engine/gr/nvc0.o +nvkm-y += nvkm/engine/gr/nvc1.o +nvkm-y += nvkm/engine/gr/nvc4.o +nvkm-y += nvkm/engine/gr/nvc8.o +nvkm-y += nvkm/engine/gr/nvd7.o +nvkm-y += nvkm/engine/gr/nvd9.o +nvkm-y += nvkm/engine/gr/nve4.o +nvkm-y += nvkm/engine/gr/gk20a.o +nvkm-y += nvkm/engine/gr/nvf0.o +nvkm-y += nvkm/engine/gr/gk110b.o +nvkm-y += nvkm/engine/gr/nv108.o +nvkm-y += nvkm/engine/gr/gm107.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h new file mode 100644 index 000000000000..e1947013d3bc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h @@ -0,0 +1,129 @@ +#ifndef __NOUVEAU_GRCTX_H__ +#define __NOUVEAU_GRCTX_H__ + +struct nouveau_grctx { + struct nouveau_device *device; + + enum { + NOUVEAU_GRCTX_PROG, + NOUVEAU_GRCTX_VALS + } mode; + void *data; + + u32 ctxprog_max; + u32 ctxprog_len; + u32 ctxprog_reg; + int ctxprog_label[32]; + u32 ctxvals_pos; + u32 ctxvals_base; +}; + +static inline void +cp_out(struct nouveau_grctx *ctx, u32 inst) +{ + u32 *ctxprog = ctx->data; + + if (ctx->mode != NOUVEAU_GRCTX_PROG) + return; + + BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); + ctxprog[ctx->ctxprog_len++] = inst; +} + +static inline void +cp_lsr(struct nouveau_grctx *ctx, u32 val) +{ + cp_out(ctx, CP_LOAD_SR | val); +} + +static inline void +cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length) +{ + ctx->ctxprog_reg = (reg - 0x00400000) >> 2; + + ctx->ctxvals_base = ctx->ctxvals_pos; + ctx->ctxvals_pos = ctx->ctxvals_base + length; + + if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) { + cp_lsr(ctx, length); + length = 0; + } + + cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg); +} + +static inline void +cp_name(struct nouveau_grctx *ctx, int name) +{ + u32 *ctxprog = ctx->data; + int i; + + if (ctx->mode != NOUVEAU_GRCTX_PROG) + return; + + ctx->ctxprog_label[name] = ctx->ctxprog_len; + for (i = 0; i < ctx->ctxprog_len; i++) { + if ((ctxprog[i] & 0xfff00000) != 0xff400000) + continue; + if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT)) + continue; + ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | + (ctx->ctxprog_len << CP_BRA_IP_SHIFT); + } +} + +static inline void +_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) +{ + int ip = 0; + + if (mod != 2) { + ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT; + if (ip == 0) + ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); + } + + cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | + (state ? 0 : CP_BRA_IF_CLEAR)); +} +#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) +#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) +#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) + +static inline void +_cp_wait(struct nouveau_grctx *ctx, int flag, int state) +{ + cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); +} +#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) + +static inline void +_cp_set(struct nouveau_grctx *ctx, int flag, int state) +{ + cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); +} +#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) + +static inline void +cp_pos(struct nouveau_grctx *ctx, int offset) +{ + ctx->ctxvals_pos = offset; + ctx->ctxvals_base = ctx->ctxvals_pos; + + cp_lsr(ctx, ctx->ctxvals_pos); + cp_out(ctx, CP_SET_CONTEXT_POINTER); +} + +static inline void +gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val) +{ + if (ctx->mode != NOUVEAU_GRCTX_VALS) + return; + + reg = (reg - 0x00400000) / 4; + reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; + + nv_wo32(ctx->data, reg * 4, val); +} + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c new file mode 100644 index 000000000000..05a69ca48f25 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c @@ -0,0 +1,104 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +gk110b_grctx_init_sm_0[] = { + { 0x419e04, 1, 0x04, 0x00000000 }, + { 0x419e08, 1, 0x04, 0x0000001d }, + { 0x419e0c, 1, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00001c02 }, + { 0x419e44, 1, 0x04, 0x0013eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 2, 0x04, 0x00000000 }, + { 0x419e58, 1, 0x04, 0x00000001 }, + { 0x419e5c, 3, 0x04, 0x00000000 }, + { 0x419e68, 1, 0x04, 0x00000002 }, + { 0x419e6c, 12, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x00001f8f }, + { 0x419eb0, 1, 0x04, 0x0db00d2f }, + { 0x419eb8, 1, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0001304f }, + { 0x419f30, 4, 0x04, 0x00000000 }, + { 0x419f40, 1, 0x04, 0x00000018 }, + { 0x419f44, 3, 0x04, 0x00000000 }, + { 0x419f58, 1, 0x04, 0x00000000 }, + { 0x419f70, 1, 0x04, 0x00006300 }, + { 0x419f78, 1, 0x04, 0x000000eb }, + { 0x419f7c, 1, 0x04, 0x00000404 }, + {} +}; + +static const struct nvc0_gr_pack +gk110b_grctx_pack_tpc[] = { + { nvd7_grctx_init_pe_0 }, + { nvf0_grctx_init_tex_0 }, + { nvf0_grctx_init_mpc_0 }, + { nvf0_grctx_init_l1c_0 }, + { gk110b_grctx_init_sm_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +struct nouveau_oclass * +gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xf1), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nve4_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = nvf0_grctx_pack_hub, + .gpc = nvf0_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = gk110b_grctx_pack_tpc, + .ppc = nvf0_grctx_pack_ppc, + .icmd = nvf0_grctx_pack_icmd, + .mthd = nvf0_grctx_pack_mthd, + .bundle = nve4_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0x180, + .bundle_token_limit = 0x600, + .pagepool = nve4_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvd7_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x7ff, + .alpha_nr = 0x648, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c new file mode 100644 index 000000000000..5aae94ced9ed --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "ctxnvc0.h" + +static const struct nvc0_gr_pack +gk20a_grctx_pack_mthd[] = { + { nve4_grctx_init_a097_0, 0xa297 }, + { nvc0_grctx_init_902d_0, 0x902d }, + {} +}; + +struct nouveau_oclass * +gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xea), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nve4_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = nve4_grctx_pack_hub, + .gpc = nve4_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nve4_grctx_pack_tpc, + .ppc = nve4_grctx_pack_ppc, + .icmd = nve4_grctx_pack_icmd, + .mthd = gk20a_grctx_pack_mthd, + .bundle = nve4_grctx_generate_bundle, + .bundle_size = 0x1800, + .bundle_min_gpm_fifo_depth = 0x62, + .bundle_token_limit = 0x100, + .pagepool = nve4_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvd7_grctx_generate_attrib, + .attrib_nr_max = 0x240, + .attrib_nr = 0x240, + .alpha_nr_max = 0x648 + (0x648 / 2), + .alpha_nr = 0x648, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c new file mode 100644 index 000000000000..cf6199fe3b59 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -0,0 +1,1032 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +gm107_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x0000b1, 2, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000a8, 1, 0x01, 0x0000ffff }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002f2, 2, 0x01, 0x00000001 }, + { 0x0002f5, 1, 0x01, 0x00000001 }, + { 0x0002f7, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x0000de, 1, 0x01, 0x00000001 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000383, 1, 0x01, 0x00000011 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x0005d0, 1, 0x01, 0x20181008 }, + { 0x0005d1, 1, 0x01, 0x40383028 }, + { 0x0005d2, 1, 0x01, 0x60585048 }, + { 0x0005d3, 1, 0x01, 0x80787068 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000550, 32, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x000595, 1, 0x01, 0x00400040 }, + { 0x000596, 1, 0x01, 0x00000492 }, + { 0x000597, 1, 0x01, 0x08080203 }, + { 0x0005ad, 1, 0x01, 0x00000008 }, + { 0x000598, 1, 0x01, 0x00020001 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000662, 1, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000a0d, 1, 0x01, 0x00000006 }, + { 0x00097d, 1, 0x01, 0x0000000c }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000687, 1, 0x01, 0x003fffff }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00400008 }, + { 0x000841, 1, 0x01, 0x08000080 }, + { 0x000842, 1, 0x01, 0x00400008 }, + { 0x000843, 1, 0x01, 0x08000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000008 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_pack +gm107_grctx_pack_icmd[] = { + { gm107_grctx_init_icmd_0 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_b097_0[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x001480, 8, 0x10, 0x00000000 }, + { 0x001484, 8, 0x10, 0x00000000 }, + { 0x001488, 8, 0x10, 0x00000000 }, + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000754, 1, 0x04, 0x00000001 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001080, 2, 0x04, 0x00000000 }, + { 0x001088, 2, 0x04, 0x00000001 }, + { 0x001090, 1, 0x04, 0x00000000 }, + { 0x001094, 1, 0x04, 0x00000001 }, + { 0x001098, 1, 0x04, 0x00000000 }, + { 0x00109c, 1, 0x04, 0x00000001 }, + { 0x0010a0, 2, 0x04, 0x00000000 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x000f40, 5, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00000fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x000fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00260c, 1, 0x04, 0x00000000 }, + { 0x0007ac, 1, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x0002e4, 1, 0x04, 0x0000b001 }, + { 0x00036c, 2, 0x04, 0x00000000 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000f60, 1, 0x04, 0x00000000 }, + { 0x000f64, 1, 0x04, 0x00400040 }, + { 0x000f68, 1, 0x04, 0x00002212 }, + { 0x000f6c, 1, 0x04, 0x08080203 }, + { 0x001108, 1, 0x04, 0x00000008 }, + { 0x000f70, 1, 0x04, 0x00080001 }, + { 0x000ffc, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 4, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x000dd0, 1, 0x04, 0x00000000 }, + { 0x000dd4, 1, 0x04, 0x00000001 }, + { 0x0002f4, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x0007a4, 2, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x000f14, 1, 0x04, 0x00000000 }, + { 0x000374, 1, 0x04, 0x00000000 }, + { 0x000378, 1, 0x04, 0x0000000c }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000da8, 1, 0x04, 0x00000030 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x0002d0, 1, 0x04, 0x003fffff }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00400008 }, + { 0x001284, 1, 0x04, 0x08000080 }, + { 0x001450, 1, 0x04, 0x00400008 }, + { 0x001454, 1, 0x04, 0x08000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +gm107_grctx_pack_mthd[] = { + { gm107_grctx_init_b097_0, 0xb097 }, + { nvc0_grctx_init_902d_0, 0x902d }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_fe_0[] = { + { 0x404004, 8, 0x04, 0x00000000 }, + { 0x404024, 1, 0x04, 0x0000e000 }, + { 0x404028, 8, 0x04, 0x00000000 }, + { 0x4040a8, 8, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf800008f }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404100, 10, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000045 }, + { 0x40417c, 2, 0x04, 0x00000000 }, + { 0x404194, 1, 0x04, 0x01000700 }, + { 0x4041a0, 4, 0x04, 0x00000000 }, + { 0x404200, 4, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x0f8001bf }, + { 0x405830, 1, 0x04, 0x0aa01000 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + { 0x405a1c, 1, 0x04, 0x000000ff }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x07410001 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b0, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x80400280 }, + { 0x4064c4, 1, 0x04, 0x0400ffff }, + { 0x4064c8, 1, 0x04, 0x018001ff }, + { 0x4064cc, 9, 0x04, 0x00000000 }, + { 0x4064fc, 1, 0x04, 0x0000022a }, + { 0x406500, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x32802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1003e005 }, + { 0x408840, 1, 0x04, 0x0000000b }, + { 0x408900, 1, 0x04, 0xb080b801 }, + { 0x408904, 1, 0x04, 0x63038001 }, + { 0x408908, 1, 0x04, 0x02c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static const struct nvc0_gr_pack +gm107_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { gm107_grctx_init_fe_0 }, + { nvf0_grctx_init_pri_0 }, + { nve4_grctx_init_memfmt_0 }, + { gm107_grctx_init_ds_0 }, + { nvf0_grctx_init_cwd_0 }, + { gm107_grctx_init_pd_0 }, + { nv108_grctx_init_rstr2d_0 }, + { nve4_grctx_init_scc_0 }, + { gm107_grctx_init_be_0 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_gpc_unk_0[] = { + { 0x418380, 1, 0x04, 0x00000056 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_gpc_unk_1[] = { + { 0x418600, 1, 0x04, 0x0000007f }, + { 0x418684, 1, 0x04, 0x0000001f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 1, 0x04, 0x40000000 }, + { 0x41870c, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x7006863a }, + { 0x418810, 1, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00000044 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100058 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_gpc_unk_2[] = { + { 0x418d24, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x90000000 }, + { 0x418e24, 1, 0x04, 0x00000000 }, + { 0x418e28, 1, 0x04, 0x00000030 }, + { 0x418e30, 1, 0x04, 0x00000000 }, + { 0x418e34, 1, 0x04, 0x00010000 }, + { 0x418e38, 1, 0x04, 0x00000000 }, + { 0x418e40, 22, 0x04, 0x00000000 }, + { 0x418ea0, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +gm107_grctx_pack_gpc[] = { + { gm107_grctx_init_gpc_unk_0 }, + { nv108_grctx_init_prop_0 }, + { gm107_grctx_init_gpc_unk_1 }, + { gm107_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nv108_grctx_init_crstr_0 }, + { nve4_grctx_init_gpm_0 }, + { gm107_grctx_init_gpc_unk_2 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000300f0 }, + { 0x419a04, 1, 0x04, 0x00000005 }, + { 0x419a08, 1, 0x04, 0x00000421 }, + { 0x419a0c, 1, 0x04, 0x00120000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00002200 }, + { 0x419a1c, 1, 0x04, 0x0000c000 }, + { 0x419a20, 1, 0x04, 0x20008a00 }, + { 0x419a30, 1, 0x04, 0x00000001 }, + { 0x419a3c, 1, 0x04, 0x00000002 }, + { 0x419ac4, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_mpc_0[] = { + { 0x419c00, 1, 0x04, 0x0000001a }, + { 0x419c04, 1, 0x04, 0x80000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + { 0x419c2c, 1, 0x04, 0x00000000 }, + { 0x419c34, 1, 0x04, 0x01ff1ff3 }, + { 0x419c3c, 1, 0x04, 0x00001919 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_l1c_0[] = { + { 0x419c84, 1, 0x04, 0x00000020 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_sm_0[] = { + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00001c02 }, + { 0x419e44, 1, 0x04, 0x00d3eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 1, 0x04, 0x00000000 }, + { 0x419e60, 4, 0x04, 0x00000000 }, + { 0x419e74, 10, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x0001cf8b }, + { 0x419eb0, 1, 0x04, 0x00030300 }, + { 0x419eb8, 1, 0x04, 0x00000000 }, + { 0x419ef0, 24, 0x04, 0x00000000 }, + { 0x419f68, 2, 0x04, 0x00000000 }, + { 0x419f70, 1, 0x04, 0x00000020 }, + { 0x419f78, 1, 0x04, 0x000003eb }, + { 0x419f7c, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +gm107_grctx_pack_tpc[] = { + { nvd7_grctx_init_pe_0 }, + { gm107_grctx_init_tex_0 }, + { gm107_grctx_init_mpc_0 }, + { gm107_grctx_init_l1c_0 }, + { gm107_grctx_init_sm_0 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_cbm_0[] = { + { 0x41bec0, 1, 0x04, 0x00000000 }, + { 0x41bec4, 1, 0x04, 0x01050000 }, + { 0x41bee4, 1, 0x04, 0x00000000 }, + { 0x41bef0, 1, 0x04, 0x000003ff }, + { 0x41bef4, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_grctx_init_wwdx_0[] = { + { 0x41bf00, 1, 0x04, 0x0a418820 }, + { 0x41bf04, 1, 0x04, 0x062080e6 }, + { 0x41bf08, 1, 0x04, 0x020398a4 }, + { 0x41bf0c, 1, 0x04, 0x0e629062 }, + { 0x41bf10, 1, 0x04, 0x0a418820 }, + { 0x41bf14, 1, 0x04, 0x000000e6 }, + { 0x41bfd0, 1, 0x04, 0x00900103 }, + { 0x41bfe0, 1, 0x04, 0x80000000 }, + { 0x41bfe4, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +gm107_grctx_pack_ppc[] = { + { nve4_grctx_init_pes_0 }, + { gm107_grctx_init_cbm_0 }, + { gm107_grctx_init_wwdx_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +static void +gm107_grctx_generate_bundle(struct nvc0_grctx *info) +{ + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, + impl->bundle_size / 0x20); + const u32 token_limit = impl->bundle_token_limit; + const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; + const int s = 8; + const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); + mmio_refn(info, 0x408004, 0x00000000, s, b); + mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); + mmio_refn(info, 0x418e24, 0x00000000, s, b); + mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b); + mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); +} + +static void +gm107_grctx_generate_pagepool(struct nvc0_grctx *info) +{ + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; + const int s = 8; + const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); + mmio_refn(info, 0x40800c, 0x00000000, s, b); + mmio_wr32(info, 0x408010, 0x80000000); + mmio_refn(info, 0x419004, 0x00000000, s, b); + mmio_wr32(info, 0x419008, 0x00000000); + mmio_wr32(info, 0x4064cc, 0x80000000); + mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */ +} + +static void +gm107_grctx_generate_attrib(struct nvc0_grctx *info) +{ + struct nvc0_gr_priv *priv = info->priv; + const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv); + const u32 alpha = impl->alpha_nr; + const u32 attrib = impl->attrib_nr; + const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const u32 access = NV_MEM_ACCESS_RW; + const int s = 12; + const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int max_batches = 0xffff; + u32 bo = 0; + u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; + int gpc, ppc, n = 0; + + mmio_refn(info, 0x418810, 0x80000000, s, b); + mmio_refn(info, 0x419848, 0x10000000, s, b); + mmio_refn(info, 0x419c2c, 0x10000000, s, b); + mmio_wr32(info, 0x405830, (attrib << 16) | alpha); + mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) { + const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc]; + const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc]; + const u32 u = 0x418ea0 + (n * 0x04); + const u32 o = PPC_UNIT(gpc, ppc, 0); + mmio_wr32(info, o + 0xc0, bs); + mmio_wr32(info, o + 0xf4, bo); + bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + mmio_wr32(info, o + 0xe4, as); + mmio_wr32(info, o + 0xf8, ao); + ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs); + } + } +} + +static void +gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv) +{ + int gpc, tpc, id; + + for (tpc = 0, id = 0; tpc < 4; tpc++) { + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + if (tpc < priv->tpc_nr[gpc]) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); + id++; + } + + nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); + } + } +} + +static void +gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int i; + + nvc0_gr_mmio(priv, oclass->hub); + nvc0_gr_mmio(priv, oclass->gpc); + nvc0_gr_mmio(priv, oclass->zcull); + nvc0_gr_mmio(priv, oclass->tpc); + nvc0_gr_mmio(priv, oclass->ppc); + + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->bundle(info); + oclass->pagepool(info); + oclass->attrib(info); + oclass->unkn(priv); + + gm107_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nve4_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + nv_wr32(priv, 0x4064d0, 0x00000001); + for (i = 1; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(priv, 0x406500, 0x00000001); + + nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + + if (priv->gpc_nr == 1) { + nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); + nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); + } else { + nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); + nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); + } + + nvc0_gr_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_gr_mthd(priv, oclass->mthd); + + nv_mask(priv, 0x419e00, 0x00808080, 0x00808080); + nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000); + nv_mask(priv, 0x419f80, 0x80000000, 0x80000000); + nv_mask(priv, 0x419f88, 0x80000000, 0x80000000); +} + +struct nouveau_oclass * +gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0x08), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = gm107_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = gm107_grctx_pack_hub, + .gpc = gm107_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = gm107_grctx_pack_tpc, + .ppc = gm107_grctx_pack_ppc, + .icmd = gm107_grctx_pack_icmd, + .mthd = gm107_grctx_pack_mthd, + .bundle = gm107_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0x180, + .bundle_token_limit = 0x2c0, + .pagepool = gm107_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = gm107_grctx_generate_attrib, + .attrib_nr_max = 0xff0, + .attrib_nr = 0xaa0, + .alpha_nr_max = 0x1800, + .alpha_nr = 0x1000, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c new file mode 100644 index 000000000000..f56d77e307c1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c @@ -0,0 +1,565 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nv108_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x0002f2, 2, 0x01, 0x00000001 }, + { 0x0002f5, 1, 0x01, 0x00000001 }, + { 0x0002f7, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000383, 1, 0x01, 0x00000011 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000662, 1, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x00080b, 1, 0x01, 0x00000002 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000a0d, 1, 0x01, 0x00000006 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x003fffff }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00400008 }, + { 0x000841, 1, 0x01, 0x08000080 }, + { 0x000842, 1, 0x01, 0x00400008 }, + { 0x000843, 1, 0x01, 0x08000080 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000008 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_pack +nv108_grctx_pack_icmd[] = { + { nv108_grctx_init_icmd_0 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_fe_0[] = { + { 0x404004, 8, 0x04, 0x00000000 }, + { 0x404024, 1, 0x04, 0x0000e000 }, + { 0x404028, 8, 0x04, 0x00000000 }, + { 0x4040a8, 8, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf800008f }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404100, 10, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x40417c, 2, 0x04, 0x00000000 }, + { 0x404194, 1, 0x04, 0x01000700 }, + { 0x4041a0, 4, 0x04, 0x00000000 }, + { 0x404200, 1, 0x04, 0x0000a197 }, + { 0x404204, 1, 0x04, 0x0000a1c0 }, + { 0x404208, 1, 0x04, 0x0000a140 }, + { 0x40420c, 1, 0x04, 0x0000902d }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180648 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + { 0x405a1c, 1, 0x04, 0x000000ff }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x034103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b0, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x802000f0 }, + { 0x4064c4, 1, 0x04, 0x0192ffff }, + { 0x4064c8, 1, 0x04, 0x00c20200 }, + { 0x4064cc, 9, 0x04, 0x00000000 }, + { 0x4064fc, 1, 0x04, 0x0000022a }, + {} +}; + +const struct nvc0_gr_init +nv108_grctx_init_rstr2d_0[] = { + { 0x407804, 1, 0x04, 0x00000063 }, + { 0x40780c, 1, 0x04, 0x0a418820 }, + { 0x407810, 1, 0x04, 0x062080e6 }, + { 0x407814, 1, 0x04, 0x020398a4 }, + { 0x407818, 1, 0x04, 0x0e629062 }, + { 0x40781c, 1, 0x04, 0x0a418820 }, + { 0x407820, 1, 0x04, 0x000000e6 }, + { 0x4078bc, 1, 0x04, 0x00000103 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x32802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1003e005 }, + { 0x408840, 1, 0x04, 0x0000000b }, + { 0x408900, 1, 0x04, 0xb080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x02c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static const struct nvc0_gr_pack +nv108_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nv108_grctx_init_fe_0 }, + { nvf0_grctx_init_pri_0 }, + { nve4_grctx_init_memfmt_0 }, + { nv108_grctx_init_ds_0 }, + { nvf0_grctx_init_cwd_0 }, + { nv108_grctx_init_pd_0 }, + { nv108_grctx_init_rstr2d_0 }, + { nve4_grctx_init_scc_0 }, + { nv108_grctx_init_be_0 }, + {} +}; + +const struct nvc0_gr_init +nv108_grctx_init_prop_0[] = { + { 0x418400, 1, 0x04, 0x38005e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x02200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_gpc_unk_1[] = { + { 0x418600, 1, 0x04, 0x0000007f }, + { 0x418684, 1, 0x04, 0x0000001f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 2, 0x04, 0x00000080 }, + { 0x41870c, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x7006863a }, + { 0x418808, 1, 0x04, 0x00000000 }, + { 0x41880c, 1, 0x04, 0x00000030 }, + { 0x418810, 1, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00000044 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100058 }, + {} +}; + +const struct nvc0_gr_init +nv108_grctx_init_crstr_0[] = { + { 0x418b00, 1, 0x04, 0x0000001e }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_gpm_0[] = { + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c40, 1, 0x04, 0xffffffff }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x2020000c }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_pack +nv108_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nv108_grctx_init_prop_0 }, + { nv108_grctx_init_gpc_unk_1 }, + { nv108_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nv108_grctx_init_crstr_0 }, + { nv108_grctx_init_gpm_0 }, + { nvf0_grctx_init_gpc_unk_2 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000100f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000421 }, + { 0x419a0c, 1, 0x04, 0x00120000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x0000c000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419a30, 1, 0x04, 0x00000001 }, + { 0x419ac4, 1, 0x04, 0x0037f440 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_sm_0[] = { + { 0x419e04, 1, 0x04, 0x00000000 }, + { 0x419e08, 1, 0x04, 0x0000001d }, + { 0x419e0c, 1, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00001c02 }, + { 0x419e44, 1, 0x04, 0x0013eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 2, 0x04, 0x00000000 }, + { 0x419e58, 1, 0x04, 0x00000001 }, + { 0x419e5c, 3, 0x04, 0x00000000 }, + { 0x419e68, 1, 0x04, 0x00000002 }, + { 0x419e6c, 12, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x00001f8f }, + { 0x419eb0, 1, 0x04, 0x0db00d2f }, + { 0x419eb8, 1, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0001304f }, + { 0x419f30, 4, 0x04, 0x00000000 }, + { 0x419f40, 1, 0x04, 0x00000018 }, + { 0x419f44, 3, 0x04, 0x00000000 }, + { 0x419f58, 1, 0x04, 0x00000020 }, + { 0x419f70, 1, 0x04, 0x00000000 }, + { 0x419f78, 1, 0x04, 0x000001eb }, + { 0x419f7c, 1, 0x04, 0x00000404 }, + {} +}; + +static const struct nvc0_gr_pack +nv108_grctx_pack_tpc[] = { + { nvd7_grctx_init_pe_0 }, + { nv108_grctx_init_tex_0 }, + { nvf0_grctx_init_mpc_0 }, + { nvf0_grctx_init_l1c_0 }, + { nv108_grctx_init_sm_0 }, + {} +}; + +static const struct nvc0_gr_init +nv108_grctx_init_cbm_0[] = { + { 0x41bec0, 1, 0x04, 0x10000000 }, + { 0x41bec4, 1, 0x04, 0x00037f7f }, + { 0x41bee4, 1, 0x04, 0x00000000 }, + { 0x41bef0, 1, 0x04, 0x000003ff }, + {} +}; + +static const struct nvc0_gr_pack +nv108_grctx_pack_ppc[] = { + { nve4_grctx_init_pes_0 }, + { nv108_grctx_init_cbm_0 }, + { nvd7_grctx_init_wwdx_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +struct nouveau_oclass * +nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0x08), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nve4_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = nv108_grctx_pack_hub, + .gpc = nv108_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nv108_grctx_pack_tpc, + .ppc = nv108_grctx_pack_ppc, + .icmd = nv108_grctx_pack_icmd, + .mthd = nvf0_grctx_pack_mthd, + .bundle = nve4_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0xc2, + .bundle_token_limit = 0x200, + .pagepool = nve4_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvd7_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x7ff, + .alpha_nr = 0x648, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c new file mode 100644 index 000000000000..9e311411f1b1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c @@ -0,0 +1,695 @@ +/* + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include + +/* NVIDIA context programs handle a number of other conditions which are + * not implemented in our versions. It's not clear why NVIDIA context + * programs have this code, nor whether it's strictly necessary for + * correct operation. We'll implement additional handling if/when we + * discover it's necessary. + * + * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" + * flag is set, this gets saved into the context. + * - On context save, the context program for all cards load nsource + * into a flag register and check for ILLEGAL_MTHD. If it's set, + * opcode 0x60000d is called before resuming normal operation. + * - Some context programs check more conditions than the above. NV44 + * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) + * and calls 0x60000d before resuming normal operation. + * - At the very beginning of NVIDIA's context programs, flag 9 is checked + * and if true 0x800001 is called with count=0, pos=0, the flag is cleared + * and then the ctxprog is aborted. It looks like a complicated NOP, + * its purpose is unknown. + * - In the section of code that loads the per-vs state, NVIDIA check + * flag 10. If it's set, they only transfer the small 0x300 byte block + * of state + the state for a single vs as opposed to the state for + * all vs units. It doesn't seem likely that it'll occur in normal + * operation, especially seeing as it appears NVIDIA may have screwed + * up the ctxprogs for some cards and have an invalid instruction + * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. + * - There's a number of places where context offset 0 (where we place + * the PRAMIN offset of the context) is loaded into either 0x408000, + * 0x408004 or 0x408008. Not sure what's up there either. + * - The ctxprogs for some cards save 0x400a00 again during the cleanup + * path for auto-loadctx. + */ + +#define CP_FLAG_CLEAR 0 +#define CP_FLAG_SET 1 +#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) +#define CP_FLAG_SWAP_DIRECTION_LOAD 0 +#define CP_FLAG_SWAP_DIRECTION_SAVE 1 +#define CP_FLAG_USER_SAVE ((0 * 32) + 5) +#define CP_FLAG_USER_SAVE_NOT_PENDING 0 +#define CP_FLAG_USER_SAVE_PENDING 1 +#define CP_FLAG_USER_LOAD ((0 * 32) + 6) +#define CP_FLAG_USER_LOAD_NOT_PENDING 0 +#define CP_FLAG_USER_LOAD_PENDING 1 +#define CP_FLAG_STATUS ((3 * 32) + 0) +#define CP_FLAG_STATUS_IDLE 0 +#define CP_FLAG_STATUS_BUSY 1 +#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) +#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 +#define CP_FLAG_AUTO_SAVE_PENDING 1 +#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) +#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 +#define CP_FLAG_AUTO_LOAD_PENDING 1 +#define CP_FLAG_UNK54 ((3 * 32) + 6) +#define CP_FLAG_UNK54_CLEAR 0 +#define CP_FLAG_UNK54_SET 1 +#define CP_FLAG_ALWAYS ((3 * 32) + 8) +#define CP_FLAG_ALWAYS_FALSE 0 +#define CP_FLAG_ALWAYS_TRUE 1 +#define CP_FLAG_UNK57 ((3 * 32) + 9) +#define CP_FLAG_UNK57_CLEAR 0 +#define CP_FLAG_UNK57_SET 1 + +#define CP_CTX 0x00100000 +#define CP_CTX_COUNT 0x000fc000 +#define CP_CTX_COUNT_SHIFT 14 +#define CP_CTX_REG 0x00003fff +#define CP_LOAD_SR 0x00200000 +#define CP_LOAD_SR_VALUE 0x000fffff +#define CP_BRA 0x00400000 +#define CP_BRA_IP 0x0000ff00 +#define CP_BRA_IP_SHIFT 8 +#define CP_BRA_IF_CLEAR 0x00000080 +#define CP_BRA_FLAG 0x0000007f +#define CP_WAIT 0x00500000 +#define CP_WAIT_SET 0x00000080 +#define CP_WAIT_FLAG 0x0000007f +#define CP_SET 0x00700000 +#define CP_SET_1 0x00000080 +#define CP_SET_FLAG 0x0000007f +#define CP_NEXT_TO_SWAP 0x00600007 +#define CP_NEXT_TO_CURRENT 0x00600009 +#define CP_SET_CONTEXT_POINTER 0x0060000a +#define CP_END 0x0060000e +#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ +#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ +#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ + +#include "nv40.h" +#include "ctx.h" + +/* TODO: + * - get vs count from 0x1540 + */ + +static int +nv40_gr_vs_count(struct nouveau_device *device) +{ + + switch (device->chipset) { + case 0x47: + case 0x49: + case 0x4b: + return 8; + case 0x40: + return 6; + case 0x41: + case 0x42: + return 5; + case 0x43: + case 0x44: + case 0x46: + case 0x4a: + return 3; + case 0x4c: + case 0x4e: + case 0x67: + default: + return 1; + } +} + + +enum cp_label { + cp_check_load = 1, + cp_setup_auto_load, + cp_setup_load, + cp_setup_save, + cp_swap_state, + cp_swap_state3d_3_is_save, + cp_prepare_exit, + cp_exit, +}; + +static void +nv40_gr_construct_general(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + + cp_ctx(ctx, 0x4000a4, 1); + gr_def(ctx, 0x4000a4, 0x00000008); + cp_ctx(ctx, 0x400144, 58); + gr_def(ctx, 0x400144, 0x00000001); + cp_ctx(ctx, 0x400314, 1); + gr_def(ctx, 0x400314, 0x00000000); + cp_ctx(ctx, 0x400400, 10); + cp_ctx(ctx, 0x400480, 10); + cp_ctx(ctx, 0x400500, 19); + gr_def(ctx, 0x400514, 0x00040000); + gr_def(ctx, 0x400524, 0x55555555); + gr_def(ctx, 0x400528, 0x55555555); + gr_def(ctx, 0x40052c, 0x55555555); + gr_def(ctx, 0x400530, 0x55555555); + cp_ctx(ctx, 0x400560, 6); + gr_def(ctx, 0x400568, 0x0000ffff); + gr_def(ctx, 0x40056c, 0x0000ffff); + cp_ctx(ctx, 0x40057c, 5); + cp_ctx(ctx, 0x400710, 3); + gr_def(ctx, 0x400710, 0x20010001); + gr_def(ctx, 0x400714, 0x0f73ef00); + cp_ctx(ctx, 0x400724, 1); + gr_def(ctx, 0x400724, 0x02008821); + cp_ctx(ctx, 0x400770, 3); + if (device->chipset == 0x40) { + cp_ctx(ctx, 0x400814, 4); + cp_ctx(ctx, 0x400828, 5); + cp_ctx(ctx, 0x400840, 5); + gr_def(ctx, 0x400850, 0x00000040); + cp_ctx(ctx, 0x400858, 4); + gr_def(ctx, 0x400858, 0x00000040); + gr_def(ctx, 0x40085c, 0x00000040); + gr_def(ctx, 0x400864, 0x80000000); + cp_ctx(ctx, 0x40086c, 9); + gr_def(ctx, 0x40086c, 0x80000000); + gr_def(ctx, 0x400870, 0x80000000); + gr_def(ctx, 0x400874, 0x80000000); + gr_def(ctx, 0x400878, 0x80000000); + gr_def(ctx, 0x400888, 0x00000040); + gr_def(ctx, 0x40088c, 0x80000000); + cp_ctx(ctx, 0x4009c0, 8); + gr_def(ctx, 0x4009cc, 0x80000000); + gr_def(ctx, 0x4009dc, 0x80000000); + } else { + cp_ctx(ctx, 0x400840, 20); + if (nv44_gr_class(ctx->device)) { + for (i = 0; i < 8; i++) + gr_def(ctx, 0x400860 + (i * 4), 0x00000001); + } + gr_def(ctx, 0x400880, 0x00000040); + gr_def(ctx, 0x400884, 0x00000040); + gr_def(ctx, 0x400888, 0x00000040); + cp_ctx(ctx, 0x400894, 11); + gr_def(ctx, 0x400894, 0x00000040); + if (!nv44_gr_class(ctx->device)) { + for (i = 0; i < 8; i++) + gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); + } + cp_ctx(ctx, 0x4008e0, 2); + cp_ctx(ctx, 0x4008f8, 2); + if (device->chipset == 0x4c || + (device->chipset & 0xf0) == 0x60) + cp_ctx(ctx, 0x4009f8, 1); + } + cp_ctx(ctx, 0x400a00, 73); + gr_def(ctx, 0x400b0c, 0x0b0b0b0c); + cp_ctx(ctx, 0x401000, 4); + cp_ctx(ctx, 0x405004, 1); + switch (device->chipset) { + case 0x47: + case 0x49: + case 0x4b: + cp_ctx(ctx, 0x403448, 1); + gr_def(ctx, 0x403448, 0x00001010); + break; + default: + cp_ctx(ctx, 0x403440, 1); + switch (device->chipset) { + case 0x40: + gr_def(ctx, 0x403440, 0x00000010); + break; + case 0x44: + case 0x46: + case 0x4a: + gr_def(ctx, 0x403440, 0x00003010); + break; + case 0x41: + case 0x42: + case 0x43: + case 0x4c: + case 0x4e: + case 0x67: + default: + gr_def(ctx, 0x403440, 0x00001010); + break; + } + break; + } +} + +static void +nv40_gr_construct_state3d(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + + if (device->chipset == 0x40) { + cp_ctx(ctx, 0x401880, 51); + gr_def(ctx, 0x401940, 0x00000100); + } else + if (device->chipset == 0x46 || device->chipset == 0x47 || + device->chipset == 0x49 || device->chipset == 0x4b) { + cp_ctx(ctx, 0x401880, 32); + for (i = 0; i < 16; i++) + gr_def(ctx, 0x401880 + (i * 4), 0x00000111); + if (device->chipset == 0x46) + cp_ctx(ctx, 0x401900, 16); + cp_ctx(ctx, 0x401940, 3); + } + cp_ctx(ctx, 0x40194c, 18); + gr_def(ctx, 0x401954, 0x00000111); + gr_def(ctx, 0x401958, 0x00080060); + gr_def(ctx, 0x401974, 0x00000080); + gr_def(ctx, 0x401978, 0xffff0000); + gr_def(ctx, 0x40197c, 0x00000001); + gr_def(ctx, 0x401990, 0x46400000); + if (device->chipset == 0x40) { + cp_ctx(ctx, 0x4019a0, 2); + cp_ctx(ctx, 0x4019ac, 5); + } else { + cp_ctx(ctx, 0x4019a0, 1); + cp_ctx(ctx, 0x4019b4, 3); + } + gr_def(ctx, 0x4019bc, 0xffff0000); + switch (device->chipset) { + case 0x46: + case 0x47: + case 0x49: + case 0x4b: + cp_ctx(ctx, 0x4019c0, 18); + for (i = 0; i < 16; i++) + gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); + break; + } + cp_ctx(ctx, 0x401a08, 8); + gr_def(ctx, 0x401a10, 0x0fff0000); + gr_def(ctx, 0x401a14, 0x0fff0000); + gr_def(ctx, 0x401a1c, 0x00011100); + cp_ctx(ctx, 0x401a2c, 4); + cp_ctx(ctx, 0x401a44, 26); + for (i = 0; i < 16; i++) + gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); + gr_def(ctx, 0x401a8c, 0x4b7fffff); + if (device->chipset == 0x40) { + cp_ctx(ctx, 0x401ab8, 3); + } else { + cp_ctx(ctx, 0x401ab8, 1); + cp_ctx(ctx, 0x401ac0, 1); + } + cp_ctx(ctx, 0x401ad0, 8); + gr_def(ctx, 0x401ad0, 0x30201000); + gr_def(ctx, 0x401ad4, 0x70605040); + gr_def(ctx, 0x401ad8, 0xb8a89888); + gr_def(ctx, 0x401adc, 0xf8e8d8c8); + cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); + gr_def(ctx, 0x401b10, 0x40100000); + cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); + gr_def(ctx, 0x401b28, device->chipset == 0x40 ? + 0x00000004 : 0x00000000); + cp_ctx(ctx, 0x401b30, 25); + gr_def(ctx, 0x401b34, 0x0000ffff); + gr_def(ctx, 0x401b68, 0x435185d6); + gr_def(ctx, 0x401b6c, 0x2155b699); + gr_def(ctx, 0x401b70, 0xfedcba98); + gr_def(ctx, 0x401b74, 0x00000098); + gr_def(ctx, 0x401b84, 0xffffffff); + gr_def(ctx, 0x401b88, 0x00ff7000); + gr_def(ctx, 0x401b8c, 0x0000ffff); + if (device->chipset != 0x44 && device->chipset != 0x4a && + device->chipset != 0x4e) + cp_ctx(ctx, 0x401b94, 1); + cp_ctx(ctx, 0x401b98, 8); + gr_def(ctx, 0x401b9c, 0x00ff0000); + cp_ctx(ctx, 0x401bc0, 9); + gr_def(ctx, 0x401be0, 0x00ffff00); + cp_ctx(ctx, 0x401c00, 192); + for (i = 0; i < 16; i++) { /* fragment texture units */ + gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); + gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); + gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); + gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); + gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); + gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); + } + for (i = 0; i < 4; i++) { /* vertex texture units */ + gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); + gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); + gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); + gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); + } + cp_ctx(ctx, 0x400f5c, 3); + gr_def(ctx, 0x400f5c, 0x00000002); + cp_ctx(ctx, 0x400f84, 1); +} + +static void +nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + + cp_ctx(ctx, 0x402000, 1); + cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); + switch (device->chipset) { + case 0x40: + gr_def(ctx, 0x402404, 0x00000001); + break; + case 0x4c: + case 0x4e: + case 0x67: + gr_def(ctx, 0x402404, 0x00000020); + break; + case 0x46: + case 0x49: + case 0x4b: + gr_def(ctx, 0x402404, 0x00000421); + break; + default: + gr_def(ctx, 0x402404, 0x00000021); + } + if (device->chipset != 0x40) + gr_def(ctx, 0x402408, 0x030c30c3); + switch (device->chipset) { + case 0x44: + case 0x46: + case 0x4a: + case 0x4c: + case 0x4e: + case 0x67: + cp_ctx(ctx, 0x402440, 1); + gr_def(ctx, 0x402440, 0x00011001); + break; + default: + break; + } + cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); + gr_def(ctx, 0x402488, 0x3e020200); + gr_def(ctx, 0x40248c, 0x00ffffff); + switch (device->chipset) { + case 0x40: + gr_def(ctx, 0x402490, 0x60103f00); + break; + case 0x47: + gr_def(ctx, 0x402490, 0x40103f00); + break; + case 0x41: + case 0x42: + case 0x49: + case 0x4b: + gr_def(ctx, 0x402490, 0x20103f00); + break; + default: + gr_def(ctx, 0x402490, 0x0c103f00); + break; + } + gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? + 0x00020000 : 0x00040000); + cp_ctx(ctx, 0x402500, 31); + gr_def(ctx, 0x402530, 0x00008100); + if (device->chipset == 0x40) + cp_ctx(ctx, 0x40257c, 6); + cp_ctx(ctx, 0x402594, 16); + cp_ctx(ctx, 0x402800, 17); + gr_def(ctx, 0x402800, 0x00000001); + switch (device->chipset) { + case 0x47: + case 0x49: + case 0x4b: + cp_ctx(ctx, 0x402864, 1); + gr_def(ctx, 0x402864, 0x00001001); + cp_ctx(ctx, 0x402870, 3); + gr_def(ctx, 0x402878, 0x00000003); + if (device->chipset != 0x47) { /* belong at end!! */ + cp_ctx(ctx, 0x402900, 1); + cp_ctx(ctx, 0x402940, 1); + cp_ctx(ctx, 0x402980, 1); + cp_ctx(ctx, 0x4029c0, 1); + cp_ctx(ctx, 0x402a00, 1); + cp_ctx(ctx, 0x402a40, 1); + cp_ctx(ctx, 0x402a80, 1); + cp_ctx(ctx, 0x402ac0, 1); + } + break; + case 0x40: + cp_ctx(ctx, 0x402844, 1); + gr_def(ctx, 0x402844, 0x00000001); + cp_ctx(ctx, 0x402850, 1); + break; + default: + cp_ctx(ctx, 0x402844, 1); + gr_def(ctx, 0x402844, 0x00001001); + cp_ctx(ctx, 0x402850, 2); + gr_def(ctx, 0x402854, 0x00000003); + break; + } + + cp_ctx(ctx, 0x402c00, 4); + gr_def(ctx, 0x402c00, device->chipset == 0x40 ? + 0x80800001 : 0x00888001); + switch (device->chipset) { + case 0x47: + case 0x49: + case 0x4b: + cp_ctx(ctx, 0x402c20, 40); + for (i = 0; i < 32; i++) + gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); + cp_ctx(ctx, 0x4030b8, 13); + gr_def(ctx, 0x4030dc, 0x00000005); + gr_def(ctx, 0x4030e8, 0x0000ffff); + break; + default: + cp_ctx(ctx, 0x402c10, 4); + if (device->chipset == 0x40) + cp_ctx(ctx, 0x402c20, 36); + else + if (device->chipset <= 0x42) + cp_ctx(ctx, 0x402c20, 24); + else + if (device->chipset <= 0x4a) + cp_ctx(ctx, 0x402c20, 16); + else + cp_ctx(ctx, 0x402c20, 8); + cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); + gr_def(ctx, 0x402cd4, 0x00000005); + if (device->chipset != 0x40) + gr_def(ctx, 0x402ce0, 0x0000ffff); + break; + } + + cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); + cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); + cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); + for (i = 0; i < nv40_gr_vs_count(ctx->device); i++) + gr_def(ctx, 0x403420 + (i * 4), 0x00005555); + + if (device->chipset != 0x40) { + cp_ctx(ctx, 0x403600, 1); + gr_def(ctx, 0x403600, 0x00000001); + } + cp_ctx(ctx, 0x403800, 1); + + cp_ctx(ctx, 0x403c18, 1); + gr_def(ctx, 0x403c18, 0x00000001); + switch (device->chipset) { + case 0x46: + case 0x47: + case 0x49: + case 0x4b: + cp_ctx(ctx, 0x405018, 1); + gr_def(ctx, 0x405018, 0x08e00001); + cp_ctx(ctx, 0x405c24, 1); + gr_def(ctx, 0x405c24, 0x000e3000); + break; + } + if (device->chipset != 0x4e) + cp_ctx(ctx, 0x405800, 11); + cp_ctx(ctx, 0x407000, 1); +} + +static void +nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx) +{ + int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684; + + cp_out (ctx, 0x300000); + cp_lsr (ctx, len - 4); + cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); + cp_lsr (ctx, len); + cp_name(ctx, cp_swap_state3d_3_is_save); + cp_out (ctx, 0x800001); + + ctx->ctxvals_pos += len; +} + +static void +nv40_gr_construct_shader(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + struct nouveau_gpuobj *obj = ctx->data; + int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; + int offset, i; + + vs_nr = nv40_gr_vs_count(ctx->device); + vs_nr_b0 = 363; + vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; + if (device->chipset == 0x40) { + b0_offset = 0x2200/4; /* 33a0 */ + b1_offset = 0x55a0/4; /* 1500 */ + vs_len = 0x6aa0/4; + } else + if (device->chipset == 0x41 || device->chipset == 0x42) { + b0_offset = 0x2200/4; /* 2200 */ + b1_offset = 0x4400/4; /* 0b00 */ + vs_len = 0x4f00/4; + } else { + b0_offset = 0x1d40/4; /* 2200 */ + b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ + vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4; + } + + cp_lsr(ctx, vs_len * vs_nr + 0x300/4); + cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041); + + offset = ctx->ctxvals_pos; + ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); + + if (ctx->mode != NOUVEAU_GRCTX_VALS) + return; + + offset += 0x0280/4; + for (i = 0; i < 16; i++, offset += 2) + nv_wo32(obj, offset * 4, 0x3f800000); + + for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { + for (i = 0; i < vs_nr_b0 * 6; i += 6) + nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); + for (i = 0; i < vs_nr_b1 * 4; i += 4) + nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); + } +} + +static void +nv40_grctx_generate(struct nouveau_grctx *ctx) +{ + /* decide whether we're loading/unloading the context */ + cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); + cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); + + cp_name(ctx, cp_check_load); + cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); + cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); + cp_bra (ctx, ALWAYS, TRUE, cp_exit); + + /* setup for context load */ + cp_name(ctx, cp_setup_auto_load); + cp_wait(ctx, STATUS, IDLE); + cp_out (ctx, CP_NEXT_TO_SWAP); + cp_name(ctx, cp_setup_load); + cp_wait(ctx, STATUS, IDLE); + cp_set (ctx, SWAP_DIRECTION, LOAD); + cp_out (ctx, 0x00910880); /* ?? */ + cp_out (ctx, 0x00901ffe); /* ?? */ + cp_out (ctx, 0x01940000); /* ?? */ + cp_lsr (ctx, 0x20); + cp_out (ctx, 0x0060000b); /* ?? */ + cp_wait(ctx, UNK57, CLEAR); + cp_out (ctx, 0x0060000c); /* ?? */ + cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); + + /* setup for context save */ + cp_name(ctx, cp_setup_save); + cp_set (ctx, SWAP_DIRECTION, SAVE); + + /* general PGRAPH state */ + cp_name(ctx, cp_swap_state); + cp_pos (ctx, 0x00020/4); + nv40_gr_construct_general(ctx); + cp_wait(ctx, STATUS, IDLE); + + /* 3D state, block 1 */ + cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); + nv40_gr_construct_state3d(ctx); + cp_wait(ctx, STATUS, IDLE); + + /* 3D state, block 2 */ + nv40_gr_construct_state3d_2(ctx); + + /* Some other block of "random" state */ + nv40_gr_construct_state3d_3(ctx); + + /* Per-vertex shader state */ + cp_pos (ctx, ctx->ctxvals_pos); + nv40_gr_construct_shader(ctx); + + /* pre-exit state updates */ + cp_name(ctx, cp_prepare_exit); + cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); + cp_bra (ctx, USER_SAVE, PENDING, cp_exit); + cp_out (ctx, CP_NEXT_TO_CURRENT); + + cp_name(ctx, cp_exit); + cp_set (ctx, USER_SAVE, NOT_PENDING); + cp_set (ctx, USER_LOAD, NOT_PENDING); + cp_out (ctx, CP_END); +} + +void +nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) +{ + nv40_grctx_generate(&(struct nouveau_grctx) { + .device = device, + .mode = NOUVEAU_GRCTX_VALS, + .data = mem, + }); +} + +int +nv40_grctx_init(struct nouveau_device *device, u32 *size) +{ + u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; + struct nouveau_grctx ctx = { + .device = device, + .mode = NOUVEAU_GRCTX_PROG, + .data = ctxprog, + .ctxprog_max = 256, + }; + + if (!ctxprog) + return -ENOMEM; + + nv40_grctx_generate(&ctx); + + nv_wr32(device, 0x400324, 0); + for (i = 0; i < ctx.ctxprog_len; i++) + nv_wr32(device, 0x400328, ctxprog[i]); + *size = ctx.ctxvals_pos * 4; + + kfree(ctxprog); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c new file mode 100644 index 000000000000..8b7d879a7fa1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -0,0 +1,3347 @@ +/* + * Copyright 2009 Marcin Kościelnicki + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#define CP_FLAG_CLEAR 0 +#define CP_FLAG_SET 1 +#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) +#define CP_FLAG_SWAP_DIRECTION_LOAD 0 +#define CP_FLAG_SWAP_DIRECTION_SAVE 1 +#define CP_FLAG_UNK01 ((0 * 32) + 1) +#define CP_FLAG_UNK01_CLEAR 0 +#define CP_FLAG_UNK01_SET 1 +#define CP_FLAG_UNK03 ((0 * 32) + 3) +#define CP_FLAG_UNK03_CLEAR 0 +#define CP_FLAG_UNK03_SET 1 +#define CP_FLAG_USER_SAVE ((0 * 32) + 5) +#define CP_FLAG_USER_SAVE_NOT_PENDING 0 +#define CP_FLAG_USER_SAVE_PENDING 1 +#define CP_FLAG_USER_LOAD ((0 * 32) + 6) +#define CP_FLAG_USER_LOAD_NOT_PENDING 0 +#define CP_FLAG_USER_LOAD_PENDING 1 +#define CP_FLAG_UNK0B ((0 * 32) + 0xb) +#define CP_FLAG_UNK0B_CLEAR 0 +#define CP_FLAG_UNK0B_SET 1 +#define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe) +#define CP_FLAG_XFER_SWITCH_DISABLE 0 +#define CP_FLAG_XFER_SWITCH_ENABLE 1 +#define CP_FLAG_STATE ((0 * 32) + 0x1c) +#define CP_FLAG_STATE_STOPPED 0 +#define CP_FLAG_STATE_RUNNING 1 +#define CP_FLAG_UNK1D ((0 * 32) + 0x1d) +#define CP_FLAG_UNK1D_CLEAR 0 +#define CP_FLAG_UNK1D_SET 1 +#define CP_FLAG_UNK20 ((1 * 32) + 0) +#define CP_FLAG_UNK20_CLEAR 0 +#define CP_FLAG_UNK20_SET 1 +#define CP_FLAG_STATUS ((2 * 32) + 0) +#define CP_FLAG_STATUS_BUSY 0 +#define CP_FLAG_STATUS_IDLE 1 +#define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) +#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 +#define CP_FLAG_AUTO_SAVE_PENDING 1 +#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) +#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 +#define CP_FLAG_AUTO_LOAD_PENDING 1 +#define CP_FLAG_NEWCTX ((2 * 32) + 10) +#define CP_FLAG_NEWCTX_BUSY 0 +#define CP_FLAG_NEWCTX_DONE 1 +#define CP_FLAG_XFER ((2 * 32) + 11) +#define CP_FLAG_XFER_IDLE 0 +#define CP_FLAG_XFER_BUSY 1 +#define CP_FLAG_ALWAYS ((2 * 32) + 13) +#define CP_FLAG_ALWAYS_FALSE 0 +#define CP_FLAG_ALWAYS_TRUE 1 +#define CP_FLAG_INTR ((2 * 32) + 15) +#define CP_FLAG_INTR_NOT_PENDING 0 +#define CP_FLAG_INTR_PENDING 1 + +#define CP_CTX 0x00100000 +#define CP_CTX_COUNT 0x000f0000 +#define CP_CTX_COUNT_SHIFT 16 +#define CP_CTX_REG 0x00003fff +#define CP_LOAD_SR 0x00200000 +#define CP_LOAD_SR_VALUE 0x000fffff +#define CP_BRA 0x00400000 +#define CP_BRA_IP 0x0001ff00 +#define CP_BRA_IP_SHIFT 8 +#define CP_BRA_IF_CLEAR 0x00000080 +#define CP_BRA_FLAG 0x0000007f +#define CP_WAIT 0x00500000 +#define CP_WAIT_SET 0x00000080 +#define CP_WAIT_FLAG 0x0000007f +#define CP_SET 0x00700000 +#define CP_SET_1 0x00000080 +#define CP_SET_FLAG 0x0000007f +#define CP_NEWCTX 0x00600004 +#define CP_NEXT_TO_SWAP 0x00600005 +#define CP_SET_CONTEXT_POINTER 0x00600006 +#define CP_SET_XFER_POINTER 0x00600007 +#define CP_ENABLE 0x00600009 +#define CP_END 0x0060000c +#define CP_NEXT_TO_CURRENT 0x0060000d +#define CP_DISABLE1 0x0090ffff +#define CP_DISABLE2 0x0091ffff +#define CP_XFER_1 0x008000ff +#define CP_XFER_2 0x008800ff +#define CP_SEEK_1 0x00c000ff +#define CP_SEEK_2 0x00c800ff + +#include "nv50.h" +#include "ctx.h" + +#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) +#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) + +#include + +/* + * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's + * the GPU itself that does context-switching, but it needs a special + * microcode to do it. And it's the driver's task to supply this microcode, + * further known as ctxprog, as well as the initial context values, known + * as ctxvals. + * + * Without ctxprog, you cannot switch contexts. Not even in software, since + * the majority of context [xfer strands] isn't accessible directly. You're + * stuck with a single channel, and you also suffer all the problems resulting + * from missing ctxvals, since you cannot load them. + * + * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to + * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, + * since you don't have... some sort of needed setup. + * + * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since + * it's too much hassle to handle no-ctxprog as a special case. + */ + +/* + * How ctxprogs work. + * + * The ctxprog is written in its own kind of microcode, with very small and + * crappy set of available commands. You upload it to a small [512 insns] + * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to + * switch channel. or when the driver explicitely requests it. Stuff visible + * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, + * the per-channel context save area in VRAM [known as ctxvals or grctx], + * 4 flags registers, a scratch register, two grctx pointers, plus many + * random poorly-understood details. + * + * When ctxprog runs, it's supposed to check what operations are asked of it, + * save old context if requested, optionally reset PGRAPH and switch to the + * new channel, and load the new context. Context consists of three major + * parts: subset of MMIO registers and two "xfer areas". + */ + +/* TODO: + * - document unimplemented bits compared to nvidia + * - NVAx: make a TP subroutine, use it. + * - use 0x4008fc instead of 0x1540? + */ + +enum cp_label { + cp_check_load = 1, + cp_setup_auto_load, + cp_setup_load, + cp_setup_save, + cp_swap_state, + cp_prepare_exit, + cp_exit, +}; + +static void nv50_gr_construct_mmio(struct nouveau_grctx *ctx); +static void nv50_gr_construct_xfer1(struct nouveau_grctx *ctx); +static void nv50_gr_construct_xfer2(struct nouveau_grctx *ctx); + +/* Main function: construct the ctxprog skeleton, call the other functions. */ + +static int +nv50_grctx_generate(struct nouveau_grctx *ctx) +{ + cp_set (ctx, STATE, RUNNING); + cp_set (ctx, XFER_SWITCH, ENABLE); + /* decide whether we're loading/unloading the context */ + cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); + cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); + + cp_name(ctx, cp_check_load); + cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); + cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); + cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit); + + /* setup for context load */ + cp_name(ctx, cp_setup_auto_load); + cp_out (ctx, CP_DISABLE1); + cp_out (ctx, CP_DISABLE2); + cp_out (ctx, CP_ENABLE); + cp_out (ctx, CP_NEXT_TO_SWAP); + cp_set (ctx, UNK01, SET); + cp_name(ctx, cp_setup_load); + cp_out (ctx, CP_NEWCTX); + cp_wait(ctx, NEWCTX, BUSY); + cp_set (ctx, UNK1D, CLEAR); + cp_set (ctx, SWAP_DIRECTION, LOAD); + cp_bra (ctx, UNK0B, SET, cp_prepare_exit); + cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); + + /* setup for context save */ + cp_name(ctx, cp_setup_save); + cp_set (ctx, UNK1D, SET); + cp_wait(ctx, STATUS, BUSY); + cp_wait(ctx, INTR, PENDING); + cp_bra (ctx, STATUS, BUSY, cp_setup_save); + cp_set (ctx, UNK01, SET); + cp_set (ctx, SWAP_DIRECTION, SAVE); + + /* general PGRAPH state */ + cp_name(ctx, cp_swap_state); + cp_set (ctx, UNK03, SET); + cp_pos (ctx, 0x00004/4); + cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ + cp_pos (ctx, 0x00100/4); + nv50_gr_construct_mmio(ctx); + nv50_gr_construct_xfer1(ctx); + nv50_gr_construct_xfer2(ctx); + + cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); + + cp_set (ctx, UNK20, SET); + cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ + cp_lsr (ctx, ctx->ctxvals_base); + cp_out (ctx, CP_SET_XFER_POINTER); + cp_lsr (ctx, 4); + cp_out (ctx, CP_SEEK_1); + cp_out (ctx, CP_XFER_1); + cp_wait(ctx, XFER, BUSY); + + /* pre-exit state updates */ + cp_name(ctx, cp_prepare_exit); + cp_set (ctx, UNK01, CLEAR); + cp_set (ctx, UNK03, CLEAR); + cp_set (ctx, UNK1D, CLEAR); + + cp_bra (ctx, USER_SAVE, PENDING, cp_exit); + cp_out (ctx, CP_NEXT_TO_CURRENT); + + cp_name(ctx, cp_exit); + cp_set (ctx, USER_SAVE, NOT_PENDING); + cp_set (ctx, USER_LOAD, NOT_PENDING); + cp_set (ctx, XFER_SWITCH, DISABLE); + cp_set (ctx, STATE, STOPPED); + cp_out (ctx, CP_END); + ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ + + return 0; +} + +void +nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) +{ + nv50_grctx_generate(&(struct nouveau_grctx) { + .device = device, + .mode = NOUVEAU_GRCTX_VALS, + .data = mem, + }); +} + +int +nv50_grctx_init(struct nouveau_device *device, u32 *size) +{ + u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; + struct nouveau_grctx ctx = { + .device = device, + .mode = NOUVEAU_GRCTX_PROG, + .data = ctxprog, + .ctxprog_max = 512, + }; + + if (!ctxprog) + return -ENOMEM; + nv50_grctx_generate(&ctx); + + nv_wr32(device, 0x400324, 0); + for (i = 0; i < ctx.ctxprog_len; i++) + nv_wr32(device, 0x400328, ctxprog[i]); + *size = ctx.ctxvals_pos * 4; + kfree(ctxprog); + return 0; +} + +/* + * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which + * registers to save/restore and the default values for them. + */ + +static void +nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx); + +static void +nv50_gr_construct_mmio(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i, j; + int offset, base; + u32 units = nv_rd32 (ctx->device, 0x1540); + + /* 0800: DISPATCH */ + cp_ctx(ctx, 0x400808, 7); + gr_def(ctx, 0x400814, 0x00000030); + cp_ctx(ctx, 0x400834, 0x32); + if (device->chipset == 0x50) { + gr_def(ctx, 0x400834, 0xff400040); + gr_def(ctx, 0x400838, 0xfff00080); + gr_def(ctx, 0x40083c, 0xfff70090); + gr_def(ctx, 0x400840, 0xffe806a8); + } + gr_def(ctx, 0x400844, 0x00000002); + if (IS_NVA3F(device->chipset)) + gr_def(ctx, 0x400894, 0x00001000); + gr_def(ctx, 0x4008e8, 0x00000003); + gr_def(ctx, 0x4008ec, 0x00001000); + if (device->chipset == 0x50) + cp_ctx(ctx, 0x400908, 0xb); + else if (device->chipset < 0xa0) + cp_ctx(ctx, 0x400908, 0xc); + else + cp_ctx(ctx, 0x400908, 0xe); + + if (device->chipset >= 0xa0) + cp_ctx(ctx, 0x400b00, 0x1); + if (IS_NVA3F(device->chipset)) { + cp_ctx(ctx, 0x400b10, 0x1); + gr_def(ctx, 0x400b10, 0x0001629d); + cp_ctx(ctx, 0x400b20, 0x1); + gr_def(ctx, 0x400b20, 0x0001629d); + } + + nv50_gr_construct_mmio_ddata(ctx); + + /* 0C00: VFETCH */ + cp_ctx(ctx, 0x400c08, 0x2); + gr_def(ctx, 0x400c08, 0x0000fe0c); + + /* 1000 */ + if (device->chipset < 0xa0) { + cp_ctx(ctx, 0x401008, 0x4); + gr_def(ctx, 0x401014, 0x00001000); + } else if (!IS_NVA3F(device->chipset)) { + cp_ctx(ctx, 0x401008, 0x5); + gr_def(ctx, 0x401018, 0x00001000); + } else { + cp_ctx(ctx, 0x401008, 0x5); + gr_def(ctx, 0x401018, 0x00004000); + } + + /* 1400 */ + cp_ctx(ctx, 0x401400, 0x8); + cp_ctx(ctx, 0x401424, 0x3); + if (device->chipset == 0x50) + gr_def(ctx, 0x40142c, 0x0001fd87); + else + gr_def(ctx, 0x40142c, 0x00000187); + cp_ctx(ctx, 0x401540, 0x5); + gr_def(ctx, 0x401550, 0x00001018); + + /* 1800: STREAMOUT */ + cp_ctx(ctx, 0x401814, 0x1); + gr_def(ctx, 0x401814, 0x000000ff); + if (device->chipset == 0x50) { + cp_ctx(ctx, 0x40181c, 0xe); + gr_def(ctx, 0x401850, 0x00000004); + } else if (device->chipset < 0xa0) { + cp_ctx(ctx, 0x40181c, 0xf); + gr_def(ctx, 0x401854, 0x00000004); + } else { + cp_ctx(ctx, 0x40181c, 0x13); + gr_def(ctx, 0x401864, 0x00000004); + } + + /* 1C00 */ + cp_ctx(ctx, 0x401c00, 0x1); + switch (device->chipset) { + case 0x50: + gr_def(ctx, 0x401c00, 0x0001005f); + break; + case 0x84: + case 0x86: + case 0x94: + gr_def(ctx, 0x401c00, 0x044d00df); + break; + case 0x92: + case 0x96: + case 0x98: + case 0xa0: + case 0xaa: + case 0xac: + gr_def(ctx, 0x401c00, 0x042500df); + break; + case 0xa3: + case 0xa5: + case 0xa8: + case 0xaf: + gr_def(ctx, 0x401c00, 0x142500df); + break; + } + + /* 2000 */ + + /* 2400 */ + cp_ctx(ctx, 0x402400, 0x1); + if (device->chipset == 0x50) + cp_ctx(ctx, 0x402408, 0x1); + else + cp_ctx(ctx, 0x402408, 0x2); + gr_def(ctx, 0x402408, 0x00000600); + + /* 2800: CSCHED */ + cp_ctx(ctx, 0x402800, 0x1); + if (device->chipset == 0x50) + gr_def(ctx, 0x402800, 0x00000006); + + /* 2C00: ZCULL */ + cp_ctx(ctx, 0x402c08, 0x6); + if (device->chipset != 0x50) + gr_def(ctx, 0x402c14, 0x01000000); + gr_def(ctx, 0x402c18, 0x000000ff); + if (device->chipset == 0x50) + cp_ctx(ctx, 0x402ca0, 0x1); + else + cp_ctx(ctx, 0x402ca0, 0x2); + if (device->chipset < 0xa0) + gr_def(ctx, 0x402ca0, 0x00000400); + else if (!IS_NVA3F(device->chipset)) + gr_def(ctx, 0x402ca0, 0x00000800); + else + gr_def(ctx, 0x402ca0, 0x00000400); + cp_ctx(ctx, 0x402cac, 0x4); + + /* 3000: ENG2D */ + cp_ctx(ctx, 0x403004, 0x1); + gr_def(ctx, 0x403004, 0x00000001); + + /* 3400 */ + if (device->chipset >= 0xa0) { + cp_ctx(ctx, 0x403404, 0x1); + gr_def(ctx, 0x403404, 0x00000001); + } + + /* 5000: CCACHE */ + cp_ctx(ctx, 0x405000, 0x1); + switch (device->chipset) { + case 0x50: + gr_def(ctx, 0x405000, 0x00300080); + break; + case 0x84: + case 0xa0: + case 0xa3: + case 0xa5: + case 0xa8: + case 0xaa: + case 0xac: + case 0xaf: + gr_def(ctx, 0x405000, 0x000e0080); + break; + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0x98: + gr_def(ctx, 0x405000, 0x00000080); + break; + } + cp_ctx(ctx, 0x405014, 0x1); + gr_def(ctx, 0x405014, 0x00000004); + cp_ctx(ctx, 0x40501c, 0x1); + cp_ctx(ctx, 0x405024, 0x1); + cp_ctx(ctx, 0x40502c, 0x1); + + /* 6000? */ + if (device->chipset == 0x50) + cp_ctx(ctx, 0x4063e0, 0x1); + + /* 6800: M2MF */ + if (device->chipset < 0x90) { + cp_ctx(ctx, 0x406814, 0x2b); + gr_def(ctx, 0x406818, 0x00000f80); + gr_def(ctx, 0x406860, 0x007f0080); + gr_def(ctx, 0x40689c, 0x007f0080); + } else { + cp_ctx(ctx, 0x406814, 0x4); + if (device->chipset == 0x98) + gr_def(ctx, 0x406818, 0x00000f80); + else + gr_def(ctx, 0x406818, 0x00001f80); + if (IS_NVA3F(device->chipset)) + gr_def(ctx, 0x40681c, 0x00000030); + cp_ctx(ctx, 0x406830, 0x3); + } + + /* 7000: per-ROP group state */ + for (i = 0; i < 8; i++) { + if (units & (1<<(i+16))) { + cp_ctx(ctx, 0x407000 + (i<<8), 3); + if (device->chipset == 0x50) + gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); + else if (device->chipset != 0xa5) + gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); + else + gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); + gr_def(ctx, 0x407004 + (i<<8), 0x89058001); + + if (device->chipset == 0x50) { + cp_ctx(ctx, 0x407010 + (i<<8), 1); + } else if (device->chipset < 0xa0) { + cp_ctx(ctx, 0x407010 + (i<<8), 2); + gr_def(ctx, 0x407010 + (i<<8), 0x00001000); + gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); + } else { + cp_ctx(ctx, 0x407010 + (i<<8), 3); + gr_def(ctx, 0x407010 + (i<<8), 0x00001000); + if (device->chipset != 0xa5) + gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); + else + gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); + } + + cp_ctx(ctx, 0x407080 + (i<<8), 4); + if (device->chipset != 0xa5) + gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); + else + gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); + if (device->chipset == 0x50) + gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); + else + gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); + gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); + + if (device->chipset < 0xa0) + cp_ctx(ctx, 0x407094 + (i<<8), 1); + else if (!IS_NVA3F(device->chipset)) + cp_ctx(ctx, 0x407094 + (i<<8), 3); + else { + cp_ctx(ctx, 0x407094 + (i<<8), 4); + gr_def(ctx, 0x4070a0 + (i<<8), 1); + } + } + } + + cp_ctx(ctx, 0x407c00, 0x3); + if (device->chipset < 0x90) + gr_def(ctx, 0x407c00, 0x00010040); + else if (device->chipset < 0xa0) + gr_def(ctx, 0x407c00, 0x00390040); + else + gr_def(ctx, 0x407c00, 0x003d0040); + gr_def(ctx, 0x407c08, 0x00000022); + if (device->chipset >= 0xa0) { + cp_ctx(ctx, 0x407c10, 0x3); + cp_ctx(ctx, 0x407c20, 0x1); + cp_ctx(ctx, 0x407c2c, 0x1); + } + + if (device->chipset < 0xa0) { + cp_ctx(ctx, 0x407d00, 0x9); + } else { + cp_ctx(ctx, 0x407d00, 0x15); + } + if (device->chipset == 0x98) + gr_def(ctx, 0x407d08, 0x00380040); + else { + if (device->chipset < 0x90) + gr_def(ctx, 0x407d08, 0x00010040); + else if (device->chipset < 0xa0) + gr_def(ctx, 0x407d08, 0x00390040); + else { + if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) + gr_def(ctx, 0x407d08, 0x003d0040); + else + gr_def(ctx, 0x407d08, 0x003c0040); + } + gr_def(ctx, 0x407d0c, 0x00000022); + } + + /* 8000+: per-TP state */ + for (i = 0; i < 10; i++) { + if (units & (1<chipset < 0xa0) + base = 0x408000 + (i<<12); + else + base = 0x408000 + (i<<11); + if (device->chipset < 0xa0) + offset = base + 0xc00; + else + offset = base + 0x80; + cp_ctx(ctx, offset + 0x00, 1); + gr_def(ctx, offset + 0x00, 0x0000ff0a); + cp_ctx(ctx, offset + 0x08, 1); + + /* per-MP state */ + for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) { + if (!(units & (1 << (j+24)))) continue; + if (device->chipset < 0xa0) + offset = base + 0x200 + (j<<7); + else + offset = base + 0x100 + (j<<7); + cp_ctx(ctx, offset, 0x20); + gr_def(ctx, offset + 0x00, 0x01800000); + gr_def(ctx, offset + 0x04, 0x00160000); + gr_def(ctx, offset + 0x08, 0x01800000); + gr_def(ctx, offset + 0x18, 0x0003ffff); + switch (device->chipset) { + case 0x50: + gr_def(ctx, offset + 0x1c, 0x00080000); + break; + case 0x84: + gr_def(ctx, offset + 0x1c, 0x00880000); + break; + case 0x86: + gr_def(ctx, offset + 0x1c, 0x018c0000); + break; + case 0x92: + case 0x96: + case 0x98: + gr_def(ctx, offset + 0x1c, 0x118c0000); + break; + case 0x94: + gr_def(ctx, offset + 0x1c, 0x10880000); + break; + case 0xa0: + case 0xa5: + gr_def(ctx, offset + 0x1c, 0x310c0000); + break; + case 0xa3: + case 0xa8: + case 0xaa: + case 0xac: + case 0xaf: + gr_def(ctx, offset + 0x1c, 0x300c0000); + break; + } + gr_def(ctx, offset + 0x40, 0x00010401); + if (device->chipset == 0x50) + gr_def(ctx, offset + 0x48, 0x00000040); + else + gr_def(ctx, offset + 0x48, 0x00000078); + gr_def(ctx, offset + 0x50, 0x000000bf); + gr_def(ctx, offset + 0x58, 0x00001210); + if (device->chipset == 0x50) + gr_def(ctx, offset + 0x5c, 0x00000080); + else + gr_def(ctx, offset + 0x5c, 0x08000080); + if (device->chipset >= 0xa0) + gr_def(ctx, offset + 0x68, 0x0000003e); + } + + if (device->chipset < 0xa0) + cp_ctx(ctx, base + 0x300, 0x4); + else + cp_ctx(ctx, base + 0x300, 0x5); + if (device->chipset == 0x50) + gr_def(ctx, base + 0x304, 0x00007070); + else if (device->chipset < 0xa0) + gr_def(ctx, base + 0x304, 0x00027070); + else if (!IS_NVA3F(device->chipset)) + gr_def(ctx, base + 0x304, 0x01127070); + else + gr_def(ctx, base + 0x304, 0x05127070); + + if (device->chipset < 0xa0) + cp_ctx(ctx, base + 0x318, 1); + else + cp_ctx(ctx, base + 0x320, 1); + if (device->chipset == 0x50) + gr_def(ctx, base + 0x318, 0x0003ffff); + else if (device->chipset < 0xa0) + gr_def(ctx, base + 0x318, 0x03ffffff); + else + gr_def(ctx, base + 0x320, 0x07ffffff); + + if (device->chipset < 0xa0) + cp_ctx(ctx, base + 0x324, 5); + else + cp_ctx(ctx, base + 0x328, 4); + + if (device->chipset < 0xa0) { + cp_ctx(ctx, base + 0x340, 9); + offset = base + 0x340; + } else if (!IS_NVA3F(device->chipset)) { + cp_ctx(ctx, base + 0x33c, 0xb); + offset = base + 0x344; + } else { + cp_ctx(ctx, base + 0x33c, 0xd); + offset = base + 0x344; + } + gr_def(ctx, offset + 0x0, 0x00120407); + gr_def(ctx, offset + 0x4, 0x05091507); + if (device->chipset == 0x84) + gr_def(ctx, offset + 0x8, 0x05100202); + else + gr_def(ctx, offset + 0x8, 0x05010202); + gr_def(ctx, offset + 0xc, 0x00030201); + if (device->chipset == 0xa3) + cp_ctx(ctx, base + 0x36c, 1); + + cp_ctx(ctx, base + 0x400, 2); + gr_def(ctx, base + 0x404, 0x00000040); + cp_ctx(ctx, base + 0x40c, 2); + gr_def(ctx, base + 0x40c, 0x0d0c0b0a); + gr_def(ctx, base + 0x410, 0x00141210); + + if (device->chipset < 0xa0) + offset = base + 0x800; + else + offset = base + 0x500; + cp_ctx(ctx, offset, 6); + gr_def(ctx, offset + 0x0, 0x000001f0); + gr_def(ctx, offset + 0x4, 0x00000001); + gr_def(ctx, offset + 0x8, 0x00000003); + if (device->chipset == 0x50 || IS_NVAAF(device->chipset)) + gr_def(ctx, offset + 0xc, 0x00008000); + gr_def(ctx, offset + 0x14, 0x00039e00); + cp_ctx(ctx, offset + 0x1c, 2); + if (device->chipset == 0x50) + gr_def(ctx, offset + 0x1c, 0x00000040); + else + gr_def(ctx, offset + 0x1c, 0x00000100); + gr_def(ctx, offset + 0x20, 0x00003800); + + if (device->chipset >= 0xa0) { + cp_ctx(ctx, base + 0x54c, 2); + if (!IS_NVA3F(device->chipset)) + gr_def(ctx, base + 0x54c, 0x003fe006); + else + gr_def(ctx, base + 0x54c, 0x003fe007); + gr_def(ctx, base + 0x550, 0x003fe000); + } + + if (device->chipset < 0xa0) + offset = base + 0xa00; + else + offset = base + 0x680; + cp_ctx(ctx, offset, 1); + gr_def(ctx, offset, 0x00404040); + + if (device->chipset < 0xa0) + offset = base + 0xe00; + else + offset = base + 0x700; + cp_ctx(ctx, offset, 2); + if (device->chipset < 0xa0) + gr_def(ctx, offset, 0x0077f005); + else if (device->chipset == 0xa5) + gr_def(ctx, offset, 0x6cf7f007); + else if (device->chipset == 0xa8) + gr_def(ctx, offset, 0x6cfff007); + else if (device->chipset == 0xac) + gr_def(ctx, offset, 0x0cfff007); + else + gr_def(ctx, offset, 0x0cf7f007); + if (device->chipset == 0x50) + gr_def(ctx, offset + 0x4, 0x00007fff); + else if (device->chipset < 0xa0) + gr_def(ctx, offset + 0x4, 0x003f7fff); + else + gr_def(ctx, offset + 0x4, 0x02bf7fff); + cp_ctx(ctx, offset + 0x2c, 1); + if (device->chipset == 0x50) { + cp_ctx(ctx, offset + 0x50, 9); + gr_def(ctx, offset + 0x54, 0x000003ff); + gr_def(ctx, offset + 0x58, 0x00000003); + gr_def(ctx, offset + 0x5c, 0x00000003); + gr_def(ctx, offset + 0x60, 0x000001ff); + gr_def(ctx, offset + 0x64, 0x0000001f); + gr_def(ctx, offset + 0x68, 0x0000000f); + gr_def(ctx, offset + 0x6c, 0x0000000f); + } else if (device->chipset < 0xa0) { + cp_ctx(ctx, offset + 0x50, 1); + cp_ctx(ctx, offset + 0x70, 1); + } else { + cp_ctx(ctx, offset + 0x50, 1); + cp_ctx(ctx, offset + 0x60, 5); + } + } + } +} + +static void +dd_emit(struct nouveau_grctx *ctx, int num, u32 val) { + int i; + if (val && ctx->mode == NOUVEAU_GRCTX_VALS) + for (i = 0; i < num; i++) + nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); + ctx->ctxvals_pos += num; +} + +static void +nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int base, num; + base = ctx->ctxvals_pos; + + /* tesla state */ + dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */ + dd_emit(ctx, 1, 0); /* 00000001 UNK135C */ + + /* SRC_TIC state */ + dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */ + dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */ + dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */ + dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */ + dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */ + if (device->chipset >= 0x94) + dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */ + dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */ + dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */ + + /* turing state */ + dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */ + dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */ + dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ + dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ + dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ + dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ + dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */ + dd_emit(ctx, 1, 1); /* 00000001 LANES32 */ + dd_emit(ctx, 1, 0); /* 000000ff UNK370 */ + dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */ + dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */ + dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */ + dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ + dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ + dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ + dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */ + dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */ + dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */ + dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */ + dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */ + dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */ + dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */ + dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */ + if (IS_NVA3F(device->chipset)) + dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */ + dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */ + dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */ + dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */ + dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */ + dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */ + dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */ + dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */ + dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */ + + /* compat 2d state */ + if (device->chipset == 0x50) { + dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */ + + dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */ + + dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */ + dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */ + + dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */ + dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */ + dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */ + dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */ + dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */ + dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */ + dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */ + dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */ + dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */ + + dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */ + dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */ + dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */ + + dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */ + dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */ + + dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */ + + dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */ + dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */ + } + + /* m2mf state */ + dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */ + dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */ + dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */ + dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */ + dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */ + dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */ + dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */ + dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */ + dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */ + dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */ + dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */ + dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */ + dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */ + dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */ + dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */ + + /* more compat 2d state */ + if (device->chipset == 0x50) { + dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */ + + dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */ + + dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */ + dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */ + dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */ + dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */ + dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */ + dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */ + dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */ + dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */ + dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */ + dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */ + dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */ + + dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */ + } + + /* tesla state */ + dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */ + dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */ + dd_emit(ctx, 1, 0); /* 000000ff */ + dd_emit(ctx, 1, 0); /* ffffffff */ + dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */ + dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */ + dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */ + dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */ + dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */ + dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */ + if (IS_NVA3F(device->chipset)) { + dd_emit(ctx, 1, 0); /* ffffffff */ + dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */ + } else { + dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */ + } + dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */ + if (device->chipset != 0x50) + dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */ + dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */ + dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */ + if (device->chipset == 0x50) { + dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */ + dd_emit(ctx, 1, 0); /* 00000001 */ + } else { + dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */ + dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */ + dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */ + dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ + dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */ + dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */ + dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ + dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */ + } + dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */ + dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */ + dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */ + dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */ + dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */ + dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */ + dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */ + dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */ + dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */ + dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */ + dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ + dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */ + dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */ + if (device->chipset != 0x50) + dd_emit(ctx, 3, 0); /* 1, 1, 1 */ + else + dd_emit(ctx, 2, 0); /* 1, 1 */ + dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */ + dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/ + dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ + dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + if (IS_NVA3F(device->chipset)) { + dd_emit(ctx, 1, 3); /* 00000003 */ + dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */ + } + if (device->chipset != 0x50) + dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */ + dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */ + dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */ + if (device->chipset != 0x50) + dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */ + dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */ + dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */ + dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */ + dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */ + dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */ + dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */ + dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */ + dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ + dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ + dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ + if (device->chipset >= 0xa0) + dd_emit(ctx, 1, 0); /* ffffffff */ + dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */ + dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */ + dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ + dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ + dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/ + if (device->chipset != 0x50) + dd_emit(ctx, 8, 0); /* 00000001 */ + if (device->chipset >= 0xa0) { + dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */ + dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */ + dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */ + dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */ + } + dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */ + dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */ + dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */ + if (IS_NVA3F(device->chipset)) + dd_emit(ctx, 1, 0); /* 00000001 */ + dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */ + if (device->chipset >= 0xa0) + dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */ + dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ + if (device->chipset >= 0xa0) + dd_emit(ctx, 1, 0); /* 00000003 */ + dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */ + dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */ + dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */ + dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */ + dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */ + if (device->chipset != 0x50) { + dd_emit(ctx, 1, 0xe00); /* 7fff */ + dd_emit(ctx, 1, 0x1000); /* 7fff */ + dd_emit(ctx, 1, 0x1e00); /* 7fff */ + } + dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */ + dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */ + dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */ + dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */ + dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */ + dd_emit(ctx, 1, 1); /* 00000001 */ + dd_emit(ctx, 1, 0); /* 00000001 */ + dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */ + dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */ + dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */ + if (IS_NVA3F(device->chipset)) + dd_emit(ctx, 1, 0x200); + dd_emit(ctx, 1, 0); /* 00000001 */ + if (device->chipset < 0xa0) { + dd_emit(ctx, 1, 1); /* 00000001 */ + dd_emit(ctx, 1, 0x70); /* 000000ff */ + dd_emit(ctx, 1, 0x80); /* 000000ff */ + dd_emit(ctx, 1, 0); /* 000000ff */ + dd_emit(ctx, 1, 0); /* 00000001 */ + dd_emit(ctx, 1, 1); /* 00000001 */ + dd_emit(ctx, 1, 0x70); /* 000000ff */ + dd_emit(ctx, 1, 0x80); /* 000000ff */ + dd_emit(ctx, 1, 0); /* 000000ff */ + } else { + dd_emit(ctx, 1, 1); /* 00000001 */ + dd_emit(ctx, 1, 0xf0); /* 000000ff */ + dd_emit(ctx, 1, 0xff); /* 000000ff */ + dd_emit(ctx, 1, 0); /* 000000ff */ + dd_emit(ctx, 1, 0); /* 00000001 */ + dd_emit(ctx, 1, 1); /* 00000001 */ + dd_emit(ctx, 1, 0xf0); /* 000000ff */ + dd_emit(ctx, 1, 0xff); /* 000000ff */ + dd_emit(ctx, 1, 0); /* 000000ff */ + dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */ + } + + /* eng2d state */ + dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */ + dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */ + dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */ + dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */ + dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */ + dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */ + dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */ + dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */ + dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */ + dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */ + dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */ + dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */ + dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */ + dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */ + dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */ + dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */ + dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */ + dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */ + dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */ + dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */ + + num = ctx->ctxvals_pos - base; + ctx->ctxvals_pos = base; + if (IS_NVA3F(device->chipset)) + cp_ctx(ctx, 0x404800, num); + else + cp_ctx(ctx, 0x405400, num); +} + +/* + * xfer areas. These are a pain. + * + * There are 2 xfer areas: the first one is big and contains all sorts of + * stuff, the second is small and contains some per-TP context. + * + * Each area is split into 8 "strands". The areas, when saved to grctx, + * are made of 8-word blocks. Each block contains a single word from + * each strand. The strands are independent of each other, their + * addresses are unrelated to each other, and data in them is closely + * packed together. The strand layout varies a bit between cards: here + * and there, a single word is thrown out in the middle and the whole + * strand is offset by a bit from corresponding one on another chipset. + * For this reason, addresses of stuff in strands are almost useless. + * Knowing sequence of stuff and size of gaps between them is much more + * useful, and that's how we build the strands in our generator. + * + * NVA0 takes this mess to a whole new level by cutting the old strands + * into a few dozen pieces [known as genes], rearranging them randomly, + * and putting them back together to make new strands. Hopefully these + * genes correspond more or less directly to the same PGRAPH subunits + * as in 400040 register. + * + * The most common value in default context is 0, and when the genes + * are separated by 0's, gene bounduaries are quite speculative... + * some of them can be clearly deduced, others can be guessed, and yet + * others won't be resolved without figuring out the real meaning of + * given ctxval. For the same reason, ending point of each strand + * is unknown. Except for strand 0, which is the longest strand and + * its end corresponds to end of the whole xfer. + * + * An unsolved mystery is the seek instruction: it takes an argument + * in bits 8-18, and that argument is clearly the place in strands to + * seek to... but the offsets don't seem to correspond to offsets as + * seen in grctx. Perhaps there's another, real, not randomly-changing + * addressing in strands, and the xfer insn just happens to skip over + * the unused bits? NV10-NV30 PIPE comes to mind... + * + * As far as I know, there's no way to access the xfer areas directly + * without the help of ctxprog. + */ + +static void +xf_emit(struct nouveau_grctx *ctx, int num, u32 val) { + int i; + if (val && ctx->mode == NOUVEAU_GRCTX_VALS) + for (i = 0; i < num; i++) + nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); + ctx->ctxvals_pos += num << 3; +} + +/* Gene declarations... */ + +static void nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx); +static void nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx); + +static void +nv50_gr_construct_xfer1(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + int offset; + int size = 0; + u32 units = nv_rd32 (ctx->device, 0x1540); + + offset = (ctx->ctxvals_pos+0x3f)&~0x3f; + ctx->ctxvals_base = offset; + + if (device->chipset < 0xa0) { + /* Strand 0 */ + ctx->ctxvals_pos = offset; + nv50_gr_construct_gene_dispatch(ctx); + nv50_gr_construct_gene_m2mf(ctx); + nv50_gr_construct_gene_unk24xx(ctx); + nv50_gr_construct_gene_clipid(ctx); + nv50_gr_construct_gene_zcull(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 1 */ + ctx->ctxvals_pos = offset + 0x1; + nv50_gr_construct_gene_vfetch(ctx); + nv50_gr_construct_gene_eng2d(ctx); + nv50_gr_construct_gene_csched(ctx); + nv50_gr_construct_gene_ropm1(ctx); + nv50_gr_construct_gene_ropm2(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 2 */ + ctx->ctxvals_pos = offset + 0x2; + nv50_gr_construct_gene_ccache(ctx); + nv50_gr_construct_gene_unk1cxx(ctx); + nv50_gr_construct_gene_strmout(ctx); + nv50_gr_construct_gene_unk14xx(ctx); + nv50_gr_construct_gene_unk10xx(ctx); + nv50_gr_construct_gene_unk34xx(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 3: per-ROP group state */ + ctx->ctxvals_pos = offset + 3; + for (i = 0; i < 6; i++) + if (units & (1 << (i + 16))) + nv50_gr_construct_gene_ropc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strands 4-7: per-TP state */ + for (i = 0; i < 4; i++) { + ctx->ctxvals_pos = offset + 4 + i; + if (units & (1 << (2 * i))) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << (2 * i + 1))) + nv50_gr_construct_xfer_tp(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + } else { + /* Strand 0 */ + ctx->ctxvals_pos = offset; + nv50_gr_construct_gene_dispatch(ctx); + nv50_gr_construct_gene_m2mf(ctx); + nv50_gr_construct_gene_unk34xx(ctx); + nv50_gr_construct_gene_csched(ctx); + nv50_gr_construct_gene_unk1cxx(ctx); + nv50_gr_construct_gene_strmout(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 1 */ + ctx->ctxvals_pos = offset + 1; + nv50_gr_construct_gene_unk10xx(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 2 */ + ctx->ctxvals_pos = offset + 2; + if (device->chipset == 0xa0) + nv50_gr_construct_gene_unk14xx(ctx); + nv50_gr_construct_gene_unk24xx(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 3 */ + ctx->ctxvals_pos = offset + 3; + nv50_gr_construct_gene_vfetch(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 4 */ + ctx->ctxvals_pos = offset + 4; + nv50_gr_construct_gene_ccache(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 5 */ + ctx->ctxvals_pos = offset + 5; + nv50_gr_construct_gene_ropm2(ctx); + nv50_gr_construct_gene_ropm1(ctx); + /* per-ROP context */ + for (i = 0; i < 8; i++) + if (units & (1<<(i+16))) + nv50_gr_construct_gene_ropc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 6 */ + ctx->ctxvals_pos = offset + 6; + nv50_gr_construct_gene_zcull(ctx); + nv50_gr_construct_gene_clipid(ctx); + nv50_gr_construct_gene_eng2d(ctx); + if (units & (1 << 0)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 1)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 2)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 3)) + nv50_gr_construct_xfer_tp(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 7 */ + ctx->ctxvals_pos = offset + 7; + if (device->chipset == 0xa0) { + if (units & (1 << 4)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 5)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 6)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 7)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 8)) + nv50_gr_construct_xfer_tp(ctx); + if (units & (1 << 9)) + nv50_gr_construct_xfer_tp(ctx); + } else { + nv50_gr_construct_gene_unk14xx(ctx); + } + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + + ctx->ctxvals_pos = offset + size * 8; + ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; + cp_lsr (ctx, offset); + cp_out (ctx, CP_SET_XFER_POINTER); + cp_lsr (ctx, size); + cp_out (ctx, CP_SEEK_1); + cp_out (ctx, CP_XFER_1); + cp_wait(ctx, XFER, BUSY); +} + +/* + * non-trivial demagiced parts of ctx init go here + */ + +static void +nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx) +{ + /* start of strand 0 */ + struct nouveau_device *device = ctx->device; + /* SEEK */ + if (device->chipset == 0x50) + xf_emit(ctx, 5, 0); + else if (!IS_NVA3F(device->chipset)) + xf_emit(ctx, 6, 0); + else + xf_emit(ctx, 4, 0); + /* SEEK */ + /* the PGRAPH's internal FIFO */ + if (device->chipset == 0x50) + xf_emit(ctx, 8*3, 0); + else + xf_emit(ctx, 0x100*3, 0); + /* and another bonus slot?!? */ + xf_emit(ctx, 3, 0); + /* and YET ANOTHER bonus slot? */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 3, 0); + /* SEEK */ + /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */ + xf_emit(ctx, 9, 0); + /* SEEK */ + xf_emit(ctx, 9, 0); + /* SEEK */ + xf_emit(ctx, 9, 0); + /* SEEK */ + xf_emit(ctx, 9, 0); + /* SEEK */ + if (device->chipset < 0x90) + xf_emit(ctx, 4, 0); + /* SEEK */ + xf_emit(ctx, 2, 0); + /* SEEK */ + xf_emit(ctx, 6*2, 0); + xf_emit(ctx, 2, 0); + /* SEEK */ + xf_emit(ctx, 2, 0); + /* SEEK */ + xf_emit(ctx, 6*2, 0); + xf_emit(ctx, 2, 0); + /* SEEK */ + if (device->chipset == 0x50) + xf_emit(ctx, 0x1c, 0); + else if (device->chipset < 0xa0) + xf_emit(ctx, 0x1e, 0); + else + xf_emit(ctx, 0x22, 0); + /* SEEK */ + xf_emit(ctx, 0x15, 0); +} + +static void +nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx) +{ + /* Strand 0, right after dispatch */ + struct nouveau_device *device = ctx->device; + int smallm2mf = 0; + if (device->chipset < 0x92 || device->chipset == 0x98) + smallm2mf = 1; + /* SEEK */ + xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ + xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ + xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ + xf_emit (ctx, 1, 0); /* OFFSET_IN */ + xf_emit (ctx, 1, 0); /* OFFSET_OUT */ + xf_emit (ctx, 1, 0); /* PITCH_IN */ + xf_emit (ctx, 1, 0); /* PITCH_OUT */ + xf_emit (ctx, 1, 0); /* LINE_LENGTH */ + xf_emit (ctx, 1, 0); /* LINE_COUNT */ + xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ + xf_emit (ctx, 1, 1); /* LINEAR_IN */ + xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ + xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ + xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ + xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ + xf_emit (ctx, 1, 1); /* LINEAR_OUT */ + xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ + xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ + xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ + xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ + xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ + xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ + /* SEEK */ + if (smallm2mf) + xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */ + else + xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */ + xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */ + /* SEEK */ + if (smallm2mf) + xf_emit(ctx, 0x400, 0); /* ffffffff */ + else + xf_emit(ctx, 0x800, 0); /* ffffffff */ + xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */ + /* SEEK */ + xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */ + xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */ +} + +static void +nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + xf_emit(ctx, 2, 0); /* RO */ + xf_emit(ctx, 0x800, 0); /* ffffffff */ + switch (device->chipset) { + case 0x50: + case 0x92: + case 0xa0: + xf_emit(ctx, 0x2b, 0); + break; + case 0x84: + xf_emit(ctx, 0x29, 0); + break; + case 0x94: + case 0x96: + case 0xa3: + xf_emit(ctx, 0x27, 0); + break; + case 0x86: + case 0x98: + case 0xa5: + case 0xa8: + case 0xaa: + case 0xac: + case 0xaf: + xf_emit(ctx, 0x25, 0); + break; + } + /* CB bindings, 0x80 of them. first word is address >> 8, second is + * size >> 4 | valid << 24 */ + xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */ + xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */ + xf_emit(ctx, 1, 0); /* 0 */ + xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */ + xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */ + xf_emit(ctx, 4, 0); /* RO */ + xf_emit(ctx, 0x100, 0); /* ffffffff */ + xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */ + xf_emit(ctx, 8, 0); /* ffffffff */ + xf_emit(ctx, 4, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 3 */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */ + xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ + xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */ + xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ + xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */ + xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ + xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */ + xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */ + xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */ + xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */ + xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ + xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */ +} + +static void +nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + /* end of area 2 on pre-NVA0, area 1 on NVAx */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ + xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ + if (device->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); + else + xf_emit(ctx, 1, 0x7ff); /* 000007ff */ + xf_emit(ctx, 1, 0); /* 111/113 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + for (i = 0; i < 8; i++) { + switch (device->chipset) { + case 0x50: + case 0x86: + case 0x98: + case 0xaa: + case 0xac: + xf_emit(ctx, 0xa0, 0); /* ffffffff */ + break; + case 0x84: + case 0x92: + case 0x94: + case 0x96: + xf_emit(ctx, 0x120, 0); + break; + case 0xa5: + case 0xa8: + xf_emit(ctx, 0x100, 0); /* ffffffff */ + break; + case 0xa0: + case 0xa3: + case 0xaf: + xf_emit(ctx, 0x400, 0); /* ffffffff */ + break; + } + xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */ + xf_emit(ctx, 4, 0); /* ffffffff */ + } + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ + xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */ + xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +} + +static void +nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + /* end of area 2 on pre-NVA0, area 1 on NVAx */ + xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ + xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ + xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */ + xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ + xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */ + xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ + xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ + xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 0x0fac6881); + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 1); + xf_emit(ctx, 3, 0); + } +} + +static void +nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ + if (device->chipset != 0x50) { + xf_emit(ctx, 5, 0); /* ffffffff */ + xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 2, 4); /* 7f, ff */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + } + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 0); /* 3ff */ + xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ + xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ + xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */ + xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0); /* 0000000f */ + if (device->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ + else + xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ + xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ + xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */ + xf_emit(ctx, 3, 0); /* f, 0, 0 */ + xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ + xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */ + xf_emit(ctx, 3, 0); /* f, 0, 0 */ + xf_emit(ctx, 3, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ + xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ + xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ + xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ + xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0); /* 0000000f */ + xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ + xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ + if (device->chipset != 0x50) { + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + } + xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */ + xf_emit(ctx, 1, 0); /* f */ + xf_emit(ctx, 1, 0); /* 0? */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 003fffff */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ + xf_emit(ctx, 1, 0); /* 0000000f */ +} + +static void +nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ + /* SEEK */ + xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ + xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ + xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ + xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ + xf_emit(ctx, 1, 0); /* 0000ffff */ + xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */ + xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ + xf_emit(ctx, 1, 0); /* 00000007 */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */ + xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ + /* SEEK */ + xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ + xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ + xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ + xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ + xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ + xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */ +} + +static void +nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx) +{ + /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */ + /* SEEK */ + xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */ + xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */ + xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ + xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */ + xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ + xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */ + xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */ + xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */ + xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */ +} + +static void +nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ + /* SEEK */ + xf_emit(ctx, 0x33, 0); + /* SEEK */ + xf_emit(ctx, 2, 0); + /* SEEK */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + /* SEEK */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 4, 0); /* RO */ + xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ + xf_emit(ctx, 1, 0); /* 1ff */ + xf_emit(ctx, 8, 0); /* 0? */ + xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ + + xf_emit(ctx, 4, 0); /* RO */ + xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ + xf_emit(ctx, 1, 0); /* 1ff */ + xf_emit(ctx, 8, 0); /* 0? */ + xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ + } else { + xf_emit(ctx, 0xc, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ + xf_emit(ctx, 1, 0); /* 1ff */ + xf_emit(ctx, 8, 0); /* 0? */ + + /* SEEK */ + xf_emit(ctx, 0xc, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ + xf_emit(ctx, 1, 0); /* 1ff */ + xf_emit(ctx, 8, 0); /* 0? */ + } + /* SEEK */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ + xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ + xf_emit(ctx, 1, 1); /* 00000001 */ + /* SEEK */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 2, 4); /* 000000ff */ + xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f */ + xf_emit(ctx, 1, 1); /* 00000001 */ + for (i = 0; i < 10; i++) { + /* SEEK */ + xf_emit(ctx, 0x40, 0); /* ffffffff */ + xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */ + xf_emit(ctx, 0x10, 0); /* ffffffff */ + } + /* SEEK */ + xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */ + xf_emit(ctx, 1, 1); /* 00000001 */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ + xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */ + xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 0); /* 000003ff */ +} + +static void +nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int acnt = 0x10, rep, i; + /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ + if (IS_NVA3F(device->chipset)) + acnt = 0x20; + /* SEEK */ + if (device->chipset >= 0xa0) { + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */ + xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */ + } + xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */ + xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */ + xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */ + xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */ + xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ + xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */ + xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */ + xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + /* SEEK */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0xb, 0); /* RO */ + else if (device->chipset >= 0xa0) + xf_emit(ctx, 0x9, 0); /* RO */ + else + xf_emit(ctx, 0x8, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */ + xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ + /* SEEK */ + xf_emit(ctx, 0xc, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* 7f/ff */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ + xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */ + xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + if (device->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */ + else + xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */ + if (device->chipset == 0xa8) + xf_emit(ctx, 1, 0x1e00); /* 7fff */ + /* SEEK */ + xf_emit(ctx, 0xc, 0); /* RO or close */ + /* SEEK */ + xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ + if (device->chipset > 0x50 && device->chipset < 0xa0) + xf_emit(ctx, 2, 0); /* ffffffff */ + else + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */ + /* SEEK */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 0x10, 0); /* 0? */ + xf_emit(ctx, 2, 0); /* weird... */ + xf_emit(ctx, 2, 0); /* RO */ + } else { + xf_emit(ctx, 8, 0); /* 0? */ + xf_emit(ctx, 1, 0); /* weird... */ + xf_emit(ctx, 2, 0); /* RO */ + } + /* SEEK */ + xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */ + xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */ + xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ + xf_emit(ctx, 1, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ + xf_emit(ctx, 1, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* RO */ + xf_emit(ctx, 2, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */ + xf_emit(ctx, 1, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */ + xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */ + xf_emit(ctx, 3, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */ + xf_emit(ctx, 3, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */ + xf_emit(ctx, 3, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */ + xf_emit(ctx, 3, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */ + xf_emit(ctx, 3, 0); /* f/1f */ + /* SEEK */ + xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */ + xf_emit(ctx, 3, 0); /* f/1f */ + /* SEEK */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, acnt, 0); /* f */ + xf_emit(ctx, 3, 0); /* f/1f */ + } + /* SEEK */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 2, 0); /* RO */ + else + xf_emit(ctx, 5, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */ + /* SEEK */ + if (device->chipset < 0xa0) { + xf_emit(ctx, 0x41, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 0x11, 0); /* RO */ + } else if (!IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x50, 0); /* RO */ + else + xf_emit(ctx, 0x58, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, 1, 1); /* 1 UNK0DEC */ + /* SEEK */ + xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */ + xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */ + /* SEEK */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x1d, 0); /* RO */ + else + xf_emit(ctx, 0x16, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ + /* SEEK */ + if (device->chipset < 0xa0) + xf_emit(ctx, 8, 0); /* RO */ + else if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0xc, 0); /* RO */ + else + xf_emit(ctx, 7, 0); /* RO */ + /* SEEK */ + xf_emit(ctx, 0xa, 0); /* RO */ + if (device->chipset == 0xa0) + rep = 0xc; + else + rep = 4; + for (i = 0; i < rep; i++) { + /* SEEK */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x20, 0); /* ffffffff */ + xf_emit(ctx, 0x200, 0); /* ffffffff */ + xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */ + xf_emit(ctx, 4, 0); /* ffffffff */ + } + /* SEEK */ + xf_emit(ctx, 1, 0); /* 113/111 */ + xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ + xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */ + xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + /* SEEK */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 7, 0); /* weird... */ + else + xf_emit(ctx, 5, 0); /* weird... */ +} + +static void +nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ + /* SEEK */ + xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ + xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */ + xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */ + if (device->chipset < 0xa0) { + /* this is useless on everything but the original NV50, + * guess they forgot to nuke it. Or just didn't bother. */ + xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */ + xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */ + xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */ + } + xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ + xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ + xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ + xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */ + xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */ + xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */ + xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */ + xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */ + xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */ + xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */ + xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */ + xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */ + xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */ + xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */ + xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */ + xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */ + xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ + xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */ + xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */ + xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */ + xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */ + xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */ + xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ + xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ + xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ + xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ + xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */ + xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */ + xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */ + xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */ + xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */ + xf_emit(ctx, 1, 0); /* 00000001 UNK888 */ + xf_emit(ctx, 1, 4); /* 0000003f UNK884 */ + xf_emit(ctx, 1, 0); /* 00000007 UNK880 */ + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */ + xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */ + xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */ + xf_emit(ctx, 1, 0); /* 00000001 UNK260 */ + xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */ + /* SEEK */ + xf_emit(ctx, 0x10, 0); + /* SEEK */ + xf_emit(ctx, 0x27, 0); +} + +static void +nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ + /* SEEK */ + xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ + xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 0); /* 000003ff */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */ + xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */ + xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */ + xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */ + xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */ + xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */ + xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ + xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ + xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ + xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ + xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ + xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ + /* SEEK */ + xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */ + switch (device->chipset) { + case 0x50: + case 0x92: + xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ + xf_emit(ctx, 0x80, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */ + break; + case 0x84: + xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ + xf_emit(ctx, 0x60, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ + break; + case 0x94: + case 0x96: + xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ + xf_emit(ctx, 0x40, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */ + break; + case 0x86: + case 0x98: + xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ + xf_emit(ctx, 0x10, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ + break; + case 0xa0: + xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ + xf_emit(ctx, 0xf0, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */ + break; + case 0xa3: + xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ + xf_emit(ctx, 0x60, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ + break; + case 0xa5: + case 0xaf: + xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ + xf_emit(ctx, 0x30, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */ + break; + case 0xaa: + xf_emit(ctx, 0x12, 0); + break; + case 0xa8: + case 0xac: + xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ + xf_emit(ctx, 0x10, 0); /* fff */ + xf_emit(ctx, 2, 0); /* ff, fff */ + xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ + break; + } + xf_emit(ctx, 1, 0); /* 0000000f */ + xf_emit(ctx, 1, 0); /* 00000000 */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 0000001f */ + xf_emit(ctx, 4, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 4, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 000000ff */ +} + +static void +nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ + xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ + xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ + xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */ + xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ + xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ + xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */ + xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ + xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ + xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */ + else if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */ + xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ + xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ + xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ + xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */ + xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ + xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */ + if (device->chipset != 0x50) { + xf_emit(ctx, 1, 0); /* 3ff */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */ + } + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ + xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ + xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ + xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */ + xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ + xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */ + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ + xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ + if (device->chipset < 0xa0) + xf_emit(ctx, 0x1c, 0); /* RO */ + else if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x9, 0); + xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ + xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ + if (device->chipset != 0x50) { + xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ + xf_emit(ctx, 1, 0); /* 3ff */ + } + /* XXX: the following block could belong either to unk1cxx, or + * to STRMOUT. Rather hard to tell. */ + if (device->chipset < 0xa0) + xf_emit(ctx, 0x25, 0); + else + xf_emit(ctx, 0x3b, 0); +} + +static void +nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ + xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ + xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ + if (device->chipset >= 0xa0) { + xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ + xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ + } + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + if (device->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ + else + xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + /* SEEK */ + xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ + xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ + xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */ + xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */ + xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ + if (device->chipset >= 0xa0) { + xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ + xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ + } + xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ + xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ + xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */ + xf_emit(ctx, 2, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + /* SEEK */ + xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */ + xf_emit(ctx, 1, 0); /* 0000000f */ + xf_emit(ctx, 1, 0); /* 00000000? */ + xf_emit(ctx, 2, 0); /* ffffffff */ +} + +static void +nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ + xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +} + +static void +nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + /* SEEK */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 2, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ + xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ + xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ + xf_emit(ctx, 1, 0); /* 7 */ + /* SEEK */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ + xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ + xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ + xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ + xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ + xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 0); /* 00000007 */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +} + +static void +nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int magic2; + if (device->chipset == 0x50) { + magic2 = 0x00003e60; + } else if (!IS_NVA3F(device->chipset)) { + magic2 = 0x001ffe67; + } else { + magic2 = 0x00087e67; + } + xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset)) + xf_emit(ctx, 1, 0x15); /* 000000ff */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ + xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) { + xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */ + xf_emit(ctx, 1, 4); /* 7 */ + xf_emit(ctx, 1, 0x400); /* fffffff */ + xf_emit(ctx, 1, 0x300); /* ffff */ + xf_emit(ctx, 1, 0x1001); /* 1fff */ + if (device->chipset != 0xa0) { + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */ + else + xf_emit(ctx, 1, 0x15); /* ff */ + } + } + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ + xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ + xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ + xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ + xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ + if (device->chipset >= 0xa0) { + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x1001); + xf_emit(ctx, 0xb, 0); + } else { + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + } + xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 1, 0x11); /* 3f/7f */ + xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ + if (device->chipset != 0x50) { + xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ + xf_emit(ctx, 1, 0); /* 000000ff */ + } + xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ + xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */ + xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ + xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ + xf_emit(ctx, 2, 0); /* 00000001 */ + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* 0000000f */ + xf_emit(ctx, 1, 0); /* 00000003 */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 2, 0); /* 00000001 */ + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + } else if (device->chipset >= 0xa0) { + xf_emit(ctx, 2, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* 00000003 */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 2, 0); /* 00000001 */ + } else { + xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + } + xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */ + xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */ + xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 2, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ + xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ + xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */ + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ + } + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ + xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */ + xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */ + xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */ + xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */ + xf_emit(ctx, 1, 0); /* 000000ff ROP */ + xf_emit(ctx, 1, 0); /* ffffffff BETA1 */ + xf_emit(ctx, 1, 0); /* ffffffff BETA4 */ + xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ + xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */ +} + +static void +nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int magic3; + switch (device->chipset) { + case 0x50: + magic3 = 0x1000; + break; + case 0x86: + case 0x98: + case 0xa8: + case 0xaa: + case 0xac: + case 0xaf: + magic3 = 0x1e00; + break; + default: + magic3 = 0; + } + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x1f, 0); /* ffffffff */ + else if (device->chipset >= 0xa0) + xf_emit(ctx, 0x0f, 0); /* ffffffff */ + else + xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */ + xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 0x03020100); /* ffffffff */ + else + xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ + if (magic3) + xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0); /* 111/113 */ + xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */ + xf_emit(ctx, 1, 0); /* 0000001f */ + xf_emit(ctx, 1, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */ + xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ + if (magic3) + xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0); /* 111/113 */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ + xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */ + xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + xf_emit(ctx, 1, 0); /* 111/113 */ + if (device->chipset == 0x94 || device->chipset == 0x96) + xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ + else if (device->chipset < 0xa0) + xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ + else if (!IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x210, 0); /* ffffffff */ + else + xf_emit(ctx, 0x410, 0); /* ffffffff */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ + xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ + xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +} + +static void +nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int magic1, magic2; + if (device->chipset == 0x50) { + magic1 = 0x3ff; + magic2 = 0x00003e60; + } else if (!IS_NVA3F(device->chipset)) { + magic1 = 0x7ff; + magic2 = 0x001ffe67; + } else { + magic1 = 0x7ff; + magic2 = 0x00087e67; + } + xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */ + xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */ + xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ + xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */ + xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ + xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ + xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ + xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ + xf_emit(ctx, 1, 0); /* 7 */ + xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */ + xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */ + xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */ + xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ + xf_emit(ctx, 1, 0); /* 00000003 */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */ + } else if (device->chipset >= 0xa0) { + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */ + xf_emit(ctx, 1, 0); /* 00000003 */ + } else { + xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ + } + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ + xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */ + xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ + } + xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ + xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ + xf_emit(ctx, 1, 0); /* 7 */ + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ + xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ + xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ + xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */ + xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */ + xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + if (device->chipset == 0x50) + xf_emit(ctx, 1, 0); /* ff */ + else + xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ + xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ + xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ + xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ + xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */ + xf_emit(ctx, 1, 0); /* 7 */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */ + xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */ + xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ + xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */ + xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */ + xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */ + xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */ + xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */ + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ + xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */ + xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ + xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */ + xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */ + xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ + xf_emit(ctx, 1, 0); /* 0000ffff */ + xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ + xf_emit(ctx, 1, 0); /* 00000007 */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 2, 0); /* ffff, ff/3ff */ + xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */ + xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */ + xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */ + xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */ + xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 0); /* 00000001 */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ + xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ + xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ + xf_emit(ctx, 1, 0); /* 7 */ + xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + } + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 0x0fac6881); /* fffffff */ + xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ + xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ + xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */ + } + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ + if (device->chipset >= 0xa0) { + xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */ + xf_emit(ctx, 1, 0xfac6881); /* fffffff */ + xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */ + xf_emit(ctx, 1, 4); /* 7 */ + xf_emit(ctx, 1, 0); /* 1 */ + xf_emit(ctx, 2, 1); /* 1 */ + xf_emit(ctx, 2, 0); /* 7, f */ + xf_emit(ctx, 1, 1); /* 1 */ + xf_emit(ctx, 1, 0); /* 7/f */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 0x9, 0); /* 1 */ + else + xf_emit(ctx, 0x8, 0); /* 1 */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 8, 1); /* 1 */ + xf_emit(ctx, 1, 0x11); /* 7f */ + xf_emit(ctx, 7, 0); /* 7f */ + xf_emit(ctx, 1, 0xfac6881); /* fffffff */ + xf_emit(ctx, 1, 0xf); /* f */ + xf_emit(ctx, 7, 0); /* f */ + xf_emit(ctx, 1, 0x11); /* 7f */ + xf_emit(ctx, 1, 1); /* 1 */ + xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + } + } +} + +static void +nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ + if (device->chipset != 0x50) + xf_emit(ctx, 1, 0); /* 3 */ + xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */ + xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */ + xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */ + xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */ + if (device->chipset == 0x50) + xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */ + else + xf_emit(ctx, 2, 0); /* 3ff, 1 */ + xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */ + xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */ + xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */ + xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */ + xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */ + xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */ + xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */ + xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */ + if (device->chipset == 0x50) { + xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ + xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */ + xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */ + } else if (!IS_NVAAF(device->chipset)) { + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ + xf_emit(ctx, 1, 0); /* 00000003 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + xf_emit(ctx, 1, 0); /* 00000003 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */ + xf_emit(ctx, 1, 0); /* 00000003 */ + xf_emit(ctx, 1, 0); /* 000003ff */ + } else { + xf_emit(ctx, 0x6, 0); + } + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */ + xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */ +} + +static void +nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ + xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ + xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ + xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ + xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ + xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ + xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ + xf_emit(ctx, 1, 0); /* ffff0ff3 */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ + xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ + xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ + xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ + xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */ + xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */ + xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */ + xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */ + xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ + xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +} + +static void +nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + if (device->chipset < 0xa0) { + nv50_gr_construct_xfer_unk84xx(ctx); + nv50_gr_construct_xfer_tprop(ctx); + nv50_gr_construct_xfer_tex(ctx); + nv50_gr_construct_xfer_unk8cxx(ctx); + } else { + nv50_gr_construct_xfer_tex(ctx); + nv50_gr_construct_xfer_tprop(ctx); + nv50_gr_construct_xfer_unk8cxx(ctx); + nv50_gr_construct_xfer_unk84xx(ctx); + } +} + +static void +nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i, mpcnt = 2; + switch (device->chipset) { + case 0x98: + case 0xaa: + mpcnt = 1; + break; + case 0x50: + case 0x84: + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0xa8: + case 0xac: + mpcnt = 2; + break; + case 0xa0: + case 0xa3: + case 0xa5: + case 0xaf: + mpcnt = 3; + break; + } + for (i = 0; i < mpcnt; i++) { + xf_emit(ctx, 1, 0); /* ff */ + xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */ + xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */ + xf_emit(ctx, 1, 0x04000400); /* ffffffff */ + if (device->chipset >= 0xa0) + xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */ + xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ + if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) { + xf_emit(ctx, 1, 0xe00); /* 7fff */ + xf_emit(ctx, 1, 0x1e00); /* 7fff */ + } + xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */ + xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + if (device->chipset == 0x50) + xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */ + xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */ + xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ + xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ + xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ + if (IS_NVAAF(device->chipset)) + xf_emit(ctx, 0xb, 0); /* RO */ + else if (device->chipset >= 0xa0) + xf_emit(ctx, 0xc, 0); /* RO */ + else + xf_emit(ctx, 0xa, 0); /* RO */ + } + xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + if (device->chipset >= 0xa0) { + xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */ + } + xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */ + xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ + xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ + xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ + xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ + xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ + xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ + xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ + xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ + xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */ + xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ + xf_emit(ctx, 1, 0); /* ff/3ff */ + xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */ + xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */ + xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ + xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ + xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ + xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */ + xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ + xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ + xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ + xf_emit(ctx, 1, 0); /* 00000007 */ + xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */ + xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ + if (IS_NVA3F(device->chipset)) + xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ + xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ + xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ + xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */ + xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ + xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ + xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ + xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ + if (IS_NVA3F(device->chipset)) { + xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ + xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ + xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ + xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ + xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ + xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ + } + xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ + xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ + /* XXX: demagic this part some day */ + if (device->chipset == 0x50) + xf_emit(ctx, 0x3a0, 0); + else if (device->chipset < 0x94) + xf_emit(ctx, 0x3a2, 0); + else if (device->chipset == 0x98 || device->chipset == 0xaa) + xf_emit(ctx, 0x39f, 0); + else + xf_emit(ctx, 0x3a3, 0); + xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ + xf_emit(ctx, 1, 0); /* 7 OPERATION */ + xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */ + xf_emit(ctx, 0x2d, 0); +} + +static void +nv50_gr_construct_xfer2(struct nouveau_grctx *ctx) +{ + struct nouveau_device *device = ctx->device; + int i; + u32 offset; + u32 units = nv_rd32 (ctx->device, 0x1540); + int size = 0; + + offset = (ctx->ctxvals_pos+0x3f)&~0x3f; + + if (device->chipset < 0xa0) { + for (i = 0; i < 8; i++) { + ctx->ctxvals_pos = offset + i; + /* that little bugger belongs to csched. No idea + * what it's doing here. */ + if (i == 0) + xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ + if (units & (1 << i)) + nv50_gr_construct_xfer_mpc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + } else { + /* Strand 0: TPs 0, 1 */ + ctx->ctxvals_pos = offset; + /* that little bugger belongs to csched. No idea + * what it's doing here. */ + xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ + if (units & (1 << 0)) + nv50_gr_construct_xfer_mpc(ctx); + if (units & (1 << 1)) + nv50_gr_construct_xfer_mpc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 1: TPs 2, 3 */ + ctx->ctxvals_pos = offset + 1; + if (units & (1 << 2)) + nv50_gr_construct_xfer_mpc(ctx); + if (units & (1 << 3)) + nv50_gr_construct_xfer_mpc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 2: TPs 4, 5, 6 */ + ctx->ctxvals_pos = offset + 2; + if (units & (1 << 4)) + nv50_gr_construct_xfer_mpc(ctx); + if (units & (1 << 5)) + nv50_gr_construct_xfer_mpc(ctx); + if (units & (1 << 6)) + nv50_gr_construct_xfer_mpc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 3: TPs 7, 8, 9 */ + ctx->ctxvals_pos = offset + 3; + if (units & (1 << 7)) + nv50_gr_construct_xfer_mpc(ctx); + if (units & (1 << 8)) + nv50_gr_construct_xfer_mpc(ctx); + if (units & (1 << 9)) + nv50_gr_construct_xfer_mpc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + ctx->ctxvals_pos = offset + size * 8; + ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; + cp_lsr (ctx, offset); + cp_out (ctx, CP_SET_XFER_POINTER); + cp_lsr (ctx, size); + cp_out (ctx, CP_SEEK_2); + cp_out (ctx, CP_XFER_2); + cp_wait(ctx, XFER, BUSY); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c new file mode 100644 index 000000000000..08a925efecf2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c @@ -0,0 +1,1386 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvc0_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +const struct nvc0_gr_pack +nvc0_grctx_pack_icmd[] = { + { nvc0_grctx_init_icmd_0 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_9097_0[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x002700, 8, 0x20, 0x00000000 }, + { 0x002704, 8, 0x20, 0x00000000 }, + { 0x002708, 8, 0x20, 0x00000000 }, + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x002710, 8, 0x20, 0x00014000 }, + { 0x002714, 8, 0x20, 0x00000040 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002200, 5, 0x10, 0x00000022 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00001fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x003fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 4, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 1, 0x04, 0x003fffff }, + { 0x0002d0, 1, 0x04, 0x00000c48 }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00300008 }, + { 0x001284, 1, 0x04, 0x04000080 }, + { 0x001450, 1, 0x04, 0x00300008 }, + { 0x001454, 1, 0x04, 0x04000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_902d_0[] = { + { 0x000200, 1, 0x04, 0x000000cf }, + { 0x000204, 1, 0x04, 0x00000001 }, + { 0x000208, 1, 0x04, 0x00000020 }, + { 0x00020c, 1, 0x04, 0x00000001 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000214, 1, 0x04, 0x00000080 }, + { 0x000218, 2, 0x04, 0x00000100 }, + { 0x000220, 2, 0x04, 0x00000000 }, + { 0x000230, 1, 0x04, 0x000000cf }, + { 0x000234, 1, 0x04, 0x00000001 }, + { 0x000238, 1, 0x04, 0x00000020 }, + { 0x00023c, 1, 0x04, 0x00000001 }, + { 0x000244, 1, 0x04, 0x00000080 }, + { 0x000248, 2, 0x04, 0x00000100 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_9039_0[] = { + { 0x00030c, 3, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000238, 2, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_90c0_0[] = { + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x000758, 1, 0x04, 0x00000100 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x000204, 3, 0x04, 0x00000000 }, + { 0x000214, 1, 0x04, 0x00000000 }, + { 0x00024c, 1, 0x04, 0x00000000 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvc0_grctx_pack_mthd[] = { + { nvc0_grctx_init_9097_0, 0x9097 }, + { nvc0_grctx_init_902d_0, 0x902d }, + { nvc0_grctx_init_9039_0, 0x9039 }, + { nvc0_grctx_init_90c0_0, 0x90c0 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_main_0[] = { + { 0x400204, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_fe_0[] = { + { 0x404004, 11, 0x04, 0x00000000 }, + { 0x404044, 1, 0x04, 0x00000000 }, + { 0x404094, 13, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf0000087 }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x404168, 1, 0x04, 0x00000000 }, + { 0x404174, 3, 0x04, 0x00000000 }, + { 0x404200, 8, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_pri_0[] = { + { 0x404404, 14, 0x04, 0x00000000 }, + { 0x404460, 2, 0x04, 0x00000000 }, + { 0x404468, 1, 0x04, 0x00ffffff }, + { 0x40446c, 1, 0x04, 0x00000000 }, + { 0x404480, 1, 0x04, 0x00000001 }, + { 0x404498, 1, 0x04, 0x00000001 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_memfmt_0[] = { + { 0x404604, 1, 0x04, 0x00000015 }, + { 0x404608, 1, 0x04, 0x00000000 }, + { 0x40460c, 1, 0x04, 0x00002e00 }, + { 0x404610, 1, 0x04, 0x00000100 }, + { 0x404618, 8, 0x04, 0x00000000 }, + { 0x404638, 1, 0x04, 0x00000004 }, + { 0x40463c, 8, 0x04, 0x00000000 }, + { 0x40465c, 1, 0x04, 0x007f0100 }, + { 0x404660, 7, 0x04, 0x00000000 }, + { 0x40467c, 1, 0x04, 0x00000002 }, + { 0x404680, 8, 0x04, 0x00000000 }, + { 0x4046a0, 1, 0x04, 0x007f0080 }, + { 0x4046a4, 18, 0x04, 0x00000000 }, + { 0x4046f0, 2, 0x04, 0x00000000 }, + { 0x404700, 13, 0x04, 0x00000000 }, + { 0x404734, 1, 0x04, 0x00000100 }, + { 0x404738, 8, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x078000bf }, + { 0x405830, 1, 0x04, 0x02180000 }, + { 0x405834, 2, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x000103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_rstr2d_0[] = { + { 0x407804, 1, 0x04, 0x00000023 }, + { 0x40780c, 1, 0x04, 0x0a418820 }, + { 0x407810, 1, 0x04, 0x062080e6 }, + { 0x407814, 1, 0x04, 0x020398a4 }, + { 0x407818, 1, 0x04, 0x0e629062 }, + { 0x40781c, 1, 0x04, 0x0a418820 }, + { 0x407820, 1, 0x04, 0x000000e6 }, + { 0x4078bc, 1, 0x04, 0x00000103 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_scc_0[] = { + { 0x408000, 2, 0x04, 0x00000000 }, + { 0x408008, 1, 0x04, 0x00000018 }, + { 0x40800c, 2, 0x04, 0x00000000 }, + { 0x408014, 1, 0x04, 0x00000069 }, + { 0x408018, 1, 0x04, 0xe100e100 }, + { 0x408064, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x0003e00d }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x02000001 }, + { 0x408908, 1, 0x04, 0x00c80929 }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +const struct nvc0_gr_pack +nvc0_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nvc0_grctx_init_fe_0 }, + { nvc0_grctx_init_pri_0 }, + { nvc0_grctx_init_memfmt_0 }, + { nvc0_grctx_init_ds_0 }, + { nvc0_grctx_init_pd_0 }, + { nvc0_grctx_init_rstr2d_0 }, + { nvc0_grctx_init_scc_0 }, + { nvc0_grctx_init_be_0 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_gpc_unk_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_prop_0[] = { + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x00200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_gpc_unk_1[] = { + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 1, 0x04, 0x00000000 }, + { 0x41870c, 1, 0x04, 0x07c80000 }, + { 0x418710, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x0006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x00000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x00100000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_zcull_0[] = { + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_crstr_0[] = { + { 0x418b00, 1, 0x04, 0x00000000 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_gpm_0[] = { + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_gcc_0[] = { + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +const struct nvc0_gr_pack +nvc0_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvc0_grctx_init_prop_0 }, + { nvc0_grctx_init_gpc_unk_1 }, + { nvc0_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvc0_grctx_init_crstr_0 }, + { nvc0_grctx_init_gpm_0 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_zcullr_0[] = { + { 0x418a00, 3, 0x04, 0x00000000 }, + { 0x418a0c, 1, 0x04, 0x00010000 }, + { 0x418a10, 3, 0x04, 0x00000000 }, + { 0x418a20, 3, 0x04, 0x00000000 }, + { 0x418a2c, 1, 0x04, 0x00010000 }, + { 0x418a30, 3, 0x04, 0x00000000 }, + { 0x418a40, 3, 0x04, 0x00000000 }, + { 0x418a4c, 1, 0x04, 0x00010000 }, + { 0x418a50, 3, 0x04, 0x00000000 }, + { 0x418a60, 3, 0x04, 0x00000000 }, + { 0x418a6c, 1, 0x04, 0x00010000 }, + { 0x418a70, 3, 0x04, 0x00000000 }, + { 0x418a80, 3, 0x04, 0x00000000 }, + { 0x418a8c, 1, 0x04, 0x00010000 }, + { 0x418a90, 3, 0x04, 0x00000000 }, + { 0x418aa0, 3, 0x04, 0x00000000 }, + { 0x418aac, 1, 0x04, 0x00010000 }, + { 0x418ab0, 3, 0x04, 0x00000000 }, + { 0x418ac0, 3, 0x04, 0x00000000 }, + { 0x418acc, 1, 0x04, 0x00010000 }, + { 0x418ad0, 3, 0x04, 0x00000000 }, + { 0x418ae0, 3, 0x04, 0x00000000 }, + { 0x418aec, 1, 0x04, 0x00010000 }, + { 0x418af0, 3, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvc0_grctx_pack_zcull[] = { + { nvc0_grctx_init_zcullr_0 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_pe_0[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x0000012a }, + { 0x419888, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_wwdx_0[] = { + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00000001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_mpc_0[] = { + { 0x419c00, 1, 0x04, 0x00000002 }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_l1c_0[] = { + { 0x419cb0, 1, 0x04, 0x00060048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + {} +}; + +const struct nvc0_gr_init +nvc0_grctx_init_tpccs_0[] = { + { 0x419d20, 1, 0x04, 0x02180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + {} +}; + +static const struct nvc0_gr_init +nvc0_grctx_init_sm_0[] = { + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419f50, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvc0_grctx_pack_tpc[] = { + { nvc0_grctx_init_pe_0 }, + { nvc0_grctx_init_tex_0 }, + { nvc0_grctx_init_wwdx_0 }, + { nvc0_grctx_init_mpc_0 }, + { nvc0_grctx_init_l1c_0 }, + { nvc0_grctx_init_tpccs_0 }, + { nvc0_grctx_init_sm_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +int +nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) +{ + if (info->data) { + info->buffer[info->buffer_nr] = round_up(info->addr, align); + info->addr = info->buffer[info->buffer_nr] + size; + info->data->size = size; + info->data->align = align; + info->data->access = access; + info->data++; + return info->buffer_nr++; + } + return -1; +} + +void +nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, + int shift, int buffer) +{ + if (info->data) { + if (shift >= 0) { + info->mmio->addr = addr; + info->mmio->data = data; + info->mmio->shift = shift; + info->mmio->buffer = buffer; + if (buffer >= 0) + data |= info->buffer[buffer] >> shift; + info->mmio++; + } else + return; + } else { + if (buffer >= 0) + return; + } + + nv_wr32(info->priv, addr, data); +} + +void +nvc0_grctx_generate_bundle(struct nvc0_grctx *info) +{ + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; + const int s = 8; + const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); + mmio_refn(info, 0x408004, 0x00000000, s, b); + mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); + mmio_refn(info, 0x418808, 0x00000000, s, b); + mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); +} + +void +nvc0_grctx_generate_pagepool(struct nvc0_grctx *info) +{ + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; + const int s = 8; + const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); + mmio_refn(info, 0x40800c, 0x00000000, s, b); + mmio_wr32(info, 0x408010, 0x80000000); + mmio_refn(info, 0x419004, 0x00000000, s, b); + mmio_wr32(info, 0x419008, 0x00000000); +} + +void +nvc0_grctx_generate_attrib(struct nvc0_grctx *info) +{ + struct nvc0_gr_priv *priv = info->priv; + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); + const u32 attrib = impl->attrib_nr; + const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const u32 access = NV_MEM_ACCESS_RW; + const int s = 12; + const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + int gpc, tpc; + u32 bo = 0; + + mmio_refn(info, 0x418810, 0x80000000, s, b); + mmio_refn(info, 0x419848, 0x10000000, s, b); + mmio_wr32(info, 0x405830, (attrib << 16)); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + const u32 o = TPC_UNIT(gpc, tpc, 0x0520); + mmio_skip(info, o, (attrib << 16) | ++bo); + mmio_wr32(info, o, (attrib << 16) | --bo); + bo += impl->attrib_nr_max; + } + } +} + +void +nvc0_grctx_generate_unkn(struct nvc0_gr_priv *priv) +{ +} + +void +nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *priv) +{ + int gpc, tpc, id; + + for (tpc = 0, id = 0; tpc < 4; tpc++) { + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + if (tpc < priv->tpc_nr[gpc]) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); + id++; + } + + nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); + } + } +} + +void +nvc0_grctx_generate_r406028(struct nvc0_gr_priv *priv) +{ + u32 tmp[GPC_MAX / 8] = {}, i = 0; + for (i = 0; i < priv->gpc_nr; i++) + tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4); + for (i = 0; i < 4; i++) { + nv_wr32(priv, 0x406028 + (i * 4), tmp[i]); + nv_wr32(priv, 0x405870 + (i * 4), tmp[i]); + } +} + +void +nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *priv) +{ + u8 tpcnr[GPC_MAX], data[TPC_MAX]; + int gpc, tpc, i; + + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + memset(data, 0x1f, sizeof(data)); + + gpc = -1; + for (tpc = 0; tpc < priv->tpc_total; tpc++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpcnr[gpc]--; + data[tpc] = gpc; + } + + for (i = 0; i < 4; i++) + nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); +} + +void +nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *priv) +{ + u32 data[6] = {}, data2[2] = {}; + u8 tpcnr[GPC_MAX]; + u8 shift, ntpcv; + int gpc, tpc, i; + + /* calculate first set of magics */ + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + + gpc = -1; + for (tpc = 0; tpc < priv->tpc_total; tpc++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpcnr[gpc]--; + + data[tpc / 6] |= gpc << ((tpc % 6) * 5); + } + + for (; tpc < 32; tpc++) + data[tpc / 6] |= 7 << ((tpc % 6) * 5); + + /* and the second... */ + shift = 0; + ntpcv = priv->tpc_total; + while (!(ntpcv & (1 << 4))) { + ntpcv <<= 1; + shift++; + } + + data2[0] = (ntpcv << 16); + data2[0] |= (shift << 21); + data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); + for (i = 1; i < 7; i++) + data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); + + /* GPC_BROADCAST */ + nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x418b08 + (i * 4), data[i]); + + /* GPC_BROADCAST.TP_BROADCAST */ + nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) | + priv->magic_not_rop_nr | data2[0]); + nv_wr32(priv, 0x419be4, data2[1]); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x419b00 + (i * 4), data[i]); + + /* UNK78xx */ + nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x40780c + (i * 4), data[i]); +} + +void +nvc0_grctx_generate_r406800(struct nvc0_gr_priv *priv) +{ + u64 tpc_mask = 0, tpc_set = 0; + u8 tpcnr[GPC_MAX]; + int gpc, tpc; + int i, a, b; + + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (gpc = 0; gpc < priv->gpc_nr; gpc++) + tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8); + + for (i = 0, gpc = -1, b = -1; i < 32; i++) { + a = (i * (priv->tpc_total - 1)) / 32; + if (a != b) { + b = a; + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + tpc_set |= 1ULL << ((gpc * 8) + tpc); + } + + nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); + nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); + if (priv->gpc_nr > 4) { + nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); + nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); + } + } +} + +void +nvc0_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + + nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + + nvc0_gr_mmio(priv, oclass->hub); + nvc0_gr_mmio(priv, oclass->gpc); + nvc0_gr_mmio(priv, oclass->zcull); + nvc0_gr_mmio(priv, oclass->tpc); + nvc0_gr_mmio(priv, oclass->ppc); + + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->bundle(info); + oclass->pagepool(info); + oclass->attrib(info); + oclass->unkn(priv); + + nvc0_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nvc0_grctx_generate_r4060a8(priv); + nvc0_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + nvc0_gr_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_gr_mthd(priv, oclass->mthd); + nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +} + +int +nvc0_grctx_generate(struct nvc0_gr_priv *priv) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct nouveau_bar *bar = nouveau_bar(priv); + struct nouveau_gpuobj *chan; + struct nvc0_grctx info; + int ret, i; + + /* allocate memory to for a "channel", which we'll use to generate + * the default context values + */ + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); + if (ret) { + nv_error(priv, "failed to allocate channel memory, %d\n", ret); + return ret; + } + + /* PGD pointer */ + nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); + nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); + nv_wo32(chan, 0x0208, 0xffffffff); + nv_wo32(chan, 0x020c, 0x000000ff); + + /* PGT[0] pointer */ + nv_wo32(chan, 0x1000, 0x00000000); + nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); + + /* identity-map the whole "channel" into its own vm */ + for (i = 0; i < chan->size / 4096; i++) { + u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; + nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); + nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); + } + + /* context pointer (virt) */ + nv_wo32(chan, 0x0210, 0x00080004); + nv_wo32(chan, 0x0214, 0x00000000); + + bar->flush(bar); + + nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); + nv_wr32(priv, 0x100cbc, 0x80000001); + nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); + + /* setup default state for mmio list construction */ + info.priv = priv; + info.data = priv->mmio_data; + info.mmio = priv->mmio_list; + info.addr = 0x2000 + (i * 8); + info.buffer_nr = 0; + + /* make channel current */ + if (priv->firmware) { + nv_wr32(priv, 0x409840, 0x00000030); + nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); + nv_wr32(priv, 0x409504, 0x00000003); + if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) + nv_error(priv, "load_ctx timeout\n"); + + nv_wo32(chan, 0x8001c, 1); + nv_wo32(chan, 0x80020, 0); + nv_wo32(chan, 0x80028, 0); + nv_wo32(chan, 0x8002c, 0); + bar->flush(bar); + } else { + nv_wr32(priv, 0x409840, 0x80000000); + nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); + nv_wr32(priv, 0x409504, 0x00000001); + if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) + nv_error(priv, "HUB_SET_CHAN timeout\n"); + } + + oclass->main(priv, &info); + + /* trigger a context unload by unsetting the "next channel valid" bit + * and faking a context switch interrupt + */ + nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); + nv_wr32(priv, 0x409000, 0x00000100); + if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) { + nv_error(priv, "grctx template channel unload timeout\n"); + ret = -EBUSY; + goto done; + } + + priv->data = kmalloc(priv->size, GFP_KERNEL); + if (priv->data) { + for (i = 0; i < priv->size; i += 4) + priv->data[i / 4] = nv_ro32(chan, 0x80000 + i); + ret = 0; + } else { + ret = -ENOMEM; + } + +done: + nouveau_gpuobj_ref(NULL, &chan); + return ret; +} + +struct nouveau_oclass * +nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .unkn = nvc0_grctx_generate_unkn, + .hub = nvc0_grctx_pack_hub, + .gpc = nvc0_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvc0_grctx_pack_tpc, + .icmd = nvc0_grctx_pack_icmd, + .mthd = nvc0_grctx_pack_mthd, + .bundle = nvc0_grctx_generate_bundle, + .bundle_size = 0x1800, + .pagepool = nvc0_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvc0_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h new file mode 100644 index 000000000000..0dbcd5839252 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h @@ -0,0 +1,202 @@ +#ifndef __NVKM_GRCTX_NVC0_H__ +#define __NVKM_GRCTX_NVC0_H__ + +#include "nvc0.h" + +struct nvc0_grctx { + struct nvc0_gr_priv *priv; + struct nvc0_gr_data *data; + struct nvc0_gr_mmio *mmio; + int buffer_nr; + u64 buffer[4]; + u64 addr; +}; + +int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access); +void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int); + +#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d)) +#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e)) +#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) +#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1) + +struct nvc0_grctx_oclass { + struct nouveau_oclass base; + /* main context generation function */ + void (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *); + /* context-specific modify-on-first-load list generation function */ + void (*unkn)(struct nvc0_gr_priv *); + /* mmio context data */ + const struct nvc0_gr_pack *hub; + const struct nvc0_gr_pack *gpc; + const struct nvc0_gr_pack *zcull; + const struct nvc0_gr_pack *tpc; + const struct nvc0_gr_pack *ppc; + /* indirect context data, generated with icmds/mthds */ + const struct nvc0_gr_pack *icmd; + const struct nvc0_gr_pack *mthd; + /* bundle circular buffer */ + void (*bundle)(struct nvc0_grctx *); + u32 bundle_size; + u32 bundle_min_gpm_fifo_depth; + u32 bundle_token_limit; + /* pagepool */ + void (*pagepool)(struct nvc0_grctx *); + u32 pagepool_size; + /* attribute(/alpha) circular buffer */ + void (*attrib)(struct nvc0_grctx *); + u32 attrib_nr_max; + u32 attrib_nr; + u32 alpha_nr_max; + u32 alpha_nr; +}; + +static inline const struct nvc0_grctx_oclass * +nvc0_grctx_impl(struct nvc0_gr_priv *priv) +{ + return (void *)nv_engine(priv)->cclass; +} + +extern struct nouveau_oclass *nvc0_grctx_oclass; +int nvc0_grctx_generate(struct nvc0_gr_priv *); +void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *); +void nvc0_grctx_generate_bundle(struct nvc0_grctx *); +void nvc0_grctx_generate_pagepool(struct nvc0_grctx *); +void nvc0_grctx_generate_attrib(struct nvc0_grctx *); +void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *); +void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *); +void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *); +void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *); +void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *); +void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *); + +extern struct nouveau_oclass *nvc1_grctx_oclass; +void nvc1_grctx_generate_attrib(struct nvc0_grctx *); +void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *); + +extern struct nouveau_oclass *nvc4_grctx_oclass; +extern struct nouveau_oclass *nvc8_grctx_oclass; + +extern struct nouveau_oclass *nvd7_grctx_oclass; +void nvd7_grctx_generate_attrib(struct nvc0_grctx *); + +extern struct nouveau_oclass *nvd9_grctx_oclass; + +extern struct nouveau_oclass *nve4_grctx_oclass; +extern struct nouveau_oclass *gk20a_grctx_oclass; +void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *); +void nve4_grctx_generate_bundle(struct nvc0_grctx *); +void nve4_grctx_generate_pagepool(struct nvc0_grctx *); +void nve4_grctx_generate_unkn(struct nvc0_gr_priv *); +void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *); + +extern struct nouveau_oclass *nvf0_grctx_oclass; +extern struct nouveau_oclass *gk110b_grctx_oclass; +extern struct nouveau_oclass *nv108_grctx_oclass; +extern struct nouveau_oclass *gm107_grctx_oclass; + +/* context init value lists */ + +extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[]; + +extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[]; +extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[]; + +extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[]; +extern const struct nvc0_gr_init nvc0_grctx_init_main_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[]; + +extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[]; +extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[]; +extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[]; + +extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[]; + +extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[]; +extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[]; +extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[]; + +extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[]; +extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[]; +extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[]; + +extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[]; + +extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[]; + +extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[]; +extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[]; +extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[]; + +extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[]; +extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[]; + +extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[]; + +extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[]; + +extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[]; +extern const struct nvc0_gr_init nvd9_grctx_init_be_0[]; + +extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[]; +extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[]; +extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[]; + +extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[]; + +extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[]; + +extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[]; + +extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[]; +extern const struct nvc0_gr_init nve4_grctx_init_ds_0[]; +extern const struct nvc0_gr_init nve4_grctx_init_scc_0[]; + +extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[]; + +extern const struct nvc0_gr_init nve4_grctx_init_pes_0[]; + +extern const struct nvc0_gr_pack nve4_grctx_pack_hub[]; +extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[]; +extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[]; +extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[]; +extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[]; +extern const struct nvc0_gr_init nve4_grctx_init_a097_0[]; + +extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[]; + +extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[]; + +extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[]; +extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[]; +extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[]; + +extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[]; +extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[]; + +extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[]; +extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[]; +extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[]; + +extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[]; + +extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[]; + +extern const struct nvc0_gr_init nv108_grctx_init_prop_0[]; +extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[]; + + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c new file mode 100644 index 000000000000..b5ced99abce9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c @@ -0,0 +1,805 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvc1_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_pack +nvc1_grctx_pack_icmd[] = { + { nvc1_grctx_init_icmd_0 }, + {} +}; + +const struct nvc0_gr_init +nvc1_grctx_init_9097_0[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x002700, 8, 0x20, 0x00000000 }, + { 0x002704, 8, 0x20, 0x00000000 }, + { 0x002708, 8, 0x20, 0x00000000 }, + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x002710, 8, 0x20, 0x00014000 }, + { 0x002714, 8, 0x20, 0x00000040 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002200, 5, 0x10, 0x00000022 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00001fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x003fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 4, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 1, 0x04, 0x003fffff }, + { 0x0002d0, 1, 0x04, 0x00000c48 }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00300008 }, + { 0x001284, 1, 0x04, 0x04000080 }, + { 0x001450, 1, 0x04, 0x00300008 }, + { 0x001454, 1, 0x04, 0x04000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc1_grctx_init_9197_0[] = { + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x0002e4, 1, 0x04, 0x0000b001 }, + {} +}; + +static const struct nvc0_gr_pack +nvc1_grctx_pack_mthd[] = { + { nvc1_grctx_init_9097_0, 0x9097 }, + { nvc1_grctx_init_9197_0, 0x9197 }, + { nvc0_grctx_init_902d_0, 0x902d }, + { nvc0_grctx_init_9039_0, 0x9039 }, + { nvc0_grctx_init_90c0_0, 0x90c0 }, + {} +}; + +static const struct nvc0_gr_init +nvc1_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180218 }, + { 0x405834, 2, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc1_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x000103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 2, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x80140078 }, + { 0x4064c4, 1, 0x04, 0x0086ffff }, + {} +}; + +static const struct nvc0_gr_init +nvc1_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1003e005 }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c80929 }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static const struct nvc0_gr_pack +nvc1_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nvc0_grctx_init_fe_0 }, + { nvc0_grctx_init_pri_0 }, + { nvc0_grctx_init_memfmt_0 }, + { nvc1_grctx_init_ds_0 }, + { nvc1_grctx_init_pd_0 }, + { nvc0_grctx_init_rstr2d_0 }, + { nvc0_grctx_init_scc_0 }, + { nvc1_grctx_init_be_0 }, + {} +}; + +static const struct nvc0_gr_init +nvc1_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x0006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x00100018 }, + {} +}; + +const struct nvc0_gr_init +nvc1_grctx_init_gpm_0[] = { + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_pack +nvc1_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvc0_grctx_init_prop_0 }, + { nvc0_grctx_init_gpc_unk_1 }, + { nvc1_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvc0_grctx_init_crstr_0 }, + { nvc1_grctx_init_gpm_0 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +const struct nvc0_gr_init +nvc1_grctx_init_pe_0[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc1_grctx_init_wwdx_0[] = { + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00400001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc1_grctx_init_tpccs_0[] = { + { 0x419d20, 1, 0x04, 0x12180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + { 0x419d44, 1, 0x04, 0x02180218 }, + {} +}; + +static const struct nvc0_gr_pack +nvc1_grctx_pack_tpc[] = { + { nvc1_grctx_init_pe_0 }, + { nvc4_grctx_init_tex_0 }, + { nvc1_grctx_init_wwdx_0 }, + { nvc0_grctx_init_mpc_0 }, + { nvc4_grctx_init_l1c_0 }, + { nvc1_grctx_init_tpccs_0 }, + { nvc4_grctx_init_sm_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +void +nvc1_grctx_generate_attrib(struct nvc0_grctx *info) +{ + struct nvc0_gr_priv *priv = info->priv; + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); + const u32 alpha = impl->alpha_nr; + const u32 beta = impl->attrib_nr; + const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const u32 access = NV_MEM_ACCESS_RW; + const int s = 12; + const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int timeslice_mode = 1; + const int max_batches = 0xffff; + u32 bo = 0; + u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; + int gpc, tpc; + + mmio_refn(info, 0x418810, 0x80000000, s, b); + mmio_refn(info, 0x419848, 0x10000000, s, b); + mmio_wr32(info, 0x405830, (beta << 16) | alpha); + mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + const u32 a = alpha; + const u32 b = beta; + const u32 t = timeslice_mode; + const u32 o = TPC_UNIT(gpc, tpc, 0x500); + mmio_skip(info, o + 0x20, (t << 28) | (b << 16) | ++bo); + mmio_wr32(info, o + 0x20, (t << 28) | (b << 16) | --bo); + bo += impl->attrib_nr_max; + mmio_wr32(info, o + 0x44, (a << 16) | ao); + ao += impl->alpha_nr_max; + } + } +} + +void +nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv) +{ + nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); + nv_mask(priv, 0x419814, 0x00000004, 0x00000004); + nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(priv, 0x405800, 0x08000000, 0x08000000); + nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +} + +struct nouveau_oclass * +nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc1), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .unkn = nvc1_grctx_generate_unkn, + .hub = nvc1_grctx_pack_hub, + .gpc = nvc1_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvc1_grctx_pack_tpc, + .icmd = nvc1_grctx_pack_icmd, + .mthd = nvc1_grctx_pack_mthd, + .bundle = nvc0_grctx_generate_bundle, + .bundle_size = 0x1800, + .pagepool = nvc0_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvc1_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x324, + .alpha_nr = 0x218, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c new file mode 100644 index 000000000000..c883e7229fd5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c @@ -0,0 +1,109 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nvc4_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00000000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0007f440 }, + {} +}; + +const struct nvc0_gr_init +nvc4_grctx_init_l1c_0[] = { + { 0x419cb0, 1, 0x04, 0x00020048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + {} +}; + +const struct nvc0_gr_init +nvc4_grctx_init_sm_0[] = { + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00011110 }, + { 0x419f30, 11, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvc4_grctx_pack_tpc[] = { + { nvc0_grctx_init_pe_0 }, + { nvc4_grctx_init_tex_0 }, + { nvc0_grctx_init_wwdx_0 }, + { nvc0_grctx_init_mpc_0 }, + { nvc4_grctx_init_l1c_0 }, + { nvc0_grctx_init_tpccs_0 }, + { nvc4_grctx_init_sm_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +struct nouveau_oclass * +nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc3), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .unkn = nvc0_grctx_generate_unkn, + .hub = nvc0_grctx_pack_hub, + .gpc = nvc0_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvc4_grctx_pack_tpc, + .icmd = nvc0_grctx_pack_icmd, + .mthd = nvc0_grctx_pack_mthd, + .bundle = nvc0_grctx_generate_bundle, + .bundle_size = 0x1800, + .pagepool = nvc0_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvc0_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c new file mode 100644 index 000000000000..4876a9375803 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c @@ -0,0 +1,360 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvc8_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_pack +nvc8_grctx_pack_icmd[] = { + { nvc8_grctx_init_icmd_0 }, + {} +}; + +const struct nvc0_gr_init +nvc8_grctx_init_9197_0[] = { + { 0x0002e4, 1, 0x04, 0x0000b001 }, + {} +}; + +const struct nvc0_gr_init +nvc8_grctx_init_9297_0[] = { + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00036c, 2, 0x04, 0x00000000 }, + { 0x0007a4, 2, 0x04, 0x00000000 }, + { 0x000374, 1, 0x04, 0x00000000 }, + { 0x000378, 1, 0x04, 0x00000020 }, + {} +}; + +static const struct nvc0_gr_pack +nvc8_grctx_pack_mthd[] = { + { nvc1_grctx_init_9097_0, 0x9097 }, + { nvc8_grctx_init_9197_0, 0x9197 }, + { nvc8_grctx_init_9297_0, 0x9297 }, + { nvc0_grctx_init_902d_0, 0x902d }, + { nvc0_grctx_init_9039_0, 0x9039 }, + { nvc0_grctx_init_90c0_0, 0x90c0 }, + {} +}; + +static const struct nvc0_gr_init +nvc8_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x0006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x00000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100000 }, + {} +}; + +static const struct nvc0_gr_pack +nvc8_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvc0_grctx_init_prop_0 }, + { nvc0_grctx_init_gpc_unk_1 }, + { nvc8_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvc0_grctx_init_crstr_0 }, + { nvc0_grctx_init_gpm_0 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +struct nouveau_oclass * +nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc8), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .unkn = nvc0_grctx_generate_unkn, + .hub = nvc0_grctx_pack_hub, + .gpc = nvc8_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvc0_grctx_pack_tpc, + .icmd = nvc8_grctx_pack_icmd, + .mthd = nvc8_grctx_pack_mthd, + .bundle = nvc0_grctx_generate_bundle, + .bundle_size = 0x1800, + .pagepool = nvc0_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvc0_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c new file mode 100644 index 000000000000..b53896c511d9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c @@ -0,0 +1,282 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvd7_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180324 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd7_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x000103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x801a0078 }, + { 0x4064c4, 1, 0x04, 0x00c9ffff }, + { 0x4064d0, 8, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvd7_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nvd9_grctx_init_fe_0 }, + { nvc0_grctx_init_pri_0 }, + { nvc0_grctx_init_memfmt_0 }, + { nvd7_grctx_init_ds_0 }, + { nvd7_grctx_init_pd_0 }, + { nvc0_grctx_init_rstr2d_0 }, + { nvc0_grctx_init_scc_0 }, + { nvd9_grctx_init_be_0 }, + {} +}; + +static const struct nvc0_gr_init +nvd7_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100018 }, + {} +}; + +static const struct nvc0_gr_pack +nvd7_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvd9_grctx_init_prop_0 }, + { nvd9_grctx_init_gpc_unk_1 }, + { nvd7_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvd9_grctx_init_crstr_0 }, + { nvc1_grctx_init_gpm_0 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +const struct nvc0_gr_init +nvd7_grctx_init_pe_0[] = { + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd7_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00008000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0017f440 }, + {} +}; + +static const struct nvc0_gr_init +nvd7_grctx_init_mpc_0[] = { + { 0x419c00, 1, 0x04, 0x0000000a }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + {} +}; + +static const struct nvc0_gr_pack +nvd7_grctx_pack_tpc[] = { + { nvd7_grctx_init_pe_0 }, + { nvd7_grctx_init_tex_0 }, + { nvd7_grctx_init_mpc_0 }, + { nvc4_grctx_init_l1c_0 }, + { nvd9_grctx_init_sm_0 }, + {} +}; + +static const struct nvc0_gr_init +nvd7_grctx_init_pes_0[] = { + { 0x41be24, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_init +nvd7_grctx_init_cbm_0[] = { + { 0x41bec0, 1, 0x04, 0x12180000 }, + { 0x41bec4, 1, 0x04, 0x00003fff }, + { 0x41bee4, 1, 0x04, 0x03240218 }, + {} +}; + +const struct nvc0_gr_init +nvd7_grctx_init_wwdx_0[] = { + { 0x41bf00, 1, 0x04, 0x0a418820 }, + { 0x41bf04, 1, 0x04, 0x062080e6 }, + { 0x41bf08, 1, 0x04, 0x020398a4 }, + { 0x41bf0c, 1, 0x04, 0x0e629062 }, + { 0x41bf10, 1, 0x04, 0x0a418820 }, + { 0x41bf14, 1, 0x04, 0x000000e6 }, + { 0x41bfd0, 1, 0x04, 0x00900103 }, + { 0x41bfe0, 1, 0x04, 0x00400001 }, + { 0x41bfe4, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvd7_grctx_pack_ppc[] = { + { nvd7_grctx_init_pes_0 }, + { nvd7_grctx_init_cbm_0 }, + { nvd7_grctx_init_wwdx_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +void +nvd7_grctx_generate_attrib(struct nvc0_grctx *info) +{ + struct nvc0_gr_priv *priv = info->priv; + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); + const u32 alpha = impl->alpha_nr; + const u32 beta = impl->attrib_nr; + const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const u32 access = NV_MEM_ACCESS_RW; + const int s = 12; + const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int timeslice_mode = 1; + const int max_batches = 0xffff; + u32 bo = 0; + u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; + int gpc, ppc; + + mmio_refn(info, 0x418810, 0x80000000, s, b); + mmio_refn(info, 0x419848, 0x10000000, s, b); + mmio_wr32(info, 0x405830, (beta << 16) | alpha); + mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) { + const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc]; + const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc]; + const u32 t = timeslice_mode; + const u32 o = PPC_UNIT(gpc, ppc, 0); + mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); + mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); + bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + mmio_wr32(info, o + 0xe4, (a << 16) | ao); + ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + } + } +} + +void +nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int i; + + nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + + nvc0_gr_mmio(priv, oclass->hub); + nvc0_gr_mmio(priv, oclass->gpc); + nvc0_gr_mmio(priv, oclass->zcull); + nvc0_gr_mmio(priv, oclass->tpc); + nvc0_gr_mmio(priv, oclass->ppc); + + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->bundle(info); + oclass->pagepool(info); + oclass->attrib(info); + oclass->unkn(priv); + + nvc0_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nvc0_grctx_generate_r4060a8(priv); + nve4_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + + nvc0_gr_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_gr_mthd(priv, oclass->mthd); + nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +} + +struct nouveau_oclass * +nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xd7), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nvd7_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = nvd7_grctx_pack_hub, + .gpc = nvd7_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvd7_grctx_pack_tpc, + .ppc = nvd7_grctx_pack_ppc, + .icmd = nvd9_grctx_pack_icmd, + .mthd = nvd9_grctx_pack_mthd, + .bundle = nvc0_grctx_generate_bundle, + .bundle_size = 0x1800, + .pagepool = nvc0_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvd7_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x7ff, + .alpha_nr = 0x324, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c new file mode 100644 index 000000000000..adc69e247bf2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c @@ -0,0 +1,530 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvd9_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000400, 24, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x000440, 24, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +const struct nvc0_gr_pack +nvd9_grctx_pack_icmd[] = { + { nvd9_grctx_init_icmd_0 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_grctx_init_90c0_0[] = { + { 0x002700, 8, 0x20, 0x00000000 }, + { 0x002704, 8, 0x20, 0x00000000 }, + { 0x002708, 8, 0x20, 0x00000000 }, + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x002710, 8, 0x20, 0x00014000 }, + { 0x002714, 8, 0x20, 0x00000040 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x000758, 1, 0x04, 0x00000100 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x000204, 3, 0x04, 0x00000000 }, + { 0x000214, 1, 0x04, 0x00000000 }, + { 0x00024c, 1, 0x04, 0x00000000 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvd9_grctx_pack_mthd[] = { + { nvc1_grctx_init_9097_0, 0x9097 }, + { nvc8_grctx_init_9197_0, 0x9197 }, + { nvc8_grctx_init_9297_0, 0x9297 }, + { nvc0_grctx_init_902d_0, 0x902d }, + { nvc0_grctx_init_9039_0, 0x9039 }, + { nvd9_grctx_init_90c0_0, 0x90c0 }, + {} +}; + +const struct nvc0_gr_init +nvd9_grctx_init_fe_0[] = { + { 0x404004, 10, 0x04, 0x00000000 }, + { 0x404044, 1, 0x04, 0x00000000 }, + { 0x404094, 13, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf0000087 }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x404168, 1, 0x04, 0x00000000 }, + { 0x404178, 2, 0x04, 0x00000000 }, + { 0x404200, 8, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180218 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x000103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x80140078 }, + { 0x4064c4, 1, 0x04, 0x0086ffff }, + {} +}; + +const struct nvc0_gr_init +nvd9_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1043e005 }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static const struct nvc0_gr_pack +nvd9_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nvd9_grctx_init_fe_0 }, + { nvc0_grctx_init_pri_0 }, + { nvc0_grctx_init_memfmt_0 }, + { nvd9_grctx_init_ds_0 }, + { nvd9_grctx_init_pd_0 }, + { nvc0_grctx_init_rstr2d_0 }, + { nvc0_grctx_init_scc_0 }, + { nvd9_grctx_init_be_0 }, + {} +}; + +const struct nvc0_gr_init +nvd9_grctx_init_prop_0[] = { + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x02200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_grctx_init_gpc_unk_1[] = { + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 3, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100008 }, + {} +}; + +const struct nvc0_gr_init +nvd9_grctx_init_crstr_0[] = { + { 0x418b00, 1, 0x04, 0x00000006 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + {} +}; + +static const struct nvc0_gr_pack +nvd9_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvd9_grctx_init_prop_0 }, + { nvd9_grctx_init_gpc_unk_1 }, + { nvd9_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvd9_grctx_init_crstr_0 }, + { nvc1_grctx_init_gpm_0 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00000000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0017f440 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_grctx_init_mpc_0[] = { + { 0x419c00, 1, 0x04, 0x0000000a }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3cf3cf3c }, + {} +}; + +const struct nvc0_gr_init +nvd9_grctx_init_sm_0[] = { + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00010110 }, + { 0x419f30, 11, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvd9_grctx_pack_tpc[] = { + { nvc1_grctx_init_pe_0 }, + { nvd9_grctx_init_tex_0 }, + { nvc1_grctx_init_wwdx_0 }, + { nvd9_grctx_init_mpc_0 }, + { nvc4_grctx_init_l1c_0 }, + { nvc1_grctx_init_tpccs_0 }, + { nvd9_grctx_init_sm_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +struct nouveau_oclass * +nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xd9), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .unkn = nvc1_grctx_generate_unkn, + .hub = nvd9_grctx_pack_hub, + .gpc = nvd9_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvd9_grctx_pack_tpc, + .icmd = nvd9_grctx_pack_icmd, + .mthd = nvd9_grctx_pack_mthd, + .bundle = nvc0_grctx_generate_bundle, + .bundle_size = 0x1800, + .pagepool = nvc0_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvc1_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x324, + .alpha_nr = 0x218, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c new file mode 100644 index 000000000000..d78c7e7bbda0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c @@ -0,0 +1,1020 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nve4_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000383, 1, 0x01, 0x00000011 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x003fffff }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00400008 }, + { 0x000841, 1, 0x01, 0x08000080 }, + { 0x000842, 1, 0x01, 0x00400008 }, + { 0x000843, 1, 0x01, 0x08000080 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000008 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +const struct nvc0_gr_pack +nve4_grctx_pack_icmd[] = { + { nve4_grctx_init_icmd_0 }, + {} +}; + +const struct nvc0_gr_init +nve4_grctx_init_a097_0[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00000fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x000fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00260c, 1, 0x04, 0x00000000 }, + { 0x0007ac, 1, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x0002e4, 1, 0x04, 0x0000b001 }, + { 0x00036c, 2, 0x04, 0x00000000 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 4, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x0007a4, 2, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x000374, 1, 0x04, 0x00000000 }, + { 0x000378, 1, 0x04, 0x00000020 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 2, 0x04, 0x003fffff }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00400008 }, + { 0x001284, 1, 0x04, 0x08000080 }, + { 0x001450, 1, 0x04, 0x00400008 }, + { 0x001454, 1, 0x04, 0x08000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nve4_grctx_pack_mthd[] = { + { nve4_grctx_init_a097_0, 0xa097 }, + { nvc0_grctx_init_902d_0, 0x902d }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_fe_0[] = { + { 0x404010, 5, 0x04, 0x00000000 }, + { 0x404024, 1, 0x04, 0x0000e000 }, + { 0x404028, 1, 0x04, 0x00000000 }, + { 0x4040a8, 8, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf800008f }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x4041a0, 4, 0x04, 0x00000000 }, + { 0x404200, 4, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nve4_grctx_init_memfmt_0[] = { + { 0x404604, 1, 0x04, 0x00000014 }, + { 0x404608, 1, 0x04, 0x00000000 }, + { 0x40460c, 1, 0x04, 0x00003fff }, + { 0x404610, 1, 0x04, 0x00000100 }, + { 0x404618, 4, 0x04, 0x00000000 }, + { 0x40462c, 2, 0x04, 0x00000000 }, + { 0x404640, 1, 0x04, 0x00000000 }, + { 0x404654, 1, 0x04, 0x00000000 }, + { 0x404660, 1, 0x04, 0x00000000 }, + { 0x404678, 1, 0x04, 0x00000000 }, + { 0x40467c, 1, 0x04, 0x00000002 }, + { 0x404680, 8, 0x04, 0x00000000 }, + { 0x4046a0, 1, 0x04, 0x007f0080 }, + { 0x4046a4, 8, 0x04, 0x00000000 }, + { 0x4046c8, 3, 0x04, 0x00000000 }, + { 0x404700, 3, 0x04, 0x00000000 }, + { 0x404718, 7, 0x04, 0x00000000 }, + { 0x404734, 1, 0x04, 0x00000100 }, + { 0x404738, 2, 0x04, 0x00000000 }, + { 0x404744, 2, 0x04, 0x00000000 }, + { 0x404754, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nve4_grctx_init_ds_0[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180648 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_cwd_0[] = { + { 0x405b00, 1, 0x04, 0x00000000 }, + { 0x405b10, 1, 0x04, 0x00001000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x004103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 2, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x801a00f0 }, + { 0x4064c4, 1, 0x04, 0x0192ffff }, + { 0x4064c8, 1, 0x04, 0x01800600 }, + { 0x4064cc, 9, 0x04, 0x00000000 }, + { 0x4064fc, 1, 0x04, 0x0000022a }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_sked_0[] = { + { 0x407040, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nve4_grctx_init_scc_0[] = { + { 0x408000, 2, 0x04, 0x00000000 }, + { 0x408008, 1, 0x04, 0x00000030 }, + { 0x40800c, 2, 0x04, 0x00000000 }, + { 0x408014, 1, 0x04, 0x00000069 }, + { 0x408018, 1, 0x04, 0xe100e100 }, + { 0x408064, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1043e005 }, + { 0x408840, 1, 0x04, 0x0000000b }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +const struct nvc0_gr_pack +nve4_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nve4_grctx_init_fe_0 }, + { nvc0_grctx_init_pri_0 }, + { nve4_grctx_init_memfmt_0 }, + { nve4_grctx_init_ds_0 }, + { nve4_grctx_init_cwd_0 }, + { nve4_grctx_init_pd_0 }, + { nve4_grctx_init_sked_0 }, + { nvc0_grctx_init_rstr2d_0 }, + { nve4_grctx_init_scc_0 }, + { nve4_grctx_init_be_0 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00000044 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100018 }, + {} +}; + +const struct nvc0_gr_init +nve4_grctx_init_gpm_0[] = { + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c40, 1, 0x04, 0xffffffff }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + {} +}; + +const struct nvc0_gr_pack +nve4_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvd9_grctx_init_prop_0 }, + { nvd9_grctx_init_gpc_unk_1 }, + { nve4_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvd9_grctx_init_crstr_0 }, + { nve4_grctx_init_gpm_0 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000000f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000021 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x0000c000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419a30, 1, 0x04, 0x00000001 }, + { 0x419ac4, 1, 0x04, 0x0037f440 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_mpc_0[] = { + { 0x419c00, 1, 0x04, 0x0000000a }, + { 0x419c04, 1, 0x04, 0x80000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_l1c_0[] = { + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00003203 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_sm_0[] = { + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000402 }, + { 0x419e44, 1, 0x04, 0x0013eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 19, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x00001f8f }, + { 0x419eb0, 1, 0x04, 0x00000d3f }, + { 0x419ec8, 1, 0x04, 0x0001304f }, + { 0x419f30, 8, 0x04, 0x00000000 }, + { 0x419f58, 1, 0x04, 0x00000000 }, + { 0x419f70, 1, 0x04, 0x00000000 }, + { 0x419f78, 1, 0x04, 0x0000000b }, + { 0x419f7c, 1, 0x04, 0x0000027c }, + {} +}; + +const struct nvc0_gr_pack +nve4_grctx_pack_tpc[] = { + { nvd7_grctx_init_pe_0 }, + { nve4_grctx_init_tex_0 }, + { nve4_grctx_init_mpc_0 }, + { nve4_grctx_init_l1c_0 }, + { nve4_grctx_init_sm_0 }, + {} +}; + +const struct nvc0_gr_init +nve4_grctx_init_pes_0[] = { + { 0x41be24, 1, 0x04, 0x00000006 }, + {} +}; + +static const struct nvc0_gr_init +nve4_grctx_init_cbm_0[] = { + { 0x41bec0, 1, 0x04, 0x12180000 }, + { 0x41bec4, 1, 0x04, 0x00037f7f }, + { 0x41bee4, 1, 0x04, 0x06480430 }, + {} +}; + +const struct nvc0_gr_pack +nve4_grctx_pack_ppc[] = { + { nve4_grctx_init_pes_0 }, + { nve4_grctx_init_cbm_0 }, + { nvd7_grctx_init_wwdx_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +void +nve4_grctx_generate_bundle(struct nvc0_grctx *info) +{ + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, + impl->bundle_size / 0x20); + const u32 token_limit = impl->bundle_token_limit; + const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; + const int s = 8; + const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); + mmio_refn(info, 0x408004, 0x00000000, s, b); + mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); + mmio_refn(info, 0x418808, 0x00000000, s, b); + mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); + mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); +} + +void +nve4_grctx_generate_pagepool(struct nvc0_grctx *info) +{ + const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; + const int s = 8; + const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); + mmio_refn(info, 0x40800c, 0x00000000, s, b); + mmio_wr32(info, 0x408010, 0x80000000); + mmio_refn(info, 0x419004, 0x00000000, s, b); + mmio_wr32(info, 0x419008, 0x00000000); + mmio_wr32(info, 0x4064cc, 0x80000000); +} + +void +nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv) +{ + nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); + nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); + nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(priv, 0x405800, 0x08000000, 0x08000000); + nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +} + +void +nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv) +{ + u32 data[6] = {}, data2[2] = {}; + u8 tpcnr[GPC_MAX]; + u8 shift, ntpcv; + int gpc, tpc, i; + + /* calculate first set of magics */ + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + + gpc = -1; + for (tpc = 0; tpc < priv->tpc_total; tpc++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpcnr[gpc]--; + + data[tpc / 6] |= gpc << ((tpc % 6) * 5); + } + + for (; tpc < 32; tpc++) + data[tpc / 6] |= 7 << ((tpc % 6) * 5); + + /* and the second... */ + shift = 0; + ntpcv = priv->tpc_total; + while (!(ntpcv & (1 << 4))) { + ntpcv <<= 1; + shift++; + } + + data2[0] = (ntpcv << 16); + data2[0] |= (shift << 21); + data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); + for (i = 1; i < 7; i++) + data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); + + /* GPC_BROADCAST */ + nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x418b08 + (i * 4), data[i]); + + /* GPC_BROADCAST.TP_BROADCAST */ + nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) | + priv->magic_not_rop_nr | data2[0]); + nv_wr32(priv, 0x41bfe4, data2[1]); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); + + /* UNK78xx */ + nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x40780c + (i * 4), data[i]); +} + +void +nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int i; + + nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + + nvc0_gr_mmio(priv, oclass->hub); + nvc0_gr_mmio(priv, oclass->gpc); + nvc0_gr_mmio(priv, oclass->zcull); + nvc0_gr_mmio(priv, oclass->tpc); + nvc0_gr_mmio(priv, oclass->ppc); + + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->bundle(info); + oclass->pagepool(info); + oclass->attrib(info); + oclass->unkn(priv); + + nvc0_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nve4_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + + nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + if (priv->gpc_nr == 1) { + nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); + nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); + } else { + nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); + nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); + } + nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); + + nvc0_gr_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_gr_mthd(priv, oclass->mthd); + nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + + nv_mask(priv, 0x418800, 0x00200000, 0x00200000); + nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); +} + +struct nouveau_oclass * +nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xe4), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nve4_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = nve4_grctx_pack_hub, + .gpc = nve4_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nve4_grctx_pack_tpc, + .ppc = nve4_grctx_pack_ppc, + .icmd = nve4_grctx_pack_icmd, + .mthd = nve4_grctx_pack_mthd, + .bundle = nve4_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0x180, + .bundle_token_limit = 0x600, + .pagepool = nve4_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvd7_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x7ff, + .alpha_nr = 0x648, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c new file mode 100644 index 000000000000..f7444690b4d4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c @@ -0,0 +1,843 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH context register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvf0_grctx_init_icmd_0[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x0002f2, 2, 0x01, 0x00000001 }, + { 0x0002f5, 1, 0x01, 0x00000001 }, + { 0x0002f7, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000383, 1, 0x01, 0x00000011 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 2, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000662, 1, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x00080b, 1, 0x01, 0x00000002 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000a0d, 1, 0x01, 0x00000006 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x003fffff }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00400008 }, + { 0x000841, 1, 0x01, 0x08000080 }, + { 0x000842, 1, 0x01, 0x00400008 }, + { 0x000843, 1, 0x01, 0x08000080 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 3, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 3, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000008 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +const struct nvc0_gr_pack +nvf0_grctx_pack_icmd[] = { + { nvf0_grctx_init_icmd_0 }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_a197_0[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00000fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x000fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00260c, 1, 0x04, 0x00000000 }, + { 0x0007ac, 1, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x0002e4, 1, 0x04, 0x0000b001 }, + { 0x00036c, 2, 0x04, 0x00000000 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 4, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x0007a4, 2, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x000ddc, 1, 0x04, 0x00000002 }, + { 0x000374, 1, 0x04, 0x00000000 }, + { 0x000378, 1, 0x04, 0x00000020 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 2, 0x04, 0x003fffff }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00400008 }, + { 0x001284, 1, 0x04, 0x08000080 }, + { 0x001450, 1, 0x04, 0x00400008 }, + { 0x001454, 1, 0x04, 0x08000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvf0_grctx_pack_mthd[] = { + { nvf0_grctx_init_a197_0, 0xa197 }, + { nvc0_grctx_init_902d_0, 0x902d }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_fe_0[] = { + { 0x404004, 8, 0x04, 0x00000000 }, + { 0x404024, 1, 0x04, 0x0000e000 }, + { 0x404028, 8, 0x04, 0x00000000 }, + { 0x4040a8, 8, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf800008f }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404100, 10, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x40417c, 2, 0x04, 0x00000000 }, + { 0x4041a0, 4, 0x04, 0x00000000 }, + { 0x404200, 1, 0x04, 0x0000a197 }, + { 0x404204, 1, 0x04, 0x0000a1c0 }, + { 0x404208, 1, 0x04, 0x0000a140 }, + { 0x40420c, 1, 0x04, 0x0000902d }, + {} +}; + +const struct nvc0_gr_init +nvf0_grctx_init_pri_0[] = { + { 0x404404, 12, 0x04, 0x00000000 }, + { 0x404438, 1, 0x04, 0x00000000 }, + { 0x404460, 2, 0x04, 0x00000000 }, + { 0x404468, 1, 0x04, 0x00ffffff }, + { 0x40446c, 1, 0x04, 0x00000000 }, + { 0x404480, 1, 0x04, 0x00000001 }, + { 0x404498, 1, 0x04, 0x00000001 }, + {} +}; + +const struct nvc0_gr_init +nvf0_grctx_init_cwd_0[] = { + { 0x405b00, 1, 0x04, 0x00000000 }, + { 0x405b10, 1, 0x04, 0x00001000 }, + { 0x405b20, 1, 0x04, 0x04000000 }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_pd_0[] = { + { 0x406020, 1, 0x04, 0x034103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b0, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x802000f0 }, + { 0x4064c4, 1, 0x04, 0x0192ffff }, + { 0x4064c8, 1, 0x04, 0x018007c0 }, + { 0x4064cc, 9, 0x04, 0x00000000 }, + { 0x4064fc, 1, 0x04, 0x0000022a }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_be_0[] = { + { 0x408800, 1, 0x04, 0x12802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1003e005 }, + { 0x408840, 1, 0x04, 0x0000000b }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +const struct nvc0_gr_pack +nvf0_grctx_pack_hub[] = { + { nvc0_grctx_init_main_0 }, + { nvf0_grctx_init_fe_0 }, + { nvf0_grctx_init_pri_0 }, + { nve4_grctx_init_memfmt_0 }, + { nve4_grctx_init_ds_0 }, + { nvf0_grctx_init_cwd_0 }, + { nvf0_grctx_init_pd_0 }, + { nvc0_grctx_init_rstr2d_0 }, + { nve4_grctx_init_scc_0 }, + { nvf0_grctx_init_be_0 }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_setup_0[] = { + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 1, 0x04, 0x00000000 }, + { 0x41880c, 1, 0x04, 0x00000030 }, + { 0x418810, 1, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00000044 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100018 }, + {} +}; + +const struct nvc0_gr_init +nvf0_grctx_init_gpc_unk_2[] = { + { 0x418d24, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvf0_grctx_pack_gpc[] = { + { nvc0_grctx_init_gpc_unk_0 }, + { nvd9_grctx_init_prop_0 }, + { nvd9_grctx_init_gpc_unk_1 }, + { nvf0_grctx_init_setup_0 }, + { nvc0_grctx_init_zcull_0 }, + { nvd9_grctx_init_crstr_0 }, + { nve4_grctx_init_gpm_0 }, + { nvf0_grctx_init_gpc_unk_2 }, + { nvc0_grctx_init_gcc_0 }, + {} +}; + +const struct nvc0_gr_init +nvf0_grctx_init_tex_0[] = { + { 0x419a00, 1, 0x04, 0x000000f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000021 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x0000c000 }, + { 0x419a20, 1, 0x04, 0x00020800 }, + { 0x419a30, 1, 0x04, 0x00000001 }, + { 0x419ac4, 1, 0x04, 0x0037f440 }, + {} +}; + +const struct nvc0_gr_init +nvf0_grctx_init_mpc_0[] = { + { 0x419c00, 1, 0x04, 0x0000001a }, + { 0x419c04, 1, 0x04, 0x80000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + {} +}; + +const struct nvc0_gr_init +nvf0_grctx_init_l1c_0[] = { + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000203 }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_sm_0[] = { + { 0x419e04, 1, 0x04, 0x00000000 }, + { 0x419e08, 1, 0x04, 0x0000001d }, + { 0x419e0c, 1, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00001c02 }, + { 0x419e44, 1, 0x04, 0x0013eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 2, 0x04, 0x00000000 }, + { 0x419e58, 1, 0x04, 0x00000001 }, + { 0x419e5c, 3, 0x04, 0x00000000 }, + { 0x419e68, 1, 0x04, 0x00000002 }, + { 0x419e6c, 12, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x00001f8f }, + { 0x419eb0, 1, 0x04, 0x0db00d2f }, + { 0x419eb8, 1, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0001304f }, + { 0x419f30, 4, 0x04, 0x00000000 }, + { 0x419f40, 1, 0x04, 0x00000018 }, + { 0x419f44, 3, 0x04, 0x00000000 }, + { 0x419f58, 1, 0x04, 0x00000000 }, + { 0x419f70, 1, 0x04, 0x00007300 }, + { 0x419f78, 1, 0x04, 0x000000eb }, + { 0x419f7c, 1, 0x04, 0x00000404 }, + {} +}; + +static const struct nvc0_gr_pack +nvf0_grctx_pack_tpc[] = { + { nvd7_grctx_init_pe_0 }, + { nvf0_grctx_init_tex_0 }, + { nvf0_grctx_init_mpc_0 }, + { nvf0_grctx_init_l1c_0 }, + { nvf0_grctx_init_sm_0 }, + {} +}; + +static const struct nvc0_gr_init +nvf0_grctx_init_cbm_0[] = { + { 0x41bec0, 1, 0x04, 0x10000000 }, + { 0x41bec4, 1, 0x04, 0x00037f7f }, + { 0x41bee4, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_pack +nvf0_grctx_pack_ppc[] = { + { nve4_grctx_init_pes_0 }, + { nvf0_grctx_init_cbm_0 }, + { nvd7_grctx_init_wwdx_0 }, + {} +}; + +/******************************************************************************* + * PGRAPH context implementation + ******************************************************************************/ + +struct nouveau_oclass * +nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xf0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_context_ctor, + .dtor = nvc0_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, + .main = nve4_grctx_generate_main, + .unkn = nve4_grctx_generate_unkn, + .hub = nvf0_grctx_pack_hub, + .gpc = nvf0_grctx_pack_gpc, + .zcull = nvc0_grctx_pack_zcull, + .tpc = nvf0_grctx_pack_tpc, + .ppc = nvf0_grctx_pack_ppc, + .icmd = nvf0_grctx_pack_icmd, + .mthd = nvf0_grctx_pack_mthd, + .bundle = nve4_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0x180, + .bundle_token_limit = 0x7c0, + .pagepool = nve4_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = nvd7_grctx_generate_attrib, + .attrib_nr_max = 0x324, + .attrib_nr = 0x218, + .alpha_nr_max = 0x7ff, + .alpha_nr = 0x648, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc new file mode 100644 index 000000000000..e37d8106ae1a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc @@ -0,0 +1,335 @@ +/* fuc microcode util functions for nvc0 PGRAPH + * + * Copyright 2011 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifdef INCLUDE_CODE +// queue_put - add request to queue +// +// In : $r13 queue pointer +// $r14 command +// $r15 data +// +queue_put: + // make sure we have space.. + ld b32 $r8 D[$r13 + 0x0] // GET + ld b32 $r9 D[$r13 + 0x4] // PUT + xor $r8 8 + cmpu b32 $r8 $r9 + bra ne #queue_put_next + mov $r15 E_CMD_OVERFLOW + call(error) + ret + + // store cmd/data on queue + queue_put_next: + and $r8 $r9 7 + shl b32 $r8 3 + add b32 $r8 $r13 + add b32 $r8 8 + st b32 D[$r8 + 0x0] $r14 + st b32 D[$r8 + 0x4] $r15 + + // update PUT + add b32 $r9 1 + and $r9 0xf + st b32 D[$r13 + 0x4] $r9 + ret + +// queue_get - fetch request from queue +// +// In : $r13 queue pointer +// +// Out: $p1 clear on success (data available) +// $r14 command +// $r15 data +// +queue_get: + bset $flags $p1 + ld b32 $r8 D[$r13 + 0x0] // GET + ld b32 $r9 D[$r13 + 0x4] // PUT + cmpu b32 $r8 $r9 + bra e #queue_get_done + // fetch first cmd/data pair + and $r9 $r8 7 + shl b32 $r9 3 + add b32 $r9 $r13 + add b32 $r9 8 + ld b32 $r14 D[$r9 + 0x0] + ld b32 $r15 D[$r9 + 0x4] + + // update GET + add b32 $r8 1 + and $r8 0xf + st b32 D[$r13 + 0x0] $r8 + bclr $flags $p1 +queue_get_done: + ret + +// nv_rd32 - read 32-bit value from nv register +// +// In : $r14 register +// Out: $r15 value +// +nv_rd32: + mov b32 $r12 $r14 + bset $r12 31 // MMIO_CTRL_PENDING + nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) + nv_rd32_wait: + nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) + xbit $r12 $r12 31 + bra ne #nv_rd32_wait + mov $r10 6 // DONE_MMIO_RD + call(wait_doneo) + nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0) + ret + +// nv_wr32 - write 32-bit value to nv register +// +// In : $r14 register +// $r15 value +// +nv_wr32: + nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15) + mov b32 $r12 $r14 + bset $r12 31 // MMIO_CTRL_PENDING + bset $r12 30 // MMIO_CTRL_WRITE + nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) + nv_wr32_wait: + nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) + xbit $r12 $r12 31 + bra ne #nv_wr32_wait + ret + +// wait_donez - wait on FUC_DONE bit to become clear +// +// In : $r10 bit to wait on +// +wait_donez: + trace_set(T_WAIT); + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) + wait_donez_ne: + nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) + xbit $r8 $r8 $r10 + bra ne #wait_donez_ne + trace_clr(T_WAIT) + ret + +// wait_doneo - wait on FUC_DONE bit to become set +// +// In : $r10 bit to wait on +// +wait_doneo: + trace_set(T_WAIT); + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) + wait_doneo_e: + nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) + xbit $r8 $r8 $r10 + bra e #wait_doneo_e + trace_clr(T_WAIT) + ret + +// mmctx_size - determine size of a mmio list transfer +// +// In : $r14 mmio list head +// $r15 mmio list tail +// Out: $r15 transfer size (in bytes) +// +mmctx_size: + clear b32 $r9 + nv_mmctx_size_loop: + ld b32 $r8 D[$r14] + shr b32 $r8 26 + add b32 $r8 1 + shl b32 $r8 2 + add b32 $r9 $r8 + add b32 $r14 4 + cmpu b32 $r14 $r15 + bra ne #nv_mmctx_size_loop + mov b32 $r15 $r9 + ret + +// mmctx_xfer - execute a list of mmio transfers +// +// In : $r10 flags +// bit 0: direction (0 = save, 1 = load) +// bit 1: set if first transfer +// bit 2: set if last transfer +// $r11 base +// $r12 mmio list head +// $r13 mmio list tail +// $r14 multi_stride +// $r15 multi_mask +// +mmctx_xfer: + trace_set(T_MMCTX) + clear b32 $r9 + or $r11 $r11 + bra e #mmctx_base_disabled + nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11) + bset $r9 0 // BASE_EN + mmctx_base_disabled: + or $r14 $r14 + bra e #mmctx_multi_disabled + nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14) + nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15) + bset $r9 1 // MULTI_EN + mmctx_multi_disabled: + + xbit $r11 $r10 0 + shl b32 $r11 16 // DIR + bset $r11 12 // QLIMIT = 0x10 + xbit $r14 $r10 1 + shl b32 $r14 17 + or $r11 $r14 // START_TRIGGER + nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) + + // loop over the mmio list, and send requests to the hw + mmctx_exec_loop: + // wait for space in mmctx queue + mmctx_wait_free: + nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0) + and $r14 0x1f + bra e #mmctx_wait_free + + // queue up an entry + ld b32 $r14 D[$r12] + or $r14 $r9 + nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14) + add b32 $r12 4 + cmpu b32 $r12 $r13 + bra ne #mmctx_exec_loop + + xbit $r11 $r10 2 + bra ne #mmctx_stop + // wait for queue to empty + mmctx_fini_wait: + nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) + and $r11 0x1f + cmpu b32 $r11 0x10 + bra ne #mmctx_fini_wait + mov $r10 5 // DONE_MMCTX + call(wait_donez) + bra #mmctx_done + mmctx_stop: + xbit $r11 $r10 0 + shl b32 $r11 16 // DIR + bset $r11 12 // QLIMIT = 0x10 + bset $r11 18 // STOP_TRIGGER + nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) + mmctx_stop_wait: + // wait for STOP_TRIGGER to clear + nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) + xbit $r11 $r11 18 + bra ne #mmctx_stop_wait + mmctx_done: + trace_clr(T_MMCTX) + ret + +// Wait for DONE_STRAND +// +strand_wait: + push $r10 + mov $r10 2 + call(wait_donez) + pop $r10 + ret + +// unknown - call before issuing strand commands +// +strand_pre: + mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) + call(strand_wait) + ret + +// unknown - call after issuing strand commands +// +strand_post: + mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) + call(strand_wait) + ret + +// Selects strand set?! +// +// In: $r14 id +// +strand_set: + mov $r12 0xf + nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12) + mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) + nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14) + mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) + call(strand_wait) + ret + +// Initialise strand context data +// +// In : $r15 context base +// Out: $r15 context size (in bytes) +// +// Strandset(?) 3 hardcoded currently +// +strand_ctx_init: + trace_set(T_STRINIT) + call(strand_pre) + mov $r14 3 + call(strand_set) + + clear b32 $r12 + nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12) + mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) + call(strand_wait) + sub b32 $r12 $r0 1 + nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12) + mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) + call(strand_wait) + call(strand_post) + + // read the size of each strand, poke the context offset of + // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry + // about it later then. + nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00) + nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00) + shr b32 $r14 $r15 8 + ctx_init_strand_loop: + iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE + iowr I[$r8 + 0x100] $r14 // STRAND_LOAD_SWBASE + iord $r10 I[$r8 + 0x200] // STRAND_SIZE + shr b32 $r10 6 + add b32 $r10 1 + add b32 $r14 $r10 + add b32 $r8 4 + sub b32 $r9 1 + bra ne #ctx_init_strand_loop + + shl b32 $r14 8 + sub b32 $r15 $r14 $r15 + trace_clr(T_STRINIT) + ret +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc new file mode 100644 index 000000000000..7445f12b1d9e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc @@ -0,0 +1,378 @@ +/* fuc microcode for nvc0 PGRAPH/GPC + * + * Copyright 2011 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +/* TODO + * - bracket certain functions with scratch writes, useful for debugging + * - watchdog timer around ctx operations + */ + +#ifdef INCLUDE_DATA +gpc_mmio_list_head: .b32 #mmio_list_base +gpc_mmio_list_tail: +tpc_mmio_list_head: .b32 #mmio_list_base +tpc_mmio_list_tail: +unk_mmio_list_head: .b32 #mmio_list_base +unk_mmio_list_tail: .b32 #mmio_list_base + +gpc_id: .b32 0 + +tpc_count: .b32 0 +tpc_mask: .b32 0 + +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 +unk_count: .b32 0 +unk_mask: .b32 0 +#endif + +cmd_queue: queue_init + +mmio_list_base: +#endif + +#ifdef INCLUDE_CODE +// reports an exception to the host +// +// In: $r15 error code (see os.h) +// +error: + push $r14 + nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15) + mov $r15 1 + nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15) + pop $r14 + ret + +// GPC fuc initialisation, executed by triggering ucode start, will +// fall through to main loop after completion. +// +// Input: +// CC_SCRATCH[1]: context base +// +// Output: +// CC_SCRATCH[0]: +// 31:31: set to signal completion +// CC_SCRATCH[1]: +// 31:0: GPC context size +// +init: + clear b32 $r0 + + // setup stack + nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0) + extr $r1 $r1 9:17 + shl b32 $r1 8 + mov $sp $r1 + + // enable fifo access + mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO + nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2) + + // setup i0 handler, and route all interrupts to it + mov $r1 #ih + mov $iv0 $r1 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0) + + // enable fifo interrupt + mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO + nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2) + + // enable interrupts + bset $flags ie0 + + // figure out which GPC we are, and how many TPCs we have + nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0) + mov $r3 1 + and $r2 0x1f + shl b32 $r3 $r2 + sub b32 $r3 1 + st b32 D[$r0 + #tpc_count] $r2 + st b32 D[$r0 + #tpc_mask] $r3 + nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0) + st b32 D[$r0 + #gpc_id] $r2 + +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // figure out which, and how many, UNKs are actually present + imm32($r14, 0x500c30) + clear b32 $r2 + clear b32 $r3 + clear b32 $r4 + init_unk_loop: + call(nv_rd32) + cmp b32 $r15 0 + bra z #init_unk_next + mov $r15 1 + shl b32 $r15 $r2 + or $r4 $r15 + add b32 $r3 1 + init_unk_next: + add b32 $r2 1 + add b32 $r14 4 + cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE + bra ne #init_unk_loop + init_unk_done: + st b32 D[$r0 + #unk_count] $r3 + st b32 D[$r0 + #unk_mask] $r4 +#endif + + // initialise context base, and size tracking + nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0) + clear b32 $r3 // track GPC context size here + + // set mmctx base addresses now so we don't have to do it later, + // they don't currently ever change + shr b32 $r5 $r2 8 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5) + nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5) + + // calculate GPC mmio context size + ld b32 $r14 D[$r0 + #gpc_mmio_list_head] + ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] + call(mmctx_size) + add b32 $r2 $r15 + add b32 $r3 $r15 + + // calculate per-TPC mmio context size + ld b32 $r14 D[$r0 + #tpc_mmio_list_head] + ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] + call(mmctx_size) + ld b32 $r14 D[$r0 + #tpc_count] + mulu $r14 $r15 + add b32 $r2 $r14 + add b32 $r3 $r14 + +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // calculate per-UNK mmio context size + ld b32 $r14 D[$r0 + #unk_mmio_list_head] + ld b32 $r15 D[$r0 + #unk_mmio_list_tail] + call(mmctx_size) + ld b32 $r14 D[$r0 + #unk_count] + mulu $r14 $r15 + add b32 $r2 $r14 + add b32 $r3 $r14 +#endif + + // round up base/size to 256 byte boundary (for strand SWBASE) + shr b32 $r3 2 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?! + shr b32 $r2 8 + shr b32 $r3 6 + add b32 $r2 1 + add b32 $r3 1 + shl b32 $r2 8 + shl b32 $r3 8 + + // calculate size of strand context data + mov b32 $r15 $r2 + call(strand_ctx_init) + add b32 $r3 $r15 + + // save context size, and tell HUB we're done + nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3) + clear b32 $r2 + bset $r2 31 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2) + +// Main program loop, very simple, sleeps until woken up by the interrupt +// handler, pulls a command from the queue and executes its handler +// +main: + bset $flags $p0 + sleep $p0 + mov $r13 #cmd_queue + call(queue_get) + bra $p1 #main + + // 0x0000-0x0003 are all context transfers + cmpu b32 $r14 0x04 + bra nc #main_not_ctx_xfer + // fetch $flags and mask off $p1/$p2 + mov $r1 $flags + mov $r2 0x0006 + not b32 $r2 + and $r1 $r2 + // set $p1/$p2 according to transfer type + shl b32 $r14 1 + or $r1 $r14 + mov $flags $r1 + // transfer context data + call(ctx_xfer) + bra #main + + main_not_ctx_xfer: + shl b32 $r15 $r14 16 + or $r15 E_BAD_COMMAND + call(error) + bra #main + +// interrupt handler +ih: + push $r8 + mov $r8 $flags + push $r8 + push $r9 + push $r10 + push $r11 + push $r13 + push $r14 + push $r15 + clear b32 $r0 + + // incoming fifo command? + nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0) + and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO + bra e #ih_no_fifo + // queue incoming fifo command for later processing + mov $r13 #cmd_queue + nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0) + nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0) + call(queue_put) + mov $r14 1 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14) + + // ack, and wake up main() + ih_no_fifo: + nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10) + + pop $r15 + pop $r14 + pop $r13 + pop $r11 + pop $r10 + pop $r9 + pop $r8 + mov $flags $r8 + pop $r8 + bclr $flags $p0 + iret + +// Set this GPC's bit in HUB_BAR, used to signal completion of various +// activities to the HUB fuc +// +hub_barrier_done: + mov $r15 1 + ld b32 $r14 D[$r0 + #gpc_id] + shl b32 $r15 $r14 + nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET + ret + +// Disables various things, waits a bit, and re-enables them.. +// +// Not sure how exactly this helps, perhaps "ENABLE" is not such a +// good description for the bits we turn off? Anyways, without this, +// funny things happen. +// +ctx_redswitch: + mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER + nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) + mov $r14 8 + ctx_redswitch_delay: + sub b32 $r14 1 + bra ne #ctx_redswitch_delay + or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 + or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE + nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) + ret + +// Transfer GPC context data between GPU and storage area +// +// In: $r15 context base address +// $p1 clear on save, set on load +// $p2 set if opposite direction done/will be done, so: +// on save it means: "a load will follow this save" +// on load it means: "a save preceeded this load" +// +ctx_xfer: + // set context base address + nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15) + bra not $p1 #ctx_xfer_not_load + call(ctx_redswitch) + ctx_xfer_not_load: + + // strands + call(strand_pre) + clear b32 $r2 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2) + xbit $r2 $flags $p1 // SAVE/LOAD + add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE + nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2) + + // mmio context + xbit $r10 $flags $p1 // direction + or $r10 2 // first + imm32($r11,0x500000) + ld b32 $r12 D[$r0 + #gpc_id] + shl b32 $r12 15 + add b32 $r11 $r12 // base = NV_PGRAPH_GPCn + ld b32 $r12 D[$r0 + #gpc_mmio_list_head] + ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] + mov $r14 0 // not multi + call(mmctx_xfer) + + // per-TPC mmio context + xbit $r10 $flags $p1 // direction +#if !NV_PGRAPH_GPCX_UNK__SIZE + or $r10 4 // last +#endif + imm32($r11, 0x504000) + ld b32 $r12 D[$r0 + #gpc_id] + shl b32 $r12 15 + add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 + ld b32 $r12 D[$r0 + #tpc_mmio_list_head] + ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] + ld b32 $r15 D[$r0 + #tpc_mask] + mov $r14 0x800 // stride = 0x800 + call(mmctx_xfer) + +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // per-UNK mmio context + xbit $r10 $flags $p1 // direction + or $r10 4 // last + imm32($r11, 0x503000) + ld b32 $r12 D[$r0 + #gpc_id] + shl b32 $r12 15 + add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 + ld b32 $r12 D[$r0 + #unk_mmio_list_head] + ld b32 $r13 D[$r0 + #unk_mmio_list_tail] + ld b32 $r15 D[$r0 + #unk_mask] + mov $r14 0x200 // stride = 0x200 + call(mmctx_xfer) +#endif + + // wait for strands to finish + call(strand_wait) + + // if load, or a save without a load following, do some + // unknown stuff that's done after finishing a block of + // strand commands + bra $p1 #ctx_xfer_post + bra not $p2 #ctx_xfer_done + ctx_xfer_post: + call(strand_post) + + // mark completion in HUB's barrier + ctx_xfer_done: + call(hub_barrier_done) + ret +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 new file mode 100644 index 000000000000..e730603891d7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 + +#define CHIPSET GK208 +#include "macros.fuc" + +.section #gm107_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #gm107_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h new file mode 100644 index 000000000000..6d53b67dd3c4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h @@ -0,0 +1,473 @@ +uint32_t gm107_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t gm107_grgpc_code[] = { + 0x03140ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0xf489a408, + 0x020f0b1b, + 0x0002f87e, +/* 0x001a: queue_put_next */ + 0x98c400f8, + 0x0384b607, + 0xb6008dbb, + 0x8eb50880, + 0x018fb500, + 0xf00190b6, + 0xd9b50f94, +/* 0x0037: queue_get */ + 0xf400f801, + 0xd8980131, + 0x01d99800, + 0x0bf489a4, + 0x0789c421, + 0xbb0394b6, + 0x90b6009d, + 0x009e9808, + 0xb6019f98, + 0x84f00180, + 0x00d8b50f, +/* 0x0063: queue_get_done */ + 0xf80132f4, +/* 0x0065: nv_rd32 */ + 0xf0ecb200, + 0x00801fc9, + 0x0cf601ca, +/* 0x0073: nv_rd32_wait */ + 0x8c04bd00, + 0xcf01ca00, + 0xccc800cc, + 0xf61bf41f, + 0xec7e060a, + 0x008f0000, + 0xffcf01cb, +/* 0x008f: nv_wr32 */ + 0x8000f800, + 0xf601cc00, + 0x04bd000f, + 0xc9f0ecb2, + 0x1ec9f01f, + 0x01ca0080, + 0xbd000cf6, +/* 0x00a9: nv_wr32_wait */ + 0xca008c04, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f61b, +/* 0x00b8: wait_donez */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x00cf: wait_donez_ne */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf61bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x00ec: wait_doneo */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x0103: wait_doneo_e */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf60bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x0120: mmctx_size */ +/* 0x0122: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0x1bf4efa4, + 0xf89fb2ec, +/* 0x013d: mmctx_xfer */ + 0xf094bd00, + 0x00800199, + 0x09f60237, + 0xbd04bd00, + 0x05bbfd94, + 0x800f0bf4, + 0xf601c400, + 0x04bd000b, +/* 0x015f: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0xc6008018, + 0x000ef601, + 0x008004bd, + 0x0ff601c7, + 0xf004bd00, +/* 0x017a: mmctx_multi_disabled */ + 0xabc80199, + 0x10b4b600, + 0xc80cb9f0, + 0xe4b601ae, + 0x05befd11, + 0x01c50080, + 0xbd000bf6, +/* 0x0195: mmctx_exec_loop */ +/* 0x0195: mmctx_wait_free */ + 0xc5008e04, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f60b, + 0x05e9fd00, + 0x01c80080, + 0xbd000ef6, + 0x04c0b604, + 0x1bf4cda4, + 0x02abc8df, +/* 0x01bf: mmctx_fini_wait */ + 0x8b1c1bf4, + 0xcf01c500, + 0xb4f000bb, + 0x10b4b01f, + 0x0af31bf4, + 0x00b87e05, + 0x250ef400, +/* 0x01d8: mmctx_stop */ + 0xb600abc8, + 0xb9f010b4, + 0x12b9f00c, + 0x01c50080, + 0xbd000bf6, +/* 0x01ed: mmctx_stop_wait */ + 0xc5008b04, + 0x00bbcf01, + 0xf412bbc8, +/* 0x01fa: mmctx_done */ + 0x94bdf61b, + 0x800199f0, + 0xf6021700, + 0x04bd0009, +/* 0x020a: strand_wait */ + 0xa0f900f8, + 0xb87e020a, + 0xa0fc0000, +/* 0x0216: strand_pre */ + 0x0c0900f8, + 0x024afc80, + 0xbd0009f6, + 0x020a7e04, +/* 0x0227: strand_post */ + 0x0900f800, + 0x4afc800d, + 0x0009f602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0238: strand_set */ + 0xfc800f0c, + 0x0cf6024f, + 0x0c04bd00, + 0x4afc800b, + 0x000cf602, + 0xfc8004bd, + 0x0ef6024f, + 0x0c04bd00, + 0x4afc800a, + 0x000cf602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0268: strand_ctx_init */ + 0x99f094bd, + 0x37008003, + 0x0009f602, + 0x167e04bd, + 0x030e0002, + 0x0002387e, + 0xfc80c4bd, + 0x0cf60247, + 0x0c04bd00, + 0x4afc8001, + 0x000cf602, + 0x0a7e04bd, + 0x0c920002, + 0x46fc8001, + 0x000cf602, + 0x020c04bd, + 0x024afc80, + 0xbd000cf6, + 0x020a7e04, + 0x02277e00, + 0x42008800, + 0x20008902, + 0x0099cf02, +/* 0x02c7: ctx_init_strand_loop */ + 0xf608fe95, + 0x8ef6008e, + 0x808acf40, + 0xb606a5b6, + 0xeabb01a0, + 0x0480b600, + 0xf40192b6, + 0xe4b6e81b, + 0xf2efbc08, + 0x99f094bd, + 0x17008003, + 0x0009f602, + 0x00f804bd, +/* 0x02f8: error */ + 0xffb2e0f9, + 0x4098148e, + 0x00008f7e, + 0xffb2010f, + 0x409c1c8e, + 0x00008f7e, + 0x00f8e0fc, +/* 0x0314: init */ + 0x004104bd, + 0x0011cf42, + 0x010911e7, + 0xfe0814b6, + 0x02020014, + 0xf6120040, + 0x04bd0002, + 0xfe047241, + 0x00400010, + 0x0000f607, + 0x040204bd, + 0xf6040040, + 0x04bd0002, + 0x821031f4, + 0xcf018200, + 0x01030022, + 0xbb1f24f0, + 0x32b60432, + 0x0502b501, + 0x820603b5, + 0xcf018600, + 0x02b50022, + 0x0c308e04, + 0xbd24bd50, +/* 0x0377: init_unk_loop */ + 0x7e44bd34, + 0xb0000065, + 0x0bf400f6, + 0xbb010f0e, + 0x4ffd04f2, + 0x0130b605, +/* 0x038c: init_unk_next */ + 0xb60120b6, + 0x26b004e0, + 0xe21bf402, +/* 0x0398: init_unk_done */ + 0xb50703b5, + 0x00820804, + 0x22cf0201, + 0x9534bd00, + 0x00800825, + 0x05f601c0, + 0x8004bd00, + 0xf601c100, + 0x04bd0005, + 0x98000e98, + 0x207e010f, + 0x2fbb0001, + 0x003fbb00, + 0x98010e98, + 0x207e020f, + 0x0e980001, + 0x00effd05, + 0xbb002ebb, + 0x0e98003e, + 0x030f9802, + 0x0001207e, + 0xfd070e98, + 0x2ebb00ef, + 0x003ebb00, + 0x800235b6, + 0xf601d300, + 0x04bd0003, + 0xb60825b6, + 0x20b60635, + 0x0130b601, + 0xb60824b6, + 0x2fb20834, + 0x0002687e, + 0x80003fbb, + 0xf6020100, + 0x04bd0003, + 0x29f024bd, + 0x3000801f, + 0x0002f602, +/* 0x0436: main */ + 0x31f404bd, + 0x0028f400, + 0x377e240d, + 0x01f40000, + 0x04e4b0f4, + 0xfe1d18f4, + 0x06020181, + 0x12fd20bd, + 0x01e4b604, + 0xfe051efd, + 0x097e0018, + 0x0ef40005, +/* 0x0465: main_not_ctx_xfer */ + 0x10ef94d4, + 0x7e01f5f0, + 0xf40002f8, +/* 0x0472: ih */ + 0x80f9c70e, + 0xf90188fe, + 0xf990f980, + 0xf9b0f9a0, + 0xf9e0f9d0, + 0x4a04bdf0, + 0xaacf0200, + 0x04abc400, + 0x0d1f0bf4, + 0x1a004e24, + 0x4f00eecf, + 0xffcf1900, + 0x00047e00, + 0x40010e00, + 0x0ef61d00, +/* 0x04af: ih_no_fifo */ + 0x4004bd00, + 0x0af60100, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x04cf: hub_barrier_done */ + 0x0f01f800, + 0x040e9801, + 0xb204febb, + 0x94188eff, + 0x008f7e40, +/* 0x04e3: ctx_redswitch */ + 0x0f00f800, + 0x85008020, + 0x000ff601, + 0x080e04bd, +/* 0x04f0: ctx_redswitch_delay */ + 0xf401e2b6, + 0xf5f1fd1b, + 0xf5f10800, + 0x00800200, + 0x0ff60185, + 0xf804bd00, +/* 0x0509: ctx_xfer */ + 0x81008000, + 0x000ff602, + 0x11f404bd, + 0x04e37e07, +/* 0x0519: ctx_xfer_not_load */ + 0x02167e00, + 0x8024bd00, + 0xf60247fc, + 0x04bd0002, + 0xb6012cf0, + 0xfc800320, + 0x02f6024a, + 0xf004bd00, + 0xa5f001ac, + 0x00008b02, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x010d9800, + 0x3d7e000e, + 0xacf00001, + 0x40008b01, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x020d9801, + 0x4e060f98, + 0x3d7e0800, + 0xacf00001, + 0x04a5f001, + 0x5030008b, + 0xb6040c98, + 0xbcbb0fc4, + 0x020c9800, + 0x98030d98, + 0x004e080f, + 0x013d7e02, + 0x020a7e00, + 0x0601f400, +/* 0x05a3: ctx_xfer_post */ + 0x7e0712f4, +/* 0x05a7: ctx_xfer_done */ + 0x7e000227, + 0xf80004cf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 new file mode 100644 index 000000000000..bd30262d635b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 + +#define CHIPSET GK208 +#include "macros.fuc" + +.section #nv108_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nv108_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h new file mode 100644 index 000000000000..31922707794f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h @@ -0,0 +1,473 @@ +uint32_t nv108_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nv108_grgpc_code[] = { + 0x03140ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0xf489a408, + 0x020f0b1b, + 0x0002f87e, +/* 0x001a: queue_put_next */ + 0x98c400f8, + 0x0384b607, + 0xb6008dbb, + 0x8eb50880, + 0x018fb500, + 0xf00190b6, + 0xd9b50f94, +/* 0x0037: queue_get */ + 0xf400f801, + 0xd8980131, + 0x01d99800, + 0x0bf489a4, + 0x0789c421, + 0xbb0394b6, + 0x90b6009d, + 0x009e9808, + 0xb6019f98, + 0x84f00180, + 0x00d8b50f, +/* 0x0063: queue_get_done */ + 0xf80132f4, +/* 0x0065: nv_rd32 */ + 0xf0ecb200, + 0x00801fc9, + 0x0cf601ca, +/* 0x0073: nv_rd32_wait */ + 0x8c04bd00, + 0xcf01ca00, + 0xccc800cc, + 0xf61bf41f, + 0xec7e060a, + 0x008f0000, + 0xffcf01cb, +/* 0x008f: nv_wr32 */ + 0x8000f800, + 0xf601cc00, + 0x04bd000f, + 0xc9f0ecb2, + 0x1ec9f01f, + 0x01ca0080, + 0xbd000cf6, +/* 0x00a9: nv_wr32_wait */ + 0xca008c04, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f61b, +/* 0x00b8: wait_donez */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x00cf: wait_donez_ne */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf61bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x00ec: wait_doneo */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x0103: wait_doneo_e */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf60bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x0120: mmctx_size */ +/* 0x0122: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0x1bf4efa4, + 0xf89fb2ec, +/* 0x013d: mmctx_xfer */ + 0xf094bd00, + 0x00800199, + 0x09f60237, + 0xbd04bd00, + 0x05bbfd94, + 0x800f0bf4, + 0xf601c400, + 0x04bd000b, +/* 0x015f: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0xc6008018, + 0x000ef601, + 0x008004bd, + 0x0ff601c7, + 0xf004bd00, +/* 0x017a: mmctx_multi_disabled */ + 0xabc80199, + 0x10b4b600, + 0xc80cb9f0, + 0xe4b601ae, + 0x05befd11, + 0x01c50080, + 0xbd000bf6, +/* 0x0195: mmctx_exec_loop */ +/* 0x0195: mmctx_wait_free */ + 0xc5008e04, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f60b, + 0x05e9fd00, + 0x01c80080, + 0xbd000ef6, + 0x04c0b604, + 0x1bf4cda4, + 0x02abc8df, +/* 0x01bf: mmctx_fini_wait */ + 0x8b1c1bf4, + 0xcf01c500, + 0xb4f000bb, + 0x10b4b01f, + 0x0af31bf4, + 0x00b87e05, + 0x250ef400, +/* 0x01d8: mmctx_stop */ + 0xb600abc8, + 0xb9f010b4, + 0x12b9f00c, + 0x01c50080, + 0xbd000bf6, +/* 0x01ed: mmctx_stop_wait */ + 0xc5008b04, + 0x00bbcf01, + 0xf412bbc8, +/* 0x01fa: mmctx_done */ + 0x94bdf61b, + 0x800199f0, + 0xf6021700, + 0x04bd0009, +/* 0x020a: strand_wait */ + 0xa0f900f8, + 0xb87e020a, + 0xa0fc0000, +/* 0x0216: strand_pre */ + 0x0c0900f8, + 0x024afc80, + 0xbd0009f6, + 0x020a7e04, +/* 0x0227: strand_post */ + 0x0900f800, + 0x4afc800d, + 0x0009f602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0238: strand_set */ + 0xfc800f0c, + 0x0cf6024f, + 0x0c04bd00, + 0x4afc800b, + 0x000cf602, + 0xfc8004bd, + 0x0ef6024f, + 0x0c04bd00, + 0x4afc800a, + 0x000cf602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0268: strand_ctx_init */ + 0x99f094bd, + 0x37008003, + 0x0009f602, + 0x167e04bd, + 0x030e0002, + 0x0002387e, + 0xfc80c4bd, + 0x0cf60247, + 0x0c04bd00, + 0x4afc8001, + 0x000cf602, + 0x0a7e04bd, + 0x0c920002, + 0x46fc8001, + 0x000cf602, + 0x020c04bd, + 0x024afc80, + 0xbd000cf6, + 0x020a7e04, + 0x02277e00, + 0x42008800, + 0x20008902, + 0x0099cf02, +/* 0x02c7: ctx_init_strand_loop */ + 0xf608fe95, + 0x8ef6008e, + 0x808acf40, + 0xb606a5b6, + 0xeabb01a0, + 0x0480b600, + 0xf40192b6, + 0xe4b6e81b, + 0xf2efbc08, + 0x99f094bd, + 0x17008003, + 0x0009f602, + 0x00f804bd, +/* 0x02f8: error */ + 0xffb2e0f9, + 0x4098148e, + 0x00008f7e, + 0xffb2010f, + 0x409c1c8e, + 0x00008f7e, + 0x00f8e0fc, +/* 0x0314: init */ + 0x004104bd, + 0x0011cf42, + 0x010911e7, + 0xfe0814b6, + 0x02020014, + 0xf6120040, + 0x04bd0002, + 0xfe047241, + 0x00400010, + 0x0000f607, + 0x040204bd, + 0xf6040040, + 0x04bd0002, + 0x821031f4, + 0xcf018200, + 0x01030022, + 0xbb1f24f0, + 0x32b60432, + 0x0502b501, + 0x820603b5, + 0xcf018600, + 0x02b50022, + 0x0c308e04, + 0xbd24bd50, +/* 0x0377: init_unk_loop */ + 0x7e44bd34, + 0xb0000065, + 0x0bf400f6, + 0xbb010f0e, + 0x4ffd04f2, + 0x0130b605, +/* 0x038c: init_unk_next */ + 0xb60120b6, + 0x26b004e0, + 0xe21bf401, +/* 0x0398: init_unk_done */ + 0xb50703b5, + 0x00820804, + 0x22cf0201, + 0x9534bd00, + 0x00800825, + 0x05f601c0, + 0x8004bd00, + 0xf601c100, + 0x04bd0005, + 0x98000e98, + 0x207e010f, + 0x2fbb0001, + 0x003fbb00, + 0x98010e98, + 0x207e020f, + 0x0e980001, + 0x00effd05, + 0xbb002ebb, + 0x0e98003e, + 0x030f9802, + 0x0001207e, + 0xfd070e98, + 0x2ebb00ef, + 0x003ebb00, + 0x800235b6, + 0xf601d300, + 0x04bd0003, + 0xb60825b6, + 0x20b60635, + 0x0130b601, + 0xb60824b6, + 0x2fb20834, + 0x0002687e, + 0x80003fbb, + 0xf6020100, + 0x04bd0003, + 0x29f024bd, + 0x3000801f, + 0x0002f602, +/* 0x0436: main */ + 0x31f404bd, + 0x0028f400, + 0x377e240d, + 0x01f40000, + 0x04e4b0f4, + 0xfe1d18f4, + 0x06020181, + 0x12fd20bd, + 0x01e4b604, + 0xfe051efd, + 0x097e0018, + 0x0ef40005, +/* 0x0465: main_not_ctx_xfer */ + 0x10ef94d4, + 0x7e01f5f0, + 0xf40002f8, +/* 0x0472: ih */ + 0x80f9c70e, + 0xf90188fe, + 0xf990f980, + 0xf9b0f9a0, + 0xf9e0f9d0, + 0x4a04bdf0, + 0xaacf0200, + 0x04abc400, + 0x0d1f0bf4, + 0x1a004e24, + 0x4f00eecf, + 0xffcf1900, + 0x00047e00, + 0x40010e00, + 0x0ef61d00, +/* 0x04af: ih_no_fifo */ + 0x4004bd00, + 0x0af60100, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x04cf: hub_barrier_done */ + 0x0f01f800, + 0x040e9801, + 0xb204febb, + 0x94188eff, + 0x008f7e40, +/* 0x04e3: ctx_redswitch */ + 0x0f00f800, + 0x85008020, + 0x000ff601, + 0x080e04bd, +/* 0x04f0: ctx_redswitch_delay */ + 0xf401e2b6, + 0xf5f1fd1b, + 0xf5f10800, + 0x00800200, + 0x0ff60185, + 0xf804bd00, +/* 0x0509: ctx_xfer */ + 0x81008000, + 0x000ff602, + 0x11f404bd, + 0x04e37e07, +/* 0x0519: ctx_xfer_not_load */ + 0x02167e00, + 0x8024bd00, + 0xf60247fc, + 0x04bd0002, + 0xb6012cf0, + 0xfc800320, + 0x02f6024a, + 0xf004bd00, + 0xa5f001ac, + 0x00008b02, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x010d9800, + 0x3d7e000e, + 0xacf00001, + 0x40008b01, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x020d9801, + 0x4e060f98, + 0x3d7e0800, + 0xacf00001, + 0x04a5f001, + 0x5030008b, + 0xb6040c98, + 0xbcbb0fc4, + 0x020c9800, + 0x98030d98, + 0x004e080f, + 0x013d7e02, + 0x020a7e00, + 0x0601f400, +/* 0x05a3: ctx_xfer_post */ + 0x7e0712f4, +/* 0x05a7: ctx_xfer_done */ + 0x7e000227, + 0xf80004cf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 new file mode 100644 index 000000000000..5ae06a2d64c9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000 + +#define CHIPSET GF100 +#include "macros.fuc" + +.section #nvc0_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nvc0_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h new file mode 100644 index 000000000000..325cc7b7b2fb --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h @@ -0,0 +1,530 @@ +uint32_t nvc0_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x00000064, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x00000064, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x00000064, +/* 0x000c: unk_mmio_list_tail */ + 0x00000064, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nvc0_grgpc_code[] = { + 0x03a10ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0xe0f900f8, + 0xf102ffb9, + 0xf09814e7, + 0x21f440e3, + 0x01f7f09d, + 0xf102ffb9, + 0xf09c1ce7, + 0x21f440e3, + 0xf8e0fc9d, +/* 0x03a1: init */ + 0xf104bd00, + 0xf0420017, + 0x11cf0013, + 0x0911e700, + 0x0814b601, + 0xf00014fe, + 0x07f10227, + 0x03f01200, + 0x0002d000, + 0x17f104bd, + 0x10fe04e6, + 0x0007f100, + 0x0003f007, + 0xbd0000d0, + 0x0427f004, + 0x040007f1, + 0xd00003f0, + 0x04bd0002, + 0xf11031f4, + 0xf0820027, + 0x22cf0123, + 0x0137f000, + 0xbb1f24f0, + 0x32b60432, + 0x05028001, + 0xf1060380, + 0xf0860027, + 0x22cf0123, + 0x04028000, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0xf1082595, + 0xf0c00007, + 0x05d00103, + 0xf104bd00, + 0xf0c10007, + 0x05d00103, + 0x9804bd00, + 0x0f98000e, + 0x5021f501, + 0x002fbb01, + 0x98003fbb, + 0x0f98010e, + 0x5021f502, + 0x050e9801, + 0xbb00effd, + 0x3ebb002e, + 0x0235b600, + 0xd30007f1, + 0xd00103f0, + 0x04bd0003, + 0xb60825b6, + 0x20b60635, + 0x0130b601, + 0xb60824b6, + 0x2fb90834, + 0xd321f502, + 0x003fbb02, + 0x010007f1, + 0xd00203f0, + 0x04bd0003, + 0x29f024bd, + 0x0007f11f, + 0x0203f008, + 0xbd0002d0, +/* 0x04a9: main */ + 0x0031f404, + 0xf00028f4, + 0x21f41cd7, + 0xf401f439, + 0xf404e4b0, + 0x81fe1e18, + 0x0627f001, + 0x12fd20bd, + 0x01e4b604, + 0xfe051efd, + 0x21f50018, + 0x0ef4059e, +/* 0x04d9: main_not_ctx_xfer */ + 0x10ef94d3, + 0xf501f5f0, + 0xf4037e21, +/* 0x04e6: ih */ + 0x80f9c60e, + 0xf90188fe, + 0xf990f980, + 0xf9b0f9a0, + 0xf9e0f9d0, + 0xf104bdf0, + 0xf00200a7, + 0xaacf00a3, + 0x04abc400, + 0xf02c0bf4, + 0xe7f11cd7, + 0xe3f01a00, + 0x00eecf00, + 0x1900f7f1, + 0xcf00f3f0, + 0x21f400ff, + 0x01e7f004, + 0x1d0007f1, + 0xd00003f0, + 0x04bd000e, +/* 0x0534: ih_no_fifo */ + 0x010007f1, + 0xd00003f0, + 0x04bd000a, + 0xe0fcf0fc, + 0xb0fcd0fc, + 0x90fca0fc, + 0x88fe80fc, + 0xf480fc00, + 0x01f80032, +/* 0x0558: hub_barrier_done */ + 0x9801f7f0, + 0xfebb040e, + 0x02ffb904, + 0x9418e7f1, + 0xf440e3f0, + 0x00f89d21, +/* 0x0570: ctx_redswitch */ + 0xf120f7f0, + 0xf0850007, + 0x0fd00103, + 0xf004bd00, +/* 0x0582: ctx_redswitch_delay */ + 0xe2b608e7, + 0xfd1bf401, + 0x0800f5f1, + 0x0200f5f1, + 0x850007f1, + 0xd00103f0, + 0x04bd000f, +/* 0x059e: ctx_xfer */ + 0x07f100f8, + 0x03f08100, + 0x000fd002, + 0x11f404bd, + 0x7021f507, +/* 0x05b1: ctx_xfer_not_load */ + 0x6a21f505, + 0xf124bd02, + 0xf047fc07, + 0x02d00203, + 0xf004bd00, + 0x20b6012c, + 0xfc07f103, + 0x0203f04a, + 0xbd0002d0, + 0x01acf004, + 0xf102a5f0, + 0xf00000b7, + 0x0c9850b3, + 0x0fc4b604, + 0x9800bcbb, + 0x0d98000c, + 0x00e7f001, + 0x016f21f5, + 0xf001acf0, + 0xb7f104a5, + 0xb3f04000, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x020d9801, + 0xf1060f98, + 0xf50800e7, + 0xf5016f21, + 0xf4025e21, + 0x12f40601, +/* 0x0629: ctx_xfer_post */ + 0x7f21f507, +/* 0x062d: ctx_xfer_done */ + 0x5821f502, + 0x0000f805, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 new file mode 100644 index 000000000000..c2f754edbd7d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 + +#define CHIPSET GF117 +#include "macros.fuc" + +.section #nvd7_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nvd7_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h new file mode 100644 index 000000000000..d1504a4059c6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h @@ -0,0 +1,537 @@ +uint32_t nvd7_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nvd7_grgpc_code[] = { + 0x03a10ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0xe0f900f8, + 0xf102ffb9, + 0xf09814e7, + 0x21f440e3, + 0x01f7f09d, + 0xf102ffb9, + 0xf09c1ce7, + 0x21f440e3, + 0xf8e0fc9d, +/* 0x03a1: init */ + 0xf104bd00, + 0xf0420017, + 0x11cf0013, + 0x0911e700, + 0x0814b601, + 0xf00014fe, + 0x07f10227, + 0x03f01200, + 0x0002d000, + 0x17f104bd, + 0x10fe0530, + 0x0007f100, + 0x0003f007, + 0xbd0000d0, + 0x0427f004, + 0x040007f1, + 0xd00003f0, + 0x04bd0002, + 0xf11031f4, + 0xf0820027, + 0x22cf0123, + 0x0137f000, + 0xbb1f24f0, + 0x32b60432, + 0x05028001, + 0xf1060380, + 0xf0860027, + 0x22cf0123, + 0x04028000, + 0x0c30e7f1, + 0xbd50e3f0, + 0xbd34bd24, +/* 0x0421: init_unk_loop */ + 0x6821f444, + 0xf400f6b0, + 0xf7f00f0b, + 0x04f2bb01, + 0xb6054ffd, +/* 0x0436: init_unk_next */ + 0x20b60130, + 0x04e0b601, + 0xf40126b0, +/* 0x0442: init_unk_done */ + 0x0380e21b, + 0x08048007, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0xf1082595, + 0xf0c00007, + 0x05d00103, + 0xf104bd00, + 0xf0c10007, + 0x05d00103, + 0x9804bd00, + 0x0f98000e, + 0x5021f501, + 0x002fbb01, + 0x98003fbb, + 0x0f98010e, + 0x5021f502, + 0x050e9801, + 0xbb00effd, + 0x3ebb002e, + 0x020e9800, + 0xf5030f98, + 0x98015021, + 0xeffd070e, + 0x002ebb00, + 0xb6003ebb, + 0x07f10235, + 0x03f0d300, + 0x0003d001, + 0x25b604bd, + 0x0635b608, + 0xb60120b6, + 0x24b60130, + 0x0834b608, + 0xf5022fb9, + 0xbb02d321, + 0x07f1003f, + 0x03f00100, + 0x0003d002, + 0x24bd04bd, + 0xf11f29f0, + 0xf0080007, + 0x02d00203, +/* 0x04f3: main */ + 0xf404bd00, + 0x28f40031, + 0x24d7f000, + 0xf43921f4, + 0xe4b0f401, + 0x1e18f404, + 0xf00181fe, + 0x20bd0627, + 0xb60412fd, + 0x1efd01e4, + 0x0018fe05, + 0x05e821f5, +/* 0x0523: main_not_ctx_xfer */ + 0x94d30ef4, + 0xf5f010ef, + 0x7e21f501, + 0xc60ef403, +/* 0x0530: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x24d7f02c, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xf00421f4, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x057e: ih_no_fifo */ + 0x07f104bd, + 0x03f00100, + 0x000ad000, + 0xf0fc04bd, + 0xd0fce0fc, + 0xa0fcb0fc, + 0x80fc90fc, + 0xfc0088fe, + 0x0032f480, +/* 0x05a2: hub_barrier_done */ + 0xf7f001f8, + 0x040e9801, + 0xb904febb, + 0xe7f102ff, + 0xe3f09418, + 0x9d21f440, +/* 0x05ba: ctx_redswitch */ + 0xf7f000f8, + 0x0007f120, + 0x0103f085, + 0xbd000fd0, + 0x08e7f004, +/* 0x05cc: ctx_redswitch_delay */ + 0xf401e2b6, + 0xf5f1fd1b, + 0xf5f10800, + 0x07f10200, + 0x03f08500, + 0x000fd001, + 0x00f804bd, +/* 0x05e8: ctx_xfer */ + 0x810007f1, + 0xd00203f0, + 0x04bd000f, + 0xf50711f4, +/* 0x05fb: ctx_xfer_not_load */ + 0xf505ba21, + 0xbd026a21, + 0xfc07f124, + 0x0203f047, + 0xbd0002d0, + 0x012cf004, + 0xf10320b6, + 0xf04afc07, + 0x02d00203, + 0xf004bd00, + 0xa5f001ac, + 0x00b7f102, + 0x50b3f000, + 0xb6040c98, + 0xbcbb0fc4, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xacf0016f, + 0x00b7f101, + 0x50b3f040, + 0xb6040c98, + 0xbcbb0fc4, + 0x010c9800, + 0x98020d98, + 0xe7f1060f, + 0x21f50800, + 0xacf0016f, + 0x04a5f001, + 0x3000b7f1, + 0x9850b3f0, + 0xc4b6040c, + 0x00bcbb0f, + 0x98020c98, + 0x0f98030d, + 0x00e7f108, + 0x6f21f502, + 0x5e21f501, + 0x0601f402, +/* 0x0697: ctx_xfer_post */ + 0xf50712f4, +/* 0x069b: ctx_xfer_done */ + 0xf5027f21, + 0xf805a221, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 new file mode 100644 index 000000000000..6b906cd2a31f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 + +#define CHIPSET GK100 +#include "macros.fuc" + +.section #nve0_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nve0_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h new file mode 100644 index 000000000000..855b220378f9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h @@ -0,0 +1,537 @@ +uint32_t nve0_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nve0_grgpc_code[] = { + 0x03a10ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0xe0f900f8, + 0xf102ffb9, + 0xf09814e7, + 0x21f440e3, + 0x01f7f09d, + 0xf102ffb9, + 0xf09c1ce7, + 0x21f440e3, + 0xf8e0fc9d, +/* 0x03a1: init */ + 0xf104bd00, + 0xf0420017, + 0x11cf0013, + 0x0911e700, + 0x0814b601, + 0xf00014fe, + 0x07f10227, + 0x03f01200, + 0x0002d000, + 0x17f104bd, + 0x10fe0530, + 0x0007f100, + 0x0003f007, + 0xbd0000d0, + 0x0427f004, + 0x040007f1, + 0xd00003f0, + 0x04bd0002, + 0xf11031f4, + 0xf0820027, + 0x22cf0123, + 0x0137f000, + 0xbb1f24f0, + 0x32b60432, + 0x05028001, + 0xf1060380, + 0xf0860027, + 0x22cf0123, + 0x04028000, + 0x0c30e7f1, + 0xbd50e3f0, + 0xbd34bd24, +/* 0x0421: init_unk_loop */ + 0x6821f444, + 0xf400f6b0, + 0xf7f00f0b, + 0x04f2bb01, + 0xb6054ffd, +/* 0x0436: init_unk_next */ + 0x20b60130, + 0x04e0b601, + 0xf40126b0, +/* 0x0442: init_unk_done */ + 0x0380e21b, + 0x08048007, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0xf1082595, + 0xf0c00007, + 0x05d00103, + 0xf104bd00, + 0xf0c10007, + 0x05d00103, + 0x9804bd00, + 0x0f98000e, + 0x5021f501, + 0x002fbb01, + 0x98003fbb, + 0x0f98010e, + 0x5021f502, + 0x050e9801, + 0xbb00effd, + 0x3ebb002e, + 0x020e9800, + 0xf5030f98, + 0x98015021, + 0xeffd070e, + 0x002ebb00, + 0xb6003ebb, + 0x07f10235, + 0x03f0d300, + 0x0003d001, + 0x25b604bd, + 0x0635b608, + 0xb60120b6, + 0x24b60130, + 0x0834b608, + 0xf5022fb9, + 0xbb02d321, + 0x07f1003f, + 0x03f00100, + 0x0003d002, + 0x24bd04bd, + 0xf11f29f0, + 0xf0080007, + 0x02d00203, +/* 0x04f3: main */ + 0xf404bd00, + 0x28f40031, + 0x24d7f000, + 0xf43921f4, + 0xe4b0f401, + 0x1e18f404, + 0xf00181fe, + 0x20bd0627, + 0xb60412fd, + 0x1efd01e4, + 0x0018fe05, + 0x05e821f5, +/* 0x0523: main_not_ctx_xfer */ + 0x94d30ef4, + 0xf5f010ef, + 0x7e21f501, + 0xc60ef403, +/* 0x0530: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x24d7f02c, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xf00421f4, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x057e: ih_no_fifo */ + 0x07f104bd, + 0x03f00100, + 0x000ad000, + 0xf0fc04bd, + 0xd0fce0fc, + 0xa0fcb0fc, + 0x80fc90fc, + 0xfc0088fe, + 0x0032f480, +/* 0x05a2: hub_barrier_done */ + 0xf7f001f8, + 0x040e9801, + 0xb904febb, + 0xe7f102ff, + 0xe3f09418, + 0x9d21f440, +/* 0x05ba: ctx_redswitch */ + 0xf7f000f8, + 0x0007f120, + 0x0103f085, + 0xbd000fd0, + 0x08e7f004, +/* 0x05cc: ctx_redswitch_delay */ + 0xf401e2b6, + 0xf5f1fd1b, + 0xf5f10800, + 0x07f10200, + 0x03f08500, + 0x000fd001, + 0x00f804bd, +/* 0x05e8: ctx_xfer */ + 0x810007f1, + 0xd00203f0, + 0x04bd000f, + 0xf50711f4, +/* 0x05fb: ctx_xfer_not_load */ + 0xf505ba21, + 0xbd026a21, + 0xfc07f124, + 0x0203f047, + 0xbd0002d0, + 0x012cf004, + 0xf10320b6, + 0xf04afc07, + 0x02d00203, + 0xf004bd00, + 0xa5f001ac, + 0x00b7f102, + 0x50b3f000, + 0xb6040c98, + 0xbcbb0fc4, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xacf0016f, + 0x00b7f101, + 0x50b3f040, + 0xb6040c98, + 0xbcbb0fc4, + 0x010c9800, + 0x98020d98, + 0xe7f1060f, + 0x21f50800, + 0xacf0016f, + 0x04a5f001, + 0x3000b7f1, + 0x9850b3f0, + 0xc4b6040c, + 0x00bcbb0f, + 0x98020c98, + 0x0f98030d, + 0x00e7f108, + 0x6f21f502, + 0x5e21f501, + 0x0601f402, +/* 0x0697: ctx_xfer_post */ + 0xf50712f4, +/* 0x069b: ctx_xfer_done */ + 0xf5027f21, + 0xf805a221, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 new file mode 100644 index 000000000000..90bbe525b626 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 + +#define CHIPSET GK110 +#include "macros.fuc" + +.section #nvf0_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nvf0_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h new file mode 100644 index 000000000000..1b803197d28b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h @@ -0,0 +1,537 @@ +uint32_t nvf0_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nvf0_grgpc_code[] = { + 0x03a10ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f037, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f037, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0xe0f900f8, + 0xf102ffb9, + 0xf09814e7, + 0x21f440e3, + 0x01f7f09d, + 0xf102ffb9, + 0xf09c1ce7, + 0x21f440e3, + 0xf8e0fc9d, +/* 0x03a1: init */ + 0xf104bd00, + 0xf0420017, + 0x11cf0013, + 0x0911e700, + 0x0814b601, + 0xf00014fe, + 0x07f10227, + 0x03f01200, + 0x0002d000, + 0x17f104bd, + 0x10fe0530, + 0x0007f100, + 0x0003f007, + 0xbd0000d0, + 0x0427f004, + 0x040007f1, + 0xd00003f0, + 0x04bd0002, + 0xf11031f4, + 0xf0820027, + 0x22cf0123, + 0x0137f000, + 0xbb1f24f0, + 0x32b60432, + 0x05028001, + 0xf1060380, + 0xf0860027, + 0x22cf0123, + 0x04028000, + 0x0c30e7f1, + 0xbd50e3f0, + 0xbd34bd24, +/* 0x0421: init_unk_loop */ + 0x6821f444, + 0xf400f6b0, + 0xf7f00f0b, + 0x04f2bb01, + 0xb6054ffd, +/* 0x0436: init_unk_next */ + 0x20b60130, + 0x04e0b601, + 0xf40226b0, +/* 0x0442: init_unk_done */ + 0x0380e21b, + 0x08048007, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0xf1082595, + 0xf0c00007, + 0x05d00103, + 0xf104bd00, + 0xf0c10007, + 0x05d00103, + 0x9804bd00, + 0x0f98000e, + 0x5021f501, + 0x002fbb01, + 0x98003fbb, + 0x0f98010e, + 0x5021f502, + 0x050e9801, + 0xbb00effd, + 0x3ebb002e, + 0x020e9800, + 0xf5030f98, + 0x98015021, + 0xeffd070e, + 0x002ebb00, + 0xb6003ebb, + 0x07f10235, + 0x03f0d300, + 0x0003d001, + 0x25b604bd, + 0x0635b608, + 0xb60120b6, + 0x24b60130, + 0x0834b608, + 0xf5022fb9, + 0xbb02d321, + 0x07f1003f, + 0x03f00100, + 0x0003d002, + 0x24bd04bd, + 0xf11f29f0, + 0xf0300007, + 0x02d00203, +/* 0x04f3: main */ + 0xf404bd00, + 0x28f40031, + 0x24d7f000, + 0xf43921f4, + 0xe4b0f401, + 0x1e18f404, + 0xf00181fe, + 0x20bd0627, + 0xb60412fd, + 0x1efd01e4, + 0x0018fe05, + 0x05e821f5, +/* 0x0523: main_not_ctx_xfer */ + 0x94d30ef4, + 0xf5f010ef, + 0x7e21f501, + 0xc60ef403, +/* 0x0530: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x24d7f02c, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xf00421f4, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x057e: ih_no_fifo */ + 0x07f104bd, + 0x03f00100, + 0x000ad000, + 0xf0fc04bd, + 0xd0fce0fc, + 0xa0fcb0fc, + 0x80fc90fc, + 0xfc0088fe, + 0x0032f480, +/* 0x05a2: hub_barrier_done */ + 0xf7f001f8, + 0x040e9801, + 0xb904febb, + 0xe7f102ff, + 0xe3f09418, + 0x9d21f440, +/* 0x05ba: ctx_redswitch */ + 0xf7f000f8, + 0x0007f120, + 0x0103f085, + 0xbd000fd0, + 0x08e7f004, +/* 0x05cc: ctx_redswitch_delay */ + 0xf401e2b6, + 0xf5f1fd1b, + 0xf5f10800, + 0x07f10200, + 0x03f08500, + 0x000fd001, + 0x00f804bd, +/* 0x05e8: ctx_xfer */ + 0x810007f1, + 0xd00203f0, + 0x04bd000f, + 0xf50711f4, +/* 0x05fb: ctx_xfer_not_load */ + 0xf505ba21, + 0xbd026a21, + 0xfc07f124, + 0x0203f047, + 0xbd0002d0, + 0x012cf004, + 0xf10320b6, + 0xf04afc07, + 0x02d00203, + 0xf004bd00, + 0xa5f001ac, + 0x00b7f102, + 0x50b3f000, + 0xb6040c98, + 0xbcbb0fc4, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xacf0016f, + 0x00b7f101, + 0x50b3f040, + 0xb6040c98, + 0xbcbb0fc4, + 0x010c9800, + 0x98020d98, + 0xe7f1060f, + 0x21f50800, + 0xacf0016f, + 0x04a5f001, + 0x3000b7f1, + 0x9850b3f0, + 0xc4b6040c, + 0x00bcbb0f, + 0x98020c98, + 0x0f98030d, + 0x00e7f108, + 0x6f21f502, + 0x5e21f501, + 0x0601f402, +/* 0x0697: ctx_xfer_post */ + 0xf50712f4, +/* 0x069b: ctx_xfer_done */ + 0xf5027f21, + 0xf805a221, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc new file mode 100644 index 000000000000..b4ad18bf5a26 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc @@ -0,0 +1,696 @@ +/* fuc microcode for nvc0 PGRAPH/HUB + * + * Copyright 2011 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifdef INCLUDE_DATA +hub_mmio_list_head: .b32 #hub_mmio_list_base +hub_mmio_list_tail: .b32 #hub_mmio_list_next + +gpc_count: .b32 0 +rop_count: .b32 0 +cmd_queue: queue_init + +ctx_current: .b32 0 + +.align 256 +chan_data: +chan_mmio_count: .b32 0 +chan_mmio_address: .b32 0 + +.align 256 +xfer_data: .skip 256 + +hub_mmio_list_base: +.b32 0x0417e91c // 0x17e91c, 2 +hub_mmio_list_next: +#endif + +#ifdef INCLUDE_CODE +// reports an exception to the host +// +// In: $r15 error code (see os.h) +// +error: + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) + mov $r15 1 + nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15) + ret + +// HUB fuc initialisation, executed by triggering ucode start, will +// fall through to main loop after completion. +// +// Output: +// CC_SCRATCH[0]: +// 31:31: set to signal completion +// CC_SCRATCH[1]: +// 31:0: total PGRAPH context size +// +init: + clear b32 $r0 + mov $xdbase $r0 + + // setup stack + nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0) + extr $r1 $r1 9:17 + shl b32 $r1 8 + mov $sp $r1 + + // enable fifo access + mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO + nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2) + + // setup i0 handler, and route all interrupts to it + mov $r1 #ih + mov $iv0 $r1 + + clear b32 $r2 + nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2) + + // route HUB_CHSW_PULSE to fuc interrupt 8 + mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8 + nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2) + + // not sure what these are, route them because NVIDIA does, and + // the IRQ handler will signal the host if we ever get one.. we + // may find out if/why we need to handle these if so.. + // + mov $r2 0x2004 // { 0x04, ZERO } -> intr 9 + nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2) + mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10 + nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2) + mov $r2 0x200c // { 0x0c, ZERO } -> intr 15 + nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2) + + // enable all INTR_UP interrupts + sub b32 $r3 $r0 1 + nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3) + + // enable fifo, ctxsw, 9, fwmthd, 15 interrupts + imm32($r2, 0x8704) + nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2) + + // fifo level triggered, rest edge + mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL + nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2) + + // enable interrupts + bset $flags ie0 + + // fetch enabled GPC/ROP counts + nv_rd32($r14, 0x409604) + extr $r1 $r15 16:20 + st b32 D[$r0 + #rop_count] $r1 + and $r15 0x1f + st b32 D[$r0 + #gpc_count] $r15 + + // set BAR_REQMASK to GPC mask + mov $r1 1 + shl b32 $r1 $r15 + sub b32 $r1 1 + nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1) + nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1) + + // context size calculation, reserve first 256 bytes for use by fuc + mov $r1 256 + + // + mov $r15 2 + call(ctx_4170s) + call(ctx_4170w) + mov $r15 0x10 + call(ctx_86c) + + // calculate size of mmio context data + ld b32 $r14 D[$r0 + #hub_mmio_list_head] + ld b32 $r15 D[$r0 + #hub_mmio_list_tail] + call(mmctx_size) + + // set mmctx base addresses now so we don't have to do it later, + // they don't (currently) ever change + shr b32 $r4 $r1 8 + nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4) + nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4) + add b32 $r3 0x1300 + add b32 $r1 $r15 + shr b32 $r15 2 + nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf?? + + // strands, base offset needs to be aligned to 256 bytes + shr b32 $r1 8 + add b32 $r1 1 + shl b32 $r1 8 + mov b32 $r15 $r1 + call(strand_ctx_init) + add b32 $r1 $r15 + + // initialise each GPC in sequence by passing in the offset of its + // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which + // has previously been uploaded by the host) running. + // + // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31 + // when it has completed, and return the size of its context data + // in GPCn_CC_SCRATCH[1] + // + ld b32 $r3 D[$r0 + #gpc_count] + imm32($r4, 0x502000) + init_gpc: + // setup, and start GPC ucode running + add b32 $r14 $r4 0x804 + mov b32 $r15 $r1 + call(nv_wr32) // CC_SCRATCH[1] = ctx offset + add b32 $r14 $r4 0x10c + clear b32 $r15 + call(nv_wr32) + add b32 $r14 $r4 0x104 + call(nv_wr32) // ENTRY + add b32 $r14 $r4 0x100 + mov $r15 2 // CTRL_START_TRIGGER + call(nv_wr32) // CTRL + + // wait for it to complete, and adjust context size + add b32 $r14 $r4 0x800 + init_gpc_wait: + call(nv_rd32) + xbit $r15 $r15 31 + bra e #init_gpc_wait + add b32 $r14 $r4 0x804 + call(nv_rd32) + add b32 $r1 $r15 + + // next! + add b32 $r4 0x8000 + sub b32 $r3 1 + bra ne #init_gpc + + // + mov $r15 0 + call(ctx_86c) + mov $r15 0 + call(ctx_4170s) + + // save context size, and tell host we're ready + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) + clear b32 $r1 + bset $r1 31 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1) + +// Main program loop, very simple, sleeps until woken up by the interrupt +// handler, pulls a command from the queue and executes its handler +// +main: + // sleep until we have something to do + bset $flags $p0 + sleep $p0 + mov $r13 #cmd_queue + call(queue_get) + bra $p1 #main + + // context switch, requested by GPU? + cmpu b32 $r14 0x4001 + bra ne #main_not_ctx_switch + trace_set(T_AUTO) + nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0) + nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0) + + xbit $r3 $r1 31 + bra e #chsw_no_prev + xbit $r3 $r2 31 + bra e #chsw_prev_no_next + push $r2 + mov b32 $r2 $r1 + trace_set(T_SAVE) + bclr $flags $p1 + bset $flags $p2 + call(ctx_xfer) + trace_clr(T_SAVE); + pop $r2 + trace_set(T_LOAD); + bset $flags $p1 + call(ctx_xfer) + trace_clr(T_LOAD); + bra #chsw_done + chsw_prev_no_next: + push $r2 + mov b32 $r2 $r1 + bclr $flags $p1 + bclr $flags $p2 + call(ctx_xfer) + pop $r2 + nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) + bra #chsw_done + chsw_no_prev: + xbit $r3 $r2 31 + bra e #chsw_done + bset $flags $p1 + bclr $flags $p2 + call(ctx_xfer) + + // ack the context switch request + chsw_done: + mov $r2 NV_PGRAPH_FECS_CHSW_ACK + nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2) + trace_clr(T_AUTO) + bra #main + + // request to set current channel? (*not* a context switch) + main_not_ctx_switch: + cmpu b32 $r14 0x0001 + bra ne #main_not_ctx_chan + mov b32 $r2 $r15 + call(ctx_chan) + bra #main_done + + // request to store current channel context? + main_not_ctx_chan: + cmpu b32 $r14 0x0002 + bra ne #main_not_ctx_save + trace_set(T_SAVE) + bclr $flags $p1 + bclr $flags $p2 + call(ctx_xfer) + trace_clr(T_SAVE) + bra #main_done + + main_not_ctx_save: + shl b32 $r15 $r14 16 + or $r15 E_BAD_COMMAND + call(error) + bra #main + + main_done: + clear b32 $r2 + bset $r2 31 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2) + bra #main + +// interrupt handler +ih: + push $r8 + mov $r8 $flags + push $r8 + push $r9 + push $r10 + push $r11 + push $r13 + push $r14 + push $r15 + clear b32 $r0 + + // incoming fifo command? + nv_iord($r10, NV_PGRAPH_FECS_INTR, 0) + and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO + bra e #ih_no_fifo + // queue incoming fifo command for later processing + mov $r13 #cmd_queue + nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0) + nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0) + call(queue_put) + add b32 $r11 0x400 + mov $r14 1 + nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14) + + // context switch request? + ih_no_fifo: + and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW + bra e #ih_no_ctxsw + // enqueue a context switch for later processing + mov $r13 #cmd_queue + mov $r14 0x4001 + call(queue_put) + + // firmware method? + ih_no_ctxsw: + and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD + bra e #ih_no_fwmthd + // none we handle; report to host and ack + nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO) + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15) + nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR) + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15) + extr $r14 $r15 16:18 + shl b32 $r14 $r14 2 + imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0)) + add b32 $r14 $r15 + call(nv_rd32) + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15) + mov $r15 E_BAD_FWMTHD + call(error) + mov $r11 0x100 + nv_wr32(0x400144, $r11) + + // anything we didn't handle, bring it to the host's attention + ih_no_fwmthd: + mov $r11 0x504 // FIFO | CHSW | FWMTHD + not b32 $r11 + and $r11 $r10 $r11 + bra e #ih_no_other + nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11) + + // ack, and wake up main() + ih_no_other: + nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10) + + pop $r15 + pop $r14 + pop $r13 + pop $r11 + pop $r10 + pop $r9 + pop $r8 + mov $flags $r8 + pop $r8 + bclr $flags $p0 + iret + +#if CHIPSET < GK100 +// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done +ctx_4160s: + mov $r15 1 + nv_wr32(0x404160, $r15) + ctx_4160s_wait: + nv_rd32($r15, 0x404160) + xbit $r15 $r15 4 + bra e #ctx_4160s_wait + ret + +// Without clearing again at end of xfer, some things cause PGRAPH +// to hang with STATUS=0x00000007 until it's cleared.. fbcon can +// still function with it set however... +ctx_4160c: + clear b32 $r15 + nv_wr32(0x404160, $r15) + ret +#endif + +// Again, not real sure +// +// In: $r15 value to set 0x404170 to +// +ctx_4170s: + or $r15 0x10 + nv_wr32(0x404170, $r15) + ret + +// Waits for a ctx_4170s() call to complete +// +ctx_4170w: + nv_rd32($r15, 0x404170) + and $r15 0x10 + bra ne #ctx_4170w + ret + +// Disables various things, waits a bit, and re-enables them.. +// +// Not sure how exactly this helps, perhaps "ENABLE" is not such a +// good description for the bits we turn off? Anyways, without this, +// funny things happen. +// +ctx_redswitch: + mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC + or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP + or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC + or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN + nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) + mov $r15 8 + ctx_redswitch_delay: + sub b32 $r15 1 + bra ne #ctx_redswitch_delay + or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP + or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN + nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) + ret + +// Not a clue what this is for, except that unless the value is 0x10, the +// strand context is saved (and presumably restored) incorrectly.. +// +// In: $r15 value to set to (0x00/0x10 are used) +// +ctx_86c: + nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15) + nv_wr32(0x408a14, $r15) + nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15) + ret + +// In: $r15 NV_PGRAPH_FECS_MEM_CMD_* +ctx_mem: + nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15) + ctx_mem_wait: + nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0) + or $r15 $r15 + bra ne #ctx_mem_wait + ret + +// ctx_load - load's a channel's ctxctl data, and selects its vm +// +// In: $r2 channel address +// +ctx_load: + trace_set(T_CHAN) + + // switch to channel, somewhat magic in parts.. + mov $r10 12 // DONE_UNK12 + call(wait_donez) + clear b32 $r15 + nv_iowr(0x409a24, 0, $r15) + nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2) + nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2) + mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN + call(ctx_mem) + nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) + + // load channel header, fetch PGRAPH context pointer + mov $xtargets $r0 + bclr $r2 31 + shl b32 $r2 4 + add b32 $r2 2 + + trace_set(T_LCHAN) + nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2) + imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31) + or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM + nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) + mov $r1 0x10 // chan + 0x0210 + mov $r2 #xfer_data + sethi $r2 0x00020000 // 16 bytes + xdld $r1 $r2 + xdwait + trace_clr(T_LCHAN) + + // update current context + ld b32 $r1 D[$r0 + #xfer_data + 4] + shl b32 $r1 24 + ld b32 $r2 D[$r0 + #xfer_data + 0] + shr b32 $r2 8 + or $r1 $r2 + st b32 D[$r0 + #ctx_current] $r1 + + // set transfer base to start of context, and fetch context header + trace_set(T_LCTXH) + nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1) + mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM + nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) + mov $r1 #chan_data + sethi $r1 0x00060000 // 256 bytes + xdld $r0 $r1 + xdwait + trace_clr(T_LCTXH) + + trace_clr(T_CHAN) + ret + +// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as +// the active channel for ctxctl, but not actually transfer +// any context data. intended for use only during initial +// context construction. +// +// In: $r2 channel address +// +ctx_chan: +#if CHIPSET < GK100 + call(ctx_4160s) +#endif + call(ctx_load) + mov $r10 12 // DONE_UNK12 + call(wait_donez) + mov $r15 5 // MEM_CMD 5 ??? + call(ctx_mem) +#if CHIPSET < GK100 + call(ctx_4160c) +#endif + ret + +// Execute per-context state overrides list +// +// Only executed on the first load of a channel. Might want to look into +// removing this and having the host directly modify the channel's context +// to change this state... The nouveau DRM already builds this list as +// it's definitely needed for NVIDIA's, so we may as well use it for now +// +// Input: $r1 mmio list length +// +ctx_mmio_exec: + // set transfer base to be the mmio list + ld b32 $r3 D[$r0 + #chan_mmio_address] + nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) + + clear b32 $r3 + ctx_mmio_loop: + // fetch next 256 bytes of mmio list if necessary + and $r4 $r3 0xff + bra ne #ctx_mmio_pull + mov $r5 #xfer_data + sethi $r5 0x00060000 // 256 bytes + xdld $r3 $r5 + xdwait + + // execute a single list entry + ctx_mmio_pull: + ld b32 $r14 D[$r4 + #xfer_data + 0x00] + ld b32 $r15 D[$r4 + #xfer_data + 0x04] + call(nv_wr32) + + // next! + add b32 $r3 8 + sub b32 $r1 1 + bra ne #ctx_mmio_loop + + // set transfer base back to the current context + ctx_mmio_done: + ld b32 $r3 D[$r0 + #ctx_current] + nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) + + // disable the mmio list now, we don't need/want to execute it again + st b32 D[$r0 + #chan_mmio_count] $r0 + mov $r1 #chan_data + sethi $r1 0x00060000 // 256 bytes + xdst $r0 $r1 + xdwait + ret + +// Transfer HUB context data between GPU and storage area +// +// In: $r2 channel address +// $p1 clear on save, set on load +// $p2 set if opposite direction done/will be done, so: +// on save it means: "a load will follow this save" +// on load it means: "a save preceeded this load" +// +ctx_xfer: + // according to mwk, some kind of wait for idle + mov $r14 4 + nv_iowr(0x409c08, 0, $r14) + ctx_xfer_idle: + nv_iord($r14, 0x409c00, 0) + and $r14 0x2000 + bra ne #ctx_xfer_idle + + bra not $p1 #ctx_xfer_pre + bra $p2 #ctx_xfer_pre_load + ctx_xfer_pre: + mov $r15 0x10 + call(ctx_86c) +#if CHIPSET < GK100 + call(ctx_4160s) +#endif + bra not $p1 #ctx_xfer_exec + + ctx_xfer_pre_load: + mov $r15 2 + call(ctx_4170s) + call(ctx_4170w) + call(ctx_redswitch) + clear b32 $r15 + call(ctx_4170s) + call(ctx_load) + + // fetch context pointer, and initiate xfer on all GPCs + ctx_xfer_exec: + ld b32 $r1 D[$r0 + #ctx_current] + + clear b32 $r2 + nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2) + + nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer + xbit $r15 $flags $p1 + xbit $r2 $flags $p2 + shl b32 $r2 1 + or $r15 $r2 + nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) + + // strands + call(strand_pre) + clear b32 $r2 + nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2) + xbit $r2 $flags $p1 // SAVE/LOAD + add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE + nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2) + + // mmio context + xbit $r10 $flags $p1 // direction + or $r10 6 // first, last + mov $r11 0 // base = 0 + ld b32 $r12 D[$r0 + #hub_mmio_list_head] + ld b32 $r13 D[$r0 + #hub_mmio_list_tail] + mov $r14 0 // not multi + call(mmctx_xfer) + + // wait for GPCs to all complete + mov $r10 8 // DONE_BAR + call(wait_doneo) + + // wait for strand xfer to complete + call(strand_wait) + + // post-op + bra $p1 #ctx_xfer_post + mov $r10 12 // DONE_UNK12 + call(wait_donez) + mov $r15 5 // MEM_CMD 5 ??? + call(ctx_mem) + + bra $p2 #ctx_xfer_done + ctx_xfer_post: + mov $r15 2 + call(ctx_4170s) + clear b32 $r15 + call(ctx_86c) + call(strand_post) + call(ctx_4170w) + clear b32 $r15 + call(ctx_4170s) + + bra not $p1 #ctx_xfer_no_post_mmio + ld b32 $r1 D[$r0 + #chan_mmio_count] + or $r1 $r1 + bra e #ctx_xfer_no_post_mmio + call(ctx_mmio_exec) + + ctx_xfer_no_post_mmio: +#if CHIPSET < GK100 + call(ctx_4160c) +#endif + + ctx_xfer_done: + ret +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 new file mode 100644 index 000000000000..27591b3086a5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define CHIPSET GK208 +#include "macros.fuc" + +.section #gm107_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #gm107_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h new file mode 100644 index 000000000000..5f953c5c20b7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h @@ -0,0 +1,916 @@ +uint32_t gm107_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t gm107_grhub_code[] = { + 0x030e0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0xf489a408, + 0x020f0b1b, + 0x0002f87e, +/* 0x001a: queue_put_next */ + 0x98c400f8, + 0x0384b607, + 0xb6008dbb, + 0x8eb50880, + 0x018fb500, + 0xf00190b6, + 0xd9b50f94, +/* 0x0037: queue_get */ + 0xf400f801, + 0xd8980131, + 0x01d99800, + 0x0bf489a4, + 0x0789c421, + 0xbb0394b6, + 0x90b6009d, + 0x009e9808, + 0xb6019f98, + 0x84f00180, + 0x00d8b50f, +/* 0x0063: queue_get_done */ + 0xf80132f4, +/* 0x0065: nv_rd32 */ + 0xf0ecb200, + 0x00801fc9, + 0x0cf601ca, +/* 0x0073: nv_rd32_wait */ + 0x8c04bd00, + 0xcf01ca00, + 0xccc800cc, + 0xf61bf41f, + 0xec7e060a, + 0x008f0000, + 0xffcf01cb, +/* 0x008f: nv_wr32 */ + 0x8000f800, + 0xf601cc00, + 0x04bd000f, + 0xc9f0ecb2, + 0x1ec9f01f, + 0x01ca0080, + 0xbd000cf6, +/* 0x00a9: nv_wr32_wait */ + 0xca008c04, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f61b, +/* 0x00b8: wait_donez */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x00cf: wait_donez_ne */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf61bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x00ec: wait_doneo */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x0103: wait_doneo_e */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf60bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x0120: mmctx_size */ +/* 0x0122: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0x1bf4efa4, + 0xf89fb2ec, +/* 0x013d: mmctx_xfer */ + 0xf094bd00, + 0x00800199, + 0x09f60237, + 0xbd04bd00, + 0x05bbfd94, + 0x800f0bf4, + 0xf601c400, + 0x04bd000b, +/* 0x015f: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0xc6008018, + 0x000ef601, + 0x008004bd, + 0x0ff601c7, + 0xf004bd00, +/* 0x017a: mmctx_multi_disabled */ + 0xabc80199, + 0x10b4b600, + 0xc80cb9f0, + 0xe4b601ae, + 0x05befd11, + 0x01c50080, + 0xbd000bf6, +/* 0x0195: mmctx_exec_loop */ +/* 0x0195: mmctx_wait_free */ + 0xc5008e04, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f60b, + 0x05e9fd00, + 0x01c80080, + 0xbd000ef6, + 0x04c0b604, + 0x1bf4cda4, + 0x02abc8df, +/* 0x01bf: mmctx_fini_wait */ + 0x8b1c1bf4, + 0xcf01c500, + 0xb4f000bb, + 0x10b4b01f, + 0x0af31bf4, + 0x00b87e05, + 0x250ef400, +/* 0x01d8: mmctx_stop */ + 0xb600abc8, + 0xb9f010b4, + 0x12b9f00c, + 0x01c50080, + 0xbd000bf6, +/* 0x01ed: mmctx_stop_wait */ + 0xc5008b04, + 0x00bbcf01, + 0xf412bbc8, +/* 0x01fa: mmctx_done */ + 0x94bdf61b, + 0x800199f0, + 0xf6021700, + 0x04bd0009, +/* 0x020a: strand_wait */ + 0xa0f900f8, + 0xb87e020a, + 0xa0fc0000, +/* 0x0216: strand_pre */ + 0x0c0900f8, + 0x024afc80, + 0xbd0009f6, + 0x020a7e04, +/* 0x0227: strand_post */ + 0x0900f800, + 0x4afc800d, + 0x0009f602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0238: strand_set */ + 0xfc800f0c, + 0x0cf6024f, + 0x0c04bd00, + 0x4afc800b, + 0x000cf602, + 0xfc8004bd, + 0x0ef6024f, + 0x0c04bd00, + 0x4afc800a, + 0x000cf602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0268: strand_ctx_init */ + 0x99f094bd, + 0x37008003, + 0x0009f602, + 0x167e04bd, + 0x030e0002, + 0x0002387e, + 0xfc80c4bd, + 0x0cf60247, + 0x0c04bd00, + 0x4afc8001, + 0x000cf602, + 0x0a7e04bd, + 0x0c920002, + 0x46fc8001, + 0x000cf602, + 0x020c04bd, + 0x024afc80, + 0xbd000cf6, + 0x020a7e04, + 0x02277e00, + 0x42008800, + 0x20008902, + 0x0099cf02, +/* 0x02c7: ctx_init_strand_loop */ + 0xf608fe95, + 0x8ef6008e, + 0x808acf40, + 0xb606a5b6, + 0xeabb01a0, + 0x0480b600, + 0xf40192b6, + 0xe4b6e81b, + 0xf2efbc08, + 0x99f094bd, + 0x17008003, + 0x0009f602, + 0x00f804bd, +/* 0x02f8: error */ + 0x02050080, + 0xbd000ff6, + 0x80010f04, + 0xf6030700, + 0x04bd000f, +/* 0x030e: init */ + 0x04bd00f8, + 0x410007fe, + 0x11cf4200, + 0x0911e700, + 0x0814b601, + 0x020014fe, + 0x12004002, + 0xbd0002f6, + 0x05c94104, + 0xbd0010fe, + 0x07004024, + 0xbd0002f6, + 0x20034204, + 0x01010080, + 0xbd0002f6, + 0x20044204, + 0x01010480, + 0xbd0002f6, + 0x200b4204, + 0x01010880, + 0xbd0002f6, + 0x200c4204, + 0x01011c80, + 0xbd0002f6, + 0x01039204, + 0x03090080, + 0xbd0003f6, + 0x87044204, + 0xf6040040, + 0x04bd0002, + 0x00400402, + 0x0002f603, + 0x31f404bd, + 0x96048e10, + 0x00657e40, + 0xc7feb200, + 0x01b590f1, + 0x1ff4f003, + 0x01020fb5, + 0x041fbb01, + 0x800112b6, + 0xf6010300, + 0x04bd0001, + 0x01040080, + 0xbd0001f6, + 0x01004104, + 0xa87e020f, + 0xb77e0006, + 0x100f0006, + 0x0006f97e, + 0x98000e98, + 0x207e010f, + 0x14950001, + 0xc0008008, + 0x0004f601, + 0x008004bd, + 0x04f601c1, + 0xb704bd00, + 0xbb130030, + 0xf5b6001f, + 0xd3008002, + 0x000ff601, + 0x15b604bd, + 0x0110b608, + 0xb20814b6, + 0x02687e1f, + 0x001fbb00, + 0x84020398, +/* 0x041f: init_gpc */ + 0xb8502000, + 0x0008044e, + 0x8f7e1fb2, + 0x4eb80000, + 0xbd00010c, + 0x008f7ef4, + 0x044eb800, + 0x8f7e0001, + 0x4eb80000, + 0x0f000100, + 0x008f7e02, + 0x004eb800, +/* 0x044e: init_gpc_wait */ + 0x657e0008, + 0xffc80000, + 0xf90bf41f, + 0x08044eb8, + 0x00657e00, + 0x001fbb00, + 0x800040b7, + 0xf40132b6, + 0x000fb41b, + 0x0006f97e, + 0xa87e000f, + 0x00800006, + 0x01f60201, + 0xbd04bd00, + 0x1f19f014, + 0x02300080, + 0xbd0001f6, +/* 0x0491: main */ + 0x0031f404, + 0x0d0028f4, + 0x00377e10, + 0xf401f400, + 0x4001e4b1, + 0x00c71bf5, + 0x99f094bd, + 0x37008004, + 0x0009f602, + 0x008104bd, + 0x11cf02c0, + 0xc1008200, + 0x0022cf02, + 0xf41f13c8, + 0x23c8770b, + 0x550bf41f, + 0x12b220f9, + 0x99f094bd, + 0x37008007, + 0x0009f602, + 0x32f404bd, + 0x0231f401, + 0x00087c7e, + 0x99f094bd, + 0x17008007, + 0x0009f602, + 0x20fc04bd, + 0x99f094bd, + 0x37008006, + 0x0009f602, + 0x31f404bd, + 0x087c7e01, + 0xf094bd00, + 0x00800699, + 0x09f60217, + 0xf404bd00, +/* 0x0522: chsw_prev_no_next */ + 0x20f92f0e, + 0x32f412b2, + 0x0232f401, + 0x00087c7e, + 0x008020fc, + 0x02f602c0, + 0xf404bd00, +/* 0x053e: chsw_no_prev */ + 0x23c8130e, + 0x0d0bf41f, + 0xf40131f4, + 0x7c7e0232, +/* 0x054e: chsw_done */ + 0x01020008, + 0x02c30080, + 0xbd0002f6, + 0xf094bd04, + 0x00800499, + 0x09f60217, + 0xf504bd00, +/* 0x056b: main_not_ctx_switch */ + 0xb0ff2a0e, + 0x1bf401e4, + 0x7ef2b20c, + 0xf400081c, +/* 0x057a: main_not_ctx_chan */ + 0xe4b0400e, + 0x2c1bf402, + 0x99f094bd, + 0x37008007, + 0x0009f602, + 0x32f404bd, + 0x0232f401, + 0x00087c7e, + 0x99f094bd, + 0x17008007, + 0x0009f602, + 0x0ef404bd, +/* 0x05a9: main_not_ctx_save */ + 0x10ef9411, + 0x7e01f5f0, + 0xf50002f8, +/* 0x05b7: main_done */ + 0xbdfede0e, + 0x1f29f024, + 0x02300080, + 0xbd0002f6, + 0xcc0ef504, +/* 0x05c9: ih */ + 0xfe80f9fe, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x004a04bd, + 0x00aacf02, + 0xf404abc4, + 0x100d230b, + 0xcf1a004e, + 0x004f00ee, + 0x00ffcf19, + 0x0000047e, + 0x0400b0b7, + 0x0040010e, + 0x000ef61d, +/* 0x060a: ih_no_fifo */ + 0xabe404bd, + 0x0bf40100, + 0x4e100d0c, + 0x047e4001, +/* 0x061a: ih_no_ctxsw */ + 0xabe40000, + 0x0bf40400, + 0x07088e56, + 0x00657e40, + 0x80ffb200, + 0xf6020400, + 0x04bd000f, + 0x4007048e, + 0x0000657e, + 0x0080ffb2, + 0x0ff60203, + 0xc704bd00, + 0xee9450fe, + 0x07008f02, + 0x00efbb40, + 0x0000657e, + 0x02020080, + 0xbd000ff6, + 0x7e030f04, + 0x4b0002f8, + 0xbfb20100, + 0x4001448e, + 0x00008f7e, +/* 0x0674: ih_no_fwmthd */ + 0xbd05044b, + 0xb4abffb0, + 0x800c0bf4, + 0xf6030700, + 0x04bd000b, +/* 0x0688: ih_no_other */ + 0xf6010040, + 0x04bd000a, + 0xe0fcf0fc, + 0xb0fcd0fc, + 0x90fca0fc, + 0x88fe80fc, + 0xf480fc00, + 0x01f80032, +/* 0x06a8: ctx_4170s */ + 0xb210f5f0, + 0x41708eff, + 0x008f7e40, +/* 0x06b7: ctx_4170w */ + 0x8e00f800, + 0x7e404170, + 0xb2000065, + 0x10f4f0ff, + 0xf8f31bf4, +/* 0x06c9: ctx_redswitch */ + 0x02004e00, + 0xf040e5f0, + 0xe5f020e5, + 0x85008010, + 0x000ef601, + 0x080f04bd, +/* 0x06e0: ctx_redswitch_delay */ + 0xf401f2b6, + 0xe5f1fd1b, + 0xe5f10400, + 0x00800100, + 0x0ef60185, + 0xf804bd00, +/* 0x06f9: ctx_86c */ + 0x23008000, + 0x000ff602, + 0xffb204bd, + 0x408a148e, + 0x00008f7e, + 0x8c8effb2, + 0x8f7e41a8, + 0x00f80000, +/* 0x0718: ctx_mem */ + 0x02840080, + 0xbd000ff6, +/* 0x0721: ctx_mem_wait */ + 0x84008f04, + 0x00ffcf02, + 0xf405fffd, + 0x00f8f61b, +/* 0x0730: ctx_load */ + 0x99f094bd, + 0x37008005, + 0x0009f602, + 0x0c0a04bd, + 0x0000b87e, + 0x0080f4bd, + 0x0ff60289, + 0x8004bd00, + 0xf602c100, + 0x04bd0002, + 0x02830080, + 0xbd0002f6, + 0x7e070f04, + 0x80000718, + 0xf602c000, + 0x04bd0002, + 0xf0000bfe, + 0x24b61f2a, + 0x0220b604, + 0x99f094bd, + 0x37008008, + 0x0009f602, + 0x008004bd, + 0x02f60281, + 0xd204bd00, + 0x80000000, + 0x800225f0, + 0xf6028800, + 0x04bd0002, + 0x00421001, + 0x0223f002, + 0xf80512fa, + 0xf094bd03, + 0x00800899, + 0x09f60217, + 0x9804bd00, + 0x14b68101, + 0x80029818, + 0xfd0825b6, + 0x01b50512, + 0xf094bd16, + 0x00800999, + 0x09f60237, + 0x8004bd00, + 0xf6028100, + 0x04bd0001, + 0x00800102, + 0x02f60288, + 0x4104bd00, + 0x13f00100, + 0x0501fa06, + 0x94bd03f8, + 0x800999f0, + 0xf6021700, + 0x04bd0009, + 0x99f094bd, + 0x17008005, + 0x0009f602, + 0x00f804bd, +/* 0x081c: ctx_chan */ + 0x0007307e, + 0xb87e0c0a, + 0x050f0000, + 0x0007187e, +/* 0x082e: ctx_mmio_exec */ + 0x039800f8, + 0x81008041, + 0x0003f602, + 0x34bd04bd, +/* 0x083c: ctx_mmio_loop */ + 0xf4ff34c4, + 0x00450e1b, + 0x0653f002, + 0xf80535fa, +/* 0x084d: ctx_mmio_pull */ + 0x804e9803, + 0x7e814f98, + 0xb600008f, + 0x12b60830, + 0xdf1bf401, +/* 0x0860: ctx_mmio_done */ + 0x80160398, + 0xf6028100, + 0x04bd0003, + 0x414000b5, + 0x13f00100, + 0x0601fa06, + 0x00f803f8, +/* 0x087c: ctx_xfer */ + 0x0080040e, + 0x0ef60302, +/* 0x0887: ctx_xfer_idle */ + 0x8e04bd00, + 0xcf030000, + 0xe4f100ee, + 0x1bf42000, + 0x0611f4f5, +/* 0x089b: ctx_xfer_pre */ + 0x0f0c02f4, + 0x06f97e10, + 0x1b11f400, +/* 0x08a4: ctx_xfer_pre_load */ + 0xa87e020f, + 0xb77e0006, + 0xc97e0006, + 0xf4bd0006, + 0x0006a87e, + 0x0007307e, +/* 0x08bc: ctx_xfer_exec */ + 0xbd160198, + 0x05008024, + 0x0002f601, + 0x1fb204bd, + 0x41a5008e, + 0x00008f7e, + 0xf001fcf0, + 0x24b6022c, + 0x05f2fd01, + 0x048effb2, + 0x8f7e41a5, + 0x167e0000, + 0x24bd0002, + 0x0247fc80, + 0xbd0002f6, + 0x012cf004, + 0x800320b6, + 0xf6024afc, + 0x04bd0002, + 0xf001acf0, + 0x000b06a5, + 0x98000c98, + 0x000e010d, + 0x00013d7e, + 0xec7e080a, + 0x0a7e0000, + 0x01f40002, + 0x7e0c0a12, + 0x0f0000b8, + 0x07187e05, + 0x2d02f400, +/* 0x0938: ctx_xfer_post */ + 0xa87e020f, + 0xf4bd0006, + 0x0006f97e, + 0x0002277e, + 0x0006b77e, + 0xa87ef4bd, + 0x11f40006, + 0x40019810, + 0xf40511fd, + 0x2e7e070b, +/* 0x0962: ctx_xfer_no_post_mmio */ +/* 0x0962: ctx_xfer_done */ + 0x00f80008, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 new file mode 100644 index 000000000000..7c5d25630fa8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define CHIPSET GK208 +#include "macros.fuc" + +.section #nv108_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nv108_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h new file mode 100644 index 000000000000..e49b5a877ae4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h @@ -0,0 +1,916 @@ +uint32_t nv108_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nv108_grhub_code[] = { + 0x030e0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0xf489a408, + 0x020f0b1b, + 0x0002f87e, +/* 0x001a: queue_put_next */ + 0x98c400f8, + 0x0384b607, + 0xb6008dbb, + 0x8eb50880, + 0x018fb500, + 0xf00190b6, + 0xd9b50f94, +/* 0x0037: queue_get */ + 0xf400f801, + 0xd8980131, + 0x01d99800, + 0x0bf489a4, + 0x0789c421, + 0xbb0394b6, + 0x90b6009d, + 0x009e9808, + 0xb6019f98, + 0x84f00180, + 0x00d8b50f, +/* 0x0063: queue_get_done */ + 0xf80132f4, +/* 0x0065: nv_rd32 */ + 0xf0ecb200, + 0x00801fc9, + 0x0cf601ca, +/* 0x0073: nv_rd32_wait */ + 0x8c04bd00, + 0xcf01ca00, + 0xccc800cc, + 0xf61bf41f, + 0xec7e060a, + 0x008f0000, + 0xffcf01cb, +/* 0x008f: nv_wr32 */ + 0x8000f800, + 0xf601cc00, + 0x04bd000f, + 0xc9f0ecb2, + 0x1ec9f01f, + 0x01ca0080, + 0xbd000cf6, +/* 0x00a9: nv_wr32_wait */ + 0xca008c04, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f61b, +/* 0x00b8: wait_donez */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x00cf: wait_donez_ne */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf61bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x00ec: wait_doneo */ + 0x99f094bd, + 0x37008000, + 0x0009f602, + 0x008004bd, + 0x0af60206, +/* 0x0103: wait_doneo_e */ + 0x8804bd00, + 0xcf010000, + 0x8aff0088, + 0xf60bf488, + 0x99f094bd, + 0x17008000, + 0x0009f602, + 0x00f804bd, +/* 0x0120: mmctx_size */ +/* 0x0122: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0x1bf4efa4, + 0xf89fb2ec, +/* 0x013d: mmctx_xfer */ + 0xf094bd00, + 0x00800199, + 0x09f60237, + 0xbd04bd00, + 0x05bbfd94, + 0x800f0bf4, + 0xf601c400, + 0x04bd000b, +/* 0x015f: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0xc6008018, + 0x000ef601, + 0x008004bd, + 0x0ff601c7, + 0xf004bd00, +/* 0x017a: mmctx_multi_disabled */ + 0xabc80199, + 0x10b4b600, + 0xc80cb9f0, + 0xe4b601ae, + 0x05befd11, + 0x01c50080, + 0xbd000bf6, +/* 0x0195: mmctx_exec_loop */ +/* 0x0195: mmctx_wait_free */ + 0xc5008e04, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f60b, + 0x05e9fd00, + 0x01c80080, + 0xbd000ef6, + 0x04c0b604, + 0x1bf4cda4, + 0x02abc8df, +/* 0x01bf: mmctx_fini_wait */ + 0x8b1c1bf4, + 0xcf01c500, + 0xb4f000bb, + 0x10b4b01f, + 0x0af31bf4, + 0x00b87e05, + 0x250ef400, +/* 0x01d8: mmctx_stop */ + 0xb600abc8, + 0xb9f010b4, + 0x12b9f00c, + 0x01c50080, + 0xbd000bf6, +/* 0x01ed: mmctx_stop_wait */ + 0xc5008b04, + 0x00bbcf01, + 0xf412bbc8, +/* 0x01fa: mmctx_done */ + 0x94bdf61b, + 0x800199f0, + 0xf6021700, + 0x04bd0009, +/* 0x020a: strand_wait */ + 0xa0f900f8, + 0xb87e020a, + 0xa0fc0000, +/* 0x0216: strand_pre */ + 0x0c0900f8, + 0x024afc80, + 0xbd0009f6, + 0x020a7e04, +/* 0x0227: strand_post */ + 0x0900f800, + 0x4afc800d, + 0x0009f602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0238: strand_set */ + 0xfc800f0c, + 0x0cf6024f, + 0x0c04bd00, + 0x4afc800b, + 0x000cf602, + 0xfc8004bd, + 0x0ef6024f, + 0x0c04bd00, + 0x4afc800a, + 0x000cf602, + 0x0a7e04bd, + 0x00f80002, +/* 0x0268: strand_ctx_init */ + 0x99f094bd, + 0x37008003, + 0x0009f602, + 0x167e04bd, + 0x030e0002, + 0x0002387e, + 0xfc80c4bd, + 0x0cf60247, + 0x0c04bd00, + 0x4afc8001, + 0x000cf602, + 0x0a7e04bd, + 0x0c920002, + 0x46fc8001, + 0x000cf602, + 0x020c04bd, + 0x024afc80, + 0xbd000cf6, + 0x020a7e04, + 0x02277e00, + 0x42008800, + 0x20008902, + 0x0099cf02, +/* 0x02c7: ctx_init_strand_loop */ + 0xf608fe95, + 0x8ef6008e, + 0x808acf40, + 0xb606a5b6, + 0xeabb01a0, + 0x0480b600, + 0xf40192b6, + 0xe4b6e81b, + 0xf2efbc08, + 0x99f094bd, + 0x17008003, + 0x0009f602, + 0x00f804bd, +/* 0x02f8: error */ + 0x02050080, + 0xbd000ff6, + 0x80010f04, + 0xf6030700, + 0x04bd000f, +/* 0x030e: init */ + 0x04bd00f8, + 0x410007fe, + 0x11cf4200, + 0x0911e700, + 0x0814b601, + 0x020014fe, + 0x12004002, + 0xbd0002f6, + 0x05c94104, + 0xbd0010fe, + 0x07004024, + 0xbd0002f6, + 0x20034204, + 0x01010080, + 0xbd0002f6, + 0x20044204, + 0x01010480, + 0xbd0002f6, + 0x200b4204, + 0x01010880, + 0xbd0002f6, + 0x200c4204, + 0x01011c80, + 0xbd0002f6, + 0x01039204, + 0x03090080, + 0xbd0003f6, + 0x87044204, + 0xf6040040, + 0x04bd0002, + 0x00400402, + 0x0002f603, + 0x31f404bd, + 0x96048e10, + 0x00657e40, + 0xc7feb200, + 0x01b590f1, + 0x1ff4f003, + 0x01020fb5, + 0x041fbb01, + 0x800112b6, + 0xf6010300, + 0x04bd0001, + 0x01040080, + 0xbd0001f6, + 0x01004104, + 0xa87e020f, + 0xb77e0006, + 0x100f0006, + 0x0006f97e, + 0x98000e98, + 0x207e010f, + 0x14950001, + 0xc0008008, + 0x0004f601, + 0x008004bd, + 0x04f601c1, + 0xb704bd00, + 0xbb130030, + 0xf5b6001f, + 0xd3008002, + 0x000ff601, + 0x15b604bd, + 0x0110b608, + 0xb20814b6, + 0x02687e1f, + 0x001fbb00, + 0x84020398, +/* 0x041f: init_gpc */ + 0xb8502000, + 0x0008044e, + 0x8f7e1fb2, + 0x4eb80000, + 0xbd00010c, + 0x008f7ef4, + 0x044eb800, + 0x8f7e0001, + 0x4eb80000, + 0x0f000100, + 0x008f7e02, + 0x004eb800, +/* 0x044e: init_gpc_wait */ + 0x657e0008, + 0xffc80000, + 0xf90bf41f, + 0x08044eb8, + 0x00657e00, + 0x001fbb00, + 0x800040b7, + 0xf40132b6, + 0x000fb41b, + 0x0006f97e, + 0xa87e000f, + 0x00800006, + 0x01f60201, + 0xbd04bd00, + 0x1f19f014, + 0x02300080, + 0xbd0001f6, +/* 0x0491: main */ + 0x0031f404, + 0x0d0028f4, + 0x00377e10, + 0xf401f400, + 0x4001e4b1, + 0x00c71bf5, + 0x99f094bd, + 0x37008004, + 0x0009f602, + 0x008104bd, + 0x11cf02c0, + 0xc1008200, + 0x0022cf02, + 0xf41f13c8, + 0x23c8770b, + 0x550bf41f, + 0x12b220f9, + 0x99f094bd, + 0x37008007, + 0x0009f602, + 0x32f404bd, + 0x0231f401, + 0x00087c7e, + 0x99f094bd, + 0x17008007, + 0x0009f602, + 0x20fc04bd, + 0x99f094bd, + 0x37008006, + 0x0009f602, + 0x31f404bd, + 0x087c7e01, + 0xf094bd00, + 0x00800699, + 0x09f60217, + 0xf404bd00, +/* 0x0522: chsw_prev_no_next */ + 0x20f92f0e, + 0x32f412b2, + 0x0232f401, + 0x00087c7e, + 0x008020fc, + 0x02f602c0, + 0xf404bd00, +/* 0x053e: chsw_no_prev */ + 0x23c8130e, + 0x0d0bf41f, + 0xf40131f4, + 0x7c7e0232, +/* 0x054e: chsw_done */ + 0x01020008, + 0x02c30080, + 0xbd0002f6, + 0xf094bd04, + 0x00800499, + 0x09f60217, + 0xf504bd00, +/* 0x056b: main_not_ctx_switch */ + 0xb0ff2a0e, + 0x1bf401e4, + 0x7ef2b20c, + 0xf400081c, +/* 0x057a: main_not_ctx_chan */ + 0xe4b0400e, + 0x2c1bf402, + 0x99f094bd, + 0x37008007, + 0x0009f602, + 0x32f404bd, + 0x0232f401, + 0x00087c7e, + 0x99f094bd, + 0x17008007, + 0x0009f602, + 0x0ef404bd, +/* 0x05a9: main_not_ctx_save */ + 0x10ef9411, + 0x7e01f5f0, + 0xf50002f8, +/* 0x05b7: main_done */ + 0xbdfede0e, + 0x1f29f024, + 0x02300080, + 0xbd0002f6, + 0xcc0ef504, +/* 0x05c9: ih */ + 0xfe80f9fe, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x004a04bd, + 0x00aacf02, + 0xf404abc4, + 0x100d230b, + 0xcf1a004e, + 0x004f00ee, + 0x00ffcf19, + 0x0000047e, + 0x0400b0b7, + 0x0040010e, + 0x000ef61d, +/* 0x060a: ih_no_fifo */ + 0xabe404bd, + 0x0bf40100, + 0x4e100d0c, + 0x047e4001, +/* 0x061a: ih_no_ctxsw */ + 0xabe40000, + 0x0bf40400, + 0x07088e56, + 0x00657e40, + 0x80ffb200, + 0xf6020400, + 0x04bd000f, + 0x4007048e, + 0x0000657e, + 0x0080ffb2, + 0x0ff60203, + 0xc704bd00, + 0xee9450fe, + 0x07008f02, + 0x00efbb40, + 0x0000657e, + 0x02020080, + 0xbd000ff6, + 0x7e030f04, + 0x4b0002f8, + 0xbfb20100, + 0x4001448e, + 0x00008f7e, +/* 0x0674: ih_no_fwmthd */ + 0xbd05044b, + 0xb4abffb0, + 0x800c0bf4, + 0xf6030700, + 0x04bd000b, +/* 0x0688: ih_no_other */ + 0xf6010040, + 0x04bd000a, + 0xe0fcf0fc, + 0xb0fcd0fc, + 0x90fca0fc, + 0x88fe80fc, + 0xf480fc00, + 0x01f80032, +/* 0x06a8: ctx_4170s */ + 0xb210f5f0, + 0x41708eff, + 0x008f7e40, +/* 0x06b7: ctx_4170w */ + 0x8e00f800, + 0x7e404170, + 0xb2000065, + 0x10f4f0ff, + 0xf8f31bf4, +/* 0x06c9: ctx_redswitch */ + 0x02004e00, + 0xf040e5f0, + 0xe5f020e5, + 0x85008010, + 0x000ef601, + 0x080f04bd, +/* 0x06e0: ctx_redswitch_delay */ + 0xf401f2b6, + 0xe5f1fd1b, + 0xe5f10400, + 0x00800100, + 0x0ef60185, + 0xf804bd00, +/* 0x06f9: ctx_86c */ + 0x23008000, + 0x000ff602, + 0xffb204bd, + 0x408a148e, + 0x00008f7e, + 0x8c8effb2, + 0x8f7e41a8, + 0x00f80000, +/* 0x0718: ctx_mem */ + 0x02840080, + 0xbd000ff6, +/* 0x0721: ctx_mem_wait */ + 0x84008f04, + 0x00ffcf02, + 0xf405fffd, + 0x00f8f61b, +/* 0x0730: ctx_load */ + 0x99f094bd, + 0x37008005, + 0x0009f602, + 0x0c0a04bd, + 0x0000b87e, + 0x0080f4bd, + 0x0ff60289, + 0x8004bd00, + 0xf602c100, + 0x04bd0002, + 0x02830080, + 0xbd0002f6, + 0x7e070f04, + 0x80000718, + 0xf602c000, + 0x04bd0002, + 0xf0000bfe, + 0x24b61f2a, + 0x0220b604, + 0x99f094bd, + 0x37008008, + 0x0009f602, + 0x008004bd, + 0x02f60281, + 0xd204bd00, + 0x80000000, + 0x800225f0, + 0xf6028800, + 0x04bd0002, + 0x00421001, + 0x0223f002, + 0xf80512fa, + 0xf094bd03, + 0x00800899, + 0x09f60217, + 0x9804bd00, + 0x14b68101, + 0x80029818, + 0xfd0825b6, + 0x01b50512, + 0xf094bd16, + 0x00800999, + 0x09f60237, + 0x8004bd00, + 0xf6028100, + 0x04bd0001, + 0x00800102, + 0x02f60288, + 0x4104bd00, + 0x13f00100, + 0x0501fa06, + 0x94bd03f8, + 0x800999f0, + 0xf6021700, + 0x04bd0009, + 0x99f094bd, + 0x17008005, + 0x0009f602, + 0x00f804bd, +/* 0x081c: ctx_chan */ + 0x0007307e, + 0xb87e0c0a, + 0x050f0000, + 0x0007187e, +/* 0x082e: ctx_mmio_exec */ + 0x039800f8, + 0x81008041, + 0x0003f602, + 0x34bd04bd, +/* 0x083c: ctx_mmio_loop */ + 0xf4ff34c4, + 0x00450e1b, + 0x0653f002, + 0xf80535fa, +/* 0x084d: ctx_mmio_pull */ + 0x804e9803, + 0x7e814f98, + 0xb600008f, + 0x12b60830, + 0xdf1bf401, +/* 0x0860: ctx_mmio_done */ + 0x80160398, + 0xf6028100, + 0x04bd0003, + 0x414000b5, + 0x13f00100, + 0x0601fa06, + 0x00f803f8, +/* 0x087c: ctx_xfer */ + 0x0080040e, + 0x0ef60302, +/* 0x0887: ctx_xfer_idle */ + 0x8e04bd00, + 0xcf030000, + 0xe4f100ee, + 0x1bf42000, + 0x0611f4f5, +/* 0x089b: ctx_xfer_pre */ + 0x0f0c02f4, + 0x06f97e10, + 0x1b11f400, +/* 0x08a4: ctx_xfer_pre_load */ + 0xa87e020f, + 0xb77e0006, + 0xc97e0006, + 0xf4bd0006, + 0x0006a87e, + 0x0007307e, +/* 0x08bc: ctx_xfer_exec */ + 0xbd160198, + 0x05008024, + 0x0002f601, + 0x1fb204bd, + 0x41a5008e, + 0x00008f7e, + 0xf001fcf0, + 0x24b6022c, + 0x05f2fd01, + 0x048effb2, + 0x8f7e41a5, + 0x167e0000, + 0x24bd0002, + 0x0247fc80, + 0xbd0002f6, + 0x012cf004, + 0x800320b6, + 0xf6024afc, + 0x04bd0002, + 0xf001acf0, + 0x000b06a5, + 0x98000c98, + 0x000e010d, + 0x00013d7e, + 0xec7e080a, + 0x0a7e0000, + 0x01f40002, + 0x7e0c0a12, + 0x0f0000b8, + 0x07187e05, + 0x2d02f400, +/* 0x0938: ctx_xfer_post */ + 0xa87e020f, + 0xf4bd0006, + 0x0006f97e, + 0x0002277e, + 0x0006b77e, + 0xa87ef4bd, + 0x11f40006, + 0x40019810, + 0xf40511fd, + 0x2e7e070b, +/* 0x0962: ctx_xfer_no_post_mmio */ +/* 0x0962: ctx_xfer_done */ + 0x00f80008, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 new file mode 100644 index 000000000000..3ff52badf932 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define CHIPSET GF100 +#include "macros.fuc" + +.section #nvc0_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nvc0_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h new file mode 100644 index 000000000000..92dfe6a4ac87 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h @@ -0,0 +1,1047 @@ +uint32_t nvc0_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nvc0_grhub_code[] = { + 0x039b0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x039b: init */ + 0xbd00f804, + 0x0007fe04, + 0x420017f1, + 0xcf0013f0, + 0x11e70011, + 0x14b60109, + 0x0014fe08, + 0xf10227f0, + 0xf0120007, + 0x02d00003, + 0xf104bd00, + 0xfe06c817, + 0x24bd0010, + 0x070007f1, + 0xd00003f0, + 0x04bd0002, + 0x200327f1, + 0x010007f1, + 0xd00103f0, + 0x04bd0002, + 0x200427f1, + 0x010407f1, + 0xd00103f0, + 0x04bd0002, + 0x200b27f1, + 0x010807f1, + 0xd00103f0, + 0x04bd0002, + 0x200c27f1, + 0x011c07f1, + 0xd00103f0, + 0x04bd0002, + 0xf1010392, + 0xf0090007, + 0x03d00303, + 0xf104bd00, + 0xf0870427, + 0x07f10023, + 0x03f00400, + 0x0002d000, + 0x27f004bd, + 0x0007f104, + 0x0003f003, + 0xbd0002d0, + 0x1031f404, + 0x9604e7f1, + 0xf440e3f0, + 0xfeb96821, + 0x90f1c702, + 0xf0030180, + 0x0f801ff4, + 0x0117f002, + 0xb6041fbb, + 0x07f10112, + 0x03f00300, + 0x0001d001, + 0x07f104bd, + 0x03f00400, + 0x0001d001, + 0x17f104bd, + 0xf7f00100, + 0x0d21f502, + 0x1f21f508, + 0x10f7f008, + 0x086c21f5, + 0x98000e98, + 0x21f5010f, + 0x14950150, + 0x0007f108, + 0x0103f0c0, + 0xbd0004d0, + 0x0007f104, + 0x0103f0c1, + 0xbd0004d0, + 0x0030b704, + 0x001fbb13, + 0xf102f5b6, + 0xf0d30007, + 0x0fd00103, + 0xb604bd00, + 0x10b60815, + 0x0814b601, + 0xf5021fb9, + 0xbb02d321, + 0x0398001f, + 0x0047f102, + 0x5043f020, +/* 0x04f4: init_gpc */ + 0x08044ea0, + 0xf4021fb9, + 0x4ea09d21, + 0xf4bd010c, + 0xa09d21f4, + 0xf401044e, + 0x4ea09d21, + 0xf7f00100, + 0x9d21f402, + 0x08004ea0, +/* 0x051c: init_gpc_wait */ + 0xc86821f4, + 0x0bf41fff, + 0x044ea0fa, + 0x6821f408, + 0xb7001fbb, + 0xb6800040, + 0x1bf40132, + 0x00f7f0be, + 0x086c21f5, + 0xf500f7f0, + 0xf1080d21, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x080007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0564: main */ + 0xf40031f4, + 0xd7f00028, + 0x3921f410, + 0xb1f401f4, + 0xf54001e4, + 0xbd00e91b, + 0x0499f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xc00017f1, + 0xcf0213f0, + 0x27f10011, + 0x23f0c100, + 0x0022cf02, + 0xf51f13c8, + 0xc800890b, + 0x0bf41f23, + 0xb920f962, + 0x94bd0212, + 0xf10799f0, + 0xf00f0007, + 0x09d00203, + 0xf404bd00, + 0x31f40132, + 0x4021f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x20fc04bd, + 0x99f094bd, + 0x0007f106, + 0x0203f00f, + 0xbd0009d0, + 0x0131f404, + 0x0a4021f5, + 0x99f094bd, + 0x0007f106, + 0x0203f017, + 0xbd0009d0, + 0x330ef404, +/* 0x060c: chsw_prev_no_next */ + 0x12b920f9, + 0x0132f402, + 0xf50232f4, + 0xfc0a4021, + 0x0007f120, + 0x0203f0c0, + 0xbd0002d0, + 0x130ef404, +/* 0x062c: chsw_no_prev */ + 0xf41f23c8, + 0x31f40d0b, + 0x0232f401, + 0x0a4021f5, +/* 0x063c: chsw_done */ + 0xf10127f0, + 0xf0c30007, + 0x02d00203, + 0xbd04bd00, + 0x0499f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0xff080ef5, +/* 0x0660: main_not_ctx_switch */ + 0xf401e4b0, + 0xf2b90d1b, + 0xd021f502, + 0x460ef409, +/* 0x0670: main_not_ctx_chan */ + 0xf402e4b0, + 0x94bd321b, + 0xf10799f0, + 0xf00f0007, + 0x09d00203, + 0xf404bd00, + 0x32f40132, + 0x4021f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x06a5: main_not_ctx_save */ + 0x10ef9411, + 0xf501f5f0, + 0xf5037e21, +/* 0x06b3: main_done */ + 0xbdfeb50e, + 0x1f29f024, + 0x080007f1, + 0xd00203f0, + 0x04bd0002, + 0xfea00ef5, +/* 0x06c8: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x10d7f030, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xb70421f4, + 0xf00400b0, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x071a: ih_no_fifo */ + 0xabe404bd, + 0x0bf40100, + 0x10d7f00d, + 0x4001e7f1, +/* 0x072b: ih_no_ctxsw */ + 0xe40421f4, + 0xf40400ab, + 0xe7f16c0b, + 0xe3f00708, + 0x6821f440, + 0xf102ffb9, + 0xf0040007, + 0x0fd00203, + 0xf104bd00, + 0xf00704e7, + 0x21f440e3, + 0x02ffb968, + 0x030007f1, + 0xd00203f0, + 0x04bd000f, + 0x9450fec7, + 0xf7f102ee, + 0xf3f00700, + 0x00efbb40, + 0xf16821f4, + 0xf0020007, + 0x0fd00203, + 0xf004bd00, + 0x21f503f7, + 0xb7f1037e, + 0xbfb90100, + 0x44e7f102, + 0x40e3f001, +/* 0x079b: ih_no_fwmthd */ + 0xf19d21f4, + 0xbd0504b7, + 0xb4abffb0, + 0xf10f0bf4, + 0xf0070007, + 0x0bd00303, +/* 0x07b3: ih_no_other */ + 0xf104bd00, + 0xf0010007, + 0x0ad00003, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x07d7: ctx_4160s */ + 0xf001f800, + 0xffb901f7, + 0x60e7f102, + 0x40e3f041, +/* 0x07e7: ctx_4160s_wait */ + 0xf19d21f4, + 0xf04160e7, + 0x21f440e3, + 0x02ffb968, + 0xf404ffc8, + 0x00f8f00b, +/* 0x07fc: ctx_4160c */ + 0xffb9f4bd, + 0x60e7f102, + 0x40e3f041, + 0xf89d21f4, +/* 0x080d: ctx_4170s */ + 0x10f5f000, + 0xf102ffb9, + 0xf04170e7, + 0x21f440e3, +/* 0x081f: ctx_4170w */ + 0xf100f89d, + 0xf04170e7, + 0x21f440e3, + 0x02ffb968, + 0xf410f4f0, + 0x00f8f01b, +/* 0x0834: ctx_redswitch */ + 0x0200e7f1, + 0xf040e5f0, + 0xe5f020e5, + 0x0007f110, + 0x0103f085, + 0xbd000ed0, + 0x08f7f004, +/* 0x0850: ctx_redswitch_delay */ + 0xf401f2b6, + 0xe5f1fd1b, + 0xe5f10400, + 0x07f10100, + 0x03f08500, + 0x000ed001, + 0x00f804bd, +/* 0x086c: ctx_86c */ + 0x1b0007f1, + 0xd00203f0, + 0x04bd000f, + 0xf102ffb9, + 0xf08a14e7, + 0x21f440e3, + 0x02ffb99d, + 0xa86ce7f1, + 0xf441e3f0, + 0x00f89d21, +/* 0x0894: ctx_mem */ + 0x840007f1, + 0xd00203f0, + 0x04bd000f, +/* 0x08a0: ctx_mem_wait */ + 0x8400f7f1, + 0xcf02f3f0, + 0xfffd00ff, + 0xf31bf405, +/* 0x08b2: ctx_load */ + 0x94bd00f8, + 0xf10599f0, + 0xf00f0007, + 0x09d00203, + 0xf004bd00, + 0x21f40ca7, + 0xf1f4bdd0, + 0xf0890007, + 0x0fd00203, + 0xf104bd00, + 0xf0c10007, + 0x02d00203, + 0xf104bd00, + 0xf0830007, + 0x02d00203, + 0xf004bd00, + 0x21f507f7, + 0x07f10894, + 0x03f0c000, + 0x0002d002, + 0x0bfe04bd, + 0x1f2af000, + 0xb60424b6, + 0x94bd0220, + 0xf10899f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, + 0xf0810007, + 0x02d00203, + 0xf104bd00, + 0xf1000027, + 0xf0800023, + 0x07f10225, + 0x03f08800, + 0x0002d002, + 0x17f004bd, + 0x0027f110, + 0x0223f002, + 0xf80512fa, + 0xf094bd03, + 0x07f10899, + 0x03f01700, + 0x0009d002, + 0x019804bd, + 0x1814b681, + 0xb6800298, + 0x12fd0825, + 0x16018005, + 0x99f094bd, + 0x0007f109, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f081, + 0xbd0001d0, + 0x0127f004, + 0x880007f1, + 0xd00203f0, + 0x04bd0002, + 0x010017f1, + 0xfa0613f0, + 0x03f80501, + 0x99f094bd, + 0x0007f109, + 0x0203f017, + 0xbd0009d0, + 0xf094bd04, + 0x07f10599, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x09d0: ctx_chan */ + 0x07d721f5, + 0x08b221f5, + 0xf40ca7f0, + 0xf7f0d021, + 0x9421f505, + 0xfc21f508, +/* 0x09eb: ctx_mmio_exec */ + 0x9800f807, + 0x07f14103, + 0x03f08100, + 0x0003d002, + 0x34bd04bd, +/* 0x09fc: ctx_mmio_loop */ + 0xf4ff34c4, + 0x57f10f1b, + 0x53f00200, + 0x0535fa06, +/* 0x0a0e: ctx_mmio_pull */ + 0x4e9803f8, + 0x814f9880, + 0xb69d21f4, + 0x12b60830, + 0xdf1bf401, +/* 0x0a20: ctx_mmio_done */ + 0xf1160398, + 0xf0810007, + 0x03d00203, + 0x8004bd00, + 0x17f14000, + 0x13f00100, + 0x0601fa06, + 0x00f803f8, +/* 0x0a40: ctx_xfer */ + 0xf104e7f0, + 0xf0020007, + 0x0ed00303, +/* 0x0a4f: ctx_xfer_idle */ + 0xf104bd00, + 0xf00000e7, + 0xeecf03e3, + 0x00e4f100, + 0xf21bf420, + 0xf40611f4, +/* 0x0a66: ctx_xfer_pre */ + 0xf7f01102, + 0x6c21f510, + 0xd721f508, + 0x1c11f407, +/* 0x0a74: ctx_xfer_pre_load */ + 0xf502f7f0, + 0xf5080d21, + 0xf5081f21, + 0xbd083421, + 0x0d21f5f4, + 0xb221f508, +/* 0x0a8d: ctx_xfer_exec */ + 0x16019808, + 0x07f124bd, + 0x03f00500, + 0x0002d001, + 0x1fb904bd, + 0x00e7f102, + 0x41e3f0a5, + 0xf09d21f4, + 0x2cf001fc, + 0x0124b602, + 0xb905f2fd, + 0xe7f102ff, + 0xe3f0a504, + 0x9d21f441, + 0x026a21f5, + 0x07f124bd, + 0x03f047fc, + 0x0002d002, + 0x2cf004bd, + 0x0320b601, + 0x4afc07f1, + 0xd00203f0, + 0x04bd0002, + 0xf001acf0, + 0xb7f006a5, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xa7f0016f, + 0x1021f508, + 0x5e21f501, + 0x1301f402, + 0xf40ca7f0, + 0xf7f0d021, + 0x9421f505, + 0x3202f408, +/* 0x0b1c: ctx_xfer_post */ + 0xf502f7f0, + 0xbd080d21, + 0x6c21f5f4, + 0x7f21f508, + 0x1f21f502, + 0xf5f4bd08, + 0xf4080d21, + 0x01981011, + 0x0511fd40, + 0xf5070bf4, +/* 0x0b47: ctx_xfer_no_post_mmio */ + 0xf509eb21, +/* 0x0b4b: ctx_xfer_done */ + 0xf807fc21, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 new file mode 100644 index 000000000000..afbe03ac9077 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define CHIPSET GF117 +#include "macros.fuc" + +.section #nvd7_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nvd7_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h new file mode 100644 index 000000000000..62b0c7601d8b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h @@ -0,0 +1,1047 @@ +uint32_t nvd7_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nvd7_grhub_code[] = { + 0x039b0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x039b: init */ + 0xbd00f804, + 0x0007fe04, + 0x420017f1, + 0xcf0013f0, + 0x11e70011, + 0x14b60109, + 0x0014fe08, + 0xf10227f0, + 0xf0120007, + 0x02d00003, + 0xf104bd00, + 0xfe06c817, + 0x24bd0010, + 0x070007f1, + 0xd00003f0, + 0x04bd0002, + 0x200327f1, + 0x010007f1, + 0xd00103f0, + 0x04bd0002, + 0x200427f1, + 0x010407f1, + 0xd00103f0, + 0x04bd0002, + 0x200b27f1, + 0x010807f1, + 0xd00103f0, + 0x04bd0002, + 0x200c27f1, + 0x011c07f1, + 0xd00103f0, + 0x04bd0002, + 0xf1010392, + 0xf0090007, + 0x03d00303, + 0xf104bd00, + 0xf0870427, + 0x07f10023, + 0x03f00400, + 0x0002d000, + 0x27f004bd, + 0x0007f104, + 0x0003f003, + 0xbd0002d0, + 0x1031f404, + 0x9604e7f1, + 0xf440e3f0, + 0xfeb96821, + 0x90f1c702, + 0xf0030180, + 0x0f801ff4, + 0x0117f002, + 0xb6041fbb, + 0x07f10112, + 0x03f00300, + 0x0001d001, + 0x07f104bd, + 0x03f00400, + 0x0001d001, + 0x17f104bd, + 0xf7f00100, + 0x0d21f502, + 0x1f21f508, + 0x10f7f008, + 0x086c21f5, + 0x98000e98, + 0x21f5010f, + 0x14950150, + 0x0007f108, + 0x0103f0c0, + 0xbd0004d0, + 0x0007f104, + 0x0103f0c1, + 0xbd0004d0, + 0x0030b704, + 0x001fbb13, + 0xf102f5b6, + 0xf0d30007, + 0x0fd00103, + 0xb604bd00, + 0x10b60815, + 0x0814b601, + 0xf5021fb9, + 0xbb02d321, + 0x0398001f, + 0x0047f102, + 0x5043f020, +/* 0x04f4: init_gpc */ + 0x08044ea0, + 0xf4021fb9, + 0x4ea09d21, + 0xf4bd010c, + 0xa09d21f4, + 0xf401044e, + 0x4ea09d21, + 0xf7f00100, + 0x9d21f402, + 0x08004ea0, +/* 0x051c: init_gpc_wait */ + 0xc86821f4, + 0x0bf41fff, + 0x044ea0fa, + 0x6821f408, + 0xb7001fbb, + 0xb6800040, + 0x1bf40132, + 0x00f7f0be, + 0x086c21f5, + 0xf500f7f0, + 0xf1080d21, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x080007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0564: main */ + 0xf40031f4, + 0xd7f00028, + 0x3921f410, + 0xb1f401f4, + 0xf54001e4, + 0xbd00e91b, + 0x0499f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xc00017f1, + 0xcf0213f0, + 0x27f10011, + 0x23f0c100, + 0x0022cf02, + 0xf51f13c8, + 0xc800890b, + 0x0bf41f23, + 0xb920f962, + 0x94bd0212, + 0xf10799f0, + 0xf00f0007, + 0x09d00203, + 0xf404bd00, + 0x31f40132, + 0x4021f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x20fc04bd, + 0x99f094bd, + 0x0007f106, + 0x0203f00f, + 0xbd0009d0, + 0x0131f404, + 0x0a4021f5, + 0x99f094bd, + 0x0007f106, + 0x0203f017, + 0xbd0009d0, + 0x330ef404, +/* 0x060c: chsw_prev_no_next */ + 0x12b920f9, + 0x0132f402, + 0xf50232f4, + 0xfc0a4021, + 0x0007f120, + 0x0203f0c0, + 0xbd0002d0, + 0x130ef404, +/* 0x062c: chsw_no_prev */ + 0xf41f23c8, + 0x31f40d0b, + 0x0232f401, + 0x0a4021f5, +/* 0x063c: chsw_done */ + 0xf10127f0, + 0xf0c30007, + 0x02d00203, + 0xbd04bd00, + 0x0499f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0xff080ef5, +/* 0x0660: main_not_ctx_switch */ + 0xf401e4b0, + 0xf2b90d1b, + 0xd021f502, + 0x460ef409, +/* 0x0670: main_not_ctx_chan */ + 0xf402e4b0, + 0x94bd321b, + 0xf10799f0, + 0xf00f0007, + 0x09d00203, + 0xf404bd00, + 0x32f40132, + 0x4021f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x06a5: main_not_ctx_save */ + 0x10ef9411, + 0xf501f5f0, + 0xf5037e21, +/* 0x06b3: main_done */ + 0xbdfeb50e, + 0x1f29f024, + 0x080007f1, + 0xd00203f0, + 0x04bd0002, + 0xfea00ef5, +/* 0x06c8: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x10d7f030, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xb70421f4, + 0xf00400b0, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x071a: ih_no_fifo */ + 0xabe404bd, + 0x0bf40100, + 0x10d7f00d, + 0x4001e7f1, +/* 0x072b: ih_no_ctxsw */ + 0xe40421f4, + 0xf40400ab, + 0xe7f16c0b, + 0xe3f00708, + 0x6821f440, + 0xf102ffb9, + 0xf0040007, + 0x0fd00203, + 0xf104bd00, + 0xf00704e7, + 0x21f440e3, + 0x02ffb968, + 0x030007f1, + 0xd00203f0, + 0x04bd000f, + 0x9450fec7, + 0xf7f102ee, + 0xf3f00700, + 0x00efbb40, + 0xf16821f4, + 0xf0020007, + 0x0fd00203, + 0xf004bd00, + 0x21f503f7, + 0xb7f1037e, + 0xbfb90100, + 0x44e7f102, + 0x40e3f001, +/* 0x079b: ih_no_fwmthd */ + 0xf19d21f4, + 0xbd0504b7, + 0xb4abffb0, + 0xf10f0bf4, + 0xf0070007, + 0x0bd00303, +/* 0x07b3: ih_no_other */ + 0xf104bd00, + 0xf0010007, + 0x0ad00003, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x07d7: ctx_4160s */ + 0xf001f800, + 0xffb901f7, + 0x60e7f102, + 0x40e3f041, +/* 0x07e7: ctx_4160s_wait */ + 0xf19d21f4, + 0xf04160e7, + 0x21f440e3, + 0x02ffb968, + 0xf404ffc8, + 0x00f8f00b, +/* 0x07fc: ctx_4160c */ + 0xffb9f4bd, + 0x60e7f102, + 0x40e3f041, + 0xf89d21f4, +/* 0x080d: ctx_4170s */ + 0x10f5f000, + 0xf102ffb9, + 0xf04170e7, + 0x21f440e3, +/* 0x081f: ctx_4170w */ + 0xf100f89d, + 0xf04170e7, + 0x21f440e3, + 0x02ffb968, + 0xf410f4f0, + 0x00f8f01b, +/* 0x0834: ctx_redswitch */ + 0x0200e7f1, + 0xf040e5f0, + 0xe5f020e5, + 0x0007f110, + 0x0103f085, + 0xbd000ed0, + 0x08f7f004, +/* 0x0850: ctx_redswitch_delay */ + 0xf401f2b6, + 0xe5f1fd1b, + 0xe5f10400, + 0x07f10100, + 0x03f08500, + 0x000ed001, + 0x00f804bd, +/* 0x086c: ctx_86c */ + 0x1b0007f1, + 0xd00203f0, + 0x04bd000f, + 0xf102ffb9, + 0xf08a14e7, + 0x21f440e3, + 0x02ffb99d, + 0xa86ce7f1, + 0xf441e3f0, + 0x00f89d21, +/* 0x0894: ctx_mem */ + 0x840007f1, + 0xd00203f0, + 0x04bd000f, +/* 0x08a0: ctx_mem_wait */ + 0x8400f7f1, + 0xcf02f3f0, + 0xfffd00ff, + 0xf31bf405, +/* 0x08b2: ctx_load */ + 0x94bd00f8, + 0xf10599f0, + 0xf00f0007, + 0x09d00203, + 0xf004bd00, + 0x21f40ca7, + 0xf1f4bdd0, + 0xf0890007, + 0x0fd00203, + 0xf104bd00, + 0xf0c10007, + 0x02d00203, + 0xf104bd00, + 0xf0830007, + 0x02d00203, + 0xf004bd00, + 0x21f507f7, + 0x07f10894, + 0x03f0c000, + 0x0002d002, + 0x0bfe04bd, + 0x1f2af000, + 0xb60424b6, + 0x94bd0220, + 0xf10899f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, + 0xf0810007, + 0x02d00203, + 0xf104bd00, + 0xf1000027, + 0xf0800023, + 0x07f10225, + 0x03f08800, + 0x0002d002, + 0x17f004bd, + 0x0027f110, + 0x0223f002, + 0xf80512fa, + 0xf094bd03, + 0x07f10899, + 0x03f01700, + 0x0009d002, + 0x019804bd, + 0x1814b681, + 0xb6800298, + 0x12fd0825, + 0x16018005, + 0x99f094bd, + 0x0007f109, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f081, + 0xbd0001d0, + 0x0127f004, + 0x880007f1, + 0xd00203f0, + 0x04bd0002, + 0x010017f1, + 0xfa0613f0, + 0x03f80501, + 0x99f094bd, + 0x0007f109, + 0x0203f017, + 0xbd0009d0, + 0xf094bd04, + 0x07f10599, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x09d0: ctx_chan */ + 0x07d721f5, + 0x08b221f5, + 0xf40ca7f0, + 0xf7f0d021, + 0x9421f505, + 0xfc21f508, +/* 0x09eb: ctx_mmio_exec */ + 0x9800f807, + 0x07f14103, + 0x03f08100, + 0x0003d002, + 0x34bd04bd, +/* 0x09fc: ctx_mmio_loop */ + 0xf4ff34c4, + 0x57f10f1b, + 0x53f00200, + 0x0535fa06, +/* 0x0a0e: ctx_mmio_pull */ + 0x4e9803f8, + 0x814f9880, + 0xb69d21f4, + 0x12b60830, + 0xdf1bf401, +/* 0x0a20: ctx_mmio_done */ + 0xf1160398, + 0xf0810007, + 0x03d00203, + 0x8004bd00, + 0x17f14000, + 0x13f00100, + 0x0601fa06, + 0x00f803f8, +/* 0x0a40: ctx_xfer */ + 0xf104e7f0, + 0xf0020007, + 0x0ed00303, +/* 0x0a4f: ctx_xfer_idle */ + 0xf104bd00, + 0xf00000e7, + 0xeecf03e3, + 0x00e4f100, + 0xf21bf420, + 0xf40611f4, +/* 0x0a66: ctx_xfer_pre */ + 0xf7f01102, + 0x6c21f510, + 0xd721f508, + 0x1c11f407, +/* 0x0a74: ctx_xfer_pre_load */ + 0xf502f7f0, + 0xf5080d21, + 0xf5081f21, + 0xbd083421, + 0x0d21f5f4, + 0xb221f508, +/* 0x0a8d: ctx_xfer_exec */ + 0x16019808, + 0x07f124bd, + 0x03f00500, + 0x0002d001, + 0x1fb904bd, + 0x00e7f102, + 0x41e3f0a5, + 0xf09d21f4, + 0x2cf001fc, + 0x0124b602, + 0xb905f2fd, + 0xe7f102ff, + 0xe3f0a504, + 0x9d21f441, + 0x026a21f5, + 0x07f124bd, + 0x03f047fc, + 0x0002d002, + 0x2cf004bd, + 0x0320b601, + 0x4afc07f1, + 0xd00203f0, + 0x04bd0002, + 0xf001acf0, + 0xb7f006a5, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xa7f0016f, + 0x1021f508, + 0x5e21f501, + 0x1301f402, + 0xf40ca7f0, + 0xf7f0d021, + 0x9421f505, + 0x3202f408, +/* 0x0b1c: ctx_xfer_post */ + 0xf502f7f0, + 0xbd080d21, + 0x6c21f5f4, + 0x7f21f508, + 0x1f21f502, + 0xf5f4bd08, + 0xf4080d21, + 0x01981011, + 0x0511fd40, + 0xf5070bf4, +/* 0x0b47: ctx_xfer_no_post_mmio */ + 0xf509eb21, +/* 0x0b4b: ctx_xfer_done */ + 0xf807fc21, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 new file mode 100644 index 000000000000..d4840f1879fd --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define CHIPSET GK100 +#include "macros.fuc" + +.section #nve0_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nve0_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h new file mode 100644 index 000000000000..51c3797d8537 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h @@ -0,0 +1,1044 @@ +uint32_t nve0_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nve0_grhub_code[] = { + 0x039b0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x039b: init */ + 0xbd00f804, + 0x0007fe04, + 0x420017f1, + 0xcf0013f0, + 0x11e70011, + 0x14b60109, + 0x0014fe08, + 0xf10227f0, + 0xf0120007, + 0x02d00003, + 0xf104bd00, + 0xfe06c817, + 0x24bd0010, + 0x070007f1, + 0xd00003f0, + 0x04bd0002, + 0x200327f1, + 0x010007f1, + 0xd00103f0, + 0x04bd0002, + 0x200427f1, + 0x010407f1, + 0xd00103f0, + 0x04bd0002, + 0x200b27f1, + 0x010807f1, + 0xd00103f0, + 0x04bd0002, + 0x200c27f1, + 0x011c07f1, + 0xd00103f0, + 0x04bd0002, + 0xf1010392, + 0xf0090007, + 0x03d00303, + 0xf104bd00, + 0xf0870427, + 0x07f10023, + 0x03f00400, + 0x0002d000, + 0x27f004bd, + 0x0007f104, + 0x0003f003, + 0xbd0002d0, + 0x1031f404, + 0x9604e7f1, + 0xf440e3f0, + 0xfeb96821, + 0x90f1c702, + 0xf0030180, + 0x0f801ff4, + 0x0117f002, + 0xb6041fbb, + 0x07f10112, + 0x03f00300, + 0x0001d001, + 0x07f104bd, + 0x03f00400, + 0x0001d001, + 0x17f104bd, + 0xf7f00100, + 0xd721f502, + 0xe921f507, + 0x10f7f007, + 0x083621f5, + 0x98000e98, + 0x21f5010f, + 0x14950150, + 0x0007f108, + 0x0103f0c0, + 0xbd0004d0, + 0x0007f104, + 0x0103f0c1, + 0xbd0004d0, + 0x0030b704, + 0x001fbb13, + 0xf102f5b6, + 0xf0d30007, + 0x0fd00103, + 0xb604bd00, + 0x10b60815, + 0x0814b601, + 0xf5021fb9, + 0xbb02d321, + 0x0398001f, + 0x0047f102, + 0x5043f020, +/* 0x04f4: init_gpc */ + 0x08044ea0, + 0xf4021fb9, + 0x4ea09d21, + 0xf4bd010c, + 0xa09d21f4, + 0xf401044e, + 0x4ea09d21, + 0xf7f00100, + 0x9d21f402, + 0x08004ea0, +/* 0x051c: init_gpc_wait */ + 0xc86821f4, + 0x0bf41fff, + 0x044ea0fa, + 0x6821f408, + 0xb7001fbb, + 0xb6800040, + 0x1bf40132, + 0x00f7f0be, + 0x083621f5, + 0xf500f7f0, + 0xf107d721, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x080007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0564: main */ + 0xf40031f4, + 0xd7f00028, + 0x3921f410, + 0xb1f401f4, + 0xf54001e4, + 0xbd00e91b, + 0x0499f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xc00017f1, + 0xcf0213f0, + 0x27f10011, + 0x23f0c100, + 0x0022cf02, + 0xf51f13c8, + 0xc800890b, + 0x0bf41f23, + 0xb920f962, + 0x94bd0212, + 0xf10799f0, + 0xf00f0007, + 0x09d00203, + 0xf404bd00, + 0x31f40132, + 0x0221f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x20fc04bd, + 0x99f094bd, + 0x0007f106, + 0x0203f00f, + 0xbd0009d0, + 0x0131f404, + 0x0a0221f5, + 0x99f094bd, + 0x0007f106, + 0x0203f017, + 0xbd0009d0, + 0x330ef404, +/* 0x060c: chsw_prev_no_next */ + 0x12b920f9, + 0x0132f402, + 0xf50232f4, + 0xfc0a0221, + 0x0007f120, + 0x0203f0c0, + 0xbd0002d0, + 0x130ef404, +/* 0x062c: chsw_no_prev */ + 0xf41f23c8, + 0x31f40d0b, + 0x0232f401, + 0x0a0221f5, +/* 0x063c: chsw_done */ + 0xf10127f0, + 0xf0c30007, + 0x02d00203, + 0xbd04bd00, + 0x0499f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0xff080ef5, +/* 0x0660: main_not_ctx_switch */ + 0xf401e4b0, + 0xf2b90d1b, + 0x9a21f502, + 0x460ef409, +/* 0x0670: main_not_ctx_chan */ + 0xf402e4b0, + 0x94bd321b, + 0xf10799f0, + 0xf00f0007, + 0x09d00203, + 0xf404bd00, + 0x32f40132, + 0x0221f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x06a5: main_not_ctx_save */ + 0x10ef9411, + 0xf501f5f0, + 0xf5037e21, +/* 0x06b3: main_done */ + 0xbdfeb50e, + 0x1f29f024, + 0x080007f1, + 0xd00203f0, + 0x04bd0002, + 0xfea00ef5, +/* 0x06c8: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x10d7f030, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xb70421f4, + 0xf00400b0, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x071a: ih_no_fifo */ + 0xabe404bd, + 0x0bf40100, + 0x10d7f00d, + 0x4001e7f1, +/* 0x072b: ih_no_ctxsw */ + 0xe40421f4, + 0xf40400ab, + 0xe7f16c0b, + 0xe3f00708, + 0x6821f440, + 0xf102ffb9, + 0xf0040007, + 0x0fd00203, + 0xf104bd00, + 0xf00704e7, + 0x21f440e3, + 0x02ffb968, + 0x030007f1, + 0xd00203f0, + 0x04bd000f, + 0x9450fec7, + 0xf7f102ee, + 0xf3f00700, + 0x00efbb40, + 0xf16821f4, + 0xf0020007, + 0x0fd00203, + 0xf004bd00, + 0x21f503f7, + 0xb7f1037e, + 0xbfb90100, + 0x44e7f102, + 0x40e3f001, +/* 0x079b: ih_no_fwmthd */ + 0xf19d21f4, + 0xbd0504b7, + 0xb4abffb0, + 0xf10f0bf4, + 0xf0070007, + 0x0bd00303, +/* 0x07b3: ih_no_other */ + 0xf104bd00, + 0xf0010007, + 0x0ad00003, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x07d7: ctx_4170s */ + 0xf001f800, + 0xffb910f5, + 0x70e7f102, + 0x40e3f041, + 0xf89d21f4, +/* 0x07e9: ctx_4170w */ + 0x70e7f100, + 0x40e3f041, + 0xb96821f4, + 0xf4f002ff, + 0xf01bf410, +/* 0x07fe: ctx_redswitch */ + 0xe7f100f8, + 0xe5f00200, + 0x20e5f040, + 0xf110e5f0, + 0xf0850007, + 0x0ed00103, + 0xf004bd00, +/* 0x081a: ctx_redswitch_delay */ + 0xf2b608f7, + 0xfd1bf401, + 0x0400e5f1, + 0x0100e5f1, + 0x850007f1, + 0xd00103f0, + 0x04bd000e, +/* 0x0836: ctx_86c */ + 0x07f100f8, + 0x03f01b00, + 0x000fd002, + 0xffb904bd, + 0x14e7f102, + 0x40e3f08a, + 0xb99d21f4, + 0xe7f102ff, + 0xe3f0a86c, + 0x9d21f441, +/* 0x085e: ctx_mem */ + 0x07f100f8, + 0x03f08400, + 0x000fd002, +/* 0x086a: ctx_mem_wait */ + 0xf7f104bd, + 0xf3f08400, + 0x00ffcf02, + 0xf405fffd, + 0x00f8f31b, +/* 0x087c: ctx_load */ + 0x99f094bd, + 0x0007f105, + 0x0203f00f, + 0xbd0009d0, + 0x0ca7f004, + 0xbdd021f4, + 0x0007f1f4, + 0x0203f089, + 0xbd000fd0, + 0x0007f104, + 0x0203f0c1, + 0xbd0002d0, + 0x0007f104, + 0x0203f083, + 0xbd0002d0, + 0x07f7f004, + 0x085e21f5, + 0xc00007f1, + 0xd00203f0, + 0x04bd0002, + 0xf0000bfe, + 0x24b61f2a, + 0x0220b604, + 0x99f094bd, + 0x0007f108, + 0x0203f00f, + 0xbd0009d0, + 0x0007f104, + 0x0203f081, + 0xbd0002d0, + 0x0027f104, + 0x0023f100, + 0x0225f080, + 0x880007f1, + 0xd00203f0, + 0x04bd0002, + 0xf11017f0, + 0xf0020027, + 0x12fa0223, + 0xbd03f805, + 0x0899f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0xb6810198, + 0x02981814, + 0x0825b680, + 0x800512fd, + 0x94bd1601, + 0xf10999f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, + 0xf0810007, + 0x01d00203, + 0xf004bd00, + 0x07f10127, + 0x03f08800, + 0x0002d002, + 0x17f104bd, + 0x13f00100, + 0x0501fa06, + 0x94bd03f8, + 0xf10999f0, + 0xf0170007, + 0x09d00203, + 0xbd04bd00, + 0x0599f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x099a: ctx_chan */ + 0x21f500f8, + 0xa7f0087c, + 0xd021f40c, + 0xf505f7f0, + 0xf8085e21, +/* 0x09ad: ctx_mmio_exec */ + 0x41039800, + 0x810007f1, + 0xd00203f0, + 0x04bd0003, +/* 0x09be: ctx_mmio_loop */ + 0x34c434bd, + 0x0f1bf4ff, + 0x020057f1, + 0xfa0653f0, + 0x03f80535, +/* 0x09d0: ctx_mmio_pull */ + 0x98804e98, + 0x21f4814f, + 0x0830b69d, + 0xf40112b6, +/* 0x09e2: ctx_mmio_done */ + 0x0398df1b, + 0x0007f116, + 0x0203f081, + 0xbd0003d0, + 0x40008004, + 0x010017f1, + 0xfa0613f0, + 0x03f80601, +/* 0x0a02: ctx_xfer */ + 0xe7f000f8, + 0x0007f104, + 0x0303f002, + 0xbd000ed0, +/* 0x0a11: ctx_xfer_idle */ + 0x00e7f104, + 0x03e3f000, + 0xf100eecf, + 0xf42000e4, + 0x11f4f21b, + 0x0d02f406, +/* 0x0a28: ctx_xfer_pre */ + 0xf510f7f0, + 0xf4083621, +/* 0x0a32: ctx_xfer_pre_load */ + 0xf7f01c11, + 0xd721f502, + 0xe921f507, + 0xfe21f507, + 0xf5f4bd07, + 0xf507d721, +/* 0x0a4b: ctx_xfer_exec */ + 0x98087c21, + 0x24bd1601, + 0x050007f1, + 0xd00103f0, + 0x04bd0002, + 0xf1021fb9, + 0xf0a500e7, + 0x21f441e3, + 0x01fcf09d, + 0xb6022cf0, + 0xf2fd0124, + 0x02ffb905, + 0xa504e7f1, + 0xf441e3f0, + 0x21f59d21, + 0x24bd026a, + 0x47fc07f1, + 0xd00203f0, + 0x04bd0002, + 0xb6012cf0, + 0x07f10320, + 0x03f04afc, + 0x0002d002, + 0xacf004bd, + 0x06a5f001, + 0x9800b7f0, + 0x0d98000c, + 0x00e7f001, + 0x016f21f5, + 0xf508a7f0, + 0xf5011021, + 0xf4025e21, + 0xa7f01301, + 0xd021f40c, + 0xf505f7f0, + 0xf4085e21, +/* 0x0ada: ctx_xfer_post */ + 0xf7f02e02, + 0xd721f502, + 0xf5f4bd07, + 0xf5083621, + 0xf5027f21, + 0xbd07e921, + 0xd721f5f4, + 0x1011f407, + 0xfd400198, + 0x0bf40511, + 0xad21f507, +/* 0x0b05: ctx_xfer_no_post_mmio */ +/* 0x0b05: ctx_xfer_done */ + 0x0000f809, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 new file mode 100644 index 000000000000..ec42ed29b50d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define CHIPSET GK110 +#include "macros.fuc" + +.section #nvf0_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nvf0_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h new file mode 100644 index 000000000000..a0af4b703a8e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h @@ -0,0 +1,1044 @@ +uint32_t nvf0_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nvf0_grhub_code[] = { + 0x039b0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f8037e, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0xf002ecb9, + 0x07f11fc9, + 0x03f0ca00, + 0x000cd001, +/* 0x007a: nv_rd32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0xa7f0f31b, + 0x1021f506, + 0x00f7f101, + 0x01f3f0cb, + 0xf800ffcf, +/* 0x009d: nv_wr32 */ + 0x0007f100, + 0x0103f0cc, + 0xbd000fd0, + 0x02ecb904, + 0xf01fc9f0, + 0x07f11ec9, + 0x03f0ca00, + 0x000cd001, +/* 0x00be: nv_wr32_wait */ + 0xc7f104bd, + 0xc3f0ca00, + 0x00cccf01, + 0xf41fccc8, + 0x00f8f31b, +/* 0x00d0: wait_donez */ + 0x99f094bd, + 0x0007f100, + 0x0203f037, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x00ed: wait_donez_ne */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x1bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0110: wait_doneo */ + 0x99f094bd, + 0x0007f100, + 0x0203f037, + 0xbd0009d0, + 0x0007f104, + 0x0203f006, + 0xbd000ad0, +/* 0x012d: wait_doneo_e */ + 0x0087f104, + 0x0183f000, + 0xff0088cf, + 0x0bf4888a, + 0xf094bdf3, + 0x07f10099, + 0x03f01700, + 0x0009d002, + 0x00f804bd, +/* 0x0150: mmctx_size */ +/* 0x0152: nv_mmctx_size_loop */ + 0xe89894bd, + 0x1a85b600, + 0xb60180b6, + 0x98bb0284, + 0x04e0b600, + 0xf404efb8, + 0x9fb9eb1b, +/* 0x016f: mmctx_xfer */ + 0xbd00f802, + 0x0199f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0xbbfd94bd, + 0x120bf405, + 0xc40007f1, + 0xd00103f0, + 0x04bd000b, +/* 0x0197: mmctx_base_disabled */ + 0xfd0099f0, + 0x0bf405ee, + 0x0007f11e, + 0x0103f0c6, + 0xbd000ed0, + 0x0007f104, + 0x0103f0c7, + 0xbd000fd0, + 0x0199f004, +/* 0x01b8: mmctx_multi_disabled */ + 0xb600abc8, + 0xb9f010b4, + 0x01aec80c, + 0xfd11e4b6, + 0x07f105be, + 0x03f0c500, + 0x000bd001, +/* 0x01d6: mmctx_exec_loop */ +/* 0x01d6: mmctx_wait_free */ + 0xe7f104bd, + 0xe3f0c500, + 0x00eecf01, + 0xf41fe4f0, + 0xce98f30b, + 0x05e9fd00, + 0xc80007f1, + 0xd00103f0, + 0x04bd000e, + 0xb804c0b6, + 0x1bf404cd, + 0x02abc8d8, +/* 0x0207: mmctx_fini_wait */ + 0xf11f1bf4, + 0xf0c500b7, + 0xbbcf01b3, + 0x1fb4f000, + 0xf410b4b0, + 0xa7f0f01b, + 0xd021f405, +/* 0x0223: mmctx_stop */ + 0xc82b0ef4, + 0xb4b600ab, + 0x0cb9f010, + 0xf112b9f0, + 0xf0c50007, + 0x0bd00103, +/* 0x023b: mmctx_stop_wait */ + 0xf104bd00, + 0xf0c500b7, + 0xbbcf01b3, + 0x12bbc800, +/* 0x024b: mmctx_done */ + 0xbdf31bf4, + 0x0199f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x025e: strand_wait */ + 0xa0f900f8, + 0xf402a7f0, + 0xa0fcd021, +/* 0x026a: strand_pre */ + 0x97f000f8, + 0xfc07f10c, + 0x0203f04a, + 0xbd0009d0, + 0x5e21f504, +/* 0x027f: strand_post */ + 0xf000f802, + 0x07f10d97, + 0x03f04afc, + 0x0009d002, + 0x21f504bd, + 0x00f8025e, +/* 0x0294: strand_set */ + 0xf10fc7f0, + 0xf04ffc07, + 0x0cd00203, + 0xf004bd00, + 0x07f10bc7, + 0x03f04afc, + 0x000cd002, + 0x07f104bd, + 0x03f04ffc, + 0x000ed002, + 0xc7f004bd, + 0xfc07f10a, + 0x0203f04a, + 0xbd000cd0, + 0x5e21f504, +/* 0x02d3: strand_ctx_init */ + 0xbd00f802, + 0x0399f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0x026a21f5, + 0xf503e7f0, + 0xbd029421, + 0xfc07f1c4, + 0x0203f047, + 0xbd000cd0, + 0x01c7f004, + 0x4afc07f1, + 0xd00203f0, + 0x04bd000c, + 0x025e21f5, + 0xf1010c92, + 0xf046fc07, + 0x0cd00203, + 0xf004bd00, + 0x07f102c7, + 0x03f04afc, + 0x000cd002, + 0x21f504bd, + 0x21f5025e, + 0x87f1027f, + 0x83f04200, + 0x0097f102, + 0x0293f020, + 0x950099cf, +/* 0x034a: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x037e: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x039b: init */ + 0xbd00f804, + 0x0007fe04, + 0x420017f1, + 0xcf0013f0, + 0x11e70011, + 0x14b60109, + 0x0014fe08, + 0xf10227f0, + 0xf0120007, + 0x02d00003, + 0xf104bd00, + 0xfe06c817, + 0x24bd0010, + 0x070007f1, + 0xd00003f0, + 0x04bd0002, + 0x200327f1, + 0x010007f1, + 0xd00103f0, + 0x04bd0002, + 0x200427f1, + 0x010407f1, + 0xd00103f0, + 0x04bd0002, + 0x200b27f1, + 0x010807f1, + 0xd00103f0, + 0x04bd0002, + 0x200c27f1, + 0x011c07f1, + 0xd00103f0, + 0x04bd0002, + 0xf1010392, + 0xf0090007, + 0x03d00303, + 0xf104bd00, + 0xf0870427, + 0x07f10023, + 0x03f00400, + 0x0002d000, + 0x27f004bd, + 0x0007f104, + 0x0003f003, + 0xbd0002d0, + 0x1031f404, + 0x9604e7f1, + 0xf440e3f0, + 0xfeb96821, + 0x90f1c702, + 0xf0030180, + 0x0f801ff4, + 0x0117f002, + 0xb6041fbb, + 0x07f10112, + 0x03f00300, + 0x0001d001, + 0x07f104bd, + 0x03f00400, + 0x0001d001, + 0x17f104bd, + 0xf7f00100, + 0xd721f502, + 0xe921f507, + 0x10f7f007, + 0x083621f5, + 0x98000e98, + 0x21f5010f, + 0x14950150, + 0x0007f108, + 0x0103f0c0, + 0xbd0004d0, + 0x0007f104, + 0x0103f0c1, + 0xbd0004d0, + 0x0030b704, + 0x001fbb13, + 0xf102f5b6, + 0xf0d30007, + 0x0fd00103, + 0xb604bd00, + 0x10b60815, + 0x0814b601, + 0xf5021fb9, + 0xbb02d321, + 0x0398001f, + 0x0047f102, + 0x5043f020, +/* 0x04f4: init_gpc */ + 0x08044ea0, + 0xf4021fb9, + 0x4ea09d21, + 0xf4bd010c, + 0xa09d21f4, + 0xf401044e, + 0x4ea09d21, + 0xf7f00100, + 0x9d21f402, + 0x08004ea0, +/* 0x051c: init_gpc_wait */ + 0xc86821f4, + 0x0bf41fff, + 0x044ea0fa, + 0x6821f408, + 0xb7001fbb, + 0xb6800040, + 0x1bf40132, + 0x00f7f0be, + 0x083621f5, + 0xf500f7f0, + 0xf107d721, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x300007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0564: main */ + 0xf40031f4, + 0xd7f00028, + 0x3921f410, + 0xb1f401f4, + 0xf54001e4, + 0xbd00e91b, + 0x0499f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0xc00017f1, + 0xcf0213f0, + 0x27f10011, + 0x23f0c100, + 0x0022cf02, + 0xf51f13c8, + 0xc800890b, + 0x0bf41f23, + 0xb920f962, + 0x94bd0212, + 0xf10799f0, + 0xf0370007, + 0x09d00203, + 0xf404bd00, + 0x31f40132, + 0x0221f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x20fc04bd, + 0x99f094bd, + 0x0007f106, + 0x0203f037, + 0xbd0009d0, + 0x0131f404, + 0x0a0221f5, + 0x99f094bd, + 0x0007f106, + 0x0203f017, + 0xbd0009d0, + 0x330ef404, +/* 0x060c: chsw_prev_no_next */ + 0x12b920f9, + 0x0132f402, + 0xf50232f4, + 0xfc0a0221, + 0x0007f120, + 0x0203f0c0, + 0xbd0002d0, + 0x130ef404, +/* 0x062c: chsw_no_prev */ + 0xf41f23c8, + 0x31f40d0b, + 0x0232f401, + 0x0a0221f5, +/* 0x063c: chsw_done */ + 0xf10127f0, + 0xf0c30007, + 0x02d00203, + 0xbd04bd00, + 0x0499f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0xff080ef5, +/* 0x0660: main_not_ctx_switch */ + 0xf401e4b0, + 0xf2b90d1b, + 0x9a21f502, + 0x460ef409, +/* 0x0670: main_not_ctx_chan */ + 0xf402e4b0, + 0x94bd321b, + 0xf10799f0, + 0xf0370007, + 0x09d00203, + 0xf404bd00, + 0x32f40132, + 0x0221f502, + 0xf094bd0a, + 0x07f10799, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x06a5: main_not_ctx_save */ + 0x10ef9411, + 0xf501f5f0, + 0xf5037e21, +/* 0x06b3: main_done */ + 0xbdfeb50e, + 0x1f29f024, + 0x300007f1, + 0xd00203f0, + 0x04bd0002, + 0xfea00ef5, +/* 0x06c8: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x00a7f104, + 0x00a3f002, + 0xc400aacf, + 0x0bf404ab, + 0x10d7f030, + 0x1a00e7f1, + 0xcf00e3f0, + 0xf7f100ee, + 0xf3f01900, + 0x00ffcf00, + 0xb70421f4, + 0xf00400b0, + 0x07f101e7, + 0x03f01d00, + 0x000ed000, +/* 0x071a: ih_no_fifo */ + 0xabe404bd, + 0x0bf40100, + 0x10d7f00d, + 0x4001e7f1, +/* 0x072b: ih_no_ctxsw */ + 0xe40421f4, + 0xf40400ab, + 0xe7f16c0b, + 0xe3f00708, + 0x6821f440, + 0xf102ffb9, + 0xf0040007, + 0x0fd00203, + 0xf104bd00, + 0xf00704e7, + 0x21f440e3, + 0x02ffb968, + 0x030007f1, + 0xd00203f0, + 0x04bd000f, + 0x9450fec7, + 0xf7f102ee, + 0xf3f00700, + 0x00efbb40, + 0xf16821f4, + 0xf0020007, + 0x0fd00203, + 0xf004bd00, + 0x21f503f7, + 0xb7f1037e, + 0xbfb90100, + 0x44e7f102, + 0x40e3f001, +/* 0x079b: ih_no_fwmthd */ + 0xf19d21f4, + 0xbd0504b7, + 0xb4abffb0, + 0xf10f0bf4, + 0xf0070007, + 0x0bd00303, +/* 0x07b3: ih_no_other */ + 0xf104bd00, + 0xf0010007, + 0x0ad00003, + 0xfc04bd00, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x07d7: ctx_4170s */ + 0xf001f800, + 0xffb910f5, + 0x70e7f102, + 0x40e3f041, + 0xf89d21f4, +/* 0x07e9: ctx_4170w */ + 0x70e7f100, + 0x40e3f041, + 0xb96821f4, + 0xf4f002ff, + 0xf01bf410, +/* 0x07fe: ctx_redswitch */ + 0xe7f100f8, + 0xe5f00200, + 0x20e5f040, + 0xf110e5f0, + 0xf0850007, + 0x0ed00103, + 0xf004bd00, +/* 0x081a: ctx_redswitch_delay */ + 0xf2b608f7, + 0xfd1bf401, + 0x0400e5f1, + 0x0100e5f1, + 0x850007f1, + 0xd00103f0, + 0x04bd000e, +/* 0x0836: ctx_86c */ + 0x07f100f8, + 0x03f02300, + 0x000fd002, + 0xffb904bd, + 0x14e7f102, + 0x40e3f08a, + 0xb99d21f4, + 0xe7f102ff, + 0xe3f0a88c, + 0x9d21f441, +/* 0x085e: ctx_mem */ + 0x07f100f8, + 0x03f08400, + 0x000fd002, +/* 0x086a: ctx_mem_wait */ + 0xf7f104bd, + 0xf3f08400, + 0x00ffcf02, + 0xf405fffd, + 0x00f8f31b, +/* 0x087c: ctx_load */ + 0x99f094bd, + 0x0007f105, + 0x0203f037, + 0xbd0009d0, + 0x0ca7f004, + 0xbdd021f4, + 0x0007f1f4, + 0x0203f089, + 0xbd000fd0, + 0x0007f104, + 0x0203f0c1, + 0xbd0002d0, + 0x0007f104, + 0x0203f083, + 0xbd0002d0, + 0x07f7f004, + 0x085e21f5, + 0xc00007f1, + 0xd00203f0, + 0x04bd0002, + 0xf0000bfe, + 0x24b61f2a, + 0x0220b604, + 0x99f094bd, + 0x0007f108, + 0x0203f037, + 0xbd0009d0, + 0x0007f104, + 0x0203f081, + 0xbd0002d0, + 0x0027f104, + 0x0023f100, + 0x0225f080, + 0x880007f1, + 0xd00203f0, + 0x04bd0002, + 0xf11017f0, + 0xf0020027, + 0x12fa0223, + 0xbd03f805, + 0x0899f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0xb6810198, + 0x02981814, + 0x0825b680, + 0x800512fd, + 0x94bd1601, + 0xf10999f0, + 0xf0370007, + 0x09d00203, + 0xf104bd00, + 0xf0810007, + 0x01d00203, + 0xf004bd00, + 0x07f10127, + 0x03f08800, + 0x0002d002, + 0x17f104bd, + 0x13f00100, + 0x0501fa06, + 0x94bd03f8, + 0xf10999f0, + 0xf0170007, + 0x09d00203, + 0xbd04bd00, + 0x0599f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x099a: ctx_chan */ + 0x21f500f8, + 0xa7f0087c, + 0xd021f40c, + 0xf505f7f0, + 0xf8085e21, +/* 0x09ad: ctx_mmio_exec */ + 0x41039800, + 0x810007f1, + 0xd00203f0, + 0x04bd0003, +/* 0x09be: ctx_mmio_loop */ + 0x34c434bd, + 0x0f1bf4ff, + 0x020057f1, + 0xfa0653f0, + 0x03f80535, +/* 0x09d0: ctx_mmio_pull */ + 0x98804e98, + 0x21f4814f, + 0x0830b69d, + 0xf40112b6, +/* 0x09e2: ctx_mmio_done */ + 0x0398df1b, + 0x0007f116, + 0x0203f081, + 0xbd0003d0, + 0x40008004, + 0x010017f1, + 0xfa0613f0, + 0x03f80601, +/* 0x0a02: ctx_xfer */ + 0xe7f000f8, + 0x0007f104, + 0x0303f002, + 0xbd000ed0, +/* 0x0a11: ctx_xfer_idle */ + 0x00e7f104, + 0x03e3f000, + 0xf100eecf, + 0xf42000e4, + 0x11f4f21b, + 0x0d02f406, +/* 0x0a28: ctx_xfer_pre */ + 0xf510f7f0, + 0xf4083621, +/* 0x0a32: ctx_xfer_pre_load */ + 0xf7f01c11, + 0xd721f502, + 0xe921f507, + 0xfe21f507, + 0xf5f4bd07, + 0xf507d721, +/* 0x0a4b: ctx_xfer_exec */ + 0x98087c21, + 0x24bd1601, + 0x050007f1, + 0xd00103f0, + 0x04bd0002, + 0xf1021fb9, + 0xf0a500e7, + 0x21f441e3, + 0x01fcf09d, + 0xb6022cf0, + 0xf2fd0124, + 0x02ffb905, + 0xa504e7f1, + 0xf441e3f0, + 0x21f59d21, + 0x24bd026a, + 0x47fc07f1, + 0xd00203f0, + 0x04bd0002, + 0xb6012cf0, + 0x07f10320, + 0x03f04afc, + 0x0002d002, + 0xacf004bd, + 0x06a5f001, + 0x9800b7f0, + 0x0d98000c, + 0x00e7f001, + 0x016f21f5, + 0xf508a7f0, + 0xf5011021, + 0xf4025e21, + 0xa7f01301, + 0xd021f40c, + 0xf505f7f0, + 0xf4085e21, +/* 0x0ada: ctx_xfer_post */ + 0xf7f02e02, + 0xd721f502, + 0xf5f4bd07, + 0xf5083621, + 0xf5027f21, + 0xbd07e921, + 0xd721f5f4, + 0x1011f407, + 0xfd400198, + 0x0bf40511, + 0xad21f507, +/* 0x0b05: ctx_xfer_no_post_mmio */ +/* 0x0b05: ctx_xfer_done */ + 0x0000f809, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc new file mode 100644 index 000000000000..2a0b0f844299 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc @@ -0,0 +1,229 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "os.h" + +#define GF100 0xc0 +#define GF117 0xd7 +#define GK100 0xe0 +#define GK110 0xf0 +#define GK208 0x108 + +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c + +#define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700) + +#define NV_PGRAPH_FECS_INTR_ACK 0x409004 +#define NV_PGRAPH_FECS_INTR 0x409008 +#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 +#define NV_PGRAPH_FECS_INTR_CHSW 0x00000100 +#define NV_PGRAPH_FECS_INTR_FIFO 0x00000004 +#define NV_PGRAPH_FECS_INTR_MODE 0x40900c +#define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004 +#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004 +#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000 +#define NV_PGRAPH_FECS_INTR_EN_SET 0x409010 +#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004 +#define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c +#define NV_PGRAPH_FECS_ACCESS 0x409048 +#define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002 +#define NV_PGRAPH_FECS_FIFO_DATA 0x409064 +#define NV_PGRAPH_FECS_FIFO_CMD 0x409068 +#define NV_PGRAPH_FECS_FIFO_ACK 0x409074 +#define NV_PGRAPH_FECS_CAPS 0x409108 +#define NV_PGRAPH_FECS_SIGNAL 0x409400 +#define NV_PGRAPH_FECS_IROUTE 0x409404 +#define NV_PGRAPH_FECS_BAR_MASK0 0x40940c +#define NV_PGRAPH_FECS_BAR_MASK1 0x409410 +#define NV_PGRAPH_FECS_BAR 0x409414 +#define NV_PGRAPH_FECS_BAR_SET 0x409418 +#define NV_PGRAPH_FECS_RED_SWITCH 0x409614 +#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400 +#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200 +#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100 +#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040 +#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020 +#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010 +#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002 +#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001 +#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 +#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 +#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c +#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 +#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 +#define NV_PGRAPH_FECS_MMCTX_BASE 0x409710 +#define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714 +#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718 +#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c +#define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720 +#define NV_PGRAPH_FECS_MMIO_CTRL 0x409728 +#define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c +#define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730 +#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c +#if CHIPSET < GK110 +#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) +#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) +#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) +#define NV_PGRAPH_FECS_UNK86C 0x40986c +#else +#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) +#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) +#define NV_PGRAPH_FECS_UNK86C 0x40988c +#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) +#endif +#define NV_PGRAPH_FECS_STRANDS_CNT 0x409880 +#define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908 +#define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c +#define NV_PGRAPH_FECS_STRAND_WORDS 0x409910 +#define NV_PGRAPH_FECS_STRAND_DATA 0x409918 +#define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c +#define NV_PGRAPH_FECS_STRAND_CMD 0x409928 +#define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001 +#define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002 +#define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003 +#define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004 +#define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a +#define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b +#define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c +#define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d +#define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c +#define NV_PGRAPH_FECS_MEM_BASE 0x409a04 +#define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c +#define NV_PGRAPH_FECS_MEM_CMD 0x409a10 +#define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007 +#define NV_PGRAPH_FECS_MEM_TARGET 0x409a20 +#define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000 +#define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f +#define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001 +#define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002 +#define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00 +#define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04 +#define NV_PGRAPH_FECS_CHSW 0x409b0c +#define NV_PGRAPH_FECS_CHSW_ACK 0x00000001 +#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c +#define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24 + +#define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004 +#define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008 +#define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004 +#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010 +#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004 +#define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c +#define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048 +#define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002 +#define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064 +#define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068 +#define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074 +#define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608 +#define NV_PGRAPH_GPCX_GPCCS_CAPS 0x41a108 +#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614 +#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800 +#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200 +#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020 +#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002 +#define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618 +#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700 +#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704 +#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c +#if CHIPSET < GK110 +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) +#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c +#else +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) +#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) +#endif +#define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c +#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928 +#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003 +#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004 +#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04 + +#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) +#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) + +#define T_WAIT 0 +#define T_MMCTX 1 +#define T_STRWAIT 2 +#define T_STRINIT 3 +#define T_AUTO 4 +#define T_CHAN 5 +#define T_LOAD 6 +#define T_SAVE 7 +#define T_LCHAN 8 +#define T_LCTXH 9 + +#if CHIPSET < GK208 +#define imm32(reg,val) /* +*/ movw reg ((val) & 0x0000ffff) /* +*/ sethi reg ((val) & 0xffff0000) +#else +#define imm32(reg,val) /* +*/ mov reg (val) +#endif + +#define nv_mkio(rv,r,i) /* +*/ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2)) + +#define hash # +#define fn(a) a +#if CHIPSET < GK208 +#define call(a) call fn(hash)a +#else +#define call(a) lcall fn(hash)a +#endif + +#define nv_iord(rv,r,i) /* +*/ nv_mkio(rv,r,i) /* +*/ iord rv I[rv] + +#define nv_iowr(r,i,rv) /* +*/ nv_mkio($r0,r,i) /* +*/ iowr I[$r0] rv /* +*/ clear b32 $r0 + +#define nv_rd32(reg,addr) /* +*/ imm32($r14, addr) /* +*/ call(nv_rd32) /* +*/ mov b32 reg $r15 + +#define nv_wr32(addr,reg) /* +*/ mov b32 $r15 reg /* +*/ imm32($r14, addr) /* +*/ call(nv_wr32) + +#define trace_set(bit) /* +*/ clear b32 $r9 /* +*/ bset $r9 bit /* +*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) + +#define trace_clr(bit) /* +*/ clear b32 $r9 /* +*/ bset $r9 bit /* +*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h new file mode 100644 index 000000000000..1718ae4e8224 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h @@ -0,0 +1,8 @@ +#ifndef __NVKM_GRAPH_OS_H__ +#define __NVKM_GRAPH_OS_H__ + +#define E_BAD_COMMAND 0x00000001 +#define E_CMD_OVERFLOW 0x00000002 +#define E_BAD_FWMTHD 0x00000003 + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c new file mode 100644 index 000000000000..59d7d9bf7bb5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -0,0 +1,117 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +gk110b_gr_init_l1c_0[] = { + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x09000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00b08bea }, + { 0x419c84, 1, 0x04, 0x00010384 }, + { 0x419cbc, 1, 0x04, 0x281b3646 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x00020230 }, + { 0x419ccc, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gk110b_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000080 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ee4, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00000000 }, + { 0x419eb4, 1, 0x04, 0x00000000 }, + { 0x419ebc, 2, 0x04, 0x00000000 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419ed0, 1, 0x04, 0x00002616 }, + { 0x419f74, 1, 0x04, 0x00015555 }, + { 0x419f80, 4, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +gk110b_gr_pack_mmio[] = { + { nve4_gr_init_main_0 }, + { nvf0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvd9_gr_init_pd_0 }, + { nvf0_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvf0_gr_init_sked_0 }, + { nvf0_gr_init_cwd_0 }, + { nvd9_gr_init_prop_0 }, + { nvc1_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvd9_gr_init_gpm_0 }, + { nvf0_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nve4_gr_init_tpccs_0 }, + { nvf0_gr_init_tex_0 }, + { nve4_gr_init_pe_0 }, + { gk110b_gr_init_l1c_0 }, + { nvc0_gr_init_mpc_0 }, + { gk110b_gr_init_sm_0 }, + { nvd7_gr_init_pes_0 }, + { nvd7_gr_init_wwdx_0 }, + { nvd7_gr_init_cbm_0 }, + { nve4_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nouveau_oclass * +gk110b_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xf1), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nve4_gr_init, + .fini = nvf0_gr_fini, + }, + .cclass = &gk110b_grctx_oclass, + .sclass = nvf0_gr_sclass, + .mmio = gk110b_gr_pack_mmio, + .fecs.ucode = &nvf0_gr_fecs_ucode, + .gpccs.ucode = &nvf0_gr_gpccs_ucode, + .ppc_nr = 2, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c new file mode 100644 index 000000000000..082ea9f08e1c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +static struct nouveau_oclass +gk20a_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa040, &nouveau_object_ofuncs }, + { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +struct nouveau_oclass * +gk20a_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xea), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nve4_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &gk20a_grctx_oclass, + .sclass = gk20a_gr_sclass, + .mmio = nve4_gr_pack_mmio, + .ppc_nr = 1, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c new file mode 100644 index 000000000000..5a4669087a17 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -0,0 +1,469 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +gm107_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa140, &nouveau_object_ofuncs }, + { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +gm107_gr_init_main_0[] = { + { 0x400080, 1, 0x04, 0x003003c2 }, + { 0x400088, 1, 0x04, 0x0001bfe7 }, + { 0x40008c, 1, 0x04, 0x00060000 }, + { 0x400090, 1, 0x04, 0x00000030 }, + { 0x40013c, 1, 0x04, 0x003901f3 }, + { 0x400140, 1, 0x04, 0x00000100 }, + { 0x400144, 1, 0x04, 0x00000000 }, + { 0x400148, 1, 0x04, 0x00000110 }, + { 0x400138, 1, 0x04, 0x00000000 }, + { 0x400130, 2, 0x04, 0x00000000 }, + { 0x400124, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x00000000 }, + { 0x405908, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_scc_0[] = { + { 0x40803c, 1, 0x04, 0x00000010 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_sked_0[] = { + { 0x407010, 1, 0x04, 0x00000000 }, + { 0x407040, 1, 0x04, 0x40440424 }, + { 0x407048, 1, 0x04, 0x0000000a }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_prop_0[] = { + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x4184a0, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_setup_1[] = { + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00010201 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_zcull_0[] = { + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418930, 2, 0x04, 0x00000000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_gpc_unk_1[] = { + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000400 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_tpccs_0[] = { + { 0x419dc4, 1, 0x04, 0x00000000 }, + { 0x419dc8, 1, 0x04, 0x00000501 }, + { 0x419dd0, 1, 0x04, 0x00000000 }, + { 0x419dd4, 1, 0x04, 0x00000100 }, + { 0x419dd8, 1, 0x04, 0x00000001 }, + { 0x419ddc, 1, 0x04, 0x00000002 }, + { 0x419de0, 1, 0x04, 0x00000001 }, + { 0x419d0c, 1, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_tex_0[] = { + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 1, 0x04, 0x00000000 }, + { 0x419acc, 1, 0x04, 0x000000ff }, + { 0x419ac0, 1, 0x04, 0x00000000 }, + { 0x419aa8, 2, 0x04, 0x00000000 }, + { 0x419ad0, 2, 0x04, 0x00000000 }, + { 0x419ae0, 2, 0x04, 0x00000000 }, + { 0x419af0, 4, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_pe_0[] = { + { 0x419900, 1, 0x04, 0x000000ff }, + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x419838, 1, 0x04, 0x000000ff }, + { 0x419850, 1, 0x04, 0x00000004 }, + { 0x419854, 2, 0x04, 0x00000000 }, + { 0x419894, 3, 0x04, 0x00100401 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_l1c_0[] = { + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_sm_0[] = { + { 0x419e30, 1, 0x04, 0x000000ff }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ee4, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x01000000 }, + { 0x419ee8, 1, 0x04, 0x00000091 }, + { 0x419eb4, 1, 0x04, 0x00000000 }, + { 0x419ebc, 2, 0x04, 0x00000000 }, + { 0x419edc, 1, 0x04, 0x000c1810 }, + { 0x419ed8, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00000000 }, + { 0x419f74, 1, 0x04, 0x00005155 }, + { 0x419f80, 4, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_l1c_1[] = { + { 0x419ccc, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x3f006022 }, + { 0x419c88, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_pes_0[] = { + { 0x41be50, 1, 0x04, 0x000000ff }, + { 0x41be04, 1, 0x04, 0x00000000 }, + { 0x41be08, 1, 0x04, 0x00000004 }, + { 0x41be0c, 1, 0x04, 0x00000008 }, + { 0x41be10, 1, 0x04, 0x0e3b8bc7 }, + { 0x41be14, 2, 0x04, 0x00000000 }, + { 0x41be3c, 5, 0x04, 0x00100401 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_wwdx_0[] = { + { 0x41bfd4, 1, 0x04, 0x00800000 }, + { 0x41bfdc, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_cbm_0[] = { + { 0x41becc, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_be_0[] = { + { 0x408890, 1, 0x04, 0x000000ff }, + { 0x40880c, 1, 0x04, 0x00000000 }, + { 0x408850, 1, 0x04, 0x00000004 }, + { 0x408878, 1, 0x04, 0x00c81603 }, + { 0x40887c, 1, 0x04, 0x80543432 }, + { 0x408880, 1, 0x04, 0x0010581e }, + { 0x408884, 1, 0x04, 0x00001205 }, + { 0x408974, 1, 0x04, 0x000000ff }, + { 0x408910, 9, 0x04, 0x00000000 }, + { 0x408950, 1, 0x04, 0x00000000 }, + { 0x408954, 1, 0x04, 0x0000ffff }, + { 0x408958, 1, 0x04, 0x00000034 }, + { 0x40895c, 1, 0x04, 0x8531a003 }, + { 0x408960, 1, 0x04, 0x0561985a }, + { 0x408964, 1, 0x04, 0x04e15c4f }, + { 0x408968, 1, 0x04, 0x02808833 }, + { 0x40896c, 1, 0x04, 0x01f02438 }, + { 0x408970, 1, 0x04, 0x00012c00 }, + { 0x408984, 1, 0x04, 0x00000000 }, + { 0x408988, 1, 0x04, 0x08040201 }, + { 0x40898c, 1, 0x04, 0x80402010 }, + {} +}; + +static const struct nvc0_gr_init +gm107_gr_init_sm_1[] = { + { 0x419e5c, 1, 0x04, 0x00000000 }, + { 0x419e58, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +gm107_gr_pack_mmio[] = { + { gm107_gr_init_main_0 }, + { nvf0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvc0_gr_init_pd_0 }, + { gm107_gr_init_ds_0 }, + { gm107_gr_init_scc_0 }, + { gm107_gr_init_sked_0 }, + { nvf0_gr_init_cwd_0 }, + { gm107_gr_init_prop_0 }, + { nv108_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { gm107_gr_init_setup_1 }, + { gm107_gr_init_zcull_0 }, + { nvc0_gr_init_gpm_0 }, + { gm107_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { gm107_gr_init_tpccs_0 }, + { gm107_gr_init_tex_0 }, + { gm107_gr_init_pe_0 }, + { gm107_gr_init_l1c_0 }, + { nvc0_gr_init_mpc_0 }, + { gm107_gr_init_sm_0 }, + { gm107_gr_init_l1c_1 }, + { gm107_gr_init_pes_0 }, + { gm107_gr_init_wwdx_0 }, + { gm107_gr_init_cbm_0 }, + { gm107_gr_init_be_0 }, + { gm107_gr_init_sm_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static void +gm107_gr_init_bios(struct nvc0_gr_priv *priv) +{ + static const struct { + u32 ctrl; + u32 data; + } regs[] = { + { 0x419ed8, 0x419ee0 }, + { 0x419ad0, 0x419ad4 }, + { 0x419ae0, 0x419ae4 }, + { 0x419af0, 0x419af4 }, + { 0x419af8, 0x419afc }, + }; + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_P0260E infoE; + struct nvbios_P0260X infoX; + int E = -1, X; + u8 ver, hdr; + + while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { + if (X = -1, E < ARRAY_SIZE(regs)) { + nv_wr32(priv, regs[E].ctrl, infoE.data); + while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) + nv_wr32(priv, regs[E].data, infoX.data); + } + } +} + +int +gm107_gr_init(struct nouveau_object *object) +{ + struct nvc0_gr_oclass *oclass = (void *)object->oclass; + struct nvc0_gr_priv *priv = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + u32 data[TPC_MAX / 8] = {}; + u8 tpcnr[GPC_MAX]; + int gpc, tpc, ppc, rop; + int ret, i; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); + nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + + nvc0_gr_mmio(priv, oclass->mmio); + + gm107_gr_init_bios(priv); + + nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); + + memset(data, 0x00, sizeof(data)); + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + data[i / 8] |= tpc << ((i % 8) * 4); + } + + nv_wr32(priv, GPC_BCAST(0x0980), data[0]); + nv_wr32(priv, GPC_BCAST(0x0984), data[1]); + nv_wr32(priv, GPC_BCAST(0x0988), data[2]); + nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0914), + priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | + priv->tpc_total); + nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); + + nv_wr32(priv, 0x400500, 0x00010001); + + nv_wr32(priv, 0x400100, 0xffffffff); + nv_wr32(priv, 0x40013c, 0xffffffff); + nv_wr32(priv, 0x400124, 0x00000002); + nv_wr32(priv, 0x409c24, 0x000e0000); + + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(priv, 0x408030, 0xc0000000); + nv_wr32(priv, 0x404490, 0xc0000000); + nv_wr32(priv, 0x406018, 0xc0000000); + nv_wr32(priv, 0x407020, 0x40000000); + nv_wr32(priv, 0x405840, 0xc0000000); + nv_wr32(priv, 0x405844, 0x00ffffff); + nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++) + nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); + } + nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + } + + for (rop = 0; rop < priv->rop_nr; rop++) { + nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); + nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); + nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + } + + nv_wr32(priv, 0x400108, 0xffffffff); + nv_wr32(priv, 0x400138, 0xffffffff); + nv_wr32(priv, 0x400118, 0xffffffff); + nv_wr32(priv, 0x400130, 0xffffffff); + nv_wr32(priv, 0x40011c, 0xffffffff); + nv_wr32(priv, 0x400134, 0xffffffff); + + nv_wr32(priv, 0x400054, 0x2c350f63); + + nvc0_gr_zbc_init(priv); + + return nvc0_gr_init_ctxctl(priv); +} + +#include "fuc/hubgm107.fuc5.h" + +static struct nvc0_gr_ucode +gm107_gr_fecs_ucode = { + .code.data = gm107_grhub_code, + .code.size = sizeof(gm107_grhub_code), + .data.data = gm107_grhub_data, + .data.size = sizeof(gm107_grhub_data), +}; + +#include "fuc/gpcgm107.fuc5.h" + +static struct nvc0_gr_ucode +gm107_gr_gpccs_ucode = { + .code.data = gm107_grgpc_code, + .code.size = sizeof(gm107_grgpc_code), + .data.data = gm107_grgpc_data, + .data.size = sizeof(gm107_grgpc_data), +}; + +struct nouveau_oclass * +gm107_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0x07), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = gm107_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &gm107_grctx_oclass, + .sclass = gm107_gr_sclass, + .mmio = gm107_gr_pack_mmio, + .fecs.ucode = 0 ? &gm107_gr_fecs_ucode : NULL, + .gpccs.ucode = &gm107_gr_gpccs_ucode, + .ppc_nr = 2, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c new file mode 100644 index 000000000000..4d25c9532b2b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -0,0 +1,1388 @@ +/* + * Copyright 2007 Stephane Marchesin + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragr) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "regs.h" + +static u32 +nv04_gr_ctx_regs[] = { + 0x0040053c, + 0x00400544, + 0x00400540, + 0x00400548, + NV04_PGRAPH_CTX_SWITCH1, + NV04_PGRAPH_CTX_SWITCH2, + NV04_PGRAPH_CTX_SWITCH3, + NV04_PGRAPH_CTX_SWITCH4, + NV04_PGRAPH_CTX_CACHE1, + NV04_PGRAPH_CTX_CACHE2, + NV04_PGRAPH_CTX_CACHE3, + NV04_PGRAPH_CTX_CACHE4, + 0x00400184, + 0x004001a4, + 0x004001c4, + 0x004001e4, + 0x00400188, + 0x004001a8, + 0x004001c8, + 0x004001e8, + 0x0040018c, + 0x004001ac, + 0x004001cc, + 0x004001ec, + 0x00400190, + 0x004001b0, + 0x004001d0, + 0x004001f0, + 0x00400194, + 0x004001b4, + 0x004001d4, + 0x004001f4, + 0x00400198, + 0x004001b8, + 0x004001d8, + 0x004001f8, + 0x0040019c, + 0x004001bc, + 0x004001dc, + 0x004001fc, + 0x00400174, + NV04_PGRAPH_DMA_START_0, + NV04_PGRAPH_DMA_START_1, + NV04_PGRAPH_DMA_LENGTH, + NV04_PGRAPH_DMA_MISC, + NV04_PGRAPH_DMA_PITCH, + NV04_PGRAPH_BOFFSET0, + NV04_PGRAPH_BBASE0, + NV04_PGRAPH_BLIMIT0, + NV04_PGRAPH_BOFFSET1, + NV04_PGRAPH_BBASE1, + NV04_PGRAPH_BLIMIT1, + NV04_PGRAPH_BOFFSET2, + NV04_PGRAPH_BBASE2, + NV04_PGRAPH_BLIMIT2, + NV04_PGRAPH_BOFFSET3, + NV04_PGRAPH_BBASE3, + NV04_PGRAPH_BLIMIT3, + NV04_PGRAPH_BOFFSET4, + NV04_PGRAPH_BBASE4, + NV04_PGRAPH_BLIMIT4, + NV04_PGRAPH_BOFFSET5, + NV04_PGRAPH_BBASE5, + NV04_PGRAPH_BLIMIT5, + NV04_PGRAPH_BPITCH0, + NV04_PGRAPH_BPITCH1, + NV04_PGRAPH_BPITCH2, + NV04_PGRAPH_BPITCH3, + NV04_PGRAPH_BPITCH4, + NV04_PGRAPH_SURFACE, + NV04_PGRAPH_STATE, + NV04_PGRAPH_BSWIZZLE2, + NV04_PGRAPH_BSWIZZLE5, + NV04_PGRAPH_BPIXEL, + NV04_PGRAPH_NOTIFY, + NV04_PGRAPH_PATT_COLOR0, + NV04_PGRAPH_PATT_COLOR1, + NV04_PGRAPH_PATT_COLORRAM+0x00, + NV04_PGRAPH_PATT_COLORRAM+0x04, + NV04_PGRAPH_PATT_COLORRAM+0x08, + NV04_PGRAPH_PATT_COLORRAM+0x0c, + NV04_PGRAPH_PATT_COLORRAM+0x10, + NV04_PGRAPH_PATT_COLORRAM+0x14, + NV04_PGRAPH_PATT_COLORRAM+0x18, + NV04_PGRAPH_PATT_COLORRAM+0x1c, + NV04_PGRAPH_PATT_COLORRAM+0x20, + NV04_PGRAPH_PATT_COLORRAM+0x24, + NV04_PGRAPH_PATT_COLORRAM+0x28, + NV04_PGRAPH_PATT_COLORRAM+0x2c, + NV04_PGRAPH_PATT_COLORRAM+0x30, + NV04_PGRAPH_PATT_COLORRAM+0x34, + NV04_PGRAPH_PATT_COLORRAM+0x38, + NV04_PGRAPH_PATT_COLORRAM+0x3c, + NV04_PGRAPH_PATT_COLORRAM+0x40, + NV04_PGRAPH_PATT_COLORRAM+0x44, + NV04_PGRAPH_PATT_COLORRAM+0x48, + NV04_PGRAPH_PATT_COLORRAM+0x4c, + NV04_PGRAPH_PATT_COLORRAM+0x50, + NV04_PGRAPH_PATT_COLORRAM+0x54, + NV04_PGRAPH_PATT_COLORRAM+0x58, + NV04_PGRAPH_PATT_COLORRAM+0x5c, + NV04_PGRAPH_PATT_COLORRAM+0x60, + NV04_PGRAPH_PATT_COLORRAM+0x64, + NV04_PGRAPH_PATT_COLORRAM+0x68, + NV04_PGRAPH_PATT_COLORRAM+0x6c, + NV04_PGRAPH_PATT_COLORRAM+0x70, + NV04_PGRAPH_PATT_COLORRAM+0x74, + NV04_PGRAPH_PATT_COLORRAM+0x78, + NV04_PGRAPH_PATT_COLORRAM+0x7c, + NV04_PGRAPH_PATT_COLORRAM+0x80, + NV04_PGRAPH_PATT_COLORRAM+0x84, + NV04_PGRAPH_PATT_COLORRAM+0x88, + NV04_PGRAPH_PATT_COLORRAM+0x8c, + NV04_PGRAPH_PATT_COLORRAM+0x90, + NV04_PGRAPH_PATT_COLORRAM+0x94, + NV04_PGRAPH_PATT_COLORRAM+0x98, + NV04_PGRAPH_PATT_COLORRAM+0x9c, + NV04_PGRAPH_PATT_COLORRAM+0xa0, + NV04_PGRAPH_PATT_COLORRAM+0xa4, + NV04_PGRAPH_PATT_COLORRAM+0xa8, + NV04_PGRAPH_PATT_COLORRAM+0xac, + NV04_PGRAPH_PATT_COLORRAM+0xb0, + NV04_PGRAPH_PATT_COLORRAM+0xb4, + NV04_PGRAPH_PATT_COLORRAM+0xb8, + NV04_PGRAPH_PATT_COLORRAM+0xbc, + NV04_PGRAPH_PATT_COLORRAM+0xc0, + NV04_PGRAPH_PATT_COLORRAM+0xc4, + NV04_PGRAPH_PATT_COLORRAM+0xc8, + NV04_PGRAPH_PATT_COLORRAM+0xcc, + NV04_PGRAPH_PATT_COLORRAM+0xd0, + NV04_PGRAPH_PATT_COLORRAM+0xd4, + NV04_PGRAPH_PATT_COLORRAM+0xd8, + NV04_PGRAPH_PATT_COLORRAM+0xdc, + NV04_PGRAPH_PATT_COLORRAM+0xe0, + NV04_PGRAPH_PATT_COLORRAM+0xe4, + NV04_PGRAPH_PATT_COLORRAM+0xe8, + NV04_PGRAPH_PATT_COLORRAM+0xec, + NV04_PGRAPH_PATT_COLORRAM+0xf0, + NV04_PGRAPH_PATT_COLORRAM+0xf4, + NV04_PGRAPH_PATT_COLORRAM+0xf8, + NV04_PGRAPH_PATT_COLORRAM+0xfc, + NV04_PGRAPH_PATTERN, + 0x0040080c, + NV04_PGRAPH_PATTERN_SHAPE, + 0x00400600, + NV04_PGRAPH_ROP3, + NV04_PGRAPH_CHROMA, + NV04_PGRAPH_BETA_AND, + NV04_PGRAPH_BETA_PREMULT, + NV04_PGRAPH_CONTROL0, + NV04_PGRAPH_CONTROL1, + NV04_PGRAPH_CONTROL2, + NV04_PGRAPH_BLEND, + NV04_PGRAPH_STORED_FMT, + NV04_PGRAPH_SOURCE_COLOR, + 0x00400560, + 0x00400568, + 0x00400564, + 0x0040056c, + 0x00400400, + 0x00400480, + 0x00400404, + 0x00400484, + 0x00400408, + 0x00400488, + 0x0040040c, + 0x0040048c, + 0x00400410, + 0x00400490, + 0x00400414, + 0x00400494, + 0x00400418, + 0x00400498, + 0x0040041c, + 0x0040049c, + 0x00400420, + 0x004004a0, + 0x00400424, + 0x004004a4, + 0x00400428, + 0x004004a8, + 0x0040042c, + 0x004004ac, + 0x00400430, + 0x004004b0, + 0x00400434, + 0x004004b4, + 0x00400438, + 0x004004b8, + 0x0040043c, + 0x004004bc, + 0x00400440, + 0x004004c0, + 0x00400444, + 0x004004c4, + 0x00400448, + 0x004004c8, + 0x0040044c, + 0x004004cc, + 0x00400450, + 0x004004d0, + 0x00400454, + 0x004004d4, + 0x00400458, + 0x004004d8, + 0x0040045c, + 0x004004dc, + 0x00400460, + 0x004004e0, + 0x00400464, + 0x004004e4, + 0x00400468, + 0x004004e8, + 0x0040046c, + 0x004004ec, + 0x00400470, + 0x004004f0, + 0x00400474, + 0x004004f4, + 0x00400478, + 0x004004f8, + 0x0040047c, + 0x004004fc, + 0x00400534, + 0x00400538, + 0x00400514, + 0x00400518, + 0x0040051c, + 0x00400520, + 0x00400524, + 0x00400528, + 0x0040052c, + 0x00400530, + 0x00400d00, + 0x00400d40, + 0x00400d80, + 0x00400d04, + 0x00400d44, + 0x00400d84, + 0x00400d08, + 0x00400d48, + 0x00400d88, + 0x00400d0c, + 0x00400d4c, + 0x00400d8c, + 0x00400d10, + 0x00400d50, + 0x00400d90, + 0x00400d14, + 0x00400d54, + 0x00400d94, + 0x00400d18, + 0x00400d58, + 0x00400d98, + 0x00400d1c, + 0x00400d5c, + 0x00400d9c, + 0x00400d20, + 0x00400d60, + 0x00400da0, + 0x00400d24, + 0x00400d64, + 0x00400da4, + 0x00400d28, + 0x00400d68, + 0x00400da8, + 0x00400d2c, + 0x00400d6c, + 0x00400dac, + 0x00400d30, + 0x00400d70, + 0x00400db0, + 0x00400d34, + 0x00400d74, + 0x00400db4, + 0x00400d38, + 0x00400d78, + 0x00400db8, + 0x00400d3c, + 0x00400d7c, + 0x00400dbc, + 0x00400590, + 0x00400594, + 0x00400598, + 0x0040059c, + 0x004005a8, + 0x004005ac, + 0x004005b0, + 0x004005b4, + 0x004005c0, + 0x004005c4, + 0x004005c8, + 0x004005cc, + 0x004005d0, + 0x004005d4, + 0x004005d8, + 0x004005dc, + 0x004005e0, + NV04_PGRAPH_PASSTHRU_0, + NV04_PGRAPH_PASSTHRU_1, + NV04_PGRAPH_PASSTHRU_2, + NV04_PGRAPH_DVD_COLORFMT, + NV04_PGRAPH_SCALED_FORMAT, + NV04_PGRAPH_MISC24_0, + NV04_PGRAPH_MISC24_1, + NV04_PGRAPH_MISC24_2, + 0x00400500, + 0x00400504, + NV04_PGRAPH_VALID1, + NV04_PGRAPH_VALID2, + NV04_PGRAPH_DEBUG_3 +}; + +struct nv04_gr_priv { + struct nouveau_gr base; + struct nv04_gr_chan *chan[16]; + spinlock_t lock; +}; + +struct nv04_gr_chan { + struct nouveau_object base; + int chid; + u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)]; +}; + + +static inline struct nv04_gr_priv * +nv04_gr_priv(struct nv04_gr_chan *chan) +{ + return (void *)nv_object(chan)->engine; +} + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +/* + * Software methods, why they are needed, and how they all work: + * + * NV04 and NV05 keep most of the state in PGRAPH context itself, but some + * 2d engine settings are kept inside the grobjs themselves. The grobjs are + * 3 words long on both. grobj format on NV04 is: + * + * word 0: + * - bits 0-7: class + * - bit 12: color key active + * - bit 13: clip rect active + * - bit 14: if set, destination surface is swizzled and taken from buffer 5 + * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken + * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or + * NV03_CONTEXT_SURFACE_DST]. + * - bits 15-17: 2d operation [aka patch config] + * - bit 24: patch valid [enables rendering using this object] + * - bit 25: surf3d valid [for tex_tri and multitex_tri only] + * word 1: + * - bits 0-1: mono format + * - bits 8-13: color format + * - bits 16-31: DMA_NOTIFY instance + * word 2: + * - bits 0-15: DMA_A instance + * - bits 16-31: DMA_B instance + * + * On NV05 it's: + * + * word 0: + * - bits 0-7: class + * - bit 12: color key active + * - bit 13: clip rect active + * - bit 14: if set, destination surface is swizzled and taken from buffer 5 + * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken + * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or + * NV03_CONTEXT_SURFACE_DST]. + * - bits 15-17: 2d operation [aka patch config] + * - bits 20-22: dither mode + * - bit 24: patch valid [enables rendering using this object] + * - bit 25: surface_dst/surface_color/surf2d/surf3d valid + * - bit 26: surface_src/surface_zeta valid + * - bit 27: pattern valid + * - bit 28: rop valid + * - bit 29: beta1 valid + * - bit 30: beta4 valid + * word 1: + * - bits 0-1: mono format + * - bits 8-13: color format + * - bits 16-31: DMA_NOTIFY instance + * word 2: + * - bits 0-15: DMA_A instance + * - bits 16-31: DMA_B instance + * + * NV05 will set/unset the relevant valid bits when you poke the relevant + * object-binding methods with object of the proper type, or with the NULL + * type. It'll only allow rendering using the grobj if all needed objects + * are bound. The needed set of objects depends on selected operation: for + * example rop object is needed by ROP_AND, but not by SRCCOPY_AND. + * + * NV04 doesn't have these methods implemented at all, and doesn't have the + * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24 + * is set. So we have to emulate them in software, internally keeping the + * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04, + * but the last word isn't actually used for anything, we abuse it for this + * purpose. + * + * Actually, NV05 can optionally check bit 24 too, but we disable this since + * there's no use for it. + * + * For unknown reasons, NV04 implements surf3d binding in hardware as an + * exception. Also for unknown reasons, NV04 doesn't implement the clipping + * methods on the surf3d object, so we have to emulate them too. + */ + +static void +nv04_gr_set_ctx1(struct nouveau_object *object, u32 mask, u32 value) +{ + struct nv04_gr_priv *priv = (void *)object->engine; + int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; + u32 tmp; + + tmp = nv_ro32(object, 0x00); + tmp &= ~mask; + tmp |= value; + nv_wo32(object, 0x00, tmp); + + nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp); + nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); +} + +static void +nv04_gr_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value) +{ + int class, op, valid = 1; + u32 tmp, ctx1; + + ctx1 = nv_ro32(object, 0x00); + class = ctx1 & 0xff; + op = (ctx1 >> 15) & 7; + + tmp = nv_ro32(object, 0x0c); + tmp &= ~mask; + tmp |= value; + nv_wo32(object, 0x0c, tmp); + + /* check for valid surf2d/surf_dst/surf_color */ + if (!(tmp & 0x02000000)) + valid = 0; + /* check for valid surf_src/surf_zeta */ + if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000)) + valid = 0; + + switch (op) { + /* SRCCOPY_AND, SRCCOPY: no extra objects required */ + case 0: + case 3: + break; + /* ROP_AND: requires pattern and rop */ + case 1: + if (!(tmp & 0x18000000)) + valid = 0; + break; + /* BLEND_AND: requires beta1 */ + case 2: + if (!(tmp & 0x20000000)) + valid = 0; + break; + /* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */ + case 4: + case 5: + if (!(tmp & 0x40000000)) + valid = 0; + break; + } + + nv04_gr_set_ctx1(object, 0x01000000, valid << 24); +} + +static int +nv04_gr_mthd_set_operation(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + u32 class = nv_ro32(object, 0) & 0xff; + u32 data = *(u32 *)args; + if (data > 5) + return 1; + /* Old versions of the objects only accept first three operations. */ + if (data > 2 && class < 0x40) + return 1; + nv04_gr_set_ctx1(object, 0x00038000, data << 15); + /* changing operation changes set of objects needed for validation */ + nv04_gr_set_ctx_val(object, 0, 0); + return 0; +} + +static int +nv04_gr_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv04_gr_priv *priv = (void *)object->engine; + u32 data = *(u32 *)args; + u32 min = data & 0xffff, max; + u32 w = data >> 16; + if (min & 0x8000) + /* too large */ + return 1; + if (w & 0x8000) + /* yes, it accepts negative for some reason. */ + w |= 0xffff0000; + max = min + w; + max &= 0x3ffff; + nv_wr32(priv, 0x40053c, min); + nv_wr32(priv, 0x400544, max); + return 0; +} + +static int +nv04_gr_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv04_gr_priv *priv = (void *)object->engine; + u32 data = *(u32 *)args; + u32 min = data & 0xffff, max; + u32 w = data >> 16; + if (min & 0x8000) + /* too large */ + return 1; + if (w & 0x8000) + /* yes, it accepts negative for some reason. */ + w |= 0xffff0000; + max = min + w; + max &= 0x3ffff; + nv_wr32(priv, 0x400540, min); + nv_wr32(priv, 0x400548, max); + return 0; +} + +static u16 +nv04_gr_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size) +{ + struct nouveau_instmem *imem = nouveau_instmem(object); + u32 inst = *(u32 *)args << 4; + return nv_ro32(imem, inst); +} + +static int +nv04_gr_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0); + return 0; + case 0x42: + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0); + return 0; + case 0x42: + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); + return 0; + case 0x52: + nv04_gr_set_ctx1(object, 0x00004000, 0x00004000); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); + return 0; + } + return 1; +} + +static int +nv01_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x08000000, 0); + return 0; + case 0x18: + nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x08000000, 0); + return 0; + case 0x44: + nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_rop(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x10000000, 0); + return 0; + case 0x43: + nv04_gr_set_ctx_val(object, 0x10000000, 0x10000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_beta1(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x20000000, 0); + return 0; + case 0x12: + nv04_gr_set_ctx_val(object, 0x20000000, 0x20000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_beta4(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x40000000, 0); + return 0; + case 0x72: + nv04_gr_set_ctx_val(object, 0x40000000, 0x40000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x02000000, 0); + return 0; + case 0x58: + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x04000000, 0); + return 0; + case 0x59: + nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x02000000, 0); + return 0; + case 0x5a: + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); + return 0; + } + return 1; +} + +static int +nv04_gr_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx_val(object, 0x04000000, 0); + return 0; + case 0x5b: + nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000); + return 0; + } + return 1; +} + +static int +nv01_gr_mthd_bind_clip(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx1(object, 0x2000, 0); + return 0; + case 0x19: + nv04_gr_set_ctx1(object, 0x2000, 0x2000); + return 0; + } + return 1; +} + +static int +nv01_gr_mthd_bind_chroma(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + switch (nv04_gr_mthd_bind_class(object, args, size)) { + case 0x30: + nv04_gr_set_ctx1(object, 0x1000, 0); + return 0; + /* Yes, for some reason even the old versions of objects + * accept 0x57 and not 0x17. Consistency be damned. + */ + case 0x57: + nv04_gr_set_ctx1(object, 0x1000, 0x1000); + return 0; + } + return 1; +} + +static struct nouveau_omthds +nv03_gr_gdi_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_patt }, + { 0x0188, 0x0188, nv04_gr_mthd_bind_rop }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_beta1 }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_gdi_omthds[] = { + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv01_gr_blit_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv01_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_surf_src }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_blit_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_iifc_omthds[] = { + { 0x0188, 0x0188, nv01_gr_mthd_bind_chroma }, + { 0x018c, 0x018c, nv01_gr_mthd_bind_clip }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_patt }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_rop }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_beta1 }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_beta4 }, + { 0x01a0, 0x01a0, nv04_gr_mthd_bind_surf2d_swzsurf }, + { 0x03e4, 0x03e4, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv01_gr_ifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv01_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_ifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv03_gr_sifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_sifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv03_gr_sifm_omthds[] = { + { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, + { 0x0304, 0x0304, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_sifm_omthds[] = { + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x0304, 0x0304, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_surf3d_omthds[] = { + { 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h }, + { 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v }, + {} +}; + +static struct nouveau_omthds +nv03_gr_ttri_omthds[] = { + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_zeta }, + {} +}; + +static struct nouveau_omthds +nv01_gr_prim_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_clip }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static struct nouveau_omthds +nv04_gr_prim_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_clip }, + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, + {} +}; + +static int +nv04_gr_object_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_gpuobj *obj; + int ret; + + ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, + 16, 16, 0, &obj); + *pobject = nv_object(obj); + if (ret) + return ret; + + nv_wo32(obj, 0x00, nv_mclass(obj)); +#ifdef __BIG_ENDIAN + nv_mo32(obj, 0x00, 0x00080000, 0x00080000); +#endif + nv_wo32(obj, 0x04, 0x00000000); + nv_wo32(obj, 0x08, 0x00000000); + nv_wo32(obj, 0x0c, 0x00000000); + return 0; +} + +struct nouveau_ofuncs +nv04_gr_ofuncs = { + .ctor = nv04_gr_object_ctor, + .dtor = _nouveau_gpuobj_dtor, + .init = _nouveau_gpuobj_init, + .fini = _nouveau_gpuobj_fini, + .rd32 = _nouveau_gpuobj_rd32, + .wr32 = _nouveau_gpuobj_wr32, +}; + +static struct nouveau_oclass +nv04_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0017, &nv04_gr_ofuncs }, /* chroma */ + { 0x0018, &nv04_gr_ofuncs }, /* pattern (nv01) */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x001c, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* line */ + { 0x001d, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* tri */ + { 0x001e, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* rect */ + { 0x001f, &nv04_gr_ofuncs, nv01_gr_blit_omthds }, + { 0x0021, &nv04_gr_ofuncs, nv01_gr_ifc_omthds }, + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0036, &nv04_gr_ofuncs, nv03_gr_sifc_omthds }, + { 0x0037, &nv04_gr_ofuncs, nv03_gr_sifm_omthds }, + { 0x0038, &nv04_gr_ofuncs }, /* dvd subpicture */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0042, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x0048, &nv04_gr_ofuncs, nv03_gr_ttri_omthds }, + { 0x004a, &nv04_gr_ofuncs, nv04_gr_gdi_omthds }, + { 0x004b, &nv04_gr_ofuncs, nv03_gr_gdi_omthds }, + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x0053, &nv04_gr_ofuncs, nv04_gr_surf3d_omthds }, + { 0x0054, &nv04_gr_ofuncs }, /* ttri */ + { 0x0055, &nv04_gr_ofuncs }, /* mtri */ + { 0x0057, &nv04_gr_ofuncs }, /* chroma */ + { 0x0058, &nv04_gr_ofuncs }, /* surf_dst */ + { 0x0059, &nv04_gr_ofuncs }, /* surf_src */ + { 0x005a, &nv04_gr_ofuncs }, /* surf_color */ + { 0x005b, &nv04_gr_ofuncs }, /* surf_zeta */ + { 0x005c, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* line */ + { 0x005d, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* tri */ + { 0x005e, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* rect */ + { 0x005f, &nv04_gr_ofuncs, nv04_gr_blit_omthds }, + { 0x0060, &nv04_gr_ofuncs, nv04_gr_iifc_omthds }, + { 0x0061, &nv04_gr_ofuncs, nv04_gr_ifc_omthds }, + { 0x0064, &nv04_gr_ofuncs }, /* iifc (nv05) */ + { 0x0065, &nv04_gr_ofuncs }, /* ifc (nv05) */ + { 0x0066, &nv04_gr_ofuncs }, /* sifc (nv05) */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0076, &nv04_gr_ofuncs, nv04_gr_sifc_omthds }, + { 0x0077, &nv04_gr_ofuncs, nv04_gr_sifm_omthds }, + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static struct nv04_gr_chan * +nv04_gr_channel(struct nv04_gr_priv *priv) +{ + struct nv04_gr_chan *chan = NULL; + if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { + int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; + if (chid < ARRAY_SIZE(priv->chan)) + chan = priv->chan[chid]; + } + return chan; +} + +static int +nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) +{ + struct nv04_gr_priv *priv = nv04_gr_priv(chan); + int i; + + for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) + nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]); + + nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100); + nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); + nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); + return 0; +} + +static int +nv04_gr_unload_context(struct nv04_gr_chan *chan) +{ + struct nv04_gr_priv *priv = nv04_gr_priv(chan); + int i; + + for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) + chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]); + + nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000); + nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + return 0; +} + +static void +nv04_gr_context_switch(struct nv04_gr_priv *priv) +{ + struct nv04_gr_chan *prev = NULL; + struct nv04_gr_chan *next = NULL; + unsigned long flags; + int chid; + + spin_lock_irqsave(&priv->lock, flags); + nv04_gr_idle(priv); + + /* If previous context is valid, we need to save it */ + prev = nv04_gr_channel(priv); + if (prev) + nv04_gr_unload_context(prev); + + /* load context for next channel */ + chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; + next = priv->chan[chid]; + if (next) + nv04_gr_load_context(next, chid); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) { + if (nv04_gr_ctx_regs[i] == reg) + return &chan->nv04[i]; + } + + return NULL; +} + +static int +nv04_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_fifo_chan *fifo = (void *)parent; + struct nv04_gr_priv *priv = (void *)engine; + struct nv04_gr_chan *chan; + unsigned long flags; + int ret; + + ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + spin_lock_irqsave(&priv->lock, flags); + if (priv->chan[fifo->chid]) { + *pobject = nv_object(priv->chan[fifo->chid]); + atomic_inc(&(*pobject)->refcount); + spin_unlock_irqrestore(&priv->lock, flags); + nouveau_object_destroy(&chan->base); + return 1; + } + + *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; + + priv->chan[fifo->chid] = chan; + chan->chid = fifo->chid; + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static void +nv04_gr_context_dtor(struct nouveau_object *object) +{ + struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr_chan *chan = (void *)object; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->chan[chan->chid] = NULL; + spin_unlock_irqrestore(&priv->lock, flags); + + nouveau_object_destroy(&chan->base); +} + +static int +nv04_gr_context_fini(struct nouveau_object *object, bool suspend) +{ + struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr_chan *chan = (void *)object; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + if (nv04_gr_channel(priv) == chan) + nv04_gr_unload_context(chan); + nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&priv->lock, flags); + + return nouveau_object_fini(&chan->base, suspend); +} + +static struct nouveau_oclass +nv04_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_gr_context_ctor, + .dtor = nv04_gr_context_dtor, + .init = nouveau_object_init, + .fini = nv04_gr_context_fini, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +bool +nv04_gr_idle(void *obj) +{ + struct nouveau_gr *gr = nouveau_gr(obj); + u32 mask = 0xffffffff; + + if (nv_device(obj)->card_type == NV_40) + mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; + + if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) { + nv_error(gr, "idle timed out with status 0x%08x\n", + nv_rd32(gr, NV04_PGRAPH_STATUS)); + return false; + } + + return true; +} + +static const struct nouveau_bitfield +nv04_gr_intr_name[] = { + { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, + {} +}; + +static const struct nouveau_bitfield +nv04_gr_nstatus[] = { + { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, + { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, + { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, + { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }, + {} +}; + +const struct nouveau_bitfield +nv04_gr_nsource[] = { + { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, + { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, + { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, + { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" }, + { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" }, + { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" }, + { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" }, + { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" }, + { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" }, + { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" }, + { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" }, + { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" }, + { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" }, + { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" }, + { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" }, + { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" }, + { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" }, + { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" }, + { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" }, + {} +}; + +static void +nv04_gr_intr(struct nouveau_subdev *subdev) +{ + struct nv04_gr_priv *priv = (void *)subdev; + struct nv04_gr_chan *chan = NULL; + struct nouveau_namedb *namedb = NULL; + struct nouveau_handle *handle = NULL; + u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); + u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + u32 chid = (addr & 0x0f000000) >> 24; + u32 subc = (addr & 0x0000e000) >> 13; + u32 mthd = (addr & 0x00001ffc); + u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff; + u32 inst = (nv_rd32(priv, 0x40016c) & 0xffff) << 4; + u32 show = stat; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + chan = priv->chan[chid]; + if (chan) + namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); + spin_unlock_irqrestore(&priv->lock, flags); + + if (stat & NV_PGRAPH_INTR_NOTIFY) { + if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { + handle = nouveau_namedb_get_vinst(namedb, inst); + if (handle && !nv_call(handle->object, mthd, data)) + show &= ~NV_PGRAPH_INTR_NOTIFY; + } + } + + if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { + nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); + stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + nv04_gr_context_switch(priv); + } + + nv_wr32(priv, NV03_PGRAPH_INTR, stat); + nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + + if (show) { + nv_error(priv, "%s", ""); + nouveau_bitfield_print(nv04_gr_intr_name, show); + pr_cont(" nsource:"); + nouveau_bitfield_print(nv04_gr_nsource, nsource); + pr_cont(" nstatus:"); + nouveau_bitfield_print(nv04_gr_nstatus, nstatus); + pr_cont("\n"); + nv_error(priv, + "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, nouveau_client_name(chan), subc, class, mthd, + data); + } + + nouveau_namedb_put(handle); +} + +static int +nv04_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv04_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv04_gr_intr; + nv_engine(priv)->cclass = &nv04_gr_cclass; + nv_engine(priv)->sclass = nv04_gr_sclass; + spin_lock_init(&priv->lock); + return 0; +} + +static int +nv04_gr_init(struct nouveau_object *object) +{ + struct nouveau_engine *engine = nv_engine(object); + struct nv04_gr_priv *priv = (void *)engine; + int ret; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + /* Enable PGRAPH interrupts */ + nv_wr32(priv, NV03_PGRAPH_INTR, 0xFFFFFFFF); + nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(priv, NV04_PGRAPH_VALID1, 0); + nv_wr32(priv, NV04_PGRAPH_VALID2, 0); + /*nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x000001FF); + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x1231c000); + /*1231C000 blob, 001 haiku*/ + /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ + nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x72111100); + /*0x72111100 blob , 01 haiku*/ + /*nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ + nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f071); + /*haiku same*/ + + /*nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ + nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); + /*haiku and blob 10d4*/ + + nv_wr32(priv, NV04_PGRAPH_STATE , 0xFFFFFFFF); + nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL , 0x10000100); + nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + + /* These don't belong here, they're part of a per-channel context */ + nv_wr32(priv, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); + nv_wr32(priv, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); + return 0; +} + +struct nouveau_oclass +nv04_gr_oclass = { + .handle = NV_ENGINE(GR, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_gr_ctor, + .dtor = _nouveau_gr_dtor, + .init = nv04_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c new file mode 100644 index 000000000000..9cc5c25f571b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -0,0 +1,1319 @@ +/* + * Copyright 2007 Matthieu CASTET + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragr) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include + +#include +#include + +#include "regs.h" + +struct pipe_state { + u32 pipe_0x0000[0x040/4]; + u32 pipe_0x0040[0x010/4]; + u32 pipe_0x0200[0x0c0/4]; + u32 pipe_0x4400[0x080/4]; + u32 pipe_0x6400[0x3b0/4]; + u32 pipe_0x6800[0x2f0/4]; + u32 pipe_0x6c00[0x030/4]; + u32 pipe_0x7000[0x130/4]; + u32 pipe_0x7400[0x0c0/4]; + u32 pipe_0x7800[0x0c0/4]; +}; + +static int nv10_gr_ctx_regs[] = { + NV10_PGRAPH_CTX_SWITCH(0), + NV10_PGRAPH_CTX_SWITCH(1), + NV10_PGRAPH_CTX_SWITCH(2), + NV10_PGRAPH_CTX_SWITCH(3), + NV10_PGRAPH_CTX_SWITCH(4), + NV10_PGRAPH_CTX_CACHE(0, 0), + NV10_PGRAPH_CTX_CACHE(0, 1), + NV10_PGRAPH_CTX_CACHE(0, 2), + NV10_PGRAPH_CTX_CACHE(0, 3), + NV10_PGRAPH_CTX_CACHE(0, 4), + NV10_PGRAPH_CTX_CACHE(1, 0), + NV10_PGRAPH_CTX_CACHE(1, 1), + NV10_PGRAPH_CTX_CACHE(1, 2), + NV10_PGRAPH_CTX_CACHE(1, 3), + NV10_PGRAPH_CTX_CACHE(1, 4), + NV10_PGRAPH_CTX_CACHE(2, 0), + NV10_PGRAPH_CTX_CACHE(2, 1), + NV10_PGRAPH_CTX_CACHE(2, 2), + NV10_PGRAPH_CTX_CACHE(2, 3), + NV10_PGRAPH_CTX_CACHE(2, 4), + NV10_PGRAPH_CTX_CACHE(3, 0), + NV10_PGRAPH_CTX_CACHE(3, 1), + NV10_PGRAPH_CTX_CACHE(3, 2), + NV10_PGRAPH_CTX_CACHE(3, 3), + NV10_PGRAPH_CTX_CACHE(3, 4), + NV10_PGRAPH_CTX_CACHE(4, 0), + NV10_PGRAPH_CTX_CACHE(4, 1), + NV10_PGRAPH_CTX_CACHE(4, 2), + NV10_PGRAPH_CTX_CACHE(4, 3), + NV10_PGRAPH_CTX_CACHE(4, 4), + NV10_PGRAPH_CTX_CACHE(5, 0), + NV10_PGRAPH_CTX_CACHE(5, 1), + NV10_PGRAPH_CTX_CACHE(5, 2), + NV10_PGRAPH_CTX_CACHE(5, 3), + NV10_PGRAPH_CTX_CACHE(5, 4), + NV10_PGRAPH_CTX_CACHE(6, 0), + NV10_PGRAPH_CTX_CACHE(6, 1), + NV10_PGRAPH_CTX_CACHE(6, 2), + NV10_PGRAPH_CTX_CACHE(6, 3), + NV10_PGRAPH_CTX_CACHE(6, 4), + NV10_PGRAPH_CTX_CACHE(7, 0), + NV10_PGRAPH_CTX_CACHE(7, 1), + NV10_PGRAPH_CTX_CACHE(7, 2), + NV10_PGRAPH_CTX_CACHE(7, 3), + NV10_PGRAPH_CTX_CACHE(7, 4), + NV10_PGRAPH_CTX_USER, + NV04_PGRAPH_DMA_START_0, + NV04_PGRAPH_DMA_START_1, + NV04_PGRAPH_DMA_LENGTH, + NV04_PGRAPH_DMA_MISC, + NV10_PGRAPH_DMA_PITCH, + NV04_PGRAPH_BOFFSET0, + NV04_PGRAPH_BBASE0, + NV04_PGRAPH_BLIMIT0, + NV04_PGRAPH_BOFFSET1, + NV04_PGRAPH_BBASE1, + NV04_PGRAPH_BLIMIT1, + NV04_PGRAPH_BOFFSET2, + NV04_PGRAPH_BBASE2, + NV04_PGRAPH_BLIMIT2, + NV04_PGRAPH_BOFFSET3, + NV04_PGRAPH_BBASE3, + NV04_PGRAPH_BLIMIT3, + NV04_PGRAPH_BOFFSET4, + NV04_PGRAPH_BBASE4, + NV04_PGRAPH_BLIMIT4, + NV04_PGRAPH_BOFFSET5, + NV04_PGRAPH_BBASE5, + NV04_PGRAPH_BLIMIT5, + NV04_PGRAPH_BPITCH0, + NV04_PGRAPH_BPITCH1, + NV04_PGRAPH_BPITCH2, + NV04_PGRAPH_BPITCH3, + NV04_PGRAPH_BPITCH4, + NV10_PGRAPH_SURFACE, + NV10_PGRAPH_STATE, + NV04_PGRAPH_BSWIZZLE2, + NV04_PGRAPH_BSWIZZLE5, + NV04_PGRAPH_BPIXEL, + NV10_PGRAPH_NOTIFY, + NV04_PGRAPH_PATT_COLOR0, + NV04_PGRAPH_PATT_COLOR1, + NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ + 0x00400904, + 0x00400908, + 0x0040090c, + 0x00400910, + 0x00400914, + 0x00400918, + 0x0040091c, + 0x00400920, + 0x00400924, + 0x00400928, + 0x0040092c, + 0x00400930, + 0x00400934, + 0x00400938, + 0x0040093c, + 0x00400940, + 0x00400944, + 0x00400948, + 0x0040094c, + 0x00400950, + 0x00400954, + 0x00400958, + 0x0040095c, + 0x00400960, + 0x00400964, + 0x00400968, + 0x0040096c, + 0x00400970, + 0x00400974, + 0x00400978, + 0x0040097c, + 0x00400980, + 0x00400984, + 0x00400988, + 0x0040098c, + 0x00400990, + 0x00400994, + 0x00400998, + 0x0040099c, + 0x004009a0, + 0x004009a4, + 0x004009a8, + 0x004009ac, + 0x004009b0, + 0x004009b4, + 0x004009b8, + 0x004009bc, + 0x004009c0, + 0x004009c4, + 0x004009c8, + 0x004009cc, + 0x004009d0, + 0x004009d4, + 0x004009d8, + 0x004009dc, + 0x004009e0, + 0x004009e4, + 0x004009e8, + 0x004009ec, + 0x004009f0, + 0x004009f4, + 0x004009f8, + 0x004009fc, + NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ + 0x0040080c, + NV04_PGRAPH_PATTERN_SHAPE, + NV03_PGRAPH_MONO_COLOR0, + NV04_PGRAPH_ROP3, + NV04_PGRAPH_CHROMA, + NV04_PGRAPH_BETA_AND, + NV04_PGRAPH_BETA_PREMULT, + 0x00400e70, + 0x00400e74, + 0x00400e78, + 0x00400e7c, + 0x00400e80, + 0x00400e84, + 0x00400e88, + 0x00400e8c, + 0x00400ea0, + 0x00400ea4, + 0x00400ea8, + 0x00400e90, + 0x00400e94, + 0x00400e98, + 0x00400e9c, + NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */ + NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */ + 0x00400f04, + 0x00400f24, + 0x00400f08, + 0x00400f28, + 0x00400f0c, + 0x00400f2c, + 0x00400f10, + 0x00400f30, + 0x00400f14, + 0x00400f34, + 0x00400f18, + 0x00400f38, + 0x00400f1c, + 0x00400f3c, + NV10_PGRAPH_XFMODE0, + NV10_PGRAPH_XFMODE1, + NV10_PGRAPH_GLOBALSTATE0, + NV10_PGRAPH_GLOBALSTATE1, + NV04_PGRAPH_STORED_FMT, + NV04_PGRAPH_SOURCE_COLOR, + NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ + NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ + 0x00400404, + 0x00400484, + 0x00400408, + 0x00400488, + 0x0040040c, + 0x0040048c, + 0x00400410, + 0x00400490, + 0x00400414, + 0x00400494, + 0x00400418, + 0x00400498, + 0x0040041c, + 0x0040049c, + 0x00400420, + 0x004004a0, + 0x00400424, + 0x004004a4, + 0x00400428, + 0x004004a8, + 0x0040042c, + 0x004004ac, + 0x00400430, + 0x004004b0, + 0x00400434, + 0x004004b4, + 0x00400438, + 0x004004b8, + 0x0040043c, + 0x004004bc, + 0x00400440, + 0x004004c0, + 0x00400444, + 0x004004c4, + 0x00400448, + 0x004004c8, + 0x0040044c, + 0x004004cc, + 0x00400450, + 0x004004d0, + 0x00400454, + 0x004004d4, + 0x00400458, + 0x004004d8, + 0x0040045c, + 0x004004dc, + 0x00400460, + 0x004004e0, + 0x00400464, + 0x004004e4, + 0x00400468, + 0x004004e8, + 0x0040046c, + 0x004004ec, + 0x00400470, + 0x004004f0, + 0x00400474, + 0x004004f4, + 0x00400478, + 0x004004f8, + 0x0040047c, + 0x004004fc, + NV03_PGRAPH_ABS_UCLIP_XMIN, + NV03_PGRAPH_ABS_UCLIP_XMAX, + NV03_PGRAPH_ABS_UCLIP_YMIN, + NV03_PGRAPH_ABS_UCLIP_YMAX, + 0x00400550, + 0x00400558, + 0x00400554, + 0x0040055c, + NV03_PGRAPH_ABS_UCLIPA_XMIN, + NV03_PGRAPH_ABS_UCLIPA_XMAX, + NV03_PGRAPH_ABS_UCLIPA_YMIN, + NV03_PGRAPH_ABS_UCLIPA_YMAX, + NV03_PGRAPH_ABS_ICLIP_XMAX, + NV03_PGRAPH_ABS_ICLIP_YMAX, + NV03_PGRAPH_XY_LOGIC_MISC0, + NV03_PGRAPH_XY_LOGIC_MISC1, + NV03_PGRAPH_XY_LOGIC_MISC2, + NV03_PGRAPH_XY_LOGIC_MISC3, + NV03_PGRAPH_CLIPX_0, + NV03_PGRAPH_CLIPX_1, + NV03_PGRAPH_CLIPY_0, + NV03_PGRAPH_CLIPY_1, + NV10_PGRAPH_COMBINER0_IN_ALPHA, + NV10_PGRAPH_COMBINER1_IN_ALPHA, + NV10_PGRAPH_COMBINER0_IN_RGB, + NV10_PGRAPH_COMBINER1_IN_RGB, + NV10_PGRAPH_COMBINER_COLOR0, + NV10_PGRAPH_COMBINER_COLOR1, + NV10_PGRAPH_COMBINER0_OUT_ALPHA, + NV10_PGRAPH_COMBINER1_OUT_ALPHA, + NV10_PGRAPH_COMBINER0_OUT_RGB, + NV10_PGRAPH_COMBINER1_OUT_RGB, + NV10_PGRAPH_COMBINER_FINAL0, + NV10_PGRAPH_COMBINER_FINAL1, + 0x00400e00, + 0x00400e04, + 0x00400e08, + 0x00400e0c, + 0x00400e10, + 0x00400e14, + 0x00400e18, + 0x00400e1c, + 0x00400e20, + 0x00400e24, + 0x00400e28, + 0x00400e2c, + 0x00400e30, + 0x00400e34, + 0x00400e38, + 0x00400e3c, + NV04_PGRAPH_PASSTHRU_0, + NV04_PGRAPH_PASSTHRU_1, + NV04_PGRAPH_PASSTHRU_2, + NV10_PGRAPH_DIMX_TEXTURE, + NV10_PGRAPH_WDIMX_TEXTURE, + NV10_PGRAPH_DVD_COLORFMT, + NV10_PGRAPH_SCALED_FORMAT, + NV04_PGRAPH_MISC24_0, + NV04_PGRAPH_MISC24_1, + NV04_PGRAPH_MISC24_2, + NV03_PGRAPH_X_MISC, + NV03_PGRAPH_Y_MISC, + NV04_PGRAPH_VALID1, + NV04_PGRAPH_VALID2, +}; + +static int nv17_gr_ctx_regs[] = { + NV10_PGRAPH_DEBUG_4, + 0x004006b0, + 0x00400eac, + 0x00400eb0, + 0x00400eb4, + 0x00400eb8, + 0x00400ebc, + 0x00400ec0, + 0x00400ec4, + 0x00400ec8, + 0x00400ecc, + 0x00400ed0, + 0x00400ed4, + 0x00400ed8, + 0x00400edc, + 0x00400ee0, + 0x00400a00, + 0x00400a04, +}; + +struct nv10_gr_priv { + struct nouveau_gr base; + struct nv10_gr_chan *chan[32]; + spinlock_t lock; +}; + +struct nv10_gr_chan { + struct nouveau_object base; + int chid; + int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)]; + int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)]; + struct pipe_state pipe_state; + u32 lma_window[4]; +}; + + +static inline struct nv10_gr_priv * +nv10_gr_priv(struct nv10_gr_chan *chan) +{ + return (void *)nv_object(chan)->engine; +} + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +#define PIPE_SAVE(priv, state, addr) \ + do { \ + int __i; \ + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ + for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ + state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \ + } while (0) + +#define PIPE_RESTORE(priv, state, addr) \ + do { \ + int __i; \ + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ + for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \ + } while (0) + +static struct nouveau_oclass +nv10_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x004a, &nv04_gr_ofuncs }, /* gdi */ + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x005f, &nv04_gr_ofuncs }, /* blit */ + { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs }, /* blit */ + { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ + { 0x0094, &nv04_gr_ofuncs }, /* ttri */ + { 0x0095, &nv04_gr_ofuncs }, /* mtri */ + { 0x0056, &nv04_gr_ofuncs }, /* celcius */ + {}, +}; + +static struct nouveau_oclass +nv15_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x004a, &nv04_gr_ofuncs }, /* gdi */ + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x005f, &nv04_gr_ofuncs }, /* blit */ + { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs }, /* blit */ + { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ + { 0x0094, &nv04_gr_ofuncs }, /* ttri */ + { 0x0095, &nv04_gr_ofuncs }, /* mtri */ + { 0x0096, &nv04_gr_ofuncs }, /* celcius */ + {}, +}; + +static int +nv17_gr_mthd_lma_window(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv10_gr_chan *chan = (void *)object->parent; + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct pipe_state *pipe = &chan->pipe_state; + u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; + u32 xfmode0, xfmode1; + u32 data = *(u32 *)args; + int i; + + chan->lma_window[(mthd - 0x1638) / 4] = data; + + if (mthd != 0x1644) + return 0; + + nv04_gr_idle(priv); + + PIPE_SAVE(priv, pipe_0x0040, 0x0040); + PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); + + PIPE_RESTORE(priv, chan->lma_window, 0x6790); + + nv04_gr_idle(priv); + + xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); + xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); + + PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); + PIPE_SAVE(priv, pipe_0x64c0, 0x64c0); + PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0); + PIPE_SAVE(priv, pipe_0x6a80, 0x6a80); + + nv04_gr_idle(priv); + + nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); + nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + for (i = 0; i < 4; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + for (i = 0; i < 4; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + for (i = 0; i < 3; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + for (i = 0; i < 3; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); + + PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); + + nv04_gr_idle(priv); + + PIPE_RESTORE(priv, pipe_0x0040, 0x0040); + + nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); + nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); + + PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0); + PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0); + PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80); + PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + + nv04_gr_idle(priv); + + return 0; +} + +static int +nv17_gr_mthd_lma_enable(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv10_gr_chan *chan = (void *)object->parent; + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + + nv04_gr_idle(priv); + + nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); + nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000); + return 0; +} + +static struct nouveau_omthds +nv17_celcius_omthds[] = { + { 0x1638, 0x1638, nv17_gr_mthd_lma_window }, + { 0x163c, 0x163c, nv17_gr_mthd_lma_window }, + { 0x1640, 0x1640, nv17_gr_mthd_lma_window }, + { 0x1644, 0x1644, nv17_gr_mthd_lma_window }, + { 0x1658, 0x1658, nv17_gr_mthd_lma_enable }, + {} +}; + +static struct nouveau_oclass +nv17_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x004a, &nv04_gr_ofuncs }, /* gdi */ + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x005f, &nv04_gr_ofuncs }, /* blit */ + { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs }, /* blit */ + { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ + { 0x0094, &nv04_gr_ofuncs }, /* ttri */ + { 0x0095, &nv04_gr_ofuncs }, /* mtri */ + { 0x0099, &nv04_gr_ofuncs, nv17_celcius_omthds }, + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static struct nv10_gr_chan * +nv10_gr_channel(struct nv10_gr_priv *priv) +{ + struct nv10_gr_chan *chan = NULL; + if (nv_rd32(priv, 0x400144) & 0x00010000) { + int chid = nv_rd32(priv, 0x400148) >> 24; + if (chid < ARRAY_SIZE(priv->chan)) + chan = priv->chan[chid]; + } + return chan; +} + +static void +nv10_gr_save_pipe(struct nv10_gr_chan *chan) +{ + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct pipe_state *pipe = &chan->pipe_state; + + PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); + PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); + PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400); + PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800); + PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00); + PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000); + PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400); + PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800); + PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040); + PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000); +} + +static void +nv10_gr_load_pipe(struct nv10_gr_chan *chan) +{ + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct pipe_state *pipe = &chan->pipe_state; + u32 xfmode0, xfmode1; + int i; + + nv04_gr_idle(priv); + /* XXX check haiku comments */ + xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); + xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); + nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); + nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + for (i = 0; i < 4; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + for (i = 0; i < 4; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + for (i = 0; i < 3; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + for (i = 0; i < 3; i++) + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + + nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); + + + PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); + nv04_gr_idle(priv); + + /* restore XFMODE */ + nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); + nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); + PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400); + PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800); + PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00); + PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000); + PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400); + PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800); + PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); + PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000); + PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040); + nv04_gr_idle(priv); +} + +static void +nv10_gr_create_pipe(struct nv10_gr_chan *chan) +{ + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct pipe_state *pipe_state = &chan->pipe_state; + u32 *pipe_state_addr; + int i; +#define PIPE_INIT(addr) \ + do { \ + pipe_state_addr = pipe_state->pipe_##addr; \ + } while (0) +#define PIPE_INIT_END(addr) \ + do { \ + u32 *__end_addr = pipe_state->pipe_##addr + \ + ARRAY_SIZE(pipe_state->pipe_##addr); \ + if (pipe_state_addr != __end_addr) \ + nv_error(priv, "incomplete pipe init for 0x%x : %p/%p\n", \ + addr, pipe_state_addr, __end_addr); \ + } while (0) +#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value + + PIPE_INIT(0x0200); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0200); + + PIPE_INIT(0x6400); + for (i = 0; i < 211; i++) + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f000000); + NV_WRITE_PIPE_INIT(0x3f000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + PIPE_INIT_END(0x6400); + + PIPE_INIT(0x6800); + for (i = 0; i < 162; i++) + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + for (i = 0; i < 25; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x6800); + + PIPE_INIT(0x6c00); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0xbf800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x6c00); + + PIPE_INIT(0x7000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + for (i = 0; i < 35; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7000); + + PIPE_INIT(0x7400); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7400); + + PIPE_INIT(0x7800); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7800); + + PIPE_INIT(0x4400); + for (i = 0; i < 32; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x4400); + + PIPE_INIT(0x0000); + for (i = 0; i < 16; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0000); + + PIPE_INIT(0x0040); + for (i = 0; i < 4; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0040); + +#undef PIPE_INIT +#undef PIPE_INIT_END +#undef NV_WRITE_PIPE_INIT +} + +static int +nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg) +{ + int i; + for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) { + if (nv10_gr_ctx_regs[i] == reg) + return i; + } + nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg); + return -1; +} + +static int +nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg) +{ + int i; + for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) { + if (nv17_gr_ctx_regs[i] == reg) + return i; + } + nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg); + return -1; +} + +static void +nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) +{ + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; + u32 ctx_user, ctx_switch[5]; + int i, subchan = -1; + + /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state + * that cannot be restored via MMIO. Do it through the FIFO + * instead. + */ + + /* Look for a celsius object */ + for (i = 0; i < 8; i++) { + int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; + + if (class == 0x56 || class == 0x96 || class == 0x99) { + subchan = i; + break; + } + } + + if (subchan < 0 || !inst) + return; + + /* Save the current ctx object */ + ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER); + for (i = 0; i < 5; i++) + ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i)); + + /* Save the FIFO state */ + st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2); + st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL); + st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH); + fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR); + + for (i = 0; i < ARRAY_SIZE(fifo); i++) + fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i); + + /* Switch to the celsius subchannel */ + for (i = 0; i < 5; i++) + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), + nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i))); + nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); + + /* Inject NV10TCL_DMA_VTXBUF */ + nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); + nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, + 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); + nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst); + nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); + nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + + /* Restore the FIFO state */ + for (i = 0; i < ARRAY_SIZE(fifo); i++) + nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]); + + nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); + nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2); + nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); + nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); + + /* Restore the current ctx object */ + for (i = 0; i < 5; i++) + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); + nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user); +} + +static int +nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) +{ + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + u32 inst; + int i; + + for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) + nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]); + + if (nv_device(priv)->card_type >= NV_11 && + nv_device(priv)->chipset >= 0x17) { + for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) + nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]); + } + + nv10_gr_load_pipe(chan); + + inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; + nv10_gr_load_dma_vtxbuf(chan, chid, inst); + + nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); + nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); + nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); + return 0; +} + +static int +nv10_gr_unload_context(struct nv10_gr_chan *chan) +{ + struct nv10_gr_priv *priv = nv10_gr_priv(chan); + int i; + + for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) + chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]); + + if (nv_device(priv)->card_type >= NV_11 && + nv_device(priv)->chipset >= 0x17) { + for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) + chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]); + } + + nv10_gr_save_pipe(chan); + + nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000); + nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); + return 0; +} + +static void +nv10_gr_context_switch(struct nv10_gr_priv *priv) +{ + struct nv10_gr_chan *prev = NULL; + struct nv10_gr_chan *next = NULL; + unsigned long flags; + int chid; + + spin_lock_irqsave(&priv->lock, flags); + nv04_gr_idle(priv); + + /* If previous context is valid, we need to save it */ + prev = nv10_gr_channel(priv); + if (prev) + nv10_gr_unload_context(prev); + + /* load context for next channel */ + chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; + next = priv->chan[chid]; + if (next) + nv10_gr_load_context(next, chid); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +#define NV_WRITE_CTX(reg, val) do { \ + int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \ + if (offset > 0) \ + chan->nv10[offset] = val; \ + } while (0) + +#define NV17_WRITE_CTX(reg, val) do { \ + int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \ + if (offset > 0) \ + chan->nv17[offset] = val; \ + } while (0) + +static int +nv10_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_fifo_chan *fifo = (void *)parent; + struct nv10_gr_priv *priv = (void *)engine; + struct nv10_gr_chan *chan; + unsigned long flags; + int ret; + + ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + spin_lock_irqsave(&priv->lock, flags); + if (priv->chan[fifo->chid]) { + *pobject = nv_object(priv->chan[fifo->chid]); + atomic_inc(&(*pobject)->refcount); + spin_unlock_irqrestore(&priv->lock, flags); + nouveau_object_destroy(&chan->base); + return 1; + } + + NV_WRITE_CTX(0x00400e88, 0x08000000); + NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); + NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); + NV_WRITE_CTX(0x00400e10, 0x00001000); + NV_WRITE_CTX(0x00400e14, 0x00001000); + NV_WRITE_CTX(0x00400e30, 0x00080008); + NV_WRITE_CTX(0x00400e34, 0x00080008); + if (nv_device(priv)->card_type >= NV_11 && + nv_device(priv)->chipset >= 0x17) { + /* is it really needed ??? */ + NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, + nv_rd32(priv, NV10_PGRAPH_DEBUG_4)); + NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0)); + NV17_WRITE_CTX(0x00400eac, 0x0fff0000); + NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); + NV17_WRITE_CTX(0x00400ec0, 0x00000080); + NV17_WRITE_CTX(0x00400ed0, 0x00000080); + } + NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24); + + nv10_gr_create_pipe(chan); + + priv->chan[fifo->chid] = chan; + chan->chid = fifo->chid; + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static void +nv10_gr_context_dtor(struct nouveau_object *object) +{ + struct nv10_gr_priv *priv = (void *)object->engine; + struct nv10_gr_chan *chan = (void *)object; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->chan[chan->chid] = NULL; + spin_unlock_irqrestore(&priv->lock, flags); + + nouveau_object_destroy(&chan->base); +} + +static int +nv10_gr_context_fini(struct nouveau_object *object, bool suspend) +{ + struct nv10_gr_priv *priv = (void *)object->engine; + struct nv10_gr_chan *chan = (void *)object; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + if (nv10_gr_channel(priv) == chan) + nv10_gr_unload_context(chan); + nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&priv->lock, flags); + + return nouveau_object_fini(&chan->base, suspend); +} + +static struct nouveau_oclass +nv10_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x10), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv10_gr_context_ctor, + .dtor = nv10_gr_context_dtor, + .init = nouveau_object_init, + .fini = nv10_gr_context_fini, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static void +nv10_gr_tile_prog(struct nouveau_engine *engine, int i) +{ + struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; + struct nouveau_fifo *pfifo = nouveau_fifo(engine); + struct nv10_gr_priv *priv = (void *)engine; + unsigned long flags; + + pfifo->pause(pfifo, &flags); + nv04_gr_idle(priv); + + nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr); + + pfifo->start(pfifo, &flags); +} + +const struct nouveau_bitfield nv10_gr_intr_name[] = { + { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, + { NV_PGRAPH_INTR_ERROR, "ERROR" }, + {} +}; + +const struct nouveau_bitfield nv10_gr_nstatus[] = { + { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, + { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, + { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, + { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }, + {} +}; + +static void +nv10_gr_intr(struct nouveau_subdev *subdev) +{ + struct nv10_gr_priv *priv = (void *)subdev; + struct nv10_gr_chan *chan = NULL; + struct nouveau_namedb *namedb = NULL; + struct nouveau_handle *handle = NULL; + u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); + u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + u32 chid = (addr & 0x01f00000) >> 20; + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00001ffc); + u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; + u32 show = stat; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + chan = priv->chan[chid]; + if (chan) + namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); + spin_unlock_irqrestore(&priv->lock, flags); + + if (stat & NV_PGRAPH_INTR_ERROR) { + if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { + handle = nouveau_namedb_get_class(namedb, class); + if (handle && !nv_call(handle->object, mthd, data)) + show &= ~NV_PGRAPH_INTR_ERROR; + } + } + + if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { + nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); + stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + nv10_gr_context_switch(priv); + } + + nv_wr32(priv, NV03_PGRAPH_INTR, stat); + nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + + if (show) { + nv_error(priv, "%s", ""); + nouveau_bitfield_print(nv10_gr_intr_name, show); + pr_cont(" nsource:"); + nouveau_bitfield_print(nv04_gr_nsource, nsource); + pr_cont(" nstatus:"); + nouveau_bitfield_print(nv10_gr_nstatus, nstatus); + pr_cont("\n"); + nv_error(priv, + "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, nouveau_client_name(chan), subc, class, mthd, + data); + } + + nouveau_namedb_put(handle); +} + +static int +nv10_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv10_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv10_gr_intr; + nv_engine(priv)->cclass = &nv10_gr_cclass; + + if (nv_device(priv)->chipset <= 0x10) + nv_engine(priv)->sclass = nv10_gr_sclass; + else + if (nv_device(priv)->chipset < 0x17 || + nv_device(priv)->card_type < NV_11) + nv_engine(priv)->sclass = nv15_gr_sclass; + else + nv_engine(priv)->sclass = nv17_gr_sclass; + + nv_engine(priv)->tile_prog = nv10_gr_tile_prog; + spin_lock_init(&priv->lock); + return 0; +} + +static void +nv10_gr_dtor(struct nouveau_object *object) +{ + struct nv10_gr_priv *priv = (void *)object; + nouveau_gr_destroy(&priv->base); +} + +static int +nv10_gr_init(struct nouveau_object *object) +{ + struct nouveau_engine *engine = nv_engine(object); + struct nouveau_fb *pfb = nouveau_fb(object); + struct nv10_gr_priv *priv = (void *)engine; + int ret, i; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); + /* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ + nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); + nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); + + if (nv_device(priv)->card_type >= NV_11 && + nv_device(priv)->chipset >= 0x17) { + nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000); + nv_wr32(priv, 0x400a10, 0x03ff3fb6); + nv_wr32(priv, 0x400838, 0x002f8684); + nv_wr32(priv, 0x40083c, 0x00115f3f); + nv_wr32(priv, 0x4006b0, 0x40000020); + } else { + nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); + } + + /* Turn all the tiling regions off. */ + for (i = 0; i < pfb->tile.regions; i++) + engine->tile_prog(engine, i); + + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); + nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); + nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF); + + nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); + nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); + return 0; +} + +static int +nv10_gr_fini(struct nouveau_object *object, bool suspend) +{ + struct nv10_gr_priv *priv = (void *)object; + return nouveau_gr_fini(&priv->base, suspend); +} + +struct nouveau_oclass +nv10_gr_oclass = { + .handle = NV_ENGINE(GR, 0x10), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv10_gr_ctor, + .dtor = nv10_gr_dtor, + .init = nv10_gr_init, + .fini = nv10_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c new file mode 100644 index 000000000000..669ee49ba58b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c @@ -0,0 +1,224 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nv108_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa140, &nouveau_object_ofuncs }, + { KEPLER_B, &nvc0_fermi_ofuncs }, + { 0xa1c0, &nouveau_object_ofuncs }, + {} +}; + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nv108_gr_init_main_0[] = { + { 0x400080, 1, 0x04, 0x003083c2 }, + { 0x400088, 1, 0x04, 0x0001bfe7 }, + { 0x40008c, 1, 0x04, 0x00000000 }, + { 0x400090, 1, 0x04, 0x00000030 }, + { 0x40013c, 1, 0x04, 0x003901f7 }, + { 0x400140, 1, 0x04, 0x00000100 }, + { 0x400144, 1, 0x04, 0x00000000 }, + { 0x400148, 1, 0x04, 0x00000110 }, + { 0x400138, 1, 0x04, 0x00000000 }, + { 0x400130, 2, 0x04, 0x00000000 }, + { 0x400124, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_init +nv108_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x00000000 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nv108_gr_init_gpc_unk_0[] = { + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nv108_gr_init_setup_1[] = { + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000201 }, + {} +}; + +static const struct nvc0_gr_init +nv108_gr_init_tex_0[] = { + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + { 0x419aa8, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nv108_gr_init_l1c_0[] = { + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x01000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00b08bea }, + { 0x419c84, 1, 0x04, 0x00010384 }, + { 0x419cbc, 1, 0x04, 0x281b3646 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x00000230 }, + { 0x419ccc, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nv108_gr_pack_mmio[] = { + { nv108_gr_init_main_0 }, + { nvf0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvd9_gr_init_pd_0 }, + { nv108_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvf0_gr_init_sked_0 }, + { nvf0_gr_init_cwd_0 }, + { nvd9_gr_init_prop_0 }, + { nv108_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nv108_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvd9_gr_init_gpm_0 }, + { nvf0_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nve4_gr_init_tpccs_0 }, + { nv108_gr_init_tex_0 }, + { nve4_gr_init_pe_0 }, + { nv108_gr_init_l1c_0 }, + { nvc0_gr_init_mpc_0 }, + { nvf0_gr_init_sm_0 }, + { nvd7_gr_init_pes_0 }, + { nvd7_gr_init_wwdx_0 }, + { nvd7_gr_init_cbm_0 }, + { nve4_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static int +nv108_gr_fini(struct nouveau_object *object, bool suspend) +{ + struct nvc0_gr_priv *priv = (void *)object; + static const struct { + u32 addr; + u32 data; + } magic[] = { + { 0x020520, 0xfffffffc }, + { 0x020524, 0xfffffffe }, + { 0x020524, 0xfffffffc }, + { 0x020524, 0xfffffff8 }, + { 0x020524, 0xffffffe0 }, + { 0x020530, 0xfffffffe }, + { 0x02052c, 0xfffffffa }, + { 0x02052c, 0xfffffff0 }, + { 0x02052c, 0xffffffc0 }, + { 0x02052c, 0xffffff00 }, + { 0x02052c, 0xfffffc00 }, + { 0x02052c, 0xfffcfc00 }, + { 0x02052c, 0xfff0fc00 }, + { 0x02052c, 0xff80fc00 }, + { 0x020528, 0xfffffffe }, + { 0x020528, 0xfffffffc }, + }; + int i; + + nv_mask(priv, 0x000200, 0x08001000, 0x00000000); + nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); + for (i = 0; i < ARRAY_SIZE(magic); i++) { + nv_wr32(priv, magic[i].addr, magic[i].data); + nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); + } + + return nouveau_gr_fini(&priv->base, suspend); +} + +#include "fuc/hubnv108.fuc5.h" + +static struct nvc0_gr_ucode +nv108_gr_fecs_ucode = { + .code.data = nv108_grhub_code, + .code.size = sizeof(nv108_grhub_code), + .data.data = nv108_grhub_data, + .data.size = sizeof(nv108_grhub_data), +}; + +#include "fuc/gpcnv108.fuc5.h" + +static struct nvc0_gr_ucode +nv108_gr_gpccs_ucode = { + .code.data = nv108_grgpc_code, + .code.size = sizeof(nv108_grgpc_code), + .data.data = nv108_grgpc_data, + .data.size = sizeof(nv108_grgpc_data), +}; + +struct nouveau_oclass * +nv108_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0x08), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nve4_gr_init, + .fini = nv108_gr_fini, + }, + .cclass = &nv108_grctx_oclass, + .sclass = nv108_gr_sclass, + .mmio = nv108_gr_pack_mmio, + .fecs.ucode = &nv108_gr_fecs_ucode, + .gpccs.ucode = &nv108_gr_gpccs_ucode, + .ppc_nr = 1, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c new file mode 100644 index 000000000000..8caf0c338425 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -0,0 +1,383 @@ +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "nv20.h" +#include "regs.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nv20_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ + { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */ + { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv20_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_chan *chan; + int ret, i; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, + 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC, + &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->chid = nouveau_fifo_chan(parent)->chid; + + nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); + nv_wo32(chan, 0x033c, 0xffff0000); + nv_wo32(chan, 0x03a0, 0x0fff0000); + nv_wo32(chan, 0x03a4, 0x0fff0000); + nv_wo32(chan, 0x047c, 0x00000101); + nv_wo32(chan, 0x0490, 0x00000111); + nv_wo32(chan, 0x04a8, 0x44400000); + for (i = 0x04d4; i <= 0x04e0; i += 4) + nv_wo32(chan, i, 0x00030303); + for (i = 0x04f4; i <= 0x0500; i += 4) + nv_wo32(chan, i, 0x00080000); + for (i = 0x050c; i <= 0x0518; i += 4) + nv_wo32(chan, i, 0x01012000); + for (i = 0x051c; i <= 0x0528; i += 4) + nv_wo32(chan, i, 0x000105b8); + for (i = 0x052c; i <= 0x0538; i += 4) + nv_wo32(chan, i, 0x00080008); + for (i = 0x055c; i <= 0x0598; i += 4) + nv_wo32(chan, i, 0x07ff0000); + nv_wo32(chan, 0x05a4, 0x4b7fffff); + nv_wo32(chan, 0x05fc, 0x00000001); + nv_wo32(chan, 0x0604, 0x00004000); + nv_wo32(chan, 0x0610, 0x00000001); + nv_wo32(chan, 0x0618, 0x00040000); + nv_wo32(chan, 0x061c, 0x00010000); + for (i = 0x1c1c; i <= 0x248c; i += 16) { + nv_wo32(chan, (i + 0), 0x10700ff9); + nv_wo32(chan, (i + 4), 0x0436086c); + nv_wo32(chan, (i + 8), 0x000c001b); + } + nv_wo32(chan, 0x281c, 0x3f800000); + nv_wo32(chan, 0x2830, 0x3f800000); + nv_wo32(chan, 0x285c, 0x40000000); + nv_wo32(chan, 0x2860, 0x3f800000); + nv_wo32(chan, 0x2864, 0x3f000000); + nv_wo32(chan, 0x286c, 0x40000000); + nv_wo32(chan, 0x2870, 0x3f800000); + nv_wo32(chan, 0x2878, 0xbf800000); + nv_wo32(chan, 0x2880, 0xbf800000); + nv_wo32(chan, 0x34a4, 0x000fe000); + nv_wo32(chan, 0x3530, 0x000003f8); + nv_wo32(chan, 0x3540, 0x002fe000); + for (i = 0x355c; i <= 0x3578; i += 4) + nv_wo32(chan, i, 0x001c527c); + return 0; +} + +int +nv20_gr_context_init(struct nouveau_object *object) +{ + struct nv20_gr_priv *priv = (void *)object->engine; + struct nv20_gr_chan *chan = (void *)object; + int ret; + + ret = nouveau_gr_context_init(&chan->base); + if (ret) + return ret; + + nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); + return 0; +} + +int +nv20_gr_context_fini(struct nouveau_object *object, bool suspend) +{ + struct nv20_gr_priv *priv = (void *)object->engine; + struct nv20_gr_chan *chan = (void *)object; + int chid = -1; + + nv_mask(priv, 0x400720, 0x00000001, 0x00000000); + if (nv_rd32(priv, 0x400144) & 0x00010000) + chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; + if (chan->chid == chid) { + nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); + nv_wr32(priv, 0x400788, 0x00000002); + nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); + nv_wr32(priv, 0x400144, 0x10000000); + nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); + } + nv_mask(priv, 0x400720, 0x00000001, 0x00000001); + + nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); + return nouveau_gr_context_fini(&chan->base, suspend); +} + +static struct nouveau_oclass +nv20_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x20), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv20_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +void +nv20_gr_tile_prog(struct nouveau_engine *engine, int i) +{ + struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; + struct nouveau_fifo *pfifo = nouveau_fifo(engine); + struct nv20_gr_priv *priv = (void *)engine; + unsigned long flags; + + pfifo->pause(pfifo, &flags); + nv04_gr_idle(priv); + + nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); + + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); + + if (nv_device(engine)->chipset != 0x34) { + nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); + } + + pfifo->start(pfifo, &flags); +} + +void +nv20_gr_intr(struct nouveau_subdev *subdev) +{ + struct nouveau_engine *engine = nv_engine(subdev); + struct nouveau_object *engctx; + struct nouveau_handle *handle; + struct nv20_gr_priv *priv = (void *)subdev; + u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); + u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + u32 chid = (addr & 0x01f00000) >> 20; + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00001ffc); + u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; + u32 show = stat; + + engctx = nouveau_engctx_get(engine, chid); + if (stat & NV_PGRAPH_INTR_ERROR) { + if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { + handle = nouveau_handle_get_class(engctx, class); + if (handle && !nv_call(handle->object, mthd, data)) + show &= ~NV_PGRAPH_INTR_ERROR; + nouveau_handle_put(handle); + } + } + + nv_wr32(priv, NV03_PGRAPH_INTR, stat); + nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + + if (show) { + nv_error(priv, "%s", ""); + nouveau_bitfield_print(nv10_gr_intr_name, show); + pr_cont(" nsource:"); + nouveau_bitfield_print(nv04_gr_nsource, nsource); + pr_cont(" nstatus:"); + nouveau_bitfield_print(nv10_gr_nstatus, nstatus); + pr_cont("\n"); + nv_error(priv, + "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, nouveau_client_name(engctx), subc, class, mthd, + data); + } + + nouveau_engctx_put(engctx); +} + +static int +nv20_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv20_gr_cclass; + nv_engine(priv)->sclass = nv20_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + return 0; +} + +void +nv20_gr_dtor(struct nouveau_object *object) +{ + struct nv20_gr_priv *priv = (void *)object; + nouveau_gpuobj_ref(NULL, &priv->ctxtab); + nouveau_gr_destroy(&priv->base); +} + +int +nv20_gr_init(struct nouveau_object *object) +{ + struct nouveau_engine *engine = nv_engine(object); + struct nv20_gr_priv *priv = (void *)engine; + struct nouveau_fb *pfb = nouveau_fb(object); + u32 tmp, vramsz; + int ret, i; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); + + if (nv_device(priv)->chipset == 0x20) { + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000); + for (i = 0; i < 15; i++) + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); + nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); + } else { + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000); + for (i = 0; i < 32; i++) + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); + nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); + } + + nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); + nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ + nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); + nv_wr32(priv, 0x40009C , 0x00000040); + + if (nv_device(priv)->chipset >= 0x25) { + nv_wr32(priv, 0x400890, 0x00a8cfff); + nv_wr32(priv, 0x400610, 0x304B1FB6); + nv_wr32(priv, 0x400B80, 0x1cbd3883); + nv_wr32(priv, 0x400B84, 0x44000000); + nv_wr32(priv, 0x400098, 0x40000080); + nv_wr32(priv, 0x400B88, 0x000000ff); + + } else { + nv_wr32(priv, 0x400880, 0x0008c7df); + nv_wr32(priv, 0x400094, 0x00000005); + nv_wr32(priv, 0x400B80, 0x45eae20e); + nv_wr32(priv, 0x400B84, 0x24000000); + nv_wr32(priv, 0x400098, 0x00000040); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); + } + + /* Turn all the tiling regions off. */ + for (i = 0; i < pfb->tile.regions; i++) + engine->tile_prog(engine, i); + + nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); + + nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); + + tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00; + nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); + tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100; + nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); + + /* begin RAM config */ + vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; + nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200)); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204)); + nv_wr32(priv, 0x400820, 0); + nv_wr32(priv, 0x400824, 0); + nv_wr32(priv, 0x400864, vramsz - 1); + nv_wr32(priv, 0x400868, vramsz - 1); + + /* interesting.. the below overwrites some of the tile setup above.. */ + nv_wr32(priv, 0x400B20, 0x00000000); + nv_wr32(priv, 0x400B04, 0xFFFFFFFF); + + nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); + nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); + nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); + nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); + return 0; +} + +struct nouveau_oclass +nv20_gr_oclass = { + .handle = NV_ENGINE(GR, 0x20), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv20_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv20_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h new file mode 100644 index 000000000000..9019eea4a613 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -0,0 +1,31 @@ +#ifndef __NV20_GR_H__ +#define __NV20_GR_H__ + +#include + +#include +#include + +struct nv20_gr_priv { + struct nouveau_gr base; + struct nouveau_gpuobj *ctxtab; +}; + +struct nv20_gr_chan { + struct nouveau_gr_chan base; + int chid; +}; + +extern struct nouveau_oclass nv25_gr_sclass[]; +int nv20_gr_context_init(struct nouveau_object *); +int nv20_gr_context_fini(struct nouveau_object *, bool); + +void nv20_gr_tile_prog(struct nouveau_engine *, int); +void nv20_gr_intr(struct nouveau_subdev *); + +void nv20_gr_dtor(struct nouveau_object *); +int nv20_gr_init(struct nouveau_object *); + +int nv30_gr_init(struct nouveau_object *); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c new file mode 100644 index 000000000000..903a2ec361ce --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -0,0 +1,166 @@ +#include +#include +#include + +#include +#include + +#include + +#include "nv20.h" +#include "regs.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +struct nouveau_oclass +nv25_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ + { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */ + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv25_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_chan *chan; + int ret, i; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->chid = nouveau_fifo_chan(parent)->chid; + + nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); + nv_wo32(chan, 0x035c, 0xffff0000); + nv_wo32(chan, 0x03c0, 0x0fff0000); + nv_wo32(chan, 0x03c4, 0x0fff0000); + nv_wo32(chan, 0x049c, 0x00000101); + nv_wo32(chan, 0x04b0, 0x00000111); + nv_wo32(chan, 0x04c8, 0x00000080); + nv_wo32(chan, 0x04cc, 0xffff0000); + nv_wo32(chan, 0x04d0, 0x00000001); + nv_wo32(chan, 0x04e4, 0x44400000); + nv_wo32(chan, 0x04fc, 0x4b800000); + for (i = 0x0510; i <= 0x051c; i += 4) + nv_wo32(chan, i, 0x00030303); + for (i = 0x0530; i <= 0x053c; i += 4) + nv_wo32(chan, i, 0x00080000); + for (i = 0x0548; i <= 0x0554; i += 4) + nv_wo32(chan, i, 0x01012000); + for (i = 0x0558; i <= 0x0564; i += 4) + nv_wo32(chan, i, 0x000105b8); + for (i = 0x0568; i <= 0x0574; i += 4) + nv_wo32(chan, i, 0x00080008); + for (i = 0x0598; i <= 0x05d4; i += 4) + nv_wo32(chan, i, 0x07ff0000); + nv_wo32(chan, 0x05e0, 0x4b7fffff); + nv_wo32(chan, 0x0620, 0x00000080); + nv_wo32(chan, 0x0624, 0x30201000); + nv_wo32(chan, 0x0628, 0x70605040); + nv_wo32(chan, 0x062c, 0xb0a09080); + nv_wo32(chan, 0x0630, 0xf0e0d0c0); + nv_wo32(chan, 0x0664, 0x00000001); + nv_wo32(chan, 0x066c, 0x00004000); + nv_wo32(chan, 0x0678, 0x00000001); + nv_wo32(chan, 0x0680, 0x00040000); + nv_wo32(chan, 0x0684, 0x00010000); + for (i = 0x1b04; i <= 0x2374; i += 16) { + nv_wo32(chan, (i + 0), 0x10700ff9); + nv_wo32(chan, (i + 4), 0x0436086c); + nv_wo32(chan, (i + 8), 0x000c001b); + } + nv_wo32(chan, 0x2704, 0x3f800000); + nv_wo32(chan, 0x2718, 0x3f800000); + nv_wo32(chan, 0x2744, 0x40000000); + nv_wo32(chan, 0x2748, 0x3f800000); + nv_wo32(chan, 0x274c, 0x3f000000); + nv_wo32(chan, 0x2754, 0x40000000); + nv_wo32(chan, 0x2758, 0x3f800000); + nv_wo32(chan, 0x2760, 0xbf800000); + nv_wo32(chan, 0x2768, 0xbf800000); + nv_wo32(chan, 0x308c, 0x000fe000); + nv_wo32(chan, 0x3108, 0x000003f8); + nv_wo32(chan, 0x3468, 0x002fe000); + for (i = 0x3484; i <= 0x34a0; i += 4) + nv_wo32(chan, i, 0x001c527c); + return 0; +} + +static struct nouveau_oclass +nv25_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x25), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv25_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static int +nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv25_gr_cclass; + nv_engine(priv)->sclass = nv25_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + return 0; +} + +struct nouveau_oclass +nv25_gr_oclass = { + .handle = NV_ENGINE(GR, 0x25), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv25_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv20_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c new file mode 100644 index 000000000000..e31f6c766729 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -0,0 +1,133 @@ +#include +#include +#include + +#include +#include + +#include + +#include "nv20.h" +#include "regs.h" + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv2a_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_chan *chan; + int ret, i; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x36b0, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->chid = nouveau_fifo_chan(parent)->chid; + + nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); + nv_wo32(chan, 0x033c, 0xffff0000); + nv_wo32(chan, 0x03a0, 0x0fff0000); + nv_wo32(chan, 0x03a4, 0x0fff0000); + nv_wo32(chan, 0x047c, 0x00000101); + nv_wo32(chan, 0x0490, 0x00000111); + nv_wo32(chan, 0x04a8, 0x44400000); + for (i = 0x04d4; i <= 0x04e0; i += 4) + nv_wo32(chan, i, 0x00030303); + for (i = 0x04f4; i <= 0x0500; i += 4) + nv_wo32(chan, i, 0x00080000); + for (i = 0x050c; i <= 0x0518; i += 4) + nv_wo32(chan, i, 0x01012000); + for (i = 0x051c; i <= 0x0528; i += 4) + nv_wo32(chan, i, 0x000105b8); + for (i = 0x052c; i <= 0x0538; i += 4) + nv_wo32(chan, i, 0x00080008); + for (i = 0x055c; i <= 0x0598; i += 4) + nv_wo32(chan, i, 0x07ff0000); + nv_wo32(chan, 0x05a4, 0x4b7fffff); + nv_wo32(chan, 0x05fc, 0x00000001); + nv_wo32(chan, 0x0604, 0x00004000); + nv_wo32(chan, 0x0610, 0x00000001); + nv_wo32(chan, 0x0618, 0x00040000); + nv_wo32(chan, 0x061c, 0x00010000); + for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ + nv_wo32(chan, (i + 0), 0x10700ff9); + nv_wo32(chan, (i + 4), 0x0436086c); + nv_wo32(chan, (i + 8), 0x000c001b); + } + nv_wo32(chan, 0x269c, 0x3f800000); + nv_wo32(chan, 0x26b0, 0x3f800000); + nv_wo32(chan, 0x26dc, 0x40000000); + nv_wo32(chan, 0x26e0, 0x3f800000); + nv_wo32(chan, 0x26e4, 0x3f000000); + nv_wo32(chan, 0x26ec, 0x40000000); + nv_wo32(chan, 0x26f0, 0x3f800000); + nv_wo32(chan, 0x26f8, 0xbf800000); + nv_wo32(chan, 0x2700, 0xbf800000); + nv_wo32(chan, 0x3024, 0x000fe000); + nv_wo32(chan, 0x30a0, 0x000003f8); + nv_wo32(chan, 0x33fc, 0x002fe000); + for (i = 0x341c; i <= 0x3438; i += 4) + nv_wo32(chan, i, 0x001c527c); + return 0; +} + +static struct nouveau_oclass +nv2a_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x2a), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv2a_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static int +nv2a_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv2a_gr_cclass; + nv_engine(priv)->sclass = nv25_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + return 0; +} + +struct nouveau_oclass +nv2a_gr_oclass = { + .handle = NV_ENGINE(GR, 0x2a), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv2a_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv20_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c new file mode 100644 index 000000000000..d9d85508cbcf --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -0,0 +1,237 @@ +#include +#include +#include + +#include +#include + +#include + +#include "nv20.h" +#include "regs.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nv30_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ + { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ + { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ + { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ + { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */ + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv30_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_chan *chan; + int ret, i; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x5f48, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->chid = nouveau_fifo_chan(parent)->chid; + + nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); + nv_wo32(chan, 0x0410, 0x00000101); + nv_wo32(chan, 0x0424, 0x00000111); + nv_wo32(chan, 0x0428, 0x00000060); + nv_wo32(chan, 0x0444, 0x00000080); + nv_wo32(chan, 0x0448, 0xffff0000); + nv_wo32(chan, 0x044c, 0x00000001); + nv_wo32(chan, 0x0460, 0x44400000); + nv_wo32(chan, 0x048c, 0xffff0000); + for (i = 0x04e0; i < 0x04e8; i += 4) + nv_wo32(chan, i, 0x0fff0000); + nv_wo32(chan, 0x04ec, 0x00011100); + for (i = 0x0508; i < 0x0548; i += 4) + nv_wo32(chan, i, 0x07ff0000); + nv_wo32(chan, 0x0550, 0x4b7fffff); + nv_wo32(chan, 0x058c, 0x00000080); + nv_wo32(chan, 0x0590, 0x30201000); + nv_wo32(chan, 0x0594, 0x70605040); + nv_wo32(chan, 0x0598, 0xb8a89888); + nv_wo32(chan, 0x059c, 0xf8e8d8c8); + nv_wo32(chan, 0x05b0, 0xb0000000); + for (i = 0x0600; i < 0x0640; i += 4) + nv_wo32(chan, i, 0x00010588); + for (i = 0x0640; i < 0x0680; i += 4) + nv_wo32(chan, i, 0x00030303); + for (i = 0x06c0; i < 0x0700; i += 4) + nv_wo32(chan, i, 0x0008aae4); + for (i = 0x0700; i < 0x0740; i += 4) + nv_wo32(chan, i, 0x01012000); + for (i = 0x0740; i < 0x0780; i += 4) + nv_wo32(chan, i, 0x00080008); + nv_wo32(chan, 0x085c, 0x00040000); + nv_wo32(chan, 0x0860, 0x00010000); + for (i = 0x0864; i < 0x0874; i += 4) + nv_wo32(chan, i, 0x00040004); + for (i = 0x1f18; i <= 0x3088 ; i += 16) { + nv_wo32(chan, i + 0, 0x10700ff9); + nv_wo32(chan, i + 1, 0x0436086c); + nv_wo32(chan, i + 2, 0x000c001b); + } + for (i = 0x30b8; i < 0x30c8; i += 4) + nv_wo32(chan, i, 0x0000ffff); + nv_wo32(chan, 0x344c, 0x3f800000); + nv_wo32(chan, 0x3808, 0x3f800000); + nv_wo32(chan, 0x381c, 0x3f800000); + nv_wo32(chan, 0x3848, 0x40000000); + nv_wo32(chan, 0x384c, 0x3f800000); + nv_wo32(chan, 0x3850, 0x3f000000); + nv_wo32(chan, 0x3858, 0x40000000); + nv_wo32(chan, 0x385c, 0x3f800000); + nv_wo32(chan, 0x3864, 0xbf800000); + nv_wo32(chan, 0x386c, 0xbf800000); + return 0; +} + +static struct nouveau_oclass +nv30_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x30), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv30_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static int +nv30_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv30_gr_cclass; + nv_engine(priv)->sclass = nv30_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + return 0; +} + +int +nv30_gr_init(struct nouveau_object *object) +{ + struct nouveau_engine *engine = nv_engine(object); + struct nv20_gr_priv *priv = (void *)engine; + struct nouveau_fb *pfb = nouveau_fb(object); + int ret, i; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); + + nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); + nv_wr32(priv, 0x400890, 0x01b463ff); + nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475); + nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); + nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); + nv_wr32(priv, 0x400B80, 0x1003d888); + nv_wr32(priv, 0x400B84, 0x0c000000); + nv_wr32(priv, 0x400098, 0x00000000); + nv_wr32(priv, 0x40009C, 0x0005ad00); + nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ + nv_wr32(priv, 0x4000a0, 0x00000000); + nv_wr32(priv, 0x4000a4, 0x00000008); + nv_wr32(priv, 0x4008a8, 0xb784a400); + nv_wr32(priv, 0x400ba0, 0x002f8685); + nv_wr32(priv, 0x400ba4, 0x00231f3f); + nv_wr32(priv, 0x4008a4, 0x40000020); + + if (nv_device(priv)->chipset == 0x34) { + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032); + nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004); + nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002); + } + + nv_wr32(priv, 0x4000c0, 0x00000016); + + /* Turn all the tiling regions off. */ + for (i = 0; i < pfb->tile.regions; i++) + engine->tile_prog(engine, i); + + nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nv_wr32(priv, 0x0040075c , 0x00000001); + + /* begin RAM config */ + /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */ + nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); + if (nv_device(priv)->chipset != 0x34) { + nv_wr32(priv, 0x400750, 0x00EA0000); + nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x400750, 0x00EA0004); + nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); + } + return 0; +} + +struct nouveau_oclass +nv30_gr_oclass = { + .handle = NV_ENGINE(GR, 0x30), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv30_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv30_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c new file mode 100644 index 000000000000..5c2787056292 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -0,0 +1,167 @@ +#include +#include +#include + +#include +#include + +#include + +#include "nv20.h" +#include "regs.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nv34_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ + { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ + { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ + { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ + { 0x0697, &nv04_gr_ofuncs, NULL }, /* rankine */ + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv34_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_chan *chan; + int ret, i; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x46dc, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->chid = nouveau_fifo_chan(parent)->chid; + + nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); + nv_wo32(chan, 0x040c, 0x01000101); + nv_wo32(chan, 0x0420, 0x00000111); + nv_wo32(chan, 0x0424, 0x00000060); + nv_wo32(chan, 0x0440, 0x00000080); + nv_wo32(chan, 0x0444, 0xffff0000); + nv_wo32(chan, 0x0448, 0x00000001); + nv_wo32(chan, 0x045c, 0x44400000); + nv_wo32(chan, 0x0480, 0xffff0000); + for (i = 0x04d4; i < 0x04dc; i += 4) + nv_wo32(chan, i, 0x0fff0000); + nv_wo32(chan, 0x04e0, 0x00011100); + for (i = 0x04fc; i < 0x053c; i += 4) + nv_wo32(chan, i, 0x07ff0000); + nv_wo32(chan, 0x0544, 0x4b7fffff); + nv_wo32(chan, 0x057c, 0x00000080); + nv_wo32(chan, 0x0580, 0x30201000); + nv_wo32(chan, 0x0584, 0x70605040); + nv_wo32(chan, 0x0588, 0xb8a89888); + nv_wo32(chan, 0x058c, 0xf8e8d8c8); + nv_wo32(chan, 0x05a0, 0xb0000000); + for (i = 0x05f0; i < 0x0630; i += 4) + nv_wo32(chan, i, 0x00010588); + for (i = 0x0630; i < 0x0670; i += 4) + nv_wo32(chan, i, 0x00030303); + for (i = 0x06b0; i < 0x06f0; i += 4) + nv_wo32(chan, i, 0x0008aae4); + for (i = 0x06f0; i < 0x0730; i += 4) + nv_wo32(chan, i, 0x01012000); + for (i = 0x0730; i < 0x0770; i += 4) + nv_wo32(chan, i, 0x00080008); + nv_wo32(chan, 0x0850, 0x00040000); + nv_wo32(chan, 0x0854, 0x00010000); + for (i = 0x0858; i < 0x0868; i += 4) + nv_wo32(chan, i, 0x00040004); + for (i = 0x15ac; i <= 0x271c ; i += 16) { + nv_wo32(chan, i + 0, 0x10700ff9); + nv_wo32(chan, i + 1, 0x0436086c); + nv_wo32(chan, i + 2, 0x000c001b); + } + for (i = 0x274c; i < 0x275c; i += 4) + nv_wo32(chan, i, 0x0000ffff); + nv_wo32(chan, 0x2ae0, 0x3f800000); + nv_wo32(chan, 0x2e9c, 0x3f800000); + nv_wo32(chan, 0x2eb0, 0x3f800000); + nv_wo32(chan, 0x2edc, 0x40000000); + nv_wo32(chan, 0x2ee0, 0x3f800000); + nv_wo32(chan, 0x2ee4, 0x3f000000); + nv_wo32(chan, 0x2eec, 0x40000000); + nv_wo32(chan, 0x2ef0, 0x3f800000); + nv_wo32(chan, 0x2ef8, 0xbf800000); + nv_wo32(chan, 0x2f00, 0xbf800000); + return 0; +} + +static struct nouveau_oclass +nv34_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x34), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv34_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static int +nv34_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv34_gr_cclass; + nv_engine(priv)->sclass = nv34_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + return 0; +} + +struct nouveau_oclass +nv34_gr_oclass = { + .handle = NV_ENGINE(GR, 0x34), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv34_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv30_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c new file mode 100644 index 000000000000..af3f914813e2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -0,0 +1,165 @@ +#include +#include +#include + +#include +#include + +#include "nv20.h" +#include "regs.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nv35_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ + { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ + { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ + { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ + { 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */ + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv35_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_chan *chan; + int ret, i; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x577c, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->chid = nouveau_fifo_chan(parent)->chid; + + nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); + nv_wo32(chan, 0x040c, 0x00000101); + nv_wo32(chan, 0x0420, 0x00000111); + nv_wo32(chan, 0x0424, 0x00000060); + nv_wo32(chan, 0x0440, 0x00000080); + nv_wo32(chan, 0x0444, 0xffff0000); + nv_wo32(chan, 0x0448, 0x00000001); + nv_wo32(chan, 0x045c, 0x44400000); + nv_wo32(chan, 0x0488, 0xffff0000); + for (i = 0x04dc; i < 0x04e4; i += 4) + nv_wo32(chan, i, 0x0fff0000); + nv_wo32(chan, 0x04e8, 0x00011100); + for (i = 0x0504; i < 0x0544; i += 4) + nv_wo32(chan, i, 0x07ff0000); + nv_wo32(chan, 0x054c, 0x4b7fffff); + nv_wo32(chan, 0x0588, 0x00000080); + nv_wo32(chan, 0x058c, 0x30201000); + nv_wo32(chan, 0x0590, 0x70605040); + nv_wo32(chan, 0x0594, 0xb8a89888); + nv_wo32(chan, 0x0598, 0xf8e8d8c8); + nv_wo32(chan, 0x05ac, 0xb0000000); + for (i = 0x0604; i < 0x0644; i += 4) + nv_wo32(chan, i, 0x00010588); + for (i = 0x0644; i < 0x0684; i += 4) + nv_wo32(chan, i, 0x00030303); + for (i = 0x06c4; i < 0x0704; i += 4) + nv_wo32(chan, i, 0x0008aae4); + for (i = 0x0704; i < 0x0744; i += 4) + nv_wo32(chan, i, 0x01012000); + for (i = 0x0744; i < 0x0784; i += 4) + nv_wo32(chan, i, 0x00080008); + nv_wo32(chan, 0x0860, 0x00040000); + nv_wo32(chan, 0x0864, 0x00010000); + for (i = 0x0868; i < 0x0878; i += 4) + nv_wo32(chan, i, 0x00040004); + for (i = 0x1f1c; i <= 0x308c ; i += 16) { + nv_wo32(chan, i + 0, 0x10700ff9); + nv_wo32(chan, i + 4, 0x0436086c); + nv_wo32(chan, i + 8, 0x000c001b); + } + for (i = 0x30bc; i < 0x30cc; i += 4) + nv_wo32(chan, i, 0x0000ffff); + nv_wo32(chan, 0x3450, 0x3f800000); + nv_wo32(chan, 0x380c, 0x3f800000); + nv_wo32(chan, 0x3820, 0x3f800000); + nv_wo32(chan, 0x384c, 0x40000000); + nv_wo32(chan, 0x3850, 0x3f800000); + nv_wo32(chan, 0x3854, 0x3f000000); + nv_wo32(chan, 0x385c, 0x40000000); + nv_wo32(chan, 0x3860, 0x3f800000); + nv_wo32(chan, 0x3868, 0xbf800000); + nv_wo32(chan, 0x3870, 0xbf800000); + return 0; +} + +static struct nouveau_oclass +nv35_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x35), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv35_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static int +nv35_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv20_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv35_gr_cclass; + nv_engine(priv)->sclass = nv35_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + return 0; +} + +struct nouveau_oclass +nv35_gr_oclass = { + .handle = NV_ENGINE(GR, 0x35), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv35_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv30_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c new file mode 100644 index 000000000000..6fadd830bc25 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -0,0 +1,536 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "nv40.h" +#include "regs.h" + +struct nv40_gr_priv { + struct nouveau_gr base; + u32 size; +}; + +struct nv40_gr_chan { + struct nouveau_gr_chan base; +}; + +static u64 +nv40_gr_units(struct nouveau_gr *gr) +{ + struct nv40_gr_priv *priv = (void *)gr; + + return nv_rd32(priv, 0x1540); +} + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static int +nv40_gr_object_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_gpuobj *obj; + int ret; + + ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, + 20, 16, 0, &obj); + *pobject = nv_object(obj); + if (ret) + return ret; + + nv_wo32(obj, 0x00, nv_mclass(obj)); + nv_wo32(obj, 0x04, 0x00000000); + nv_wo32(obj, 0x08, 0x00000000); +#ifdef __BIG_ENDIAN + nv_mo32(obj, 0x08, 0x01000000, 0x01000000); +#endif + nv_wo32(obj, 0x0c, 0x00000000); + nv_wo32(obj, 0x10, 0x00000000); + return 0; +} + +static struct nouveau_ofuncs +nv40_gr_ofuncs = { + .ctor = nv40_gr_object_ctor, + .dtor = _nouveau_gpuobj_dtor, + .init = _nouveau_gpuobj_init, + .fini = _nouveau_gpuobj_fini, + .rd32 = _nouveau_gpuobj_rd32, + .wr32 = _nouveau_gpuobj_wr32, +}; + +static struct nouveau_oclass +nv40_gr_sclass[] = { + { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */ + { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */ + { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */ + { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */ + { 0x4097, &nv40_gr_ofuncs, NULL }, /* curie */ + {}, +}; + +static struct nouveau_oclass +nv44_gr_sclass[] = { + { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */ + { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */ + { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */ + { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */ + { 0x4497, &nv40_gr_ofuncs, NULL }, /* curie */ + {}, +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv40_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv40_gr_priv *priv = (void *)engine; + struct nv40_gr_chan *chan; + int ret; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, + priv->size, 16, + NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan)); + nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4); + return 0; +} + +static int +nv40_gr_context_fini(struct nouveau_object *object, bool suspend) +{ + struct nv40_gr_priv *priv = (void *)object->engine; + struct nv40_gr_chan *chan = (void *)object; + u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; + int ret = 0; + + nv_mask(priv, 0x400720, 0x00000001, 0x00000000); + + if (nv_rd32(priv, 0x40032c) == inst) { + if (suspend) { + nv_wr32(priv, 0x400720, 0x00000000); + nv_wr32(priv, 0x400784, inst); + nv_mask(priv, 0x400310, 0x00000020, 0x00000020); + nv_mask(priv, 0x400304, 0x00000001, 0x00000001); + if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) { + u32 insn = nv_rd32(priv, 0x400308); + nv_warn(priv, "ctxprog timeout 0x%08x\n", insn); + ret = -EBUSY; + } + } + + nv_mask(priv, 0x40032c, 0x01000000, 0x00000000); + } + + if (nv_rd32(priv, 0x400330) == inst) + nv_mask(priv, 0x400330, 0x01000000, 0x00000000); + + nv_mask(priv, 0x400720, 0x00000001, 0x00000001); + return ret; +} + +static struct nouveau_oclass +nv40_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x40), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv40_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = nv40_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static void +nv40_gr_tile_prog(struct nouveau_engine *engine, int i) +{ + struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; + struct nouveau_fifo *pfifo = nouveau_fifo(engine); + struct nv40_gr_priv *priv = (void *)engine; + unsigned long flags; + + pfifo->pause(pfifo, &flags); + nv04_gr_idle(priv); + + switch (nv_device(priv)->chipset) { + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x45: + case 0x4e: + nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); + nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); + switch (nv_device(priv)->chipset) { + case 0x40: + case 0x45: + nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); + nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); + break; + case 0x41: + case 0x42: + case 0x43: + nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); + nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); + break; + default: + break; + } + break; + case 0x44: + case 0x4a: + nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); + break; + case 0x46: + case 0x4c: + case 0x47: + case 0x49: + case 0x4b: + case 0x63: + case 0x67: + case 0x68: + nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr); + nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); + switch (nv_device(priv)->chipset) { + case 0x47: + case 0x49: + case 0x4b: + nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); + nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); + break; + default: + break; + } + break; + default: + break; + } + + pfifo->start(pfifo, &flags); +} + +static void +nv40_gr_intr(struct nouveau_subdev *subdev) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(subdev); + struct nouveau_engine *engine = nv_engine(subdev); + struct nouveau_object *engctx; + struct nouveau_handle *handle = NULL; + struct nv40_gr_priv *priv = (void *)subdev; + u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); + u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff; + u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00001ffc); + u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff; + u32 show = stat; + int chid; + + engctx = nouveau_engctx_get(engine, inst); + chid = pfifo->chid(pfifo, engctx); + + if (stat & NV_PGRAPH_INTR_ERROR) { + if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { + handle = nouveau_handle_get_class(engctx, class); + if (handle && !nv_call(handle->object, mthd, data)) + show &= ~NV_PGRAPH_INTR_ERROR; + nouveau_handle_put(handle); + } + + if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { + nv_mask(priv, 0x402000, 0, 0); + } + } + + nv_wr32(priv, NV03_PGRAPH_INTR, stat); + nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + + if (show) { + nv_error(priv, "%s", ""); + nouveau_bitfield_print(nv10_gr_intr_name, show); + pr_cont(" nsource:"); + nouveau_bitfield_print(nv04_gr_nsource, nsource); + pr_cont(" nstatus:"); + nouveau_bitfield_print(nv10_gr_nstatus, nstatus); + pr_cont("\n"); + nv_error(priv, + "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, inst << 4, nouveau_client_name(engctx), subc, + class, mthd, data); + } + + nouveau_engctx_put(engctx); +} + +static int +nv40_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv40_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00001000; + nv_subdev(priv)->intr = nv40_gr_intr; + nv_engine(priv)->cclass = &nv40_gr_cclass; + if (nv44_gr_class(priv)) + nv_engine(priv)->sclass = nv44_gr_sclass; + else + nv_engine(priv)->sclass = nv40_gr_sclass; + nv_engine(priv)->tile_prog = nv40_gr_tile_prog; + + priv->base.units = nv40_gr_units; + return 0; +} + +static int +nv40_gr_init(struct nouveau_object *object) +{ + struct nouveau_engine *engine = nv_engine(object); + struct nouveau_fb *pfb = nouveau_fb(object); + struct nv40_gr_priv *priv = (void *)engine; + int ret, i, j; + u32 vramsz; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + /* generate and upload context program */ + ret = nv40_grctx_init(nv_device(priv), &priv->size); + if (ret) + return ret; + + /* No context present currently */ + nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); + + nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); + nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055); + nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); + nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); + + nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); + nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); + + j = nv_rd32(priv, 0x1540) & 0xff; + if (j) { + for (i = 0; !(j & 1); j >>= 1, i++) + ; + nv_wr32(priv, 0x405000, i); + } + + if (nv_device(priv)->chipset == 0x40) { + nv_wr32(priv, 0x4009b0, 0x83280fff); + nv_wr32(priv, 0x4009b4, 0x000000a0); + } else { + nv_wr32(priv, 0x400820, 0x83280eff); + nv_wr32(priv, 0x400824, 0x000000a0); + } + + switch (nv_device(priv)->chipset) { + case 0x40: + case 0x45: + nv_wr32(priv, 0x4009b8, 0x0078e366); + nv_wr32(priv, 0x4009bc, 0x0000014c); + break; + case 0x41: + case 0x42: /* pciid also 0x00Cx */ + /* case 0x0120: XXX (pciid) */ + nv_wr32(priv, 0x400828, 0x007596ff); + nv_wr32(priv, 0x40082c, 0x00000108); + break; + case 0x43: + nv_wr32(priv, 0x400828, 0x0072cb77); + nv_wr32(priv, 0x40082c, 0x00000108); + break; + case 0x44: + case 0x46: /* G72 */ + case 0x4a: + case 0x4c: /* G7x-based C51 */ + case 0x4e: + nv_wr32(priv, 0x400860, 0); + nv_wr32(priv, 0x400864, 0); + break; + case 0x47: /* G70 */ + case 0x49: /* G71 */ + case 0x4b: /* G73 */ + nv_wr32(priv, 0x400828, 0x07830610); + nv_wr32(priv, 0x40082c, 0x0000016A); + break; + default: + break; + } + + nv_wr32(priv, 0x400b38, 0x2ffff800); + nv_wr32(priv, 0x400b3c, 0x00006000); + + /* Tiling related stuff. */ + switch (nv_device(priv)->chipset) { + case 0x44: + case 0x4a: + nv_wr32(priv, 0x400bc4, 0x1003d888); + nv_wr32(priv, 0x400bbc, 0xb7a7b500); + break; + case 0x46: + nv_wr32(priv, 0x400bc4, 0x0000e024); + nv_wr32(priv, 0x400bbc, 0xb7a7b520); + break; + case 0x4c: + case 0x4e: + case 0x67: + nv_wr32(priv, 0x400bc4, 0x1003d888); + nv_wr32(priv, 0x400bbc, 0xb7a7b540); + break; + default: + break; + } + + /* Turn all the tiling regions off. */ + for (i = 0; i < pfb->tile.regions; i++) + engine->tile_prog(engine, i); + + /* begin RAM config */ + vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; + switch (nv_device(priv)->chipset) { + case 0x40: + nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); + nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204)); + nv_wr32(priv, 0x400820, 0); + nv_wr32(priv, 0x400824, 0); + nv_wr32(priv, 0x400864, vramsz); + nv_wr32(priv, 0x400868, vramsz); + break; + default: + switch (nv_device(priv)->chipset) { + case 0x41: + case 0x42: + case 0x43: + case 0x45: + case 0x4e: + case 0x44: + case 0x4a: + nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204)); + break; + default: + nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204)); + break; + } + nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200)); + nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204)); + nv_wr32(priv, 0x400840, 0); + nv_wr32(priv, 0x400844, 0); + nv_wr32(priv, 0x4008A0, vramsz); + nv_wr32(priv, 0x4008A4, vramsz); + break; + } + + return 0; +} + +struct nouveau_oclass +nv40_gr_oclass = { + .handle = NV_ENGINE(GR, 0x40), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv40_gr_ctor, + .dtor = _nouveau_gr_dtor, + .init = nv40_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h new file mode 100644 index 000000000000..40545f260c0d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -0,0 +1,24 @@ +#ifndef __NV40_GR_H__ +#define __NV40_GR_H__ + +#include +#include + +/* returns 1 if device is one of the nv4x using the 0x4497 object class, + * helpful to determine a number of other hardware features + */ +static inline int +nv44_gr_class(void *priv) +{ + struct nouveau_device *device = nv_device(priv); + + if ((device->chipset & 0xf0) == 0x60) + return 1; + + return !(0x0baf & (1 << (device->chipset & 0x0f))); +} + +int nv40_grctx_init(struct nouveau_device *, u32 *size); +void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c new file mode 100644 index 000000000000..bd7687c683c8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -0,0 +1,1009 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "nv50.h" + +struct nv50_gr_priv { + struct nouveau_gr base; + spinlock_t lock; + u32 size; +}; + +struct nv50_gr_chan { + struct nouveau_gr_chan base; +}; + +static u64 +nv50_gr_units(struct nouveau_gr *gr) +{ + struct nv50_gr_priv *priv = (void *)gr; + + return nv_rd32(priv, 0x1540); +} + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static int +nv50_gr_object_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_gpuobj *obj; + int ret; + + ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, + 16, 16, 0, &obj); + *pobject = nv_object(obj); + if (ret) + return ret; + + nv_wo32(obj, 0x00, nv_mclass(obj)); + nv_wo32(obj, 0x04, 0x00000000); + nv_wo32(obj, 0x08, 0x00000000); + nv_wo32(obj, 0x0c, 0x00000000); + return 0; +} + +static struct nouveau_ofuncs +nv50_gr_ofuncs = { + .ctor = nv50_gr_object_ctor, + .dtor = _nouveau_gpuobj_dtor, + .init = _nouveau_gpuobj_init, + .fini = _nouveau_gpuobj_fini, + .rd32 = _nouveau_gpuobj_rd32, + .wr32 = _nouveau_gpuobj_wr32, +}; + +static struct nouveau_oclass +nv50_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x5097, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + {} +}; + +static struct nouveau_oclass +nv84_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x8297, &nv50_gr_ofuncs }, + {} +}; + +static struct nouveau_oclass +nva0_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x8397, &nv50_gr_ofuncs }, + {} +}; + +static struct nouveau_oclass +nva3_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x8597, &nv50_gr_ofuncs }, + { 0x85c0, &nv50_gr_ofuncs }, + {} +}; + +static struct nouveau_oclass +nvaf_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x85c0, &nv50_gr_ofuncs }, + { 0x8697, &nv50_gr_ofuncs }, + {} +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +static int +nv50_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_gr_priv *priv = (void *)engine; + struct nv50_gr_chan *chan; + int ret; + + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, + priv->size, 0, + NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); + return 0; +} + +static struct nouveau_oclass +nv50_gr_cclass = { + .handle = NV_ENGCTX(GR, 0x50), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_gr_context_ctor, + .dtor = _nouveau_gr_context_dtor, + .init = _nouveau_gr_context_init, + .fini = _nouveau_gr_context_fini, + .rd32 = _nouveau_gr_context_rd32, + .wr32 = _nouveau_gr_context_wr32, + }, +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_bitfield nv50_pgr_status[] = { + { 0x00000001, "BUSY" }, /* set when any bit is set */ + { 0x00000002, "DISPATCH" }, + { 0x00000004, "UNK2" }, + { 0x00000008, "UNK3" }, + { 0x00000010, "UNK4" }, + { 0x00000020, "UNK5" }, + { 0x00000040, "M2MF" }, + { 0x00000080, "UNK7" }, + { 0x00000100, "CTXPROG" }, + { 0x00000200, "VFETCH" }, + { 0x00000400, "CCACHE_PREGEOM" }, + { 0x00000800, "STRMOUT_VATTR_POSTGEOM" }, + { 0x00001000, "VCLIP" }, + { 0x00002000, "RATTR_APLANE" }, + { 0x00004000, "TRAST" }, + { 0x00008000, "CLIPID" }, + { 0x00010000, "ZCULL" }, + { 0x00020000, "ENG2D" }, + { 0x00040000, "RMASK" }, + { 0x00080000, "TPC_RAST" }, + { 0x00100000, "TPC_PROP" }, + { 0x00200000, "TPC_TEX" }, + { 0x00400000, "TPC_GEOM" }, + { 0x00800000, "TPC_MP" }, + { 0x01000000, "ROP" }, + {} +}; + +static const char *const nv50_pgr_vstatus_0[] = { + "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP", + NULL +}; + +static const char *const nv50_pgr_vstatus_1[] = { + "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL +}; + +static const char *const nv50_pgr_vstatus_2[] = { + "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK", + "ROP", NULL +}; + +static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r, + const char *const units[], u32 status) +{ + int i; + + nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); + + for (i = 0; units[i] && status; i++) { + if ((status & 7) == 1) + pr_cont(" %s", units[i]); + status >>= 3; + } + if (status) + pr_cont(" (invalid: 0x%x)", status); + pr_cont("\n"); +} + +static int +nv84_gr_tlb_flush(struct nouveau_engine *engine) +{ + struct nouveau_timer *ptimer = nouveau_timer(engine); + struct nv50_gr_priv *priv = (void *)engine; + bool idle, timeout = false; + unsigned long flags; + u64 start; + u32 tmp; + + spin_lock_irqsave(&priv->lock, flags); + nv_mask(priv, 0x400500, 0x00000001, 0x00000000); + + start = ptimer->read(ptimer); + do { + idle = true; + + for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { + if ((tmp & 7) == 1) + idle = false; + } + + for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { + if ((tmp & 7) == 1) + idle = false; + } + + for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { + if ((tmp & 7) == 1) + idle = false; + } + } while (!idle && + !(timeout = ptimer->read(ptimer) - start > 2000000000)); + + if (timeout) { + nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); + + tmp = nv_rd32(priv, 0x400700); + nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); + nouveau_bitfield_print(nv50_pgr_status, tmp); + pr_cont("\n"); + + nouveau_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0, + nv_rd32(priv, 0x400380)); + nouveau_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1, + nv_rd32(priv, 0x400384)); + nouveau_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2, + nv_rd32(priv, 0x400388)); + } + + + nv_wr32(priv, 0x100c80, 0x00000001); + if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) + nv_error(priv, "vm flush timeout\n"); + nv_mask(priv, 0x400500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&priv->lock, flags); + return timeout ? -EBUSY : 0; +} + +static const struct nouveau_bitfield nv50_mp_exec_errors[] = { + { 0x01, "STACK_UNDERFLOW" }, + { 0x02, "STACK_MISMATCH" }, + { 0x04, "QUADON_ACTIVE" }, + { 0x08, "TIMEOUT" }, + { 0x10, "INVALID_OPCODE" }, + { 0x20, "PM_OVERFLOW" }, + { 0x40, "BREAKPOINT" }, + {} +}; + +static const struct nouveau_bitfield nv50_mpc_traps[] = { + { 0x0000001, "LOCAL_LIMIT_READ" }, + { 0x0000010, "LOCAL_LIMIT_WRITE" }, + { 0x0000040, "STACK_LIMIT" }, + { 0x0000100, "GLOBAL_LIMIT_READ" }, + { 0x0001000, "GLOBAL_LIMIT_WRITE" }, + { 0x0010000, "MP0" }, + { 0x0020000, "MP1" }, + { 0x0040000, "GLOBAL_LIMIT_RED" }, + { 0x0400000, "GLOBAL_LIMIT_ATOM" }, + { 0x4000000, "MP2" }, + {} +}; + +static const struct nouveau_bitfield nv50_tex_traps[] = { + { 0x00000001, "" }, /* any bit set? */ + { 0x00000002, "FAULT" }, + { 0x00000004, "STORAGE_TYPE_MISMATCH" }, + { 0x00000008, "LINEAR_MISMATCH" }, + { 0x00000020, "WRONG_MEMTYPE" }, + {} +}; + +static const struct nouveau_bitfield nv50_gr_trap_m2mf[] = { + { 0x00000001, "NOTIFY" }, + { 0x00000002, "IN" }, + { 0x00000004, "OUT" }, + {} +}; + +static const struct nouveau_bitfield nv50_gr_trap_vfetch[] = { + { 0x00000001, "FAULT" }, + {} +}; + +static const struct nouveau_bitfield nv50_gr_trap_strmout[] = { + { 0x00000001, "FAULT" }, + {} +}; + +static const struct nouveau_bitfield nv50_gr_trap_ccache[] = { + { 0x00000001, "FAULT" }, + {} +}; + +/* There must be a *lot* of these. Will take some time to gather them up. */ +const struct nouveau_enum nv50_data_error_names[] = { + { 0x00000003, "INVALID_OPERATION", NULL }, + { 0x00000004, "INVALID_VALUE", NULL }, + { 0x00000005, "INVALID_ENUM", NULL }, + { 0x00000008, "INVALID_OBJECT", NULL }, + { 0x00000009, "READ_ONLY_OBJECT", NULL }, + { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, + { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, + { 0x0000000c, "INVALID_BITFIELD", NULL }, + { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, + { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, + { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, + { 0x00000010, "RT_DOUBLE_BIND", NULL }, + { 0x00000011, "RT_TYPES_MISMATCH", NULL }, + { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, + { 0x00000015, "FP_TOO_FEW_REGS", NULL }, + { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, + { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, + { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, + { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, + { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, + { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, + { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, + { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, + { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, + { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, + { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, + { 0x00000024, "VP_ZERO_INPUTS", NULL }, + { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, + { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, + { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, + { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, + { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, + { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, + { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, + { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, + { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, + { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, + { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, + { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, + { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, + { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, + { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, + {} +}; + +static const struct nouveau_bitfield nv50_gr_intr_name[] = { + { 0x00000001, "NOTIFY" }, + { 0x00000002, "COMPUTE_QUERY" }, + { 0x00000010, "ILLEGAL_MTHD" }, + { 0x00000020, "ILLEGAL_CLASS" }, + { 0x00000040, "DOUBLE_NOTIFY" }, + { 0x00001000, "CONTEXT_SWITCH" }, + { 0x00010000, "BUFFER_NOTIFY" }, + { 0x00100000, "DATA_ERROR" }, + { 0x00200000, "TRAP" }, + { 0x01000000, "SINGLE_STEP" }, + {} +}; + +static const struct nouveau_bitfield nv50_gr_trap_prop[] = { + { 0x00000004, "SURF_WIDTH_OVERRUN" }, + { 0x00000008, "SURF_HEIGHT_OVERRUN" }, + { 0x00000010, "DST2D_FAULT" }, + { 0x00000020, "ZETA_FAULT" }, + { 0x00000040, "RT_FAULT" }, + { 0x00000080, "CUDA_FAULT" }, + { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" }, + { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" }, + { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" }, + { 0x00000800, "DST2D_LINEAR_MISMATCH" }, + { 0x00001000, "RT_LINEAR_MISMATCH" }, + {} +}; + +static void +nv50_priv_prop_trap(struct nv50_gr_priv *priv, + u32 ustatus_addr, u32 ustatus, u32 tp) +{ + u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); + u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); + u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); + u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); + u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); + u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); + u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); + + /* CUDA memory: l[], g[] or stack. */ + if (ustatus & 0x00000080) { + if (e18 & 0x80000000) { + /* g[] read fault? */ + nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", + tp, e14, e10 | ((e18 >> 24) & 0x1f)); + e18 &= ~0x1f000000; + } else if (e18 & 0xc) { + /* g[] write fault? */ + nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", + tp, e14, e10 | ((e18 >> 7) & 0x1f)); + e18 &= ~0x00000f80; + } else { + nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", + tp, e14, e10); + } + ustatus &= ~0x00000080; + } + if (ustatus) { + nv_error(priv, "TRAP_PROP - TP %d -", tp); + nouveau_bitfield_print(nv50_gr_trap_prop, ustatus); + pr_cont(" - Address %02x%08x\n", e14, e10); + } + nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", + tp, e0c, e18, e1c, e20, e24); +} + +static void +nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display) +{ + u32 units = nv_rd32(priv, 0x1540); + u32 addr, mp10, status, pc, oplow, ophigh; + int i; + int mps = 0; + for (i = 0; i < 4; i++) { + if (!(units & 1 << (i+24))) + continue; + if (nv_device(priv)->chipset < 0xa0) + addr = 0x408200 + (tpid << 12) + (i << 7); + else + addr = 0x408100 + (tpid << 11) + (i << 7); + mp10 = nv_rd32(priv, addr + 0x10); + status = nv_rd32(priv, addr + 0x14); + if (!status) + continue; + if (display) { + nv_rd32(priv, addr + 0x20); + pc = nv_rd32(priv, addr + 0x24); + oplow = nv_rd32(priv, addr + 0x70); + ophigh = nv_rd32(priv, addr + 0x74); + nv_error(priv, "TRAP_MP_EXEC - " + "TP %d MP %d:", tpid, i); + nouveau_bitfield_print(nv50_mp_exec_errors, status); + pr_cont(" at %06x warp %d, opcode %08x %08x\n", + pc&0xffffff, pc >> 24, + oplow, ophigh); + } + nv_wr32(priv, addr + 0x10, mp10); + nv_wr32(priv, addr + 0x14, 0); + mps++; + } + if (!mps && display) + nv_error(priv, "TRAP_MP_EXEC - TP %d: " + "No MPs claiming errors?\n", tpid); +} + +static void +nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old, + u32 ustatus_new, int display, const char *name) +{ + int tps = 0; + u32 units = nv_rd32(priv, 0x1540); + int i, r; + u32 ustatus_addr, ustatus; + for (i = 0; i < 16; i++) { + if (!(units & (1 << i))) + continue; + if (nv_device(priv)->chipset < 0xa0) + ustatus_addr = ustatus_old + (i << 12); + else + ustatus_addr = ustatus_new + (i << 11); + ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; + if (!ustatus) + continue; + tps++; + switch (type) { + case 6: /* texture error... unknown for now */ + if (display) { + nv_error(priv, "magic set %d:\n", i); + for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) + nv_error(priv, "\t0x%08x: 0x%08x\n", r, + nv_rd32(priv, r)); + if (ustatus) { + nv_error(priv, "%s - TP%d:", name, i); + nouveau_bitfield_print(nv50_tex_traps, + ustatus); + pr_cont("\n"); + ustatus = 0; + } + } + break; + case 7: /* MP error */ + if (ustatus & 0x04030000) { + nv50_priv_mp_trap(priv, i, display); + ustatus &= ~0x04030000; + } + if (ustatus && display) { + nv_error(priv, "%s - TP%d:", name, i); + nouveau_bitfield_print(nv50_mpc_traps, ustatus); + pr_cont("\n"); + ustatus = 0; + } + break; + case 8: /* PROP error */ + if (display) + nv50_priv_prop_trap( + priv, ustatus_addr, ustatus, i); + ustatus = 0; + break; + } + if (ustatus) { + if (display) + nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); + } + nv_wr32(priv, ustatus_addr, 0xc0000000); + } + + if (!tps && display) + nv_warn(priv, "%s - No TPs claiming errors?\n", name); +} + +static int +nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, + int chid, u64 inst, struct nouveau_object *engctx) +{ + u32 status = nv_rd32(priv, 0x400108); + u32 ustatus; + + if (!status && display) { + nv_error(priv, "TRAP: no units reporting traps?\n"); + return 1; + } + + /* DISPATCH: Relays commands to other units and handles NOTIFY, + * COND, QUERY. If you get a trap from it, the command is still stuck + * in DISPATCH and you need to do something about it. */ + if (status & 0x001) { + ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; + if (!ustatus && display) { + nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); + } + + nv_wr32(priv, 0x400500, 0x00000000); + + /* Known to be triggered by screwed up NOTIFY and COND... */ + if (ustatus & 0x00000001) { + u32 addr = nv_rd32(priv, 0x400808); + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00001ffc); + u32 datal = nv_rd32(priv, 0x40080c); + u32 datah = nv_rd32(priv, 0x400810); + u32 class = nv_rd32(priv, 0x400814); + u32 r848 = nv_rd32(priv, 0x400848); + + nv_error(priv, "TRAP DISPATCH_FAULT\n"); + if (display && (addr & 0x80000000)) { + nv_error(priv, + "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", + chid, inst, + nouveau_client_name(engctx), subc, + class, mthd, datah, datal, addr, r848); + } else + if (display) { + nv_error(priv, "no stuck command?\n"); + } + + nv_wr32(priv, 0x400808, 0); + nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); + nv_wr32(priv, 0x400848, 0); + ustatus &= ~0x00000001; + } + + if (ustatus & 0x00000002) { + u32 addr = nv_rd32(priv, 0x40084c); + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00001ffc); + u32 data = nv_rd32(priv, 0x40085c); + u32 class = nv_rd32(priv, 0x400814); + + nv_error(priv, "TRAP DISPATCH_QUERY\n"); + if (display && (addr & 0x80000000)) { + nv_error(priv, + "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", + chid, inst, + nouveau_client_name(engctx), subc, + class, mthd, data, addr); + } else + if (display) { + nv_error(priv, "no stuck command?\n"); + } + + nv_wr32(priv, 0x40084c, 0); + ustatus &= ~0x00000002; + } + + if (ustatus && display) { + nv_error(priv, "TRAP_DISPATCH (unknown " + "0x%08x)\n", ustatus); + } + + nv_wr32(priv, 0x400804, 0xc0000000); + nv_wr32(priv, 0x400108, 0x001); + status &= ~0x001; + if (!status) + return 0; + } + + /* M2MF: Memory to memory copy engine. */ + if (status & 0x002) { + u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; + if (display) { + nv_error(priv, "TRAP_M2MF"); + nouveau_bitfield_print(nv50_gr_trap_m2mf, ustatus); + pr_cont("\n"); + nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", + nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), + nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); + + } + + /* No sane way found yet -- just reset the bugger. */ + nv_wr32(priv, 0x400040, 2); + nv_wr32(priv, 0x400040, 0); + nv_wr32(priv, 0x406800, 0xc0000000); + nv_wr32(priv, 0x400108, 0x002); + status &= ~0x002; + } + + /* VFETCH: Fetches data from vertex buffers. */ + if (status & 0x004) { + u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; + if (display) { + nv_error(priv, "TRAP_VFETCH"); + nouveau_bitfield_print(nv50_gr_trap_vfetch, ustatus); + pr_cont("\n"); + nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", + nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), + nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); + } + + nv_wr32(priv, 0x400c04, 0xc0000000); + nv_wr32(priv, 0x400108, 0x004); + status &= ~0x004; + } + + /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ + if (status & 0x008) { + ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; + if (display) { + nv_error(priv, "TRAP_STRMOUT"); + nouveau_bitfield_print(nv50_gr_trap_strmout, ustatus); + pr_cont("\n"); + nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", + nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), + nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); + + } + + /* No sane way found yet -- just reset the bugger. */ + nv_wr32(priv, 0x400040, 0x80); + nv_wr32(priv, 0x400040, 0); + nv_wr32(priv, 0x401800, 0xc0000000); + nv_wr32(priv, 0x400108, 0x008); + status &= ~0x008; + } + + /* CCACHE: Handles code and c[] caches and fills them. */ + if (status & 0x010) { + ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; + if (display) { + nv_error(priv, "TRAP_CCACHE"); + nouveau_bitfield_print(nv50_gr_trap_ccache, ustatus); + pr_cont("\n"); + nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" + " %08x %08x %08x\n", + nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), + nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), + nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), + nv_rd32(priv, 0x40501c)); + + } + + nv_wr32(priv, 0x405018, 0xc0000000); + nv_wr32(priv, 0x400108, 0x010); + status &= ~0x010; + } + + /* Unknown, not seen yet... 0x402000 is the only trap status reg + * remaining, so try to handle it anyway. Perhaps related to that + * unknown DMA slot on tesla? */ + if (status & 0x20) { + ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; + if (display) + nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); + nv_wr32(priv, 0x402000, 0xc0000000); + /* no status modifiction on purpose */ + } + + /* TEXTURE: CUDA texturing units */ + if (status & 0x040) { + nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, + "TRAP_TEXTURE"); + nv_wr32(priv, 0x400108, 0x040); + status &= ~0x040; + } + + /* MP: CUDA execution engines. */ + if (status & 0x080) { + nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, + "TRAP_MP"); + nv_wr32(priv, 0x400108, 0x080); + status &= ~0x080; + } + + /* PROP: Handles TP-initiated uncached memory accesses: + * l[], g[], stack, 2d surfaces, render targets. */ + if (status & 0x100) { + nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, + "TRAP_PROP"); + nv_wr32(priv, 0x400108, 0x100); + status &= ~0x100; + } + + if (status) { + if (display) + nv_error(priv, "TRAP: unknown 0x%08x\n", status); + nv_wr32(priv, 0x400108, status); + } + + return 1; +} + +static void +nv50_gr_intr(struct nouveau_subdev *subdev) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(subdev); + struct nouveau_engine *engine = nv_engine(subdev); + struct nouveau_object *engctx; + struct nouveau_handle *handle = NULL; + struct nv50_gr_priv *priv = (void *)subdev; + u32 stat = nv_rd32(priv, 0x400100); + u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; + u32 addr = nv_rd32(priv, 0x400704); + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00001ffc); + u32 data = nv_rd32(priv, 0x400708); + u32 class = nv_rd32(priv, 0x400814); + u32 show = stat, show_bitfield = stat; + int chid; + + engctx = nouveau_engctx_get(engine, inst); + chid = pfifo->chid(pfifo, engctx); + + if (stat & 0x00000010) { + handle = nouveau_handle_get_class(engctx, class); + if (handle && !nv_call(handle->object, mthd, data)) + show &= ~0x00000010; + nouveau_handle_put(handle); + } + + if (show & 0x00100000) { + u32 ecode = nv_rd32(priv, 0x400110); + nv_error(priv, "DATA_ERROR "); + nouveau_enum_print(nv50_data_error_names, ecode); + pr_cont("\n"); + show_bitfield &= ~0x00100000; + } + + if (stat & 0x00200000) { + if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12, + engctx)) + show &= ~0x00200000; + show_bitfield &= ~0x00200000; + } + + nv_wr32(priv, 0x400100, stat); + nv_wr32(priv, 0x400500, 0x00010001); + + if (show) { + show &= show_bitfield; + if (show) { + nv_error(priv, "%s", ""); + nouveau_bitfield_print(nv50_gr_intr_name, show); + pr_cont("\n"); + } + nv_error(priv, + "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, (u64)inst << 12, nouveau_client_name(engctx), + subc, class, mthd, data); + } + + if (nv_rd32(priv, 0x400824) & (1 << 31)) + nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); + + nouveau_engctx_put(engctx); +} + +static int +nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_gr_priv *priv; + int ret; + + ret = nouveau_gr_create(parent, engine, oclass, true, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00201000; + nv_subdev(priv)->intr = nv50_gr_intr; + nv_engine(priv)->cclass = &nv50_gr_cclass; + + priv->base.units = nv50_gr_units; + + switch (nv_device(priv)->chipset) { + case 0x50: + nv_engine(priv)->sclass = nv50_gr_sclass; + break; + case 0x84: + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0x98: + nv_engine(priv)->sclass = nv84_gr_sclass; + break; + case 0xa0: + case 0xaa: + case 0xac: + nv_engine(priv)->sclass = nva0_gr_sclass; + break; + case 0xa3: + case 0xa5: + case 0xa8: + nv_engine(priv)->sclass = nva3_gr_sclass; + break; + case 0xaf: + nv_engine(priv)->sclass = nvaf_gr_sclass; + break; + + } + + /* unfortunate hw bug workaround... */ + if (nv_device(priv)->chipset != 0x50 && + nv_device(priv)->chipset != 0xac) + nv_engine(priv)->tlb_flush = nv84_gr_tlb_flush; + + spin_lock_init(&priv->lock); + return 0; +} + +static int +nv50_gr_init(struct nouveau_object *object) +{ + struct nv50_gr_priv *priv = (void *)object; + int ret, units, i; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ + nv_wr32(priv, 0x40008c, 0x00000004); + + /* reset/enable traps and interrupts */ + nv_wr32(priv, 0x400804, 0xc0000000); + nv_wr32(priv, 0x406800, 0xc0000000); + nv_wr32(priv, 0x400c04, 0xc0000000); + nv_wr32(priv, 0x401800, 0xc0000000); + nv_wr32(priv, 0x405018, 0xc0000000); + nv_wr32(priv, 0x402000, 0xc0000000); + + units = nv_rd32(priv, 0x001540); + for (i = 0; i < 16; i++) { + if (!(units & (1 << i))) + continue; + + if (nv_device(priv)->chipset < 0xa0) { + nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); + nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); + nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); + } else { + nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); + nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); + nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); + } + } + + nv_wr32(priv, 0x400108, 0xffffffff); + nv_wr32(priv, 0x400138, 0xffffffff); + nv_wr32(priv, 0x400100, 0xffffffff); + nv_wr32(priv, 0x40013c, 0xffffffff); + nv_wr32(priv, 0x400500, 0x00010001); + + /* upload context program, initialise ctxctl defaults */ + ret = nv50_grctx_init(nv_device(priv), &priv->size); + if (ret) + return ret; + + nv_wr32(priv, 0x400824, 0x00000000); + nv_wr32(priv, 0x400828, 0x00000000); + nv_wr32(priv, 0x40082c, 0x00000000); + nv_wr32(priv, 0x400830, 0x00000000); + nv_wr32(priv, 0x40032c, 0x00000000); + nv_wr32(priv, 0x400330, 0x00000000); + + /* some unknown zcull magic */ + switch (nv_device(priv)->chipset & 0xf0) { + case 0x50: + case 0x80: + case 0x90: + nv_wr32(priv, 0x402ca8, 0x00000800); + break; + case 0xa0: + default: + if (nv_device(priv)->chipset == 0xa0 || + nv_device(priv)->chipset == 0xaa || + nv_device(priv)->chipset == 0xac) { + nv_wr32(priv, 0x402ca8, 0x00000802); + } else { + nv_wr32(priv, 0x402cc0, 0x00000000); + nv_wr32(priv, 0x402ca8, 0x00000002); + } + + break; + } + + /* zero out zcull regions */ + for (i = 0; i < 8; i++) { + nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); + nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); + nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); + nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); + } + return 0; +} + +struct nouveau_oclass +nv50_gr_oclass = { + .handle = NV_ENGINE(GR, 0x50), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_gr_ctor, + .dtor = _nouveau_gr_dtor, + .init = nv50_gr_init, + .fini = _nouveau_gr_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h new file mode 100644 index 000000000000..eb39af055bbb --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -0,0 +1,7 @@ +#ifndef __NV50_GR_H__ +#define __NV50_GR_H__ + +int nv50_grctx_init(struct nouveau_device *, u32 *size); +void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c new file mode 100644 index 000000000000..8133650b2777 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c @@ -0,0 +1,1667 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Zero Bandwidth Clear + ******************************************************************************/ + +static void +nvc0_gr_zbc_clear_color(struct nvc0_gr_priv *priv, int zbc) +{ + if (priv->zbc_color[zbc].format) { + nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); + nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); + nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); + nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); + } + nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); + nv_wr32(priv, 0x405820, zbc); + nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ +} + +static int +nvc0_gr_zbc_color_get(struct nvc0_gr_priv *priv, int format, + const u32 ds[4], const u32 l2[4]) +{ + struct nouveau_ltc *ltc = nouveau_ltc(priv); + int zbc = -ENOSPC, i; + + for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { + if (priv->zbc_color[i].format) { + if (priv->zbc_color[i].format != format) + continue; + if (memcmp(priv->zbc_color[i].ds, ds, sizeof( + priv->zbc_color[i].ds))) + continue; + if (memcmp(priv->zbc_color[i].l2, l2, sizeof( + priv->zbc_color[i].l2))) { + WARN_ON(1); + return -EINVAL; + } + return i; + } else { + zbc = (zbc < 0) ? i : zbc; + } + } + + if (zbc < 0) + return zbc; + + memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); + memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); + priv->zbc_color[zbc].format = format; + ltc->zbc_color_get(ltc, zbc, l2); + nvc0_gr_zbc_clear_color(priv, zbc); + return zbc; +} + +static void +nvc0_gr_zbc_clear_depth(struct nvc0_gr_priv *priv, int zbc) +{ + if (priv->zbc_depth[zbc].format) + nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); + nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); + nv_wr32(priv, 0x405820, zbc); + nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ +} + +static int +nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format, + const u32 ds, const u32 l2) +{ + struct nouveau_ltc *ltc = nouveau_ltc(priv); + int zbc = -ENOSPC, i; + + for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { + if (priv->zbc_depth[i].format) { + if (priv->zbc_depth[i].format != format) + continue; + if (priv->zbc_depth[i].ds != ds) + continue; + if (priv->zbc_depth[i].l2 != l2) { + WARN_ON(1); + return -EINVAL; + } + return i; + } else { + zbc = (zbc < 0) ? i : zbc; + } + } + + if (zbc < 0) + return zbc; + + priv->zbc_depth[zbc].format = format; + priv->zbc_depth[zbc].ds = ds; + priv->zbc_depth[zbc].l2 = l2; + ltc->zbc_depth_get(ltc, zbc, l2); + nvc0_gr_zbc_clear_depth(priv, zbc); + return zbc; +} + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static int +nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size) +{ + struct nvc0_gr_priv *priv = (void *)object->engine; + union { + struct fermi_a_zbc_color_v0 v0; + } *args = data; + int ret; + + if (nvif_unpack(args->v0, 0, 0, false)) { + switch (args->v0.format) { + case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: + case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: + case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: + case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: + case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: + case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: + case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: + case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: + case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: + case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: + case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: + case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: + case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: + case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: + case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: + case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: + case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: + case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: + case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: + ret = nvc0_gr_zbc_color_get(priv, args->v0.format, + args->v0.ds, + args->v0.l2); + if (ret >= 0) { + args->v0.index = ret; + return 0; + } + break; + default: + return -EINVAL; + } + } + + return ret; +} + +static int +nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size) +{ + struct nvc0_gr_priv *priv = (void *)object->engine; + union { + struct fermi_a_zbc_depth_v0 v0; + } *args = data; + int ret; + + if (nvif_unpack(args->v0, 0, 0, false)) { + switch (args->v0.format) { + case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: + ret = nvc0_gr_zbc_depth_get(priv, args->v0.format, + args->v0.ds, + args->v0.l2); + return (ret >= 0) ? 0 : -ENOSPC; + default: + return -EINVAL; + } + } + + return ret; +} + +static int +nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) +{ + switch (mthd) { + case FERMI_A_ZBC_COLOR: + return nvc0_fermi_mthd_zbc_color(object, data, size); + case FERMI_A_ZBC_DEPTH: + return nvc0_fermi_mthd_zbc_depth(object, data, size); + default: + break; + } + return -EINVAL; +} + +struct nouveau_ofuncs +nvc0_fermi_ofuncs = { + .ctor = _nouveau_object_ctor, + .dtor = nouveau_object_destroy, + .init = nouveau_object_init, + .fini = nouveau_object_fini, + .mthd = nvc0_fermi_mthd, +}; + +static int +nvc0_gr_set_shader_exceptions(struct nouveau_object *object, u32 mthd, + void *pdata, u32 size) +{ + struct nvc0_gr_priv *priv = (void *)nv_engine(object); + if (size >= sizeof(u32)) { + u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; + nv_wr32(priv, 0x419e44, data); + nv_wr32(priv, 0x419e4c, data); + return 0; + } + return -EINVAL; +} + +struct nouveau_omthds +nvc0_gr_9097_omthds[] = { + { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions }, + {} +}; + +struct nouveau_omthds +nvc0_gr_90c0_omthds[] = { + { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions }, + {} +}; + +struct nouveau_oclass +nvc0_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0x9039, &nouveau_object_ofuncs }, + { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +/******************************************************************************* + * PGRAPH context + ******************************************************************************/ + +int +nvc0_gr_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *args, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_vm *vm = nouveau_client(parent)->vm; + struct nvc0_gr_priv *priv = (void *)engine; + struct nvc0_gr_data *data = priv->mmio_data; + struct nvc0_gr_mmio *mmio = priv->mmio_list; + struct nvc0_gr_chan *chan; + int ret, i; + + /* allocate memory for context, and fill with default values */ + ret = nouveau_gr_context_create(parent, engine, oclass, NULL, + priv->size, 0x100, + NVOBJ_FLAG_ZERO_ALLOC, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + /* allocate memory for a "mmio list" buffer that's used by the HUB + * fuc to modify some per-context register settings on first load + * of the context. + */ + ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, + &chan->mmio); + if (ret) + return ret; + + ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, + NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, + &chan->mmio_vma); + if (ret) + return ret; + + /* allocate buffers referenced by mmio list */ + for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { + ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size, + data->align, 0, &chan->data[i].mem); + if (ret) + return ret; + + ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access, + &chan->data[i].vma); + if (ret) + return ret; + + data++; + } + + /* finally, fill in the mmio list and point the context at it */ + for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { + u32 addr = mmio->addr; + u32 data = mmio->data; + + if (mmio->buffer >= 0) { + u64 info = chan->data[mmio->buffer].vma.offset; + data |= info >> mmio->shift; + } + + nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); + nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); + mmio++; + } + + for (i = 0; i < priv->size; i += 4) + nv_wo32(chan, i, priv->data[i / 4]); + + if (!priv->firmware) { + nv_wo32(chan, 0x00, chan->mmio_nr / 2); + nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); + } else { + nv_wo32(chan, 0xf4, 0); + nv_wo32(chan, 0xf8, 0); + nv_wo32(chan, 0x10, chan->mmio_nr / 2); + nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); + nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); + nv_wo32(chan, 0x1c, 1); + nv_wo32(chan, 0x20, 0); + nv_wo32(chan, 0x28, 0); + nv_wo32(chan, 0x2c, 0); + } + + return 0; +} + +void +nvc0_gr_context_dtor(struct nouveau_object *object) +{ + struct nvc0_gr_chan *chan = (void *)object; + int i; + + for (i = 0; i < ARRAY_SIZE(chan->data); i++) { + nouveau_gpuobj_unmap(&chan->data[i].vma); + nouveau_gpuobj_ref(NULL, &chan->data[i].mem); + } + + nouveau_gpuobj_unmap(&chan->mmio_vma); + nouveau_gpuobj_ref(NULL, &chan->mmio); + + nouveau_gr_context_destroy(&chan->base); +} + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nvc0_gr_init_main_0[] = { + { 0x400080, 1, 0x04, 0x003083c2 }, + { 0x400088, 1, 0x04, 0x00006fe7 }, + { 0x40008c, 1, 0x04, 0x00000000 }, + { 0x400090, 1, 0x04, 0x00000030 }, + { 0x40013c, 1, 0x04, 0x013901f7 }, + { 0x400140, 1, 0x04, 0x00000100 }, + { 0x400144, 1, 0x04, 0x00000000 }, + { 0x400148, 1, 0x04, 0x00000110 }, + { 0x400138, 1, 0x04, 0x00000000 }, + { 0x400130, 2, 0x04, 0x00000000 }, + { 0x400124, 1, 0x04, 0x00000002 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_fe_0[] = { + { 0x40415c, 1, 0x04, 0x00000000 }, + { 0x404170, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_pri_0[] = { + { 0x404488, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_rstr2d_0[] = { + { 0x407808, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_pd_0[] = { + { 0x406024, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405908, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_scc_0[] = { + { 0x40803c, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_prop_0[] = { + { 0x4184a0, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_gpc_unk_0[] = { + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x80000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_setup_0[] = { + { 0x418814, 3, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_crstr_0[] = { + { 0x418b04, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_setup_1[] = { + { 0x4188c8, 1, 0x04, 0x80000000 }, + { 0x4188cc, 1, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_zcull_0[] = { + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_gpm_0[] = { + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_gpc_unk_1[] = { + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000050 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_gcc_0[] = { + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_tpccs_0[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_tex_0[] = { + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_pe_0[] = { + { 0x41980c, 3, 0x04, 0x00000000 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_l1c_0[] = { + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_wwdx_0[] = { + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_tpccs_1[] = { + { 0x419d2c, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_mpc_0[] = { + { 0x419c0c, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc0_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x06060618 }, + { 0x419ed0, 1, 0x04, 0x0eff0e38 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_be_0[] = { + { 0x40880c, 1, 0x04, 0x00000000 }, + { 0x408910, 9, 0x04, 0x00000000 }, + { 0x408950, 1, 0x04, 0x00000000 }, + { 0x408954, 1, 0x04, 0x0000ffff }, + { 0x408984, 1, 0x04, 0x00000000 }, + { 0x408988, 1, 0x04, 0x08040201 }, + { 0x40898c, 1, 0x04, 0x80402010 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_fe_1[] = { + { 0x4040f0, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc0_gr_init_pe_1[] = { + { 0x419880, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_pack +nvc0_gr_pack_mmio[] = { + { nvc0_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvc0_gr_init_pd_0 }, + { nvc0_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvc0_gr_init_prop_0 }, + { nvc0_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc0_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvc0_gr_init_gpm_0 }, + { nvc0_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nvc0_gr_init_tpccs_0 }, + { nvc0_gr_init_tex_0 }, + { nvc0_gr_init_pe_0 }, + { nvc0_gr_init_l1c_0 }, + { nvc0_gr_init_wwdx_0 }, + { nvc0_gr_init_tpccs_1 }, + { nvc0_gr_init_mpc_0 }, + { nvc0_gr_init_sm_0 }, + { nvc0_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + { nvc0_gr_init_pe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +void +nvc0_gr_zbc_init(struct nvc0_gr_priv *priv) +{ + const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; + const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; + const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; + const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; + struct nouveau_ltc *ltc = nouveau_ltc(priv); + int index; + + if (!priv->zbc_color[0].format) { + nvc0_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]); + nvc0_gr_zbc_color_get(priv, 2, & one[0], &one[4]); + nvc0_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); + nvc0_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); + nvc0_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); + nvc0_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); + } + + for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) + nvc0_gr_zbc_clear_color(priv, index); + for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) + nvc0_gr_zbc_clear_depth(priv, index); +} + +void +nvc0_gr_mmio(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p) +{ + const struct nvc0_gr_pack *pack; + const struct nvc0_gr_init *init; + + pack_for_each_init(init, pack, p) { + u32 next = init->addr + init->count * init->pitch; + u32 addr = init->addr; + while (addr < next) { + nv_wr32(priv, addr, init->data); + addr += init->pitch; + } + } +} + +void +nvc0_gr_icmd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p) +{ + const struct nvc0_gr_pack *pack; + const struct nvc0_gr_init *init; + u32 data = 0; + + nv_wr32(priv, 0x400208, 0x80000000); + + pack_for_each_init(init, pack, p) { + u32 next = init->addr + init->count * init->pitch; + u32 addr = init->addr; + + if ((pack == p && init == p->init) || data != init->data) { + nv_wr32(priv, 0x400204, init->data); + data = init->data; + } + + while (addr < next) { + nv_wr32(priv, 0x400200, addr); + nv_wait(priv, 0x400700, 0x00000002, 0x00000000); + addr += init->pitch; + } + } + + nv_wr32(priv, 0x400208, 0x00000000); +} + +void +nvc0_gr_mthd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p) +{ + const struct nvc0_gr_pack *pack; + const struct nvc0_gr_init *init; + u32 data = 0; + + pack_for_each_init(init, pack, p) { + u32 ctrl = 0x80000000 | pack->type; + u32 next = init->addr + init->count * init->pitch; + u32 addr = init->addr; + + if ((pack == p && init == p->init) || data != init->data) { + nv_wr32(priv, 0x40448c, init->data); + data = init->data; + } + + while (addr < next) { + nv_wr32(priv, 0x404488, ctrl | (addr << 14)); + addr += init->pitch; + } + } +} + +u64 +nvc0_gr_units(struct nouveau_gr *gr) +{ + struct nvc0_gr_priv *priv = (void *)gr; + u64 cfg; + + cfg = (u32)priv->gpc_nr; + cfg |= (u32)priv->tpc_total << 8; + cfg |= (u64)priv->rop_nr << 32; + + return cfg; +} + +static const struct nouveau_enum nve0_sked_error[] = { + { 7, "CONSTANT_BUFFER_SIZE" }, + { 9, "LOCAL_MEMORY_SIZE_POS" }, + { 10, "LOCAL_MEMORY_SIZE_NEG" }, + { 11, "WARP_CSTACK_SIZE" }, + { 12, "TOTAL_TEMP_SIZE" }, + { 13, "REGISTER_COUNT" }, + { 18, "TOTAL_THREADS" }, + { 20, "PROGRAM_OFFSET" }, + { 21, "SHARED_MEMORY_SIZE" }, + { 25, "SHARED_CONFIG_TOO_SMALL" }, + { 26, "TOTAL_REGISTER_COUNT" }, + {} +}; + +static const struct nouveau_enum nvc0_gpc_rop_error[] = { + { 1, "RT_PITCH_OVERRUN" }, + { 4, "RT_WIDTH_OVERRUN" }, + { 5, "RT_HEIGHT_OVERRUN" }, + { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, + { 8, "RT_STORAGE_TYPE_MISMATCH" }, + { 10, "RT_LINEAR_MISMATCH" }, + {} +}; + +static void +nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc) +{ + u32 trap[4]; + int i; + + trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); + trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); + trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); + trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); + + nv_error(priv, "GPC%d/PROP trap:", gpc); + for (i = 0; i <= 29; ++i) { + if (!(trap[0] & (1 << i))) + continue; + pr_cont(" "); + nouveau_enum_print(nvc0_gpc_rop_error, i); + } + pr_cont("\n"); + + nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", + trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, + trap[3] & 0xff); + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); +} + +static const struct nouveau_enum nvc0_mp_warp_error[] = { + { 0x00, "NO_ERROR" }, + { 0x01, "STACK_MISMATCH" }, + { 0x05, "MISALIGNED_PC" }, + { 0x08, "MISALIGNED_GPR" }, + { 0x09, "INVALID_OPCODE" }, + { 0x0d, "GPR_OUT_OF_BOUNDS" }, + { 0x0e, "MEM_OUT_OF_BOUNDS" }, + { 0x0f, "UNALIGNED_MEM_ACCESS" }, + { 0x11, "INVALID_PARAM" }, + {} +}; + +static const struct nouveau_bitfield nvc0_mp_global_error[] = { + { 0x00000004, "MULTIPLE_WARP_ERRORS" }, + { 0x00000008, "OUT_OF_STACK_SPACE" }, + {} +}; + +static void +nvc0_gr_trap_mp(struct nvc0_gr_priv *priv, int gpc, int tpc) +{ + u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); + u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); + + nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); + nouveau_bitfield_print(nvc0_mp_global_error, gerr); + if (werr) { + pr_cont(" "); + nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff); + } + pr_cont("\n"); + + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); +} + +static void +nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc) +{ + u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); + + if (stat & 0x00000001) { + u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); + nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); + stat &= ~0x00000001; + } + + if (stat & 0x00000002) { + nvc0_gr_trap_mp(priv, gpc, tpc); + stat &= ~0x00000002; + } + + if (stat & 0x00000004) { + u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); + nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); + stat &= ~0x00000004; + } + + if (stat & 0x00000008) { + u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); + nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); + stat &= ~0x00000008; + } + + if (stat) { + nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); + } +} + +static void +nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc) +{ + u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); + int tpc; + + if (stat & 0x00000001) { + nvc0_gr_trap_gpc_rop(priv, gpc); + stat &= ~0x00000001; + } + + if (stat & 0x00000002) { + u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); + nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); + nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + stat &= ~0x00000002; + } + + if (stat & 0x00000004) { + u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); + nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); + nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + stat &= ~0x00000004; + } + + if (stat & 0x00000008) { + u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); + nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); + nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + stat &= ~0x00000009; + } + + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + u32 mask = 0x00010000 << tpc; + if (stat & mask) { + nvc0_gr_trap_tpc(priv, gpc, tpc); + nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); + stat &= ~mask; + } + } + + if (stat) { + nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); + } +} + +static void +nvc0_gr_trap_intr(struct nvc0_gr_priv *priv) +{ + u32 trap = nv_rd32(priv, 0x400108); + int rop, gpc, i; + + if (trap & 0x00000001) { + u32 stat = nv_rd32(priv, 0x404000); + nv_error(priv, "DISPATCH 0x%08x\n", stat); + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x400108, 0x00000001); + trap &= ~0x00000001; + } + + if (trap & 0x00000002) { + u32 stat = nv_rd32(priv, 0x404600); + nv_error(priv, "M2MF 0x%08x\n", stat); + nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(priv, 0x400108, 0x00000002); + trap &= ~0x00000002; + } + + if (trap & 0x00000008) { + u32 stat = nv_rd32(priv, 0x408030); + nv_error(priv, "CCACHE 0x%08x\n", stat); + nv_wr32(priv, 0x408030, 0xc0000000); + nv_wr32(priv, 0x400108, 0x00000008); + trap &= ~0x00000008; + } + + if (trap & 0x00000010) { + u32 stat = nv_rd32(priv, 0x405840); + nv_error(priv, "SHADER 0x%08x\n", stat); + nv_wr32(priv, 0x405840, 0xc0000000); + nv_wr32(priv, 0x400108, 0x00000010); + trap &= ~0x00000010; + } + + if (trap & 0x00000040) { + u32 stat = nv_rd32(priv, 0x40601c); + nv_error(priv, "UNK6 0x%08x\n", stat); + nv_wr32(priv, 0x40601c, 0xc0000000); + nv_wr32(priv, 0x400108, 0x00000040); + trap &= ~0x00000040; + } + + if (trap & 0x00000080) { + u32 stat = nv_rd32(priv, 0x404490); + nv_error(priv, "MACRO 0x%08x\n", stat); + nv_wr32(priv, 0x404490, 0xc0000000); + nv_wr32(priv, 0x400108, 0x00000080); + trap &= ~0x00000080; + } + + if (trap & 0x00000100) { + u32 stat = nv_rd32(priv, 0x407020); + + nv_error(priv, "SKED:"); + for (i = 0; i <= 29; ++i) { + if (!(stat & (1 << i))) + continue; + pr_cont(" "); + nouveau_enum_print(nve0_sked_error, i); + } + pr_cont("\n"); + + if (stat & 0x3fffffff) + nv_wr32(priv, 0x407020, 0x40000000); + nv_wr32(priv, 0x400108, 0x00000100); + trap &= ~0x00000100; + } + + if (trap & 0x01000000) { + u32 stat = nv_rd32(priv, 0x400118); + for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { + u32 mask = 0x00000001 << gpc; + if (stat & mask) { + nvc0_gr_trap_gpc(priv, gpc); + nv_wr32(priv, 0x400118, mask); + stat &= ~mask; + } + } + nv_wr32(priv, 0x400108, 0x01000000); + trap &= ~0x01000000; + } + + if (trap & 0x02000000) { + for (rop = 0; rop < priv->rop_nr; rop++) { + u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); + u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); + nv_error(priv, "ROP%d 0x%08x 0x%08x\n", + rop, statz, statc); + nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); + } + nv_wr32(priv, 0x400108, 0x02000000); + trap &= ~0x02000000; + } + + if (trap) { + nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); + nv_wr32(priv, 0x400108, trap); + } +} + +static void +nvc0_gr_ctxctl_debug_unit(struct nvc0_gr_priv *priv, u32 base) +{ + nv_error(priv, "%06x - done 0x%08x\n", base, + nv_rd32(priv, base + 0x400)); + nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, + nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), + nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); + nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, + nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), + nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); +} + +void +nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *priv) +{ + u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; + u32 gpc; + + nvc0_gr_ctxctl_debug_unit(priv, 0x409000); + for (gpc = 0; gpc < gpcnr; gpc++) + nvc0_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); +} + +static void +nvc0_gr_ctxctl_isr(struct nvc0_gr_priv *priv) +{ + u32 stat = nv_rd32(priv, 0x409c18); + + if (stat & 0x00000001) { + u32 code = nv_rd32(priv, 0x409814); + if (code == E_BAD_FWMTHD) { + u32 class = nv_rd32(priv, 0x409808); + u32 addr = nv_rd32(priv, 0x40980c); + u32 subc = (addr & 0x00070000) >> 16; + u32 mthd = (addr & 0x00003ffc); + u32 data = nv_rd32(priv, 0x409810); + + nv_error(priv, "FECS MTHD subc %d class 0x%04x " + "mthd 0x%04x data 0x%08x\n", + subc, class, mthd, data); + + nv_wr32(priv, 0x409c20, 0x00000001); + stat &= ~0x00000001; + } else { + nv_error(priv, "FECS ucode error %d\n", code); + } + } + + if (stat & 0x00080000) { + nv_error(priv, "FECS watchdog timeout\n"); + nvc0_gr_ctxctl_debug(priv); + nv_wr32(priv, 0x409c20, 0x00080000); + stat &= ~0x00080000; + } + + if (stat) { + nv_error(priv, "FECS 0x%08x\n", stat); + nvc0_gr_ctxctl_debug(priv); + nv_wr32(priv, 0x409c20, stat); + } +} + +static void +nvc0_gr_intr(struct nouveau_subdev *subdev) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(subdev); + struct nouveau_engine *engine = nv_engine(subdev); + struct nouveau_object *engctx; + struct nouveau_handle *handle; + struct nvc0_gr_priv *priv = (void *)subdev; + u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; + u32 stat = nv_rd32(priv, 0x400100); + u32 addr = nv_rd32(priv, 0x400704); + u32 mthd = (addr & 0x00003ffc); + u32 subc = (addr & 0x00070000) >> 16; + u32 data = nv_rd32(priv, 0x400708); + u32 code = nv_rd32(priv, 0x400110); + u32 class = nv_rd32(priv, 0x404200 + (subc * 4)); + int chid; + + engctx = nouveau_engctx_get(engine, inst); + chid = pfifo->chid(pfifo, engctx); + + if (stat & 0x00000010) { + handle = nouveau_handle_get_class(engctx, class); + if (!handle || nv_call(handle->object, mthd, data)) { + nv_error(priv, + "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, inst << 12, nouveau_client_name(engctx), + subc, class, mthd, data); + } + nouveau_handle_put(handle); + nv_wr32(priv, 0x400100, 0x00000010); + stat &= ~0x00000010; + } + + if (stat & 0x00000020) { + nv_error(priv, + "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, inst << 12, nouveau_client_name(engctx), subc, + class, mthd, data); + nv_wr32(priv, 0x400100, 0x00000020); + stat &= ~0x00000020; + } + + if (stat & 0x00100000) { + nv_error(priv, "DATA_ERROR ["); + nouveau_enum_print(nv50_data_error_names, code); + pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, inst << 12, nouveau_client_name(engctx), subc, + class, mthd, data); + nv_wr32(priv, 0x400100, 0x00100000); + stat &= ~0x00100000; + } + + if (stat & 0x00200000) { + nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, + nouveau_client_name(engctx)); + nvc0_gr_trap_intr(priv); + nv_wr32(priv, 0x400100, 0x00200000); + stat &= ~0x00200000; + } + + if (stat & 0x00080000) { + nvc0_gr_ctxctl_isr(priv); + nv_wr32(priv, 0x400100, 0x00080000); + stat &= ~0x00080000; + } + + if (stat) { + nv_error(priv, "unknown stat 0x%08x\n", stat); + nv_wr32(priv, 0x400100, stat); + } + + nv_wr32(priv, 0x400500, 0x00010001); + nouveau_engctx_put(engctx); +} + +void +nvc0_gr_init_fw(struct nvc0_gr_priv *priv, u32 fuc_base, + struct nvc0_gr_fuc *code, struct nvc0_gr_fuc *data) +{ + int i; + + nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); + for (i = 0; i < data->size / 4; i++) + nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); + + nv_wr32(priv, fuc_base + 0x0180, 0x01000000); + for (i = 0; i < code->size / 4; i++) { + if ((i & 0x3f) == 0) + nv_wr32(priv, fuc_base + 0x0188, i >> 6); + nv_wr32(priv, fuc_base + 0x0184, code->data[i]); + } + + /* code must be padded to 0x40 words */ + for (; i & 0x3f; i++) + nv_wr32(priv, fuc_base + 0x0184, 0); +} + +static void +nvc0_gr_init_csdata(struct nvc0_gr_priv *priv, + const struct nvc0_gr_pack *pack, + u32 falcon, u32 starstar, u32 base) +{ + const struct nvc0_gr_pack *iter; + const struct nvc0_gr_init *init; + u32 addr = ~0, prev = ~0, xfer = 0; + u32 star, temp; + + nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); + star = nv_rd32(priv, falcon + 0x01c4); + temp = nv_rd32(priv, falcon + 0x01c4); + if (temp > star) + star = temp; + nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); + + pack_for_each_init(init, iter, pack) { + u32 head = init->addr - base; + u32 tail = head + init->count * init->pitch; + while (head < tail) { + if (head != prev + 4 || xfer >= 32) { + if (xfer) { + u32 data = ((--xfer << 26) | addr); + nv_wr32(priv, falcon + 0x01c4, data); + star += 4; + } + addr = head; + xfer = 0; + } + prev = head; + xfer = xfer + 1; + head = head + init->pitch; + } + } + + nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); + nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); + nv_wr32(priv, falcon + 0x01c4, star + 4); +} + +int +nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv) +{ + struct nvc0_gr_oclass *oclass = (void *)nv_object(priv)->oclass; + struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; + int i; + + if (priv->firmware) { + /* load fuc microcode */ + nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + nvc0_gr_init_fw(priv, 0x409000, &priv->fuc409c, + &priv->fuc409d); + nvc0_gr_init_fw(priv, 0x41a000, &priv->fuc41ac, + &priv->fuc41ad); + nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + + /* start both of them running */ + nv_wr32(priv, 0x409840, 0xffffffff); + nv_wr32(priv, 0x41a10c, 0x00000000); + nv_wr32(priv, 0x40910c, 0x00000000); + nv_wr32(priv, 0x41a100, 0x00000002); + nv_wr32(priv, 0x409100, 0x00000002); + if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) + nv_warn(priv, "0x409800 wait failed\n"); + + nv_wr32(priv, 0x409840, 0xffffffff); + nv_wr32(priv, 0x409500, 0x7fffffff); + nv_wr32(priv, 0x409504, 0x00000021); + + nv_wr32(priv, 0x409840, 0xffffffff); + nv_wr32(priv, 0x409500, 0x00000000); + nv_wr32(priv, 0x409504, 0x00000010); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x10 timeout\n"); + return -EBUSY; + } + priv->size = nv_rd32(priv, 0x409800); + + nv_wr32(priv, 0x409840, 0xffffffff); + nv_wr32(priv, 0x409500, 0x00000000); + nv_wr32(priv, 0x409504, 0x00000016); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x16 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409840, 0xffffffff); + nv_wr32(priv, 0x409500, 0x00000000); + nv_wr32(priv, 0x409504, 0x00000025); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x25 timeout\n"); + return -EBUSY; + } + + if (nv_device(priv)->chipset >= 0xe0) { + nv_wr32(priv, 0x409800, 0x00000000); + nv_wr32(priv, 0x409500, 0x00000001); + nv_wr32(priv, 0x409504, 0x00000030); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x30 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409810, 0xb00095c8); + nv_wr32(priv, 0x409800, 0x00000000); + nv_wr32(priv, 0x409500, 0x00000001); + nv_wr32(priv, 0x409504, 0x00000031); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x31 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409810, 0x00080420); + nv_wr32(priv, 0x409800, 0x00000000); + nv_wr32(priv, 0x409500, 0x00000001); + nv_wr32(priv, 0x409504, 0x00000032); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x32 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409614, 0x00000070); + nv_wr32(priv, 0x409614, 0x00000770); + nv_wr32(priv, 0x40802c, 0x00000001); + } + + if (priv->data == NULL) { + int ret = nvc0_grctx_generate(priv); + if (ret) { + nv_error(priv, "failed to construct context\n"); + return ret; + } + } + + return 0; + } else + if (!oclass->fecs.ucode) { + return -ENOSYS; + } + + /* load HUB microcode */ + nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + nv_wr32(priv, 0x4091c0, 0x01000000); + for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) + nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); + + nv_wr32(priv, 0x409180, 0x01000000); + for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { + if ((i & 0x3f) == 0) + nv_wr32(priv, 0x409188, i >> 6); + nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); + } + + /* load GPC microcode */ + nv_wr32(priv, 0x41a1c0, 0x01000000); + for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) + nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); + + nv_wr32(priv, 0x41a180, 0x01000000); + for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { + if ((i & 0x3f) == 0) + nv_wr32(priv, 0x41a188, i >> 6); + nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); + } + nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + + /* load register lists */ + nvc0_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); + nvc0_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); + nvc0_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); + nvc0_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); + + /* start HUB ucode running, it'll init the GPCs */ + nv_wr32(priv, 0x40910c, 0x00000000); + nv_wr32(priv, 0x409100, 0x00000002); + if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { + nv_error(priv, "HUB_INIT timed out\n"); + nvc0_gr_ctxctl_debug(priv); + return -EBUSY; + } + + priv->size = nv_rd32(priv, 0x409804); + if (priv->data == NULL) { + int ret = nvc0_grctx_generate(priv); + if (ret) { + nv_error(priv, "failed to construct context\n"); + return ret; + } + } + + return 0; +} + +int +nvc0_gr_init(struct nouveau_object *object) +{ + struct nvc0_gr_oclass *oclass = (void *)object->oclass; + struct nvc0_gr_priv *priv = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + u32 data[TPC_MAX / 8] = {}; + u8 tpcnr[GPC_MAX]; + int gpc, tpc, rop; + int ret, i; + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); + nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + + nvc0_gr_mmio(priv, oclass->mmio); + + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + data[i / 8] |= tpc << ((i % 8) * 4); + } + + nv_wr32(priv, GPC_BCAST(0x0980), data[0]); + nv_wr32(priv, GPC_BCAST(0x0984), data[1]); + nv_wr32(priv, GPC_BCAST(0x0988), data[2]); + nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0914), + priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | + priv->tpc_total); + nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + if (nv_device(priv)->chipset != 0xd7) + nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); + else + nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + + nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); + + nv_wr32(priv, 0x400500, 0x00010001); + + nv_wr32(priv, 0x400100, 0xffffffff); + nv_wr32(priv, 0x40013c, 0xffffffff); + + nv_wr32(priv, 0x409c24, 0x000f0000); + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(priv, 0x408030, 0xc0000000); + nv_wr32(priv, 0x40601c, 0xc0000000); + nv_wr32(priv, 0x404490, 0xc0000000); + nv_wr32(priv, 0x406018, 0xc0000000); + nv_wr32(priv, 0x405840, 0xc0000000); + nv_wr32(priv, 0x405844, 0x00ffffff); + nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); + nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + } + nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + } + + for (rop = 0; rop < priv->rop_nr; rop++) { + nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + } + + nv_wr32(priv, 0x400108, 0xffffffff); + nv_wr32(priv, 0x400138, 0xffffffff); + nv_wr32(priv, 0x400118, 0xffffffff); + nv_wr32(priv, 0x400130, 0xffffffff); + nv_wr32(priv, 0x40011c, 0xffffffff); + nv_wr32(priv, 0x400134, 0xffffffff); + + nv_wr32(priv, 0x400054, 0x34ce3464); + + nvc0_gr_zbc_init(priv); + + return nvc0_gr_init_ctxctl(priv); +} + +static void +nvc0_gr_dtor_fw(struct nvc0_gr_fuc *fuc) +{ + kfree(fuc->data); + fuc->data = NULL; +} + +int +nvc0_gr_ctor_fw(struct nvc0_gr_priv *priv, const char *fwname, + struct nvc0_gr_fuc *fuc) +{ + struct nouveau_device *device = nv_device(priv); + const struct firmware *fw; + char f[32]; + int ret; + + snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); + ret = request_firmware(&fw, f, nv_device_base(device)); + if (ret) { + snprintf(f, sizeof(f), "nouveau/%s", fwname); + ret = request_firmware(&fw, f, nv_device_base(device)); + if (ret) { + nv_error(priv, "failed to load %s\n", fwname); + return ret; + } + } + + fuc->size = fw->size; + fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); + release_firmware(fw); + return (fuc->data != NULL) ? 0 : -ENOMEM; +} + +void +nvc0_gr_dtor(struct nouveau_object *object) +{ + struct nvc0_gr_priv *priv = (void *)object; + + kfree(priv->data); + + nvc0_gr_dtor_fw(&priv->fuc409c); + nvc0_gr_dtor_fw(&priv->fuc409d); + nvc0_gr_dtor_fw(&priv->fuc41ac); + nvc0_gr_dtor_fw(&priv->fuc41ad); + + nouveau_gpuobj_ref(NULL, &priv->unk4188b8); + nouveau_gpuobj_ref(NULL, &priv->unk4188b4); + + nouveau_gr_destroy(&priv->base); +} + +int +nvc0_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *bclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_gr_oclass *oclass = (void *)bclass; + struct nouveau_device *device = nv_device(parent); + struct nvc0_gr_priv *priv; + bool use_ext_fw, enable; + int ret, i, j; + + use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW", + oclass->fecs.ucode == NULL); + enable = use_ext_fw || oclass->fecs.ucode != NULL; + + ret = nouveau_gr_create(parent, engine, bclass, enable, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x08001000; + nv_subdev(priv)->intr = nvc0_gr_intr; + + priv->base.units = nvc0_gr_units; + + if (use_ext_fw) { + nv_info(priv, "using external firmware\n"); + if (nvc0_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) || + nvc0_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) || + nvc0_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || + nvc0_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) + return -ENODEV; + priv->firmware = true; + } + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, + &priv->unk4188b4); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, + &priv->unk4188b8); + if (ret) + return ret; + + for (i = 0; i < 0x1000; i += 4) { + nv_wo32(priv->unk4188b4, i, 0x00000010); + nv_wo32(priv->unk4188b8, i, 0x00000010); + } + + priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; + priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; + for (i = 0; i < priv->gpc_nr; i++) { + priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); + priv->tpc_total += priv->tpc_nr[i]; + priv->ppc_nr[i] = oclass->ppc_nr; + for (j = 0; j < priv->ppc_nr[i]; j++) { + u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); + priv->ppc_tpc_nr[i][j] = hweight8(mask); + } + } + + /*XXX: these need figuring out... though it might not even matter */ + switch (nv_device(priv)->chipset) { + case 0xc0: + if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ + priv->magic_not_rop_nr = 0x07; + } else + if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ + priv->magic_not_rop_nr = 0x05; + } else + if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ + priv->magic_not_rop_nr = 0x06; + } + break; + case 0xc3: /* 450, 4/0/0/0, 2 */ + priv->magic_not_rop_nr = 0x03; + break; + case 0xc4: /* 460, 3/4/0/0, 4 */ + priv->magic_not_rop_nr = 0x01; + break; + case 0xc1: /* 2/0/0/0, 1 */ + priv->magic_not_rop_nr = 0x01; + break; + case 0xc8: /* 4/4/3/4, 5 */ + priv->magic_not_rop_nr = 0x06; + break; + case 0xce: /* 4/4/0/0, 4 */ + priv->magic_not_rop_nr = 0x03; + break; + case 0xcf: /* 4/0/0/0, 3 */ + priv->magic_not_rop_nr = 0x03; + break; + case 0xd7: + case 0xd9: /* 1/0/0/0, 1 */ + priv->magic_not_rop_nr = 0x01; + break; + } + + nv_engine(priv)->cclass = *oclass->cclass; + nv_engine(priv)->sclass = oclass->sclass; + return 0; +} + +#include "fuc/hubnvc0.fuc3.h" + +struct nvc0_gr_ucode +nvc0_gr_fecs_ucode = { + .code.data = nvc0_grhub_code, + .code.size = sizeof(nvc0_grhub_code), + .data.data = nvc0_grhub_data, + .data.size = sizeof(nvc0_grhub_data), +}; + +#include "fuc/gpcnvc0.fuc3.h" + +struct nvc0_gr_ucode +nvc0_gr_gpccs_ucode = { + .code.data = nvc0_grgpc_code, + .code.size = sizeof(nvc0_grgpc_code), + .data.data = nvc0_grgpc_data, + .data.size = sizeof(nvc0_grgpc_data), +}; + +struct nouveau_oclass * +nvc0_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nvc0_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nvc0_grctx_oclass, + .sclass = nvc0_gr_sclass, + .mmio = nvc0_gr_pack_mmio, + .fecs.ucode = &nvc0_gr_fecs_ucode, + .gpccs.ucode = &nvc0_gr_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h new file mode 100644 index 000000000000..f2818a2b6d68 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h @@ -0,0 +1,270 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifndef __NVC0_GR_H__ +#define __NVC0_GR_H__ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "fuc/os.h" + +#define GPC_MAX 32 +#define TPC_MAX (GPC_MAX * 8) + +#define ROP_BCAST(r) (0x408800 + (r)) +#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) +#define GPC_BCAST(r) (0x418000 + (r)) +#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r)) +#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r)) +#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) + +struct nvc0_gr_data { + u32 size; + u32 align; + u32 access; +}; + +struct nvc0_gr_mmio { + u32 addr; + u32 data; + u32 shift; + int buffer; +}; + +struct nvc0_gr_fuc { + u32 *data; + u32 size; +}; + +struct nvc0_gr_zbc_color { + u32 format; + u32 ds[4]; + u32 l2[4]; +}; + +struct nvc0_gr_zbc_depth { + u32 format; + u32 ds; + u32 l2; +}; + +struct nvc0_gr_priv { + struct nouveau_gr base; + + struct nvc0_gr_fuc fuc409c; + struct nvc0_gr_fuc fuc409d; + struct nvc0_gr_fuc fuc41ac; + struct nvc0_gr_fuc fuc41ad; + bool firmware; + + struct nvc0_gr_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT]; + struct nvc0_gr_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; + + u8 rop_nr; + u8 gpc_nr; + u8 tpc_nr[GPC_MAX]; + u8 tpc_total; + u8 ppc_nr[GPC_MAX]; + u8 ppc_tpc_nr[GPC_MAX][4]; + + struct nouveau_gpuobj *unk4188b4; + struct nouveau_gpuobj *unk4188b8; + + struct nvc0_gr_data mmio_data[4]; + struct nvc0_gr_mmio mmio_list[4096/8]; + u32 size; + u32 *data; + + u8 magic_not_rop_nr; +}; + +struct nvc0_gr_chan { + struct nouveau_gr_chan base; + + struct nouveau_gpuobj *mmio; + struct nouveau_vma mmio_vma; + int mmio_nr; + struct { + struct nouveau_gpuobj *mem; + struct nouveau_vma vma; + } data[4]; +}; + +int nvc0_gr_context_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); +void nvc0_gr_context_dtor(struct nouveau_object *); + +void nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *); + +u64 nvc0_gr_units(struct nouveau_gr *); +int nvc0_gr_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *data, u32 size, + struct nouveau_object **); +void nvc0_gr_dtor(struct nouveau_object *); +int nvc0_gr_init(struct nouveau_object *); +void nvc0_gr_zbc_init(struct nvc0_gr_priv *); + +int nve4_gr_fini(struct nouveau_object *, bool); +int nve4_gr_init(struct nouveau_object *); + +int nvf0_gr_fini(struct nouveau_object *, bool); + +extern struct nouveau_ofuncs nvc0_fermi_ofuncs; + +extern struct nouveau_oclass nvc0_gr_sclass[]; +extern struct nouveau_omthds nvc0_gr_9097_omthds[]; +extern struct nouveau_omthds nvc0_gr_90c0_omthds[]; +extern struct nouveau_oclass nvc8_gr_sclass[]; +extern struct nouveau_oclass nvf0_gr_sclass[]; + +struct nvc0_gr_init { + u32 addr; + u8 count; + u8 pitch; + u32 data; +}; + +struct nvc0_gr_pack { + const struct nvc0_gr_init *init; + u32 type; +}; + +#define pack_for_each_init(init, pack, head) \ + for (pack = head; pack && pack->init; pack++) \ + for (init = pack->init; init && init->count; init++) + +struct nvc0_gr_ucode { + struct nvc0_gr_fuc code; + struct nvc0_gr_fuc data; +}; + +extern struct nvc0_gr_ucode nvc0_gr_fecs_ucode; +extern struct nvc0_gr_ucode nvc0_gr_gpccs_ucode; + +extern struct nvc0_gr_ucode nvf0_gr_fecs_ucode; +extern struct nvc0_gr_ucode nvf0_gr_gpccs_ucode; + +struct nvc0_gr_oclass { + struct nouveau_oclass base; + struct nouveau_oclass **cclass; + struct nouveau_oclass *sclass; + const struct nvc0_gr_pack *mmio; + struct { + struct nvc0_gr_ucode *ucode; + } fecs; + struct { + struct nvc0_gr_ucode *ucode; + } gpccs; + int ppc_nr; +}; + +void nvc0_gr_mmio(struct nvc0_gr_priv *, const struct nvc0_gr_pack *); +void nvc0_gr_icmd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *); +void nvc0_gr_mthd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *); +int nvc0_gr_init_ctxctl(struct nvc0_gr_priv *); + +/* register init value lists */ + +extern const struct nvc0_gr_init nvc0_gr_init_main_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_fe_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_pri_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_rstr2d_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_pd_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_ds_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_scc_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_prop_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_setup_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_crstr_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_setup_1[]; +extern const struct nvc0_gr_init nvc0_gr_init_zcull_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_gpm_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_1[]; +extern const struct nvc0_gr_init nvc0_gr_init_gcc_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_tpccs_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_tex_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_pe_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_l1c_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_wwdx_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_tpccs_1[]; +extern const struct nvc0_gr_init nvc0_gr_init_mpc_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_be_0[]; +extern const struct nvc0_gr_init nvc0_gr_init_fe_1[]; +extern const struct nvc0_gr_init nvc0_gr_init_pe_1[]; + +extern const struct nvc0_gr_init nvc4_gr_init_ds_0[]; +extern const struct nvc0_gr_init nvc4_gr_init_tex_0[]; +extern const struct nvc0_gr_init nvc4_gr_init_sm_0[]; + +extern const struct nvc0_gr_init nvc1_gr_init_gpc_unk_0[]; +extern const struct nvc0_gr_init nvc1_gr_init_setup_1[]; + +extern const struct nvc0_gr_init nvd9_gr_init_pd_0[]; +extern const struct nvc0_gr_init nvd9_gr_init_ds_0[]; +extern const struct nvc0_gr_init nvd9_gr_init_prop_0[]; +extern const struct nvc0_gr_init nvd9_gr_init_gpm_0[]; +extern const struct nvc0_gr_init nvd9_gr_init_gpc_unk_1[]; +extern const struct nvc0_gr_init nvd9_gr_init_tex_0[]; +extern const struct nvc0_gr_init nvd9_gr_init_sm_0[]; +extern const struct nvc0_gr_init nvd9_gr_init_fe_1[]; + +extern const struct nvc0_gr_init nvd7_gr_init_pes_0[]; +extern const struct nvc0_gr_init nvd7_gr_init_wwdx_0[]; +extern const struct nvc0_gr_init nvd7_gr_init_cbm_0[]; + +extern const struct nvc0_gr_init nve4_gr_init_main_0[]; +extern const struct nvc0_gr_init nve4_gr_init_tpccs_0[]; +extern const struct nvc0_gr_init nve4_gr_init_pe_0[]; +extern const struct nvc0_gr_init nve4_gr_init_be_0[]; +extern const struct nvc0_gr_pack nve4_gr_pack_mmio[]; + +extern const struct nvc0_gr_init nvf0_gr_init_fe_0[]; +extern const struct nvc0_gr_init nvf0_gr_init_ds_0[]; +extern const struct nvc0_gr_init nvf0_gr_init_sked_0[]; +extern const struct nvc0_gr_init nvf0_gr_init_cwd_0[]; +extern const struct nvc0_gr_init nvf0_gr_init_gpc_unk_1[]; +extern const struct nvc0_gr_init nvf0_gr_init_tex_0[]; +extern const struct nvc0_gr_init nvf0_gr_init_sm_0[]; + +extern const struct nvc0_gr_init nv108_gr_init_gpc_unk_0[]; + + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c new file mode 100644 index 000000000000..4a70ea30bae9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c @@ -0,0 +1,133 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nvc1_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0x9039, &nouveau_object_ofuncs }, + { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nvc1_gr_init_gpc_unk_0[] = { + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc1_gr_init_setup_1[] = { + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + {} +}; + +static const struct nvc0_gr_init +nvc1_gr_init_gpc_unk_1[] = { + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000003 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc1_gr_init_pe_0[] = { + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419810, 1, 0x04, 0x00000000 }, + { 0x419814, 1, 0x04, 0x00000004 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419880, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_pack +nvc1_gr_pack_mmio[] = { + { nvc0_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvc0_gr_init_pd_0 }, + { nvc4_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvc0_gr_init_prop_0 }, + { nvc1_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvc0_gr_init_gpm_0 }, + { nvc1_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nvc0_gr_init_tpccs_0 }, + { nvc4_gr_init_tex_0 }, + { nvc1_gr_init_pe_0 }, + { nvc0_gr_init_l1c_0 }, + { nvc0_gr_init_wwdx_0 }, + { nvc0_gr_init_tpccs_1 }, + { nvc0_gr_init_mpc_0 }, + { nvc4_gr_init_sm_0 }, + { nvc0_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nouveau_oclass * +nvc1_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xc1), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nvc0_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nvc1_grctx_oclass, + .sclass = nvc1_gr_sclass, + .mmio = nvc1_gr_pack_mmio, + .fecs.ucode = &nvc0_gr_fecs_ucode, + .gpccs.ucode = &nvc0_gr_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c new file mode 100644 index 000000000000..0af6335efa50 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c @@ -0,0 +1,128 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nvc4_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x00002834 }, + { 0x405908, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvc4_gr_init_tex_0[] = { + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvc4_gr_init_pe_0[] = { + { 0x41980c, 3, 0x04, 0x00000000 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419880, 1, 0x04, 0x00000002 }, + {} +}; + +const struct nvc0_gr_init +nvc4_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0e063818 }, + { 0x419ecc, 1, 0x04, 0x0e060e06 }, + { 0x419ed0, 1, 0x04, 0x00003818 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvc4_gr_pack_mmio[] = { + { nvc0_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvc0_gr_init_pd_0 }, + { nvc4_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvc0_gr_init_prop_0 }, + { nvc0_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc0_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvc0_gr_init_gpm_0 }, + { nvc0_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nvc0_gr_init_tpccs_0 }, + { nvc4_gr_init_tex_0 }, + { nvc4_gr_init_pe_0 }, + { nvc0_gr_init_l1c_0 }, + { nvc0_gr_init_wwdx_0 }, + { nvc0_gr_init_tpccs_1 }, + { nvc0_gr_init_mpc_0 }, + { nvc4_gr_init_sm_0 }, + { nvc0_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nouveau_oclass * +nvc4_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xc3), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nvc0_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nvc4_grctx_oclass, + .sclass = nvc0_gr_sclass, + .mmio = nvc4_gr_pack_mmio, + .fecs.ucode = &nvc0_gr_fecs_ucode, + .gpccs.ucode = &nvc0_gr_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c new file mode 100644 index 000000000000..692ee30855fb --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c @@ -0,0 +1,115 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +struct nouveau_oclass +nvc8_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0x9039, &nouveau_object_ofuncs }, + { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { FERMI_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvc8_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100f02 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x06060618 }, + { 0x419ed0, 1, 0x04, 0x0eff0e38 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvc8_gr_pack_mmio[] = { + { nvc0_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvc0_gr_init_pd_0 }, + { nvc0_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvc0_gr_init_prop_0 }, + { nvc0_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvc0_gr_init_gpm_0 }, + { nvc0_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nvc0_gr_init_tpccs_0 }, + { nvc0_gr_init_tex_0 }, + { nvc0_gr_init_pe_0 }, + { nvc0_gr_init_l1c_0 }, + { nvc0_gr_init_wwdx_0 }, + { nvc0_gr_init_tpccs_1 }, + { nvc0_gr_init_mpc_0 }, + { nvc8_gr_init_sm_0 }, + { nvc0_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + { nvc0_gr_init_pe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nouveau_oclass * +nvc8_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xc8), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nvc0_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nvc8_grctx_oclass, + .sclass = nvc8_gr_sclass, + .mmio = nvc8_gr_pack_mmio, + .fecs.ucode = &nvc0_gr_fecs_ucode, + .gpccs.ucode = &nvc0_gr_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c new file mode 100644 index 000000000000..a2371a9f21de --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c @@ -0,0 +1,137 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +static const struct nvc0_gr_init +nvd7_gr_init_pe_0[] = { + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc8 }, + { 0x419850, 3, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd7_gr_init_pes_0[] = { + { 0x41be04, 1, 0x04, 0x00000000 }, + { 0x41be08, 1, 0x04, 0x00000004 }, + { 0x41be0c, 1, 0x04, 0x00000000 }, + { 0x41be10, 1, 0x04, 0x003b8bc7 }, + { 0x41be14, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd7_gr_init_wwdx_0[] = { + { 0x41bfd4, 1, 0x04, 0x00800000 }, + { 0x41bfdc, 1, 0x04, 0x00000000 }, + { 0x41bff8, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd7_gr_init_cbm_0[] = { + { 0x41becc, 1, 0x04, 0x00000000 }, + { 0x41bee8, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvd7_gr_pack_mmio[] = { + { nvc0_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvd9_gr_init_pd_0 }, + { nvd9_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvd9_gr_init_prop_0 }, + { nvc1_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvd9_gr_init_gpm_0 }, + { nvd9_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nvc0_gr_init_tpccs_0 }, + { nvd9_gr_init_tex_0 }, + { nvd7_gr_init_pe_0 }, + { nvc0_gr_init_l1c_0 }, + { nvc0_gr_init_mpc_0 }, + { nvd9_gr_init_sm_0 }, + { nvd7_gr_init_pes_0 }, + { nvd7_gr_init_wwdx_0 }, + { nvd7_gr_init_cbm_0 }, + { nvc0_gr_init_be_0 }, + { nvd9_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +#include "fuc/hubnvd7.fuc3.h" + +struct nvc0_gr_ucode +nvd7_gr_fecs_ucode = { + .code.data = nvd7_grhub_code, + .code.size = sizeof(nvd7_grhub_code), + .data.data = nvd7_grhub_data, + .data.size = sizeof(nvd7_grhub_data), +}; + +#include "fuc/gpcnvd7.fuc3.h" + +struct nvc0_gr_ucode +nvd7_gr_gpccs_ucode = { + .code.data = nvd7_grgpc_code, + .code.size = sizeof(nvd7_grgpc_code), + .data.data = nvd7_grgpc_data, + .data.size = sizeof(nvd7_grgpc_data), +}; + +struct nouveau_oclass * +nvd7_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xd7), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nvc0_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nvd7_grctx_oclass, + .sclass = nvc8_gr_sclass, + .mmio = nvd7_gr_pack_mmio, + .fecs.ucode = &nvd7_gr_fecs_ucode, + .gpccs.ucode = &nvd7_gr_gpccs_ucode, + .ppc_nr = 1, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c new file mode 100644 index 000000000000..25f5905a2b78 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c @@ -0,0 +1,191 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nvd9_gr_init_pd_0[] = { + { 0x406024, 1, 0x04, 0x00000000 }, + { 0x4064f0, 3, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x00002834 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_prop_0[] = { + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x4184a0, 3, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_gpm_0[] = { + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c64, 2, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418cb4, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_gpc_unk_1[] = { + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 2, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 2, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000003 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_tex_0[] = { + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_gr_init_pe_0[] = { + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419810, 1, 0x04, 0x00000000 }, + { 0x419814, 1, 0x04, 0x00000004 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x0000a918 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419880, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_gr_init_wwdx_0[] = { + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + { 0x419bf8, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvd9_gr_init_tpccs_1[] = { + { 0x419d2c, 1, 0x04, 0x00000000 }, + { 0x419d48, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x02001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0e063818 }, + { 0x419ecc, 1, 0x04, 0x0e060e06 }, + { 0x419ed0, 1, 0x04, 0x00003818 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvd9_gr_init_fe_1[] = { + { 0x40402c, 1, 0x04, 0x00000000 }, + { 0x4040f0, 1, 0x04, 0x00000000 }, + { 0x404174, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvd9_gr_pack_mmio[] = { + { nvc0_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvd9_gr_init_pd_0 }, + { nvd9_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvd9_gr_init_prop_0 }, + { nvc1_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvd9_gr_init_gpm_0 }, + { nvd9_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nvc0_gr_init_tpccs_0 }, + { nvd9_gr_init_tex_0 }, + { nvd9_gr_init_pe_0 }, + { nvc0_gr_init_l1c_0 }, + { nvd9_gr_init_wwdx_0 }, + { nvd9_gr_init_tpccs_1 }, + { nvc0_gr_init_mpc_0 }, + { nvd9_gr_init_sm_0 }, + { nvc0_gr_init_be_0 }, + { nvd9_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nouveau_oclass * +nvd9_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xd9), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nvc0_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nvd9_grctx_oclass, + .sclass = nvc8_gr_sclass, + .mmio = nvd9_gr_pack_mmio, + .fecs.ucode = &nvc0_gr_fecs_ucode, + .gpccs.ucode = &nvc0_gr_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c new file mode 100644 index 000000000000..f03ef38e8157 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c @@ -0,0 +1,347 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nve4_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa040, &nouveau_object_ofuncs }, + { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nve4_gr_init_main_0[] = { + { 0x400080, 1, 0x04, 0x003083c2 }, + { 0x400088, 1, 0x04, 0x0001ffe7 }, + { 0x40008c, 1, 0x04, 0x00000000 }, + { 0x400090, 1, 0x04, 0x00000030 }, + { 0x40013c, 1, 0x04, 0x003901f7 }, + { 0x400140, 1, 0x04, 0x00000100 }, + { 0x400144, 1, 0x04, 0x00000000 }, + { 0x400148, 1, 0x04, 0x00000110 }, + { 0x400138, 1, 0x04, 0x00000000 }, + { 0x400130, 2, 0x04, 0x00000000 }, + { 0x400124, 1, 0x04, 0x00000002 }, + {} +}; + +static const struct nvc0_gr_init +nve4_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x0000ff34 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_gr_init_sked_0[] = { + { 0x407010, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_gr_init_cwd_0[] = { + { 0x405b50, 1, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_gr_init_gpc_unk_1[] = { + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 2, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 2, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000060 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nve4_gr_init_tpccs_0[] = { + { 0x419d0c, 1, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + {} +}; + +const struct nvc0_gr_init +nve4_gr_init_pe_0[] = { + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x419850, 1, 0x04, 0x00000004 }, + { 0x419854, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nve4_gr_init_l1c_0[] = { + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x01000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00b08bea }, + { 0x419c84, 1, 0x04, 0x00010384 }, + { 0x419cbc, 1, 0x04, 0x28137646 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x00020232 }, + {} +}; + +static const struct nvc0_gr_init +nve4_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ee4, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00000000 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f74, 1, 0x04, 0x00000555 }, + {} +}; + +const struct nvc0_gr_init +nve4_gr_init_be_0[] = { + { 0x40880c, 1, 0x04, 0x00000000 }, + { 0x408850, 1, 0x04, 0x00000004 }, + { 0x408910, 9, 0x04, 0x00000000 }, + { 0x408950, 1, 0x04, 0x00000000 }, + { 0x408954, 1, 0x04, 0x0000ffff }, + { 0x408958, 1, 0x04, 0x00000034 }, + { 0x408984, 1, 0x04, 0x00000000 }, + { 0x408988, 1, 0x04, 0x08040201 }, + { 0x40898c, 1, 0x04, 0x80402010 }, + {} +}; + +const struct nvc0_gr_pack +nve4_gr_pack_mmio[] = { + { nve4_gr_init_main_0 }, + { nvc0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvd9_gr_init_pd_0 }, + { nve4_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nve4_gr_init_sked_0 }, + { nve4_gr_init_cwd_0 }, + { nvd9_gr_init_prop_0 }, + { nvc1_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvd9_gr_init_gpm_0 }, + { nve4_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nve4_gr_init_tpccs_0 }, + { nvd9_gr_init_tex_0 }, + { nve4_gr_init_pe_0 }, + { nve4_gr_init_l1c_0 }, + { nvc0_gr_init_mpc_0 }, + { nve4_gr_init_sm_0 }, + { nvd7_gr_init_pes_0 }, + { nvd7_gr_init_wwdx_0 }, + { nvd7_gr_init_cbm_0 }, + { nve4_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +int +nve4_gr_init(struct nouveau_object *object) +{ + struct nvc0_gr_oclass *oclass = (void *)object->oclass; + struct nvc0_gr_priv *priv = (void *)object; + struct nouveau_pmu *pmu = nouveau_pmu(priv); + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + u32 data[TPC_MAX / 8] = {}; + u8 tpcnr[GPC_MAX]; + int gpc, tpc, rop; + int ret, i; + + if (pmu) + pmu->pgob(pmu, false); + + ret = nouveau_gr_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); + nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + + nvc0_gr_mmio(priv, oclass->mmio); + + nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); + + memset(data, 0x00, sizeof(data)); + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + data[i / 8] |= tpc << ((i % 8) * 4); + } + + nv_wr32(priv, GPC_BCAST(0x0980), data[0]); + nv_wr32(priv, GPC_BCAST(0x0984), data[1]); + nv_wr32(priv, GPC_BCAST(0x0988), data[2]); + nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0914), + priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | + priv->tpc_total); + nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); + + nv_wr32(priv, 0x400500, 0x00010001); + + nv_wr32(priv, 0x400100, 0xffffffff); + nv_wr32(priv, 0x40013c, 0xffffffff); + + nv_wr32(priv, 0x409ffc, 0x00000000); + nv_wr32(priv, 0x409c14, 0x00003e3e); + nv_wr32(priv, 0x409c24, 0x000f0001); + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(priv, 0x408030, 0xc0000000); + nv_wr32(priv, 0x404490, 0xc0000000); + nv_wr32(priv, 0x406018, 0xc0000000); + nv_wr32(priv, 0x407020, 0x40000000); + nv_wr32(priv, 0x405840, 0xc0000000); + nv_wr32(priv, 0x405844, 0x00ffffff); + nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); + nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + } + nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + } + + for (rop = 0; rop < priv->rop_nr; rop++) { + nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + } + + nv_wr32(priv, 0x400108, 0xffffffff); + nv_wr32(priv, 0x400138, 0xffffffff); + nv_wr32(priv, 0x400118, 0xffffffff); + nv_wr32(priv, 0x400130, 0xffffffff); + nv_wr32(priv, 0x40011c, 0xffffffff); + nv_wr32(priv, 0x400134, 0xffffffff); + + nv_wr32(priv, 0x400054, 0x34ce3464); + + nvc0_gr_zbc_init(priv); + + return nvc0_gr_init_ctxctl(priv); +} + +#include "fuc/hubnve0.fuc3.h" + +static struct nvc0_gr_ucode +nve4_gr_fecs_ucode = { + .code.data = nve0_grhub_code, + .code.size = sizeof(nve0_grhub_code), + .data.data = nve0_grhub_data, + .data.size = sizeof(nve0_grhub_data), +}; + +#include "fuc/gpcnve0.fuc3.h" + +static struct nvc0_gr_ucode +nve4_gr_gpccs_ucode = { + .code.data = nve0_grgpc_code, + .code.size = sizeof(nve0_grgpc_code), + .data.data = nve0_grgpc_data, + .data.size = sizeof(nve0_grgpc_data), +}; + +struct nouveau_oclass * +nve4_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xe4), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nve4_gr_init, + .fini = _nouveau_gr_fini, + }, + .cclass = &nve4_grctx_oclass, + .sclass = nve4_gr_sclass, + .mmio = nve4_gr_pack_mmio, + .fecs.ucode = &nve4_gr_fecs_ucode, + .gpccs.ucode = &nve4_gr_gpccs_ucode, + .ppc_nr = 1, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c new file mode 100644 index 000000000000..84d4456503c2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c @@ -0,0 +1,245 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" +#include "ctxnvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +struct nouveau_oclass +nvf0_gr_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa140, &nouveau_object_ofuncs }, + { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds }, + { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds }, + {} +}; + +/******************************************************************************* + * PGRAPH register lists + ******************************************************************************/ + +const struct nvc0_gr_init +nvf0_gr_init_fe_0[] = { + { 0x40415c, 1, 0x04, 0x00000000 }, + { 0x404170, 1, 0x04, 0x00000000 }, + { 0x4041b4, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvf0_gr_init_ds_0[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x0000ff00 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvf0_gr_init_sked_0[] = { + { 0x407010, 1, 0x04, 0x00000000 }, + { 0x407040, 1, 0x04, 0x80440424 }, + { 0x407048, 1, 0x04, 0x0000000a }, + {} +}; + +const struct nvc0_gr_init +nvf0_gr_init_cwd_0[] = { + { 0x405b44, 1, 0x04, 0x00000000 }, + { 0x405b50, 1, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvf0_gr_init_gpc_unk_1[] = { + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 2, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000400 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 2, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000000 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvf0_gr_init_tex_0[] = { + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419aec, 1, 0x04, 0x00000000 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + { 0x419aa8, 2, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_init +nvf0_gr_init_l1c_0[] = { + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x01000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00b08bea }, + { 0x419c84, 1, 0x04, 0x00010384 }, + { 0x419cbc, 1, 0x04, 0x281b3646 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x00020230 }, + { 0x419ccc, 2, 0x04, 0x00000000 }, + {} +}; + +const struct nvc0_gr_init +nvf0_gr_init_sm_0[] = { + { 0x419e00, 1, 0x04, 0x00000080 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ee4, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00000000 }, + { 0x419eb4, 1, 0x04, 0x00000000 }, + { 0x419ebc, 2, 0x04, 0x00000000 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419ed0, 1, 0x04, 0x00003234 }, + { 0x419f74, 1, 0x04, 0x00015555 }, + { 0x419f80, 4, 0x04, 0x00000000 }, + {} +}; + +static const struct nvc0_gr_pack +nvf0_gr_pack_mmio[] = { + { nve4_gr_init_main_0 }, + { nvf0_gr_init_fe_0 }, + { nvc0_gr_init_pri_0 }, + { nvc0_gr_init_rstr2d_0 }, + { nvd9_gr_init_pd_0 }, + { nvf0_gr_init_ds_0 }, + { nvc0_gr_init_scc_0 }, + { nvf0_gr_init_sked_0 }, + { nvf0_gr_init_cwd_0 }, + { nvd9_gr_init_prop_0 }, + { nvc1_gr_init_gpc_unk_0 }, + { nvc0_gr_init_setup_0 }, + { nvc0_gr_init_crstr_0 }, + { nvc1_gr_init_setup_1 }, + { nvc0_gr_init_zcull_0 }, + { nvd9_gr_init_gpm_0 }, + { nvf0_gr_init_gpc_unk_1 }, + { nvc0_gr_init_gcc_0 }, + { nve4_gr_init_tpccs_0 }, + { nvf0_gr_init_tex_0 }, + { nve4_gr_init_pe_0 }, + { nvf0_gr_init_l1c_0 }, + { nvc0_gr_init_mpc_0 }, + { nvf0_gr_init_sm_0 }, + { nvd7_gr_init_pes_0 }, + { nvd7_gr_init_wwdx_0 }, + { nvd7_gr_init_cbm_0 }, + { nve4_gr_init_be_0 }, + { nvc0_gr_init_fe_1 }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +int +nvf0_gr_fini(struct nouveau_object *object, bool suspend) +{ + struct nvc0_gr_priv *priv = (void *)object; + static const struct { + u32 addr; + u32 data; + } magic[] = { + { 0x020520, 0xfffffffc }, + { 0x020524, 0xfffffffe }, + { 0x020524, 0xfffffffc }, + { 0x020524, 0xfffffff8 }, + { 0x020524, 0xffffffe0 }, + { 0x020530, 0xfffffffe }, + { 0x02052c, 0xfffffffa }, + { 0x02052c, 0xfffffff0 }, + { 0x02052c, 0xffffffc0 }, + { 0x02052c, 0xffffff00 }, + { 0x02052c, 0xfffffc00 }, + { 0x02052c, 0xfffcfc00 }, + { 0x02052c, 0xfff0fc00 }, + { 0x02052c, 0xff80fc00 }, + { 0x020528, 0xfffffffe }, + { 0x020528, 0xfffffffc }, + }; + int i; + + nv_mask(priv, 0x000200, 0x08001000, 0x00000000); + nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); + for (i = 0; i < ARRAY_SIZE(magic); i++) { + nv_wr32(priv, magic[i].addr, magic[i].data); + nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); + } + + return nouveau_gr_fini(&priv->base, suspend); +} + +#include "fuc/hubnvf0.fuc3.h" + +struct nvc0_gr_ucode +nvf0_gr_fecs_ucode = { + .code.data = nvf0_grhub_code, + .code.size = sizeof(nvf0_grhub_code), + .data.data = nvf0_grhub_data, + .data.size = sizeof(nvf0_grhub_data), +}; + +#include "fuc/gpcnvf0.fuc3.h" + +struct nvc0_gr_ucode +nvf0_gr_gpccs_ucode = { + .code.data = nvf0_grgpc_code, + .code.size = sizeof(nvf0_grgpc_code), + .data.data = nvf0_grgpc_data, + .data.size = sizeof(nvf0_grgpc_data), +}; + +struct nouveau_oclass * +nvf0_gr_oclass = &(struct nvc0_gr_oclass) { + .base.handle = NV_ENGINE(GR, 0xf0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_gr_ctor, + .dtor = nvc0_gr_dtor, + .init = nve4_gr_init, + .fini = nvf0_gr_fini, + }, + .cclass = &nvf0_grctx_oclass, + .sclass = nvf0_gr_sclass, + .mmio = nvf0_gr_pack_mmio, + .fecs.ucode = &nvf0_gr_fecs_ucode, + .gpccs.ucode = &nvf0_gr_gpccs_ucode, + .ppc_nr = 2, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h new file mode 100644 index 000000000000..de69c5995edd --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h @@ -0,0 +1,274 @@ +#ifndef __NOUVEAU_GR_REGS_H__ +#define __NOUVEAU_GR_REGS_H__ + +#define NV04_PGRAPH_DEBUG_0 0x00400080 +#define NV04_PGRAPH_DEBUG_1 0x00400084 +#define NV04_PGRAPH_DEBUG_2 0x00400088 +#define NV04_PGRAPH_DEBUG_3 0x0040008c +#define NV10_PGRAPH_DEBUG_4 0x00400090 +#define NV03_PGRAPH_INTR 0x00400100 +#define NV03_PGRAPH_NSTATUS 0x00400104 +# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) +# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) +# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) +# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) +# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) +# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) +# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) +# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) +#define NV03_PGRAPH_NSOURCE 0x00400108 +# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0) +# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1) +# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2) +# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3) +# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4) +# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5) +# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6) +# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7) +# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8) +# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9) +# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) +# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) +# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) +# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) +# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) +# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) +# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) +# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) +# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) +#define NV03_PGRAPH_INTR_EN 0x00400140 +#define NV40_PGRAPH_INTR_EN 0x0040013C +# define NV_PGRAPH_INTR_NOTIFY (1<<0) +# define NV_PGRAPH_INTR_MISSING_HW (1<<4) +# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) +# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) +# define NV_PGRAPH_INTR_ERROR (1<<20) +#define NV10_PGRAPH_CTX_CONTROL 0x00400144 +#define NV10_PGRAPH_CTX_USER 0x00400148 +#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i)) +#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 +#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \ + + 0x4*(i) + 0x20*(j)) +#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 +#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 +#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C +#define NV04_PGRAPH_CTX_CONTROL 0x00400170 +#define NV04_PGRAPH_CTX_USER 0x00400174 +#define NV04_PGRAPH_CTX_CACHE1 0x00400180 +#define NV03_PGRAPH_CTX_CONTROL 0x00400190 +#define NV03_PGRAPH_CTX_USER 0x00400194 +#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 +#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 +#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 +#define NV40_PGRAPH_CTXCTL_0304 0x00400304 +#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff +#define NV40_PGRAPH_CTXCTL_0310 0x00400310 +#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 +#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 +#define NV40_PGRAPH_CTXCTL_030C 0x0040030c +#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 +#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 +#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c +#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 +#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF +#define NV40_PGRAPH_CTXCTL_NEXT 0x00400330 +#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff +#define NV50_PGRAPH_CTXCTL_CUR 0x0040032c +#define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000 +#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff +#define NV50_PGRAPH_CTXCTL_NEXT 0x00400330 +#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff +#define NV03_PGRAPH_ABS_X_RAM 0x00400400 +#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 +#define NV03_PGRAPH_X_MISC 0x00400500 +#define NV03_PGRAPH_Y_MISC 0x00400504 +#define NV04_PGRAPH_VALID1 0x00400508 +#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C +#define NV04_PGRAPH_MISC24_0 0x00400510 +#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 +#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 +#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C +#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 +#define NV03_PGRAPH_CLIPX_0 0x00400524 +#define NV03_PGRAPH_CLIPX_1 0x00400528 +#define NV03_PGRAPH_CLIPY_0 0x0040052C +#define NV03_PGRAPH_CLIPY_1 0x00400530 +#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 +#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 +#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C +#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 +#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 +#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 +#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 +#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 +#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 +#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C +#define NV04_PGRAPH_MISC24_1 0x00400570 +#define NV04_PGRAPH_MISC24_2 0x00400574 +#define NV04_PGRAPH_VALID2 0x00400578 +#define NV04_PGRAPH_PASSTHRU_0 0x0040057C +#define NV04_PGRAPH_PASSTHRU_1 0x00400580 +#define NV04_PGRAPH_PASSTHRU_2 0x00400584 +#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 +#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C +#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 +#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 +#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 +#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C +#define NV04_PGRAPH_FORMAT_0 0x004005A8 +#define NV04_PGRAPH_FORMAT_1 0x004005AC +#define NV04_PGRAPH_FILTER_0 0x004005B0 +#define NV04_PGRAPH_FILTER_1 0x004005B4 +#define NV03_PGRAPH_MONO_COLOR0 0x00400600 +#define NV04_PGRAPH_ROP3 0x00400604 +#define NV04_PGRAPH_BETA_AND 0x00400608 +#define NV04_PGRAPH_BETA_PREMULT 0x0040060C +#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 +#define NV04_PGRAPH_FORMATS 0x00400618 +#define NV10_PGRAPH_DEBUG_2 0x00400620 +#define NV04_PGRAPH_BOFFSET0 0x00400640 +#define NV04_PGRAPH_BOFFSET1 0x00400644 +#define NV04_PGRAPH_BOFFSET2 0x00400648 +#define NV04_PGRAPH_BOFFSET3 0x0040064C +#define NV04_PGRAPH_BOFFSET4 0x00400650 +#define NV04_PGRAPH_BOFFSET5 0x00400654 +#define NV04_PGRAPH_BBASE0 0x00400658 +#define NV04_PGRAPH_BBASE1 0x0040065C +#define NV04_PGRAPH_BBASE2 0x00400660 +#define NV04_PGRAPH_BBASE3 0x00400664 +#define NV04_PGRAPH_BBASE4 0x00400668 +#define NV04_PGRAPH_BBASE5 0x0040066C +#define NV04_PGRAPH_BPITCH0 0x00400670 +#define NV04_PGRAPH_BPITCH1 0x00400674 +#define NV04_PGRAPH_BPITCH2 0x00400678 +#define NV04_PGRAPH_BPITCH3 0x0040067C +#define NV04_PGRAPH_BPITCH4 0x00400680 +#define NV04_PGRAPH_BLIMIT0 0x00400684 +#define NV04_PGRAPH_BLIMIT1 0x00400688 +#define NV04_PGRAPH_BLIMIT2 0x0040068C +#define NV04_PGRAPH_BLIMIT3 0x00400690 +#define NV04_PGRAPH_BLIMIT4 0x00400694 +#define NV04_PGRAPH_BLIMIT5 0x00400698 +#define NV04_PGRAPH_BSWIZZLE2 0x0040069C +#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 +#define NV03_PGRAPH_STATUS 0x004006B0 +#define NV04_PGRAPH_STATUS 0x00400700 +# define NV40_PGRAPH_STATUS_SYNC_STALL 0x00004000 +#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 +#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 +#define NV04_PGRAPH_SURFACE 0x0040070C +#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C +#define NV04_PGRAPH_STATE 0x00400710 +#define NV10_PGRAPH_SURFACE 0x00400710 +#define NV04_PGRAPH_NOTIFY 0x00400714 +#define NV10_PGRAPH_STATE 0x00400714 +#define NV10_PGRAPH_NOTIFY 0x00400718 + +#define NV04_PGRAPH_FIFO 0x00400720 + +#define NV04_PGRAPH_BPIXEL 0x00400724 +#define NV10_PGRAPH_RDI_INDEX 0x00400750 +#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 +#define NV10_PGRAPH_RDI_DATA 0x00400754 +#define NV04_PGRAPH_DMA_PITCH 0x00400760 +#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760 +#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 +#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 +#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 +#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768 +#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c +#define NV10_PGRAPH_DMA_PITCH 0x00400770 +#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 +#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 +#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 +#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 +#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 +#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 +#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 +#define NV04_PGRAPH_PATT_COLOR0 0x00400800 +#define NV04_PGRAPH_PATT_COLOR1 0x00400804 +#define NV04_PGRAPH_PATTERN 0x00400808 +#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 +#define NV04_PGRAPH_CHROMA 0x00400814 +#define NV04_PGRAPH_CONTROL0 0x00400818 +#define NV04_PGRAPH_CONTROL1 0x0040081C +#define NV04_PGRAPH_CONTROL2 0x00400820 +#define NV04_PGRAPH_BLEND 0x00400824 +#define NV04_PGRAPH_STORED_FMT 0x00400830 +#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 +#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16)) +#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16)) +#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16)) +#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16)) +#define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i)) +#define NV41_PGRAPH_ZCOMP0(i) (0x004009c0 + 4*(i)) +#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) +#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) +#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) +#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) +#define NV04_PGRAPH_U_RAM 0x00400D00 +#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16)) +#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16)) +#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16)) +#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16)) +#define NV04_PGRAPH_V_RAM 0x00400D40 +#define NV04_PGRAPH_W_RAM 0x00400D80 +#define NV47_PGRAPH_ZCOMP0(i) (0x00400e00 + 4*(i)) +#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 +#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 +#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 +#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C +#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 +#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 +#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 +#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C +#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 +#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 +#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 +#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C +#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 +#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 +#define NV10_PGRAPH_XFMODE0 0x00400F40 +#define NV10_PGRAPH_XFMODE1 0x00400F44 +#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 +#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C +#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 +#define NV10_PGRAPH_PIPE_DATA 0x00400F54 +#define NV04_PGRAPH_DMA_START_0 0x00401000 +#define NV04_PGRAPH_DMA_START_1 0x00401004 +#define NV04_PGRAPH_DMA_LENGTH 0x00401008 +#define NV04_PGRAPH_DMA_MISC 0x0040100C +#define NV04_PGRAPH_DMA_DATA_0 0x00401020 +#define NV04_PGRAPH_DMA_DATA_1 0x00401024 +#define NV04_PGRAPH_DMA_RM 0x00401030 +#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 +#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 +#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 +#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C +#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 +#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 +#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 +#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C +#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 +#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 +#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 +#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 +#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C +#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 +#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 +#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 +#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C +#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 +#define NV47_PGRAPH_ZCOMP1(i) (0x004068c0 + 4*(i)) +#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) +#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) +#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) +#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) +#define NV40_PGRAPH_ZCOMP1(i) (0x00406980 + 4*(i)) +#define NV41_PGRAPH_ZCOMP1(i) (0x004069c0 + 4*(i)) + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild deleted file mode 100644 index fd56e979344b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild +++ /dev/null @@ -1,36 +0,0 @@ -nvkm-y += nvkm/engine/graph/ctxnv40.o -nvkm-y += nvkm/engine/graph/ctxnv50.o -nvkm-y += nvkm/engine/graph/ctxnvc0.o -nvkm-y += nvkm/engine/graph/ctxnvc1.o -nvkm-y += nvkm/engine/graph/ctxnvc4.o -nvkm-y += nvkm/engine/graph/ctxnvc8.o -nvkm-y += nvkm/engine/graph/ctxnvd7.o -nvkm-y += nvkm/engine/graph/ctxnvd9.o -nvkm-y += nvkm/engine/graph/ctxnve4.o -nvkm-y += nvkm/engine/graph/ctxgk20a.o -nvkm-y += nvkm/engine/graph/ctxnvf0.o -nvkm-y += nvkm/engine/graph/ctxgk110b.o -nvkm-y += nvkm/engine/graph/ctxnv108.o -nvkm-y += nvkm/engine/graph/ctxgm107.o -nvkm-y += nvkm/engine/graph/nv04.o -nvkm-y += nvkm/engine/graph/nv10.o -nvkm-y += nvkm/engine/graph/nv20.o -nvkm-y += nvkm/engine/graph/nv25.o -nvkm-y += nvkm/engine/graph/nv2a.o -nvkm-y += nvkm/engine/graph/nv30.o -nvkm-y += nvkm/engine/graph/nv34.o -nvkm-y += nvkm/engine/graph/nv35.o -nvkm-y += nvkm/engine/graph/nv40.o -nvkm-y += nvkm/engine/graph/nv50.o -nvkm-y += nvkm/engine/graph/nvc0.o -nvkm-y += nvkm/engine/graph/nvc1.o -nvkm-y += nvkm/engine/graph/nvc4.o -nvkm-y += nvkm/engine/graph/nvc8.o -nvkm-y += nvkm/engine/graph/nvd7.o -nvkm-y += nvkm/engine/graph/nvd9.o -nvkm-y += nvkm/engine/graph/nve4.o -nvkm-y += nvkm/engine/graph/gk20a.o -nvkm-y += nvkm/engine/graph/nvf0.o -nvkm-y += nvkm/engine/graph/gk110b.o -nvkm-y += nvkm/engine/graph/nv108.o -nvkm-y += nvkm/engine/graph/gm107.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h deleted file mode 100644 index e1947013d3bc..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h +++ /dev/null @@ -1,129 +0,0 @@ -#ifndef __NOUVEAU_GRCTX_H__ -#define __NOUVEAU_GRCTX_H__ - -struct nouveau_grctx { - struct nouveau_device *device; - - enum { - NOUVEAU_GRCTX_PROG, - NOUVEAU_GRCTX_VALS - } mode; - void *data; - - u32 ctxprog_max; - u32 ctxprog_len; - u32 ctxprog_reg; - int ctxprog_label[32]; - u32 ctxvals_pos; - u32 ctxvals_base; -}; - -static inline void -cp_out(struct nouveau_grctx *ctx, u32 inst) -{ - u32 *ctxprog = ctx->data; - - if (ctx->mode != NOUVEAU_GRCTX_PROG) - return; - - BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); - ctxprog[ctx->ctxprog_len++] = inst; -} - -static inline void -cp_lsr(struct nouveau_grctx *ctx, u32 val) -{ - cp_out(ctx, CP_LOAD_SR | val); -} - -static inline void -cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length) -{ - ctx->ctxprog_reg = (reg - 0x00400000) >> 2; - - ctx->ctxvals_base = ctx->ctxvals_pos; - ctx->ctxvals_pos = ctx->ctxvals_base + length; - - if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) { - cp_lsr(ctx, length); - length = 0; - } - - cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg); -} - -static inline void -cp_name(struct nouveau_grctx *ctx, int name) -{ - u32 *ctxprog = ctx->data; - int i; - - if (ctx->mode != NOUVEAU_GRCTX_PROG) - return; - - ctx->ctxprog_label[name] = ctx->ctxprog_len; - for (i = 0; i < ctx->ctxprog_len; i++) { - if ((ctxprog[i] & 0xfff00000) != 0xff400000) - continue; - if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT)) - continue; - ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | - (ctx->ctxprog_len << CP_BRA_IP_SHIFT); - } -} - -static inline void -_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) -{ - int ip = 0; - - if (mod != 2) { - ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT; - if (ip == 0) - ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); - } - - cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | - (state ? 0 : CP_BRA_IF_CLEAR)); -} -#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) -#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) -#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) - -static inline void -_cp_wait(struct nouveau_grctx *ctx, int flag, int state) -{ - cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); -} -#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) - -static inline void -_cp_set(struct nouveau_grctx *ctx, int flag, int state) -{ - cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); -} -#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) - -static inline void -cp_pos(struct nouveau_grctx *ctx, int offset) -{ - ctx->ctxvals_pos = offset; - ctx->ctxvals_base = ctx->ctxvals_pos; - - cp_lsr(ctx, ctx->ctxvals_pos); - cp_out(ctx, CP_SET_CONTEXT_POINTER); -} - -static inline void -gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val) -{ - if (ctx->mode != NOUVEAU_GRCTX_VALS) - return; - - reg = (reg - 0x00400000) / 4; - reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; - - nv_wo32(ctx->data, reg * 4, val); -} - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c deleted file mode 100644 index 3adb7fe91772..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -gk110b_grctx_init_sm_0[] = { - { 0x419e04, 1, 0x04, 0x00000000 }, - { 0x419e08, 1, 0x04, 0x0000001d }, - { 0x419e0c, 1, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00001c02 }, - { 0x419e44, 1, 0x04, 0x0013eff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000007f }, - { 0x419e50, 2, 0x04, 0x00000000 }, - { 0x419e58, 1, 0x04, 0x00000001 }, - { 0x419e5c, 3, 0x04, 0x00000000 }, - { 0x419e68, 1, 0x04, 0x00000002 }, - { 0x419e6c, 12, 0x04, 0x00000000 }, - { 0x419eac, 1, 0x04, 0x00001f8f }, - { 0x419eb0, 1, 0x04, 0x0db00d2f }, - { 0x419eb8, 1, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x0001304f }, - { 0x419f30, 4, 0x04, 0x00000000 }, - { 0x419f40, 1, 0x04, 0x00000018 }, - { 0x419f44, 3, 0x04, 0x00000000 }, - { 0x419f58, 1, 0x04, 0x00000000 }, - { 0x419f70, 1, 0x04, 0x00006300 }, - { 0x419f78, 1, 0x04, 0x000000eb }, - { 0x419f7c, 1, 0x04, 0x00000404 }, - {} -}; - -static const struct nvc0_graph_pack -gk110b_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nvf0_grctx_init_tex_0 }, - { nvf0_grctx_init_mpc_0 }, - { nvf0_grctx_init_l1c_0 }, - { gk110b_grctx_init_sm_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -struct nouveau_oclass * -gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xf1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nvf0_grctx_pack_hub, - .gpc = nvf0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = gk110b_grctx_pack_tpc, - .ppc = nvf0_grctx_pack_ppc, - .icmd = nvf0_grctx_pack_icmd, - .mthd = nvf0_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, - .bundle_size = 0x3000, - .bundle_min_gpm_fifo_depth = 0x180, - .bundle_token_limit = 0x600, - .pagepool = nve4_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x7ff, - .alpha_nr = 0x648, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c deleted file mode 100644 index 36fc9831cc93..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "ctxnvc0.h" - -static const struct nvc0_graph_pack -gk20a_grctx_pack_mthd[] = { - { nve4_grctx_init_a097_0, 0xa297 }, - { nvc0_grctx_init_902d_0, 0x902d }, - {} -}; - -struct nouveau_oclass * -gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nve4_grctx_pack_hub, - .gpc = nve4_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nve4_grctx_pack_tpc, - .ppc = nve4_grctx_pack_ppc, - .icmd = nve4_grctx_pack_icmd, - .mthd = gk20a_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, - .bundle_size = 0x1800, - .bundle_min_gpm_fifo_depth = 0x62, - .bundle_token_limit = 0x100, - .pagepool = nve4_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, - .attrib_nr_max = 0x240, - .attrib_nr = 0x240, - .alpha_nr_max = 0x648 + (0x648 / 2), - .alpha_nr = 0x648, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c deleted file mode 100644 index 62e918b9fa81..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c +++ /dev/null @@ -1,1032 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -gm107_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x0000b1, 2, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000a8, 1, 0x01, 0x0000ffff }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002f2, 2, 0x01, 0x00000001 }, - { 0x0002f5, 1, 0x01, 0x00000001 }, - { 0x0002f7, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x0000de, 1, 0x01, 0x00000001 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000383, 1, 0x01, 0x00000011 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x0005d0, 1, 0x01, 0x20181008 }, - { 0x0005d1, 1, 0x01, 0x40383028 }, - { 0x0005d2, 1, 0x01, 0x60585048 }, - { 0x0005d3, 1, 0x01, 0x80787068 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000550, 32, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x000595, 1, 0x01, 0x00400040 }, - { 0x000596, 1, 0x01, 0x00000492 }, - { 0x000597, 1, 0x01, 0x08080203 }, - { 0x0005ad, 1, 0x01, 0x00000008 }, - { 0x000598, 1, 0x01, 0x00020001 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000662, 1, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x000a0d, 1, 0x01, 0x00000006 }, - { 0x00097d, 1, 0x01, 0x0000000c }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000687, 1, 0x01, 0x003fffff }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00400008 }, - { 0x000841, 1, 0x01, 0x08000080 }, - { 0x000842, 1, 0x01, 0x00400008 }, - { 0x000843, 1, 0x01, 0x08000080 }, - { 0x000818, 8, 0x01, 0x00000000 }, - { 0x000848, 16, 0x01, 0x00000000 }, - { 0x000738, 1, 0x01, 0x00000000 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000008 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000818, 8, 0x01, 0x00000000 }, - { 0x000848, 16, 0x01, 0x00000000 }, - { 0x000738, 1, 0x01, 0x00000000 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_pack -gm107_grctx_pack_icmd[] = { - { gm107_grctx_init_icmd_0 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_b097_0[] = { - { 0x000800, 8, 0x40, 0x00000000 }, - { 0x000804, 8, 0x40, 0x00000000 }, - { 0x000808, 8, 0x40, 0x00000400 }, - { 0x00080c, 8, 0x40, 0x00000300 }, - { 0x000810, 1, 0x04, 0x000000cf }, - { 0x000850, 7, 0x40, 0x00000000 }, - { 0x000814, 8, 0x40, 0x00000040 }, - { 0x000818, 8, 0x40, 0x00000001 }, - { 0x00081c, 8, 0x40, 0x00000000 }, - { 0x000820, 8, 0x40, 0x00000000 }, - { 0x001c00, 16, 0x10, 0x00000000 }, - { 0x001c04, 16, 0x10, 0x00000000 }, - { 0x001c08, 16, 0x10, 0x00000000 }, - { 0x001c0c, 16, 0x10, 0x00000000 }, - { 0x001d00, 16, 0x10, 0x00000000 }, - { 0x001d04, 16, 0x10, 0x00000000 }, - { 0x001d08, 16, 0x10, 0x00000000 }, - { 0x001d0c, 16, 0x10, 0x00000000 }, - { 0x001f00, 16, 0x08, 0x00000000 }, - { 0x001f04, 16, 0x08, 0x00000000 }, - { 0x001f80, 16, 0x08, 0x00000000 }, - { 0x001f84, 16, 0x08, 0x00000000 }, - { 0x002000, 1, 0x04, 0x00000000 }, - { 0x002040, 1, 0x04, 0x00000011 }, - { 0x002080, 1, 0x04, 0x00000020 }, - { 0x0020c0, 1, 0x04, 0x00000030 }, - { 0x002100, 1, 0x04, 0x00000040 }, - { 0x002140, 1, 0x04, 0x00000051 }, - { 0x00200c, 6, 0x40, 0x00000001 }, - { 0x002010, 1, 0x04, 0x00000000 }, - { 0x002050, 1, 0x04, 0x00000000 }, - { 0x002090, 1, 0x04, 0x00000001 }, - { 0x0020d0, 1, 0x04, 0x00000002 }, - { 0x002110, 1, 0x04, 0x00000003 }, - { 0x002150, 1, 0x04, 0x00000004 }, - { 0x000380, 4, 0x20, 0x00000000 }, - { 0x000384, 4, 0x20, 0x00000000 }, - { 0x000388, 4, 0x20, 0x00000000 }, - { 0x00038c, 4, 0x20, 0x00000000 }, - { 0x000700, 4, 0x10, 0x00000000 }, - { 0x000704, 4, 0x10, 0x00000000 }, - { 0x000708, 4, 0x10, 0x00000000 }, - { 0x002800, 128, 0x04, 0x00000000 }, - { 0x000a00, 16, 0x20, 0x00000000 }, - { 0x000a04, 16, 0x20, 0x00000000 }, - { 0x000a08, 16, 0x20, 0x00000000 }, - { 0x000a0c, 16, 0x20, 0x00000000 }, - { 0x000a10, 16, 0x20, 0x00000000 }, - { 0x000a14, 16, 0x20, 0x00000000 }, - { 0x000c00, 16, 0x10, 0x00000000 }, - { 0x000c04, 16, 0x10, 0x00000000 }, - { 0x000c08, 16, 0x10, 0x00000000 }, - { 0x000c0c, 16, 0x10, 0x3f800000 }, - { 0x000d00, 8, 0x08, 0xffff0000 }, - { 0x000d04, 8, 0x08, 0xffff0000 }, - { 0x000e00, 16, 0x10, 0x00000000 }, - { 0x000e04, 16, 0x10, 0xffff0000 }, - { 0x000e08, 16, 0x10, 0xffff0000 }, - { 0x000d40, 4, 0x08, 0x00000000 }, - { 0x000d44, 4, 0x08, 0x00000000 }, - { 0x001e00, 8, 0x20, 0x00000001 }, - { 0x001e04, 8, 0x20, 0x00000001 }, - { 0x001e08, 8, 0x20, 0x00000002 }, - { 0x001e0c, 8, 0x20, 0x00000001 }, - { 0x001e10, 8, 0x20, 0x00000001 }, - { 0x001e14, 8, 0x20, 0x00000002 }, - { 0x001e18, 8, 0x20, 0x00000001 }, - { 0x001480, 8, 0x10, 0x00000000 }, - { 0x001484, 8, 0x10, 0x00000000 }, - { 0x001488, 8, 0x10, 0x00000000 }, - { 0x003400, 128, 0x04, 0x00000000 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x001514, 1, 0x04, 0x00000000 }, - { 0x000d68, 1, 0x04, 0x0000ffff }, - { 0x00121c, 1, 0x04, 0x0fac6881 }, - { 0x000fac, 1, 0x04, 0x00000001 }, - { 0x001538, 1, 0x04, 0x00000001 }, - { 0x000fe0, 2, 0x04, 0x00000000 }, - { 0x000fe8, 1, 0x04, 0x00000014 }, - { 0x000fec, 1, 0x04, 0x00000040 }, - { 0x000ff0, 1, 0x04, 0x00000000 }, - { 0x00179c, 1, 0x04, 0x00000000 }, - { 0x001228, 1, 0x04, 0x00000400 }, - { 0x00122c, 1, 0x04, 0x00000300 }, - { 0x001230, 1, 0x04, 0x00010001 }, - { 0x0007f8, 1, 0x04, 0x00000000 }, - { 0x0015b4, 1, 0x04, 0x00000001 }, - { 0x0015cc, 1, 0x04, 0x00000000 }, - { 0x001534, 1, 0x04, 0x00000000 }, - { 0x000754, 1, 0x04, 0x00000001 }, - { 0x000fb0, 1, 0x04, 0x00000000 }, - { 0x0015d0, 1, 0x04, 0x00000000 }, - { 0x00153c, 1, 0x04, 0x00000000 }, - { 0x0016b4, 1, 0x04, 0x00000003 }, - { 0x000fbc, 4, 0x04, 0x0000ffff }, - { 0x000df8, 2, 0x04, 0x00000000 }, - { 0x001948, 1, 0x04, 0x00000000 }, - { 0x001970, 1, 0x04, 0x00000001 }, - { 0x00161c, 1, 0x04, 0x000009f0 }, - { 0x000dcc, 1, 0x04, 0x00000010 }, - { 0x0015e4, 1, 0x04, 0x00000000 }, - { 0x001160, 32, 0x04, 0x25e00040 }, - { 0x001880, 32, 0x04, 0x00000000 }, - { 0x000f84, 2, 0x04, 0x00000000 }, - { 0x0017c8, 2, 0x04, 0x00000000 }, - { 0x0017d0, 1, 0x04, 0x000000ff }, - { 0x0017d4, 1, 0x04, 0xffffffff }, - { 0x0017d8, 1, 0x04, 0x00000002 }, - { 0x0017dc, 1, 0x04, 0x00000000 }, - { 0x0015f4, 2, 0x04, 0x00000000 }, - { 0x001434, 2, 0x04, 0x00000000 }, - { 0x000d74, 1, 0x04, 0x00000000 }, - { 0x0013a4, 1, 0x04, 0x00000000 }, - { 0x001318, 1, 0x04, 0x00000001 }, - { 0x001080, 2, 0x04, 0x00000000 }, - { 0x001088, 2, 0x04, 0x00000001 }, - { 0x001090, 1, 0x04, 0x00000000 }, - { 0x001094, 1, 0x04, 0x00000001 }, - { 0x001098, 1, 0x04, 0x00000000 }, - { 0x00109c, 1, 0x04, 0x00000001 }, - { 0x0010a0, 2, 0x04, 0x00000000 }, - { 0x001644, 1, 0x04, 0x00000000 }, - { 0x000748, 1, 0x04, 0x00000000 }, - { 0x000de8, 1, 0x04, 0x00000000 }, - { 0x001648, 1, 0x04, 0x00000000 }, - { 0x0012a4, 1, 0x04, 0x00000000 }, - { 0x001120, 4, 0x04, 0x00000000 }, - { 0x001118, 1, 0x04, 0x00000000 }, - { 0x00164c, 1, 0x04, 0x00000000 }, - { 0x001658, 1, 0x04, 0x00000000 }, - { 0x001910, 1, 0x04, 0x00000290 }, - { 0x001518, 1, 0x04, 0x00000000 }, - { 0x00165c, 1, 0x04, 0x00000001 }, - { 0x001520, 1, 0x04, 0x00000000 }, - { 0x001604, 1, 0x04, 0x00000000 }, - { 0x001570, 1, 0x04, 0x00000000 }, - { 0x0013b0, 2, 0x04, 0x3f800000 }, - { 0x00020c, 1, 0x04, 0x00000000 }, - { 0x001670, 1, 0x04, 0x30201000 }, - { 0x001674, 1, 0x04, 0x70605040 }, - { 0x001678, 1, 0x04, 0xb8a89888 }, - { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, - { 0x00166c, 1, 0x04, 0x00000000 }, - { 0x001680, 1, 0x04, 0x00ffff00 }, - { 0x0012d0, 1, 0x04, 0x00000003 }, - { 0x0012d4, 1, 0x04, 0x00000002 }, - { 0x001684, 2, 0x04, 0x00000000 }, - { 0x000dac, 2, 0x04, 0x00001b02 }, - { 0x000db4, 1, 0x04, 0x00000000 }, - { 0x00168c, 1, 0x04, 0x00000000 }, - { 0x0015bc, 1, 0x04, 0x00000000 }, - { 0x00156c, 1, 0x04, 0x00000000 }, - { 0x00187c, 1, 0x04, 0x00000000 }, - { 0x001110, 1, 0x04, 0x00000001 }, - { 0x000dc0, 3, 0x04, 0x00000000 }, - { 0x000f40, 5, 0x04, 0x00000000 }, - { 0x001234, 1, 0x04, 0x00000000 }, - { 0x001690, 1, 0x04, 0x00000000 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x001000, 1, 0x04, 0x00000010 }, - { 0x0010fc, 1, 0x04, 0x00000000 }, - { 0x001290, 1, 0x04, 0x00000000 }, - { 0x000218, 1, 0x04, 0x00000010 }, - { 0x0012d8, 1, 0x04, 0x00000000 }, - { 0x0012dc, 1, 0x04, 0x00000010 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x00155c, 2, 0x04, 0x00000000 }, - { 0x001564, 1, 0x04, 0x00000fff }, - { 0x001574, 2, 0x04, 0x00000000 }, - { 0x00157c, 1, 0x04, 0x000fffff }, - { 0x001354, 1, 0x04, 0x00000000 }, - { 0x001610, 1, 0x04, 0x00000012 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x00260c, 1, 0x04, 0x00000000 }, - { 0x0007ac, 1, 0x04, 0x00000000 }, - { 0x00162c, 1, 0x04, 0x00000003 }, - { 0x000210, 1, 0x04, 0x00000000 }, - { 0x000320, 1, 0x04, 0x00000000 }, - { 0x000324, 6, 0x04, 0x3f800000 }, - { 0x000750, 1, 0x04, 0x00000000 }, - { 0x000760, 1, 0x04, 0x39291909 }, - { 0x000764, 1, 0x04, 0x79695949 }, - { 0x000768, 1, 0x04, 0xb9a99989 }, - { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, - { 0x000770, 1, 0x04, 0x30201000 }, - { 0x000774, 1, 0x04, 0x70605040 }, - { 0x000778, 1, 0x04, 0x00009080 }, - { 0x000780, 1, 0x04, 0x39291909 }, - { 0x000784, 1, 0x04, 0x79695949 }, - { 0x000788, 1, 0x04, 0xb9a99989 }, - { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, - { 0x0007d0, 1, 0x04, 0x30201000 }, - { 0x0007d4, 1, 0x04, 0x70605040 }, - { 0x0007d8, 1, 0x04, 0x00009080 }, - { 0x00037c, 1, 0x04, 0x00000001 }, - { 0x000740, 2, 0x04, 0x00000000 }, - { 0x002600, 1, 0x04, 0x00000000 }, - { 0x001918, 1, 0x04, 0x00000000 }, - { 0x00191c, 1, 0x04, 0x00000900 }, - { 0x001920, 1, 0x04, 0x00000405 }, - { 0x001308, 1, 0x04, 0x00000001 }, - { 0x001924, 1, 0x04, 0x00000000 }, - { 0x0013ac, 1, 0x04, 0x00000000 }, - { 0x00192c, 1, 0x04, 0x00000001 }, - { 0x00193c, 1, 0x04, 0x00002c1c }, - { 0x000d7c, 1, 0x04, 0x00000000 }, - { 0x000f8c, 1, 0x04, 0x00000000 }, - { 0x0002c0, 1, 0x04, 0x00000001 }, - { 0x001510, 1, 0x04, 0x00000000 }, - { 0x001940, 1, 0x04, 0x00000000 }, - { 0x000ff4, 2, 0x04, 0x00000000 }, - { 0x00194c, 2, 0x04, 0x00000000 }, - { 0x001968, 1, 0x04, 0x00000000 }, - { 0x001590, 1, 0x04, 0x0000003f }, - { 0x0007e8, 4, 0x04, 0x00000000 }, - { 0x00196c, 1, 0x04, 0x00000011 }, - { 0x0002e4, 1, 0x04, 0x0000b001 }, - { 0x00036c, 2, 0x04, 0x00000000 }, - { 0x00197c, 1, 0x04, 0x00000000 }, - { 0x000fcc, 2, 0x04, 0x00000000 }, - { 0x0002d8, 1, 0x04, 0x00000040 }, - { 0x001980, 1, 0x04, 0x00000080 }, - { 0x001504, 1, 0x04, 0x00000080 }, - { 0x001984, 1, 0x04, 0x00000000 }, - { 0x000f60, 1, 0x04, 0x00000000 }, - { 0x000f64, 1, 0x04, 0x00400040 }, - { 0x000f68, 1, 0x04, 0x00002212 }, - { 0x000f6c, 1, 0x04, 0x08080203 }, - { 0x001108, 1, 0x04, 0x00000008 }, - { 0x000f70, 1, 0x04, 0x00080001 }, - { 0x000ffc, 1, 0x04, 0x00000000 }, - { 0x000300, 1, 0x04, 0x00000001 }, - { 0x0013a8, 1, 0x04, 0x00000000 }, - { 0x0012ec, 1, 0x04, 0x00000000 }, - { 0x001310, 1, 0x04, 0x00000000 }, - { 0x001314, 1, 0x04, 0x00000001 }, - { 0x001380, 1, 0x04, 0x00000000 }, - { 0x001384, 4, 0x04, 0x00000001 }, - { 0x001394, 1, 0x04, 0x00000000 }, - { 0x00139c, 1, 0x04, 0x00000000 }, - { 0x001398, 1, 0x04, 0x00000000 }, - { 0x001594, 1, 0x04, 0x00000000 }, - { 0x001598, 4, 0x04, 0x00000001 }, - { 0x000f54, 3, 0x04, 0x00000000 }, - { 0x0019bc, 1, 0x04, 0x00000000 }, - { 0x000f9c, 2, 0x04, 0x00000000 }, - { 0x0012cc, 1, 0x04, 0x00000000 }, - { 0x0012e8, 1, 0x04, 0x00000000 }, - { 0x00130c, 1, 0x04, 0x00000001 }, - { 0x001360, 8, 0x04, 0x00000000 }, - { 0x00133c, 2, 0x04, 0x00000001 }, - { 0x001344, 1, 0x04, 0x00000002 }, - { 0x001348, 2, 0x04, 0x00000001 }, - { 0x001350, 1, 0x04, 0x00000002 }, - { 0x001358, 1, 0x04, 0x00000001 }, - { 0x0012e4, 1, 0x04, 0x00000000 }, - { 0x00131c, 4, 0x04, 0x00000000 }, - { 0x0019c0, 1, 0x04, 0x00000000 }, - { 0x001140, 1, 0x04, 0x00000000 }, - { 0x000dd0, 1, 0x04, 0x00000000 }, - { 0x000dd4, 1, 0x04, 0x00000001 }, - { 0x0002f4, 1, 0x04, 0x00000000 }, - { 0x0019c4, 1, 0x04, 0x00000000 }, - { 0x0019c8, 1, 0x04, 0x00001500 }, - { 0x00135c, 1, 0x04, 0x00000000 }, - { 0x000f90, 1, 0x04, 0x00000000 }, - { 0x0019e0, 8, 0x04, 0x00000001 }, - { 0x0019cc, 1, 0x04, 0x00000001 }, - { 0x0015b8, 1, 0x04, 0x00000000 }, - { 0x001a00, 1, 0x04, 0x00001111 }, - { 0x001a04, 7, 0x04, 0x00000000 }, - { 0x000d6c, 2, 0x04, 0xffff0000 }, - { 0x0010f8, 1, 0x04, 0x00001010 }, - { 0x000d80, 5, 0x04, 0x00000000 }, - { 0x000da0, 1, 0x04, 0x00000000 }, - { 0x0007a4, 2, 0x04, 0x00000000 }, - { 0x001508, 1, 0x04, 0x80000000 }, - { 0x00150c, 1, 0x04, 0x40000000 }, - { 0x001668, 1, 0x04, 0x00000000 }, - { 0x000318, 2, 0x04, 0x00000008 }, - { 0x000d9c, 1, 0x04, 0x00000001 }, - { 0x000f14, 1, 0x04, 0x00000000 }, - { 0x000374, 1, 0x04, 0x00000000 }, - { 0x000378, 1, 0x04, 0x0000000c }, - { 0x0007dc, 1, 0x04, 0x00000000 }, - { 0x00074c, 1, 0x04, 0x00000055 }, - { 0x001420, 1, 0x04, 0x00000003 }, - { 0x001008, 1, 0x04, 0x00000008 }, - { 0x00100c, 1, 0x04, 0x00000040 }, - { 0x001010, 1, 0x04, 0x0000012c }, - { 0x000d60, 1, 0x04, 0x00000040 }, - { 0x001018, 1, 0x04, 0x00000020 }, - { 0x00101c, 1, 0x04, 0x00000001 }, - { 0x001020, 1, 0x04, 0x00000020 }, - { 0x001024, 1, 0x04, 0x00000001 }, - { 0x001444, 3, 0x04, 0x00000000 }, - { 0x000360, 1, 0x04, 0x20164010 }, - { 0x000364, 1, 0x04, 0x00000020 }, - { 0x000368, 1, 0x04, 0x00000000 }, - { 0x000da8, 1, 0x04, 0x00000030 }, - { 0x000de4, 1, 0x04, 0x00000000 }, - { 0x000204, 1, 0x04, 0x00000006 }, - { 0x0002d0, 1, 0x04, 0x003fffff }, - { 0x001220, 1, 0x04, 0x00000005 }, - { 0x000fdc, 1, 0x04, 0x00000000 }, - { 0x000f98, 1, 0x04, 0x00400008 }, - { 0x001284, 1, 0x04, 0x08000080 }, - { 0x001450, 1, 0x04, 0x00400008 }, - { 0x001454, 1, 0x04, 0x08000080 }, - { 0x000214, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -gm107_grctx_pack_mthd[] = { - { gm107_grctx_init_b097_0, 0xb097 }, - { nvc0_grctx_init_902d_0, 0x902d }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_fe_0[] = { - { 0x404004, 8, 0x04, 0x00000000 }, - { 0x404024, 1, 0x04, 0x0000e000 }, - { 0x404028, 8, 0x04, 0x00000000 }, - { 0x4040a8, 8, 0x04, 0x00000000 }, - { 0x4040c8, 1, 0x04, 0xf800008f }, - { 0x4040d0, 6, 0x04, 0x00000000 }, - { 0x4040f8, 1, 0x04, 0x00000000 }, - { 0x404100, 10, 0x04, 0x00000000 }, - { 0x404130, 2, 0x04, 0x00000000 }, - { 0x404150, 1, 0x04, 0x0000002e }, - { 0x404154, 1, 0x04, 0x00000400 }, - { 0x404158, 1, 0x04, 0x00000200 }, - { 0x404164, 1, 0x04, 0x00000045 }, - { 0x40417c, 2, 0x04, 0x00000000 }, - { 0x404194, 1, 0x04, 0x01000700 }, - { 0x4041a0, 4, 0x04, 0x00000000 }, - { 0x404200, 4, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x0f8001bf }, - { 0x405830, 1, 0x04, 0x0aa01000 }, - { 0x405834, 1, 0x04, 0x08000000 }, - { 0x405838, 1, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - { 0x405a1c, 1, 0x04, 0x000000ff }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x07410001 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b0, 3, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x80400280 }, - { 0x4064c4, 1, 0x04, 0x0400ffff }, - { 0x4064c8, 1, 0x04, 0x018001ff }, - { 0x4064cc, 9, 0x04, 0x00000000 }, - { 0x4064fc, 1, 0x04, 0x0000022a }, - { 0x406500, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x32802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x1003e005 }, - { 0x408840, 1, 0x04, 0x0000000b }, - { 0x408900, 1, 0x04, 0xb080b801 }, - { 0x408904, 1, 0x04, 0x63038001 }, - { 0x408908, 1, 0x04, 0x02c8102f }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -static const struct nvc0_graph_pack -gm107_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { gm107_grctx_init_fe_0 }, - { nvf0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { gm107_grctx_init_ds_0 }, - { nvf0_grctx_init_cwd_0 }, - { gm107_grctx_init_pd_0 }, - { nv108_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { gm107_grctx_init_be_0 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_gpc_unk_0[] = { - { 0x418380, 1, 0x04, 0x00000056 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_gpc_unk_1[] = { - { 0x418600, 1, 0x04, 0x0000007f }, - { 0x418684, 1, 0x04, 0x0000001f }, - { 0x418700, 1, 0x04, 0x00000002 }, - { 0x418704, 1, 0x04, 0x00000080 }, - { 0x418708, 1, 0x04, 0x40000000 }, - { 0x41870c, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x7006863a }, - { 0x418810, 1, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00000044 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100058 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_gpc_unk_2[] = { - { 0x418d24, 1, 0x04, 0x00000000 }, - { 0x418e00, 1, 0x04, 0x90000000 }, - { 0x418e24, 1, 0x04, 0x00000000 }, - { 0x418e28, 1, 0x04, 0x00000030 }, - { 0x418e30, 1, 0x04, 0x00000000 }, - { 0x418e34, 1, 0x04, 0x00010000 }, - { 0x418e38, 1, 0x04, 0x00000000 }, - { 0x418e40, 22, 0x04, 0x00000000 }, - { 0x418ea0, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -gm107_grctx_pack_gpc[] = { - { gm107_grctx_init_gpc_unk_0 }, - { nv108_grctx_init_prop_0 }, - { gm107_grctx_init_gpc_unk_1 }, - { gm107_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nv108_grctx_init_crstr_0 }, - { nve4_grctx_init_gpm_0 }, - { gm107_grctx_init_gpc_unk_2 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000300f0 }, - { 0x419a04, 1, 0x04, 0x00000005 }, - { 0x419a08, 1, 0x04, 0x00000421 }, - { 0x419a0c, 1, 0x04, 0x00120000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00002200 }, - { 0x419a1c, 1, 0x04, 0x0000c000 }, - { 0x419a20, 1, 0x04, 0x20008a00 }, - { 0x419a30, 1, 0x04, 0x00000001 }, - { 0x419a3c, 1, 0x04, 0x00000002 }, - { 0x419ac4, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_mpc_0[] = { - { 0x419c00, 1, 0x04, 0x0000001a }, - { 0x419c04, 1, 0x04, 0x80000006 }, - { 0x419c08, 1, 0x04, 0x00000002 }, - { 0x419c20, 1, 0x04, 0x00000000 }, - { 0x419c24, 1, 0x04, 0x00084210 }, - { 0x419c28, 1, 0x04, 0x3efbefbe }, - { 0x419c2c, 1, 0x04, 0x00000000 }, - { 0x419c34, 1, 0x04, 0x01ff1ff3 }, - { 0x419c3c, 1, 0x04, 0x00001919 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_l1c_0[] = { - { 0x419c84, 1, 0x04, 0x00000020 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_sm_0[] = { - { 0x419e04, 3, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00001c02 }, - { 0x419e44, 1, 0x04, 0x00d3eff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000007f }, - { 0x419e50, 1, 0x04, 0x00000000 }, - { 0x419e60, 4, 0x04, 0x00000000 }, - { 0x419e74, 10, 0x04, 0x00000000 }, - { 0x419eac, 1, 0x04, 0x0001cf8b }, - { 0x419eb0, 1, 0x04, 0x00030300 }, - { 0x419eb8, 1, 0x04, 0x00000000 }, - { 0x419ef0, 24, 0x04, 0x00000000 }, - { 0x419f68, 2, 0x04, 0x00000000 }, - { 0x419f70, 1, 0x04, 0x00000020 }, - { 0x419f78, 1, 0x04, 0x000003eb }, - { 0x419f7c, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -gm107_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { gm107_grctx_init_tex_0 }, - { gm107_grctx_init_mpc_0 }, - { gm107_grctx_init_l1c_0 }, - { gm107_grctx_init_sm_0 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_cbm_0[] = { - { 0x41bec0, 1, 0x04, 0x00000000 }, - { 0x41bec4, 1, 0x04, 0x01050000 }, - { 0x41bee4, 1, 0x04, 0x00000000 }, - { 0x41bef0, 1, 0x04, 0x000003ff }, - { 0x41bef4, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_grctx_init_wwdx_0[] = { - { 0x41bf00, 1, 0x04, 0x0a418820 }, - { 0x41bf04, 1, 0x04, 0x062080e6 }, - { 0x41bf08, 1, 0x04, 0x020398a4 }, - { 0x41bf0c, 1, 0x04, 0x0e629062 }, - { 0x41bf10, 1, 0x04, 0x0a418820 }, - { 0x41bf14, 1, 0x04, 0x000000e6 }, - { 0x41bfd0, 1, 0x04, 0x00900103 }, - { 0x41bfe0, 1, 0x04, 0x80000000 }, - { 0x41bfe4, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -gm107_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { gm107_grctx_init_cbm_0 }, - { gm107_grctx_init_wwdx_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -static void -gm107_grctx_generate_bundle(struct nvc0_grctx *info) -{ - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); - const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, - impl->bundle_size / 0x20); - const u32 token_limit = impl->bundle_token_limit; - const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; - const int s = 8; - const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); - mmio_refn(info, 0x408004, 0x00000000, s, b); - mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); - mmio_refn(info, 0x418e24, 0x00000000, s, b); - mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b); - mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); -} - -static void -gm107_grctx_generate_pagepool(struct nvc0_grctx *info) -{ - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); - const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; - const int s = 8; - const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); - mmio_refn(info, 0x40800c, 0x00000000, s, b); - mmio_wr32(info, 0x408010, 0x80000000); - mmio_refn(info, 0x419004, 0x00000000, s, b); - mmio_wr32(info, 0x419008, 0x00000000); - mmio_wr32(info, 0x4064cc, 0x80000000); - mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */ -} - -static void -gm107_grctx_generate_attrib(struct nvc0_grctx *info) -{ - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv); - const u32 alpha = impl->alpha_nr; - const u32 attrib = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); - const u32 access = NV_MEM_ACCESS_RW; - const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); - const int max_batches = 0xffff; - u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; - int gpc, ppc, n = 0; - - mmio_refn(info, 0x418810, 0x80000000, s, b); - mmio_refn(info, 0x419848, 0x10000000, s, b); - mmio_refn(info, 0x419c2c, 0x10000000, s, b); - mmio_wr32(info, 0x405830, (attrib << 16) | alpha); - mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) { - const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc]; - const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc]; - const u32 u = 0x418ea0 + (n * 0x04); - const u32 o = PPC_UNIT(gpc, ppc, 0); - mmio_wr32(info, o + 0xc0, bs); - mmio_wr32(info, o + 0xf4, bo); - bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; - mmio_wr32(info, o + 0xe4, as); - mmio_wr32(info, o + 0xf8, ao); - ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; - mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs); - } - } -} - -static void -gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) -{ - int gpc, tpc, id; - - for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); - id++; - } - - nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); - } - } -} - -static void -gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) -{ - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - int i; - - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); - - nv_wr32(priv, 0x404154, 0x00000000); - - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(priv); - - gm107_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nve4_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); - - nv_wr32(priv, 0x4064d0, 0x00000001); - for (i = 1; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(priv, 0x406500, 0x00000001); - - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); - - if (priv->gpc_nr == 1) { - nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); - nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); - } else { - nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); - nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); - } - - nvc0_graph_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - - nv_mask(priv, 0x419e00, 0x00808080, 0x00808080); - nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000); - nv_mask(priv, 0x419f80, 0x80000000, 0x80000000); - nv_mask(priv, 0x419f88, 0x80000000, 0x80000000); -} - -struct nouveau_oclass * -gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = gm107_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = gm107_grctx_pack_hub, - .gpc = gm107_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = gm107_grctx_pack_tpc, - .ppc = gm107_grctx_pack_ppc, - .icmd = gm107_grctx_pack_icmd, - .mthd = gm107_grctx_pack_mthd, - .bundle = gm107_grctx_generate_bundle, - .bundle_size = 0x3000, - .bundle_min_gpm_fifo_depth = 0x180, - .bundle_token_limit = 0x2c0, - .pagepool = gm107_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = gm107_grctx_generate_attrib, - .attrib_nr_max = 0xff0, - .attrib_nr = 0xaa0, - .alpha_nr_max = 0x1800, - .alpha_nr = 0x1000, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c deleted file mode 100644 index ce252adbef81..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nv108_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x0002f2, 2, 0x01, 0x00000001 }, - { 0x0002f5, 1, 0x01, 0x00000001 }, - { 0x0002f7, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000383, 1, 0x01, 0x00000011 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000662, 1, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x00080b, 1, 0x01, 0x00000002 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x000a0d, 1, 0x01, 0x00000006 }, - { 0x00097d, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x003fffff }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00400008 }, - { 0x000841, 1, 0x01, 0x08000080 }, - { 0x000842, 1, 0x01, 0x00400008 }, - { 0x000843, 1, 0x01, 0x08000080 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x00c500, 1, 0x01, 0x00000003 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000008 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x00c500, 1, 0x01, 0x00000003 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_pack -nv108_grctx_pack_icmd[] = { - { nv108_grctx_init_icmd_0 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_fe_0[] = { - { 0x404004, 8, 0x04, 0x00000000 }, - { 0x404024, 1, 0x04, 0x0000e000 }, - { 0x404028, 8, 0x04, 0x00000000 }, - { 0x4040a8, 8, 0x04, 0x00000000 }, - { 0x4040c8, 1, 0x04, 0xf800008f }, - { 0x4040d0, 6, 0x04, 0x00000000 }, - { 0x4040e8, 1, 0x04, 0x00001000 }, - { 0x4040f8, 1, 0x04, 0x00000000 }, - { 0x404100, 10, 0x04, 0x00000000 }, - { 0x404130, 2, 0x04, 0x00000000 }, - { 0x404138, 1, 0x04, 0x20000040 }, - { 0x404150, 1, 0x04, 0x0000002e }, - { 0x404154, 1, 0x04, 0x00000400 }, - { 0x404158, 1, 0x04, 0x00000200 }, - { 0x404164, 1, 0x04, 0x00000055 }, - { 0x40417c, 2, 0x04, 0x00000000 }, - { 0x404194, 1, 0x04, 0x01000700 }, - { 0x4041a0, 4, 0x04, 0x00000000 }, - { 0x404200, 1, 0x04, 0x0000a197 }, - { 0x404204, 1, 0x04, 0x0000a1c0 }, - { 0x404208, 1, 0x04, 0x0000a140 }, - { 0x40420c, 1, 0x04, 0x0000902d }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x0f8000bf }, - { 0x405830, 1, 0x04, 0x02180648 }, - { 0x405834, 1, 0x04, 0x08000000 }, - { 0x405838, 1, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - { 0x405a1c, 1, 0x04, 0x000000ff }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x034103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b0, 3, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x802000f0 }, - { 0x4064c4, 1, 0x04, 0x0192ffff }, - { 0x4064c8, 1, 0x04, 0x00c20200 }, - { 0x4064cc, 9, 0x04, 0x00000000 }, - { 0x4064fc, 1, 0x04, 0x0000022a }, - {} -}; - -const struct nvc0_graph_init -nv108_grctx_init_rstr2d_0[] = { - { 0x407804, 1, 0x04, 0x00000063 }, - { 0x40780c, 1, 0x04, 0x0a418820 }, - { 0x407810, 1, 0x04, 0x062080e6 }, - { 0x407814, 1, 0x04, 0x020398a4 }, - { 0x407818, 1, 0x04, 0x0e629062 }, - { 0x40781c, 1, 0x04, 0x0a418820 }, - { 0x407820, 1, 0x04, 0x000000e6 }, - { 0x4078bc, 1, 0x04, 0x00000103 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x32802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x1003e005 }, - { 0x408840, 1, 0x04, 0x0000000b }, - { 0x408900, 1, 0x04, 0xb080b801 }, - { 0x408904, 1, 0x04, 0x62000001 }, - { 0x408908, 1, 0x04, 0x02c8102f }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -static const struct nvc0_graph_pack -nv108_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nv108_grctx_init_fe_0 }, - { nvf0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { nv108_grctx_init_ds_0 }, - { nvf0_grctx_init_cwd_0 }, - { nv108_grctx_init_pd_0 }, - { nv108_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { nv108_grctx_init_be_0 }, - {} -}; - -const struct nvc0_graph_init -nv108_grctx_init_prop_0[] = { - { 0x418400, 1, 0x04, 0x38005e00 }, - { 0x418404, 1, 0x04, 0x71e0ffff }, - { 0x41840c, 1, 0x04, 0x00001008 }, - { 0x418410, 1, 0x04, 0x0fff0fff }, - { 0x418414, 1, 0x04, 0x02200fff }, - { 0x418450, 6, 0x04, 0x00000000 }, - { 0x418468, 1, 0x04, 0x00000001 }, - { 0x41846c, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_gpc_unk_1[] = { - { 0x418600, 1, 0x04, 0x0000007f }, - { 0x418684, 1, 0x04, 0x0000001f }, - { 0x418700, 1, 0x04, 0x00000002 }, - { 0x418704, 2, 0x04, 0x00000080 }, - { 0x41870c, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x7006863a }, - { 0x418808, 1, 0x04, 0x00000000 }, - { 0x41880c, 1, 0x04, 0x00000030 }, - { 0x418810, 1, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00000044 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100058 }, - {} -}; - -const struct nvc0_graph_init -nv108_grctx_init_crstr_0[] = { - { 0x418b00, 1, 0x04, 0x0000001e }, - { 0x418b08, 1, 0x04, 0x0a418820 }, - { 0x418b0c, 1, 0x04, 0x062080e6 }, - { 0x418b10, 1, 0x04, 0x020398a4 }, - { 0x418b14, 1, 0x04, 0x0e629062 }, - { 0x418b18, 1, 0x04, 0x0a418820 }, - { 0x418b1c, 1, 0x04, 0x000000e6 }, - { 0x418bb8, 1, 0x04, 0x00000103 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_gpm_0[] = { - { 0x418c08, 1, 0x04, 0x00000001 }, - { 0x418c10, 8, 0x04, 0x00000000 }, - { 0x418c40, 1, 0x04, 0xffffffff }, - { 0x418c6c, 1, 0x04, 0x00000001 }, - { 0x418c80, 1, 0x04, 0x2020000c }, - { 0x418c8c, 1, 0x04, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_pack -nv108_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nv108_grctx_init_prop_0 }, - { nv108_grctx_init_gpc_unk_1 }, - { nv108_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nv108_grctx_init_crstr_0 }, - { nv108_grctx_init_gpm_0 }, - { nvf0_grctx_init_gpc_unk_2 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000100f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000421 }, - { 0x419a0c, 1, 0x04, 0x00120000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - { 0x419a1c, 1, 0x04, 0x0000c000 }, - { 0x419a20, 1, 0x04, 0x00000800 }, - { 0x419a30, 1, 0x04, 0x00000001 }, - { 0x419ac4, 1, 0x04, 0x0037f440 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_sm_0[] = { - { 0x419e04, 1, 0x04, 0x00000000 }, - { 0x419e08, 1, 0x04, 0x0000001d }, - { 0x419e0c, 1, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00001c02 }, - { 0x419e44, 1, 0x04, 0x0013eff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000007f }, - { 0x419e50, 2, 0x04, 0x00000000 }, - { 0x419e58, 1, 0x04, 0x00000001 }, - { 0x419e5c, 3, 0x04, 0x00000000 }, - { 0x419e68, 1, 0x04, 0x00000002 }, - { 0x419e6c, 12, 0x04, 0x00000000 }, - { 0x419eac, 1, 0x04, 0x00001f8f }, - { 0x419eb0, 1, 0x04, 0x0db00d2f }, - { 0x419eb8, 1, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x0001304f }, - { 0x419f30, 4, 0x04, 0x00000000 }, - { 0x419f40, 1, 0x04, 0x00000018 }, - { 0x419f44, 3, 0x04, 0x00000000 }, - { 0x419f58, 1, 0x04, 0x00000020 }, - { 0x419f70, 1, 0x04, 0x00000000 }, - { 0x419f78, 1, 0x04, 0x000001eb }, - { 0x419f7c, 1, 0x04, 0x00000404 }, - {} -}; - -static const struct nvc0_graph_pack -nv108_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nv108_grctx_init_tex_0 }, - { nvf0_grctx_init_mpc_0 }, - { nvf0_grctx_init_l1c_0 }, - { nv108_grctx_init_sm_0 }, - {} -}; - -static const struct nvc0_graph_init -nv108_grctx_init_cbm_0[] = { - { 0x41bec0, 1, 0x04, 0x10000000 }, - { 0x41bec4, 1, 0x04, 0x00037f7f }, - { 0x41bee4, 1, 0x04, 0x00000000 }, - { 0x41bef0, 1, 0x04, 0x000003ff }, - {} -}; - -static const struct nvc0_graph_pack -nv108_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { nv108_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -struct nouveau_oclass * -nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nv108_grctx_pack_hub, - .gpc = nv108_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nv108_grctx_pack_tpc, - .ppc = nv108_grctx_pack_ppc, - .icmd = nv108_grctx_pack_icmd, - .mthd = nvf0_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, - .bundle_size = 0x3000, - .bundle_min_gpm_fifo_depth = 0xc2, - .bundle_token_limit = 0x200, - .pagepool = nve4_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x7ff, - .alpha_nr = 0x648, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c deleted file mode 100644 index 7bbb1e1b7a8d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright 2009 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include - -/* NVIDIA context programs handle a number of other conditions which are - * not implemented in our versions. It's not clear why NVIDIA context - * programs have this code, nor whether it's strictly necessary for - * correct operation. We'll implement additional handling if/when we - * discover it's necessary. - * - * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" - * flag is set, this gets saved into the context. - * - On context save, the context program for all cards load nsource - * into a flag register and check for ILLEGAL_MTHD. If it's set, - * opcode 0x60000d is called before resuming normal operation. - * - Some context programs check more conditions than the above. NV44 - * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) - * and calls 0x60000d before resuming normal operation. - * - At the very beginning of NVIDIA's context programs, flag 9 is checked - * and if true 0x800001 is called with count=0, pos=0, the flag is cleared - * and then the ctxprog is aborted. It looks like a complicated NOP, - * its purpose is unknown. - * - In the section of code that loads the per-vs state, NVIDIA check - * flag 10. If it's set, they only transfer the small 0x300 byte block - * of state + the state for a single vs as opposed to the state for - * all vs units. It doesn't seem likely that it'll occur in normal - * operation, especially seeing as it appears NVIDIA may have screwed - * up the ctxprogs for some cards and have an invalid instruction - * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. - * - There's a number of places where context offset 0 (where we place - * the PRAMIN offset of the context) is loaded into either 0x408000, - * 0x408004 or 0x408008. Not sure what's up there either. - * - The ctxprogs for some cards save 0x400a00 again during the cleanup - * path for auto-loadctx. - */ - -#define CP_FLAG_CLEAR 0 -#define CP_FLAG_SET 1 -#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) -#define CP_FLAG_SWAP_DIRECTION_LOAD 0 -#define CP_FLAG_SWAP_DIRECTION_SAVE 1 -#define CP_FLAG_USER_SAVE ((0 * 32) + 5) -#define CP_FLAG_USER_SAVE_NOT_PENDING 0 -#define CP_FLAG_USER_SAVE_PENDING 1 -#define CP_FLAG_USER_LOAD ((0 * 32) + 6) -#define CP_FLAG_USER_LOAD_NOT_PENDING 0 -#define CP_FLAG_USER_LOAD_PENDING 1 -#define CP_FLAG_STATUS ((3 * 32) + 0) -#define CP_FLAG_STATUS_IDLE 0 -#define CP_FLAG_STATUS_BUSY 1 -#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) -#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 -#define CP_FLAG_AUTO_SAVE_PENDING 1 -#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) -#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 -#define CP_FLAG_AUTO_LOAD_PENDING 1 -#define CP_FLAG_UNK54 ((3 * 32) + 6) -#define CP_FLAG_UNK54_CLEAR 0 -#define CP_FLAG_UNK54_SET 1 -#define CP_FLAG_ALWAYS ((3 * 32) + 8) -#define CP_FLAG_ALWAYS_FALSE 0 -#define CP_FLAG_ALWAYS_TRUE 1 -#define CP_FLAG_UNK57 ((3 * 32) + 9) -#define CP_FLAG_UNK57_CLEAR 0 -#define CP_FLAG_UNK57_SET 1 - -#define CP_CTX 0x00100000 -#define CP_CTX_COUNT 0x000fc000 -#define CP_CTX_COUNT_SHIFT 14 -#define CP_CTX_REG 0x00003fff -#define CP_LOAD_SR 0x00200000 -#define CP_LOAD_SR_VALUE 0x000fffff -#define CP_BRA 0x00400000 -#define CP_BRA_IP 0x0000ff00 -#define CP_BRA_IP_SHIFT 8 -#define CP_BRA_IF_CLEAR 0x00000080 -#define CP_BRA_FLAG 0x0000007f -#define CP_WAIT 0x00500000 -#define CP_WAIT_SET 0x00000080 -#define CP_WAIT_FLAG 0x0000007f -#define CP_SET 0x00700000 -#define CP_SET_1 0x00000080 -#define CP_SET_FLAG 0x0000007f -#define CP_NEXT_TO_SWAP 0x00600007 -#define CP_NEXT_TO_CURRENT 0x00600009 -#define CP_SET_CONTEXT_POINTER 0x0060000a -#define CP_END 0x0060000e -#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ -#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ -#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ - -#include "nv40.h" -#include "ctx.h" - -/* TODO: - * - get vs count from 0x1540 - */ - -static int -nv40_graph_vs_count(struct nouveau_device *device) -{ - - switch (device->chipset) { - case 0x47: - case 0x49: - case 0x4b: - return 8; - case 0x40: - return 6; - case 0x41: - case 0x42: - return 5; - case 0x43: - case 0x44: - case 0x46: - case 0x4a: - return 3; - case 0x4c: - case 0x4e: - case 0x67: - default: - return 1; - } -} - - -enum cp_label { - cp_check_load = 1, - cp_setup_auto_load, - cp_setup_load, - cp_setup_save, - cp_swap_state, - cp_swap_state3d_3_is_save, - cp_prepare_exit, - cp_exit, -}; - -static void -nv40_graph_construct_general(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - - cp_ctx(ctx, 0x4000a4, 1); - gr_def(ctx, 0x4000a4, 0x00000008); - cp_ctx(ctx, 0x400144, 58); - gr_def(ctx, 0x400144, 0x00000001); - cp_ctx(ctx, 0x400314, 1); - gr_def(ctx, 0x400314, 0x00000000); - cp_ctx(ctx, 0x400400, 10); - cp_ctx(ctx, 0x400480, 10); - cp_ctx(ctx, 0x400500, 19); - gr_def(ctx, 0x400514, 0x00040000); - gr_def(ctx, 0x400524, 0x55555555); - gr_def(ctx, 0x400528, 0x55555555); - gr_def(ctx, 0x40052c, 0x55555555); - gr_def(ctx, 0x400530, 0x55555555); - cp_ctx(ctx, 0x400560, 6); - gr_def(ctx, 0x400568, 0x0000ffff); - gr_def(ctx, 0x40056c, 0x0000ffff); - cp_ctx(ctx, 0x40057c, 5); - cp_ctx(ctx, 0x400710, 3); - gr_def(ctx, 0x400710, 0x20010001); - gr_def(ctx, 0x400714, 0x0f73ef00); - cp_ctx(ctx, 0x400724, 1); - gr_def(ctx, 0x400724, 0x02008821); - cp_ctx(ctx, 0x400770, 3); - if (device->chipset == 0x40) { - cp_ctx(ctx, 0x400814, 4); - cp_ctx(ctx, 0x400828, 5); - cp_ctx(ctx, 0x400840, 5); - gr_def(ctx, 0x400850, 0x00000040); - cp_ctx(ctx, 0x400858, 4); - gr_def(ctx, 0x400858, 0x00000040); - gr_def(ctx, 0x40085c, 0x00000040); - gr_def(ctx, 0x400864, 0x80000000); - cp_ctx(ctx, 0x40086c, 9); - gr_def(ctx, 0x40086c, 0x80000000); - gr_def(ctx, 0x400870, 0x80000000); - gr_def(ctx, 0x400874, 0x80000000); - gr_def(ctx, 0x400878, 0x80000000); - gr_def(ctx, 0x400888, 0x00000040); - gr_def(ctx, 0x40088c, 0x80000000); - cp_ctx(ctx, 0x4009c0, 8); - gr_def(ctx, 0x4009cc, 0x80000000); - gr_def(ctx, 0x4009dc, 0x80000000); - } else { - cp_ctx(ctx, 0x400840, 20); - if (nv44_graph_class(ctx->device)) { - for (i = 0; i < 8; i++) - gr_def(ctx, 0x400860 + (i * 4), 0x00000001); - } - gr_def(ctx, 0x400880, 0x00000040); - gr_def(ctx, 0x400884, 0x00000040); - gr_def(ctx, 0x400888, 0x00000040); - cp_ctx(ctx, 0x400894, 11); - gr_def(ctx, 0x400894, 0x00000040); - if (!nv44_graph_class(ctx->device)) { - for (i = 0; i < 8; i++) - gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); - } - cp_ctx(ctx, 0x4008e0, 2); - cp_ctx(ctx, 0x4008f8, 2); - if (device->chipset == 0x4c || - (device->chipset & 0xf0) == 0x60) - cp_ctx(ctx, 0x4009f8, 1); - } - cp_ctx(ctx, 0x400a00, 73); - gr_def(ctx, 0x400b0c, 0x0b0b0b0c); - cp_ctx(ctx, 0x401000, 4); - cp_ctx(ctx, 0x405004, 1); - switch (device->chipset) { - case 0x47: - case 0x49: - case 0x4b: - cp_ctx(ctx, 0x403448, 1); - gr_def(ctx, 0x403448, 0x00001010); - break; - default: - cp_ctx(ctx, 0x403440, 1); - switch (device->chipset) { - case 0x40: - gr_def(ctx, 0x403440, 0x00000010); - break; - case 0x44: - case 0x46: - case 0x4a: - gr_def(ctx, 0x403440, 0x00003010); - break; - case 0x41: - case 0x42: - case 0x43: - case 0x4c: - case 0x4e: - case 0x67: - default: - gr_def(ctx, 0x403440, 0x00001010); - break; - } - break; - } -} - -static void -nv40_graph_construct_state3d(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - - if (device->chipset == 0x40) { - cp_ctx(ctx, 0x401880, 51); - gr_def(ctx, 0x401940, 0x00000100); - } else - if (device->chipset == 0x46 || device->chipset == 0x47 || - device->chipset == 0x49 || device->chipset == 0x4b) { - cp_ctx(ctx, 0x401880, 32); - for (i = 0; i < 16; i++) - gr_def(ctx, 0x401880 + (i * 4), 0x00000111); - if (device->chipset == 0x46) - cp_ctx(ctx, 0x401900, 16); - cp_ctx(ctx, 0x401940, 3); - } - cp_ctx(ctx, 0x40194c, 18); - gr_def(ctx, 0x401954, 0x00000111); - gr_def(ctx, 0x401958, 0x00080060); - gr_def(ctx, 0x401974, 0x00000080); - gr_def(ctx, 0x401978, 0xffff0000); - gr_def(ctx, 0x40197c, 0x00000001); - gr_def(ctx, 0x401990, 0x46400000); - if (device->chipset == 0x40) { - cp_ctx(ctx, 0x4019a0, 2); - cp_ctx(ctx, 0x4019ac, 5); - } else { - cp_ctx(ctx, 0x4019a0, 1); - cp_ctx(ctx, 0x4019b4, 3); - } - gr_def(ctx, 0x4019bc, 0xffff0000); - switch (device->chipset) { - case 0x46: - case 0x47: - case 0x49: - case 0x4b: - cp_ctx(ctx, 0x4019c0, 18); - for (i = 0; i < 16; i++) - gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); - break; - } - cp_ctx(ctx, 0x401a08, 8); - gr_def(ctx, 0x401a10, 0x0fff0000); - gr_def(ctx, 0x401a14, 0x0fff0000); - gr_def(ctx, 0x401a1c, 0x00011100); - cp_ctx(ctx, 0x401a2c, 4); - cp_ctx(ctx, 0x401a44, 26); - for (i = 0; i < 16; i++) - gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); - gr_def(ctx, 0x401a8c, 0x4b7fffff); - if (device->chipset == 0x40) { - cp_ctx(ctx, 0x401ab8, 3); - } else { - cp_ctx(ctx, 0x401ab8, 1); - cp_ctx(ctx, 0x401ac0, 1); - } - cp_ctx(ctx, 0x401ad0, 8); - gr_def(ctx, 0x401ad0, 0x30201000); - gr_def(ctx, 0x401ad4, 0x70605040); - gr_def(ctx, 0x401ad8, 0xb8a89888); - gr_def(ctx, 0x401adc, 0xf8e8d8c8); - cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); - gr_def(ctx, 0x401b10, 0x40100000); - cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); - gr_def(ctx, 0x401b28, device->chipset == 0x40 ? - 0x00000004 : 0x00000000); - cp_ctx(ctx, 0x401b30, 25); - gr_def(ctx, 0x401b34, 0x0000ffff); - gr_def(ctx, 0x401b68, 0x435185d6); - gr_def(ctx, 0x401b6c, 0x2155b699); - gr_def(ctx, 0x401b70, 0xfedcba98); - gr_def(ctx, 0x401b74, 0x00000098); - gr_def(ctx, 0x401b84, 0xffffffff); - gr_def(ctx, 0x401b88, 0x00ff7000); - gr_def(ctx, 0x401b8c, 0x0000ffff); - if (device->chipset != 0x44 && device->chipset != 0x4a && - device->chipset != 0x4e) - cp_ctx(ctx, 0x401b94, 1); - cp_ctx(ctx, 0x401b98, 8); - gr_def(ctx, 0x401b9c, 0x00ff0000); - cp_ctx(ctx, 0x401bc0, 9); - gr_def(ctx, 0x401be0, 0x00ffff00); - cp_ctx(ctx, 0x401c00, 192); - for (i = 0; i < 16; i++) { /* fragment texture units */ - gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); - gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); - gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); - gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); - gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); - gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); - } - for (i = 0; i < 4; i++) { /* vertex texture units */ - gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); - gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); - gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); - gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); - } - cp_ctx(ctx, 0x400f5c, 3); - gr_def(ctx, 0x400f5c, 0x00000002); - cp_ctx(ctx, 0x400f84, 1); -} - -static void -nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - - cp_ctx(ctx, 0x402000, 1); - cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); - switch (device->chipset) { - case 0x40: - gr_def(ctx, 0x402404, 0x00000001); - break; - case 0x4c: - case 0x4e: - case 0x67: - gr_def(ctx, 0x402404, 0x00000020); - break; - case 0x46: - case 0x49: - case 0x4b: - gr_def(ctx, 0x402404, 0x00000421); - break; - default: - gr_def(ctx, 0x402404, 0x00000021); - } - if (device->chipset != 0x40) - gr_def(ctx, 0x402408, 0x030c30c3); - switch (device->chipset) { - case 0x44: - case 0x46: - case 0x4a: - case 0x4c: - case 0x4e: - case 0x67: - cp_ctx(ctx, 0x402440, 1); - gr_def(ctx, 0x402440, 0x00011001); - break; - default: - break; - } - cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); - gr_def(ctx, 0x402488, 0x3e020200); - gr_def(ctx, 0x40248c, 0x00ffffff); - switch (device->chipset) { - case 0x40: - gr_def(ctx, 0x402490, 0x60103f00); - break; - case 0x47: - gr_def(ctx, 0x402490, 0x40103f00); - break; - case 0x41: - case 0x42: - case 0x49: - case 0x4b: - gr_def(ctx, 0x402490, 0x20103f00); - break; - default: - gr_def(ctx, 0x402490, 0x0c103f00); - break; - } - gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? - 0x00020000 : 0x00040000); - cp_ctx(ctx, 0x402500, 31); - gr_def(ctx, 0x402530, 0x00008100); - if (device->chipset == 0x40) - cp_ctx(ctx, 0x40257c, 6); - cp_ctx(ctx, 0x402594, 16); - cp_ctx(ctx, 0x402800, 17); - gr_def(ctx, 0x402800, 0x00000001); - switch (device->chipset) { - case 0x47: - case 0x49: - case 0x4b: - cp_ctx(ctx, 0x402864, 1); - gr_def(ctx, 0x402864, 0x00001001); - cp_ctx(ctx, 0x402870, 3); - gr_def(ctx, 0x402878, 0x00000003); - if (device->chipset != 0x47) { /* belong at end!! */ - cp_ctx(ctx, 0x402900, 1); - cp_ctx(ctx, 0x402940, 1); - cp_ctx(ctx, 0x402980, 1); - cp_ctx(ctx, 0x4029c0, 1); - cp_ctx(ctx, 0x402a00, 1); - cp_ctx(ctx, 0x402a40, 1); - cp_ctx(ctx, 0x402a80, 1); - cp_ctx(ctx, 0x402ac0, 1); - } - break; - case 0x40: - cp_ctx(ctx, 0x402844, 1); - gr_def(ctx, 0x402844, 0x00000001); - cp_ctx(ctx, 0x402850, 1); - break; - default: - cp_ctx(ctx, 0x402844, 1); - gr_def(ctx, 0x402844, 0x00001001); - cp_ctx(ctx, 0x402850, 2); - gr_def(ctx, 0x402854, 0x00000003); - break; - } - - cp_ctx(ctx, 0x402c00, 4); - gr_def(ctx, 0x402c00, device->chipset == 0x40 ? - 0x80800001 : 0x00888001); - switch (device->chipset) { - case 0x47: - case 0x49: - case 0x4b: - cp_ctx(ctx, 0x402c20, 40); - for (i = 0; i < 32; i++) - gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); - cp_ctx(ctx, 0x4030b8, 13); - gr_def(ctx, 0x4030dc, 0x00000005); - gr_def(ctx, 0x4030e8, 0x0000ffff); - break; - default: - cp_ctx(ctx, 0x402c10, 4); - if (device->chipset == 0x40) - cp_ctx(ctx, 0x402c20, 36); - else - if (device->chipset <= 0x42) - cp_ctx(ctx, 0x402c20, 24); - else - if (device->chipset <= 0x4a) - cp_ctx(ctx, 0x402c20, 16); - else - cp_ctx(ctx, 0x402c20, 8); - cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); - gr_def(ctx, 0x402cd4, 0x00000005); - if (device->chipset != 0x40) - gr_def(ctx, 0x402ce0, 0x0000ffff); - break; - } - - cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); - cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); - cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device)); - for (i = 0; i < nv40_graph_vs_count(ctx->device); i++) - gr_def(ctx, 0x403420 + (i * 4), 0x00005555); - - if (device->chipset != 0x40) { - cp_ctx(ctx, 0x403600, 1); - gr_def(ctx, 0x403600, 0x00000001); - } - cp_ctx(ctx, 0x403800, 1); - - cp_ctx(ctx, 0x403c18, 1); - gr_def(ctx, 0x403c18, 0x00000001); - switch (device->chipset) { - case 0x46: - case 0x47: - case 0x49: - case 0x4b: - cp_ctx(ctx, 0x405018, 1); - gr_def(ctx, 0x405018, 0x08e00001); - cp_ctx(ctx, 0x405c24, 1); - gr_def(ctx, 0x405c24, 0x000e3000); - break; - } - if (device->chipset != 0x4e) - cp_ctx(ctx, 0x405800, 11); - cp_ctx(ctx, 0x407000, 1); -} - -static void -nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) -{ - int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684; - - cp_out (ctx, 0x300000); - cp_lsr (ctx, len - 4); - cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); - cp_lsr (ctx, len); - cp_name(ctx, cp_swap_state3d_3_is_save); - cp_out (ctx, 0x800001); - - ctx->ctxvals_pos += len; -} - -static void -nv40_graph_construct_shader(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - struct nouveau_gpuobj *obj = ctx->data; - int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; - int offset, i; - - vs_nr = nv40_graph_vs_count(ctx->device); - vs_nr_b0 = 363; - vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; - if (device->chipset == 0x40) { - b0_offset = 0x2200/4; /* 33a0 */ - b1_offset = 0x55a0/4; /* 1500 */ - vs_len = 0x6aa0/4; - } else - if (device->chipset == 0x41 || device->chipset == 0x42) { - b0_offset = 0x2200/4; /* 2200 */ - b1_offset = 0x4400/4; /* 0b00 */ - vs_len = 0x4f00/4; - } else { - b0_offset = 0x1d40/4; /* 2200 */ - b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ - vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4; - } - - cp_lsr(ctx, vs_len * vs_nr + 0x300/4); - cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041); - - offset = ctx->ctxvals_pos; - ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); - - if (ctx->mode != NOUVEAU_GRCTX_VALS) - return; - - offset += 0x0280/4; - for (i = 0; i < 16; i++, offset += 2) - nv_wo32(obj, offset * 4, 0x3f800000); - - for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { - for (i = 0; i < vs_nr_b0 * 6; i += 6) - nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); - for (i = 0; i < vs_nr_b1 * 4; i += 4) - nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); - } -} - -static void -nv40_grctx_generate(struct nouveau_grctx *ctx) -{ - /* decide whether we're loading/unloading the context */ - cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); - cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); - - cp_name(ctx, cp_check_load); - cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); - cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); - cp_bra (ctx, ALWAYS, TRUE, cp_exit); - - /* setup for context load */ - cp_name(ctx, cp_setup_auto_load); - cp_wait(ctx, STATUS, IDLE); - cp_out (ctx, CP_NEXT_TO_SWAP); - cp_name(ctx, cp_setup_load); - cp_wait(ctx, STATUS, IDLE); - cp_set (ctx, SWAP_DIRECTION, LOAD); - cp_out (ctx, 0x00910880); /* ?? */ - cp_out (ctx, 0x00901ffe); /* ?? */ - cp_out (ctx, 0x01940000); /* ?? */ - cp_lsr (ctx, 0x20); - cp_out (ctx, 0x0060000b); /* ?? */ - cp_wait(ctx, UNK57, CLEAR); - cp_out (ctx, 0x0060000c); /* ?? */ - cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); - - /* setup for context save */ - cp_name(ctx, cp_setup_save); - cp_set (ctx, SWAP_DIRECTION, SAVE); - - /* general PGRAPH state */ - cp_name(ctx, cp_swap_state); - cp_pos (ctx, 0x00020/4); - nv40_graph_construct_general(ctx); - cp_wait(ctx, STATUS, IDLE); - - /* 3D state, block 1 */ - cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); - nv40_graph_construct_state3d(ctx); - cp_wait(ctx, STATUS, IDLE); - - /* 3D state, block 2 */ - nv40_graph_construct_state3d_2(ctx); - - /* Some other block of "random" state */ - nv40_graph_construct_state3d_3(ctx); - - /* Per-vertex shader state */ - cp_pos (ctx, ctx->ctxvals_pos); - nv40_graph_construct_shader(ctx); - - /* pre-exit state updates */ - cp_name(ctx, cp_prepare_exit); - cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); - cp_bra (ctx, USER_SAVE, PENDING, cp_exit); - cp_out (ctx, CP_NEXT_TO_CURRENT); - - cp_name(ctx, cp_exit); - cp_set (ctx, USER_SAVE, NOT_PENDING); - cp_set (ctx, USER_LOAD, NOT_PENDING); - cp_out (ctx, CP_END); -} - -void -nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) -{ - nv40_grctx_generate(&(struct nouveau_grctx) { - .device = device, - .mode = NOUVEAU_GRCTX_VALS, - .data = mem, - }); -} - -int -nv40_grctx_init(struct nouveau_device *device, u32 *size) -{ - u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; - struct nouveau_grctx ctx = { - .device = device, - .mode = NOUVEAU_GRCTX_PROG, - .data = ctxprog, - .ctxprog_max = 256, - }; - - if (!ctxprog) - return -ENOMEM; - - nv40_grctx_generate(&ctx); - - nv_wr32(device, 0x400324, 0); - for (i = 0; i < ctx.ctxprog_len; i++) - nv_wr32(device, 0x400328, ctxprog[i]); - *size = ctx.ctxvals_pos * 4; - - kfree(ctxprog); - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c deleted file mode 100644 index 1d0e33fb5f61..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c +++ /dev/null @@ -1,3347 +0,0 @@ -/* - * Copyright 2009 Marcin Kościelnicki - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#define CP_FLAG_CLEAR 0 -#define CP_FLAG_SET 1 -#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) -#define CP_FLAG_SWAP_DIRECTION_LOAD 0 -#define CP_FLAG_SWAP_DIRECTION_SAVE 1 -#define CP_FLAG_UNK01 ((0 * 32) + 1) -#define CP_FLAG_UNK01_CLEAR 0 -#define CP_FLAG_UNK01_SET 1 -#define CP_FLAG_UNK03 ((0 * 32) + 3) -#define CP_FLAG_UNK03_CLEAR 0 -#define CP_FLAG_UNK03_SET 1 -#define CP_FLAG_USER_SAVE ((0 * 32) + 5) -#define CP_FLAG_USER_SAVE_NOT_PENDING 0 -#define CP_FLAG_USER_SAVE_PENDING 1 -#define CP_FLAG_USER_LOAD ((0 * 32) + 6) -#define CP_FLAG_USER_LOAD_NOT_PENDING 0 -#define CP_FLAG_USER_LOAD_PENDING 1 -#define CP_FLAG_UNK0B ((0 * 32) + 0xb) -#define CP_FLAG_UNK0B_CLEAR 0 -#define CP_FLAG_UNK0B_SET 1 -#define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe) -#define CP_FLAG_XFER_SWITCH_DISABLE 0 -#define CP_FLAG_XFER_SWITCH_ENABLE 1 -#define CP_FLAG_STATE ((0 * 32) + 0x1c) -#define CP_FLAG_STATE_STOPPED 0 -#define CP_FLAG_STATE_RUNNING 1 -#define CP_FLAG_UNK1D ((0 * 32) + 0x1d) -#define CP_FLAG_UNK1D_CLEAR 0 -#define CP_FLAG_UNK1D_SET 1 -#define CP_FLAG_UNK20 ((1 * 32) + 0) -#define CP_FLAG_UNK20_CLEAR 0 -#define CP_FLAG_UNK20_SET 1 -#define CP_FLAG_STATUS ((2 * 32) + 0) -#define CP_FLAG_STATUS_BUSY 0 -#define CP_FLAG_STATUS_IDLE 1 -#define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) -#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 -#define CP_FLAG_AUTO_SAVE_PENDING 1 -#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) -#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 -#define CP_FLAG_AUTO_LOAD_PENDING 1 -#define CP_FLAG_NEWCTX ((2 * 32) + 10) -#define CP_FLAG_NEWCTX_BUSY 0 -#define CP_FLAG_NEWCTX_DONE 1 -#define CP_FLAG_XFER ((2 * 32) + 11) -#define CP_FLAG_XFER_IDLE 0 -#define CP_FLAG_XFER_BUSY 1 -#define CP_FLAG_ALWAYS ((2 * 32) + 13) -#define CP_FLAG_ALWAYS_FALSE 0 -#define CP_FLAG_ALWAYS_TRUE 1 -#define CP_FLAG_INTR ((2 * 32) + 15) -#define CP_FLAG_INTR_NOT_PENDING 0 -#define CP_FLAG_INTR_PENDING 1 - -#define CP_CTX 0x00100000 -#define CP_CTX_COUNT 0x000f0000 -#define CP_CTX_COUNT_SHIFT 16 -#define CP_CTX_REG 0x00003fff -#define CP_LOAD_SR 0x00200000 -#define CP_LOAD_SR_VALUE 0x000fffff -#define CP_BRA 0x00400000 -#define CP_BRA_IP 0x0001ff00 -#define CP_BRA_IP_SHIFT 8 -#define CP_BRA_IF_CLEAR 0x00000080 -#define CP_BRA_FLAG 0x0000007f -#define CP_WAIT 0x00500000 -#define CP_WAIT_SET 0x00000080 -#define CP_WAIT_FLAG 0x0000007f -#define CP_SET 0x00700000 -#define CP_SET_1 0x00000080 -#define CP_SET_FLAG 0x0000007f -#define CP_NEWCTX 0x00600004 -#define CP_NEXT_TO_SWAP 0x00600005 -#define CP_SET_CONTEXT_POINTER 0x00600006 -#define CP_SET_XFER_POINTER 0x00600007 -#define CP_ENABLE 0x00600009 -#define CP_END 0x0060000c -#define CP_NEXT_TO_CURRENT 0x0060000d -#define CP_DISABLE1 0x0090ffff -#define CP_DISABLE2 0x0091ffff -#define CP_XFER_1 0x008000ff -#define CP_XFER_2 0x008800ff -#define CP_SEEK_1 0x00c000ff -#define CP_SEEK_2 0x00c800ff - -#include "nv50.h" -#include "ctx.h" - -#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) -#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) - -#include - -/* - * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's - * the GPU itself that does context-switching, but it needs a special - * microcode to do it. And it's the driver's task to supply this microcode, - * further known as ctxprog, as well as the initial context values, known - * as ctxvals. - * - * Without ctxprog, you cannot switch contexts. Not even in software, since - * the majority of context [xfer strands] isn't accessible directly. You're - * stuck with a single channel, and you also suffer all the problems resulting - * from missing ctxvals, since you cannot load them. - * - * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to - * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, - * since you don't have... some sort of needed setup. - * - * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since - * it's too much hassle to handle no-ctxprog as a special case. - */ - -/* - * How ctxprogs work. - * - * The ctxprog is written in its own kind of microcode, with very small and - * crappy set of available commands. You upload it to a small [512 insns] - * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to - * switch channel. or when the driver explicitely requests it. Stuff visible - * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, - * the per-channel context save area in VRAM [known as ctxvals or grctx], - * 4 flags registers, a scratch register, two grctx pointers, plus many - * random poorly-understood details. - * - * When ctxprog runs, it's supposed to check what operations are asked of it, - * save old context if requested, optionally reset PGRAPH and switch to the - * new channel, and load the new context. Context consists of three major - * parts: subset of MMIO registers and two "xfer areas". - */ - -/* TODO: - * - document unimplemented bits compared to nvidia - * - NVAx: make a TP subroutine, use it. - * - use 0x4008fc instead of 0x1540? - */ - -enum cp_label { - cp_check_load = 1, - cp_setup_auto_load, - cp_setup_load, - cp_setup_save, - cp_swap_state, - cp_prepare_exit, - cp_exit, -}; - -static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx); -static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx); -static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx); - -/* Main function: construct the ctxprog skeleton, call the other functions. */ - -static int -nv50_grctx_generate(struct nouveau_grctx *ctx) -{ - cp_set (ctx, STATE, RUNNING); - cp_set (ctx, XFER_SWITCH, ENABLE); - /* decide whether we're loading/unloading the context */ - cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); - cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); - - cp_name(ctx, cp_check_load); - cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); - cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); - cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit); - - /* setup for context load */ - cp_name(ctx, cp_setup_auto_load); - cp_out (ctx, CP_DISABLE1); - cp_out (ctx, CP_DISABLE2); - cp_out (ctx, CP_ENABLE); - cp_out (ctx, CP_NEXT_TO_SWAP); - cp_set (ctx, UNK01, SET); - cp_name(ctx, cp_setup_load); - cp_out (ctx, CP_NEWCTX); - cp_wait(ctx, NEWCTX, BUSY); - cp_set (ctx, UNK1D, CLEAR); - cp_set (ctx, SWAP_DIRECTION, LOAD); - cp_bra (ctx, UNK0B, SET, cp_prepare_exit); - cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); - - /* setup for context save */ - cp_name(ctx, cp_setup_save); - cp_set (ctx, UNK1D, SET); - cp_wait(ctx, STATUS, BUSY); - cp_wait(ctx, INTR, PENDING); - cp_bra (ctx, STATUS, BUSY, cp_setup_save); - cp_set (ctx, UNK01, SET); - cp_set (ctx, SWAP_DIRECTION, SAVE); - - /* general PGRAPH state */ - cp_name(ctx, cp_swap_state); - cp_set (ctx, UNK03, SET); - cp_pos (ctx, 0x00004/4); - cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ - cp_pos (ctx, 0x00100/4); - nv50_graph_construct_mmio(ctx); - nv50_graph_construct_xfer1(ctx); - nv50_graph_construct_xfer2(ctx); - - cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); - - cp_set (ctx, UNK20, SET); - cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ - cp_lsr (ctx, ctx->ctxvals_base); - cp_out (ctx, CP_SET_XFER_POINTER); - cp_lsr (ctx, 4); - cp_out (ctx, CP_SEEK_1); - cp_out (ctx, CP_XFER_1); - cp_wait(ctx, XFER, BUSY); - - /* pre-exit state updates */ - cp_name(ctx, cp_prepare_exit); - cp_set (ctx, UNK01, CLEAR); - cp_set (ctx, UNK03, CLEAR); - cp_set (ctx, UNK1D, CLEAR); - - cp_bra (ctx, USER_SAVE, PENDING, cp_exit); - cp_out (ctx, CP_NEXT_TO_CURRENT); - - cp_name(ctx, cp_exit); - cp_set (ctx, USER_SAVE, NOT_PENDING); - cp_set (ctx, USER_LOAD, NOT_PENDING); - cp_set (ctx, XFER_SWITCH, DISABLE); - cp_set (ctx, STATE, STOPPED); - cp_out (ctx, CP_END); - ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ - - return 0; -} - -void -nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) -{ - nv50_grctx_generate(&(struct nouveau_grctx) { - .device = device, - .mode = NOUVEAU_GRCTX_VALS, - .data = mem, - }); -} - -int -nv50_grctx_init(struct nouveau_device *device, u32 *size) -{ - u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; - struct nouveau_grctx ctx = { - .device = device, - .mode = NOUVEAU_GRCTX_PROG, - .data = ctxprog, - .ctxprog_max = 512, - }; - - if (!ctxprog) - return -ENOMEM; - nv50_grctx_generate(&ctx); - - nv_wr32(device, 0x400324, 0); - for (i = 0; i < ctx.ctxprog_len; i++) - nv_wr32(device, 0x400328, ctxprog[i]); - *size = ctx.ctxvals_pos * 4; - kfree(ctxprog); - return 0; -} - -/* - * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which - * registers to save/restore and the default values for them. - */ - -static void -nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx); - -static void -nv50_graph_construct_mmio(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i, j; - int offset, base; - u32 units = nv_rd32 (ctx->device, 0x1540); - - /* 0800: DISPATCH */ - cp_ctx(ctx, 0x400808, 7); - gr_def(ctx, 0x400814, 0x00000030); - cp_ctx(ctx, 0x400834, 0x32); - if (device->chipset == 0x50) { - gr_def(ctx, 0x400834, 0xff400040); - gr_def(ctx, 0x400838, 0xfff00080); - gr_def(ctx, 0x40083c, 0xfff70090); - gr_def(ctx, 0x400840, 0xffe806a8); - } - gr_def(ctx, 0x400844, 0x00000002); - if (IS_NVA3F(device->chipset)) - gr_def(ctx, 0x400894, 0x00001000); - gr_def(ctx, 0x4008e8, 0x00000003); - gr_def(ctx, 0x4008ec, 0x00001000); - if (device->chipset == 0x50) - cp_ctx(ctx, 0x400908, 0xb); - else if (device->chipset < 0xa0) - cp_ctx(ctx, 0x400908, 0xc); - else - cp_ctx(ctx, 0x400908, 0xe); - - if (device->chipset >= 0xa0) - cp_ctx(ctx, 0x400b00, 0x1); - if (IS_NVA3F(device->chipset)) { - cp_ctx(ctx, 0x400b10, 0x1); - gr_def(ctx, 0x400b10, 0x0001629d); - cp_ctx(ctx, 0x400b20, 0x1); - gr_def(ctx, 0x400b20, 0x0001629d); - } - - nv50_graph_construct_mmio_ddata(ctx); - - /* 0C00: VFETCH */ - cp_ctx(ctx, 0x400c08, 0x2); - gr_def(ctx, 0x400c08, 0x0000fe0c); - - /* 1000 */ - if (device->chipset < 0xa0) { - cp_ctx(ctx, 0x401008, 0x4); - gr_def(ctx, 0x401014, 0x00001000); - } else if (!IS_NVA3F(device->chipset)) { - cp_ctx(ctx, 0x401008, 0x5); - gr_def(ctx, 0x401018, 0x00001000); - } else { - cp_ctx(ctx, 0x401008, 0x5); - gr_def(ctx, 0x401018, 0x00004000); - } - - /* 1400 */ - cp_ctx(ctx, 0x401400, 0x8); - cp_ctx(ctx, 0x401424, 0x3); - if (device->chipset == 0x50) - gr_def(ctx, 0x40142c, 0x0001fd87); - else - gr_def(ctx, 0x40142c, 0x00000187); - cp_ctx(ctx, 0x401540, 0x5); - gr_def(ctx, 0x401550, 0x00001018); - - /* 1800: STREAMOUT */ - cp_ctx(ctx, 0x401814, 0x1); - gr_def(ctx, 0x401814, 0x000000ff); - if (device->chipset == 0x50) { - cp_ctx(ctx, 0x40181c, 0xe); - gr_def(ctx, 0x401850, 0x00000004); - } else if (device->chipset < 0xa0) { - cp_ctx(ctx, 0x40181c, 0xf); - gr_def(ctx, 0x401854, 0x00000004); - } else { - cp_ctx(ctx, 0x40181c, 0x13); - gr_def(ctx, 0x401864, 0x00000004); - } - - /* 1C00 */ - cp_ctx(ctx, 0x401c00, 0x1); - switch (device->chipset) { - case 0x50: - gr_def(ctx, 0x401c00, 0x0001005f); - break; - case 0x84: - case 0x86: - case 0x94: - gr_def(ctx, 0x401c00, 0x044d00df); - break; - case 0x92: - case 0x96: - case 0x98: - case 0xa0: - case 0xaa: - case 0xac: - gr_def(ctx, 0x401c00, 0x042500df); - break; - case 0xa3: - case 0xa5: - case 0xa8: - case 0xaf: - gr_def(ctx, 0x401c00, 0x142500df); - break; - } - - /* 2000 */ - - /* 2400 */ - cp_ctx(ctx, 0x402400, 0x1); - if (device->chipset == 0x50) - cp_ctx(ctx, 0x402408, 0x1); - else - cp_ctx(ctx, 0x402408, 0x2); - gr_def(ctx, 0x402408, 0x00000600); - - /* 2800: CSCHED */ - cp_ctx(ctx, 0x402800, 0x1); - if (device->chipset == 0x50) - gr_def(ctx, 0x402800, 0x00000006); - - /* 2C00: ZCULL */ - cp_ctx(ctx, 0x402c08, 0x6); - if (device->chipset != 0x50) - gr_def(ctx, 0x402c14, 0x01000000); - gr_def(ctx, 0x402c18, 0x000000ff); - if (device->chipset == 0x50) - cp_ctx(ctx, 0x402ca0, 0x1); - else - cp_ctx(ctx, 0x402ca0, 0x2); - if (device->chipset < 0xa0) - gr_def(ctx, 0x402ca0, 0x00000400); - else if (!IS_NVA3F(device->chipset)) - gr_def(ctx, 0x402ca0, 0x00000800); - else - gr_def(ctx, 0x402ca0, 0x00000400); - cp_ctx(ctx, 0x402cac, 0x4); - - /* 3000: ENG2D */ - cp_ctx(ctx, 0x403004, 0x1); - gr_def(ctx, 0x403004, 0x00000001); - - /* 3400 */ - if (device->chipset >= 0xa0) { - cp_ctx(ctx, 0x403404, 0x1); - gr_def(ctx, 0x403404, 0x00000001); - } - - /* 5000: CCACHE */ - cp_ctx(ctx, 0x405000, 0x1); - switch (device->chipset) { - case 0x50: - gr_def(ctx, 0x405000, 0x00300080); - break; - case 0x84: - case 0xa0: - case 0xa3: - case 0xa5: - case 0xa8: - case 0xaa: - case 0xac: - case 0xaf: - gr_def(ctx, 0x405000, 0x000e0080); - break; - case 0x86: - case 0x92: - case 0x94: - case 0x96: - case 0x98: - gr_def(ctx, 0x405000, 0x00000080); - break; - } - cp_ctx(ctx, 0x405014, 0x1); - gr_def(ctx, 0x405014, 0x00000004); - cp_ctx(ctx, 0x40501c, 0x1); - cp_ctx(ctx, 0x405024, 0x1); - cp_ctx(ctx, 0x40502c, 0x1); - - /* 6000? */ - if (device->chipset == 0x50) - cp_ctx(ctx, 0x4063e0, 0x1); - - /* 6800: M2MF */ - if (device->chipset < 0x90) { - cp_ctx(ctx, 0x406814, 0x2b); - gr_def(ctx, 0x406818, 0x00000f80); - gr_def(ctx, 0x406860, 0x007f0080); - gr_def(ctx, 0x40689c, 0x007f0080); - } else { - cp_ctx(ctx, 0x406814, 0x4); - if (device->chipset == 0x98) - gr_def(ctx, 0x406818, 0x00000f80); - else - gr_def(ctx, 0x406818, 0x00001f80); - if (IS_NVA3F(device->chipset)) - gr_def(ctx, 0x40681c, 0x00000030); - cp_ctx(ctx, 0x406830, 0x3); - } - - /* 7000: per-ROP group state */ - for (i = 0; i < 8; i++) { - if (units & (1<<(i+16))) { - cp_ctx(ctx, 0x407000 + (i<<8), 3); - if (device->chipset == 0x50) - gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); - else if (device->chipset != 0xa5) - gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); - else - gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); - gr_def(ctx, 0x407004 + (i<<8), 0x89058001); - - if (device->chipset == 0x50) { - cp_ctx(ctx, 0x407010 + (i<<8), 1); - } else if (device->chipset < 0xa0) { - cp_ctx(ctx, 0x407010 + (i<<8), 2); - gr_def(ctx, 0x407010 + (i<<8), 0x00001000); - gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); - } else { - cp_ctx(ctx, 0x407010 + (i<<8), 3); - gr_def(ctx, 0x407010 + (i<<8), 0x00001000); - if (device->chipset != 0xa5) - gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); - else - gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); - } - - cp_ctx(ctx, 0x407080 + (i<<8), 4); - if (device->chipset != 0xa5) - gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); - else - gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); - if (device->chipset == 0x50) - gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); - else - gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); - gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); - - if (device->chipset < 0xa0) - cp_ctx(ctx, 0x407094 + (i<<8), 1); - else if (!IS_NVA3F(device->chipset)) - cp_ctx(ctx, 0x407094 + (i<<8), 3); - else { - cp_ctx(ctx, 0x407094 + (i<<8), 4); - gr_def(ctx, 0x4070a0 + (i<<8), 1); - } - } - } - - cp_ctx(ctx, 0x407c00, 0x3); - if (device->chipset < 0x90) - gr_def(ctx, 0x407c00, 0x00010040); - else if (device->chipset < 0xa0) - gr_def(ctx, 0x407c00, 0x00390040); - else - gr_def(ctx, 0x407c00, 0x003d0040); - gr_def(ctx, 0x407c08, 0x00000022); - if (device->chipset >= 0xa0) { - cp_ctx(ctx, 0x407c10, 0x3); - cp_ctx(ctx, 0x407c20, 0x1); - cp_ctx(ctx, 0x407c2c, 0x1); - } - - if (device->chipset < 0xa0) { - cp_ctx(ctx, 0x407d00, 0x9); - } else { - cp_ctx(ctx, 0x407d00, 0x15); - } - if (device->chipset == 0x98) - gr_def(ctx, 0x407d08, 0x00380040); - else { - if (device->chipset < 0x90) - gr_def(ctx, 0x407d08, 0x00010040); - else if (device->chipset < 0xa0) - gr_def(ctx, 0x407d08, 0x00390040); - else { - if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) - gr_def(ctx, 0x407d08, 0x003d0040); - else - gr_def(ctx, 0x407d08, 0x003c0040); - } - gr_def(ctx, 0x407d0c, 0x00000022); - } - - /* 8000+: per-TP state */ - for (i = 0; i < 10; i++) { - if (units & (1<chipset < 0xa0) - base = 0x408000 + (i<<12); - else - base = 0x408000 + (i<<11); - if (device->chipset < 0xa0) - offset = base + 0xc00; - else - offset = base + 0x80; - cp_ctx(ctx, offset + 0x00, 1); - gr_def(ctx, offset + 0x00, 0x0000ff0a); - cp_ctx(ctx, offset + 0x08, 1); - - /* per-MP state */ - for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) { - if (!(units & (1 << (j+24)))) continue; - if (device->chipset < 0xa0) - offset = base + 0x200 + (j<<7); - else - offset = base + 0x100 + (j<<7); - cp_ctx(ctx, offset, 0x20); - gr_def(ctx, offset + 0x00, 0x01800000); - gr_def(ctx, offset + 0x04, 0x00160000); - gr_def(ctx, offset + 0x08, 0x01800000); - gr_def(ctx, offset + 0x18, 0x0003ffff); - switch (device->chipset) { - case 0x50: - gr_def(ctx, offset + 0x1c, 0x00080000); - break; - case 0x84: - gr_def(ctx, offset + 0x1c, 0x00880000); - break; - case 0x86: - gr_def(ctx, offset + 0x1c, 0x018c0000); - break; - case 0x92: - case 0x96: - case 0x98: - gr_def(ctx, offset + 0x1c, 0x118c0000); - break; - case 0x94: - gr_def(ctx, offset + 0x1c, 0x10880000); - break; - case 0xa0: - case 0xa5: - gr_def(ctx, offset + 0x1c, 0x310c0000); - break; - case 0xa3: - case 0xa8: - case 0xaa: - case 0xac: - case 0xaf: - gr_def(ctx, offset + 0x1c, 0x300c0000); - break; - } - gr_def(ctx, offset + 0x40, 0x00010401); - if (device->chipset == 0x50) - gr_def(ctx, offset + 0x48, 0x00000040); - else - gr_def(ctx, offset + 0x48, 0x00000078); - gr_def(ctx, offset + 0x50, 0x000000bf); - gr_def(ctx, offset + 0x58, 0x00001210); - if (device->chipset == 0x50) - gr_def(ctx, offset + 0x5c, 0x00000080); - else - gr_def(ctx, offset + 0x5c, 0x08000080); - if (device->chipset >= 0xa0) - gr_def(ctx, offset + 0x68, 0x0000003e); - } - - if (device->chipset < 0xa0) - cp_ctx(ctx, base + 0x300, 0x4); - else - cp_ctx(ctx, base + 0x300, 0x5); - if (device->chipset == 0x50) - gr_def(ctx, base + 0x304, 0x00007070); - else if (device->chipset < 0xa0) - gr_def(ctx, base + 0x304, 0x00027070); - else if (!IS_NVA3F(device->chipset)) - gr_def(ctx, base + 0x304, 0x01127070); - else - gr_def(ctx, base + 0x304, 0x05127070); - - if (device->chipset < 0xa0) - cp_ctx(ctx, base + 0x318, 1); - else - cp_ctx(ctx, base + 0x320, 1); - if (device->chipset == 0x50) - gr_def(ctx, base + 0x318, 0x0003ffff); - else if (device->chipset < 0xa0) - gr_def(ctx, base + 0x318, 0x03ffffff); - else - gr_def(ctx, base + 0x320, 0x07ffffff); - - if (device->chipset < 0xa0) - cp_ctx(ctx, base + 0x324, 5); - else - cp_ctx(ctx, base + 0x328, 4); - - if (device->chipset < 0xa0) { - cp_ctx(ctx, base + 0x340, 9); - offset = base + 0x340; - } else if (!IS_NVA3F(device->chipset)) { - cp_ctx(ctx, base + 0x33c, 0xb); - offset = base + 0x344; - } else { - cp_ctx(ctx, base + 0x33c, 0xd); - offset = base + 0x344; - } - gr_def(ctx, offset + 0x0, 0x00120407); - gr_def(ctx, offset + 0x4, 0x05091507); - if (device->chipset == 0x84) - gr_def(ctx, offset + 0x8, 0x05100202); - else - gr_def(ctx, offset + 0x8, 0x05010202); - gr_def(ctx, offset + 0xc, 0x00030201); - if (device->chipset == 0xa3) - cp_ctx(ctx, base + 0x36c, 1); - - cp_ctx(ctx, base + 0x400, 2); - gr_def(ctx, base + 0x404, 0x00000040); - cp_ctx(ctx, base + 0x40c, 2); - gr_def(ctx, base + 0x40c, 0x0d0c0b0a); - gr_def(ctx, base + 0x410, 0x00141210); - - if (device->chipset < 0xa0) - offset = base + 0x800; - else - offset = base + 0x500; - cp_ctx(ctx, offset, 6); - gr_def(ctx, offset + 0x0, 0x000001f0); - gr_def(ctx, offset + 0x4, 0x00000001); - gr_def(ctx, offset + 0x8, 0x00000003); - if (device->chipset == 0x50 || IS_NVAAF(device->chipset)) - gr_def(ctx, offset + 0xc, 0x00008000); - gr_def(ctx, offset + 0x14, 0x00039e00); - cp_ctx(ctx, offset + 0x1c, 2); - if (device->chipset == 0x50) - gr_def(ctx, offset + 0x1c, 0x00000040); - else - gr_def(ctx, offset + 0x1c, 0x00000100); - gr_def(ctx, offset + 0x20, 0x00003800); - - if (device->chipset >= 0xa0) { - cp_ctx(ctx, base + 0x54c, 2); - if (!IS_NVA3F(device->chipset)) - gr_def(ctx, base + 0x54c, 0x003fe006); - else - gr_def(ctx, base + 0x54c, 0x003fe007); - gr_def(ctx, base + 0x550, 0x003fe000); - } - - if (device->chipset < 0xa0) - offset = base + 0xa00; - else - offset = base + 0x680; - cp_ctx(ctx, offset, 1); - gr_def(ctx, offset, 0x00404040); - - if (device->chipset < 0xa0) - offset = base + 0xe00; - else - offset = base + 0x700; - cp_ctx(ctx, offset, 2); - if (device->chipset < 0xa0) - gr_def(ctx, offset, 0x0077f005); - else if (device->chipset == 0xa5) - gr_def(ctx, offset, 0x6cf7f007); - else if (device->chipset == 0xa8) - gr_def(ctx, offset, 0x6cfff007); - else if (device->chipset == 0xac) - gr_def(ctx, offset, 0x0cfff007); - else - gr_def(ctx, offset, 0x0cf7f007); - if (device->chipset == 0x50) - gr_def(ctx, offset + 0x4, 0x00007fff); - else if (device->chipset < 0xa0) - gr_def(ctx, offset + 0x4, 0x003f7fff); - else - gr_def(ctx, offset + 0x4, 0x02bf7fff); - cp_ctx(ctx, offset + 0x2c, 1); - if (device->chipset == 0x50) { - cp_ctx(ctx, offset + 0x50, 9); - gr_def(ctx, offset + 0x54, 0x000003ff); - gr_def(ctx, offset + 0x58, 0x00000003); - gr_def(ctx, offset + 0x5c, 0x00000003); - gr_def(ctx, offset + 0x60, 0x000001ff); - gr_def(ctx, offset + 0x64, 0x0000001f); - gr_def(ctx, offset + 0x68, 0x0000000f); - gr_def(ctx, offset + 0x6c, 0x0000000f); - } else if (device->chipset < 0xa0) { - cp_ctx(ctx, offset + 0x50, 1); - cp_ctx(ctx, offset + 0x70, 1); - } else { - cp_ctx(ctx, offset + 0x50, 1); - cp_ctx(ctx, offset + 0x60, 5); - } - } - } -} - -static void -dd_emit(struct nouveau_grctx *ctx, int num, u32 val) { - int i; - if (val && ctx->mode == NOUVEAU_GRCTX_VALS) - for (i = 0; i < num; i++) - nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); - ctx->ctxvals_pos += num; -} - -static void -nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int base, num; - base = ctx->ctxvals_pos; - - /* tesla state */ - dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */ - dd_emit(ctx, 1, 0); /* 00000001 UNK135C */ - - /* SRC_TIC state */ - dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */ - dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */ - dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */ - dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */ - dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */ - if (device->chipset >= 0x94) - dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */ - dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */ - dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */ - - /* turing state */ - dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */ - dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */ - dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ - dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ - dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ - dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ - dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */ - dd_emit(ctx, 1, 1); /* 00000001 LANES32 */ - dd_emit(ctx, 1, 0); /* 000000ff UNK370 */ - dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */ - dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */ - dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */ - dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ - dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ - dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ - dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */ - dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */ - dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */ - dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */ - dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */ - dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */ - dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */ - dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */ - if (IS_NVA3F(device->chipset)) - dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */ - dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */ - dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */ - dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */ - dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */ - dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */ - dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */ - dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */ - dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */ - - /* compat 2d state */ - if (device->chipset == 0x50) { - dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */ - - dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */ - - dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */ - dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */ - - dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */ - dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */ - dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */ - dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */ - dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */ - dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */ - dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */ - dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */ - dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */ - - dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */ - dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */ - dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */ - - dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */ - dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */ - - dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */ - - dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */ - dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */ - } - - /* m2mf state */ - dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */ - dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */ - dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */ - dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */ - dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */ - dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */ - dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */ - dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */ - dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */ - dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */ - dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */ - dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */ - dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */ - dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */ - dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */ - - /* more compat 2d state */ - if (device->chipset == 0x50) { - dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */ - - dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */ - - dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */ - dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */ - dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */ - dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */ - dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */ - dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */ - dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */ - dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */ - dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */ - dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */ - dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */ - - dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */ - } - - /* tesla state */ - dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */ - dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */ - dd_emit(ctx, 1, 0); /* 000000ff */ - dd_emit(ctx, 1, 0); /* ffffffff */ - dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */ - dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */ - dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */ - dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */ - dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */ - dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */ - if (IS_NVA3F(device->chipset)) { - dd_emit(ctx, 1, 0); /* ffffffff */ - dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */ - } else { - dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */ - } - dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */ - if (device->chipset != 0x50) - dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */ - dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */ - dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */ - if (device->chipset == 0x50) { - dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */ - dd_emit(ctx, 1, 0); /* 00000001 */ - } else { - dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */ - dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */ - dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */ - dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ - dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */ - dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */ - dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ - dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */ - } - dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */ - dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */ - dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */ - dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */ - dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */ - dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */ - dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */ - dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */ - dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */ - dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */ - dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ - dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */ - dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */ - if (device->chipset != 0x50) - dd_emit(ctx, 3, 0); /* 1, 1, 1 */ - else - dd_emit(ctx, 2, 0); /* 1, 1 */ - dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */ - dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/ - dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ - dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - if (IS_NVA3F(device->chipset)) { - dd_emit(ctx, 1, 3); /* 00000003 */ - dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */ - } - if (device->chipset != 0x50) - dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */ - dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */ - dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */ - if (device->chipset != 0x50) - dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */ - dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */ - dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */ - dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */ - dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */ - dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */ - dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */ - dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */ - dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ - dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ - dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ - if (device->chipset >= 0xa0) - dd_emit(ctx, 1, 0); /* ffffffff */ - dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */ - dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */ - dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ - dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ - dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/ - if (device->chipset != 0x50) - dd_emit(ctx, 8, 0); /* 00000001 */ - if (device->chipset >= 0xa0) { - dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */ - dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */ - dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */ - dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */ - } - dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */ - dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */ - dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */ - if (IS_NVA3F(device->chipset)) - dd_emit(ctx, 1, 0); /* 00000001 */ - dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */ - if (device->chipset >= 0xa0) - dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */ - dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ - if (device->chipset >= 0xa0) - dd_emit(ctx, 1, 0); /* 00000003 */ - dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */ - dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */ - dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */ - dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */ - dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */ - if (device->chipset != 0x50) { - dd_emit(ctx, 1, 0xe00); /* 7fff */ - dd_emit(ctx, 1, 0x1000); /* 7fff */ - dd_emit(ctx, 1, 0x1e00); /* 7fff */ - } - dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */ - dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */ - dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */ - dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */ - dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */ - dd_emit(ctx, 1, 1); /* 00000001 */ - dd_emit(ctx, 1, 0); /* 00000001 */ - dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */ - dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */ - dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */ - if (IS_NVA3F(device->chipset)) - dd_emit(ctx, 1, 0x200); - dd_emit(ctx, 1, 0); /* 00000001 */ - if (device->chipset < 0xa0) { - dd_emit(ctx, 1, 1); /* 00000001 */ - dd_emit(ctx, 1, 0x70); /* 000000ff */ - dd_emit(ctx, 1, 0x80); /* 000000ff */ - dd_emit(ctx, 1, 0); /* 000000ff */ - dd_emit(ctx, 1, 0); /* 00000001 */ - dd_emit(ctx, 1, 1); /* 00000001 */ - dd_emit(ctx, 1, 0x70); /* 000000ff */ - dd_emit(ctx, 1, 0x80); /* 000000ff */ - dd_emit(ctx, 1, 0); /* 000000ff */ - } else { - dd_emit(ctx, 1, 1); /* 00000001 */ - dd_emit(ctx, 1, 0xf0); /* 000000ff */ - dd_emit(ctx, 1, 0xff); /* 000000ff */ - dd_emit(ctx, 1, 0); /* 000000ff */ - dd_emit(ctx, 1, 0); /* 00000001 */ - dd_emit(ctx, 1, 1); /* 00000001 */ - dd_emit(ctx, 1, 0xf0); /* 000000ff */ - dd_emit(ctx, 1, 0xff); /* 000000ff */ - dd_emit(ctx, 1, 0); /* 000000ff */ - dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */ - } - - /* eng2d state */ - dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */ - dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */ - dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */ - dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */ - dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */ - dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */ - dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */ - dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */ - dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */ - dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */ - dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */ - dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */ - dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */ - dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */ - dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */ - dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */ - dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */ - dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */ - dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */ - dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */ - - num = ctx->ctxvals_pos - base; - ctx->ctxvals_pos = base; - if (IS_NVA3F(device->chipset)) - cp_ctx(ctx, 0x404800, num); - else - cp_ctx(ctx, 0x405400, num); -} - -/* - * xfer areas. These are a pain. - * - * There are 2 xfer areas: the first one is big and contains all sorts of - * stuff, the second is small and contains some per-TP context. - * - * Each area is split into 8 "strands". The areas, when saved to grctx, - * are made of 8-word blocks. Each block contains a single word from - * each strand. The strands are independent of each other, their - * addresses are unrelated to each other, and data in them is closely - * packed together. The strand layout varies a bit between cards: here - * and there, a single word is thrown out in the middle and the whole - * strand is offset by a bit from corresponding one on another chipset. - * For this reason, addresses of stuff in strands are almost useless. - * Knowing sequence of stuff and size of gaps between them is much more - * useful, and that's how we build the strands in our generator. - * - * NVA0 takes this mess to a whole new level by cutting the old strands - * into a few dozen pieces [known as genes], rearranging them randomly, - * and putting them back together to make new strands. Hopefully these - * genes correspond more or less directly to the same PGRAPH subunits - * as in 400040 register. - * - * The most common value in default context is 0, and when the genes - * are separated by 0's, gene bounduaries are quite speculative... - * some of them can be clearly deduced, others can be guessed, and yet - * others won't be resolved without figuring out the real meaning of - * given ctxval. For the same reason, ending point of each strand - * is unknown. Except for strand 0, which is the longest strand and - * its end corresponds to end of the whole xfer. - * - * An unsolved mystery is the seek instruction: it takes an argument - * in bits 8-18, and that argument is clearly the place in strands to - * seek to... but the offsets don't seem to correspond to offsets as - * seen in grctx. Perhaps there's another, real, not randomly-changing - * addressing in strands, and the xfer insn just happens to skip over - * the unused bits? NV10-NV30 PIPE comes to mind... - * - * As far as I know, there's no way to access the xfer areas directly - * without the help of ctxprog. - */ - -static void -xf_emit(struct nouveau_grctx *ctx, int num, u32 val) { - int i; - if (val && ctx->mode == NOUVEAU_GRCTX_VALS) - for (i = 0; i < num; i++) - nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); - ctx->ctxvals_pos += num << 3; -} - -/* Gene declarations... */ - -static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx); -static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx); - -static void -nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - int offset; - int size = 0; - u32 units = nv_rd32 (ctx->device, 0x1540); - - offset = (ctx->ctxvals_pos+0x3f)&~0x3f; - ctx->ctxvals_base = offset; - - if (device->chipset < 0xa0) { - /* Strand 0 */ - ctx->ctxvals_pos = offset; - nv50_graph_construct_gene_dispatch(ctx); - nv50_graph_construct_gene_m2mf(ctx); - nv50_graph_construct_gene_unk24xx(ctx); - nv50_graph_construct_gene_clipid(ctx); - nv50_graph_construct_gene_zcull(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 1 */ - ctx->ctxvals_pos = offset + 0x1; - nv50_graph_construct_gene_vfetch(ctx); - nv50_graph_construct_gene_eng2d(ctx); - nv50_graph_construct_gene_csched(ctx); - nv50_graph_construct_gene_ropm1(ctx); - nv50_graph_construct_gene_ropm2(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 2 */ - ctx->ctxvals_pos = offset + 0x2; - nv50_graph_construct_gene_ccache(ctx); - nv50_graph_construct_gene_unk1cxx(ctx); - nv50_graph_construct_gene_strmout(ctx); - nv50_graph_construct_gene_unk14xx(ctx); - nv50_graph_construct_gene_unk10xx(ctx); - nv50_graph_construct_gene_unk34xx(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 3: per-ROP group state */ - ctx->ctxvals_pos = offset + 3; - for (i = 0; i < 6; i++) - if (units & (1 << (i + 16))) - nv50_graph_construct_gene_ropc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strands 4-7: per-TP state */ - for (i = 0; i < 4; i++) { - ctx->ctxvals_pos = offset + 4 + i; - if (units & (1 << (2 * i))) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << (2 * i + 1))) - nv50_graph_construct_xfer_tp(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - } - } else { - /* Strand 0 */ - ctx->ctxvals_pos = offset; - nv50_graph_construct_gene_dispatch(ctx); - nv50_graph_construct_gene_m2mf(ctx); - nv50_graph_construct_gene_unk34xx(ctx); - nv50_graph_construct_gene_csched(ctx); - nv50_graph_construct_gene_unk1cxx(ctx); - nv50_graph_construct_gene_strmout(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 1 */ - ctx->ctxvals_pos = offset + 1; - nv50_graph_construct_gene_unk10xx(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 2 */ - ctx->ctxvals_pos = offset + 2; - if (device->chipset == 0xa0) - nv50_graph_construct_gene_unk14xx(ctx); - nv50_graph_construct_gene_unk24xx(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 3 */ - ctx->ctxvals_pos = offset + 3; - nv50_graph_construct_gene_vfetch(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 4 */ - ctx->ctxvals_pos = offset + 4; - nv50_graph_construct_gene_ccache(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 5 */ - ctx->ctxvals_pos = offset + 5; - nv50_graph_construct_gene_ropm2(ctx); - nv50_graph_construct_gene_ropm1(ctx); - /* per-ROP context */ - for (i = 0; i < 8; i++) - if (units & (1<<(i+16))) - nv50_graph_construct_gene_ropc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 6 */ - ctx->ctxvals_pos = offset + 6; - nv50_graph_construct_gene_zcull(ctx); - nv50_graph_construct_gene_clipid(ctx); - nv50_graph_construct_gene_eng2d(ctx); - if (units & (1 << 0)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 1)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 2)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 3)) - nv50_graph_construct_xfer_tp(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 7 */ - ctx->ctxvals_pos = offset + 7; - if (device->chipset == 0xa0) { - if (units & (1 << 4)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 5)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 6)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 7)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 8)) - nv50_graph_construct_xfer_tp(ctx); - if (units & (1 << 9)) - nv50_graph_construct_xfer_tp(ctx); - } else { - nv50_graph_construct_gene_unk14xx(ctx); - } - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - } - - ctx->ctxvals_pos = offset + size * 8; - ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; - cp_lsr (ctx, offset); - cp_out (ctx, CP_SET_XFER_POINTER); - cp_lsr (ctx, size); - cp_out (ctx, CP_SEEK_1); - cp_out (ctx, CP_XFER_1); - cp_wait(ctx, XFER, BUSY); -} - -/* - * non-trivial demagiced parts of ctx init go here - */ - -static void -nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx) -{ - /* start of strand 0 */ - struct nouveau_device *device = ctx->device; - /* SEEK */ - if (device->chipset == 0x50) - xf_emit(ctx, 5, 0); - else if (!IS_NVA3F(device->chipset)) - xf_emit(ctx, 6, 0); - else - xf_emit(ctx, 4, 0); - /* SEEK */ - /* the PGRAPH's internal FIFO */ - if (device->chipset == 0x50) - xf_emit(ctx, 8*3, 0); - else - xf_emit(ctx, 0x100*3, 0); - /* and another bonus slot?!? */ - xf_emit(ctx, 3, 0); - /* and YET ANOTHER bonus slot? */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 3, 0); - /* SEEK */ - /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */ - xf_emit(ctx, 9, 0); - /* SEEK */ - xf_emit(ctx, 9, 0); - /* SEEK */ - xf_emit(ctx, 9, 0); - /* SEEK */ - xf_emit(ctx, 9, 0); - /* SEEK */ - if (device->chipset < 0x90) - xf_emit(ctx, 4, 0); - /* SEEK */ - xf_emit(ctx, 2, 0); - /* SEEK */ - xf_emit(ctx, 6*2, 0); - xf_emit(ctx, 2, 0); - /* SEEK */ - xf_emit(ctx, 2, 0); - /* SEEK */ - xf_emit(ctx, 6*2, 0); - xf_emit(ctx, 2, 0); - /* SEEK */ - if (device->chipset == 0x50) - xf_emit(ctx, 0x1c, 0); - else if (device->chipset < 0xa0) - xf_emit(ctx, 0x1e, 0); - else - xf_emit(ctx, 0x22, 0); - /* SEEK */ - xf_emit(ctx, 0x15, 0); -} - -static void -nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx) -{ - /* Strand 0, right after dispatch */ - struct nouveau_device *device = ctx->device; - int smallm2mf = 0; - if (device->chipset < 0x92 || device->chipset == 0x98) - smallm2mf = 1; - /* SEEK */ - xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ - xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ - xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ - xf_emit (ctx, 1, 0); /* OFFSET_IN */ - xf_emit (ctx, 1, 0); /* OFFSET_OUT */ - xf_emit (ctx, 1, 0); /* PITCH_IN */ - xf_emit (ctx, 1, 0); /* PITCH_OUT */ - xf_emit (ctx, 1, 0); /* LINE_LENGTH */ - xf_emit (ctx, 1, 0); /* LINE_COUNT */ - xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ - xf_emit (ctx, 1, 1); /* LINEAR_IN */ - xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ - xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ - xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ - xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ - xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ - xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ - xf_emit (ctx, 1, 1); /* LINEAR_OUT */ - xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ - xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ - xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ - xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ - xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ - xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ - xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ - xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ - /* SEEK */ - if (smallm2mf) - xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */ - else - xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */ - xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */ - /* SEEK */ - if (smallm2mf) - xf_emit(ctx, 0x400, 0); /* ffffffff */ - else - xf_emit(ctx, 0x800, 0); /* ffffffff */ - xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */ - /* SEEK */ - xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */ - xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */ -} - -static void -nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - xf_emit(ctx, 2, 0); /* RO */ - xf_emit(ctx, 0x800, 0); /* ffffffff */ - switch (device->chipset) { - case 0x50: - case 0x92: - case 0xa0: - xf_emit(ctx, 0x2b, 0); - break; - case 0x84: - xf_emit(ctx, 0x29, 0); - break; - case 0x94: - case 0x96: - case 0xa3: - xf_emit(ctx, 0x27, 0); - break; - case 0x86: - case 0x98: - case 0xa5: - case 0xa8: - case 0xaa: - case 0xac: - case 0xaf: - xf_emit(ctx, 0x25, 0); - break; - } - /* CB bindings, 0x80 of them. first word is address >> 8, second is - * size >> 4 | valid << 24 */ - xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */ - xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */ - xf_emit(ctx, 1, 0); /* 0 */ - xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */ - xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */ - xf_emit(ctx, 4, 0); /* RO */ - xf_emit(ctx, 0x100, 0); /* ffffffff */ - xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */ - xf_emit(ctx, 8, 0); /* ffffffff */ - xf_emit(ctx, 4, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 3 */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */ - xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ - xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */ - xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ - xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */ - xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ - xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */ - xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */ - xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */ - xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */ - xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ - xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */ -} - -static void -nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - /* end of area 2 on pre-NVA0, area 1 on NVAx */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ - xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ - if (device->chipset == 0x50) - xf_emit(ctx, 1, 0x3ff); - else - xf_emit(ctx, 1, 0x7ff); /* 000007ff */ - xf_emit(ctx, 1, 0); /* 111/113 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - for (i = 0; i < 8; i++) { - switch (device->chipset) { - case 0x50: - case 0x86: - case 0x98: - case 0xaa: - case 0xac: - xf_emit(ctx, 0xa0, 0); /* ffffffff */ - break; - case 0x84: - case 0x92: - case 0x94: - case 0x96: - xf_emit(ctx, 0x120, 0); - break; - case 0xa5: - case 0xa8: - xf_emit(ctx, 0x100, 0); /* ffffffff */ - break; - case 0xa0: - case 0xa3: - case 0xaf: - xf_emit(ctx, 0x400, 0); /* ffffffff */ - break; - } - xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */ - xf_emit(ctx, 4, 0); /* ffffffff */ - } - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ - xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */ - xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ -} - -static void -nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - /* end of area 2 on pre-NVA0, area 1 on NVAx */ - xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ - xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ - xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */ - xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ - xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */ - xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ - xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ - xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 0x0fac6881); - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 1); - xf_emit(ctx, 3, 0); - } -} - -static void -nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ - if (device->chipset != 0x50) { - xf_emit(ctx, 5, 0); /* ffffffff */ - xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 2, 4); /* 7f, ff */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - } - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 0); /* 3ff */ - xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ - xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ - xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */ - xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0); /* 0000000f */ - if (device->chipset == 0x50) - xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ - else - xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ - xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ - xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */ - xf_emit(ctx, 3, 0); /* f, 0, 0 */ - xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ - xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */ - xf_emit(ctx, 3, 0); /* f, 0, 0 */ - xf_emit(ctx, 3, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ - xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ - xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ - xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ - xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0); /* 0000000f */ - xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ - xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ - if (device->chipset != 0x50) { - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - } - xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */ - xf_emit(ctx, 1, 0); /* f */ - xf_emit(ctx, 1, 0); /* 0? */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 003fffff */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ - xf_emit(ctx, 1, 0); /* 0000000f */ -} - -static void -nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ - /* SEEK */ - xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ - xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ - xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ - xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ - xf_emit(ctx, 1, 0); /* 0000ffff */ - xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */ - xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ - xf_emit(ctx, 1, 0); /* 00000007 */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */ - xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ - /* SEEK */ - xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ - xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ - xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ - xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ - xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ - xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */ -} - -static void -nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx) -{ - /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */ - /* SEEK */ - xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */ - xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */ - xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ - xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */ - xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ - xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */ - xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */ - xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */ - xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */ -} - -static void -nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ - /* SEEK */ - xf_emit(ctx, 0x33, 0); - /* SEEK */ - xf_emit(ctx, 2, 0); - /* SEEK */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - /* SEEK */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 4, 0); /* RO */ - xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ - xf_emit(ctx, 1, 0); /* 1ff */ - xf_emit(ctx, 8, 0); /* 0? */ - xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ - - xf_emit(ctx, 4, 0); /* RO */ - xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ - xf_emit(ctx, 1, 0); /* 1ff */ - xf_emit(ctx, 8, 0); /* 0? */ - xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ - } else { - xf_emit(ctx, 0xc, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ - xf_emit(ctx, 1, 0); /* 1ff */ - xf_emit(ctx, 8, 0); /* 0? */ - - /* SEEK */ - xf_emit(ctx, 0xc, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ - xf_emit(ctx, 1, 0); /* 1ff */ - xf_emit(ctx, 8, 0); /* 0? */ - } - /* SEEK */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ - xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ - xf_emit(ctx, 1, 1); /* 00000001 */ - /* SEEK */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 2, 4); /* 000000ff */ - xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f */ - xf_emit(ctx, 1, 1); /* 00000001 */ - for (i = 0; i < 10; i++) { - /* SEEK */ - xf_emit(ctx, 0x40, 0); /* ffffffff */ - xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */ - xf_emit(ctx, 0x10, 0); /* ffffffff */ - } - /* SEEK */ - xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */ - xf_emit(ctx, 1, 1); /* 00000001 */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ - xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */ - xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 0); /* 000003ff */ -} - -static void -nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int acnt = 0x10, rep, i; - /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ - if (IS_NVA3F(device->chipset)) - acnt = 0x20; - /* SEEK */ - if (device->chipset >= 0xa0) { - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */ - xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */ - } - xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */ - xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */ - xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */ - xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */ - xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ - xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */ - xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */ - xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - /* SEEK */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0xb, 0); /* RO */ - else if (device->chipset >= 0xa0) - xf_emit(ctx, 0x9, 0); /* RO */ - else - xf_emit(ctx, 0x8, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */ - xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ - /* SEEK */ - xf_emit(ctx, 0xc, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* 7f/ff */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ - xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */ - xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - if (device->chipset == 0x50) - xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */ - else - xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */ - if (device->chipset == 0xa8) - xf_emit(ctx, 1, 0x1e00); /* 7fff */ - /* SEEK */ - xf_emit(ctx, 0xc, 0); /* RO or close */ - /* SEEK */ - xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ - if (device->chipset > 0x50 && device->chipset < 0xa0) - xf_emit(ctx, 2, 0); /* ffffffff */ - else - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */ - /* SEEK */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 0x10, 0); /* 0? */ - xf_emit(ctx, 2, 0); /* weird... */ - xf_emit(ctx, 2, 0); /* RO */ - } else { - xf_emit(ctx, 8, 0); /* 0? */ - xf_emit(ctx, 1, 0); /* weird... */ - xf_emit(ctx, 2, 0); /* RO */ - } - /* SEEK */ - xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */ - xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */ - xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ - xf_emit(ctx, 1, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ - xf_emit(ctx, 1, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* RO */ - xf_emit(ctx, 2, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */ - xf_emit(ctx, 1, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */ - xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */ - xf_emit(ctx, 3, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */ - xf_emit(ctx, 3, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */ - xf_emit(ctx, 3, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */ - xf_emit(ctx, 3, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */ - xf_emit(ctx, 3, 0); /* f/1f */ - /* SEEK */ - xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */ - xf_emit(ctx, 3, 0); /* f/1f */ - /* SEEK */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, acnt, 0); /* f */ - xf_emit(ctx, 3, 0); /* f/1f */ - } - /* SEEK */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 2, 0); /* RO */ - else - xf_emit(ctx, 5, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */ - /* SEEK */ - if (device->chipset < 0xa0) { - xf_emit(ctx, 0x41, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 0x11, 0); /* RO */ - } else if (!IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x50, 0); /* RO */ - else - xf_emit(ctx, 0x58, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, 1, 1); /* 1 UNK0DEC */ - /* SEEK */ - xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */ - xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */ - /* SEEK */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x1d, 0); /* RO */ - else - xf_emit(ctx, 0x16, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ - /* SEEK */ - if (device->chipset < 0xa0) - xf_emit(ctx, 8, 0); /* RO */ - else if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0xc, 0); /* RO */ - else - xf_emit(ctx, 7, 0); /* RO */ - /* SEEK */ - xf_emit(ctx, 0xa, 0); /* RO */ - if (device->chipset == 0xa0) - rep = 0xc; - else - rep = 4; - for (i = 0; i < rep; i++) { - /* SEEK */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x20, 0); /* ffffffff */ - xf_emit(ctx, 0x200, 0); /* ffffffff */ - xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */ - xf_emit(ctx, 4, 0); /* ffffffff */ - } - /* SEEK */ - xf_emit(ctx, 1, 0); /* 113/111 */ - xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ - xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */ - xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - /* SEEK */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 7, 0); /* weird... */ - else - xf_emit(ctx, 5, 0); /* weird... */ -} - -static void -nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ - /* SEEK */ - xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ - xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */ - xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */ - if (device->chipset < 0xa0) { - /* this is useless on everything but the original NV50, - * guess they forgot to nuke it. Or just didn't bother. */ - xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */ - xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */ - xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */ - } - xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ - xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ - xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ - xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */ - xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */ - xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */ - xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */ - xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */ - xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */ - xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */ - xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */ - xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */ - xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */ - xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */ - xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */ - xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */ - xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ - xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */ - xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */ - xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */ - xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */ - xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */ - xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ - xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ - xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ - xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ - xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */ - xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */ - xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */ - xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */ - xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */ - xf_emit(ctx, 1, 0); /* 00000001 UNK888 */ - xf_emit(ctx, 1, 4); /* 0000003f UNK884 */ - xf_emit(ctx, 1, 0); /* 00000007 UNK880 */ - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */ - xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */ - xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */ - xf_emit(ctx, 1, 0); /* 00000001 UNK260 */ - xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */ - /* SEEK */ - xf_emit(ctx, 0x10, 0); - /* SEEK */ - xf_emit(ctx, 0x27, 0); -} - -static void -nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ - /* SEEK */ - xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ - xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 0); /* 000003ff */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */ - xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */ - xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */ - xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */ - xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */ - xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */ - xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ - xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ - xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ - xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ - xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ - xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ - /* SEEK */ - xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */ - switch (device->chipset) { - case 0x50: - case 0x92: - xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ - xf_emit(ctx, 0x80, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */ - break; - case 0x84: - xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ - xf_emit(ctx, 0x60, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ - break; - case 0x94: - case 0x96: - xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ - xf_emit(ctx, 0x40, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */ - break; - case 0x86: - case 0x98: - xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ - xf_emit(ctx, 0x10, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ - break; - case 0xa0: - xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ - xf_emit(ctx, 0xf0, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */ - break; - case 0xa3: - xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ - xf_emit(ctx, 0x60, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ - break; - case 0xa5: - case 0xaf: - xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ - xf_emit(ctx, 0x30, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */ - break; - case 0xaa: - xf_emit(ctx, 0x12, 0); - break; - case 0xa8: - case 0xac: - xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ - xf_emit(ctx, 0x10, 0); /* fff */ - xf_emit(ctx, 2, 0); /* ff, fff */ - xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ - break; - } - xf_emit(ctx, 1, 0); /* 0000000f */ - xf_emit(ctx, 1, 0); /* 00000000 */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 0000001f */ - xf_emit(ctx, 4, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 4, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 000000ff */ -} - -static void -nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ - xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ - xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ - xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */ - xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ - xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ - xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */ - xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ - xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ - xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */ - else if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */ - xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ - xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ - xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ - xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */ - xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ - xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */ - if (device->chipset != 0x50) { - xf_emit(ctx, 1, 0); /* 3ff */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */ - } - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ - xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ - xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ - xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */ - xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ - xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */ - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ - xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ - if (device->chipset < 0xa0) - xf_emit(ctx, 0x1c, 0); /* RO */ - else if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x9, 0); - xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ - xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ - if (device->chipset != 0x50) { - xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ - xf_emit(ctx, 1, 0); /* 3ff */ - } - /* XXX: the following block could belong either to unk1cxx, or - * to STRMOUT. Rather hard to tell. */ - if (device->chipset < 0xa0) - xf_emit(ctx, 0x25, 0); - else - xf_emit(ctx, 0x3b, 0); -} - -static void -nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ - xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ - xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ - if (device->chipset >= 0xa0) { - xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ - xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ - } - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - if (device->chipset == 0x50) - xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ - else - xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - /* SEEK */ - xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ - xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ - xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */ - xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */ - xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ - if (device->chipset >= 0xa0) { - xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ - xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ - } - xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ - xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ - xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */ - xf_emit(ctx, 2, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - /* SEEK */ - xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */ - xf_emit(ctx, 1, 0); /* 0000000f */ - xf_emit(ctx, 1, 0); /* 00000000? */ - xf_emit(ctx, 2, 0); /* ffffffff */ -} - -static void -nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ - xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ -} - -static void -nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - /* SEEK */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 2, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ - xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ - xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ - xf_emit(ctx, 1, 0); /* 7 */ - /* SEEK */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ - xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ - xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ - xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ - xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ - xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 0); /* 00000007 */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ -} - -static void -nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int magic2; - if (device->chipset == 0x50) { - magic2 = 0x00003e60; - } else if (!IS_NVA3F(device->chipset)) { - magic2 = 0x001ffe67; - } else { - magic2 = 0x00087e67; - } - xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset)) - xf_emit(ctx, 1, 0x15); /* 000000ff */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ - xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) { - xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */ - xf_emit(ctx, 1, 4); /* 7 */ - xf_emit(ctx, 1, 0x400); /* fffffff */ - xf_emit(ctx, 1, 0x300); /* ffff */ - xf_emit(ctx, 1, 0x1001); /* 1fff */ - if (device->chipset != 0xa0) { - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */ - else - xf_emit(ctx, 1, 0x15); /* ff */ - } - } - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ - xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ - xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ - xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ - xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ - if (device->chipset >= 0xa0) { - xf_emit(ctx, 2, 0); - xf_emit(ctx, 1, 0x1001); - xf_emit(ctx, 0xb, 0); - } else { - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - } - xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 1, 0x11); /* 3f/7f */ - xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ - if (device->chipset != 0x50) { - xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ - xf_emit(ctx, 1, 0); /* 000000ff */ - } - xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ - xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */ - xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ - xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ - xf_emit(ctx, 2, 0); /* 00000001 */ - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* 0000000f */ - xf_emit(ctx, 1, 0); /* 00000003 */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 2, 0); /* 00000001 */ - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - } else if (device->chipset >= 0xa0) { - xf_emit(ctx, 2, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* 00000003 */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 2, 0); /* 00000001 */ - } else { - xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - } - xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */ - xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */ - xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 2, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ - xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ - xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */ - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ - } - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ - xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */ - xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */ - xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */ - xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */ - xf_emit(ctx, 1, 0); /* 000000ff ROP */ - xf_emit(ctx, 1, 0); /* ffffffff BETA1 */ - xf_emit(ctx, 1, 0); /* ffffffff BETA4 */ - xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ - xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */ -} - -static void -nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int magic3; - switch (device->chipset) { - case 0x50: - magic3 = 0x1000; - break; - case 0x86: - case 0x98: - case 0xa8: - case 0xaa: - case 0xac: - case 0xaf: - magic3 = 0x1e00; - break; - default: - magic3 = 0; - } - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x1f, 0); /* ffffffff */ - else if (device->chipset >= 0xa0) - xf_emit(ctx, 0x0f, 0); /* ffffffff */ - else - xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */ - xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 0x03020100); /* ffffffff */ - else - xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ - if (magic3) - xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0); /* 111/113 */ - xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */ - xf_emit(ctx, 1, 0); /* 0000001f */ - xf_emit(ctx, 1, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */ - xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ - if (magic3) - xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0); /* 111/113 */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ - xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */ - xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - xf_emit(ctx, 1, 0); /* 111/113 */ - if (device->chipset == 0x94 || device->chipset == 0x96) - xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ - else if (device->chipset < 0xa0) - xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ - else if (!IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x210, 0); /* ffffffff */ - else - xf_emit(ctx, 0x410, 0); /* ffffffff */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ - xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ - xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ -} - -static void -nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int magic1, magic2; - if (device->chipset == 0x50) { - magic1 = 0x3ff; - magic2 = 0x00003e60; - } else if (!IS_NVA3F(device->chipset)) { - magic1 = 0x7ff; - magic2 = 0x001ffe67; - } else { - magic1 = 0x7ff; - magic2 = 0x00087e67; - } - xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */ - xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */ - xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ - xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */ - xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ - xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ - xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ - xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ - xf_emit(ctx, 1, 0); /* 7 */ - xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */ - xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */ - xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */ - xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ - xf_emit(ctx, 1, 0); /* 00000003 */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */ - } else if (device->chipset >= 0xa0) { - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */ - xf_emit(ctx, 1, 0); /* 00000003 */ - } else { - xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ - } - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ - xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */ - xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ - } - xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ - xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ - xf_emit(ctx, 1, 0); /* 7 */ - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ - xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ - xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ - xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */ - xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */ - xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - if (device->chipset == 0x50) - xf_emit(ctx, 1, 0); /* ff */ - else - xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ - xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ - xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ - xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ - xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */ - xf_emit(ctx, 1, 0); /* 7 */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */ - xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */ - xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ - xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */ - xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */ - xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */ - xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */ - xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */ - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ - xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */ - xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ - xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */ - xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */ - xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ - xf_emit(ctx, 1, 0); /* 0000ffff */ - xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ - xf_emit(ctx, 1, 0); /* 00000007 */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 2, 0); /* ffff, ff/3ff */ - xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */ - xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */ - xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */ - xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */ - xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 0); /* 00000001 */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ - xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ - xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ - xf_emit(ctx, 1, 0); /* 7 */ - xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - } - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 0x0fac6881); /* fffffff */ - xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ - xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ - xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */ - } - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ - if (device->chipset >= 0xa0) { - xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */ - xf_emit(ctx, 1, 0xfac6881); /* fffffff */ - xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */ - xf_emit(ctx, 1, 4); /* 7 */ - xf_emit(ctx, 1, 0); /* 1 */ - xf_emit(ctx, 2, 1); /* 1 */ - xf_emit(ctx, 2, 0); /* 7, f */ - xf_emit(ctx, 1, 1); /* 1 */ - xf_emit(ctx, 1, 0); /* 7/f */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 0x9, 0); /* 1 */ - else - xf_emit(ctx, 0x8, 0); /* 1 */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 8, 1); /* 1 */ - xf_emit(ctx, 1, 0x11); /* 7f */ - xf_emit(ctx, 7, 0); /* 7f */ - xf_emit(ctx, 1, 0xfac6881); /* fffffff */ - xf_emit(ctx, 1, 0xf); /* f */ - xf_emit(ctx, 7, 0); /* f */ - xf_emit(ctx, 1, 0x11); /* 7f */ - xf_emit(ctx, 1, 1); /* 1 */ - xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - } - } -} - -static void -nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ - if (device->chipset != 0x50) - xf_emit(ctx, 1, 0); /* 3 */ - xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */ - xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */ - xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */ - xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */ - if (device->chipset == 0x50) - xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */ - else - xf_emit(ctx, 2, 0); /* 3ff, 1 */ - xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */ - xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */ - xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */ - xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */ - xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */ - xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */ - xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */ - xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */ - if (device->chipset == 0x50) { - xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ - xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */ - xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */ - } else if (!IS_NVAAF(device->chipset)) { - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ - xf_emit(ctx, 1, 0); /* 00000003 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - xf_emit(ctx, 1, 0); /* 00000003 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */ - xf_emit(ctx, 1, 0); /* 00000003 */ - xf_emit(ctx, 1, 0); /* 000003ff */ - } else { - xf_emit(ctx, 0x6, 0); - } - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */ - xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */ -} - -static void -nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ - xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ - xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ - xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ - xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ - xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ - xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ - xf_emit(ctx, 1, 0); /* ffff0ff3 */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ - xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ - xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ - xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ - xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */ - xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */ - xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */ - xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */ - xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ - xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ -} - -static void -nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - if (device->chipset < 0xa0) { - nv50_graph_construct_xfer_unk84xx(ctx); - nv50_graph_construct_xfer_tprop(ctx); - nv50_graph_construct_xfer_tex(ctx); - nv50_graph_construct_xfer_unk8cxx(ctx); - } else { - nv50_graph_construct_xfer_tex(ctx); - nv50_graph_construct_xfer_tprop(ctx); - nv50_graph_construct_xfer_unk8cxx(ctx); - nv50_graph_construct_xfer_unk84xx(ctx); - } -} - -static void -nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i, mpcnt = 2; - switch (device->chipset) { - case 0x98: - case 0xaa: - mpcnt = 1; - break; - case 0x50: - case 0x84: - case 0x86: - case 0x92: - case 0x94: - case 0x96: - case 0xa8: - case 0xac: - mpcnt = 2; - break; - case 0xa0: - case 0xa3: - case 0xa5: - case 0xaf: - mpcnt = 3; - break; - } - for (i = 0; i < mpcnt; i++) { - xf_emit(ctx, 1, 0); /* ff */ - xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */ - xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */ - xf_emit(ctx, 1, 0x04000400); /* ffffffff */ - if (device->chipset >= 0xa0) - xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */ - xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ - if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) { - xf_emit(ctx, 1, 0xe00); /* 7fff */ - xf_emit(ctx, 1, 0x1e00); /* 7fff */ - } - xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */ - xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - if (device->chipset == 0x50) - xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */ - xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */ - xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ - xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ - xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ - if (IS_NVAAF(device->chipset)) - xf_emit(ctx, 0xb, 0); /* RO */ - else if (device->chipset >= 0xa0) - xf_emit(ctx, 0xc, 0); /* RO */ - else - xf_emit(ctx, 0xa, 0); /* RO */ - } - xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - if (device->chipset >= 0xa0) { - xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */ - } - xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */ - xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ - xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ - xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ - xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ - xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ - xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ - xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ - xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ - xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */ - xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ - xf_emit(ctx, 1, 0); /* ff/3ff */ - xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */ - xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */ - xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ - xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ - xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ - xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */ - xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ - xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ - xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ - xf_emit(ctx, 1, 0); /* 00000007 */ - xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */ - xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ - if (IS_NVA3F(device->chipset)) - xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ - xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ - xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ - xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */ - xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ - xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ - xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ - xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ - if (IS_NVA3F(device->chipset)) { - xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ - xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ - xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ - xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ - xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ - xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ - } - xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ - xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ - /* XXX: demagic this part some day */ - if (device->chipset == 0x50) - xf_emit(ctx, 0x3a0, 0); - else if (device->chipset < 0x94) - xf_emit(ctx, 0x3a2, 0); - else if (device->chipset == 0x98 || device->chipset == 0xaa) - xf_emit(ctx, 0x39f, 0); - else - xf_emit(ctx, 0x3a3, 0); - xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ - xf_emit(ctx, 1, 0); /* 7 OPERATION */ - xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */ - xf_emit(ctx, 0x2d, 0); -} - -static void -nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) -{ - struct nouveau_device *device = ctx->device; - int i; - u32 offset; - u32 units = nv_rd32 (ctx->device, 0x1540); - int size = 0; - - offset = (ctx->ctxvals_pos+0x3f)&~0x3f; - - if (device->chipset < 0xa0) { - for (i = 0; i < 8; i++) { - ctx->ctxvals_pos = offset + i; - /* that little bugger belongs to csched. No idea - * what it's doing here. */ - if (i == 0) - xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ - if (units & (1 << i)) - nv50_graph_construct_xfer_mpc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - } - } else { - /* Strand 0: TPs 0, 1 */ - ctx->ctxvals_pos = offset; - /* that little bugger belongs to csched. No idea - * what it's doing here. */ - xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ - if (units & (1 << 0)) - nv50_graph_construct_xfer_mpc(ctx); - if (units & (1 << 1)) - nv50_graph_construct_xfer_mpc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 1: TPs 2, 3 */ - ctx->ctxvals_pos = offset + 1; - if (units & (1 << 2)) - nv50_graph_construct_xfer_mpc(ctx); - if (units & (1 << 3)) - nv50_graph_construct_xfer_mpc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 2: TPs 4, 5, 6 */ - ctx->ctxvals_pos = offset + 2; - if (units & (1 << 4)) - nv50_graph_construct_xfer_mpc(ctx); - if (units & (1 << 5)) - nv50_graph_construct_xfer_mpc(ctx); - if (units & (1 << 6)) - nv50_graph_construct_xfer_mpc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - - /* Strand 3: TPs 7, 8, 9 */ - ctx->ctxvals_pos = offset + 3; - if (units & (1 << 7)) - nv50_graph_construct_xfer_mpc(ctx); - if (units & (1 << 8)) - nv50_graph_construct_xfer_mpc(ctx); - if (units & (1 << 9)) - nv50_graph_construct_xfer_mpc(ctx); - if ((ctx->ctxvals_pos-offset)/8 > size) - size = (ctx->ctxvals_pos-offset)/8; - } - ctx->ctxvals_pos = offset + size * 8; - ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; - cp_lsr (ctx, offset); - cp_out (ctx, CP_SET_XFER_POINTER); - cp_lsr (ctx, size); - cp_out (ctx, CP_SEEK_2); - cp_out (ctx, CP_XFER_2); - cp_wait(ctx, XFER, BUSY); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c deleted file mode 100644 index b8e5fe60a1eb..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c +++ /dev/null @@ -1,1386 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvc0_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000b2, 40, 0x01, 0x00000000 }, - { 0x000210, 8, 0x01, 0x00000040 }, - { 0x000218, 8, 0x01, 0x0000c080 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00001fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x003fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x0005e0, 5, 0x01, 0x00000022 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x00000c48 }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00300008 }, - { 0x000841, 1, 0x01, 0x04000080 }, - { 0x000842, 1, 0x01, 0x00300008 }, - { 0x000843, 1, 0x01, 0x04000080 }, - { 0x000818, 8, 0x01, 0x00000000 }, - { 0x000848, 16, 0x01, 0x00000000 }, - { 0x000738, 1, 0x01, 0x00000000 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x000944, 1, 0x01, 0x00000022 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000014 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -const struct nvc0_graph_pack -nvc0_grctx_pack_icmd[] = { - { nvc0_grctx_init_icmd_0 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_9097_0[] = { - { 0x000800, 8, 0x40, 0x00000000 }, - { 0x000804, 8, 0x40, 0x00000000 }, - { 0x000808, 8, 0x40, 0x00000400 }, - { 0x00080c, 8, 0x40, 0x00000300 }, - { 0x000810, 1, 0x04, 0x000000cf }, - { 0x000850, 7, 0x40, 0x00000000 }, - { 0x000814, 8, 0x40, 0x00000040 }, - { 0x000818, 8, 0x40, 0x00000001 }, - { 0x00081c, 8, 0x40, 0x00000000 }, - { 0x000820, 8, 0x40, 0x00000000 }, - { 0x002700, 8, 0x20, 0x00000000 }, - { 0x002704, 8, 0x20, 0x00000000 }, - { 0x002708, 8, 0x20, 0x00000000 }, - { 0x00270c, 8, 0x20, 0x00000000 }, - { 0x002710, 8, 0x20, 0x00014000 }, - { 0x002714, 8, 0x20, 0x00000040 }, - { 0x001c00, 16, 0x10, 0x00000000 }, - { 0x001c04, 16, 0x10, 0x00000000 }, - { 0x001c08, 16, 0x10, 0x00000000 }, - { 0x001c0c, 16, 0x10, 0x00000000 }, - { 0x001d00, 16, 0x10, 0x00000000 }, - { 0x001d04, 16, 0x10, 0x00000000 }, - { 0x001d08, 16, 0x10, 0x00000000 }, - { 0x001d0c, 16, 0x10, 0x00000000 }, - { 0x001f00, 16, 0x08, 0x00000000 }, - { 0x001f04, 16, 0x08, 0x00000000 }, - { 0x001f80, 16, 0x08, 0x00000000 }, - { 0x001f84, 16, 0x08, 0x00000000 }, - { 0x002200, 5, 0x10, 0x00000022 }, - { 0x002000, 1, 0x04, 0x00000000 }, - { 0x002040, 1, 0x04, 0x00000011 }, - { 0x002080, 1, 0x04, 0x00000020 }, - { 0x0020c0, 1, 0x04, 0x00000030 }, - { 0x002100, 1, 0x04, 0x00000040 }, - { 0x002140, 1, 0x04, 0x00000051 }, - { 0x00200c, 6, 0x40, 0x00000001 }, - { 0x002010, 1, 0x04, 0x00000000 }, - { 0x002050, 1, 0x04, 0x00000000 }, - { 0x002090, 1, 0x04, 0x00000001 }, - { 0x0020d0, 1, 0x04, 0x00000002 }, - { 0x002110, 1, 0x04, 0x00000003 }, - { 0x002150, 1, 0x04, 0x00000004 }, - { 0x000380, 4, 0x20, 0x00000000 }, - { 0x000384, 4, 0x20, 0x00000000 }, - { 0x000388, 4, 0x20, 0x00000000 }, - { 0x00038c, 4, 0x20, 0x00000000 }, - { 0x000700, 4, 0x10, 0x00000000 }, - { 0x000704, 4, 0x10, 0x00000000 }, - { 0x000708, 4, 0x10, 0x00000000 }, - { 0x002800, 128, 0x04, 0x00000000 }, - { 0x000a00, 16, 0x20, 0x00000000 }, - { 0x000a04, 16, 0x20, 0x00000000 }, - { 0x000a08, 16, 0x20, 0x00000000 }, - { 0x000a0c, 16, 0x20, 0x00000000 }, - { 0x000a10, 16, 0x20, 0x00000000 }, - { 0x000a14, 16, 0x20, 0x00000000 }, - { 0x000c00, 16, 0x10, 0x00000000 }, - { 0x000c04, 16, 0x10, 0x00000000 }, - { 0x000c08, 16, 0x10, 0x00000000 }, - { 0x000c0c, 16, 0x10, 0x3f800000 }, - { 0x000d00, 8, 0x08, 0xffff0000 }, - { 0x000d04, 8, 0x08, 0xffff0000 }, - { 0x000e00, 16, 0x10, 0x00000000 }, - { 0x000e04, 16, 0x10, 0xffff0000 }, - { 0x000e08, 16, 0x10, 0xffff0000 }, - { 0x000d40, 4, 0x08, 0x00000000 }, - { 0x000d44, 4, 0x08, 0x00000000 }, - { 0x001e00, 8, 0x20, 0x00000001 }, - { 0x001e04, 8, 0x20, 0x00000001 }, - { 0x001e08, 8, 0x20, 0x00000002 }, - { 0x001e0c, 8, 0x20, 0x00000001 }, - { 0x001e10, 8, 0x20, 0x00000001 }, - { 0x001e14, 8, 0x20, 0x00000002 }, - { 0x001e18, 8, 0x20, 0x00000001 }, - { 0x003400, 128, 0x04, 0x00000000 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x001514, 1, 0x04, 0x00000000 }, - { 0x000d68, 1, 0x04, 0x0000ffff }, - { 0x00121c, 1, 0x04, 0x0fac6881 }, - { 0x000fac, 1, 0x04, 0x00000001 }, - { 0x001538, 1, 0x04, 0x00000001 }, - { 0x000fe0, 2, 0x04, 0x00000000 }, - { 0x000fe8, 1, 0x04, 0x00000014 }, - { 0x000fec, 1, 0x04, 0x00000040 }, - { 0x000ff0, 1, 0x04, 0x00000000 }, - { 0x00179c, 1, 0x04, 0x00000000 }, - { 0x001228, 1, 0x04, 0x00000400 }, - { 0x00122c, 1, 0x04, 0x00000300 }, - { 0x001230, 1, 0x04, 0x00010001 }, - { 0x0007f8, 1, 0x04, 0x00000000 }, - { 0x0015b4, 1, 0x04, 0x00000001 }, - { 0x0015cc, 1, 0x04, 0x00000000 }, - { 0x001534, 1, 0x04, 0x00000000 }, - { 0x000fb0, 1, 0x04, 0x00000000 }, - { 0x0015d0, 1, 0x04, 0x00000000 }, - { 0x00153c, 1, 0x04, 0x00000000 }, - { 0x0016b4, 1, 0x04, 0x00000003 }, - { 0x000fbc, 4, 0x04, 0x0000ffff }, - { 0x000df8, 2, 0x04, 0x00000000 }, - { 0x001948, 1, 0x04, 0x00000000 }, - { 0x001970, 1, 0x04, 0x00000001 }, - { 0x00161c, 1, 0x04, 0x000009f0 }, - { 0x000dcc, 1, 0x04, 0x00000010 }, - { 0x00163c, 1, 0x04, 0x00000000 }, - { 0x0015e4, 1, 0x04, 0x00000000 }, - { 0x001160, 32, 0x04, 0x25e00040 }, - { 0x001880, 32, 0x04, 0x00000000 }, - { 0x000f84, 2, 0x04, 0x00000000 }, - { 0x0017c8, 2, 0x04, 0x00000000 }, - { 0x0017d0, 1, 0x04, 0x000000ff }, - { 0x0017d4, 1, 0x04, 0xffffffff }, - { 0x0017d8, 1, 0x04, 0x00000002 }, - { 0x0017dc, 1, 0x04, 0x00000000 }, - { 0x0015f4, 2, 0x04, 0x00000000 }, - { 0x001434, 2, 0x04, 0x00000000 }, - { 0x000d74, 1, 0x04, 0x00000000 }, - { 0x000dec, 1, 0x04, 0x00000001 }, - { 0x0013a4, 1, 0x04, 0x00000000 }, - { 0x001318, 1, 0x04, 0x00000001 }, - { 0x001644, 1, 0x04, 0x00000000 }, - { 0x000748, 1, 0x04, 0x00000000 }, - { 0x000de8, 1, 0x04, 0x00000000 }, - { 0x001648, 1, 0x04, 0x00000000 }, - { 0x0012a4, 1, 0x04, 0x00000000 }, - { 0x001120, 4, 0x04, 0x00000000 }, - { 0x001118, 1, 0x04, 0x00000000 }, - { 0x00164c, 1, 0x04, 0x00000000 }, - { 0x001658, 1, 0x04, 0x00000000 }, - { 0x001910, 1, 0x04, 0x00000290 }, - { 0x001518, 1, 0x04, 0x00000000 }, - { 0x00165c, 1, 0x04, 0x00000001 }, - { 0x001520, 1, 0x04, 0x00000000 }, - { 0x001604, 1, 0x04, 0x00000000 }, - { 0x001570, 1, 0x04, 0x00000000 }, - { 0x0013b0, 2, 0x04, 0x3f800000 }, - { 0x00020c, 1, 0x04, 0x00000000 }, - { 0x001670, 1, 0x04, 0x30201000 }, - { 0x001674, 1, 0x04, 0x70605040 }, - { 0x001678, 1, 0x04, 0xb8a89888 }, - { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, - { 0x00166c, 1, 0x04, 0x00000000 }, - { 0x001680, 1, 0x04, 0x00ffff00 }, - { 0x0012d0, 1, 0x04, 0x00000003 }, - { 0x0012d4, 1, 0x04, 0x00000002 }, - { 0x001684, 2, 0x04, 0x00000000 }, - { 0x000dac, 2, 0x04, 0x00001b02 }, - { 0x000db4, 1, 0x04, 0x00000000 }, - { 0x00168c, 1, 0x04, 0x00000000 }, - { 0x0015bc, 1, 0x04, 0x00000000 }, - { 0x00156c, 1, 0x04, 0x00000000 }, - { 0x00187c, 1, 0x04, 0x00000000 }, - { 0x001110, 1, 0x04, 0x00000001 }, - { 0x000dc0, 3, 0x04, 0x00000000 }, - { 0x001234, 1, 0x04, 0x00000000 }, - { 0x001690, 1, 0x04, 0x00000000 }, - { 0x0012ac, 1, 0x04, 0x00000001 }, - { 0x0002c4, 1, 0x04, 0x00000000 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x001000, 1, 0x04, 0x00000010 }, - { 0x0010fc, 1, 0x04, 0x00000000 }, - { 0x001290, 1, 0x04, 0x00000000 }, - { 0x000218, 1, 0x04, 0x00000010 }, - { 0x0012d8, 1, 0x04, 0x00000000 }, - { 0x0012dc, 1, 0x04, 0x00000010 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x00155c, 2, 0x04, 0x00000000 }, - { 0x001564, 1, 0x04, 0x00001fff }, - { 0x001574, 2, 0x04, 0x00000000 }, - { 0x00157c, 1, 0x04, 0x003fffff }, - { 0x001354, 1, 0x04, 0x00000000 }, - { 0x001664, 1, 0x04, 0x00000000 }, - { 0x001610, 1, 0x04, 0x00000012 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x00162c, 1, 0x04, 0x00000003 }, - { 0x000210, 1, 0x04, 0x00000000 }, - { 0x000320, 1, 0x04, 0x00000000 }, - { 0x000324, 6, 0x04, 0x3f800000 }, - { 0x000750, 1, 0x04, 0x00000000 }, - { 0x000760, 1, 0x04, 0x39291909 }, - { 0x000764, 1, 0x04, 0x79695949 }, - { 0x000768, 1, 0x04, 0xb9a99989 }, - { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, - { 0x000770, 1, 0x04, 0x30201000 }, - { 0x000774, 1, 0x04, 0x70605040 }, - { 0x000778, 1, 0x04, 0x00009080 }, - { 0x000780, 1, 0x04, 0x39291909 }, - { 0x000784, 1, 0x04, 0x79695949 }, - { 0x000788, 1, 0x04, 0xb9a99989 }, - { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, - { 0x0007d0, 1, 0x04, 0x30201000 }, - { 0x0007d4, 1, 0x04, 0x70605040 }, - { 0x0007d8, 1, 0x04, 0x00009080 }, - { 0x00037c, 1, 0x04, 0x00000001 }, - { 0x000740, 2, 0x04, 0x00000000 }, - { 0x002600, 1, 0x04, 0x00000000 }, - { 0x001918, 1, 0x04, 0x00000000 }, - { 0x00191c, 1, 0x04, 0x00000900 }, - { 0x001920, 1, 0x04, 0x00000405 }, - { 0x001308, 1, 0x04, 0x00000001 }, - { 0x001924, 1, 0x04, 0x00000000 }, - { 0x0013ac, 1, 0x04, 0x00000000 }, - { 0x00192c, 1, 0x04, 0x00000001 }, - { 0x00193c, 1, 0x04, 0x00002c1c }, - { 0x000d7c, 1, 0x04, 0x00000000 }, - { 0x000f8c, 1, 0x04, 0x00000000 }, - { 0x0002c0, 1, 0x04, 0x00000001 }, - { 0x001510, 1, 0x04, 0x00000000 }, - { 0x001940, 1, 0x04, 0x00000000 }, - { 0x000ff4, 2, 0x04, 0x00000000 }, - { 0x00194c, 2, 0x04, 0x00000000 }, - { 0x001968, 1, 0x04, 0x00000000 }, - { 0x001590, 1, 0x04, 0x0000003f }, - { 0x0007e8, 4, 0x04, 0x00000000 }, - { 0x00196c, 1, 0x04, 0x00000011 }, - { 0x00197c, 1, 0x04, 0x00000000 }, - { 0x000fcc, 2, 0x04, 0x00000000 }, - { 0x0002d8, 1, 0x04, 0x00000040 }, - { 0x001980, 1, 0x04, 0x00000080 }, - { 0x001504, 1, 0x04, 0x00000080 }, - { 0x001984, 1, 0x04, 0x00000000 }, - { 0x000300, 1, 0x04, 0x00000001 }, - { 0x0013a8, 1, 0x04, 0x00000000 }, - { 0x0012ec, 1, 0x04, 0x00000000 }, - { 0x001310, 1, 0x04, 0x00000000 }, - { 0x001314, 1, 0x04, 0x00000001 }, - { 0x001380, 1, 0x04, 0x00000000 }, - { 0x001384, 4, 0x04, 0x00000001 }, - { 0x001394, 1, 0x04, 0x00000000 }, - { 0x00139c, 1, 0x04, 0x00000000 }, - { 0x001398, 1, 0x04, 0x00000000 }, - { 0x001594, 1, 0x04, 0x00000000 }, - { 0x001598, 4, 0x04, 0x00000001 }, - { 0x000f54, 3, 0x04, 0x00000000 }, - { 0x0019bc, 1, 0x04, 0x00000000 }, - { 0x000f9c, 2, 0x04, 0x00000000 }, - { 0x0012cc, 1, 0x04, 0x00000000 }, - { 0x0012e8, 1, 0x04, 0x00000000 }, - { 0x00130c, 1, 0x04, 0x00000001 }, - { 0x001360, 8, 0x04, 0x00000000 }, - { 0x00133c, 2, 0x04, 0x00000001 }, - { 0x001344, 1, 0x04, 0x00000002 }, - { 0x001348, 2, 0x04, 0x00000001 }, - { 0x001350, 1, 0x04, 0x00000002 }, - { 0x001358, 1, 0x04, 0x00000001 }, - { 0x0012e4, 1, 0x04, 0x00000000 }, - { 0x00131c, 4, 0x04, 0x00000000 }, - { 0x0019c0, 1, 0x04, 0x00000000 }, - { 0x001140, 1, 0x04, 0x00000000 }, - { 0x0019c4, 1, 0x04, 0x00000000 }, - { 0x0019c8, 1, 0x04, 0x00001500 }, - { 0x00135c, 1, 0x04, 0x00000000 }, - { 0x000f90, 1, 0x04, 0x00000000 }, - { 0x0019e0, 8, 0x04, 0x00000001 }, - { 0x0019cc, 1, 0x04, 0x00000001 }, - { 0x0015b8, 1, 0x04, 0x00000000 }, - { 0x001a00, 1, 0x04, 0x00001111 }, - { 0x001a04, 7, 0x04, 0x00000000 }, - { 0x000d6c, 2, 0x04, 0xffff0000 }, - { 0x0010f8, 1, 0x04, 0x00001010 }, - { 0x000d80, 5, 0x04, 0x00000000 }, - { 0x000da0, 1, 0x04, 0x00000000 }, - { 0x001508, 1, 0x04, 0x80000000 }, - { 0x00150c, 1, 0x04, 0x40000000 }, - { 0x001668, 1, 0x04, 0x00000000 }, - { 0x000318, 2, 0x04, 0x00000008 }, - { 0x000d9c, 1, 0x04, 0x00000001 }, - { 0x0007dc, 1, 0x04, 0x00000000 }, - { 0x00074c, 1, 0x04, 0x00000055 }, - { 0x001420, 1, 0x04, 0x00000003 }, - { 0x0017bc, 2, 0x04, 0x00000000 }, - { 0x0017c4, 1, 0x04, 0x00000001 }, - { 0x001008, 1, 0x04, 0x00000008 }, - { 0x00100c, 1, 0x04, 0x00000040 }, - { 0x001010, 1, 0x04, 0x0000012c }, - { 0x000d60, 1, 0x04, 0x00000040 }, - { 0x00075c, 1, 0x04, 0x00000003 }, - { 0x001018, 1, 0x04, 0x00000020 }, - { 0x00101c, 1, 0x04, 0x00000001 }, - { 0x001020, 1, 0x04, 0x00000020 }, - { 0x001024, 1, 0x04, 0x00000001 }, - { 0x001444, 3, 0x04, 0x00000000 }, - { 0x000360, 1, 0x04, 0x20164010 }, - { 0x000364, 1, 0x04, 0x00000020 }, - { 0x000368, 1, 0x04, 0x00000000 }, - { 0x000de4, 1, 0x04, 0x00000000 }, - { 0x000204, 1, 0x04, 0x00000006 }, - { 0x000208, 1, 0x04, 0x00000000 }, - { 0x0002cc, 1, 0x04, 0x003fffff }, - { 0x0002d0, 1, 0x04, 0x00000c48 }, - { 0x001220, 1, 0x04, 0x00000005 }, - { 0x000fdc, 1, 0x04, 0x00000000 }, - { 0x000f98, 1, 0x04, 0x00300008 }, - { 0x001284, 1, 0x04, 0x04000080 }, - { 0x001450, 1, 0x04, 0x00300008 }, - { 0x001454, 1, 0x04, 0x04000080 }, - { 0x000214, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_902d_0[] = { - { 0x000200, 1, 0x04, 0x000000cf }, - { 0x000204, 1, 0x04, 0x00000001 }, - { 0x000208, 1, 0x04, 0x00000020 }, - { 0x00020c, 1, 0x04, 0x00000001 }, - { 0x000210, 1, 0x04, 0x00000000 }, - { 0x000214, 1, 0x04, 0x00000080 }, - { 0x000218, 2, 0x04, 0x00000100 }, - { 0x000220, 2, 0x04, 0x00000000 }, - { 0x000230, 1, 0x04, 0x000000cf }, - { 0x000234, 1, 0x04, 0x00000001 }, - { 0x000238, 1, 0x04, 0x00000020 }, - { 0x00023c, 1, 0x04, 0x00000001 }, - { 0x000244, 1, 0x04, 0x00000080 }, - { 0x000248, 2, 0x04, 0x00000100 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_9039_0[] = { - { 0x00030c, 3, 0x04, 0x00000000 }, - { 0x000320, 1, 0x04, 0x00000000 }, - { 0x000238, 2, 0x04, 0x00000000 }, - { 0x000318, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_90c0_0[] = { - { 0x00270c, 8, 0x20, 0x00000000 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x000758, 1, 0x04, 0x00000100 }, - { 0x0002c4, 1, 0x04, 0x00000000 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x000204, 3, 0x04, 0x00000000 }, - { 0x000214, 1, 0x04, 0x00000000 }, - { 0x00024c, 1, 0x04, 0x00000000 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x001664, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvc0_grctx_pack_mthd[] = { - { nvc0_grctx_init_9097_0, 0x9097 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvc0_grctx_init_90c0_0, 0x90c0 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_main_0[] = { - { 0x400204, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_fe_0[] = { - { 0x404004, 11, 0x04, 0x00000000 }, - { 0x404044, 1, 0x04, 0x00000000 }, - { 0x404094, 13, 0x04, 0x00000000 }, - { 0x4040c8, 1, 0x04, 0xf0000087 }, - { 0x4040d0, 6, 0x04, 0x00000000 }, - { 0x4040e8, 1, 0x04, 0x00001000 }, - { 0x4040f8, 1, 0x04, 0x00000000 }, - { 0x404130, 2, 0x04, 0x00000000 }, - { 0x404138, 1, 0x04, 0x20000040 }, - { 0x404150, 1, 0x04, 0x0000002e }, - { 0x404154, 1, 0x04, 0x00000400 }, - { 0x404158, 1, 0x04, 0x00000200 }, - { 0x404164, 1, 0x04, 0x00000055 }, - { 0x404168, 1, 0x04, 0x00000000 }, - { 0x404174, 3, 0x04, 0x00000000 }, - { 0x404200, 8, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_pri_0[] = { - { 0x404404, 14, 0x04, 0x00000000 }, - { 0x404460, 2, 0x04, 0x00000000 }, - { 0x404468, 1, 0x04, 0x00ffffff }, - { 0x40446c, 1, 0x04, 0x00000000 }, - { 0x404480, 1, 0x04, 0x00000001 }, - { 0x404498, 1, 0x04, 0x00000001 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_memfmt_0[] = { - { 0x404604, 1, 0x04, 0x00000015 }, - { 0x404608, 1, 0x04, 0x00000000 }, - { 0x40460c, 1, 0x04, 0x00002e00 }, - { 0x404610, 1, 0x04, 0x00000100 }, - { 0x404618, 8, 0x04, 0x00000000 }, - { 0x404638, 1, 0x04, 0x00000004 }, - { 0x40463c, 8, 0x04, 0x00000000 }, - { 0x40465c, 1, 0x04, 0x007f0100 }, - { 0x404660, 7, 0x04, 0x00000000 }, - { 0x40467c, 1, 0x04, 0x00000002 }, - { 0x404680, 8, 0x04, 0x00000000 }, - { 0x4046a0, 1, 0x04, 0x007f0080 }, - { 0x4046a4, 18, 0x04, 0x00000000 }, - { 0x4046f0, 2, 0x04, 0x00000000 }, - { 0x404700, 13, 0x04, 0x00000000 }, - { 0x404734, 1, 0x04, 0x00000100 }, - { 0x404738, 8, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x078000bf }, - { 0x405830, 1, 0x04, 0x02180000 }, - { 0x405834, 2, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x000103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b4, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_rstr2d_0[] = { - { 0x407804, 1, 0x04, 0x00000023 }, - { 0x40780c, 1, 0x04, 0x0a418820 }, - { 0x407810, 1, 0x04, 0x062080e6 }, - { 0x407814, 1, 0x04, 0x020398a4 }, - { 0x407818, 1, 0x04, 0x0e629062 }, - { 0x40781c, 1, 0x04, 0x0a418820 }, - { 0x407820, 1, 0x04, 0x000000e6 }, - { 0x4078bc, 1, 0x04, 0x00000103 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_scc_0[] = { - { 0x408000, 2, 0x04, 0x00000000 }, - { 0x408008, 1, 0x04, 0x00000018 }, - { 0x40800c, 2, 0x04, 0x00000000 }, - { 0x408014, 1, 0x04, 0x00000069 }, - { 0x408018, 1, 0x04, 0xe100e100 }, - { 0x408064, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x02802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x0003e00d }, - { 0x408900, 1, 0x04, 0x3080b801 }, - { 0x408904, 1, 0x04, 0x02000001 }, - { 0x408908, 1, 0x04, 0x00c80929 }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -const struct nvc0_graph_pack -nvc0_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvc0_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvc0_grctx_init_ds_0 }, - { nvc0_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvc0_grctx_init_be_0 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_gpc_unk_0[] = { - { 0x418380, 1, 0x04, 0x00000016 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_prop_0[] = { - { 0x418400, 1, 0x04, 0x38004e00 }, - { 0x418404, 1, 0x04, 0x71e0ffff }, - { 0x418408, 1, 0x04, 0x00000000 }, - { 0x41840c, 1, 0x04, 0x00001008 }, - { 0x418410, 1, 0x04, 0x0fff0fff }, - { 0x418414, 1, 0x04, 0x00200fff }, - { 0x418450, 6, 0x04, 0x00000000 }, - { 0x418468, 1, 0x04, 0x00000001 }, - { 0x41846c, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_gpc_unk_1[] = { - { 0x418600, 1, 0x04, 0x0000001f }, - { 0x418684, 1, 0x04, 0x0000000f }, - { 0x418700, 1, 0x04, 0x00000002 }, - { 0x418704, 1, 0x04, 0x00000080 }, - { 0x418708, 1, 0x04, 0x00000000 }, - { 0x41870c, 1, 0x04, 0x07c80000 }, - { 0x418710, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x0006860a }, - { 0x418808, 3, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00008442 }, - { 0x418830, 1, 0x04, 0x00000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x00100000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_zcull_0[] = { - { 0x41891c, 1, 0x04, 0x00ff00ff }, - { 0x418924, 1, 0x04, 0x00000000 }, - { 0x418928, 1, 0x04, 0x00ffff00 }, - { 0x41892c, 1, 0x04, 0x0000ff00 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_crstr_0[] = { - { 0x418b00, 1, 0x04, 0x00000000 }, - { 0x418b08, 1, 0x04, 0x0a418820 }, - { 0x418b0c, 1, 0x04, 0x062080e6 }, - { 0x418b10, 1, 0x04, 0x020398a4 }, - { 0x418b14, 1, 0x04, 0x0e629062 }, - { 0x418b18, 1, 0x04, 0x0a418820 }, - { 0x418b1c, 1, 0x04, 0x000000e6 }, - { 0x418bb8, 1, 0x04, 0x00000103 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_gpm_0[] = { - { 0x418c08, 1, 0x04, 0x00000001 }, - { 0x418c10, 8, 0x04, 0x00000000 }, - { 0x418c80, 1, 0x04, 0x20200004 }, - { 0x418c8c, 1, 0x04, 0x00000001 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_gcc_0[] = { - { 0x419000, 1, 0x04, 0x00000780 }, - { 0x419004, 2, 0x04, 0x00000000 }, - { 0x419014, 1, 0x04, 0x00000004 }, - {} -}; - -const struct nvc0_graph_pack -nvc0_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvc0_grctx_init_prop_0 }, - { nvc0_grctx_init_gpc_unk_1 }, - { nvc0_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvc0_grctx_init_crstr_0 }, - { nvc0_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_zcullr_0[] = { - { 0x418a00, 3, 0x04, 0x00000000 }, - { 0x418a0c, 1, 0x04, 0x00010000 }, - { 0x418a10, 3, 0x04, 0x00000000 }, - { 0x418a20, 3, 0x04, 0x00000000 }, - { 0x418a2c, 1, 0x04, 0x00010000 }, - { 0x418a30, 3, 0x04, 0x00000000 }, - { 0x418a40, 3, 0x04, 0x00000000 }, - { 0x418a4c, 1, 0x04, 0x00010000 }, - { 0x418a50, 3, 0x04, 0x00000000 }, - { 0x418a60, 3, 0x04, 0x00000000 }, - { 0x418a6c, 1, 0x04, 0x00010000 }, - { 0x418a70, 3, 0x04, 0x00000000 }, - { 0x418a80, 3, 0x04, 0x00000000 }, - { 0x418a8c, 1, 0x04, 0x00010000 }, - { 0x418a90, 3, 0x04, 0x00000000 }, - { 0x418aa0, 3, 0x04, 0x00000000 }, - { 0x418aac, 1, 0x04, 0x00010000 }, - { 0x418ab0, 3, 0x04, 0x00000000 }, - { 0x418ac0, 3, 0x04, 0x00000000 }, - { 0x418acc, 1, 0x04, 0x00010000 }, - { 0x418ad0, 3, 0x04, 0x00000000 }, - { 0x418ae0, 3, 0x04, 0x00000000 }, - { 0x418aec, 1, 0x04, 0x00010000 }, - { 0x418af0, 3, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvc0_grctx_pack_zcull[] = { - { nvc0_grctx_init_zcullr_0 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_pe_0[] = { - { 0x419818, 1, 0x04, 0x00000000 }, - { 0x41983c, 1, 0x04, 0x00038bc7 }, - { 0x419848, 1, 0x04, 0x00000000 }, - { 0x419864, 1, 0x04, 0x0000012a }, - { 0x419888, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000001f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000023 }, - { 0x419a0c, 1, 0x04, 0x00020000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_wwdx_0[] = { - { 0x419b00, 1, 0x04, 0x0a418820 }, - { 0x419b04, 1, 0x04, 0x062080e6 }, - { 0x419b08, 1, 0x04, 0x020398a4 }, - { 0x419b0c, 1, 0x04, 0x0e629062 }, - { 0x419b10, 1, 0x04, 0x0a418820 }, - { 0x419b14, 1, 0x04, 0x000000e6 }, - { 0x419bd0, 1, 0x04, 0x00900103 }, - { 0x419be0, 1, 0x04, 0x00000001 }, - { 0x419be4, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_mpc_0[] = { - { 0x419c00, 1, 0x04, 0x00000002 }, - { 0x419c04, 1, 0x04, 0x00000006 }, - { 0x419c08, 1, 0x04, 0x00000002 }, - { 0x419c20, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_l1c_0[] = { - { 0x419cb0, 1, 0x04, 0x00060048 }, - { 0x419ce8, 1, 0x04, 0x00000000 }, - { 0x419cf4, 1, 0x04, 0x00000183 }, - {} -}; - -const struct nvc0_graph_init -nvc0_grctx_init_tpccs_0[] = { - { 0x419d20, 1, 0x04, 0x02180000 }, - { 0x419d24, 1, 0x04, 0x00001fff }, - {} -}; - -static const struct nvc0_graph_init -nvc0_grctx_init_sm_0[] = { - { 0x419e04, 3, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00000002 }, - { 0x419e44, 1, 0x04, 0x001beff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000000f }, - { 0x419e50, 17, 0x04, 0x00000000 }, - { 0x419e98, 1, 0x04, 0x00000000 }, - { 0x419f50, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvc0_grctx_pack_tpc[] = { - { nvc0_grctx_init_pe_0 }, - { nvc0_grctx_init_tex_0 }, - { nvc0_grctx_init_wwdx_0 }, - { nvc0_grctx_init_mpc_0 }, - { nvc0_grctx_init_l1c_0 }, - { nvc0_grctx_init_tpccs_0 }, - { nvc0_grctx_init_sm_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -int -nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) -{ - if (info->data) { - info->buffer[info->buffer_nr] = round_up(info->addr, align); - info->addr = info->buffer[info->buffer_nr] + size; - info->data->size = size; - info->data->align = align; - info->data->access = access; - info->data++; - return info->buffer_nr++; - } - return -1; -} - -void -nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, - int shift, int buffer) -{ - if (info->data) { - if (shift >= 0) { - info->mmio->addr = addr; - info->mmio->data = data; - info->mmio->shift = shift; - info->mmio->buffer = buffer; - if (buffer >= 0) - data |= info->buffer[buffer] >> shift; - info->mmio++; - } else - return; - } else { - if (buffer >= 0) - return; - } - - nv_wr32(info->priv, addr, data); -} - -void -nvc0_grctx_generate_bundle(struct nvc0_grctx *info) -{ - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); - const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; - const int s = 8; - const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); - mmio_refn(info, 0x408004, 0x00000000, s, b); - mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); - mmio_refn(info, 0x418808, 0x00000000, s, b); - mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); -} - -void -nvc0_grctx_generate_pagepool(struct nvc0_grctx *info) -{ - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); - const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; - const int s = 8; - const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); - mmio_refn(info, 0x40800c, 0x00000000, s, b); - mmio_wr32(info, 0x408010, 0x80000000); - mmio_refn(info, 0x419004, 0x00000000, s, b); - mmio_wr32(info, 0x419008, 0x00000000); -} - -void -nvc0_grctx_generate_attrib(struct nvc0_grctx *info) -{ - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); - const u32 attrib = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); - const u32 access = NV_MEM_ACCESS_RW; - const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); - int gpc, tpc; - u32 bo = 0; - - mmio_refn(info, 0x418810, 0x80000000, s, b); - mmio_refn(info, 0x419848, 0x10000000, s, b); - mmio_wr32(info, 0x405830, (attrib << 16)); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - const u32 o = TPC_UNIT(gpc, tpc, 0x0520); - mmio_skip(info, o, (attrib << 16) | ++bo); - mmio_wr32(info, o, (attrib << 16) | --bo); - bo += impl->attrib_nr_max; - } - } -} - -void -nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv) -{ -} - -void -nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv) -{ - int gpc, tpc, id; - - for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); - id++; - } - - nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); - } - } -} - -void -nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv) -{ - u32 tmp[GPC_MAX / 8] = {}, i = 0; - for (i = 0; i < priv->gpc_nr; i++) - tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4); - for (i = 0; i < 4; i++) { - nv_wr32(priv, 0x406028 + (i * 4), tmp[i]); - nv_wr32(priv, 0x405870 + (i * 4), tmp[i]); - } -} - -void -nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv) -{ - u8 tpcnr[GPC_MAX], data[TPC_MAX]; - int gpc, tpc, i; - - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - memset(data, 0x1f, sizeof(data)); - - gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpcnr[gpc]--; - data[tpc] = gpc; - } - - for (i = 0; i < 4; i++) - nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); -} - -void -nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) -{ - u32 data[6] = {}, data2[2] = {}; - u8 tpcnr[GPC_MAX]; - u8 shift, ntpcv; - int gpc, tpc, i; - - /* calculate first set of magics */ - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - - gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpcnr[gpc]--; - - data[tpc / 6] |= gpc << ((tpc % 6) * 5); - } - - for (; tpc < 32; tpc++) - data[tpc / 6] |= 7 << ((tpc % 6) * 5); - - /* and the second... */ - shift = 0; - ntpcv = priv->tpc_total; - while (!(ntpcv & (1 << 4))) { - ntpcv <<= 1; - shift++; - } - - data2[0] = (ntpcv << 16); - data2[0] |= (shift << 21); - data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); - for (i = 1; i < 7; i++) - data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); - - /* GPC_BROADCAST */ - nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x418b08 + (i * 4), data[i]); - - /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) | - priv->magic_not_rop_nr | data2[0]); - nv_wr32(priv, 0x419be4, data2[1]); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x419b00 + (i * 4), data[i]); - - /* UNK78xx */ - nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x40780c + (i * 4), data[i]); -} - -void -nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) -{ - u64 tpc_mask = 0, tpc_set = 0; - u8 tpcnr[GPC_MAX]; - int gpc, tpc; - int i, a, b; - - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) - tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8); - - for (i = 0, gpc = -1, b = -1; i < 32; i++) { - a = (i * (priv->tpc_total - 1)) / 32; - if (a != b) { - b = a; - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - tpc_set |= 1ULL << ((gpc * 8) + tpc); - } - - nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); - nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); - if (priv->gpc_nr > 4) { - nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); - nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); - } - } -} - -void -nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) -{ - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); - - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); - - nv_wr32(priv, 0x404154, 0x00000000); - - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(priv); - - nvc0_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nvc0_grctx_generate_r4060a8(priv); - nvc0_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); - - nvc0_graph_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); -} - -int -nvc0_grctx_generate(struct nvc0_graph_priv *priv) -{ - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *chan; - struct nvc0_grctx info; - int ret, i; - - /* allocate memory to for a "channel", which we'll use to generate - * the default context values - */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); - if (ret) { - nv_error(priv, "failed to allocate channel memory, %d\n", ret); - return ret; - } - - /* PGD pointer */ - nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); - nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); - nv_wo32(chan, 0x0208, 0xffffffff); - nv_wo32(chan, 0x020c, 0x000000ff); - - /* PGT[0] pointer */ - nv_wo32(chan, 0x1000, 0x00000000); - nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); - - /* identity-map the whole "channel" into its own vm */ - for (i = 0; i < chan->size / 4096; i++) { - u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; - nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); - nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); - } - - /* context pointer (virt) */ - nv_wo32(chan, 0x0210, 0x00080004); - nv_wo32(chan, 0x0214, 0x00000000); - - bar->flush(bar); - - nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); - nv_wr32(priv, 0x100cbc, 0x80000001); - nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); - - /* setup default state for mmio list construction */ - info.priv = priv; - info.data = priv->mmio_data; - info.mmio = priv->mmio_list; - info.addr = 0x2000 + (i * 8); - info.buffer_nr = 0; - - /* make channel current */ - if (priv->firmware) { - nv_wr32(priv, 0x409840, 0x00000030); - nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(priv, 0x409504, 0x00000003); - if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) - nv_error(priv, "load_ctx timeout\n"); - - nv_wo32(chan, 0x8001c, 1); - nv_wo32(chan, 0x80020, 0); - nv_wo32(chan, 0x80028, 0); - nv_wo32(chan, 0x8002c, 0); - bar->flush(bar); - } else { - nv_wr32(priv, 0x409840, 0x80000000); - nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(priv, 0x409504, 0x00000001); - if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) - nv_error(priv, "HUB_SET_CHAN timeout\n"); - } - - oclass->main(priv, &info); - - /* trigger a context unload by unsetting the "next channel valid" bit - * and faking a context switch interrupt - */ - nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); - nv_wr32(priv, 0x409000, 0x00000100); - if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) { - nv_error(priv, "grctx template channel unload timeout\n"); - ret = -EBUSY; - goto done; - } - - priv->data = kmalloc(priv->size, GFP_KERNEL); - if (priv->data) { - for (i = 0; i < priv->size; i += 4) - priv->data[i / 4] = nv_ro32(chan, 0x80000 + i); - ret = 0; - } else { - ret = -ENOMEM; - } - -done: - nouveau_gpuobj_ref(NULL, &chan); - return ret; -} - -struct nouveau_oclass * -nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nvc0_grctx_generate_main, - .unkn = nvc0_grctx_generate_unkn, - .hub = nvc0_grctx_pack_hub, - .gpc = nvc0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc0_grctx_pack_tpc, - .icmd = nvc0_grctx_pack_icmd, - .mthd = nvc0_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, - .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvc0_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h deleted file mode 100644 index c776cd715e33..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h +++ /dev/null @@ -1,202 +0,0 @@ -#ifndef __NVKM_GRCTX_NVC0_H__ -#define __NVKM_GRCTX_NVC0_H__ - -#include "nvc0.h" - -struct nvc0_grctx { - struct nvc0_graph_priv *priv; - struct nvc0_graph_data *data; - struct nvc0_graph_mmio *mmio; - int buffer_nr; - u64 buffer[4]; - u64 addr; -}; - -int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access); -void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int); - -#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d)) -#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e)) -#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) -#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1) - -struct nvc0_grctx_oclass { - struct nouveau_oclass base; - /* main context generation function */ - void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *); - /* context-specific modify-on-first-load list generation function */ - void (*unkn)(struct nvc0_graph_priv *); - /* mmio context data */ - const struct nvc0_graph_pack *hub; - const struct nvc0_graph_pack *gpc; - const struct nvc0_graph_pack *zcull; - const struct nvc0_graph_pack *tpc; - const struct nvc0_graph_pack *ppc; - /* indirect context data, generated with icmds/mthds */ - const struct nvc0_graph_pack *icmd; - const struct nvc0_graph_pack *mthd; - /* bundle circular buffer */ - void (*bundle)(struct nvc0_grctx *); - u32 bundle_size; - u32 bundle_min_gpm_fifo_depth; - u32 bundle_token_limit; - /* pagepool */ - void (*pagepool)(struct nvc0_grctx *); - u32 pagepool_size; - /* attribute(/alpha) circular buffer */ - void (*attrib)(struct nvc0_grctx *); - u32 attrib_nr_max; - u32 attrib_nr; - u32 alpha_nr_max; - u32 alpha_nr; -}; - -static inline const struct nvc0_grctx_oclass * -nvc0_grctx_impl(struct nvc0_graph_priv *priv) -{ - return (void *)nv_engine(priv)->cclass; -} - -extern struct nouveau_oclass *nvc0_grctx_oclass; -int nvc0_grctx_generate(struct nvc0_graph_priv *); -void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); -void nvc0_grctx_generate_bundle(struct nvc0_grctx *); -void nvc0_grctx_generate_pagepool(struct nvc0_grctx *); -void nvc0_grctx_generate_attrib(struct nvc0_grctx *); -void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *); -void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *); - -extern struct nouveau_oclass *nvc1_grctx_oclass; -void nvc1_grctx_generate_attrib(struct nvc0_grctx *); -void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *); - -extern struct nouveau_oclass *nvc4_grctx_oclass; -extern struct nouveau_oclass *nvc8_grctx_oclass; - -extern struct nouveau_oclass *nvd7_grctx_oclass; -void nvd7_grctx_generate_attrib(struct nvc0_grctx *); - -extern struct nouveau_oclass *nvd9_grctx_oclass; - -extern struct nouveau_oclass *nve4_grctx_oclass; -extern struct nouveau_oclass *gk20a_grctx_oclass; -void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); -void nve4_grctx_generate_bundle(struct nvc0_grctx *); -void nve4_grctx_generate_pagepool(struct nvc0_grctx *); -void nve4_grctx_generate_unkn(struct nvc0_graph_priv *); -void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *); - -extern struct nouveau_oclass *nvf0_grctx_oclass; -extern struct nouveau_oclass *gk110b_grctx_oclass; -extern struct nouveau_oclass *nv108_grctx_oclass; -extern struct nouveau_oclass *gm107_grctx_oclass; - -/* context init value lists */ - -extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[]; -extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[]; -extern const struct nvc0_graph_init nvc0_grctx_init_main_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[]; -extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[]; - -extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[]; -extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[]; -extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[]; - -extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[]; - -extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[]; - -extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[]; -extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[]; -extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[]; - -extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[]; -extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[]; - -extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[]; - -extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[]; - -extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[]; -extern const struct nvc0_graph_init nvd9_grctx_init_be_0[]; - -extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[]; -extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[]; - -extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[]; - -extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[]; - -extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[]; - -extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[]; -extern const struct nvc0_graph_init nve4_grctx_init_ds_0[]; -extern const struct nvc0_graph_init nve4_grctx_init_scc_0[]; - -extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[]; - -extern const struct nvc0_graph_init nve4_grctx_init_pes_0[]; - -extern const struct nvc0_graph_pack nve4_grctx_pack_hub[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[]; -extern const struct nvc0_graph_init nve4_grctx_init_a097_0[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_icmd[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_hub[]; -extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[]; -extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_gpc[]; -extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[]; - -extern const struct nvc0_graph_init nvf0_grctx_init_tex_0[]; -extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[]; -extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_ppc[]; - -extern const struct nvc0_graph_init nv108_grctx_init_rstr2d_0[]; - -extern const struct nvc0_graph_init nv108_grctx_init_prop_0[]; -extern const struct nvc0_graph_init nv108_grctx_init_crstr_0[]; - - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c deleted file mode 100644 index c6ba8fed18f1..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvc1_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000b2, 40, 0x01, 0x00000000 }, - { 0x000210, 8, 0x01, 0x00000040 }, - { 0x000218, 8, 0x01, 0x0000c080 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00001fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x003fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x0005e0, 5, 0x01, 0x00000022 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x00000c48 }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00300008 }, - { 0x000841, 1, 0x01, 0x04000080 }, - { 0x000842, 1, 0x01, 0x00300008 }, - { 0x000843, 1, 0x01, 0x04000080 }, - { 0x000818, 8, 0x01, 0x00000000 }, - { 0x000848, 16, 0x01, 0x00000000 }, - { 0x000738, 1, 0x01, 0x00000000 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x000944, 1, 0x01, 0x00000022 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000014 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_pack -nvc1_grctx_pack_icmd[] = { - { nvc1_grctx_init_icmd_0 }, - {} -}; - -const struct nvc0_graph_init -nvc1_grctx_init_9097_0[] = { - { 0x000800, 8, 0x40, 0x00000000 }, - { 0x000804, 8, 0x40, 0x00000000 }, - { 0x000808, 8, 0x40, 0x00000400 }, - { 0x00080c, 8, 0x40, 0x00000300 }, - { 0x000810, 1, 0x04, 0x000000cf }, - { 0x000850, 7, 0x40, 0x00000000 }, - { 0x000814, 8, 0x40, 0x00000040 }, - { 0x000818, 8, 0x40, 0x00000001 }, - { 0x00081c, 8, 0x40, 0x00000000 }, - { 0x000820, 8, 0x40, 0x00000000 }, - { 0x002700, 8, 0x20, 0x00000000 }, - { 0x002704, 8, 0x20, 0x00000000 }, - { 0x002708, 8, 0x20, 0x00000000 }, - { 0x00270c, 8, 0x20, 0x00000000 }, - { 0x002710, 8, 0x20, 0x00014000 }, - { 0x002714, 8, 0x20, 0x00000040 }, - { 0x001c00, 16, 0x10, 0x00000000 }, - { 0x001c04, 16, 0x10, 0x00000000 }, - { 0x001c08, 16, 0x10, 0x00000000 }, - { 0x001c0c, 16, 0x10, 0x00000000 }, - { 0x001d00, 16, 0x10, 0x00000000 }, - { 0x001d04, 16, 0x10, 0x00000000 }, - { 0x001d08, 16, 0x10, 0x00000000 }, - { 0x001d0c, 16, 0x10, 0x00000000 }, - { 0x001f00, 16, 0x08, 0x00000000 }, - { 0x001f04, 16, 0x08, 0x00000000 }, - { 0x001f80, 16, 0x08, 0x00000000 }, - { 0x001f84, 16, 0x08, 0x00000000 }, - { 0x002200, 5, 0x10, 0x00000022 }, - { 0x002000, 1, 0x04, 0x00000000 }, - { 0x002040, 1, 0x04, 0x00000011 }, - { 0x002080, 1, 0x04, 0x00000020 }, - { 0x0020c0, 1, 0x04, 0x00000030 }, - { 0x002100, 1, 0x04, 0x00000040 }, - { 0x002140, 1, 0x04, 0x00000051 }, - { 0x00200c, 6, 0x40, 0x00000001 }, - { 0x002010, 1, 0x04, 0x00000000 }, - { 0x002050, 1, 0x04, 0x00000000 }, - { 0x002090, 1, 0x04, 0x00000001 }, - { 0x0020d0, 1, 0x04, 0x00000002 }, - { 0x002110, 1, 0x04, 0x00000003 }, - { 0x002150, 1, 0x04, 0x00000004 }, - { 0x000380, 4, 0x20, 0x00000000 }, - { 0x000384, 4, 0x20, 0x00000000 }, - { 0x000388, 4, 0x20, 0x00000000 }, - { 0x00038c, 4, 0x20, 0x00000000 }, - { 0x000700, 4, 0x10, 0x00000000 }, - { 0x000704, 4, 0x10, 0x00000000 }, - { 0x000708, 4, 0x10, 0x00000000 }, - { 0x002800, 128, 0x04, 0x00000000 }, - { 0x000a00, 16, 0x20, 0x00000000 }, - { 0x000a04, 16, 0x20, 0x00000000 }, - { 0x000a08, 16, 0x20, 0x00000000 }, - { 0x000a0c, 16, 0x20, 0x00000000 }, - { 0x000a10, 16, 0x20, 0x00000000 }, - { 0x000a14, 16, 0x20, 0x00000000 }, - { 0x000c00, 16, 0x10, 0x00000000 }, - { 0x000c04, 16, 0x10, 0x00000000 }, - { 0x000c08, 16, 0x10, 0x00000000 }, - { 0x000c0c, 16, 0x10, 0x3f800000 }, - { 0x000d00, 8, 0x08, 0xffff0000 }, - { 0x000d04, 8, 0x08, 0xffff0000 }, - { 0x000e00, 16, 0x10, 0x00000000 }, - { 0x000e04, 16, 0x10, 0xffff0000 }, - { 0x000e08, 16, 0x10, 0xffff0000 }, - { 0x000d40, 4, 0x08, 0x00000000 }, - { 0x000d44, 4, 0x08, 0x00000000 }, - { 0x001e00, 8, 0x20, 0x00000001 }, - { 0x001e04, 8, 0x20, 0x00000001 }, - { 0x001e08, 8, 0x20, 0x00000002 }, - { 0x001e0c, 8, 0x20, 0x00000001 }, - { 0x001e10, 8, 0x20, 0x00000001 }, - { 0x001e14, 8, 0x20, 0x00000002 }, - { 0x001e18, 8, 0x20, 0x00000001 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x001514, 1, 0x04, 0x00000000 }, - { 0x000d68, 1, 0x04, 0x0000ffff }, - { 0x00121c, 1, 0x04, 0x0fac6881 }, - { 0x000fac, 1, 0x04, 0x00000001 }, - { 0x001538, 1, 0x04, 0x00000001 }, - { 0x000fe0, 2, 0x04, 0x00000000 }, - { 0x000fe8, 1, 0x04, 0x00000014 }, - { 0x000fec, 1, 0x04, 0x00000040 }, - { 0x000ff0, 1, 0x04, 0x00000000 }, - { 0x00179c, 1, 0x04, 0x00000000 }, - { 0x001228, 1, 0x04, 0x00000400 }, - { 0x00122c, 1, 0x04, 0x00000300 }, - { 0x001230, 1, 0x04, 0x00010001 }, - { 0x0007f8, 1, 0x04, 0x00000000 }, - { 0x0015b4, 1, 0x04, 0x00000001 }, - { 0x0015cc, 1, 0x04, 0x00000000 }, - { 0x001534, 1, 0x04, 0x00000000 }, - { 0x000fb0, 1, 0x04, 0x00000000 }, - { 0x0015d0, 1, 0x04, 0x00000000 }, - { 0x00153c, 1, 0x04, 0x00000000 }, - { 0x0016b4, 1, 0x04, 0x00000003 }, - { 0x000fbc, 4, 0x04, 0x0000ffff }, - { 0x000df8, 2, 0x04, 0x00000000 }, - { 0x001948, 1, 0x04, 0x00000000 }, - { 0x001970, 1, 0x04, 0x00000001 }, - { 0x00161c, 1, 0x04, 0x000009f0 }, - { 0x000dcc, 1, 0x04, 0x00000010 }, - { 0x00163c, 1, 0x04, 0x00000000 }, - { 0x0015e4, 1, 0x04, 0x00000000 }, - { 0x001160, 32, 0x04, 0x25e00040 }, - { 0x001880, 32, 0x04, 0x00000000 }, - { 0x000f84, 2, 0x04, 0x00000000 }, - { 0x0017c8, 2, 0x04, 0x00000000 }, - { 0x0017d0, 1, 0x04, 0x000000ff }, - { 0x0017d4, 1, 0x04, 0xffffffff }, - { 0x0017d8, 1, 0x04, 0x00000002 }, - { 0x0017dc, 1, 0x04, 0x00000000 }, - { 0x0015f4, 2, 0x04, 0x00000000 }, - { 0x001434, 2, 0x04, 0x00000000 }, - { 0x000d74, 1, 0x04, 0x00000000 }, - { 0x000dec, 1, 0x04, 0x00000001 }, - { 0x0013a4, 1, 0x04, 0x00000000 }, - { 0x001318, 1, 0x04, 0x00000001 }, - { 0x001644, 1, 0x04, 0x00000000 }, - { 0x000748, 1, 0x04, 0x00000000 }, - { 0x000de8, 1, 0x04, 0x00000000 }, - { 0x001648, 1, 0x04, 0x00000000 }, - { 0x0012a4, 1, 0x04, 0x00000000 }, - { 0x001120, 4, 0x04, 0x00000000 }, - { 0x001118, 1, 0x04, 0x00000000 }, - { 0x00164c, 1, 0x04, 0x00000000 }, - { 0x001658, 1, 0x04, 0x00000000 }, - { 0x001910, 1, 0x04, 0x00000290 }, - { 0x001518, 1, 0x04, 0x00000000 }, - { 0x00165c, 1, 0x04, 0x00000001 }, - { 0x001520, 1, 0x04, 0x00000000 }, - { 0x001604, 1, 0x04, 0x00000000 }, - { 0x001570, 1, 0x04, 0x00000000 }, - { 0x0013b0, 2, 0x04, 0x3f800000 }, - { 0x00020c, 1, 0x04, 0x00000000 }, - { 0x001670, 1, 0x04, 0x30201000 }, - { 0x001674, 1, 0x04, 0x70605040 }, - { 0x001678, 1, 0x04, 0xb8a89888 }, - { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, - { 0x00166c, 1, 0x04, 0x00000000 }, - { 0x001680, 1, 0x04, 0x00ffff00 }, - { 0x0012d0, 1, 0x04, 0x00000003 }, - { 0x0012d4, 1, 0x04, 0x00000002 }, - { 0x001684, 2, 0x04, 0x00000000 }, - { 0x000dac, 2, 0x04, 0x00001b02 }, - { 0x000db4, 1, 0x04, 0x00000000 }, - { 0x00168c, 1, 0x04, 0x00000000 }, - { 0x0015bc, 1, 0x04, 0x00000000 }, - { 0x00156c, 1, 0x04, 0x00000000 }, - { 0x00187c, 1, 0x04, 0x00000000 }, - { 0x001110, 1, 0x04, 0x00000001 }, - { 0x000dc0, 3, 0x04, 0x00000000 }, - { 0x001234, 1, 0x04, 0x00000000 }, - { 0x001690, 1, 0x04, 0x00000000 }, - { 0x0012ac, 1, 0x04, 0x00000001 }, - { 0x0002c4, 1, 0x04, 0x00000000 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x001000, 1, 0x04, 0x00000010 }, - { 0x0010fc, 1, 0x04, 0x00000000 }, - { 0x001290, 1, 0x04, 0x00000000 }, - { 0x000218, 1, 0x04, 0x00000010 }, - { 0x0012d8, 1, 0x04, 0x00000000 }, - { 0x0012dc, 1, 0x04, 0x00000010 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x00155c, 2, 0x04, 0x00000000 }, - { 0x001564, 1, 0x04, 0x00001fff }, - { 0x001574, 2, 0x04, 0x00000000 }, - { 0x00157c, 1, 0x04, 0x003fffff }, - { 0x001354, 1, 0x04, 0x00000000 }, - { 0x001664, 1, 0x04, 0x00000000 }, - { 0x001610, 1, 0x04, 0x00000012 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x00162c, 1, 0x04, 0x00000003 }, - { 0x000210, 1, 0x04, 0x00000000 }, - { 0x000320, 1, 0x04, 0x00000000 }, - { 0x000324, 6, 0x04, 0x3f800000 }, - { 0x000750, 1, 0x04, 0x00000000 }, - { 0x000760, 1, 0x04, 0x39291909 }, - { 0x000764, 1, 0x04, 0x79695949 }, - { 0x000768, 1, 0x04, 0xb9a99989 }, - { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, - { 0x000770, 1, 0x04, 0x30201000 }, - { 0x000774, 1, 0x04, 0x70605040 }, - { 0x000778, 1, 0x04, 0x00009080 }, - { 0x000780, 1, 0x04, 0x39291909 }, - { 0x000784, 1, 0x04, 0x79695949 }, - { 0x000788, 1, 0x04, 0xb9a99989 }, - { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, - { 0x0007d0, 1, 0x04, 0x30201000 }, - { 0x0007d4, 1, 0x04, 0x70605040 }, - { 0x0007d8, 1, 0x04, 0x00009080 }, - { 0x00037c, 1, 0x04, 0x00000001 }, - { 0x000740, 2, 0x04, 0x00000000 }, - { 0x002600, 1, 0x04, 0x00000000 }, - { 0x001918, 1, 0x04, 0x00000000 }, - { 0x00191c, 1, 0x04, 0x00000900 }, - { 0x001920, 1, 0x04, 0x00000405 }, - { 0x001308, 1, 0x04, 0x00000001 }, - { 0x001924, 1, 0x04, 0x00000000 }, - { 0x0013ac, 1, 0x04, 0x00000000 }, - { 0x00192c, 1, 0x04, 0x00000001 }, - { 0x00193c, 1, 0x04, 0x00002c1c }, - { 0x000d7c, 1, 0x04, 0x00000000 }, - { 0x000f8c, 1, 0x04, 0x00000000 }, - { 0x0002c0, 1, 0x04, 0x00000001 }, - { 0x001510, 1, 0x04, 0x00000000 }, - { 0x001940, 1, 0x04, 0x00000000 }, - { 0x000ff4, 2, 0x04, 0x00000000 }, - { 0x00194c, 2, 0x04, 0x00000000 }, - { 0x001968, 1, 0x04, 0x00000000 }, - { 0x001590, 1, 0x04, 0x0000003f }, - { 0x0007e8, 4, 0x04, 0x00000000 }, - { 0x00196c, 1, 0x04, 0x00000011 }, - { 0x00197c, 1, 0x04, 0x00000000 }, - { 0x000fcc, 2, 0x04, 0x00000000 }, - { 0x0002d8, 1, 0x04, 0x00000040 }, - { 0x001980, 1, 0x04, 0x00000080 }, - { 0x001504, 1, 0x04, 0x00000080 }, - { 0x001984, 1, 0x04, 0x00000000 }, - { 0x000300, 1, 0x04, 0x00000001 }, - { 0x0013a8, 1, 0x04, 0x00000000 }, - { 0x0012ec, 1, 0x04, 0x00000000 }, - { 0x001310, 1, 0x04, 0x00000000 }, - { 0x001314, 1, 0x04, 0x00000001 }, - { 0x001380, 1, 0x04, 0x00000000 }, - { 0x001384, 4, 0x04, 0x00000001 }, - { 0x001394, 1, 0x04, 0x00000000 }, - { 0x00139c, 1, 0x04, 0x00000000 }, - { 0x001398, 1, 0x04, 0x00000000 }, - { 0x001594, 1, 0x04, 0x00000000 }, - { 0x001598, 4, 0x04, 0x00000001 }, - { 0x000f54, 3, 0x04, 0x00000000 }, - { 0x0019bc, 1, 0x04, 0x00000000 }, - { 0x000f9c, 2, 0x04, 0x00000000 }, - { 0x0012cc, 1, 0x04, 0x00000000 }, - { 0x0012e8, 1, 0x04, 0x00000000 }, - { 0x00130c, 1, 0x04, 0x00000001 }, - { 0x001360, 8, 0x04, 0x00000000 }, - { 0x00133c, 2, 0x04, 0x00000001 }, - { 0x001344, 1, 0x04, 0x00000002 }, - { 0x001348, 2, 0x04, 0x00000001 }, - { 0x001350, 1, 0x04, 0x00000002 }, - { 0x001358, 1, 0x04, 0x00000001 }, - { 0x0012e4, 1, 0x04, 0x00000000 }, - { 0x00131c, 4, 0x04, 0x00000000 }, - { 0x0019c0, 1, 0x04, 0x00000000 }, - { 0x001140, 1, 0x04, 0x00000000 }, - { 0x0019c4, 1, 0x04, 0x00000000 }, - { 0x0019c8, 1, 0x04, 0x00001500 }, - { 0x00135c, 1, 0x04, 0x00000000 }, - { 0x000f90, 1, 0x04, 0x00000000 }, - { 0x0019e0, 8, 0x04, 0x00000001 }, - { 0x0019cc, 1, 0x04, 0x00000001 }, - { 0x0015b8, 1, 0x04, 0x00000000 }, - { 0x001a00, 1, 0x04, 0x00001111 }, - { 0x001a04, 7, 0x04, 0x00000000 }, - { 0x000d6c, 2, 0x04, 0xffff0000 }, - { 0x0010f8, 1, 0x04, 0x00001010 }, - { 0x000d80, 5, 0x04, 0x00000000 }, - { 0x000da0, 1, 0x04, 0x00000000 }, - { 0x001508, 1, 0x04, 0x80000000 }, - { 0x00150c, 1, 0x04, 0x40000000 }, - { 0x001668, 1, 0x04, 0x00000000 }, - { 0x000318, 2, 0x04, 0x00000008 }, - { 0x000d9c, 1, 0x04, 0x00000001 }, - { 0x0007dc, 1, 0x04, 0x00000000 }, - { 0x00074c, 1, 0x04, 0x00000055 }, - { 0x001420, 1, 0x04, 0x00000003 }, - { 0x0017bc, 2, 0x04, 0x00000000 }, - { 0x0017c4, 1, 0x04, 0x00000001 }, - { 0x001008, 1, 0x04, 0x00000008 }, - { 0x00100c, 1, 0x04, 0x00000040 }, - { 0x001010, 1, 0x04, 0x0000012c }, - { 0x000d60, 1, 0x04, 0x00000040 }, - { 0x00075c, 1, 0x04, 0x00000003 }, - { 0x001018, 1, 0x04, 0x00000020 }, - { 0x00101c, 1, 0x04, 0x00000001 }, - { 0x001020, 1, 0x04, 0x00000020 }, - { 0x001024, 1, 0x04, 0x00000001 }, - { 0x001444, 3, 0x04, 0x00000000 }, - { 0x000360, 1, 0x04, 0x20164010 }, - { 0x000364, 1, 0x04, 0x00000020 }, - { 0x000368, 1, 0x04, 0x00000000 }, - { 0x000de4, 1, 0x04, 0x00000000 }, - { 0x000204, 1, 0x04, 0x00000006 }, - { 0x000208, 1, 0x04, 0x00000000 }, - { 0x0002cc, 1, 0x04, 0x003fffff }, - { 0x0002d0, 1, 0x04, 0x00000c48 }, - { 0x001220, 1, 0x04, 0x00000005 }, - { 0x000fdc, 1, 0x04, 0x00000000 }, - { 0x000f98, 1, 0x04, 0x00300008 }, - { 0x001284, 1, 0x04, 0x04000080 }, - { 0x001450, 1, 0x04, 0x00300008 }, - { 0x001454, 1, 0x04, 0x04000080 }, - { 0x000214, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc1_grctx_init_9197_0[] = { - { 0x003400, 128, 0x04, 0x00000000 }, - { 0x0002e4, 1, 0x04, 0x0000b001 }, - {} -}; - -static const struct nvc0_graph_pack -nvc1_grctx_pack_mthd[] = { - { nvc1_grctx_init_9097_0, 0x9097 }, - { nvc1_grctx_init_9197_0, 0x9197 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvc0_grctx_init_90c0_0, 0x90c0 }, - {} -}; - -static const struct nvc0_graph_init -nvc1_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x0f8000bf }, - { 0x405830, 1, 0x04, 0x02180218 }, - { 0x405834, 2, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc1_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x000103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b4, 2, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x80140078 }, - { 0x4064c4, 1, 0x04, 0x0086ffff }, - {} -}; - -static const struct nvc0_graph_init -nvc1_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x02802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x1003e005 }, - { 0x408900, 1, 0x04, 0x3080b801 }, - { 0x408904, 1, 0x04, 0x62000001 }, - { 0x408908, 1, 0x04, 0x00c80929 }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -static const struct nvc0_graph_pack -nvc1_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvc0_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvc1_grctx_init_ds_0 }, - { nvc1_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvc1_grctx_init_be_0 }, - {} -}; - -static const struct nvc0_graph_init -nvc1_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x0006860a }, - { 0x418808, 3, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00008442 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x00100018 }, - {} -}; - -const struct nvc0_graph_init -nvc1_grctx_init_gpm_0[] = { - { 0x418c08, 1, 0x04, 0x00000001 }, - { 0x418c10, 8, 0x04, 0x00000000 }, - { 0x418c6c, 1, 0x04, 0x00000001 }, - { 0x418c80, 1, 0x04, 0x20200004 }, - { 0x418c8c, 1, 0x04, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_pack -nvc1_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvc0_grctx_init_prop_0 }, - { nvc0_grctx_init_gpc_unk_1 }, - { nvc1_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvc0_grctx_init_crstr_0 }, - { nvc1_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -const struct nvc0_graph_init -nvc1_grctx_init_pe_0[] = { - { 0x419818, 1, 0x04, 0x00000000 }, - { 0x41983c, 1, 0x04, 0x00038bc7 }, - { 0x419848, 1, 0x04, 0x00000000 }, - { 0x419864, 1, 0x04, 0x00000129 }, - { 0x419888, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc1_grctx_init_wwdx_0[] = { - { 0x419b00, 1, 0x04, 0x0a418820 }, - { 0x419b04, 1, 0x04, 0x062080e6 }, - { 0x419b08, 1, 0x04, 0x020398a4 }, - { 0x419b0c, 1, 0x04, 0x0e629062 }, - { 0x419b10, 1, 0x04, 0x0a418820 }, - { 0x419b14, 1, 0x04, 0x000000e6 }, - { 0x419bd0, 1, 0x04, 0x00900103 }, - { 0x419be0, 1, 0x04, 0x00400001 }, - { 0x419be4, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc1_grctx_init_tpccs_0[] = { - { 0x419d20, 1, 0x04, 0x12180000 }, - { 0x419d24, 1, 0x04, 0x00001fff }, - { 0x419d44, 1, 0x04, 0x02180218 }, - {} -}; - -static const struct nvc0_graph_pack -nvc1_grctx_pack_tpc[] = { - { nvc1_grctx_init_pe_0 }, - { nvc4_grctx_init_tex_0 }, - { nvc1_grctx_init_wwdx_0 }, - { nvc0_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvc1_grctx_init_tpccs_0 }, - { nvc4_grctx_init_sm_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -void -nvc1_grctx_generate_attrib(struct nvc0_grctx *info) -{ - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); - const u32 alpha = impl->alpha_nr; - const u32 beta = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); - const u32 access = NV_MEM_ACCESS_RW; - const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); - const int timeslice_mode = 1; - const int max_batches = 0xffff; - u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; - int gpc, tpc; - - mmio_refn(info, 0x418810, 0x80000000, s, b); - mmio_refn(info, 0x419848, 0x10000000, s, b); - mmio_wr32(info, 0x405830, (beta << 16) | alpha); - mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - const u32 a = alpha; - const u32 b = beta; - const u32 t = timeslice_mode; - const u32 o = TPC_UNIT(gpc, tpc, 0x500); - mmio_skip(info, o + 0x20, (t << 28) | (b << 16) | ++bo); - mmio_wr32(info, o + 0x20, (t << 28) | (b << 16) | --bo); - bo += impl->attrib_nr_max; - mmio_wr32(info, o + 0x44, (a << 16) | ao); - ao += impl->alpha_nr_max; - } - } -} - -void -nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv) -{ - nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); - nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); - nv_mask(priv, 0x419814, 0x00000004, 0x00000004); - nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); - nv_mask(priv, 0x405800, 0x08000000, 0x08000000); - nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); -} - -struct nouveau_oclass * -nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nvc0_grctx_generate_main, - .unkn = nvc1_grctx_generate_unkn, - .hub = nvc1_grctx_pack_hub, - .gpc = nvc1_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc1_grctx_pack_tpc, - .icmd = nvc1_grctx_pack_icmd, - .mthd = nvc1_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, - .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvc1_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x324, - .alpha_nr = 0x218, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c deleted file mode 100644 index 41705c60cc47..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nvc4_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000001f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000023 }, - { 0x419a0c, 1, 0x04, 0x00020000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - { 0x419a1c, 1, 0x04, 0x00000000 }, - { 0x419a20, 1, 0x04, 0x00000800 }, - { 0x419ac4, 1, 0x04, 0x0007f440 }, - {} -}; - -const struct nvc0_graph_init -nvc4_grctx_init_l1c_0[] = { - { 0x419cb0, 1, 0x04, 0x00020048 }, - { 0x419ce8, 1, 0x04, 0x00000000 }, - { 0x419cf4, 1, 0x04, 0x00000183 }, - {} -}; - -const struct nvc0_graph_init -nvc4_grctx_init_sm_0[] = { - { 0x419e04, 3, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00000002 }, - { 0x419e44, 1, 0x04, 0x001beff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000000f }, - { 0x419e50, 17, 0x04, 0x00000000 }, - { 0x419e98, 1, 0x04, 0x00000000 }, - { 0x419ee0, 1, 0x04, 0x00011110 }, - { 0x419f30, 11, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvc4_grctx_pack_tpc[] = { - { nvc0_grctx_init_pe_0 }, - { nvc4_grctx_init_tex_0 }, - { nvc0_grctx_init_wwdx_0 }, - { nvc0_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvc0_grctx_init_tpccs_0 }, - { nvc4_grctx_init_sm_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -struct nouveau_oclass * -nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nvc0_grctx_generate_main, - .unkn = nvc0_grctx_generate_unkn, - .hub = nvc0_grctx_pack_hub, - .gpc = nvc0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc4_grctx_pack_tpc, - .icmd = nvc0_grctx_pack_icmd, - .mthd = nvc0_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, - .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvc0_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c deleted file mode 100644 index 8f804cd8f9c7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvc8_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000b2, 40, 0x01, 0x00000000 }, - { 0x000210, 8, 0x01, 0x00000040 }, - { 0x000218, 8, 0x01, 0x0000c080 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00001fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x003fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x0005e0, 5, 0x01, 0x00000022 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x00097d, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x00000c48 }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00300008 }, - { 0x000841, 1, 0x01, 0x04000080 }, - { 0x000842, 1, 0x01, 0x00300008 }, - { 0x000843, 1, 0x01, 0x04000080 }, - { 0x000818, 8, 0x01, 0x00000000 }, - { 0x000848, 16, 0x01, 0x00000000 }, - { 0x000738, 1, 0x01, 0x00000000 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x000944, 1, 0x01, 0x00000022 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000014 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_pack -nvc8_grctx_pack_icmd[] = { - { nvc8_grctx_init_icmd_0 }, - {} -}; - -const struct nvc0_graph_init -nvc8_grctx_init_9197_0[] = { - { 0x0002e4, 1, 0x04, 0x0000b001 }, - {} -}; - -const struct nvc0_graph_init -nvc8_grctx_init_9297_0[] = { - { 0x003400, 128, 0x04, 0x00000000 }, - { 0x00036c, 2, 0x04, 0x00000000 }, - { 0x0007a4, 2, 0x04, 0x00000000 }, - { 0x000374, 1, 0x04, 0x00000000 }, - { 0x000378, 1, 0x04, 0x00000020 }, - {} -}; - -static const struct nvc0_graph_pack -nvc8_grctx_pack_mthd[] = { - { nvc1_grctx_init_9097_0, 0x9097 }, - { nvc8_grctx_init_9197_0, 0x9197 }, - { nvc8_grctx_init_9297_0, 0x9297 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvc0_grctx_init_90c0_0, 0x90c0 }, - {} -}; - -static const struct nvc0_graph_init -nvc8_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x0006860a }, - { 0x418808, 3, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00008442 }, - { 0x418830, 1, 0x04, 0x00000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100000 }, - {} -}; - -static const struct nvc0_graph_pack -nvc8_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvc0_grctx_init_prop_0 }, - { nvc0_grctx_init_gpc_unk_1 }, - { nvc8_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvc0_grctx_init_crstr_0 }, - { nvc0_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -struct nouveau_oclass * -nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc8), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nvc0_grctx_generate_main, - .unkn = nvc0_grctx_generate_unkn, - .hub = nvc0_grctx_pack_hub, - .gpc = nvc8_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc0_grctx_pack_tpc, - .icmd = nvc8_grctx_pack_icmd, - .mthd = nvc8_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, - .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvc0_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c deleted file mode 100644 index fcf534fd9e65..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvd7_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x0f8000bf }, - { 0x405830, 1, 0x04, 0x02180324 }, - { 0x405834, 1, 0x04, 0x08000000 }, - { 0x405838, 1, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd7_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x000103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b4, 3, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x801a0078 }, - { 0x4064c4, 1, 0x04, 0x00c9ffff }, - { 0x4064d0, 8, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvd7_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvd9_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvd7_grctx_init_ds_0 }, - { nvd7_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvd9_grctx_init_be_0 }, - {} -}; - -static const struct nvc0_graph_init -nvd7_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x7006860a }, - { 0x418808, 3, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00008442 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100018 }, - {} -}; - -static const struct nvc0_graph_pack -nvd7_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nvd7_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nvc1_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -const struct nvc0_graph_init -nvd7_grctx_init_pe_0[] = { - { 0x419848, 1, 0x04, 0x00000000 }, - { 0x419864, 1, 0x04, 0x00000129 }, - { 0x419888, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd7_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000001f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000023 }, - { 0x419a0c, 1, 0x04, 0x00020000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - { 0x419a1c, 1, 0x04, 0x00008000 }, - { 0x419a20, 1, 0x04, 0x00000800 }, - { 0x419ac4, 1, 0x04, 0x0017f440 }, - {} -}; - -static const struct nvc0_graph_init -nvd7_grctx_init_mpc_0[] = { - { 0x419c00, 1, 0x04, 0x0000000a }, - { 0x419c04, 1, 0x04, 0x00000006 }, - { 0x419c08, 1, 0x04, 0x00000002 }, - { 0x419c20, 1, 0x04, 0x00000000 }, - { 0x419c24, 1, 0x04, 0x00084210 }, - { 0x419c28, 1, 0x04, 0x3efbefbe }, - {} -}; - -static const struct nvc0_graph_pack -nvd7_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nvd7_grctx_init_tex_0 }, - { nvd7_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvd9_grctx_init_sm_0 }, - {} -}; - -static const struct nvc0_graph_init -nvd7_grctx_init_pes_0[] = { - { 0x41be24, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_init -nvd7_grctx_init_cbm_0[] = { - { 0x41bec0, 1, 0x04, 0x12180000 }, - { 0x41bec4, 1, 0x04, 0x00003fff }, - { 0x41bee4, 1, 0x04, 0x03240218 }, - {} -}; - -const struct nvc0_graph_init -nvd7_grctx_init_wwdx_0[] = { - { 0x41bf00, 1, 0x04, 0x0a418820 }, - { 0x41bf04, 1, 0x04, 0x062080e6 }, - { 0x41bf08, 1, 0x04, 0x020398a4 }, - { 0x41bf0c, 1, 0x04, 0x0e629062 }, - { 0x41bf10, 1, 0x04, 0x0a418820 }, - { 0x41bf14, 1, 0x04, 0x000000e6 }, - { 0x41bfd0, 1, 0x04, 0x00900103 }, - { 0x41bfe0, 1, 0x04, 0x00400001 }, - { 0x41bfe4, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvd7_grctx_pack_ppc[] = { - { nvd7_grctx_init_pes_0 }, - { nvd7_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -void -nvd7_grctx_generate_attrib(struct nvc0_grctx *info) -{ - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); - const u32 alpha = impl->alpha_nr; - const u32 beta = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); - const u32 access = NV_MEM_ACCESS_RW; - const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); - const int timeslice_mode = 1; - const int max_batches = 0xffff; - u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; - int gpc, ppc; - - mmio_refn(info, 0x418810, 0x80000000, s, b); - mmio_refn(info, 0x419848, 0x10000000, s, b); - mmio_wr32(info, 0x405830, (beta << 16) | alpha); - mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) { - const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc]; - const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc]; - const u32 t = timeslice_mode; - const u32 o = PPC_UNIT(gpc, ppc, 0); - mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); - mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); - bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; - mmio_wr32(info, o + 0xe4, (a << 16) | ao); - ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; - } - } -} - -void -nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) -{ - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - int i; - - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); - - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); - - nv_wr32(priv, 0x404154, 0x00000000); - - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(priv); - - nvc0_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nvc0_grctx_generate_r4060a8(priv); - nve4_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); - - for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - - nvc0_graph_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); -} - -struct nouveau_oclass * -nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xd7), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nvd7_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nvd7_grctx_pack_hub, - .gpc = nvd7_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvd7_grctx_pack_tpc, - .ppc = nvd7_grctx_pack_ppc, - .icmd = nvd9_grctx_pack_icmd, - .mthd = nvd9_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, - .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x7ff, - .alpha_nr = 0x324, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c deleted file mode 100644 index b9a301b6fd9f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c +++ /dev/null @@ -1,530 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvd9_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000b2, 40, 0x01, 0x00000000 }, - { 0x000210, 8, 0x01, 0x00000040 }, - { 0x000400, 24, 0x01, 0x00000040 }, - { 0x000218, 8, 0x01, 0x0000c080 }, - { 0x000440, 24, 0x01, 0x0000c080 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00001fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x003fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x0005e0, 5, 0x01, 0x00000022 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x00097d, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x00000c48 }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00300008 }, - { 0x000841, 1, 0x01, 0x04000080 }, - { 0x000842, 1, 0x01, 0x00300008 }, - { 0x000843, 1, 0x01, 0x04000080 }, - { 0x000818, 8, 0x01, 0x00000000 }, - { 0x000848, 16, 0x01, 0x00000000 }, - { 0x000738, 1, 0x01, 0x00000000 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x000944, 1, 0x01, 0x00000022 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000014 }, - { 0x000351, 1, 0x01, 0x00000100 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095d, 1, 0x01, 0x00000001 }, - { 0x00082b, 1, 0x01, 0x00000004 }, - { 0x000942, 1, 0x01, 0x00010001 }, - { 0x000943, 1, 0x01, 0x00000001 }, - { 0x0007c5, 1, 0x01, 0x00010001 }, - { 0x000834, 1, 0x01, 0x00000001 }, - { 0x0007c7, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x00080c, 1, 0x01, 0x00000002 }, - { 0x00080d, 2, 0x01, 0x00000100 }, - { 0x00080f, 1, 0x01, 0x00000001 }, - { 0x000823, 1, 0x01, 0x00000002 }, - { 0x000824, 2, 0x01, 0x00000100 }, - { 0x000826, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -const struct nvc0_graph_pack -nvd9_grctx_pack_icmd[] = { - { nvd9_grctx_init_icmd_0 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_grctx_init_90c0_0[] = { - { 0x002700, 8, 0x20, 0x00000000 }, - { 0x002704, 8, 0x20, 0x00000000 }, - { 0x002708, 8, 0x20, 0x00000000 }, - { 0x00270c, 8, 0x20, 0x00000000 }, - { 0x002710, 8, 0x20, 0x00014000 }, - { 0x002714, 8, 0x20, 0x00000040 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x000758, 1, 0x04, 0x00000100 }, - { 0x0002c4, 1, 0x04, 0x00000000 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x000204, 3, 0x04, 0x00000000 }, - { 0x000214, 1, 0x04, 0x00000000 }, - { 0x00024c, 1, 0x04, 0x00000000 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x001664, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvd9_grctx_pack_mthd[] = { - { nvc1_grctx_init_9097_0, 0x9097 }, - { nvc8_grctx_init_9197_0, 0x9197 }, - { nvc8_grctx_init_9297_0, 0x9297 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvd9_grctx_init_90c0_0, 0x90c0 }, - {} -}; - -const struct nvc0_graph_init -nvd9_grctx_init_fe_0[] = { - { 0x404004, 10, 0x04, 0x00000000 }, - { 0x404044, 1, 0x04, 0x00000000 }, - { 0x404094, 13, 0x04, 0x00000000 }, - { 0x4040c8, 1, 0x04, 0xf0000087 }, - { 0x4040d0, 6, 0x04, 0x00000000 }, - { 0x4040e8, 1, 0x04, 0x00001000 }, - { 0x4040f8, 1, 0x04, 0x00000000 }, - { 0x404130, 2, 0x04, 0x00000000 }, - { 0x404138, 1, 0x04, 0x20000040 }, - { 0x404150, 1, 0x04, 0x0000002e }, - { 0x404154, 1, 0x04, 0x00000400 }, - { 0x404158, 1, 0x04, 0x00000200 }, - { 0x404164, 1, 0x04, 0x00000055 }, - { 0x404168, 1, 0x04, 0x00000000 }, - { 0x404178, 2, 0x04, 0x00000000 }, - { 0x404200, 8, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x0f8000bf }, - { 0x405830, 1, 0x04, 0x02180218 }, - { 0x405834, 1, 0x04, 0x08000000 }, - { 0x405838, 1, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x000103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b4, 3, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x80140078 }, - { 0x4064c4, 1, 0x04, 0x0086ffff }, - {} -}; - -const struct nvc0_graph_init -nvd9_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x02802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x1043e005 }, - { 0x408900, 1, 0x04, 0x3080b801 }, - { 0x408904, 1, 0x04, 0x62000001 }, - { 0x408908, 1, 0x04, 0x00c8102f }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -static const struct nvc0_graph_pack -nvd9_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvd9_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvd9_grctx_init_ds_0 }, - { nvd9_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvd9_grctx_init_be_0 }, - {} -}; - -const struct nvc0_graph_init -nvd9_grctx_init_prop_0[] = { - { 0x418400, 1, 0x04, 0x38004e00 }, - { 0x418404, 1, 0x04, 0x71e0ffff }, - { 0x41840c, 1, 0x04, 0x00001008 }, - { 0x418410, 1, 0x04, 0x0fff0fff }, - { 0x418414, 1, 0x04, 0x02200fff }, - { 0x418450, 6, 0x04, 0x00000000 }, - { 0x418468, 1, 0x04, 0x00000001 }, - { 0x41846c, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_grctx_init_gpc_unk_1[] = { - { 0x418600, 1, 0x04, 0x0000001f }, - { 0x418684, 1, 0x04, 0x0000000f }, - { 0x418700, 1, 0x04, 0x00000002 }, - { 0x418704, 1, 0x04, 0x00000080 }, - { 0x418708, 3, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x7006860a }, - { 0x418808, 3, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00008442 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100008 }, - {} -}; - -const struct nvc0_graph_init -nvd9_grctx_init_crstr_0[] = { - { 0x418b00, 1, 0x04, 0x00000006 }, - { 0x418b08, 1, 0x04, 0x0a418820 }, - { 0x418b0c, 1, 0x04, 0x062080e6 }, - { 0x418b10, 1, 0x04, 0x020398a4 }, - { 0x418b14, 1, 0x04, 0x0e629062 }, - { 0x418b18, 1, 0x04, 0x0a418820 }, - { 0x418b1c, 1, 0x04, 0x000000e6 }, - { 0x418bb8, 1, 0x04, 0x00000103 }, - {} -}; - -static const struct nvc0_graph_pack -nvd9_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nvd9_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nvc1_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000001f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000023 }, - { 0x419a0c, 1, 0x04, 0x00020000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - { 0x419a1c, 1, 0x04, 0x00000000 }, - { 0x419a20, 1, 0x04, 0x00000800 }, - { 0x419ac4, 1, 0x04, 0x0017f440 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_grctx_init_mpc_0[] = { - { 0x419c00, 1, 0x04, 0x0000000a }, - { 0x419c04, 1, 0x04, 0x00000006 }, - { 0x419c08, 1, 0x04, 0x00000002 }, - { 0x419c20, 1, 0x04, 0x00000000 }, - { 0x419c24, 1, 0x04, 0x00084210 }, - { 0x419c28, 1, 0x04, 0x3cf3cf3c }, - {} -}; - -const struct nvc0_graph_init -nvd9_grctx_init_sm_0[] = { - { 0x419e04, 3, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00000002 }, - { 0x419e44, 1, 0x04, 0x001beff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000000f }, - { 0x419e50, 17, 0x04, 0x00000000 }, - { 0x419e98, 1, 0x04, 0x00000000 }, - { 0x419ee0, 1, 0x04, 0x00010110 }, - { 0x419f30, 11, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvd9_grctx_pack_tpc[] = { - { nvc1_grctx_init_pe_0 }, - { nvd9_grctx_init_tex_0 }, - { nvc1_grctx_init_wwdx_0 }, - { nvd9_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvc1_grctx_init_tpccs_0 }, - { nvd9_grctx_init_sm_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -struct nouveau_oclass * -nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xd9), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nvc0_grctx_generate_main, - .unkn = nvc1_grctx_generate_unkn, - .hub = nvd9_grctx_pack_hub, - .gpc = nvd9_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvd9_grctx_pack_tpc, - .icmd = nvd9_grctx_pack_icmd, - .mthd = nvd9_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, - .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvc1_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x324, - .alpha_nr = 0x218, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c deleted file mode 100644 index ccac2ee1a1cb..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c +++ /dev/null @@ -1,1020 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nve4_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000383, 1, 0x01, 0x00000011 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x00097d, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x003fffff }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00400008 }, - { 0x000841, 1, 0x01, 0x08000080 }, - { 0x000842, 1, 0x01, 0x00400008 }, - { 0x000843, 1, 0x01, 0x08000080 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x00c500, 1, 0x01, 0x00000003 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000008 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x00c500, 1, 0x01, 0x00000003 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -const struct nvc0_graph_pack -nve4_grctx_pack_icmd[] = { - { nve4_grctx_init_icmd_0 }, - {} -}; - -const struct nvc0_graph_init -nve4_grctx_init_a097_0[] = { - { 0x000800, 8, 0x40, 0x00000000 }, - { 0x000804, 8, 0x40, 0x00000000 }, - { 0x000808, 8, 0x40, 0x00000400 }, - { 0x00080c, 8, 0x40, 0x00000300 }, - { 0x000810, 1, 0x04, 0x000000cf }, - { 0x000850, 7, 0x40, 0x00000000 }, - { 0x000814, 8, 0x40, 0x00000040 }, - { 0x000818, 8, 0x40, 0x00000001 }, - { 0x00081c, 8, 0x40, 0x00000000 }, - { 0x000820, 8, 0x40, 0x00000000 }, - { 0x001c00, 16, 0x10, 0x00000000 }, - { 0x001c04, 16, 0x10, 0x00000000 }, - { 0x001c08, 16, 0x10, 0x00000000 }, - { 0x001c0c, 16, 0x10, 0x00000000 }, - { 0x001d00, 16, 0x10, 0x00000000 }, - { 0x001d04, 16, 0x10, 0x00000000 }, - { 0x001d08, 16, 0x10, 0x00000000 }, - { 0x001d0c, 16, 0x10, 0x00000000 }, - { 0x001f00, 16, 0x08, 0x00000000 }, - { 0x001f04, 16, 0x08, 0x00000000 }, - { 0x001f80, 16, 0x08, 0x00000000 }, - { 0x001f84, 16, 0x08, 0x00000000 }, - { 0x002000, 1, 0x04, 0x00000000 }, - { 0x002040, 1, 0x04, 0x00000011 }, - { 0x002080, 1, 0x04, 0x00000020 }, - { 0x0020c0, 1, 0x04, 0x00000030 }, - { 0x002100, 1, 0x04, 0x00000040 }, - { 0x002140, 1, 0x04, 0x00000051 }, - { 0x00200c, 6, 0x40, 0x00000001 }, - { 0x002010, 1, 0x04, 0x00000000 }, - { 0x002050, 1, 0x04, 0x00000000 }, - { 0x002090, 1, 0x04, 0x00000001 }, - { 0x0020d0, 1, 0x04, 0x00000002 }, - { 0x002110, 1, 0x04, 0x00000003 }, - { 0x002150, 1, 0x04, 0x00000004 }, - { 0x000380, 4, 0x20, 0x00000000 }, - { 0x000384, 4, 0x20, 0x00000000 }, - { 0x000388, 4, 0x20, 0x00000000 }, - { 0x00038c, 4, 0x20, 0x00000000 }, - { 0x000700, 4, 0x10, 0x00000000 }, - { 0x000704, 4, 0x10, 0x00000000 }, - { 0x000708, 4, 0x10, 0x00000000 }, - { 0x002800, 128, 0x04, 0x00000000 }, - { 0x000a00, 16, 0x20, 0x00000000 }, - { 0x000a04, 16, 0x20, 0x00000000 }, - { 0x000a08, 16, 0x20, 0x00000000 }, - { 0x000a0c, 16, 0x20, 0x00000000 }, - { 0x000a10, 16, 0x20, 0x00000000 }, - { 0x000a14, 16, 0x20, 0x00000000 }, - { 0x000c00, 16, 0x10, 0x00000000 }, - { 0x000c04, 16, 0x10, 0x00000000 }, - { 0x000c08, 16, 0x10, 0x00000000 }, - { 0x000c0c, 16, 0x10, 0x3f800000 }, - { 0x000d00, 8, 0x08, 0xffff0000 }, - { 0x000d04, 8, 0x08, 0xffff0000 }, - { 0x000e00, 16, 0x10, 0x00000000 }, - { 0x000e04, 16, 0x10, 0xffff0000 }, - { 0x000e08, 16, 0x10, 0xffff0000 }, - { 0x000d40, 4, 0x08, 0x00000000 }, - { 0x000d44, 4, 0x08, 0x00000000 }, - { 0x001e00, 8, 0x20, 0x00000001 }, - { 0x001e04, 8, 0x20, 0x00000001 }, - { 0x001e08, 8, 0x20, 0x00000002 }, - { 0x001e0c, 8, 0x20, 0x00000001 }, - { 0x001e10, 8, 0x20, 0x00000001 }, - { 0x001e14, 8, 0x20, 0x00000002 }, - { 0x001e18, 8, 0x20, 0x00000001 }, - { 0x003400, 128, 0x04, 0x00000000 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x001514, 1, 0x04, 0x00000000 }, - { 0x000d68, 1, 0x04, 0x0000ffff }, - { 0x00121c, 1, 0x04, 0x0fac6881 }, - { 0x000fac, 1, 0x04, 0x00000001 }, - { 0x001538, 1, 0x04, 0x00000001 }, - { 0x000fe0, 2, 0x04, 0x00000000 }, - { 0x000fe8, 1, 0x04, 0x00000014 }, - { 0x000fec, 1, 0x04, 0x00000040 }, - { 0x000ff0, 1, 0x04, 0x00000000 }, - { 0x00179c, 1, 0x04, 0x00000000 }, - { 0x001228, 1, 0x04, 0x00000400 }, - { 0x00122c, 1, 0x04, 0x00000300 }, - { 0x001230, 1, 0x04, 0x00010001 }, - { 0x0007f8, 1, 0x04, 0x00000000 }, - { 0x0015b4, 1, 0x04, 0x00000001 }, - { 0x0015cc, 1, 0x04, 0x00000000 }, - { 0x001534, 1, 0x04, 0x00000000 }, - { 0x000fb0, 1, 0x04, 0x00000000 }, - { 0x0015d0, 1, 0x04, 0x00000000 }, - { 0x00153c, 1, 0x04, 0x00000000 }, - { 0x0016b4, 1, 0x04, 0x00000003 }, - { 0x000fbc, 4, 0x04, 0x0000ffff }, - { 0x000df8, 2, 0x04, 0x00000000 }, - { 0x001948, 1, 0x04, 0x00000000 }, - { 0x001970, 1, 0x04, 0x00000001 }, - { 0x00161c, 1, 0x04, 0x000009f0 }, - { 0x000dcc, 1, 0x04, 0x00000010 }, - { 0x00163c, 1, 0x04, 0x00000000 }, - { 0x0015e4, 1, 0x04, 0x00000000 }, - { 0x001160, 32, 0x04, 0x25e00040 }, - { 0x001880, 32, 0x04, 0x00000000 }, - { 0x000f84, 2, 0x04, 0x00000000 }, - { 0x0017c8, 2, 0x04, 0x00000000 }, - { 0x0017d0, 1, 0x04, 0x000000ff }, - { 0x0017d4, 1, 0x04, 0xffffffff }, - { 0x0017d8, 1, 0x04, 0x00000002 }, - { 0x0017dc, 1, 0x04, 0x00000000 }, - { 0x0015f4, 2, 0x04, 0x00000000 }, - { 0x001434, 2, 0x04, 0x00000000 }, - { 0x000d74, 1, 0x04, 0x00000000 }, - { 0x000dec, 1, 0x04, 0x00000001 }, - { 0x0013a4, 1, 0x04, 0x00000000 }, - { 0x001318, 1, 0x04, 0x00000001 }, - { 0x001644, 1, 0x04, 0x00000000 }, - { 0x000748, 1, 0x04, 0x00000000 }, - { 0x000de8, 1, 0x04, 0x00000000 }, - { 0x001648, 1, 0x04, 0x00000000 }, - { 0x0012a4, 1, 0x04, 0x00000000 }, - { 0x001120, 4, 0x04, 0x00000000 }, - { 0x001118, 1, 0x04, 0x00000000 }, - { 0x00164c, 1, 0x04, 0x00000000 }, - { 0x001658, 1, 0x04, 0x00000000 }, - { 0x001910, 1, 0x04, 0x00000290 }, - { 0x001518, 1, 0x04, 0x00000000 }, - { 0x00165c, 1, 0x04, 0x00000001 }, - { 0x001520, 1, 0x04, 0x00000000 }, - { 0x001604, 1, 0x04, 0x00000000 }, - { 0x001570, 1, 0x04, 0x00000000 }, - { 0x0013b0, 2, 0x04, 0x3f800000 }, - { 0x00020c, 1, 0x04, 0x00000000 }, - { 0x001670, 1, 0x04, 0x30201000 }, - { 0x001674, 1, 0x04, 0x70605040 }, - { 0x001678, 1, 0x04, 0xb8a89888 }, - { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, - { 0x00166c, 1, 0x04, 0x00000000 }, - { 0x001680, 1, 0x04, 0x00ffff00 }, - { 0x0012d0, 1, 0x04, 0x00000003 }, - { 0x0012d4, 1, 0x04, 0x00000002 }, - { 0x001684, 2, 0x04, 0x00000000 }, - { 0x000dac, 2, 0x04, 0x00001b02 }, - { 0x000db4, 1, 0x04, 0x00000000 }, - { 0x00168c, 1, 0x04, 0x00000000 }, - { 0x0015bc, 1, 0x04, 0x00000000 }, - { 0x00156c, 1, 0x04, 0x00000000 }, - { 0x00187c, 1, 0x04, 0x00000000 }, - { 0x001110, 1, 0x04, 0x00000001 }, - { 0x000dc0, 3, 0x04, 0x00000000 }, - { 0x001234, 1, 0x04, 0x00000000 }, - { 0x001690, 1, 0x04, 0x00000000 }, - { 0x0012ac, 1, 0x04, 0x00000001 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x001000, 1, 0x04, 0x00000010 }, - { 0x0010fc, 1, 0x04, 0x00000000 }, - { 0x001290, 1, 0x04, 0x00000000 }, - { 0x000218, 1, 0x04, 0x00000010 }, - { 0x0012d8, 1, 0x04, 0x00000000 }, - { 0x0012dc, 1, 0x04, 0x00000010 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x00155c, 2, 0x04, 0x00000000 }, - { 0x001564, 1, 0x04, 0x00000fff }, - { 0x001574, 2, 0x04, 0x00000000 }, - { 0x00157c, 1, 0x04, 0x000fffff }, - { 0x001354, 1, 0x04, 0x00000000 }, - { 0x001610, 1, 0x04, 0x00000012 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x00260c, 1, 0x04, 0x00000000 }, - { 0x0007ac, 1, 0x04, 0x00000000 }, - { 0x00162c, 1, 0x04, 0x00000003 }, - { 0x000210, 1, 0x04, 0x00000000 }, - { 0x000320, 1, 0x04, 0x00000000 }, - { 0x000324, 6, 0x04, 0x3f800000 }, - { 0x000750, 1, 0x04, 0x00000000 }, - { 0x000760, 1, 0x04, 0x39291909 }, - { 0x000764, 1, 0x04, 0x79695949 }, - { 0x000768, 1, 0x04, 0xb9a99989 }, - { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, - { 0x000770, 1, 0x04, 0x30201000 }, - { 0x000774, 1, 0x04, 0x70605040 }, - { 0x000778, 1, 0x04, 0x00009080 }, - { 0x000780, 1, 0x04, 0x39291909 }, - { 0x000784, 1, 0x04, 0x79695949 }, - { 0x000788, 1, 0x04, 0xb9a99989 }, - { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, - { 0x0007d0, 1, 0x04, 0x30201000 }, - { 0x0007d4, 1, 0x04, 0x70605040 }, - { 0x0007d8, 1, 0x04, 0x00009080 }, - { 0x00037c, 1, 0x04, 0x00000001 }, - { 0x000740, 2, 0x04, 0x00000000 }, - { 0x002600, 1, 0x04, 0x00000000 }, - { 0x001918, 1, 0x04, 0x00000000 }, - { 0x00191c, 1, 0x04, 0x00000900 }, - { 0x001920, 1, 0x04, 0x00000405 }, - { 0x001308, 1, 0x04, 0x00000001 }, - { 0x001924, 1, 0x04, 0x00000000 }, - { 0x0013ac, 1, 0x04, 0x00000000 }, - { 0x00192c, 1, 0x04, 0x00000001 }, - { 0x00193c, 1, 0x04, 0x00002c1c }, - { 0x000d7c, 1, 0x04, 0x00000000 }, - { 0x000f8c, 1, 0x04, 0x00000000 }, - { 0x0002c0, 1, 0x04, 0x00000001 }, - { 0x001510, 1, 0x04, 0x00000000 }, - { 0x001940, 1, 0x04, 0x00000000 }, - { 0x000ff4, 2, 0x04, 0x00000000 }, - { 0x00194c, 2, 0x04, 0x00000000 }, - { 0x001968, 1, 0x04, 0x00000000 }, - { 0x001590, 1, 0x04, 0x0000003f }, - { 0x0007e8, 4, 0x04, 0x00000000 }, - { 0x00196c, 1, 0x04, 0x00000011 }, - { 0x0002e4, 1, 0x04, 0x0000b001 }, - { 0x00036c, 2, 0x04, 0x00000000 }, - { 0x00197c, 1, 0x04, 0x00000000 }, - { 0x000fcc, 2, 0x04, 0x00000000 }, - { 0x0002d8, 1, 0x04, 0x00000040 }, - { 0x001980, 1, 0x04, 0x00000080 }, - { 0x001504, 1, 0x04, 0x00000080 }, - { 0x001984, 1, 0x04, 0x00000000 }, - { 0x000300, 1, 0x04, 0x00000001 }, - { 0x0013a8, 1, 0x04, 0x00000000 }, - { 0x0012ec, 1, 0x04, 0x00000000 }, - { 0x001310, 1, 0x04, 0x00000000 }, - { 0x001314, 1, 0x04, 0x00000001 }, - { 0x001380, 1, 0x04, 0x00000000 }, - { 0x001384, 4, 0x04, 0x00000001 }, - { 0x001394, 1, 0x04, 0x00000000 }, - { 0x00139c, 1, 0x04, 0x00000000 }, - { 0x001398, 1, 0x04, 0x00000000 }, - { 0x001594, 1, 0x04, 0x00000000 }, - { 0x001598, 4, 0x04, 0x00000001 }, - { 0x000f54, 3, 0x04, 0x00000000 }, - { 0x0019bc, 1, 0x04, 0x00000000 }, - { 0x000f9c, 2, 0x04, 0x00000000 }, - { 0x0012cc, 1, 0x04, 0x00000000 }, - { 0x0012e8, 1, 0x04, 0x00000000 }, - { 0x00130c, 1, 0x04, 0x00000001 }, - { 0x001360, 8, 0x04, 0x00000000 }, - { 0x00133c, 2, 0x04, 0x00000001 }, - { 0x001344, 1, 0x04, 0x00000002 }, - { 0x001348, 2, 0x04, 0x00000001 }, - { 0x001350, 1, 0x04, 0x00000002 }, - { 0x001358, 1, 0x04, 0x00000001 }, - { 0x0012e4, 1, 0x04, 0x00000000 }, - { 0x00131c, 4, 0x04, 0x00000000 }, - { 0x0019c0, 1, 0x04, 0x00000000 }, - { 0x001140, 1, 0x04, 0x00000000 }, - { 0x0019c4, 1, 0x04, 0x00000000 }, - { 0x0019c8, 1, 0x04, 0x00001500 }, - { 0x00135c, 1, 0x04, 0x00000000 }, - { 0x000f90, 1, 0x04, 0x00000000 }, - { 0x0019e0, 8, 0x04, 0x00000001 }, - { 0x0019cc, 1, 0x04, 0x00000001 }, - { 0x0015b8, 1, 0x04, 0x00000000 }, - { 0x001a00, 1, 0x04, 0x00001111 }, - { 0x001a04, 7, 0x04, 0x00000000 }, - { 0x000d6c, 2, 0x04, 0xffff0000 }, - { 0x0010f8, 1, 0x04, 0x00001010 }, - { 0x000d80, 5, 0x04, 0x00000000 }, - { 0x000da0, 1, 0x04, 0x00000000 }, - { 0x0007a4, 2, 0x04, 0x00000000 }, - { 0x001508, 1, 0x04, 0x80000000 }, - { 0x00150c, 1, 0x04, 0x40000000 }, - { 0x001668, 1, 0x04, 0x00000000 }, - { 0x000318, 2, 0x04, 0x00000008 }, - { 0x000d9c, 1, 0x04, 0x00000001 }, - { 0x000374, 1, 0x04, 0x00000000 }, - { 0x000378, 1, 0x04, 0x00000020 }, - { 0x0007dc, 1, 0x04, 0x00000000 }, - { 0x00074c, 1, 0x04, 0x00000055 }, - { 0x001420, 1, 0x04, 0x00000003 }, - { 0x0017bc, 2, 0x04, 0x00000000 }, - { 0x0017c4, 1, 0x04, 0x00000001 }, - { 0x001008, 1, 0x04, 0x00000008 }, - { 0x00100c, 1, 0x04, 0x00000040 }, - { 0x001010, 1, 0x04, 0x0000012c }, - { 0x000d60, 1, 0x04, 0x00000040 }, - { 0x00075c, 1, 0x04, 0x00000003 }, - { 0x001018, 1, 0x04, 0x00000020 }, - { 0x00101c, 1, 0x04, 0x00000001 }, - { 0x001020, 1, 0x04, 0x00000020 }, - { 0x001024, 1, 0x04, 0x00000001 }, - { 0x001444, 3, 0x04, 0x00000000 }, - { 0x000360, 1, 0x04, 0x20164010 }, - { 0x000364, 1, 0x04, 0x00000020 }, - { 0x000368, 1, 0x04, 0x00000000 }, - { 0x000de4, 1, 0x04, 0x00000000 }, - { 0x000204, 1, 0x04, 0x00000006 }, - { 0x000208, 1, 0x04, 0x00000000 }, - { 0x0002cc, 2, 0x04, 0x003fffff }, - { 0x001220, 1, 0x04, 0x00000005 }, - { 0x000fdc, 1, 0x04, 0x00000000 }, - { 0x000f98, 1, 0x04, 0x00400008 }, - { 0x001284, 1, 0x04, 0x08000080 }, - { 0x001450, 1, 0x04, 0x00400008 }, - { 0x001454, 1, 0x04, 0x08000080 }, - { 0x000214, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nve4_grctx_pack_mthd[] = { - { nve4_grctx_init_a097_0, 0xa097 }, - { nvc0_grctx_init_902d_0, 0x902d }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_fe_0[] = { - { 0x404010, 5, 0x04, 0x00000000 }, - { 0x404024, 1, 0x04, 0x0000e000 }, - { 0x404028, 1, 0x04, 0x00000000 }, - { 0x4040a8, 8, 0x04, 0x00000000 }, - { 0x4040c8, 1, 0x04, 0xf800008f }, - { 0x4040d0, 6, 0x04, 0x00000000 }, - { 0x4040e8, 1, 0x04, 0x00001000 }, - { 0x4040f8, 1, 0x04, 0x00000000 }, - { 0x404130, 2, 0x04, 0x00000000 }, - { 0x404138, 1, 0x04, 0x20000040 }, - { 0x404150, 1, 0x04, 0x0000002e }, - { 0x404154, 1, 0x04, 0x00000400 }, - { 0x404158, 1, 0x04, 0x00000200 }, - { 0x404164, 1, 0x04, 0x00000055 }, - { 0x4041a0, 4, 0x04, 0x00000000 }, - { 0x404200, 4, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nve4_grctx_init_memfmt_0[] = { - { 0x404604, 1, 0x04, 0x00000014 }, - { 0x404608, 1, 0x04, 0x00000000 }, - { 0x40460c, 1, 0x04, 0x00003fff }, - { 0x404610, 1, 0x04, 0x00000100 }, - { 0x404618, 4, 0x04, 0x00000000 }, - { 0x40462c, 2, 0x04, 0x00000000 }, - { 0x404640, 1, 0x04, 0x00000000 }, - { 0x404654, 1, 0x04, 0x00000000 }, - { 0x404660, 1, 0x04, 0x00000000 }, - { 0x404678, 1, 0x04, 0x00000000 }, - { 0x40467c, 1, 0x04, 0x00000002 }, - { 0x404680, 8, 0x04, 0x00000000 }, - { 0x4046a0, 1, 0x04, 0x007f0080 }, - { 0x4046a4, 8, 0x04, 0x00000000 }, - { 0x4046c8, 3, 0x04, 0x00000000 }, - { 0x404700, 3, 0x04, 0x00000000 }, - { 0x404718, 7, 0x04, 0x00000000 }, - { 0x404734, 1, 0x04, 0x00000100 }, - { 0x404738, 2, 0x04, 0x00000000 }, - { 0x404744, 2, 0x04, 0x00000000 }, - { 0x404754, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nve4_grctx_init_ds_0[] = { - { 0x405800, 1, 0x04, 0x0f8000bf }, - { 0x405830, 1, 0x04, 0x02180648 }, - { 0x405834, 1, 0x04, 0x08000000 }, - { 0x405838, 1, 0x04, 0x00000000 }, - { 0x405854, 1, 0x04, 0x00000000 }, - { 0x405870, 4, 0x04, 0x00000001 }, - { 0x405a00, 2, 0x04, 0x00000000 }, - { 0x405a18, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_cwd_0[] = { - { 0x405b00, 1, 0x04, 0x00000000 }, - { 0x405b10, 1, 0x04, 0x00001000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x004103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b4, 2, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x801a00f0 }, - { 0x4064c4, 1, 0x04, 0x0192ffff }, - { 0x4064c8, 1, 0x04, 0x01800600 }, - { 0x4064cc, 9, 0x04, 0x00000000 }, - { 0x4064fc, 1, 0x04, 0x0000022a }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_sked_0[] = { - { 0x407040, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nve4_grctx_init_scc_0[] = { - { 0x408000, 2, 0x04, 0x00000000 }, - { 0x408008, 1, 0x04, 0x00000030 }, - { 0x40800c, 2, 0x04, 0x00000000 }, - { 0x408014, 1, 0x04, 0x00000069 }, - { 0x408018, 1, 0x04, 0xe100e100 }, - { 0x408064, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x02802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x1043e005 }, - { 0x408840, 1, 0x04, 0x0000000b }, - { 0x408900, 1, 0x04, 0x3080b801 }, - { 0x408904, 1, 0x04, 0x62000001 }, - { 0x408908, 1, 0x04, 0x00c8102f }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -const struct nvc0_graph_pack -nve4_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nve4_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { nve4_grctx_init_ds_0 }, - { nve4_grctx_init_cwd_0 }, - { nve4_grctx_init_pd_0 }, - { nve4_grctx_init_sked_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { nve4_grctx_init_be_0 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x7006860a }, - { 0x418808, 3, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00000044 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100018 }, - {} -}; - -const struct nvc0_graph_init -nve4_grctx_init_gpm_0[] = { - { 0x418c08, 1, 0x04, 0x00000001 }, - { 0x418c10, 8, 0x04, 0x00000000 }, - { 0x418c40, 1, 0x04, 0xffffffff }, - { 0x418c6c, 1, 0x04, 0x00000001 }, - { 0x418c80, 1, 0x04, 0x20200004 }, - { 0x418c8c, 1, 0x04, 0x00000001 }, - {} -}; - -const struct nvc0_graph_pack -nve4_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nve4_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nve4_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000000f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000021 }, - { 0x419a0c, 1, 0x04, 0x00020000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - { 0x419a1c, 1, 0x04, 0x0000c000 }, - { 0x419a20, 1, 0x04, 0x00000800 }, - { 0x419a30, 1, 0x04, 0x00000001 }, - { 0x419ac4, 1, 0x04, 0x0037f440 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_mpc_0[] = { - { 0x419c00, 1, 0x04, 0x0000000a }, - { 0x419c04, 1, 0x04, 0x80000006 }, - { 0x419c08, 1, 0x04, 0x00000002 }, - { 0x419c20, 1, 0x04, 0x00000000 }, - { 0x419c24, 1, 0x04, 0x00084210 }, - { 0x419c28, 1, 0x04, 0x3efbefbe }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_l1c_0[] = { - { 0x419ce8, 1, 0x04, 0x00000000 }, - { 0x419cf4, 1, 0x04, 0x00003203 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_sm_0[] = { - { 0x419e04, 3, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00000402 }, - { 0x419e44, 1, 0x04, 0x0013eff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000007f }, - { 0x419e50, 19, 0x04, 0x00000000 }, - { 0x419eac, 1, 0x04, 0x00001f8f }, - { 0x419eb0, 1, 0x04, 0x00000d3f }, - { 0x419ec8, 1, 0x04, 0x0001304f }, - { 0x419f30, 8, 0x04, 0x00000000 }, - { 0x419f58, 1, 0x04, 0x00000000 }, - { 0x419f70, 1, 0x04, 0x00000000 }, - { 0x419f78, 1, 0x04, 0x0000000b }, - { 0x419f7c, 1, 0x04, 0x0000027c }, - {} -}; - -const struct nvc0_graph_pack -nve4_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nve4_grctx_init_tex_0 }, - { nve4_grctx_init_mpc_0 }, - { nve4_grctx_init_l1c_0 }, - { nve4_grctx_init_sm_0 }, - {} -}; - -const struct nvc0_graph_init -nve4_grctx_init_pes_0[] = { - { 0x41be24, 1, 0x04, 0x00000006 }, - {} -}; - -static const struct nvc0_graph_init -nve4_grctx_init_cbm_0[] = { - { 0x41bec0, 1, 0x04, 0x12180000 }, - { 0x41bec4, 1, 0x04, 0x00037f7f }, - { 0x41bee4, 1, 0x04, 0x06480430 }, - {} -}; - -const struct nvc0_graph_pack -nve4_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { nve4_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -void -nve4_grctx_generate_bundle(struct nvc0_grctx *info) -{ - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); - const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, - impl->bundle_size / 0x20); - const u32 token_limit = impl->bundle_token_limit; - const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; - const int s = 8; - const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); - mmio_refn(info, 0x408004, 0x00000000, s, b); - mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); - mmio_refn(info, 0x418808, 0x00000000, s, b); - mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); - mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); -} - -void -nve4_grctx_generate_pagepool(struct nvc0_grctx *info) -{ - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); - const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; - const int s = 8; - const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); - mmio_refn(info, 0x40800c, 0x00000000, s, b); - mmio_wr32(info, 0x408010, 0x80000000); - mmio_refn(info, 0x419004, 0x00000000, s, b); - mmio_wr32(info, 0x419008, 0x00000000); - mmio_wr32(info, 0x4064cc, 0x80000000); -} - -void -nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) -{ - nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); - nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); - nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); - nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); - nv_mask(priv, 0x405800, 0x08000000, 0x08000000); - nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); -} - -void -nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) -{ - u32 data[6] = {}, data2[2] = {}; - u8 tpcnr[GPC_MAX]; - u8 shift, ntpcv; - int gpc, tpc, i; - - /* calculate first set of magics */ - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - - gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpcnr[gpc]--; - - data[tpc / 6] |= gpc << ((tpc % 6) * 5); - } - - for (; tpc < 32; tpc++) - data[tpc / 6] |= 7 << ((tpc % 6) * 5); - - /* and the second... */ - shift = 0; - ntpcv = priv->tpc_total; - while (!(ntpcv & (1 << 4))) { - ntpcv <<= 1; - shift++; - } - - data2[0] = (ntpcv << 16); - data2[0] |= (shift << 21); - data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); - for (i = 1; i < 7; i++) - data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); - - /* GPC_BROADCAST */ - nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x418b08 + (i * 4), data[i]); - - /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) | - priv->magic_not_rop_nr | data2[0]); - nv_wr32(priv, 0x41bfe4, data2[1]); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); - - /* UNK78xx */ - nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x40780c + (i * 4), data[i]); -} - -void -nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) -{ - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - int i; - - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); - - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); - - nv_wr32(priv, 0x404154, 0x00000000); - - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(priv); - - nvc0_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nve4_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); - - for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); - if (priv->gpc_nr == 1) { - nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); - nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); - } else { - nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); - nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); - } - nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); - - nvc0_graph_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); - - nv_mask(priv, 0x418800, 0x00200000, 0x00200000); - nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); -} - -struct nouveau_oclass * -nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xe4), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nve4_grctx_pack_hub, - .gpc = nve4_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nve4_grctx_pack_tpc, - .ppc = nve4_grctx_pack_ppc, - .icmd = nve4_grctx_pack_icmd, - .mthd = nve4_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, - .bundle_size = 0x3000, - .bundle_min_gpm_fifo_depth = 0x180, - .bundle_token_limit = 0x600, - .pagepool = nve4_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x7ff, - .alpha_nr = 0x648, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c deleted file mode 100644 index e9b0dcf95a49..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c +++ /dev/null @@ -1,843 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH context register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvf0_grctx_init_icmd_0[] = { - { 0x001000, 1, 0x01, 0x00000004 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x0000a9, 1, 0x01, 0x0000ffff }, - { 0x000038, 1, 0x01, 0x0fac6881 }, - { 0x00003d, 1, 0x01, 0x00000001 }, - { 0x0000e8, 8, 0x01, 0x00000400 }, - { 0x000078, 8, 0x01, 0x00000300 }, - { 0x000050, 1, 0x01, 0x00000011 }, - { 0x000058, 8, 0x01, 0x00000008 }, - { 0x000208, 8, 0x01, 0x00000001 }, - { 0x000081, 1, 0x01, 0x00000001 }, - { 0x000085, 1, 0x01, 0x00000004 }, - { 0x000088, 1, 0x01, 0x00000400 }, - { 0x000090, 1, 0x01, 0x00000300 }, - { 0x000098, 1, 0x01, 0x00001001 }, - { 0x0000e3, 1, 0x01, 0x00000001 }, - { 0x0000da, 1, 0x01, 0x00000001 }, - { 0x0000f8, 1, 0x01, 0x00000003 }, - { 0x0000fa, 1, 0x01, 0x00000001 }, - { 0x00009f, 4, 0x01, 0x0000ffff }, - { 0x0000b1, 1, 0x01, 0x00000001 }, - { 0x0000ad, 1, 0x01, 0x0000013e }, - { 0x0000e1, 1, 0x01, 0x00000010 }, - { 0x000290, 16, 0x01, 0x00000000 }, - { 0x0003b0, 16, 0x01, 0x00000000 }, - { 0x0002a0, 16, 0x01, 0x00000000 }, - { 0x000420, 16, 0x01, 0x00000000 }, - { 0x0002b0, 16, 0x01, 0x00000000 }, - { 0x000430, 16, 0x01, 0x00000000 }, - { 0x0002c0, 16, 0x01, 0x00000000 }, - { 0x0004d0, 16, 0x01, 0x00000000 }, - { 0x000720, 16, 0x01, 0x00000000 }, - { 0x0008c0, 16, 0x01, 0x00000000 }, - { 0x000890, 16, 0x01, 0x00000000 }, - { 0x0008e0, 16, 0x01, 0x00000000 }, - { 0x0008a0, 16, 0x01, 0x00000000 }, - { 0x0008f0, 16, 0x01, 0x00000000 }, - { 0x00094c, 1, 0x01, 0x000000ff }, - { 0x00094d, 1, 0x01, 0xffffffff }, - { 0x00094e, 1, 0x01, 0x00000002 }, - { 0x0002ec, 1, 0x01, 0x00000001 }, - { 0x0002f2, 2, 0x01, 0x00000001 }, - { 0x0002f5, 1, 0x01, 0x00000001 }, - { 0x0002f7, 1, 0x01, 0x00000001 }, - { 0x000303, 1, 0x01, 0x00000001 }, - { 0x0002e6, 1, 0x01, 0x00000001 }, - { 0x000466, 1, 0x01, 0x00000052 }, - { 0x000301, 1, 0x01, 0x3f800000 }, - { 0x000304, 1, 0x01, 0x30201000 }, - { 0x000305, 1, 0x01, 0x70605040 }, - { 0x000306, 1, 0x01, 0xb8a89888 }, - { 0x000307, 1, 0x01, 0xf8e8d8c8 }, - { 0x00030a, 1, 0x01, 0x00ffff00 }, - { 0x00030b, 1, 0x01, 0x0000001a }, - { 0x00030c, 1, 0x01, 0x00000001 }, - { 0x000318, 1, 0x01, 0x00000001 }, - { 0x000340, 1, 0x01, 0x00000000 }, - { 0x000375, 1, 0x01, 0x00000001 }, - { 0x00037d, 1, 0x01, 0x00000006 }, - { 0x0003a0, 1, 0x01, 0x00000002 }, - { 0x0003aa, 1, 0x01, 0x00000001 }, - { 0x0003a9, 1, 0x01, 0x00000001 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000383, 1, 0x01, 0x00000011 }, - { 0x000360, 1, 0x01, 0x00000040 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x00037a, 1, 0x01, 0x00000012 }, - { 0x000619, 1, 0x01, 0x00000003 }, - { 0x000811, 1, 0x01, 0x00000003 }, - { 0x000812, 1, 0x01, 0x00000004 }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000815, 1, 0x01, 0x0000000b }, - { 0x000800, 6, 0x01, 0x00000001 }, - { 0x000632, 1, 0x01, 0x00000001 }, - { 0x000633, 1, 0x01, 0x00000002 }, - { 0x000634, 1, 0x01, 0x00000003 }, - { 0x000635, 1, 0x01, 0x00000004 }, - { 0x000654, 1, 0x01, 0x3f800000 }, - { 0x000657, 1, 0x01, 0x3f800000 }, - { 0x000655, 2, 0x01, 0x3f800000 }, - { 0x0006cd, 1, 0x01, 0x3f800000 }, - { 0x0007f5, 1, 0x01, 0x3f800000 }, - { 0x0007dc, 1, 0x01, 0x39291909 }, - { 0x0007dd, 1, 0x01, 0x79695949 }, - { 0x0007de, 1, 0x01, 0xb9a99989 }, - { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007e8, 1, 0x01, 0x00003210 }, - { 0x0007e9, 1, 0x01, 0x00007654 }, - { 0x0007ea, 1, 0x01, 0x00000098 }, - { 0x0007ec, 1, 0x01, 0x39291909 }, - { 0x0007ed, 1, 0x01, 0x79695949 }, - { 0x0007ee, 1, 0x01, 0xb9a99989 }, - { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, - { 0x0007f0, 1, 0x01, 0x00003210 }, - { 0x0007f1, 1, 0x01, 0x00007654 }, - { 0x0007f2, 1, 0x01, 0x00000098 }, - { 0x0005a5, 1, 0x01, 0x00000001 }, - { 0x000980, 128, 0x01, 0x00000000 }, - { 0x000468, 1, 0x01, 0x00000004 }, - { 0x00046c, 1, 0x01, 0x00000001 }, - { 0x000470, 96, 0x01, 0x00000000 }, - { 0x000510, 16, 0x01, 0x3f800000 }, - { 0x000520, 1, 0x01, 0x000002b6 }, - { 0x000529, 1, 0x01, 0x00000001 }, - { 0x000530, 16, 0x01, 0xffff0000 }, - { 0x000585, 1, 0x01, 0x0000003f }, - { 0x000576, 1, 0x01, 0x00000003 }, - { 0x00057b, 1, 0x01, 0x00000059 }, - { 0x000586, 1, 0x01, 0x00000040 }, - { 0x000582, 2, 0x01, 0x00000080 }, - { 0x0005c2, 1, 0x01, 0x00000001 }, - { 0x000638, 2, 0x01, 0x00000001 }, - { 0x00063a, 1, 0x01, 0x00000002 }, - { 0x00063b, 2, 0x01, 0x00000001 }, - { 0x00063d, 1, 0x01, 0x00000002 }, - { 0x00063e, 1, 0x01, 0x00000001 }, - { 0x0008b8, 8, 0x01, 0x00000001 }, - { 0x000900, 8, 0x01, 0x00000001 }, - { 0x000908, 8, 0x01, 0x00000002 }, - { 0x000910, 16, 0x01, 0x00000001 }, - { 0x000920, 8, 0x01, 0x00000002 }, - { 0x000928, 8, 0x01, 0x00000001 }, - { 0x000662, 1, 0x01, 0x00000001 }, - { 0x000648, 9, 0x01, 0x00000001 }, - { 0x000658, 1, 0x01, 0x0000000f }, - { 0x0007ff, 1, 0x01, 0x0000000a }, - { 0x00066a, 1, 0x01, 0x40000000 }, - { 0x00066b, 1, 0x01, 0x10000000 }, - { 0x00066c, 2, 0x01, 0xffff0000 }, - { 0x0007af, 2, 0x01, 0x00000008 }, - { 0x0007f6, 1, 0x01, 0x00000001 }, - { 0x00080b, 1, 0x01, 0x00000002 }, - { 0x0006b2, 1, 0x01, 0x00000055 }, - { 0x0007ad, 1, 0x01, 0x00000003 }, - { 0x000937, 1, 0x01, 0x00000001 }, - { 0x000971, 1, 0x01, 0x00000008 }, - { 0x000972, 1, 0x01, 0x00000040 }, - { 0x000973, 1, 0x01, 0x0000012c }, - { 0x00097c, 1, 0x01, 0x00000040 }, - { 0x000979, 1, 0x01, 0x00000003 }, - { 0x000975, 1, 0x01, 0x00000020 }, - { 0x000976, 1, 0x01, 0x00000001 }, - { 0x000977, 1, 0x01, 0x00000020 }, - { 0x000978, 1, 0x01, 0x00000001 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x00095e, 1, 0x01, 0x20164010 }, - { 0x00095f, 1, 0x01, 0x00000020 }, - { 0x000a0d, 1, 0x01, 0x00000006 }, - { 0x00097d, 1, 0x01, 0x00000020 }, - { 0x000683, 1, 0x01, 0x00000006 }, - { 0x000685, 1, 0x01, 0x003fffff }, - { 0x000687, 1, 0x01, 0x003fffff }, - { 0x0006a0, 1, 0x01, 0x00000005 }, - { 0x000840, 1, 0x01, 0x00400008 }, - { 0x000841, 1, 0x01, 0x08000080 }, - { 0x000842, 1, 0x01, 0x00400008 }, - { 0x000843, 1, 0x01, 0x08000080 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ab, 1, 0x01, 0x00000002 }, - { 0x0006ac, 1, 0x01, 0x00000080 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x0006bb, 1, 0x01, 0x000000cf }, - { 0x0006ce, 1, 0x01, 0x2a712488 }, - { 0x000739, 1, 0x01, 0x4085c000 }, - { 0x00073a, 1, 0x01, 0x00000080 }, - { 0x000786, 1, 0x01, 0x80000100 }, - { 0x00073c, 1, 0x01, 0x00010100 }, - { 0x00073d, 1, 0x01, 0x02800000 }, - { 0x000787, 1, 0x01, 0x000000cf }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x000836, 1, 0x01, 0x00000001 }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c1b0, 8, 0x01, 0x0000000f }, - { 0x00c1b8, 1, 0x01, 0x0fac6881 }, - { 0x00c1b9, 1, 0x01, 0x00fac688 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x00c500, 1, 0x01, 0x00000003 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000002 }, - { 0x0006aa, 1, 0x01, 0x00000001 }, - { 0x0006ad, 2, 0x01, 0x00000100 }, - { 0x0006b1, 1, 0x01, 0x00000011 }, - { 0x00078c, 1, 0x01, 0x00000008 }, - { 0x000792, 1, 0x01, 0x00000001 }, - { 0x000794, 3, 0x01, 0x00000001 }, - { 0x000797, 1, 0x01, 0x000000cf }, - { 0x00079a, 1, 0x01, 0x00000002 }, - { 0x000833, 1, 0x01, 0x04444480 }, - { 0x0007a1, 1, 0x01, 0x00000001 }, - { 0x0007a3, 3, 0x01, 0x00000001 }, - { 0x000831, 1, 0x01, 0x00000004 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000008 }, - { 0x000039, 3, 0x01, 0x00000000 }, - { 0x000380, 1, 0x01, 0x00000001 }, - { 0x000366, 2, 0x01, 0x00000000 }, - { 0x000368, 1, 0x01, 0x00000fff }, - { 0x000370, 2, 0x01, 0x00000000 }, - { 0x000372, 1, 0x01, 0x000fffff }, - { 0x000813, 1, 0x01, 0x00000006 }, - { 0x000814, 1, 0x01, 0x00000008 }, - { 0x000957, 1, 0x01, 0x00000003 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x000a04, 1, 0x01, 0x000000ff }, - { 0x000a0b, 1, 0x01, 0x00000040 }, - { 0x00097f, 1, 0x01, 0x00000100 }, - { 0x000a02, 1, 0x01, 0x00000001 }, - { 0x000809, 1, 0x01, 0x00000007 }, - { 0x00c221, 1, 0x01, 0x00000040 }, - { 0x00c401, 1, 0x01, 0x00000001 }, - { 0x00c402, 1, 0x01, 0x00010001 }, - { 0x00c403, 2, 0x01, 0x00000001 }, - { 0x00c40e, 1, 0x01, 0x00000020 }, - { 0x00c500, 1, 0x01, 0x00000003 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - { 0x001000, 1, 0x01, 0x00000001 }, - { 0x000b07, 1, 0x01, 0x00000002 }, - { 0x000b08, 2, 0x01, 0x00000100 }, - { 0x000b0a, 1, 0x01, 0x00000001 }, - { 0x01e100, 1, 0x01, 0x00000001 }, - {} -}; - -const struct nvc0_graph_pack -nvf0_grctx_pack_icmd[] = { - { nvf0_grctx_init_icmd_0 }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_a197_0[] = { - { 0x000800, 8, 0x40, 0x00000000 }, - { 0x000804, 8, 0x40, 0x00000000 }, - { 0x000808, 8, 0x40, 0x00000400 }, - { 0x00080c, 8, 0x40, 0x00000300 }, - { 0x000810, 1, 0x04, 0x000000cf }, - { 0x000850, 7, 0x40, 0x00000000 }, - { 0x000814, 8, 0x40, 0x00000040 }, - { 0x000818, 8, 0x40, 0x00000001 }, - { 0x00081c, 8, 0x40, 0x00000000 }, - { 0x000820, 8, 0x40, 0x00000000 }, - { 0x001c00, 16, 0x10, 0x00000000 }, - { 0x001c04, 16, 0x10, 0x00000000 }, - { 0x001c08, 16, 0x10, 0x00000000 }, - { 0x001c0c, 16, 0x10, 0x00000000 }, - { 0x001d00, 16, 0x10, 0x00000000 }, - { 0x001d04, 16, 0x10, 0x00000000 }, - { 0x001d08, 16, 0x10, 0x00000000 }, - { 0x001d0c, 16, 0x10, 0x00000000 }, - { 0x001f00, 16, 0x08, 0x00000000 }, - { 0x001f04, 16, 0x08, 0x00000000 }, - { 0x001f80, 16, 0x08, 0x00000000 }, - { 0x001f84, 16, 0x08, 0x00000000 }, - { 0x002000, 1, 0x04, 0x00000000 }, - { 0x002040, 1, 0x04, 0x00000011 }, - { 0x002080, 1, 0x04, 0x00000020 }, - { 0x0020c0, 1, 0x04, 0x00000030 }, - { 0x002100, 1, 0x04, 0x00000040 }, - { 0x002140, 1, 0x04, 0x00000051 }, - { 0x00200c, 6, 0x40, 0x00000001 }, - { 0x002010, 1, 0x04, 0x00000000 }, - { 0x002050, 1, 0x04, 0x00000000 }, - { 0x002090, 1, 0x04, 0x00000001 }, - { 0x0020d0, 1, 0x04, 0x00000002 }, - { 0x002110, 1, 0x04, 0x00000003 }, - { 0x002150, 1, 0x04, 0x00000004 }, - { 0x000380, 4, 0x20, 0x00000000 }, - { 0x000384, 4, 0x20, 0x00000000 }, - { 0x000388, 4, 0x20, 0x00000000 }, - { 0x00038c, 4, 0x20, 0x00000000 }, - { 0x000700, 4, 0x10, 0x00000000 }, - { 0x000704, 4, 0x10, 0x00000000 }, - { 0x000708, 4, 0x10, 0x00000000 }, - { 0x002800, 128, 0x04, 0x00000000 }, - { 0x000a00, 16, 0x20, 0x00000000 }, - { 0x000a04, 16, 0x20, 0x00000000 }, - { 0x000a08, 16, 0x20, 0x00000000 }, - { 0x000a0c, 16, 0x20, 0x00000000 }, - { 0x000a10, 16, 0x20, 0x00000000 }, - { 0x000a14, 16, 0x20, 0x00000000 }, - { 0x000c00, 16, 0x10, 0x00000000 }, - { 0x000c04, 16, 0x10, 0x00000000 }, - { 0x000c08, 16, 0x10, 0x00000000 }, - { 0x000c0c, 16, 0x10, 0x3f800000 }, - { 0x000d00, 8, 0x08, 0xffff0000 }, - { 0x000d04, 8, 0x08, 0xffff0000 }, - { 0x000e00, 16, 0x10, 0x00000000 }, - { 0x000e04, 16, 0x10, 0xffff0000 }, - { 0x000e08, 16, 0x10, 0xffff0000 }, - { 0x000d40, 4, 0x08, 0x00000000 }, - { 0x000d44, 4, 0x08, 0x00000000 }, - { 0x001e00, 8, 0x20, 0x00000001 }, - { 0x001e04, 8, 0x20, 0x00000001 }, - { 0x001e08, 8, 0x20, 0x00000002 }, - { 0x001e0c, 8, 0x20, 0x00000001 }, - { 0x001e10, 8, 0x20, 0x00000001 }, - { 0x001e14, 8, 0x20, 0x00000002 }, - { 0x001e18, 8, 0x20, 0x00000001 }, - { 0x003400, 128, 0x04, 0x00000000 }, - { 0x00030c, 1, 0x04, 0x00000001 }, - { 0x001944, 1, 0x04, 0x00000000 }, - { 0x001514, 1, 0x04, 0x00000000 }, - { 0x000d68, 1, 0x04, 0x0000ffff }, - { 0x00121c, 1, 0x04, 0x0fac6881 }, - { 0x000fac, 1, 0x04, 0x00000001 }, - { 0x001538, 1, 0x04, 0x00000001 }, - { 0x000fe0, 2, 0x04, 0x00000000 }, - { 0x000fe8, 1, 0x04, 0x00000014 }, - { 0x000fec, 1, 0x04, 0x00000040 }, - { 0x000ff0, 1, 0x04, 0x00000000 }, - { 0x00179c, 1, 0x04, 0x00000000 }, - { 0x001228, 1, 0x04, 0x00000400 }, - { 0x00122c, 1, 0x04, 0x00000300 }, - { 0x001230, 1, 0x04, 0x00010001 }, - { 0x0007f8, 1, 0x04, 0x00000000 }, - { 0x0015b4, 1, 0x04, 0x00000001 }, - { 0x0015cc, 1, 0x04, 0x00000000 }, - { 0x001534, 1, 0x04, 0x00000000 }, - { 0x000fb0, 1, 0x04, 0x00000000 }, - { 0x0015d0, 1, 0x04, 0x00000000 }, - { 0x00153c, 1, 0x04, 0x00000000 }, - { 0x0016b4, 1, 0x04, 0x00000003 }, - { 0x000fbc, 4, 0x04, 0x0000ffff }, - { 0x000df8, 2, 0x04, 0x00000000 }, - { 0x001948, 1, 0x04, 0x00000000 }, - { 0x001970, 1, 0x04, 0x00000001 }, - { 0x00161c, 1, 0x04, 0x000009f0 }, - { 0x000dcc, 1, 0x04, 0x00000010 }, - { 0x00163c, 1, 0x04, 0x00000000 }, - { 0x0015e4, 1, 0x04, 0x00000000 }, - { 0x001160, 32, 0x04, 0x25e00040 }, - { 0x001880, 32, 0x04, 0x00000000 }, - { 0x000f84, 2, 0x04, 0x00000000 }, - { 0x0017c8, 2, 0x04, 0x00000000 }, - { 0x0017d0, 1, 0x04, 0x000000ff }, - { 0x0017d4, 1, 0x04, 0xffffffff }, - { 0x0017d8, 1, 0x04, 0x00000002 }, - { 0x0017dc, 1, 0x04, 0x00000000 }, - { 0x0015f4, 2, 0x04, 0x00000000 }, - { 0x001434, 2, 0x04, 0x00000000 }, - { 0x000d74, 1, 0x04, 0x00000000 }, - { 0x000dec, 1, 0x04, 0x00000001 }, - { 0x0013a4, 1, 0x04, 0x00000000 }, - { 0x001318, 1, 0x04, 0x00000001 }, - { 0x001644, 1, 0x04, 0x00000000 }, - { 0x000748, 1, 0x04, 0x00000000 }, - { 0x000de8, 1, 0x04, 0x00000000 }, - { 0x001648, 1, 0x04, 0x00000000 }, - { 0x0012a4, 1, 0x04, 0x00000000 }, - { 0x001120, 4, 0x04, 0x00000000 }, - { 0x001118, 1, 0x04, 0x00000000 }, - { 0x00164c, 1, 0x04, 0x00000000 }, - { 0x001658, 1, 0x04, 0x00000000 }, - { 0x001910, 1, 0x04, 0x00000290 }, - { 0x001518, 1, 0x04, 0x00000000 }, - { 0x00165c, 1, 0x04, 0x00000001 }, - { 0x001520, 1, 0x04, 0x00000000 }, - { 0x001604, 1, 0x04, 0x00000000 }, - { 0x001570, 1, 0x04, 0x00000000 }, - { 0x0013b0, 2, 0x04, 0x3f800000 }, - { 0x00020c, 1, 0x04, 0x00000000 }, - { 0x001670, 1, 0x04, 0x30201000 }, - { 0x001674, 1, 0x04, 0x70605040 }, - { 0x001678, 1, 0x04, 0xb8a89888 }, - { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, - { 0x00166c, 1, 0x04, 0x00000000 }, - { 0x001680, 1, 0x04, 0x00ffff00 }, - { 0x0012d0, 1, 0x04, 0x00000003 }, - { 0x0012d4, 1, 0x04, 0x00000002 }, - { 0x001684, 2, 0x04, 0x00000000 }, - { 0x000dac, 2, 0x04, 0x00001b02 }, - { 0x000db4, 1, 0x04, 0x00000000 }, - { 0x00168c, 1, 0x04, 0x00000000 }, - { 0x0015bc, 1, 0x04, 0x00000000 }, - { 0x00156c, 1, 0x04, 0x00000000 }, - { 0x00187c, 1, 0x04, 0x00000000 }, - { 0x001110, 1, 0x04, 0x00000001 }, - { 0x000dc0, 3, 0x04, 0x00000000 }, - { 0x001234, 1, 0x04, 0x00000000 }, - { 0x001690, 1, 0x04, 0x00000000 }, - { 0x0012ac, 1, 0x04, 0x00000001 }, - { 0x0002c4, 1, 0x04, 0x00000000 }, - { 0x000790, 5, 0x04, 0x00000000 }, - { 0x00077c, 1, 0x04, 0x00000000 }, - { 0x001000, 1, 0x04, 0x00000010 }, - { 0x0010fc, 1, 0x04, 0x00000000 }, - { 0x001290, 1, 0x04, 0x00000000 }, - { 0x000218, 1, 0x04, 0x00000010 }, - { 0x0012d8, 1, 0x04, 0x00000000 }, - { 0x0012dc, 1, 0x04, 0x00000010 }, - { 0x000d94, 1, 0x04, 0x00000001 }, - { 0x00155c, 2, 0x04, 0x00000000 }, - { 0x001564, 1, 0x04, 0x00000fff }, - { 0x001574, 2, 0x04, 0x00000000 }, - { 0x00157c, 1, 0x04, 0x000fffff }, - { 0x001354, 1, 0x04, 0x00000000 }, - { 0x001610, 1, 0x04, 0x00000012 }, - { 0x001608, 2, 0x04, 0x00000000 }, - { 0x00260c, 1, 0x04, 0x00000000 }, - { 0x0007ac, 1, 0x04, 0x00000000 }, - { 0x00162c, 1, 0x04, 0x00000003 }, - { 0x000210, 1, 0x04, 0x00000000 }, - { 0x000320, 1, 0x04, 0x00000000 }, - { 0x000324, 6, 0x04, 0x3f800000 }, - { 0x000750, 1, 0x04, 0x00000000 }, - { 0x000760, 1, 0x04, 0x39291909 }, - { 0x000764, 1, 0x04, 0x79695949 }, - { 0x000768, 1, 0x04, 0xb9a99989 }, - { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, - { 0x000770, 1, 0x04, 0x30201000 }, - { 0x000774, 1, 0x04, 0x70605040 }, - { 0x000778, 1, 0x04, 0x00009080 }, - { 0x000780, 1, 0x04, 0x39291909 }, - { 0x000784, 1, 0x04, 0x79695949 }, - { 0x000788, 1, 0x04, 0xb9a99989 }, - { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, - { 0x0007d0, 1, 0x04, 0x30201000 }, - { 0x0007d4, 1, 0x04, 0x70605040 }, - { 0x0007d8, 1, 0x04, 0x00009080 }, - { 0x00037c, 1, 0x04, 0x00000001 }, - { 0x000740, 2, 0x04, 0x00000000 }, - { 0x002600, 1, 0x04, 0x00000000 }, - { 0x001918, 1, 0x04, 0x00000000 }, - { 0x00191c, 1, 0x04, 0x00000900 }, - { 0x001920, 1, 0x04, 0x00000405 }, - { 0x001308, 1, 0x04, 0x00000001 }, - { 0x001924, 1, 0x04, 0x00000000 }, - { 0x0013ac, 1, 0x04, 0x00000000 }, - { 0x00192c, 1, 0x04, 0x00000001 }, - { 0x00193c, 1, 0x04, 0x00002c1c }, - { 0x000d7c, 1, 0x04, 0x00000000 }, - { 0x000f8c, 1, 0x04, 0x00000000 }, - { 0x0002c0, 1, 0x04, 0x00000001 }, - { 0x001510, 1, 0x04, 0x00000000 }, - { 0x001940, 1, 0x04, 0x00000000 }, - { 0x000ff4, 2, 0x04, 0x00000000 }, - { 0x00194c, 2, 0x04, 0x00000000 }, - { 0x001968, 1, 0x04, 0x00000000 }, - { 0x001590, 1, 0x04, 0x0000003f }, - { 0x0007e8, 4, 0x04, 0x00000000 }, - { 0x00196c, 1, 0x04, 0x00000011 }, - { 0x0002e4, 1, 0x04, 0x0000b001 }, - { 0x00036c, 2, 0x04, 0x00000000 }, - { 0x00197c, 1, 0x04, 0x00000000 }, - { 0x000fcc, 2, 0x04, 0x00000000 }, - { 0x0002d8, 1, 0x04, 0x00000040 }, - { 0x001980, 1, 0x04, 0x00000080 }, - { 0x001504, 1, 0x04, 0x00000080 }, - { 0x001984, 1, 0x04, 0x00000000 }, - { 0x000300, 1, 0x04, 0x00000001 }, - { 0x0013a8, 1, 0x04, 0x00000000 }, - { 0x0012ec, 1, 0x04, 0x00000000 }, - { 0x001310, 1, 0x04, 0x00000000 }, - { 0x001314, 1, 0x04, 0x00000001 }, - { 0x001380, 1, 0x04, 0x00000000 }, - { 0x001384, 4, 0x04, 0x00000001 }, - { 0x001394, 1, 0x04, 0x00000000 }, - { 0x00139c, 1, 0x04, 0x00000000 }, - { 0x001398, 1, 0x04, 0x00000000 }, - { 0x001594, 1, 0x04, 0x00000000 }, - { 0x001598, 4, 0x04, 0x00000001 }, - { 0x000f54, 3, 0x04, 0x00000000 }, - { 0x0019bc, 1, 0x04, 0x00000000 }, - { 0x000f9c, 2, 0x04, 0x00000000 }, - { 0x0012cc, 1, 0x04, 0x00000000 }, - { 0x0012e8, 1, 0x04, 0x00000000 }, - { 0x00130c, 1, 0x04, 0x00000001 }, - { 0x001360, 8, 0x04, 0x00000000 }, - { 0x00133c, 2, 0x04, 0x00000001 }, - { 0x001344, 1, 0x04, 0x00000002 }, - { 0x001348, 2, 0x04, 0x00000001 }, - { 0x001350, 1, 0x04, 0x00000002 }, - { 0x001358, 1, 0x04, 0x00000001 }, - { 0x0012e4, 1, 0x04, 0x00000000 }, - { 0x00131c, 4, 0x04, 0x00000000 }, - { 0x0019c0, 1, 0x04, 0x00000000 }, - { 0x001140, 1, 0x04, 0x00000000 }, - { 0x0019c4, 1, 0x04, 0x00000000 }, - { 0x0019c8, 1, 0x04, 0x00001500 }, - { 0x00135c, 1, 0x04, 0x00000000 }, - { 0x000f90, 1, 0x04, 0x00000000 }, - { 0x0019e0, 8, 0x04, 0x00000001 }, - { 0x0019cc, 1, 0x04, 0x00000001 }, - { 0x0015b8, 1, 0x04, 0x00000000 }, - { 0x001a00, 1, 0x04, 0x00001111 }, - { 0x001a04, 7, 0x04, 0x00000000 }, - { 0x000d6c, 2, 0x04, 0xffff0000 }, - { 0x0010f8, 1, 0x04, 0x00001010 }, - { 0x000d80, 5, 0x04, 0x00000000 }, - { 0x000da0, 1, 0x04, 0x00000000 }, - { 0x0007a4, 2, 0x04, 0x00000000 }, - { 0x001508, 1, 0x04, 0x80000000 }, - { 0x00150c, 1, 0x04, 0x40000000 }, - { 0x001668, 1, 0x04, 0x00000000 }, - { 0x000318, 2, 0x04, 0x00000008 }, - { 0x000d9c, 1, 0x04, 0x00000001 }, - { 0x000ddc, 1, 0x04, 0x00000002 }, - { 0x000374, 1, 0x04, 0x00000000 }, - { 0x000378, 1, 0x04, 0x00000020 }, - { 0x0007dc, 1, 0x04, 0x00000000 }, - { 0x00074c, 1, 0x04, 0x00000055 }, - { 0x001420, 1, 0x04, 0x00000003 }, - { 0x0017bc, 2, 0x04, 0x00000000 }, - { 0x0017c4, 1, 0x04, 0x00000001 }, - { 0x001008, 1, 0x04, 0x00000008 }, - { 0x00100c, 1, 0x04, 0x00000040 }, - { 0x001010, 1, 0x04, 0x0000012c }, - { 0x000d60, 1, 0x04, 0x00000040 }, - { 0x00075c, 1, 0x04, 0x00000003 }, - { 0x001018, 1, 0x04, 0x00000020 }, - { 0x00101c, 1, 0x04, 0x00000001 }, - { 0x001020, 1, 0x04, 0x00000020 }, - { 0x001024, 1, 0x04, 0x00000001 }, - { 0x001444, 3, 0x04, 0x00000000 }, - { 0x000360, 1, 0x04, 0x20164010 }, - { 0x000364, 1, 0x04, 0x00000020 }, - { 0x000368, 1, 0x04, 0x00000000 }, - { 0x000de4, 1, 0x04, 0x00000000 }, - { 0x000204, 1, 0x04, 0x00000006 }, - { 0x000208, 1, 0x04, 0x00000000 }, - { 0x0002cc, 2, 0x04, 0x003fffff }, - { 0x001220, 1, 0x04, 0x00000005 }, - { 0x000fdc, 1, 0x04, 0x00000000 }, - { 0x000f98, 1, 0x04, 0x00400008 }, - { 0x001284, 1, 0x04, 0x08000080 }, - { 0x001450, 1, 0x04, 0x00400008 }, - { 0x001454, 1, 0x04, 0x08000080 }, - { 0x000214, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvf0_grctx_pack_mthd[] = { - { nvf0_grctx_init_a197_0, 0xa197 }, - { nvc0_grctx_init_902d_0, 0x902d }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_fe_0[] = { - { 0x404004, 8, 0x04, 0x00000000 }, - { 0x404024, 1, 0x04, 0x0000e000 }, - { 0x404028, 8, 0x04, 0x00000000 }, - { 0x4040a8, 8, 0x04, 0x00000000 }, - { 0x4040c8, 1, 0x04, 0xf800008f }, - { 0x4040d0, 6, 0x04, 0x00000000 }, - { 0x4040e8, 1, 0x04, 0x00001000 }, - { 0x4040f8, 1, 0x04, 0x00000000 }, - { 0x404100, 10, 0x04, 0x00000000 }, - { 0x404130, 2, 0x04, 0x00000000 }, - { 0x404138, 1, 0x04, 0x20000040 }, - { 0x404150, 1, 0x04, 0x0000002e }, - { 0x404154, 1, 0x04, 0x00000400 }, - { 0x404158, 1, 0x04, 0x00000200 }, - { 0x404164, 1, 0x04, 0x00000055 }, - { 0x40417c, 2, 0x04, 0x00000000 }, - { 0x4041a0, 4, 0x04, 0x00000000 }, - { 0x404200, 1, 0x04, 0x0000a197 }, - { 0x404204, 1, 0x04, 0x0000a1c0 }, - { 0x404208, 1, 0x04, 0x0000a140 }, - { 0x40420c, 1, 0x04, 0x0000902d }, - {} -}; - -const struct nvc0_graph_init -nvf0_grctx_init_pri_0[] = { - { 0x404404, 12, 0x04, 0x00000000 }, - { 0x404438, 1, 0x04, 0x00000000 }, - { 0x404460, 2, 0x04, 0x00000000 }, - { 0x404468, 1, 0x04, 0x00ffffff }, - { 0x40446c, 1, 0x04, 0x00000000 }, - { 0x404480, 1, 0x04, 0x00000001 }, - { 0x404498, 1, 0x04, 0x00000001 }, - {} -}; - -const struct nvc0_graph_init -nvf0_grctx_init_cwd_0[] = { - { 0x405b00, 1, 0x04, 0x00000000 }, - { 0x405b10, 1, 0x04, 0x00001000 }, - { 0x405b20, 1, 0x04, 0x04000000 }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_pd_0[] = { - { 0x406020, 1, 0x04, 0x034103c1 }, - { 0x406028, 4, 0x04, 0x00000001 }, - { 0x4064a8, 1, 0x04, 0x00000000 }, - { 0x4064ac, 1, 0x04, 0x00003fff }, - { 0x4064b0, 3, 0x04, 0x00000000 }, - { 0x4064c0, 1, 0x04, 0x802000f0 }, - { 0x4064c4, 1, 0x04, 0x0192ffff }, - { 0x4064c8, 1, 0x04, 0x018007c0 }, - { 0x4064cc, 9, 0x04, 0x00000000 }, - { 0x4064fc, 1, 0x04, 0x0000022a }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_be_0[] = { - { 0x408800, 1, 0x04, 0x12802a3c }, - { 0x408804, 1, 0x04, 0x00000040 }, - { 0x408808, 1, 0x04, 0x1003e005 }, - { 0x408840, 1, 0x04, 0x0000000b }, - { 0x408900, 1, 0x04, 0x3080b801 }, - { 0x408904, 1, 0x04, 0x62000001 }, - { 0x408908, 1, 0x04, 0x00c8102f }, - { 0x408980, 1, 0x04, 0x0000011d }, - {} -}; - -const struct nvc0_graph_pack -nvf0_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvf0_grctx_init_fe_0 }, - { nvf0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { nve4_grctx_init_ds_0 }, - { nvf0_grctx_init_cwd_0 }, - { nvf0_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { nvf0_grctx_init_be_0 }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_setup_0[] = { - { 0x418800, 1, 0x04, 0x7006860a }, - { 0x418808, 1, 0x04, 0x00000000 }, - { 0x41880c, 1, 0x04, 0x00000030 }, - { 0x418810, 1, 0x04, 0x00000000 }, - { 0x418828, 1, 0x04, 0x00000044 }, - { 0x418830, 1, 0x04, 0x10000001 }, - { 0x4188d8, 1, 0x04, 0x00000008 }, - { 0x4188e0, 1, 0x04, 0x01000000 }, - { 0x4188e8, 5, 0x04, 0x00000000 }, - { 0x4188fc, 1, 0x04, 0x20100018 }, - {} -}; - -const struct nvc0_graph_init -nvf0_grctx_init_gpc_unk_2[] = { - { 0x418d24, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvf0_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nvf0_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nve4_grctx_init_gpm_0 }, - { nvf0_grctx_init_gpc_unk_2 }, - { nvc0_grctx_init_gcc_0 }, - {} -}; - -const struct nvc0_graph_init -nvf0_grctx_init_tex_0[] = { - { 0x419a00, 1, 0x04, 0x000000f0 }, - { 0x419a04, 1, 0x04, 0x00000001 }, - { 0x419a08, 1, 0x04, 0x00000021 }, - { 0x419a0c, 1, 0x04, 0x00020000 }, - { 0x419a10, 1, 0x04, 0x00000000 }, - { 0x419a14, 1, 0x04, 0x00000200 }, - { 0x419a1c, 1, 0x04, 0x0000c000 }, - { 0x419a20, 1, 0x04, 0x00020800 }, - { 0x419a30, 1, 0x04, 0x00000001 }, - { 0x419ac4, 1, 0x04, 0x0037f440 }, - {} -}; - -const struct nvc0_graph_init -nvf0_grctx_init_mpc_0[] = { - { 0x419c00, 1, 0x04, 0x0000001a }, - { 0x419c04, 1, 0x04, 0x80000006 }, - { 0x419c08, 1, 0x04, 0x00000002 }, - { 0x419c20, 1, 0x04, 0x00000000 }, - { 0x419c24, 1, 0x04, 0x00084210 }, - { 0x419c28, 1, 0x04, 0x3efbefbe }, - {} -}; - -const struct nvc0_graph_init -nvf0_grctx_init_l1c_0[] = { - { 0x419ce8, 1, 0x04, 0x00000000 }, - { 0x419cf4, 1, 0x04, 0x00000203 }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_sm_0[] = { - { 0x419e04, 1, 0x04, 0x00000000 }, - { 0x419e08, 1, 0x04, 0x0000001d }, - { 0x419e0c, 1, 0x04, 0x00000000 }, - { 0x419e10, 1, 0x04, 0x00001c02 }, - { 0x419e44, 1, 0x04, 0x0013eff2 }, - { 0x419e48, 1, 0x04, 0x00000000 }, - { 0x419e4c, 1, 0x04, 0x0000007f }, - { 0x419e50, 2, 0x04, 0x00000000 }, - { 0x419e58, 1, 0x04, 0x00000001 }, - { 0x419e5c, 3, 0x04, 0x00000000 }, - { 0x419e68, 1, 0x04, 0x00000002 }, - { 0x419e6c, 12, 0x04, 0x00000000 }, - { 0x419eac, 1, 0x04, 0x00001f8f }, - { 0x419eb0, 1, 0x04, 0x0db00d2f }, - { 0x419eb8, 1, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x0001304f }, - { 0x419f30, 4, 0x04, 0x00000000 }, - { 0x419f40, 1, 0x04, 0x00000018 }, - { 0x419f44, 3, 0x04, 0x00000000 }, - { 0x419f58, 1, 0x04, 0x00000000 }, - { 0x419f70, 1, 0x04, 0x00007300 }, - { 0x419f78, 1, 0x04, 0x000000eb }, - { 0x419f7c, 1, 0x04, 0x00000404 }, - {} -}; - -static const struct nvc0_graph_pack -nvf0_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nvf0_grctx_init_tex_0 }, - { nvf0_grctx_init_mpc_0 }, - { nvf0_grctx_init_l1c_0 }, - { nvf0_grctx_init_sm_0 }, - {} -}; - -static const struct nvc0_graph_init -nvf0_grctx_init_cbm_0[] = { - { 0x41bec0, 1, 0x04, 0x10000000 }, - { 0x41bec4, 1, 0x04, 0x00037f7f }, - { 0x41bee4, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_pack -nvf0_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { nvf0_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, - {} -}; - -/******************************************************************************* - * PGRAPH context implementation - ******************************************************************************/ - -struct nouveau_oclass * -nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xf0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nvf0_grctx_pack_hub, - .gpc = nvf0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvf0_grctx_pack_tpc, - .ppc = nvf0_grctx_pack_ppc, - .icmd = nvf0_grctx_pack_icmd, - .mthd = nvf0_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, - .bundle_size = 0x3000, - .bundle_min_gpm_fifo_depth = 0x180, - .bundle_token_limit = 0x7c0, - .pagepool = nve4_grctx_generate_pagepool, - .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, - .attrib_nr_max = 0x324, - .attrib_nr = 0x218, - .alpha_nr_max = 0x7ff, - .alpha_nr = 0x648, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc deleted file mode 100644 index e37d8106ae1a..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc +++ /dev/null @@ -1,335 +0,0 @@ -/* fuc microcode util functions for nvc0 PGRAPH - * - * Copyright 2011 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifdef INCLUDE_CODE -// queue_put - add request to queue -// -// In : $r13 queue pointer -// $r14 command -// $r15 data -// -queue_put: - // make sure we have space.. - ld b32 $r8 D[$r13 + 0x0] // GET - ld b32 $r9 D[$r13 + 0x4] // PUT - xor $r8 8 - cmpu b32 $r8 $r9 - bra ne #queue_put_next - mov $r15 E_CMD_OVERFLOW - call(error) - ret - - // store cmd/data on queue - queue_put_next: - and $r8 $r9 7 - shl b32 $r8 3 - add b32 $r8 $r13 - add b32 $r8 8 - st b32 D[$r8 + 0x0] $r14 - st b32 D[$r8 + 0x4] $r15 - - // update PUT - add b32 $r9 1 - and $r9 0xf - st b32 D[$r13 + 0x4] $r9 - ret - -// queue_get - fetch request from queue -// -// In : $r13 queue pointer -// -// Out: $p1 clear on success (data available) -// $r14 command -// $r15 data -// -queue_get: - bset $flags $p1 - ld b32 $r8 D[$r13 + 0x0] // GET - ld b32 $r9 D[$r13 + 0x4] // PUT - cmpu b32 $r8 $r9 - bra e #queue_get_done - // fetch first cmd/data pair - and $r9 $r8 7 - shl b32 $r9 3 - add b32 $r9 $r13 - add b32 $r9 8 - ld b32 $r14 D[$r9 + 0x0] - ld b32 $r15 D[$r9 + 0x4] - - // update GET - add b32 $r8 1 - and $r8 0xf - st b32 D[$r13 + 0x0] $r8 - bclr $flags $p1 -queue_get_done: - ret - -// nv_rd32 - read 32-bit value from nv register -// -// In : $r14 register -// Out: $r15 value -// -nv_rd32: - mov b32 $r12 $r14 - bset $r12 31 // MMIO_CTRL_PENDING - nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) - nv_rd32_wait: - nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) - xbit $r12 $r12 31 - bra ne #nv_rd32_wait - mov $r10 6 // DONE_MMIO_RD - call(wait_doneo) - nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0) - ret - -// nv_wr32 - write 32-bit value to nv register -// -// In : $r14 register -// $r15 value -// -nv_wr32: - nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15) - mov b32 $r12 $r14 - bset $r12 31 // MMIO_CTRL_PENDING - bset $r12 30 // MMIO_CTRL_WRITE - nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) - nv_wr32_wait: - nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) - xbit $r12 $r12 31 - bra ne #nv_wr32_wait - ret - -// wait_donez - wait on FUC_DONE bit to become clear -// -// In : $r10 bit to wait on -// -wait_donez: - trace_set(T_WAIT); - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) - wait_donez_ne: - nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) - xbit $r8 $r8 $r10 - bra ne #wait_donez_ne - trace_clr(T_WAIT) - ret - -// wait_doneo - wait on FUC_DONE bit to become set -// -// In : $r10 bit to wait on -// -wait_doneo: - trace_set(T_WAIT); - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) - wait_doneo_e: - nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) - xbit $r8 $r8 $r10 - bra e #wait_doneo_e - trace_clr(T_WAIT) - ret - -// mmctx_size - determine size of a mmio list transfer -// -// In : $r14 mmio list head -// $r15 mmio list tail -// Out: $r15 transfer size (in bytes) -// -mmctx_size: - clear b32 $r9 - nv_mmctx_size_loop: - ld b32 $r8 D[$r14] - shr b32 $r8 26 - add b32 $r8 1 - shl b32 $r8 2 - add b32 $r9 $r8 - add b32 $r14 4 - cmpu b32 $r14 $r15 - bra ne #nv_mmctx_size_loop - mov b32 $r15 $r9 - ret - -// mmctx_xfer - execute a list of mmio transfers -// -// In : $r10 flags -// bit 0: direction (0 = save, 1 = load) -// bit 1: set if first transfer -// bit 2: set if last transfer -// $r11 base -// $r12 mmio list head -// $r13 mmio list tail -// $r14 multi_stride -// $r15 multi_mask -// -mmctx_xfer: - trace_set(T_MMCTX) - clear b32 $r9 - or $r11 $r11 - bra e #mmctx_base_disabled - nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11) - bset $r9 0 // BASE_EN - mmctx_base_disabled: - or $r14 $r14 - bra e #mmctx_multi_disabled - nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14) - nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15) - bset $r9 1 // MULTI_EN - mmctx_multi_disabled: - - xbit $r11 $r10 0 - shl b32 $r11 16 // DIR - bset $r11 12 // QLIMIT = 0x10 - xbit $r14 $r10 1 - shl b32 $r14 17 - or $r11 $r14 // START_TRIGGER - nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) - - // loop over the mmio list, and send requests to the hw - mmctx_exec_loop: - // wait for space in mmctx queue - mmctx_wait_free: - nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0) - and $r14 0x1f - bra e #mmctx_wait_free - - // queue up an entry - ld b32 $r14 D[$r12] - or $r14 $r9 - nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14) - add b32 $r12 4 - cmpu b32 $r12 $r13 - bra ne #mmctx_exec_loop - - xbit $r11 $r10 2 - bra ne #mmctx_stop - // wait for queue to empty - mmctx_fini_wait: - nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) - and $r11 0x1f - cmpu b32 $r11 0x10 - bra ne #mmctx_fini_wait - mov $r10 5 // DONE_MMCTX - call(wait_donez) - bra #mmctx_done - mmctx_stop: - xbit $r11 $r10 0 - shl b32 $r11 16 // DIR - bset $r11 12 // QLIMIT = 0x10 - bset $r11 18 // STOP_TRIGGER - nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) - mmctx_stop_wait: - // wait for STOP_TRIGGER to clear - nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) - xbit $r11 $r11 18 - bra ne #mmctx_stop_wait - mmctx_done: - trace_clr(T_MMCTX) - ret - -// Wait for DONE_STRAND -// -strand_wait: - push $r10 - mov $r10 2 - call(wait_donez) - pop $r10 - ret - -// unknown - call before issuing strand commands -// -strand_pre: - mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) - call(strand_wait) - ret - -// unknown - call after issuing strand commands -// -strand_post: - mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) - call(strand_wait) - ret - -// Selects strand set?! -// -// In: $r14 id -// -strand_set: - mov $r12 0xf - nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12) - mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) - nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14) - mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) - call(strand_wait) - ret - -// Initialise strand context data -// -// In : $r15 context base -// Out: $r15 context size (in bytes) -// -// Strandset(?) 3 hardcoded currently -// -strand_ctx_init: - trace_set(T_STRINIT) - call(strand_pre) - mov $r14 3 - call(strand_set) - - clear b32 $r12 - nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12) - mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) - call(strand_wait) - sub b32 $r12 $r0 1 - nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12) - mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) - call(strand_wait) - call(strand_post) - - // read the size of each strand, poke the context offset of - // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry - // about it later then. - nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00) - nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00) - shr b32 $r14 $r15 8 - ctx_init_strand_loop: - iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE - iowr I[$r8 + 0x100] $r14 // STRAND_LOAD_SWBASE - iord $r10 I[$r8 + 0x200] // STRAND_SIZE - shr b32 $r10 6 - add b32 $r10 1 - add b32 $r14 $r10 - add b32 $r8 4 - sub b32 $r9 1 - bra ne #ctx_init_strand_loop - - shl b32 $r14 8 - sub b32 $r15 $r14 $r15 - trace_clr(T_STRINIT) - ret -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc deleted file mode 100644 index 7445f12b1d9e..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc +++ /dev/null @@ -1,378 +0,0 @@ -/* fuc microcode for nvc0 PGRAPH/GPC - * - * Copyright 2011 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -/* TODO - * - bracket certain functions with scratch writes, useful for debugging - * - watchdog timer around ctx operations - */ - -#ifdef INCLUDE_DATA -gpc_mmio_list_head: .b32 #mmio_list_base -gpc_mmio_list_tail: -tpc_mmio_list_head: .b32 #mmio_list_base -tpc_mmio_list_tail: -unk_mmio_list_head: .b32 #mmio_list_base -unk_mmio_list_tail: .b32 #mmio_list_base - -gpc_id: .b32 0 - -tpc_count: .b32 0 -tpc_mask: .b32 0 - -#if NV_PGRAPH_GPCX_UNK__SIZE > 0 -unk_count: .b32 0 -unk_mask: .b32 0 -#endif - -cmd_queue: queue_init - -mmio_list_base: -#endif - -#ifdef INCLUDE_CODE -// reports an exception to the host -// -// In: $r15 error code (see os.h) -// -error: - push $r14 - nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15) - mov $r15 1 - nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15) - pop $r14 - ret - -// GPC fuc initialisation, executed by triggering ucode start, will -// fall through to main loop after completion. -// -// Input: -// CC_SCRATCH[1]: context base -// -// Output: -// CC_SCRATCH[0]: -// 31:31: set to signal completion -// CC_SCRATCH[1]: -// 31:0: GPC context size -// -init: - clear b32 $r0 - - // setup stack - nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0) - extr $r1 $r1 9:17 - shl b32 $r1 8 - mov $sp $r1 - - // enable fifo access - mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO - nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2) - - // setup i0 handler, and route all interrupts to it - mov $r1 #ih - mov $iv0 $r1 - nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0) - - // enable fifo interrupt - mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO - nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2) - - // enable interrupts - bset $flags ie0 - - // figure out which GPC we are, and how many TPCs we have - nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0) - mov $r3 1 - and $r2 0x1f - shl b32 $r3 $r2 - sub b32 $r3 1 - st b32 D[$r0 + #tpc_count] $r2 - st b32 D[$r0 + #tpc_mask] $r3 - nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0) - st b32 D[$r0 + #gpc_id] $r2 - -#if NV_PGRAPH_GPCX_UNK__SIZE > 0 - // figure out which, and how many, UNKs are actually present - imm32($r14, 0x500c30) - clear b32 $r2 - clear b32 $r3 - clear b32 $r4 - init_unk_loop: - call(nv_rd32) - cmp b32 $r15 0 - bra z #init_unk_next - mov $r15 1 - shl b32 $r15 $r2 - or $r4 $r15 - add b32 $r3 1 - init_unk_next: - add b32 $r2 1 - add b32 $r14 4 - cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE - bra ne #init_unk_loop - init_unk_done: - st b32 D[$r0 + #unk_count] $r3 - st b32 D[$r0 + #unk_mask] $r4 -#endif - - // initialise context base, and size tracking - nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0) - clear b32 $r3 // track GPC context size here - - // set mmctx base addresses now so we don't have to do it later, - // they don't currently ever change - shr b32 $r5 $r2 8 - nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5) - nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5) - - // calculate GPC mmio context size - ld b32 $r14 D[$r0 + #gpc_mmio_list_head] - ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] - call(mmctx_size) - add b32 $r2 $r15 - add b32 $r3 $r15 - - // calculate per-TPC mmio context size - ld b32 $r14 D[$r0 + #tpc_mmio_list_head] - ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] - call(mmctx_size) - ld b32 $r14 D[$r0 + #tpc_count] - mulu $r14 $r15 - add b32 $r2 $r14 - add b32 $r3 $r14 - -#if NV_PGRAPH_GPCX_UNK__SIZE > 0 - // calculate per-UNK mmio context size - ld b32 $r14 D[$r0 + #unk_mmio_list_head] - ld b32 $r15 D[$r0 + #unk_mmio_list_tail] - call(mmctx_size) - ld b32 $r14 D[$r0 + #unk_count] - mulu $r14 $r15 - add b32 $r2 $r14 - add b32 $r3 $r14 -#endif - - // round up base/size to 256 byte boundary (for strand SWBASE) - shr b32 $r3 2 - nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?! - shr b32 $r2 8 - shr b32 $r3 6 - add b32 $r2 1 - add b32 $r3 1 - shl b32 $r2 8 - shl b32 $r3 8 - - // calculate size of strand context data - mov b32 $r15 $r2 - call(strand_ctx_init) - add b32 $r3 $r15 - - // save context size, and tell HUB we're done - nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3) - clear b32 $r2 - bset $r2 31 - nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2) - -// Main program loop, very simple, sleeps until woken up by the interrupt -// handler, pulls a command from the queue and executes its handler -// -main: - bset $flags $p0 - sleep $p0 - mov $r13 #cmd_queue - call(queue_get) - bra $p1 #main - - // 0x0000-0x0003 are all context transfers - cmpu b32 $r14 0x04 - bra nc #main_not_ctx_xfer - // fetch $flags and mask off $p1/$p2 - mov $r1 $flags - mov $r2 0x0006 - not b32 $r2 - and $r1 $r2 - // set $p1/$p2 according to transfer type - shl b32 $r14 1 - or $r1 $r14 - mov $flags $r1 - // transfer context data - call(ctx_xfer) - bra #main - - main_not_ctx_xfer: - shl b32 $r15 $r14 16 - or $r15 E_BAD_COMMAND - call(error) - bra #main - -// interrupt handler -ih: - push $r8 - mov $r8 $flags - push $r8 - push $r9 - push $r10 - push $r11 - push $r13 - push $r14 - push $r15 - clear b32 $r0 - - // incoming fifo command? - nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0) - and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO - bra e #ih_no_fifo - // queue incoming fifo command for later processing - mov $r13 #cmd_queue - nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0) - nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0) - call(queue_put) - mov $r14 1 - nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14) - - // ack, and wake up main() - ih_no_fifo: - nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10) - - pop $r15 - pop $r14 - pop $r13 - pop $r11 - pop $r10 - pop $r9 - pop $r8 - mov $flags $r8 - pop $r8 - bclr $flags $p0 - iret - -// Set this GPC's bit in HUB_BAR, used to signal completion of various -// activities to the HUB fuc -// -hub_barrier_done: - mov $r15 1 - ld b32 $r14 D[$r0 + #gpc_id] - shl b32 $r15 $r14 - nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET - ret - -// Disables various things, waits a bit, and re-enables them.. -// -// Not sure how exactly this helps, perhaps "ENABLE" is not such a -// good description for the bits we turn off? Anyways, without this, -// funny things happen. -// -ctx_redswitch: - mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER - nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) - mov $r14 8 - ctx_redswitch_delay: - sub b32 $r14 1 - bra ne #ctx_redswitch_delay - or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 - or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE - nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) - ret - -// Transfer GPC context data between GPU and storage area -// -// In: $r15 context base address -// $p1 clear on save, set on load -// $p2 set if opposite direction done/will be done, so: -// on save it means: "a load will follow this save" -// on load it means: "a save preceeded this load" -// -ctx_xfer: - // set context base address - nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15) - bra not $p1 #ctx_xfer_not_load - call(ctx_redswitch) - ctx_xfer_not_load: - - // strands - call(strand_pre) - clear b32 $r2 - nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2) - xbit $r2 $flags $p1 // SAVE/LOAD - add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE - nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2) - - // mmio context - xbit $r10 $flags $p1 // direction - or $r10 2 // first - imm32($r11,0x500000) - ld b32 $r12 D[$r0 + #gpc_id] - shl b32 $r12 15 - add b32 $r11 $r12 // base = NV_PGRAPH_GPCn - ld b32 $r12 D[$r0 + #gpc_mmio_list_head] - ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] - mov $r14 0 // not multi - call(mmctx_xfer) - - // per-TPC mmio context - xbit $r10 $flags $p1 // direction -#if !NV_PGRAPH_GPCX_UNK__SIZE - or $r10 4 // last -#endif - imm32($r11, 0x504000) - ld b32 $r12 D[$r0 + #gpc_id] - shl b32 $r12 15 - add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 - ld b32 $r12 D[$r0 + #tpc_mmio_list_head] - ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] - ld b32 $r15 D[$r0 + #tpc_mask] - mov $r14 0x800 // stride = 0x800 - call(mmctx_xfer) - -#if NV_PGRAPH_GPCX_UNK__SIZE > 0 - // per-UNK mmio context - xbit $r10 $flags $p1 // direction - or $r10 4 // last - imm32($r11, 0x503000) - ld b32 $r12 D[$r0 + #gpc_id] - shl b32 $r12 15 - add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 - ld b32 $r12 D[$r0 + #unk_mmio_list_head] - ld b32 $r13 D[$r0 + #unk_mmio_list_tail] - ld b32 $r15 D[$r0 + #unk_mask] - mov $r14 0x200 // stride = 0x200 - call(mmctx_xfer) -#endif - - // wait for strands to finish - call(strand_wait) - - // if load, or a save without a load following, do some - // unknown stuff that's done after finishing a block of - // strand commands - bra $p1 #ctx_xfer_post - bra not $p2 #ctx_xfer_done - ctx_xfer_post: - call(strand_post) - - // mark completion in HUB's barrier - ctx_xfer_done: - call(hub_barrier_done) - ret -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5 deleted file mode 100644 index e730603891d7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5 +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 - -#define CHIPSET GK208 -#include "macros.fuc" - -.section #gm107_grgpc_data -#define INCLUDE_DATA -#include "com.fuc" -#include "gpc.fuc" -#undef INCLUDE_DATA - -.section #gm107_grgpc_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "gpc.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h deleted file mode 100644 index 6d53b67dd3c4..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h +++ /dev/null @@ -1,473 +0,0 @@ -uint32_t gm107_grgpc_data[] = { -/* 0x0000: gpc_mmio_list_head */ - 0x0000006c, -/* 0x0004: gpc_mmio_list_tail */ -/* 0x0004: tpc_mmio_list_head */ - 0x0000006c, -/* 0x0008: tpc_mmio_list_tail */ -/* 0x0008: unk_mmio_list_head */ - 0x0000006c, -/* 0x000c: unk_mmio_list_tail */ - 0x0000006c, -/* 0x0010: gpc_id */ - 0x00000000, -/* 0x0014: tpc_count */ - 0x00000000, -/* 0x0018: tpc_mask */ - 0x00000000, -/* 0x001c: unk_count */ - 0x00000000, -/* 0x0020: unk_mask */ - 0x00000000, -/* 0x0024: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t gm107_grgpc_code[] = { - 0x03140ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0xf489a408, - 0x020f0b1b, - 0x0002f87e, -/* 0x001a: queue_put_next */ - 0x98c400f8, - 0x0384b607, - 0xb6008dbb, - 0x8eb50880, - 0x018fb500, - 0xf00190b6, - 0xd9b50f94, -/* 0x0037: queue_get */ - 0xf400f801, - 0xd8980131, - 0x01d99800, - 0x0bf489a4, - 0x0789c421, - 0xbb0394b6, - 0x90b6009d, - 0x009e9808, - 0xb6019f98, - 0x84f00180, - 0x00d8b50f, -/* 0x0063: queue_get_done */ - 0xf80132f4, -/* 0x0065: nv_rd32 */ - 0xf0ecb200, - 0x00801fc9, - 0x0cf601ca, -/* 0x0073: nv_rd32_wait */ - 0x8c04bd00, - 0xcf01ca00, - 0xccc800cc, - 0xf61bf41f, - 0xec7e060a, - 0x008f0000, - 0xffcf01cb, -/* 0x008f: nv_wr32 */ - 0x8000f800, - 0xf601cc00, - 0x04bd000f, - 0xc9f0ecb2, - 0x1ec9f01f, - 0x01ca0080, - 0xbd000cf6, -/* 0x00a9: nv_wr32_wait */ - 0xca008c04, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f61b, -/* 0x00b8: wait_donez */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x00cf: wait_donez_ne */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf61bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x00ec: wait_doneo */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x0103: wait_doneo_e */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf60bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x0120: mmctx_size */ -/* 0x0122: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0x1bf4efa4, - 0xf89fb2ec, -/* 0x013d: mmctx_xfer */ - 0xf094bd00, - 0x00800199, - 0x09f60237, - 0xbd04bd00, - 0x05bbfd94, - 0x800f0bf4, - 0xf601c400, - 0x04bd000b, -/* 0x015f: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0xc6008018, - 0x000ef601, - 0x008004bd, - 0x0ff601c7, - 0xf004bd00, -/* 0x017a: mmctx_multi_disabled */ - 0xabc80199, - 0x10b4b600, - 0xc80cb9f0, - 0xe4b601ae, - 0x05befd11, - 0x01c50080, - 0xbd000bf6, -/* 0x0195: mmctx_exec_loop */ -/* 0x0195: mmctx_wait_free */ - 0xc5008e04, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f60b, - 0x05e9fd00, - 0x01c80080, - 0xbd000ef6, - 0x04c0b604, - 0x1bf4cda4, - 0x02abc8df, -/* 0x01bf: mmctx_fini_wait */ - 0x8b1c1bf4, - 0xcf01c500, - 0xb4f000bb, - 0x10b4b01f, - 0x0af31bf4, - 0x00b87e05, - 0x250ef400, -/* 0x01d8: mmctx_stop */ - 0xb600abc8, - 0xb9f010b4, - 0x12b9f00c, - 0x01c50080, - 0xbd000bf6, -/* 0x01ed: mmctx_stop_wait */ - 0xc5008b04, - 0x00bbcf01, - 0xf412bbc8, -/* 0x01fa: mmctx_done */ - 0x94bdf61b, - 0x800199f0, - 0xf6021700, - 0x04bd0009, -/* 0x020a: strand_wait */ - 0xa0f900f8, - 0xb87e020a, - 0xa0fc0000, -/* 0x0216: strand_pre */ - 0x0c0900f8, - 0x024afc80, - 0xbd0009f6, - 0x020a7e04, -/* 0x0227: strand_post */ - 0x0900f800, - 0x4afc800d, - 0x0009f602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0238: strand_set */ - 0xfc800f0c, - 0x0cf6024f, - 0x0c04bd00, - 0x4afc800b, - 0x000cf602, - 0xfc8004bd, - 0x0ef6024f, - 0x0c04bd00, - 0x4afc800a, - 0x000cf602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0268: strand_ctx_init */ - 0x99f094bd, - 0x37008003, - 0x0009f602, - 0x167e04bd, - 0x030e0002, - 0x0002387e, - 0xfc80c4bd, - 0x0cf60247, - 0x0c04bd00, - 0x4afc8001, - 0x000cf602, - 0x0a7e04bd, - 0x0c920002, - 0x46fc8001, - 0x000cf602, - 0x020c04bd, - 0x024afc80, - 0xbd000cf6, - 0x020a7e04, - 0x02277e00, - 0x42008800, - 0x20008902, - 0x0099cf02, -/* 0x02c7: ctx_init_strand_loop */ - 0xf608fe95, - 0x8ef6008e, - 0x808acf40, - 0xb606a5b6, - 0xeabb01a0, - 0x0480b600, - 0xf40192b6, - 0xe4b6e81b, - 0xf2efbc08, - 0x99f094bd, - 0x17008003, - 0x0009f602, - 0x00f804bd, -/* 0x02f8: error */ - 0xffb2e0f9, - 0x4098148e, - 0x00008f7e, - 0xffb2010f, - 0x409c1c8e, - 0x00008f7e, - 0x00f8e0fc, -/* 0x0314: init */ - 0x004104bd, - 0x0011cf42, - 0x010911e7, - 0xfe0814b6, - 0x02020014, - 0xf6120040, - 0x04bd0002, - 0xfe047241, - 0x00400010, - 0x0000f607, - 0x040204bd, - 0xf6040040, - 0x04bd0002, - 0x821031f4, - 0xcf018200, - 0x01030022, - 0xbb1f24f0, - 0x32b60432, - 0x0502b501, - 0x820603b5, - 0xcf018600, - 0x02b50022, - 0x0c308e04, - 0xbd24bd50, -/* 0x0377: init_unk_loop */ - 0x7e44bd34, - 0xb0000065, - 0x0bf400f6, - 0xbb010f0e, - 0x4ffd04f2, - 0x0130b605, -/* 0x038c: init_unk_next */ - 0xb60120b6, - 0x26b004e0, - 0xe21bf402, -/* 0x0398: init_unk_done */ - 0xb50703b5, - 0x00820804, - 0x22cf0201, - 0x9534bd00, - 0x00800825, - 0x05f601c0, - 0x8004bd00, - 0xf601c100, - 0x04bd0005, - 0x98000e98, - 0x207e010f, - 0x2fbb0001, - 0x003fbb00, - 0x98010e98, - 0x207e020f, - 0x0e980001, - 0x00effd05, - 0xbb002ebb, - 0x0e98003e, - 0x030f9802, - 0x0001207e, - 0xfd070e98, - 0x2ebb00ef, - 0x003ebb00, - 0x800235b6, - 0xf601d300, - 0x04bd0003, - 0xb60825b6, - 0x20b60635, - 0x0130b601, - 0xb60824b6, - 0x2fb20834, - 0x0002687e, - 0x80003fbb, - 0xf6020100, - 0x04bd0003, - 0x29f024bd, - 0x3000801f, - 0x0002f602, -/* 0x0436: main */ - 0x31f404bd, - 0x0028f400, - 0x377e240d, - 0x01f40000, - 0x04e4b0f4, - 0xfe1d18f4, - 0x06020181, - 0x12fd20bd, - 0x01e4b604, - 0xfe051efd, - 0x097e0018, - 0x0ef40005, -/* 0x0465: main_not_ctx_xfer */ - 0x10ef94d4, - 0x7e01f5f0, - 0xf40002f8, -/* 0x0472: ih */ - 0x80f9c70e, - 0xf90188fe, - 0xf990f980, - 0xf9b0f9a0, - 0xf9e0f9d0, - 0x4a04bdf0, - 0xaacf0200, - 0x04abc400, - 0x0d1f0bf4, - 0x1a004e24, - 0x4f00eecf, - 0xffcf1900, - 0x00047e00, - 0x40010e00, - 0x0ef61d00, -/* 0x04af: ih_no_fifo */ - 0x4004bd00, - 0x0af60100, - 0xfc04bd00, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x04cf: hub_barrier_done */ - 0x0f01f800, - 0x040e9801, - 0xb204febb, - 0x94188eff, - 0x008f7e40, -/* 0x04e3: ctx_redswitch */ - 0x0f00f800, - 0x85008020, - 0x000ff601, - 0x080e04bd, -/* 0x04f0: ctx_redswitch_delay */ - 0xf401e2b6, - 0xf5f1fd1b, - 0xf5f10800, - 0x00800200, - 0x0ff60185, - 0xf804bd00, -/* 0x0509: ctx_xfer */ - 0x81008000, - 0x000ff602, - 0x11f404bd, - 0x04e37e07, -/* 0x0519: ctx_xfer_not_load */ - 0x02167e00, - 0x8024bd00, - 0xf60247fc, - 0x04bd0002, - 0xb6012cf0, - 0xfc800320, - 0x02f6024a, - 0xf004bd00, - 0xa5f001ac, - 0x00008b02, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x010d9800, - 0x3d7e000e, - 0xacf00001, - 0x40008b01, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x020d9801, - 0x4e060f98, - 0x3d7e0800, - 0xacf00001, - 0x04a5f001, - 0x5030008b, - 0xb6040c98, - 0xbcbb0fc4, - 0x020c9800, - 0x98030d98, - 0x004e080f, - 0x013d7e02, - 0x020a7e00, - 0x0601f400, -/* 0x05a3: ctx_xfer_post */ - 0x7e0712f4, -/* 0x05a7: ctx_xfer_done */ - 0x7e000227, - 0xf80004cf, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5 deleted file mode 100644 index bd30262d635b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5 +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 - -#define CHIPSET GK208 -#include "macros.fuc" - -.section #nv108_grgpc_data -#define INCLUDE_DATA -#include "com.fuc" -#include "gpc.fuc" -#undef INCLUDE_DATA - -.section #nv108_grgpc_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "gpc.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h deleted file mode 100644 index 31922707794f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h +++ /dev/null @@ -1,473 +0,0 @@ -uint32_t nv108_grgpc_data[] = { -/* 0x0000: gpc_mmio_list_head */ - 0x0000006c, -/* 0x0004: gpc_mmio_list_tail */ -/* 0x0004: tpc_mmio_list_head */ - 0x0000006c, -/* 0x0008: tpc_mmio_list_tail */ -/* 0x0008: unk_mmio_list_head */ - 0x0000006c, -/* 0x000c: unk_mmio_list_tail */ - 0x0000006c, -/* 0x0010: gpc_id */ - 0x00000000, -/* 0x0014: tpc_count */ - 0x00000000, -/* 0x0018: tpc_mask */ - 0x00000000, -/* 0x001c: unk_count */ - 0x00000000, -/* 0x0020: unk_mask */ - 0x00000000, -/* 0x0024: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t nv108_grgpc_code[] = { - 0x03140ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0xf489a408, - 0x020f0b1b, - 0x0002f87e, -/* 0x001a: queue_put_next */ - 0x98c400f8, - 0x0384b607, - 0xb6008dbb, - 0x8eb50880, - 0x018fb500, - 0xf00190b6, - 0xd9b50f94, -/* 0x0037: queue_get */ - 0xf400f801, - 0xd8980131, - 0x01d99800, - 0x0bf489a4, - 0x0789c421, - 0xbb0394b6, - 0x90b6009d, - 0x009e9808, - 0xb6019f98, - 0x84f00180, - 0x00d8b50f, -/* 0x0063: queue_get_done */ - 0xf80132f4, -/* 0x0065: nv_rd32 */ - 0xf0ecb200, - 0x00801fc9, - 0x0cf601ca, -/* 0x0073: nv_rd32_wait */ - 0x8c04bd00, - 0xcf01ca00, - 0xccc800cc, - 0xf61bf41f, - 0xec7e060a, - 0x008f0000, - 0xffcf01cb, -/* 0x008f: nv_wr32 */ - 0x8000f800, - 0xf601cc00, - 0x04bd000f, - 0xc9f0ecb2, - 0x1ec9f01f, - 0x01ca0080, - 0xbd000cf6, -/* 0x00a9: nv_wr32_wait */ - 0xca008c04, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f61b, -/* 0x00b8: wait_donez */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x00cf: wait_donez_ne */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf61bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x00ec: wait_doneo */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x0103: wait_doneo_e */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf60bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x0120: mmctx_size */ -/* 0x0122: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0x1bf4efa4, - 0xf89fb2ec, -/* 0x013d: mmctx_xfer */ - 0xf094bd00, - 0x00800199, - 0x09f60237, - 0xbd04bd00, - 0x05bbfd94, - 0x800f0bf4, - 0xf601c400, - 0x04bd000b, -/* 0x015f: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0xc6008018, - 0x000ef601, - 0x008004bd, - 0x0ff601c7, - 0xf004bd00, -/* 0x017a: mmctx_multi_disabled */ - 0xabc80199, - 0x10b4b600, - 0xc80cb9f0, - 0xe4b601ae, - 0x05befd11, - 0x01c50080, - 0xbd000bf6, -/* 0x0195: mmctx_exec_loop */ -/* 0x0195: mmctx_wait_free */ - 0xc5008e04, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f60b, - 0x05e9fd00, - 0x01c80080, - 0xbd000ef6, - 0x04c0b604, - 0x1bf4cda4, - 0x02abc8df, -/* 0x01bf: mmctx_fini_wait */ - 0x8b1c1bf4, - 0xcf01c500, - 0xb4f000bb, - 0x10b4b01f, - 0x0af31bf4, - 0x00b87e05, - 0x250ef400, -/* 0x01d8: mmctx_stop */ - 0xb600abc8, - 0xb9f010b4, - 0x12b9f00c, - 0x01c50080, - 0xbd000bf6, -/* 0x01ed: mmctx_stop_wait */ - 0xc5008b04, - 0x00bbcf01, - 0xf412bbc8, -/* 0x01fa: mmctx_done */ - 0x94bdf61b, - 0x800199f0, - 0xf6021700, - 0x04bd0009, -/* 0x020a: strand_wait */ - 0xa0f900f8, - 0xb87e020a, - 0xa0fc0000, -/* 0x0216: strand_pre */ - 0x0c0900f8, - 0x024afc80, - 0xbd0009f6, - 0x020a7e04, -/* 0x0227: strand_post */ - 0x0900f800, - 0x4afc800d, - 0x0009f602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0238: strand_set */ - 0xfc800f0c, - 0x0cf6024f, - 0x0c04bd00, - 0x4afc800b, - 0x000cf602, - 0xfc8004bd, - 0x0ef6024f, - 0x0c04bd00, - 0x4afc800a, - 0x000cf602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0268: strand_ctx_init */ - 0x99f094bd, - 0x37008003, - 0x0009f602, - 0x167e04bd, - 0x030e0002, - 0x0002387e, - 0xfc80c4bd, - 0x0cf60247, - 0x0c04bd00, - 0x4afc8001, - 0x000cf602, - 0x0a7e04bd, - 0x0c920002, - 0x46fc8001, - 0x000cf602, - 0x020c04bd, - 0x024afc80, - 0xbd000cf6, - 0x020a7e04, - 0x02277e00, - 0x42008800, - 0x20008902, - 0x0099cf02, -/* 0x02c7: ctx_init_strand_loop */ - 0xf608fe95, - 0x8ef6008e, - 0x808acf40, - 0xb606a5b6, - 0xeabb01a0, - 0x0480b600, - 0xf40192b6, - 0xe4b6e81b, - 0xf2efbc08, - 0x99f094bd, - 0x17008003, - 0x0009f602, - 0x00f804bd, -/* 0x02f8: error */ - 0xffb2e0f9, - 0x4098148e, - 0x00008f7e, - 0xffb2010f, - 0x409c1c8e, - 0x00008f7e, - 0x00f8e0fc, -/* 0x0314: init */ - 0x004104bd, - 0x0011cf42, - 0x010911e7, - 0xfe0814b6, - 0x02020014, - 0xf6120040, - 0x04bd0002, - 0xfe047241, - 0x00400010, - 0x0000f607, - 0x040204bd, - 0xf6040040, - 0x04bd0002, - 0x821031f4, - 0xcf018200, - 0x01030022, - 0xbb1f24f0, - 0x32b60432, - 0x0502b501, - 0x820603b5, - 0xcf018600, - 0x02b50022, - 0x0c308e04, - 0xbd24bd50, -/* 0x0377: init_unk_loop */ - 0x7e44bd34, - 0xb0000065, - 0x0bf400f6, - 0xbb010f0e, - 0x4ffd04f2, - 0x0130b605, -/* 0x038c: init_unk_next */ - 0xb60120b6, - 0x26b004e0, - 0xe21bf401, -/* 0x0398: init_unk_done */ - 0xb50703b5, - 0x00820804, - 0x22cf0201, - 0x9534bd00, - 0x00800825, - 0x05f601c0, - 0x8004bd00, - 0xf601c100, - 0x04bd0005, - 0x98000e98, - 0x207e010f, - 0x2fbb0001, - 0x003fbb00, - 0x98010e98, - 0x207e020f, - 0x0e980001, - 0x00effd05, - 0xbb002ebb, - 0x0e98003e, - 0x030f9802, - 0x0001207e, - 0xfd070e98, - 0x2ebb00ef, - 0x003ebb00, - 0x800235b6, - 0xf601d300, - 0x04bd0003, - 0xb60825b6, - 0x20b60635, - 0x0130b601, - 0xb60824b6, - 0x2fb20834, - 0x0002687e, - 0x80003fbb, - 0xf6020100, - 0x04bd0003, - 0x29f024bd, - 0x3000801f, - 0x0002f602, -/* 0x0436: main */ - 0x31f404bd, - 0x0028f400, - 0x377e240d, - 0x01f40000, - 0x04e4b0f4, - 0xfe1d18f4, - 0x06020181, - 0x12fd20bd, - 0x01e4b604, - 0xfe051efd, - 0x097e0018, - 0x0ef40005, -/* 0x0465: main_not_ctx_xfer */ - 0x10ef94d4, - 0x7e01f5f0, - 0xf40002f8, -/* 0x0472: ih */ - 0x80f9c70e, - 0xf90188fe, - 0xf990f980, - 0xf9b0f9a0, - 0xf9e0f9d0, - 0x4a04bdf0, - 0xaacf0200, - 0x04abc400, - 0x0d1f0bf4, - 0x1a004e24, - 0x4f00eecf, - 0xffcf1900, - 0x00047e00, - 0x40010e00, - 0x0ef61d00, -/* 0x04af: ih_no_fifo */ - 0x4004bd00, - 0x0af60100, - 0xfc04bd00, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x04cf: hub_barrier_done */ - 0x0f01f800, - 0x040e9801, - 0xb204febb, - 0x94188eff, - 0x008f7e40, -/* 0x04e3: ctx_redswitch */ - 0x0f00f800, - 0x85008020, - 0x000ff601, - 0x080e04bd, -/* 0x04f0: ctx_redswitch_delay */ - 0xf401e2b6, - 0xf5f1fd1b, - 0xf5f10800, - 0x00800200, - 0x0ff60185, - 0xf804bd00, -/* 0x0509: ctx_xfer */ - 0x81008000, - 0x000ff602, - 0x11f404bd, - 0x04e37e07, -/* 0x0519: ctx_xfer_not_load */ - 0x02167e00, - 0x8024bd00, - 0xf60247fc, - 0x04bd0002, - 0xb6012cf0, - 0xfc800320, - 0x02f6024a, - 0xf004bd00, - 0xa5f001ac, - 0x00008b02, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x010d9800, - 0x3d7e000e, - 0xacf00001, - 0x40008b01, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x020d9801, - 0x4e060f98, - 0x3d7e0800, - 0xacf00001, - 0x04a5f001, - 0x5030008b, - 0xb6040c98, - 0xbcbb0fc4, - 0x020c9800, - 0x98030d98, - 0x004e080f, - 0x013d7e02, - 0x020a7e00, - 0x0601f400, -/* 0x05a3: ctx_xfer_post */ - 0x7e0712f4, -/* 0x05a7: ctx_xfer_done */ - 0x7e000227, - 0xf80004cf, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3 deleted file mode 100644 index 5ae06a2d64c9..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3 +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000 - -#define CHIPSET GF100 -#include "macros.fuc" - -.section #nvc0_grgpc_data -#define INCLUDE_DATA -#include "com.fuc" -#include "gpc.fuc" -#undef INCLUDE_DATA - -.section #nvc0_grgpc_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "gpc.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h deleted file mode 100644 index 325cc7b7b2fb..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h +++ /dev/null @@ -1,530 +0,0 @@ -uint32_t nvc0_grgpc_data[] = { -/* 0x0000: gpc_mmio_list_head */ - 0x00000064, -/* 0x0004: gpc_mmio_list_tail */ -/* 0x0004: tpc_mmio_list_head */ - 0x00000064, -/* 0x0008: tpc_mmio_list_tail */ -/* 0x0008: unk_mmio_list_head */ - 0x00000064, -/* 0x000c: unk_mmio_list_tail */ - 0x00000064, -/* 0x0010: gpc_id */ - 0x00000000, -/* 0x0014: tpc_count */ - 0x00000000, -/* 0x0018: tpc_mask */ - 0x00000000, -/* 0x001c: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t nvc0_grgpc_code[] = { - 0x03a10ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0xe0f900f8, - 0xf102ffb9, - 0xf09814e7, - 0x21f440e3, - 0x01f7f09d, - 0xf102ffb9, - 0xf09c1ce7, - 0x21f440e3, - 0xf8e0fc9d, -/* 0x03a1: init */ - 0xf104bd00, - 0xf0420017, - 0x11cf0013, - 0x0911e700, - 0x0814b601, - 0xf00014fe, - 0x07f10227, - 0x03f01200, - 0x0002d000, - 0x17f104bd, - 0x10fe04e6, - 0x0007f100, - 0x0003f007, - 0xbd0000d0, - 0x0427f004, - 0x040007f1, - 0xd00003f0, - 0x04bd0002, - 0xf11031f4, - 0xf0820027, - 0x22cf0123, - 0x0137f000, - 0xbb1f24f0, - 0x32b60432, - 0x05028001, - 0xf1060380, - 0xf0860027, - 0x22cf0123, - 0x04028000, - 0x010027f1, - 0xcf0223f0, - 0x34bd0022, - 0xf1082595, - 0xf0c00007, - 0x05d00103, - 0xf104bd00, - 0xf0c10007, - 0x05d00103, - 0x9804bd00, - 0x0f98000e, - 0x5021f501, - 0x002fbb01, - 0x98003fbb, - 0x0f98010e, - 0x5021f502, - 0x050e9801, - 0xbb00effd, - 0x3ebb002e, - 0x0235b600, - 0xd30007f1, - 0xd00103f0, - 0x04bd0003, - 0xb60825b6, - 0x20b60635, - 0x0130b601, - 0xb60824b6, - 0x2fb90834, - 0xd321f502, - 0x003fbb02, - 0x010007f1, - 0xd00203f0, - 0x04bd0003, - 0x29f024bd, - 0x0007f11f, - 0x0203f008, - 0xbd0002d0, -/* 0x04a9: main */ - 0x0031f404, - 0xf00028f4, - 0x21f41cd7, - 0xf401f439, - 0xf404e4b0, - 0x81fe1e18, - 0x0627f001, - 0x12fd20bd, - 0x01e4b604, - 0xfe051efd, - 0x21f50018, - 0x0ef4059e, -/* 0x04d9: main_not_ctx_xfer */ - 0x10ef94d3, - 0xf501f5f0, - 0xf4037e21, -/* 0x04e6: ih */ - 0x80f9c60e, - 0xf90188fe, - 0xf990f980, - 0xf9b0f9a0, - 0xf9e0f9d0, - 0xf104bdf0, - 0xf00200a7, - 0xaacf00a3, - 0x04abc400, - 0xf02c0bf4, - 0xe7f11cd7, - 0xe3f01a00, - 0x00eecf00, - 0x1900f7f1, - 0xcf00f3f0, - 0x21f400ff, - 0x01e7f004, - 0x1d0007f1, - 0xd00003f0, - 0x04bd000e, -/* 0x0534: ih_no_fifo */ - 0x010007f1, - 0xd00003f0, - 0x04bd000a, - 0xe0fcf0fc, - 0xb0fcd0fc, - 0x90fca0fc, - 0x88fe80fc, - 0xf480fc00, - 0x01f80032, -/* 0x0558: hub_barrier_done */ - 0x9801f7f0, - 0xfebb040e, - 0x02ffb904, - 0x9418e7f1, - 0xf440e3f0, - 0x00f89d21, -/* 0x0570: ctx_redswitch */ - 0xf120f7f0, - 0xf0850007, - 0x0fd00103, - 0xf004bd00, -/* 0x0582: ctx_redswitch_delay */ - 0xe2b608e7, - 0xfd1bf401, - 0x0800f5f1, - 0x0200f5f1, - 0x850007f1, - 0xd00103f0, - 0x04bd000f, -/* 0x059e: ctx_xfer */ - 0x07f100f8, - 0x03f08100, - 0x000fd002, - 0x11f404bd, - 0x7021f507, -/* 0x05b1: ctx_xfer_not_load */ - 0x6a21f505, - 0xf124bd02, - 0xf047fc07, - 0x02d00203, - 0xf004bd00, - 0x20b6012c, - 0xfc07f103, - 0x0203f04a, - 0xbd0002d0, - 0x01acf004, - 0xf102a5f0, - 0xf00000b7, - 0x0c9850b3, - 0x0fc4b604, - 0x9800bcbb, - 0x0d98000c, - 0x00e7f001, - 0x016f21f5, - 0xf001acf0, - 0xb7f104a5, - 0xb3f04000, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x020d9801, - 0xf1060f98, - 0xf50800e7, - 0xf5016f21, - 0xf4025e21, - 0x12f40601, -/* 0x0629: ctx_xfer_post */ - 0x7f21f507, -/* 0x062d: ctx_xfer_done */ - 0x5821f502, - 0x0000f805, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3 deleted file mode 100644 index c2f754edbd7d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3 +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 - -#define CHIPSET GF117 -#include "macros.fuc" - -.section #nvd7_grgpc_data -#define INCLUDE_DATA -#include "com.fuc" -#include "gpc.fuc" -#undef INCLUDE_DATA - -.section #nvd7_grgpc_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "gpc.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h deleted file mode 100644 index d1504a4059c6..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h +++ /dev/null @@ -1,537 +0,0 @@ -uint32_t nvd7_grgpc_data[] = { -/* 0x0000: gpc_mmio_list_head */ - 0x0000006c, -/* 0x0004: gpc_mmio_list_tail */ -/* 0x0004: tpc_mmio_list_head */ - 0x0000006c, -/* 0x0008: tpc_mmio_list_tail */ -/* 0x0008: unk_mmio_list_head */ - 0x0000006c, -/* 0x000c: unk_mmio_list_tail */ - 0x0000006c, -/* 0x0010: gpc_id */ - 0x00000000, -/* 0x0014: tpc_count */ - 0x00000000, -/* 0x0018: tpc_mask */ - 0x00000000, -/* 0x001c: unk_count */ - 0x00000000, -/* 0x0020: unk_mask */ - 0x00000000, -/* 0x0024: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t nvd7_grgpc_code[] = { - 0x03a10ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0xe0f900f8, - 0xf102ffb9, - 0xf09814e7, - 0x21f440e3, - 0x01f7f09d, - 0xf102ffb9, - 0xf09c1ce7, - 0x21f440e3, - 0xf8e0fc9d, -/* 0x03a1: init */ - 0xf104bd00, - 0xf0420017, - 0x11cf0013, - 0x0911e700, - 0x0814b601, - 0xf00014fe, - 0x07f10227, - 0x03f01200, - 0x0002d000, - 0x17f104bd, - 0x10fe0530, - 0x0007f100, - 0x0003f007, - 0xbd0000d0, - 0x0427f004, - 0x040007f1, - 0xd00003f0, - 0x04bd0002, - 0xf11031f4, - 0xf0820027, - 0x22cf0123, - 0x0137f000, - 0xbb1f24f0, - 0x32b60432, - 0x05028001, - 0xf1060380, - 0xf0860027, - 0x22cf0123, - 0x04028000, - 0x0c30e7f1, - 0xbd50e3f0, - 0xbd34bd24, -/* 0x0421: init_unk_loop */ - 0x6821f444, - 0xf400f6b0, - 0xf7f00f0b, - 0x04f2bb01, - 0xb6054ffd, -/* 0x0436: init_unk_next */ - 0x20b60130, - 0x04e0b601, - 0xf40126b0, -/* 0x0442: init_unk_done */ - 0x0380e21b, - 0x08048007, - 0x010027f1, - 0xcf0223f0, - 0x34bd0022, - 0xf1082595, - 0xf0c00007, - 0x05d00103, - 0xf104bd00, - 0xf0c10007, - 0x05d00103, - 0x9804bd00, - 0x0f98000e, - 0x5021f501, - 0x002fbb01, - 0x98003fbb, - 0x0f98010e, - 0x5021f502, - 0x050e9801, - 0xbb00effd, - 0x3ebb002e, - 0x020e9800, - 0xf5030f98, - 0x98015021, - 0xeffd070e, - 0x002ebb00, - 0xb6003ebb, - 0x07f10235, - 0x03f0d300, - 0x0003d001, - 0x25b604bd, - 0x0635b608, - 0xb60120b6, - 0x24b60130, - 0x0834b608, - 0xf5022fb9, - 0xbb02d321, - 0x07f1003f, - 0x03f00100, - 0x0003d002, - 0x24bd04bd, - 0xf11f29f0, - 0xf0080007, - 0x02d00203, -/* 0x04f3: main */ - 0xf404bd00, - 0x28f40031, - 0x24d7f000, - 0xf43921f4, - 0xe4b0f401, - 0x1e18f404, - 0xf00181fe, - 0x20bd0627, - 0xb60412fd, - 0x1efd01e4, - 0x0018fe05, - 0x05e821f5, -/* 0x0523: main_not_ctx_xfer */ - 0x94d30ef4, - 0xf5f010ef, - 0x7e21f501, - 0xc60ef403, -/* 0x0530: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x24d7f02c, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xf00421f4, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x057e: ih_no_fifo */ - 0x07f104bd, - 0x03f00100, - 0x000ad000, - 0xf0fc04bd, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0x0032f480, -/* 0x05a2: hub_barrier_done */ - 0xf7f001f8, - 0x040e9801, - 0xb904febb, - 0xe7f102ff, - 0xe3f09418, - 0x9d21f440, -/* 0x05ba: ctx_redswitch */ - 0xf7f000f8, - 0x0007f120, - 0x0103f085, - 0xbd000fd0, - 0x08e7f004, -/* 0x05cc: ctx_redswitch_delay */ - 0xf401e2b6, - 0xf5f1fd1b, - 0xf5f10800, - 0x07f10200, - 0x03f08500, - 0x000fd001, - 0x00f804bd, -/* 0x05e8: ctx_xfer */ - 0x810007f1, - 0xd00203f0, - 0x04bd000f, - 0xf50711f4, -/* 0x05fb: ctx_xfer_not_load */ - 0xf505ba21, - 0xbd026a21, - 0xfc07f124, - 0x0203f047, - 0xbd0002d0, - 0x012cf004, - 0xf10320b6, - 0xf04afc07, - 0x02d00203, - 0xf004bd00, - 0xa5f001ac, - 0x00b7f102, - 0x50b3f000, - 0xb6040c98, - 0xbcbb0fc4, - 0x000c9800, - 0xf0010d98, - 0x21f500e7, - 0xacf0016f, - 0x00b7f101, - 0x50b3f040, - 0xb6040c98, - 0xbcbb0fc4, - 0x010c9800, - 0x98020d98, - 0xe7f1060f, - 0x21f50800, - 0xacf0016f, - 0x04a5f001, - 0x3000b7f1, - 0x9850b3f0, - 0xc4b6040c, - 0x00bcbb0f, - 0x98020c98, - 0x0f98030d, - 0x00e7f108, - 0x6f21f502, - 0x5e21f501, - 0x0601f402, -/* 0x0697: ctx_xfer_post */ - 0xf50712f4, -/* 0x069b: ctx_xfer_done */ - 0xf5027f21, - 0xf805a221, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3 deleted file mode 100644 index 6b906cd2a31f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3 +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 - -#define CHIPSET GK100 -#include "macros.fuc" - -.section #nve0_grgpc_data -#define INCLUDE_DATA -#include "com.fuc" -#include "gpc.fuc" -#undef INCLUDE_DATA - -.section #nve0_grgpc_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "gpc.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h deleted file mode 100644 index 855b220378f9..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h +++ /dev/null @@ -1,537 +0,0 @@ -uint32_t nve0_grgpc_data[] = { -/* 0x0000: gpc_mmio_list_head */ - 0x0000006c, -/* 0x0004: gpc_mmio_list_tail */ -/* 0x0004: tpc_mmio_list_head */ - 0x0000006c, -/* 0x0008: tpc_mmio_list_tail */ -/* 0x0008: unk_mmio_list_head */ - 0x0000006c, -/* 0x000c: unk_mmio_list_tail */ - 0x0000006c, -/* 0x0010: gpc_id */ - 0x00000000, -/* 0x0014: tpc_count */ - 0x00000000, -/* 0x0018: tpc_mask */ - 0x00000000, -/* 0x001c: unk_count */ - 0x00000000, -/* 0x0020: unk_mask */ - 0x00000000, -/* 0x0024: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t nve0_grgpc_code[] = { - 0x03a10ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0xe0f900f8, - 0xf102ffb9, - 0xf09814e7, - 0x21f440e3, - 0x01f7f09d, - 0xf102ffb9, - 0xf09c1ce7, - 0x21f440e3, - 0xf8e0fc9d, -/* 0x03a1: init */ - 0xf104bd00, - 0xf0420017, - 0x11cf0013, - 0x0911e700, - 0x0814b601, - 0xf00014fe, - 0x07f10227, - 0x03f01200, - 0x0002d000, - 0x17f104bd, - 0x10fe0530, - 0x0007f100, - 0x0003f007, - 0xbd0000d0, - 0x0427f004, - 0x040007f1, - 0xd00003f0, - 0x04bd0002, - 0xf11031f4, - 0xf0820027, - 0x22cf0123, - 0x0137f000, - 0xbb1f24f0, - 0x32b60432, - 0x05028001, - 0xf1060380, - 0xf0860027, - 0x22cf0123, - 0x04028000, - 0x0c30e7f1, - 0xbd50e3f0, - 0xbd34bd24, -/* 0x0421: init_unk_loop */ - 0x6821f444, - 0xf400f6b0, - 0xf7f00f0b, - 0x04f2bb01, - 0xb6054ffd, -/* 0x0436: init_unk_next */ - 0x20b60130, - 0x04e0b601, - 0xf40126b0, -/* 0x0442: init_unk_done */ - 0x0380e21b, - 0x08048007, - 0x010027f1, - 0xcf0223f0, - 0x34bd0022, - 0xf1082595, - 0xf0c00007, - 0x05d00103, - 0xf104bd00, - 0xf0c10007, - 0x05d00103, - 0x9804bd00, - 0x0f98000e, - 0x5021f501, - 0x002fbb01, - 0x98003fbb, - 0x0f98010e, - 0x5021f502, - 0x050e9801, - 0xbb00effd, - 0x3ebb002e, - 0x020e9800, - 0xf5030f98, - 0x98015021, - 0xeffd070e, - 0x002ebb00, - 0xb6003ebb, - 0x07f10235, - 0x03f0d300, - 0x0003d001, - 0x25b604bd, - 0x0635b608, - 0xb60120b6, - 0x24b60130, - 0x0834b608, - 0xf5022fb9, - 0xbb02d321, - 0x07f1003f, - 0x03f00100, - 0x0003d002, - 0x24bd04bd, - 0xf11f29f0, - 0xf0080007, - 0x02d00203, -/* 0x04f3: main */ - 0xf404bd00, - 0x28f40031, - 0x24d7f000, - 0xf43921f4, - 0xe4b0f401, - 0x1e18f404, - 0xf00181fe, - 0x20bd0627, - 0xb60412fd, - 0x1efd01e4, - 0x0018fe05, - 0x05e821f5, -/* 0x0523: main_not_ctx_xfer */ - 0x94d30ef4, - 0xf5f010ef, - 0x7e21f501, - 0xc60ef403, -/* 0x0530: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x24d7f02c, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xf00421f4, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x057e: ih_no_fifo */ - 0x07f104bd, - 0x03f00100, - 0x000ad000, - 0xf0fc04bd, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0x0032f480, -/* 0x05a2: hub_barrier_done */ - 0xf7f001f8, - 0x040e9801, - 0xb904febb, - 0xe7f102ff, - 0xe3f09418, - 0x9d21f440, -/* 0x05ba: ctx_redswitch */ - 0xf7f000f8, - 0x0007f120, - 0x0103f085, - 0xbd000fd0, - 0x08e7f004, -/* 0x05cc: ctx_redswitch_delay */ - 0xf401e2b6, - 0xf5f1fd1b, - 0xf5f10800, - 0x07f10200, - 0x03f08500, - 0x000fd001, - 0x00f804bd, -/* 0x05e8: ctx_xfer */ - 0x810007f1, - 0xd00203f0, - 0x04bd000f, - 0xf50711f4, -/* 0x05fb: ctx_xfer_not_load */ - 0xf505ba21, - 0xbd026a21, - 0xfc07f124, - 0x0203f047, - 0xbd0002d0, - 0x012cf004, - 0xf10320b6, - 0xf04afc07, - 0x02d00203, - 0xf004bd00, - 0xa5f001ac, - 0x00b7f102, - 0x50b3f000, - 0xb6040c98, - 0xbcbb0fc4, - 0x000c9800, - 0xf0010d98, - 0x21f500e7, - 0xacf0016f, - 0x00b7f101, - 0x50b3f040, - 0xb6040c98, - 0xbcbb0fc4, - 0x010c9800, - 0x98020d98, - 0xe7f1060f, - 0x21f50800, - 0xacf0016f, - 0x04a5f001, - 0x3000b7f1, - 0x9850b3f0, - 0xc4b6040c, - 0x00bcbb0f, - 0x98020c98, - 0x0f98030d, - 0x00e7f108, - 0x6f21f502, - 0x5e21f501, - 0x0601f402, -/* 0x0697: ctx_xfer_post */ - 0xf50712f4, -/* 0x069b: ctx_xfer_done */ - 0xf5027f21, - 0xf805a221, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3 deleted file mode 100644 index 90bbe525b626..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3 +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 - -#define CHIPSET GK110 -#include "macros.fuc" - -.section #nvf0_grgpc_data -#define INCLUDE_DATA -#include "com.fuc" -#include "gpc.fuc" -#undef INCLUDE_DATA - -.section #nvf0_grgpc_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "gpc.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h deleted file mode 100644 index 1b803197d28b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h +++ /dev/null @@ -1,537 +0,0 @@ -uint32_t nvf0_grgpc_data[] = { -/* 0x0000: gpc_mmio_list_head */ - 0x0000006c, -/* 0x0004: gpc_mmio_list_tail */ -/* 0x0004: tpc_mmio_list_head */ - 0x0000006c, -/* 0x0008: tpc_mmio_list_tail */ -/* 0x0008: unk_mmio_list_head */ - 0x0000006c, -/* 0x000c: unk_mmio_list_tail */ - 0x0000006c, -/* 0x0010: gpc_id */ - 0x00000000, -/* 0x0014: tpc_count */ - 0x00000000, -/* 0x0018: tpc_mask */ - 0x00000000, -/* 0x001c: unk_count */ - 0x00000000, -/* 0x0020: unk_mask */ - 0x00000000, -/* 0x0024: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t nvf0_grgpc_code[] = { - 0x03a10ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f037, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f037, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x370007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x370007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0xe0f900f8, - 0xf102ffb9, - 0xf09814e7, - 0x21f440e3, - 0x01f7f09d, - 0xf102ffb9, - 0xf09c1ce7, - 0x21f440e3, - 0xf8e0fc9d, -/* 0x03a1: init */ - 0xf104bd00, - 0xf0420017, - 0x11cf0013, - 0x0911e700, - 0x0814b601, - 0xf00014fe, - 0x07f10227, - 0x03f01200, - 0x0002d000, - 0x17f104bd, - 0x10fe0530, - 0x0007f100, - 0x0003f007, - 0xbd0000d0, - 0x0427f004, - 0x040007f1, - 0xd00003f0, - 0x04bd0002, - 0xf11031f4, - 0xf0820027, - 0x22cf0123, - 0x0137f000, - 0xbb1f24f0, - 0x32b60432, - 0x05028001, - 0xf1060380, - 0xf0860027, - 0x22cf0123, - 0x04028000, - 0x0c30e7f1, - 0xbd50e3f0, - 0xbd34bd24, -/* 0x0421: init_unk_loop */ - 0x6821f444, - 0xf400f6b0, - 0xf7f00f0b, - 0x04f2bb01, - 0xb6054ffd, -/* 0x0436: init_unk_next */ - 0x20b60130, - 0x04e0b601, - 0xf40226b0, -/* 0x0442: init_unk_done */ - 0x0380e21b, - 0x08048007, - 0x010027f1, - 0xcf0223f0, - 0x34bd0022, - 0xf1082595, - 0xf0c00007, - 0x05d00103, - 0xf104bd00, - 0xf0c10007, - 0x05d00103, - 0x9804bd00, - 0x0f98000e, - 0x5021f501, - 0x002fbb01, - 0x98003fbb, - 0x0f98010e, - 0x5021f502, - 0x050e9801, - 0xbb00effd, - 0x3ebb002e, - 0x020e9800, - 0xf5030f98, - 0x98015021, - 0xeffd070e, - 0x002ebb00, - 0xb6003ebb, - 0x07f10235, - 0x03f0d300, - 0x0003d001, - 0x25b604bd, - 0x0635b608, - 0xb60120b6, - 0x24b60130, - 0x0834b608, - 0xf5022fb9, - 0xbb02d321, - 0x07f1003f, - 0x03f00100, - 0x0003d002, - 0x24bd04bd, - 0xf11f29f0, - 0xf0300007, - 0x02d00203, -/* 0x04f3: main */ - 0xf404bd00, - 0x28f40031, - 0x24d7f000, - 0xf43921f4, - 0xe4b0f401, - 0x1e18f404, - 0xf00181fe, - 0x20bd0627, - 0xb60412fd, - 0x1efd01e4, - 0x0018fe05, - 0x05e821f5, -/* 0x0523: main_not_ctx_xfer */ - 0x94d30ef4, - 0xf5f010ef, - 0x7e21f501, - 0xc60ef403, -/* 0x0530: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x24d7f02c, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xf00421f4, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x057e: ih_no_fifo */ - 0x07f104bd, - 0x03f00100, - 0x000ad000, - 0xf0fc04bd, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0x0032f480, -/* 0x05a2: hub_barrier_done */ - 0xf7f001f8, - 0x040e9801, - 0xb904febb, - 0xe7f102ff, - 0xe3f09418, - 0x9d21f440, -/* 0x05ba: ctx_redswitch */ - 0xf7f000f8, - 0x0007f120, - 0x0103f085, - 0xbd000fd0, - 0x08e7f004, -/* 0x05cc: ctx_redswitch_delay */ - 0xf401e2b6, - 0xf5f1fd1b, - 0xf5f10800, - 0x07f10200, - 0x03f08500, - 0x000fd001, - 0x00f804bd, -/* 0x05e8: ctx_xfer */ - 0x810007f1, - 0xd00203f0, - 0x04bd000f, - 0xf50711f4, -/* 0x05fb: ctx_xfer_not_load */ - 0xf505ba21, - 0xbd026a21, - 0xfc07f124, - 0x0203f047, - 0xbd0002d0, - 0x012cf004, - 0xf10320b6, - 0xf04afc07, - 0x02d00203, - 0xf004bd00, - 0xa5f001ac, - 0x00b7f102, - 0x50b3f000, - 0xb6040c98, - 0xbcbb0fc4, - 0x000c9800, - 0xf0010d98, - 0x21f500e7, - 0xacf0016f, - 0x00b7f101, - 0x50b3f040, - 0xb6040c98, - 0xbcbb0fc4, - 0x010c9800, - 0x98020d98, - 0xe7f1060f, - 0x21f50800, - 0xacf0016f, - 0x04a5f001, - 0x3000b7f1, - 0x9850b3f0, - 0xc4b6040c, - 0x00bcbb0f, - 0x98020c98, - 0x0f98030d, - 0x00e7f108, - 0x6f21f502, - 0x5e21f501, - 0x0601f402, -/* 0x0697: ctx_xfer_post */ - 0xf50712f4, -/* 0x069b: ctx_xfer_done */ - 0xf5027f21, - 0xf805a221, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc deleted file mode 100644 index b4ad18bf5a26..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc +++ /dev/null @@ -1,696 +0,0 @@ -/* fuc microcode for nvc0 PGRAPH/HUB - * - * Copyright 2011 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifdef INCLUDE_DATA -hub_mmio_list_head: .b32 #hub_mmio_list_base -hub_mmio_list_tail: .b32 #hub_mmio_list_next - -gpc_count: .b32 0 -rop_count: .b32 0 -cmd_queue: queue_init - -ctx_current: .b32 0 - -.align 256 -chan_data: -chan_mmio_count: .b32 0 -chan_mmio_address: .b32 0 - -.align 256 -xfer_data: .skip 256 - -hub_mmio_list_base: -.b32 0x0417e91c // 0x17e91c, 2 -hub_mmio_list_next: -#endif - -#ifdef INCLUDE_CODE -// reports an exception to the host -// -// In: $r15 error code (see os.h) -// -error: - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) - mov $r15 1 - nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15) - ret - -// HUB fuc initialisation, executed by triggering ucode start, will -// fall through to main loop after completion. -// -// Output: -// CC_SCRATCH[0]: -// 31:31: set to signal completion -// CC_SCRATCH[1]: -// 31:0: total PGRAPH context size -// -init: - clear b32 $r0 - mov $xdbase $r0 - - // setup stack - nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0) - extr $r1 $r1 9:17 - shl b32 $r1 8 - mov $sp $r1 - - // enable fifo access - mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO - nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2) - - // setup i0 handler, and route all interrupts to it - mov $r1 #ih - mov $iv0 $r1 - - clear b32 $r2 - nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2) - - // route HUB_CHSW_PULSE to fuc interrupt 8 - mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8 - nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2) - - // not sure what these are, route them because NVIDIA does, and - // the IRQ handler will signal the host if we ever get one.. we - // may find out if/why we need to handle these if so.. - // - mov $r2 0x2004 // { 0x04, ZERO } -> intr 9 - nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2) - mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10 - nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2) - mov $r2 0x200c // { 0x0c, ZERO } -> intr 15 - nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2) - - // enable all INTR_UP interrupts - sub b32 $r3 $r0 1 - nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3) - - // enable fifo, ctxsw, 9, fwmthd, 15 interrupts - imm32($r2, 0x8704) - nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2) - - // fifo level triggered, rest edge - mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL - nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2) - - // enable interrupts - bset $flags ie0 - - // fetch enabled GPC/ROP counts - nv_rd32($r14, 0x409604) - extr $r1 $r15 16:20 - st b32 D[$r0 + #rop_count] $r1 - and $r15 0x1f - st b32 D[$r0 + #gpc_count] $r15 - - // set BAR_REQMASK to GPC mask - mov $r1 1 - shl b32 $r1 $r15 - sub b32 $r1 1 - nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1) - nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1) - - // context size calculation, reserve first 256 bytes for use by fuc - mov $r1 256 - - // - mov $r15 2 - call(ctx_4170s) - call(ctx_4170w) - mov $r15 0x10 - call(ctx_86c) - - // calculate size of mmio context data - ld b32 $r14 D[$r0 + #hub_mmio_list_head] - ld b32 $r15 D[$r0 + #hub_mmio_list_tail] - call(mmctx_size) - - // set mmctx base addresses now so we don't have to do it later, - // they don't (currently) ever change - shr b32 $r4 $r1 8 - nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4) - nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4) - add b32 $r3 0x1300 - add b32 $r1 $r15 - shr b32 $r15 2 - nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf?? - - // strands, base offset needs to be aligned to 256 bytes - shr b32 $r1 8 - add b32 $r1 1 - shl b32 $r1 8 - mov b32 $r15 $r1 - call(strand_ctx_init) - add b32 $r1 $r15 - - // initialise each GPC in sequence by passing in the offset of its - // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which - // has previously been uploaded by the host) running. - // - // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31 - // when it has completed, and return the size of its context data - // in GPCn_CC_SCRATCH[1] - // - ld b32 $r3 D[$r0 + #gpc_count] - imm32($r4, 0x502000) - init_gpc: - // setup, and start GPC ucode running - add b32 $r14 $r4 0x804 - mov b32 $r15 $r1 - call(nv_wr32) // CC_SCRATCH[1] = ctx offset - add b32 $r14 $r4 0x10c - clear b32 $r15 - call(nv_wr32) - add b32 $r14 $r4 0x104 - call(nv_wr32) // ENTRY - add b32 $r14 $r4 0x100 - mov $r15 2 // CTRL_START_TRIGGER - call(nv_wr32) // CTRL - - // wait for it to complete, and adjust context size - add b32 $r14 $r4 0x800 - init_gpc_wait: - call(nv_rd32) - xbit $r15 $r15 31 - bra e #init_gpc_wait - add b32 $r14 $r4 0x804 - call(nv_rd32) - add b32 $r1 $r15 - - // next! - add b32 $r4 0x8000 - sub b32 $r3 1 - bra ne #init_gpc - - // - mov $r15 0 - call(ctx_86c) - mov $r15 0 - call(ctx_4170s) - - // save context size, and tell host we're ready - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) - clear b32 $r1 - bset $r1 31 - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1) - -// Main program loop, very simple, sleeps until woken up by the interrupt -// handler, pulls a command from the queue and executes its handler -// -main: - // sleep until we have something to do - bset $flags $p0 - sleep $p0 - mov $r13 #cmd_queue - call(queue_get) - bra $p1 #main - - // context switch, requested by GPU? - cmpu b32 $r14 0x4001 - bra ne #main_not_ctx_switch - trace_set(T_AUTO) - nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0) - nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0) - - xbit $r3 $r1 31 - bra e #chsw_no_prev - xbit $r3 $r2 31 - bra e #chsw_prev_no_next - push $r2 - mov b32 $r2 $r1 - trace_set(T_SAVE) - bclr $flags $p1 - bset $flags $p2 - call(ctx_xfer) - trace_clr(T_SAVE); - pop $r2 - trace_set(T_LOAD); - bset $flags $p1 - call(ctx_xfer) - trace_clr(T_LOAD); - bra #chsw_done - chsw_prev_no_next: - push $r2 - mov b32 $r2 $r1 - bclr $flags $p1 - bclr $flags $p2 - call(ctx_xfer) - pop $r2 - nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) - bra #chsw_done - chsw_no_prev: - xbit $r3 $r2 31 - bra e #chsw_done - bset $flags $p1 - bclr $flags $p2 - call(ctx_xfer) - - // ack the context switch request - chsw_done: - mov $r2 NV_PGRAPH_FECS_CHSW_ACK - nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2) - trace_clr(T_AUTO) - bra #main - - // request to set current channel? (*not* a context switch) - main_not_ctx_switch: - cmpu b32 $r14 0x0001 - bra ne #main_not_ctx_chan - mov b32 $r2 $r15 - call(ctx_chan) - bra #main_done - - // request to store current channel context? - main_not_ctx_chan: - cmpu b32 $r14 0x0002 - bra ne #main_not_ctx_save - trace_set(T_SAVE) - bclr $flags $p1 - bclr $flags $p2 - call(ctx_xfer) - trace_clr(T_SAVE) - bra #main_done - - main_not_ctx_save: - shl b32 $r15 $r14 16 - or $r15 E_BAD_COMMAND - call(error) - bra #main - - main_done: - clear b32 $r2 - bset $r2 31 - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2) - bra #main - -// interrupt handler -ih: - push $r8 - mov $r8 $flags - push $r8 - push $r9 - push $r10 - push $r11 - push $r13 - push $r14 - push $r15 - clear b32 $r0 - - // incoming fifo command? - nv_iord($r10, NV_PGRAPH_FECS_INTR, 0) - and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO - bra e #ih_no_fifo - // queue incoming fifo command for later processing - mov $r13 #cmd_queue - nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0) - nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0) - call(queue_put) - add b32 $r11 0x400 - mov $r14 1 - nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14) - - // context switch request? - ih_no_fifo: - and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW - bra e #ih_no_ctxsw - // enqueue a context switch for later processing - mov $r13 #cmd_queue - mov $r14 0x4001 - call(queue_put) - - // firmware method? - ih_no_ctxsw: - and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD - bra e #ih_no_fwmthd - // none we handle; report to host and ack - nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO) - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15) - nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR) - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15) - extr $r14 $r15 16:18 - shl b32 $r14 $r14 2 - imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0)) - add b32 $r14 $r15 - call(nv_rd32) - nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15) - mov $r15 E_BAD_FWMTHD - call(error) - mov $r11 0x100 - nv_wr32(0x400144, $r11) - - // anything we didn't handle, bring it to the host's attention - ih_no_fwmthd: - mov $r11 0x504 // FIFO | CHSW | FWMTHD - not b32 $r11 - and $r11 $r10 $r11 - bra e #ih_no_other - nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11) - - // ack, and wake up main() - ih_no_other: - nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10) - - pop $r15 - pop $r14 - pop $r13 - pop $r11 - pop $r10 - pop $r9 - pop $r8 - mov $flags $r8 - pop $r8 - bclr $flags $p0 - iret - -#if CHIPSET < GK100 -// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done -ctx_4160s: - mov $r15 1 - nv_wr32(0x404160, $r15) - ctx_4160s_wait: - nv_rd32($r15, 0x404160) - xbit $r15 $r15 4 - bra e #ctx_4160s_wait - ret - -// Without clearing again at end of xfer, some things cause PGRAPH -// to hang with STATUS=0x00000007 until it's cleared.. fbcon can -// still function with it set however... -ctx_4160c: - clear b32 $r15 - nv_wr32(0x404160, $r15) - ret -#endif - -// Again, not real sure -// -// In: $r15 value to set 0x404170 to -// -ctx_4170s: - or $r15 0x10 - nv_wr32(0x404170, $r15) - ret - -// Waits for a ctx_4170s() call to complete -// -ctx_4170w: - nv_rd32($r15, 0x404170) - and $r15 0x10 - bra ne #ctx_4170w - ret - -// Disables various things, waits a bit, and re-enables them.. -// -// Not sure how exactly this helps, perhaps "ENABLE" is not such a -// good description for the bits we turn off? Anyways, without this, -// funny things happen. -// -ctx_redswitch: - mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC - or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP - or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC - or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN - nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) - mov $r15 8 - ctx_redswitch_delay: - sub b32 $r15 1 - bra ne #ctx_redswitch_delay - or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP - or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN - nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) - ret - -// Not a clue what this is for, except that unless the value is 0x10, the -// strand context is saved (and presumably restored) incorrectly.. -// -// In: $r15 value to set to (0x00/0x10 are used) -// -ctx_86c: - nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15) - nv_wr32(0x408a14, $r15) - nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15) - ret - -// In: $r15 NV_PGRAPH_FECS_MEM_CMD_* -ctx_mem: - nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15) - ctx_mem_wait: - nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0) - or $r15 $r15 - bra ne #ctx_mem_wait - ret - -// ctx_load - load's a channel's ctxctl data, and selects its vm -// -// In: $r2 channel address -// -ctx_load: - trace_set(T_CHAN) - - // switch to channel, somewhat magic in parts.. - mov $r10 12 // DONE_UNK12 - call(wait_donez) - clear b32 $r15 - nv_iowr(0x409a24, 0, $r15) - nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2) - nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2) - mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN - call(ctx_mem) - nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) - - // load channel header, fetch PGRAPH context pointer - mov $xtargets $r0 - bclr $r2 31 - shl b32 $r2 4 - add b32 $r2 2 - - trace_set(T_LCHAN) - nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2) - imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31) - or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM - nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) - mov $r1 0x10 // chan + 0x0210 - mov $r2 #xfer_data - sethi $r2 0x00020000 // 16 bytes - xdld $r1 $r2 - xdwait - trace_clr(T_LCHAN) - - // update current context - ld b32 $r1 D[$r0 + #xfer_data + 4] - shl b32 $r1 24 - ld b32 $r2 D[$r0 + #xfer_data + 0] - shr b32 $r2 8 - or $r1 $r2 - st b32 D[$r0 + #ctx_current] $r1 - - // set transfer base to start of context, and fetch context header - trace_set(T_LCTXH) - nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1) - mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM - nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) - mov $r1 #chan_data - sethi $r1 0x00060000 // 256 bytes - xdld $r0 $r1 - xdwait - trace_clr(T_LCTXH) - - trace_clr(T_CHAN) - ret - -// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as -// the active channel for ctxctl, but not actually transfer -// any context data. intended for use only during initial -// context construction. -// -// In: $r2 channel address -// -ctx_chan: -#if CHIPSET < GK100 - call(ctx_4160s) -#endif - call(ctx_load) - mov $r10 12 // DONE_UNK12 - call(wait_donez) - mov $r15 5 // MEM_CMD 5 ??? - call(ctx_mem) -#if CHIPSET < GK100 - call(ctx_4160c) -#endif - ret - -// Execute per-context state overrides list -// -// Only executed on the first load of a channel. Might want to look into -// removing this and having the host directly modify the channel's context -// to change this state... The nouveau DRM already builds this list as -// it's definitely needed for NVIDIA's, so we may as well use it for now -// -// Input: $r1 mmio list length -// -ctx_mmio_exec: - // set transfer base to be the mmio list - ld b32 $r3 D[$r0 + #chan_mmio_address] - nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) - - clear b32 $r3 - ctx_mmio_loop: - // fetch next 256 bytes of mmio list if necessary - and $r4 $r3 0xff - bra ne #ctx_mmio_pull - mov $r5 #xfer_data - sethi $r5 0x00060000 // 256 bytes - xdld $r3 $r5 - xdwait - - // execute a single list entry - ctx_mmio_pull: - ld b32 $r14 D[$r4 + #xfer_data + 0x00] - ld b32 $r15 D[$r4 + #xfer_data + 0x04] - call(nv_wr32) - - // next! - add b32 $r3 8 - sub b32 $r1 1 - bra ne #ctx_mmio_loop - - // set transfer base back to the current context - ctx_mmio_done: - ld b32 $r3 D[$r0 + #ctx_current] - nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) - - // disable the mmio list now, we don't need/want to execute it again - st b32 D[$r0 + #chan_mmio_count] $r0 - mov $r1 #chan_data - sethi $r1 0x00060000 // 256 bytes - xdst $r0 $r1 - xdwait - ret - -// Transfer HUB context data between GPU and storage area -// -// In: $r2 channel address -// $p1 clear on save, set on load -// $p2 set if opposite direction done/will be done, so: -// on save it means: "a load will follow this save" -// on load it means: "a save preceeded this load" -// -ctx_xfer: - // according to mwk, some kind of wait for idle - mov $r14 4 - nv_iowr(0x409c08, 0, $r14) - ctx_xfer_idle: - nv_iord($r14, 0x409c00, 0) - and $r14 0x2000 - bra ne #ctx_xfer_idle - - bra not $p1 #ctx_xfer_pre - bra $p2 #ctx_xfer_pre_load - ctx_xfer_pre: - mov $r15 0x10 - call(ctx_86c) -#if CHIPSET < GK100 - call(ctx_4160s) -#endif - bra not $p1 #ctx_xfer_exec - - ctx_xfer_pre_load: - mov $r15 2 - call(ctx_4170s) - call(ctx_4170w) - call(ctx_redswitch) - clear b32 $r15 - call(ctx_4170s) - call(ctx_load) - - // fetch context pointer, and initiate xfer on all GPCs - ctx_xfer_exec: - ld b32 $r1 D[$r0 + #ctx_current] - - clear b32 $r2 - nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2) - - nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer - xbit $r15 $flags $p1 - xbit $r2 $flags $p2 - shl b32 $r2 1 - or $r15 $r2 - nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) - - // strands - call(strand_pre) - clear b32 $r2 - nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2) - xbit $r2 $flags $p1 // SAVE/LOAD - add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE - nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2) - - // mmio context - xbit $r10 $flags $p1 // direction - or $r10 6 // first, last - mov $r11 0 // base = 0 - ld b32 $r12 D[$r0 + #hub_mmio_list_head] - ld b32 $r13 D[$r0 + #hub_mmio_list_tail] - mov $r14 0 // not multi - call(mmctx_xfer) - - // wait for GPCs to all complete - mov $r10 8 // DONE_BAR - call(wait_doneo) - - // wait for strand xfer to complete - call(strand_wait) - - // post-op - bra $p1 #ctx_xfer_post - mov $r10 12 // DONE_UNK12 - call(wait_donez) - mov $r15 5 // MEM_CMD 5 ??? - call(ctx_mem) - - bra $p2 #ctx_xfer_done - ctx_xfer_post: - mov $r15 2 - call(ctx_4170s) - clear b32 $r15 - call(ctx_86c) - call(strand_post) - call(ctx_4170w) - clear b32 $r15 - call(ctx_4170s) - - bra not $p1 #ctx_xfer_no_post_mmio - ld b32 $r1 D[$r0 + #chan_mmio_count] - or $r1 $r1 - bra e #ctx_xfer_no_post_mmio - call(ctx_mmio_exec) - - ctx_xfer_no_post_mmio: -#if CHIPSET < GK100 - call(ctx_4160c) -#endif - - ctx_xfer_done: - ret -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5 deleted file mode 100644 index 27591b3086a5..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5 +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define CHIPSET GK208 -#include "macros.fuc" - -.section #gm107_grhub_data -#define INCLUDE_DATA -#include "com.fuc" -#include "hub.fuc" -#undef INCLUDE_DATA - -.section #gm107_grhub_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "hub.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h deleted file mode 100644 index 5f953c5c20b7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h +++ /dev/null @@ -1,916 +0,0 @@ -uint32_t gm107_grhub_data[] = { -/* 0x0000: hub_mmio_list_head */ - 0x00000300, -/* 0x0004: hub_mmio_list_tail */ - 0x00000304, -/* 0x0008: gpc_count */ - 0x00000000, -/* 0x000c: rop_count */ - 0x00000000, -/* 0x0010: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: ctx_current */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: chan_data */ -/* 0x0100: chan_mmio_count */ - 0x00000000, -/* 0x0104: chan_mmio_address */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0200: xfer_data */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0300: hub_mmio_list_base */ - 0x0417e91c, -}; - -uint32_t gm107_grhub_code[] = { - 0x030e0ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0xf489a408, - 0x020f0b1b, - 0x0002f87e, -/* 0x001a: queue_put_next */ - 0x98c400f8, - 0x0384b607, - 0xb6008dbb, - 0x8eb50880, - 0x018fb500, - 0xf00190b6, - 0xd9b50f94, -/* 0x0037: queue_get */ - 0xf400f801, - 0xd8980131, - 0x01d99800, - 0x0bf489a4, - 0x0789c421, - 0xbb0394b6, - 0x90b6009d, - 0x009e9808, - 0xb6019f98, - 0x84f00180, - 0x00d8b50f, -/* 0x0063: queue_get_done */ - 0xf80132f4, -/* 0x0065: nv_rd32 */ - 0xf0ecb200, - 0x00801fc9, - 0x0cf601ca, -/* 0x0073: nv_rd32_wait */ - 0x8c04bd00, - 0xcf01ca00, - 0xccc800cc, - 0xf61bf41f, - 0xec7e060a, - 0x008f0000, - 0xffcf01cb, -/* 0x008f: nv_wr32 */ - 0x8000f800, - 0xf601cc00, - 0x04bd000f, - 0xc9f0ecb2, - 0x1ec9f01f, - 0x01ca0080, - 0xbd000cf6, -/* 0x00a9: nv_wr32_wait */ - 0xca008c04, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f61b, -/* 0x00b8: wait_donez */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x00cf: wait_donez_ne */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf61bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x00ec: wait_doneo */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x0103: wait_doneo_e */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf60bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x0120: mmctx_size */ -/* 0x0122: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0x1bf4efa4, - 0xf89fb2ec, -/* 0x013d: mmctx_xfer */ - 0xf094bd00, - 0x00800199, - 0x09f60237, - 0xbd04bd00, - 0x05bbfd94, - 0x800f0bf4, - 0xf601c400, - 0x04bd000b, -/* 0x015f: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0xc6008018, - 0x000ef601, - 0x008004bd, - 0x0ff601c7, - 0xf004bd00, -/* 0x017a: mmctx_multi_disabled */ - 0xabc80199, - 0x10b4b600, - 0xc80cb9f0, - 0xe4b601ae, - 0x05befd11, - 0x01c50080, - 0xbd000bf6, -/* 0x0195: mmctx_exec_loop */ -/* 0x0195: mmctx_wait_free */ - 0xc5008e04, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f60b, - 0x05e9fd00, - 0x01c80080, - 0xbd000ef6, - 0x04c0b604, - 0x1bf4cda4, - 0x02abc8df, -/* 0x01bf: mmctx_fini_wait */ - 0x8b1c1bf4, - 0xcf01c500, - 0xb4f000bb, - 0x10b4b01f, - 0x0af31bf4, - 0x00b87e05, - 0x250ef400, -/* 0x01d8: mmctx_stop */ - 0xb600abc8, - 0xb9f010b4, - 0x12b9f00c, - 0x01c50080, - 0xbd000bf6, -/* 0x01ed: mmctx_stop_wait */ - 0xc5008b04, - 0x00bbcf01, - 0xf412bbc8, -/* 0x01fa: mmctx_done */ - 0x94bdf61b, - 0x800199f0, - 0xf6021700, - 0x04bd0009, -/* 0x020a: strand_wait */ - 0xa0f900f8, - 0xb87e020a, - 0xa0fc0000, -/* 0x0216: strand_pre */ - 0x0c0900f8, - 0x024afc80, - 0xbd0009f6, - 0x020a7e04, -/* 0x0227: strand_post */ - 0x0900f800, - 0x4afc800d, - 0x0009f602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0238: strand_set */ - 0xfc800f0c, - 0x0cf6024f, - 0x0c04bd00, - 0x4afc800b, - 0x000cf602, - 0xfc8004bd, - 0x0ef6024f, - 0x0c04bd00, - 0x4afc800a, - 0x000cf602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0268: strand_ctx_init */ - 0x99f094bd, - 0x37008003, - 0x0009f602, - 0x167e04bd, - 0x030e0002, - 0x0002387e, - 0xfc80c4bd, - 0x0cf60247, - 0x0c04bd00, - 0x4afc8001, - 0x000cf602, - 0x0a7e04bd, - 0x0c920002, - 0x46fc8001, - 0x000cf602, - 0x020c04bd, - 0x024afc80, - 0xbd000cf6, - 0x020a7e04, - 0x02277e00, - 0x42008800, - 0x20008902, - 0x0099cf02, -/* 0x02c7: ctx_init_strand_loop */ - 0xf608fe95, - 0x8ef6008e, - 0x808acf40, - 0xb606a5b6, - 0xeabb01a0, - 0x0480b600, - 0xf40192b6, - 0xe4b6e81b, - 0xf2efbc08, - 0x99f094bd, - 0x17008003, - 0x0009f602, - 0x00f804bd, -/* 0x02f8: error */ - 0x02050080, - 0xbd000ff6, - 0x80010f04, - 0xf6030700, - 0x04bd000f, -/* 0x030e: init */ - 0x04bd00f8, - 0x410007fe, - 0x11cf4200, - 0x0911e700, - 0x0814b601, - 0x020014fe, - 0x12004002, - 0xbd0002f6, - 0x05c94104, - 0xbd0010fe, - 0x07004024, - 0xbd0002f6, - 0x20034204, - 0x01010080, - 0xbd0002f6, - 0x20044204, - 0x01010480, - 0xbd0002f6, - 0x200b4204, - 0x01010880, - 0xbd0002f6, - 0x200c4204, - 0x01011c80, - 0xbd0002f6, - 0x01039204, - 0x03090080, - 0xbd0003f6, - 0x87044204, - 0xf6040040, - 0x04bd0002, - 0x00400402, - 0x0002f603, - 0x31f404bd, - 0x96048e10, - 0x00657e40, - 0xc7feb200, - 0x01b590f1, - 0x1ff4f003, - 0x01020fb5, - 0x041fbb01, - 0x800112b6, - 0xf6010300, - 0x04bd0001, - 0x01040080, - 0xbd0001f6, - 0x01004104, - 0xa87e020f, - 0xb77e0006, - 0x100f0006, - 0x0006f97e, - 0x98000e98, - 0x207e010f, - 0x14950001, - 0xc0008008, - 0x0004f601, - 0x008004bd, - 0x04f601c1, - 0xb704bd00, - 0xbb130030, - 0xf5b6001f, - 0xd3008002, - 0x000ff601, - 0x15b604bd, - 0x0110b608, - 0xb20814b6, - 0x02687e1f, - 0x001fbb00, - 0x84020398, -/* 0x041f: init_gpc */ - 0xb8502000, - 0x0008044e, - 0x8f7e1fb2, - 0x4eb80000, - 0xbd00010c, - 0x008f7ef4, - 0x044eb800, - 0x8f7e0001, - 0x4eb80000, - 0x0f000100, - 0x008f7e02, - 0x004eb800, -/* 0x044e: init_gpc_wait */ - 0x657e0008, - 0xffc80000, - 0xf90bf41f, - 0x08044eb8, - 0x00657e00, - 0x001fbb00, - 0x800040b7, - 0xf40132b6, - 0x000fb41b, - 0x0006f97e, - 0xa87e000f, - 0x00800006, - 0x01f60201, - 0xbd04bd00, - 0x1f19f014, - 0x02300080, - 0xbd0001f6, -/* 0x0491: main */ - 0x0031f404, - 0x0d0028f4, - 0x00377e10, - 0xf401f400, - 0x4001e4b1, - 0x00c71bf5, - 0x99f094bd, - 0x37008004, - 0x0009f602, - 0x008104bd, - 0x11cf02c0, - 0xc1008200, - 0x0022cf02, - 0xf41f13c8, - 0x23c8770b, - 0x550bf41f, - 0x12b220f9, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0231f401, - 0x00087c7e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x20fc04bd, - 0x99f094bd, - 0x37008006, - 0x0009f602, - 0x31f404bd, - 0x087c7e01, - 0xf094bd00, - 0x00800699, - 0x09f60217, - 0xf404bd00, -/* 0x0522: chsw_prev_no_next */ - 0x20f92f0e, - 0x32f412b2, - 0x0232f401, - 0x00087c7e, - 0x008020fc, - 0x02f602c0, - 0xf404bd00, -/* 0x053e: chsw_no_prev */ - 0x23c8130e, - 0x0d0bf41f, - 0xf40131f4, - 0x7c7e0232, -/* 0x054e: chsw_done */ - 0x01020008, - 0x02c30080, - 0xbd0002f6, - 0xf094bd04, - 0x00800499, - 0x09f60217, - 0xf504bd00, -/* 0x056b: main_not_ctx_switch */ - 0xb0ff2a0e, - 0x1bf401e4, - 0x7ef2b20c, - 0xf400081c, -/* 0x057a: main_not_ctx_chan */ - 0xe4b0400e, - 0x2c1bf402, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0232f401, - 0x00087c7e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x0ef404bd, -/* 0x05a9: main_not_ctx_save */ - 0x10ef9411, - 0x7e01f5f0, - 0xf50002f8, -/* 0x05b7: main_done */ - 0xbdfede0e, - 0x1f29f024, - 0x02300080, - 0xbd0002f6, - 0xcc0ef504, -/* 0x05c9: ih */ - 0xfe80f9fe, - 0x80f90188, - 0xa0f990f9, - 0xd0f9b0f9, - 0xf0f9e0f9, - 0x004a04bd, - 0x00aacf02, - 0xf404abc4, - 0x100d230b, - 0xcf1a004e, - 0x004f00ee, - 0x00ffcf19, - 0x0000047e, - 0x0400b0b7, - 0x0040010e, - 0x000ef61d, -/* 0x060a: ih_no_fifo */ - 0xabe404bd, - 0x0bf40100, - 0x4e100d0c, - 0x047e4001, -/* 0x061a: ih_no_ctxsw */ - 0xabe40000, - 0x0bf40400, - 0x07088e56, - 0x00657e40, - 0x80ffb200, - 0xf6020400, - 0x04bd000f, - 0x4007048e, - 0x0000657e, - 0x0080ffb2, - 0x0ff60203, - 0xc704bd00, - 0xee9450fe, - 0x07008f02, - 0x00efbb40, - 0x0000657e, - 0x02020080, - 0xbd000ff6, - 0x7e030f04, - 0x4b0002f8, - 0xbfb20100, - 0x4001448e, - 0x00008f7e, -/* 0x0674: ih_no_fwmthd */ - 0xbd05044b, - 0xb4abffb0, - 0x800c0bf4, - 0xf6030700, - 0x04bd000b, -/* 0x0688: ih_no_other */ - 0xf6010040, - 0x04bd000a, - 0xe0fcf0fc, - 0xb0fcd0fc, - 0x90fca0fc, - 0x88fe80fc, - 0xf480fc00, - 0x01f80032, -/* 0x06a8: ctx_4170s */ - 0xb210f5f0, - 0x41708eff, - 0x008f7e40, -/* 0x06b7: ctx_4170w */ - 0x8e00f800, - 0x7e404170, - 0xb2000065, - 0x10f4f0ff, - 0xf8f31bf4, -/* 0x06c9: ctx_redswitch */ - 0x02004e00, - 0xf040e5f0, - 0xe5f020e5, - 0x85008010, - 0x000ef601, - 0x080f04bd, -/* 0x06e0: ctx_redswitch_delay */ - 0xf401f2b6, - 0xe5f1fd1b, - 0xe5f10400, - 0x00800100, - 0x0ef60185, - 0xf804bd00, -/* 0x06f9: ctx_86c */ - 0x23008000, - 0x000ff602, - 0xffb204bd, - 0x408a148e, - 0x00008f7e, - 0x8c8effb2, - 0x8f7e41a8, - 0x00f80000, -/* 0x0718: ctx_mem */ - 0x02840080, - 0xbd000ff6, -/* 0x0721: ctx_mem_wait */ - 0x84008f04, - 0x00ffcf02, - 0xf405fffd, - 0x00f8f61b, -/* 0x0730: ctx_load */ - 0x99f094bd, - 0x37008005, - 0x0009f602, - 0x0c0a04bd, - 0x0000b87e, - 0x0080f4bd, - 0x0ff60289, - 0x8004bd00, - 0xf602c100, - 0x04bd0002, - 0x02830080, - 0xbd0002f6, - 0x7e070f04, - 0x80000718, - 0xf602c000, - 0x04bd0002, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x99f094bd, - 0x37008008, - 0x0009f602, - 0x008004bd, - 0x02f60281, - 0xd204bd00, - 0x80000000, - 0x800225f0, - 0xf6028800, - 0x04bd0002, - 0x00421001, - 0x0223f002, - 0xf80512fa, - 0xf094bd03, - 0x00800899, - 0x09f60217, - 0x9804bd00, - 0x14b68101, - 0x80029818, - 0xfd0825b6, - 0x01b50512, - 0xf094bd16, - 0x00800999, - 0x09f60237, - 0x8004bd00, - 0xf6028100, - 0x04bd0001, - 0x00800102, - 0x02f60288, - 0x4104bd00, - 0x13f00100, - 0x0501fa06, - 0x94bd03f8, - 0x800999f0, - 0xf6021700, - 0x04bd0009, - 0x99f094bd, - 0x17008005, - 0x0009f602, - 0x00f804bd, -/* 0x081c: ctx_chan */ - 0x0007307e, - 0xb87e0c0a, - 0x050f0000, - 0x0007187e, -/* 0x082e: ctx_mmio_exec */ - 0x039800f8, - 0x81008041, - 0x0003f602, - 0x34bd04bd, -/* 0x083c: ctx_mmio_loop */ - 0xf4ff34c4, - 0x00450e1b, - 0x0653f002, - 0xf80535fa, -/* 0x084d: ctx_mmio_pull */ - 0x804e9803, - 0x7e814f98, - 0xb600008f, - 0x12b60830, - 0xdf1bf401, -/* 0x0860: ctx_mmio_done */ - 0x80160398, - 0xf6028100, - 0x04bd0003, - 0x414000b5, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x087c: ctx_xfer */ - 0x0080040e, - 0x0ef60302, -/* 0x0887: ctx_xfer_idle */ - 0x8e04bd00, - 0xcf030000, - 0xe4f100ee, - 0x1bf42000, - 0x0611f4f5, -/* 0x089b: ctx_xfer_pre */ - 0x0f0c02f4, - 0x06f97e10, - 0x1b11f400, -/* 0x08a4: ctx_xfer_pre_load */ - 0xa87e020f, - 0xb77e0006, - 0xc97e0006, - 0xf4bd0006, - 0x0006a87e, - 0x0007307e, -/* 0x08bc: ctx_xfer_exec */ - 0xbd160198, - 0x05008024, - 0x0002f601, - 0x1fb204bd, - 0x41a5008e, - 0x00008f7e, - 0xf001fcf0, - 0x24b6022c, - 0x05f2fd01, - 0x048effb2, - 0x8f7e41a5, - 0x167e0000, - 0x24bd0002, - 0x0247fc80, - 0xbd0002f6, - 0x012cf004, - 0x800320b6, - 0xf6024afc, - 0x04bd0002, - 0xf001acf0, - 0x000b06a5, - 0x98000c98, - 0x000e010d, - 0x00013d7e, - 0xec7e080a, - 0x0a7e0000, - 0x01f40002, - 0x7e0c0a12, - 0x0f0000b8, - 0x07187e05, - 0x2d02f400, -/* 0x0938: ctx_xfer_post */ - 0xa87e020f, - 0xf4bd0006, - 0x0006f97e, - 0x0002277e, - 0x0006b77e, - 0xa87ef4bd, - 0x11f40006, - 0x40019810, - 0xf40511fd, - 0x2e7e070b, -/* 0x0962: ctx_xfer_no_post_mmio */ -/* 0x0962: ctx_xfer_done */ - 0x00f80008, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5 deleted file mode 100644 index 7c5d25630fa8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5 +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define CHIPSET GK208 -#include "macros.fuc" - -.section #nv108_grhub_data -#define INCLUDE_DATA -#include "com.fuc" -#include "hub.fuc" -#undef INCLUDE_DATA - -.section #nv108_grhub_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "hub.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h deleted file mode 100644 index e49b5a877ae4..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h +++ /dev/null @@ -1,916 +0,0 @@ -uint32_t nv108_grhub_data[] = { -/* 0x0000: hub_mmio_list_head */ - 0x00000300, -/* 0x0004: hub_mmio_list_tail */ - 0x00000304, -/* 0x0008: gpc_count */ - 0x00000000, -/* 0x000c: rop_count */ - 0x00000000, -/* 0x0010: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: ctx_current */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: chan_data */ -/* 0x0100: chan_mmio_count */ - 0x00000000, -/* 0x0104: chan_mmio_address */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0200: xfer_data */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0300: hub_mmio_list_base */ - 0x0417e91c, -}; - -uint32_t nv108_grhub_code[] = { - 0x030e0ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0xf489a408, - 0x020f0b1b, - 0x0002f87e, -/* 0x001a: queue_put_next */ - 0x98c400f8, - 0x0384b607, - 0xb6008dbb, - 0x8eb50880, - 0x018fb500, - 0xf00190b6, - 0xd9b50f94, -/* 0x0037: queue_get */ - 0xf400f801, - 0xd8980131, - 0x01d99800, - 0x0bf489a4, - 0x0789c421, - 0xbb0394b6, - 0x90b6009d, - 0x009e9808, - 0xb6019f98, - 0x84f00180, - 0x00d8b50f, -/* 0x0063: queue_get_done */ - 0xf80132f4, -/* 0x0065: nv_rd32 */ - 0xf0ecb200, - 0x00801fc9, - 0x0cf601ca, -/* 0x0073: nv_rd32_wait */ - 0x8c04bd00, - 0xcf01ca00, - 0xccc800cc, - 0xf61bf41f, - 0xec7e060a, - 0x008f0000, - 0xffcf01cb, -/* 0x008f: nv_wr32 */ - 0x8000f800, - 0xf601cc00, - 0x04bd000f, - 0xc9f0ecb2, - 0x1ec9f01f, - 0x01ca0080, - 0xbd000cf6, -/* 0x00a9: nv_wr32_wait */ - 0xca008c04, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f61b, -/* 0x00b8: wait_donez */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x00cf: wait_donez_ne */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf61bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x00ec: wait_doneo */ - 0x99f094bd, - 0x37008000, - 0x0009f602, - 0x008004bd, - 0x0af60206, -/* 0x0103: wait_doneo_e */ - 0x8804bd00, - 0xcf010000, - 0x8aff0088, - 0xf60bf488, - 0x99f094bd, - 0x17008000, - 0x0009f602, - 0x00f804bd, -/* 0x0120: mmctx_size */ -/* 0x0122: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0x1bf4efa4, - 0xf89fb2ec, -/* 0x013d: mmctx_xfer */ - 0xf094bd00, - 0x00800199, - 0x09f60237, - 0xbd04bd00, - 0x05bbfd94, - 0x800f0bf4, - 0xf601c400, - 0x04bd000b, -/* 0x015f: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0xc6008018, - 0x000ef601, - 0x008004bd, - 0x0ff601c7, - 0xf004bd00, -/* 0x017a: mmctx_multi_disabled */ - 0xabc80199, - 0x10b4b600, - 0xc80cb9f0, - 0xe4b601ae, - 0x05befd11, - 0x01c50080, - 0xbd000bf6, -/* 0x0195: mmctx_exec_loop */ -/* 0x0195: mmctx_wait_free */ - 0xc5008e04, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f60b, - 0x05e9fd00, - 0x01c80080, - 0xbd000ef6, - 0x04c0b604, - 0x1bf4cda4, - 0x02abc8df, -/* 0x01bf: mmctx_fini_wait */ - 0x8b1c1bf4, - 0xcf01c500, - 0xb4f000bb, - 0x10b4b01f, - 0x0af31bf4, - 0x00b87e05, - 0x250ef400, -/* 0x01d8: mmctx_stop */ - 0xb600abc8, - 0xb9f010b4, - 0x12b9f00c, - 0x01c50080, - 0xbd000bf6, -/* 0x01ed: mmctx_stop_wait */ - 0xc5008b04, - 0x00bbcf01, - 0xf412bbc8, -/* 0x01fa: mmctx_done */ - 0x94bdf61b, - 0x800199f0, - 0xf6021700, - 0x04bd0009, -/* 0x020a: strand_wait */ - 0xa0f900f8, - 0xb87e020a, - 0xa0fc0000, -/* 0x0216: strand_pre */ - 0x0c0900f8, - 0x024afc80, - 0xbd0009f6, - 0x020a7e04, -/* 0x0227: strand_post */ - 0x0900f800, - 0x4afc800d, - 0x0009f602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0238: strand_set */ - 0xfc800f0c, - 0x0cf6024f, - 0x0c04bd00, - 0x4afc800b, - 0x000cf602, - 0xfc8004bd, - 0x0ef6024f, - 0x0c04bd00, - 0x4afc800a, - 0x000cf602, - 0x0a7e04bd, - 0x00f80002, -/* 0x0268: strand_ctx_init */ - 0x99f094bd, - 0x37008003, - 0x0009f602, - 0x167e04bd, - 0x030e0002, - 0x0002387e, - 0xfc80c4bd, - 0x0cf60247, - 0x0c04bd00, - 0x4afc8001, - 0x000cf602, - 0x0a7e04bd, - 0x0c920002, - 0x46fc8001, - 0x000cf602, - 0x020c04bd, - 0x024afc80, - 0xbd000cf6, - 0x020a7e04, - 0x02277e00, - 0x42008800, - 0x20008902, - 0x0099cf02, -/* 0x02c7: ctx_init_strand_loop */ - 0xf608fe95, - 0x8ef6008e, - 0x808acf40, - 0xb606a5b6, - 0xeabb01a0, - 0x0480b600, - 0xf40192b6, - 0xe4b6e81b, - 0xf2efbc08, - 0x99f094bd, - 0x17008003, - 0x0009f602, - 0x00f804bd, -/* 0x02f8: error */ - 0x02050080, - 0xbd000ff6, - 0x80010f04, - 0xf6030700, - 0x04bd000f, -/* 0x030e: init */ - 0x04bd00f8, - 0x410007fe, - 0x11cf4200, - 0x0911e700, - 0x0814b601, - 0x020014fe, - 0x12004002, - 0xbd0002f6, - 0x05c94104, - 0xbd0010fe, - 0x07004024, - 0xbd0002f6, - 0x20034204, - 0x01010080, - 0xbd0002f6, - 0x20044204, - 0x01010480, - 0xbd0002f6, - 0x200b4204, - 0x01010880, - 0xbd0002f6, - 0x200c4204, - 0x01011c80, - 0xbd0002f6, - 0x01039204, - 0x03090080, - 0xbd0003f6, - 0x87044204, - 0xf6040040, - 0x04bd0002, - 0x00400402, - 0x0002f603, - 0x31f404bd, - 0x96048e10, - 0x00657e40, - 0xc7feb200, - 0x01b590f1, - 0x1ff4f003, - 0x01020fb5, - 0x041fbb01, - 0x800112b6, - 0xf6010300, - 0x04bd0001, - 0x01040080, - 0xbd0001f6, - 0x01004104, - 0xa87e020f, - 0xb77e0006, - 0x100f0006, - 0x0006f97e, - 0x98000e98, - 0x207e010f, - 0x14950001, - 0xc0008008, - 0x0004f601, - 0x008004bd, - 0x04f601c1, - 0xb704bd00, - 0xbb130030, - 0xf5b6001f, - 0xd3008002, - 0x000ff601, - 0x15b604bd, - 0x0110b608, - 0xb20814b6, - 0x02687e1f, - 0x001fbb00, - 0x84020398, -/* 0x041f: init_gpc */ - 0xb8502000, - 0x0008044e, - 0x8f7e1fb2, - 0x4eb80000, - 0xbd00010c, - 0x008f7ef4, - 0x044eb800, - 0x8f7e0001, - 0x4eb80000, - 0x0f000100, - 0x008f7e02, - 0x004eb800, -/* 0x044e: init_gpc_wait */ - 0x657e0008, - 0xffc80000, - 0xf90bf41f, - 0x08044eb8, - 0x00657e00, - 0x001fbb00, - 0x800040b7, - 0xf40132b6, - 0x000fb41b, - 0x0006f97e, - 0xa87e000f, - 0x00800006, - 0x01f60201, - 0xbd04bd00, - 0x1f19f014, - 0x02300080, - 0xbd0001f6, -/* 0x0491: main */ - 0x0031f404, - 0x0d0028f4, - 0x00377e10, - 0xf401f400, - 0x4001e4b1, - 0x00c71bf5, - 0x99f094bd, - 0x37008004, - 0x0009f602, - 0x008104bd, - 0x11cf02c0, - 0xc1008200, - 0x0022cf02, - 0xf41f13c8, - 0x23c8770b, - 0x550bf41f, - 0x12b220f9, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0231f401, - 0x00087c7e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x20fc04bd, - 0x99f094bd, - 0x37008006, - 0x0009f602, - 0x31f404bd, - 0x087c7e01, - 0xf094bd00, - 0x00800699, - 0x09f60217, - 0xf404bd00, -/* 0x0522: chsw_prev_no_next */ - 0x20f92f0e, - 0x32f412b2, - 0x0232f401, - 0x00087c7e, - 0x008020fc, - 0x02f602c0, - 0xf404bd00, -/* 0x053e: chsw_no_prev */ - 0x23c8130e, - 0x0d0bf41f, - 0xf40131f4, - 0x7c7e0232, -/* 0x054e: chsw_done */ - 0x01020008, - 0x02c30080, - 0xbd0002f6, - 0xf094bd04, - 0x00800499, - 0x09f60217, - 0xf504bd00, -/* 0x056b: main_not_ctx_switch */ - 0xb0ff2a0e, - 0x1bf401e4, - 0x7ef2b20c, - 0xf400081c, -/* 0x057a: main_not_ctx_chan */ - 0xe4b0400e, - 0x2c1bf402, - 0x99f094bd, - 0x37008007, - 0x0009f602, - 0x32f404bd, - 0x0232f401, - 0x00087c7e, - 0x99f094bd, - 0x17008007, - 0x0009f602, - 0x0ef404bd, -/* 0x05a9: main_not_ctx_save */ - 0x10ef9411, - 0x7e01f5f0, - 0xf50002f8, -/* 0x05b7: main_done */ - 0xbdfede0e, - 0x1f29f024, - 0x02300080, - 0xbd0002f6, - 0xcc0ef504, -/* 0x05c9: ih */ - 0xfe80f9fe, - 0x80f90188, - 0xa0f990f9, - 0xd0f9b0f9, - 0xf0f9e0f9, - 0x004a04bd, - 0x00aacf02, - 0xf404abc4, - 0x100d230b, - 0xcf1a004e, - 0x004f00ee, - 0x00ffcf19, - 0x0000047e, - 0x0400b0b7, - 0x0040010e, - 0x000ef61d, -/* 0x060a: ih_no_fifo */ - 0xabe404bd, - 0x0bf40100, - 0x4e100d0c, - 0x047e4001, -/* 0x061a: ih_no_ctxsw */ - 0xabe40000, - 0x0bf40400, - 0x07088e56, - 0x00657e40, - 0x80ffb200, - 0xf6020400, - 0x04bd000f, - 0x4007048e, - 0x0000657e, - 0x0080ffb2, - 0x0ff60203, - 0xc704bd00, - 0xee9450fe, - 0x07008f02, - 0x00efbb40, - 0x0000657e, - 0x02020080, - 0xbd000ff6, - 0x7e030f04, - 0x4b0002f8, - 0xbfb20100, - 0x4001448e, - 0x00008f7e, -/* 0x0674: ih_no_fwmthd */ - 0xbd05044b, - 0xb4abffb0, - 0x800c0bf4, - 0xf6030700, - 0x04bd000b, -/* 0x0688: ih_no_other */ - 0xf6010040, - 0x04bd000a, - 0xe0fcf0fc, - 0xb0fcd0fc, - 0x90fca0fc, - 0x88fe80fc, - 0xf480fc00, - 0x01f80032, -/* 0x06a8: ctx_4170s */ - 0xb210f5f0, - 0x41708eff, - 0x008f7e40, -/* 0x06b7: ctx_4170w */ - 0x8e00f800, - 0x7e404170, - 0xb2000065, - 0x10f4f0ff, - 0xf8f31bf4, -/* 0x06c9: ctx_redswitch */ - 0x02004e00, - 0xf040e5f0, - 0xe5f020e5, - 0x85008010, - 0x000ef601, - 0x080f04bd, -/* 0x06e0: ctx_redswitch_delay */ - 0xf401f2b6, - 0xe5f1fd1b, - 0xe5f10400, - 0x00800100, - 0x0ef60185, - 0xf804bd00, -/* 0x06f9: ctx_86c */ - 0x23008000, - 0x000ff602, - 0xffb204bd, - 0x408a148e, - 0x00008f7e, - 0x8c8effb2, - 0x8f7e41a8, - 0x00f80000, -/* 0x0718: ctx_mem */ - 0x02840080, - 0xbd000ff6, -/* 0x0721: ctx_mem_wait */ - 0x84008f04, - 0x00ffcf02, - 0xf405fffd, - 0x00f8f61b, -/* 0x0730: ctx_load */ - 0x99f094bd, - 0x37008005, - 0x0009f602, - 0x0c0a04bd, - 0x0000b87e, - 0x0080f4bd, - 0x0ff60289, - 0x8004bd00, - 0xf602c100, - 0x04bd0002, - 0x02830080, - 0xbd0002f6, - 0x7e070f04, - 0x80000718, - 0xf602c000, - 0x04bd0002, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x99f094bd, - 0x37008008, - 0x0009f602, - 0x008004bd, - 0x02f60281, - 0xd204bd00, - 0x80000000, - 0x800225f0, - 0xf6028800, - 0x04bd0002, - 0x00421001, - 0x0223f002, - 0xf80512fa, - 0xf094bd03, - 0x00800899, - 0x09f60217, - 0x9804bd00, - 0x14b68101, - 0x80029818, - 0xfd0825b6, - 0x01b50512, - 0xf094bd16, - 0x00800999, - 0x09f60237, - 0x8004bd00, - 0xf6028100, - 0x04bd0001, - 0x00800102, - 0x02f60288, - 0x4104bd00, - 0x13f00100, - 0x0501fa06, - 0x94bd03f8, - 0x800999f0, - 0xf6021700, - 0x04bd0009, - 0x99f094bd, - 0x17008005, - 0x0009f602, - 0x00f804bd, -/* 0x081c: ctx_chan */ - 0x0007307e, - 0xb87e0c0a, - 0x050f0000, - 0x0007187e, -/* 0x082e: ctx_mmio_exec */ - 0x039800f8, - 0x81008041, - 0x0003f602, - 0x34bd04bd, -/* 0x083c: ctx_mmio_loop */ - 0xf4ff34c4, - 0x00450e1b, - 0x0653f002, - 0xf80535fa, -/* 0x084d: ctx_mmio_pull */ - 0x804e9803, - 0x7e814f98, - 0xb600008f, - 0x12b60830, - 0xdf1bf401, -/* 0x0860: ctx_mmio_done */ - 0x80160398, - 0xf6028100, - 0x04bd0003, - 0x414000b5, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x087c: ctx_xfer */ - 0x0080040e, - 0x0ef60302, -/* 0x0887: ctx_xfer_idle */ - 0x8e04bd00, - 0xcf030000, - 0xe4f100ee, - 0x1bf42000, - 0x0611f4f5, -/* 0x089b: ctx_xfer_pre */ - 0x0f0c02f4, - 0x06f97e10, - 0x1b11f400, -/* 0x08a4: ctx_xfer_pre_load */ - 0xa87e020f, - 0xb77e0006, - 0xc97e0006, - 0xf4bd0006, - 0x0006a87e, - 0x0007307e, -/* 0x08bc: ctx_xfer_exec */ - 0xbd160198, - 0x05008024, - 0x0002f601, - 0x1fb204bd, - 0x41a5008e, - 0x00008f7e, - 0xf001fcf0, - 0x24b6022c, - 0x05f2fd01, - 0x048effb2, - 0x8f7e41a5, - 0x167e0000, - 0x24bd0002, - 0x0247fc80, - 0xbd0002f6, - 0x012cf004, - 0x800320b6, - 0xf6024afc, - 0x04bd0002, - 0xf001acf0, - 0x000b06a5, - 0x98000c98, - 0x000e010d, - 0x00013d7e, - 0xec7e080a, - 0x0a7e0000, - 0x01f40002, - 0x7e0c0a12, - 0x0f0000b8, - 0x07187e05, - 0x2d02f400, -/* 0x0938: ctx_xfer_post */ - 0xa87e020f, - 0xf4bd0006, - 0x0006f97e, - 0x0002277e, - 0x0006b77e, - 0xa87ef4bd, - 0x11f40006, - 0x40019810, - 0xf40511fd, - 0x2e7e070b, -/* 0x0962: ctx_xfer_no_post_mmio */ -/* 0x0962: ctx_xfer_done */ - 0x00f80008, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3 deleted file mode 100644 index 3ff52badf932..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3 +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define CHIPSET GF100 -#include "macros.fuc" - -.section #nvc0_grhub_data -#define INCLUDE_DATA -#include "com.fuc" -#include "hub.fuc" -#undef INCLUDE_DATA - -.section #nvc0_grhub_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "hub.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h deleted file mode 100644 index 92dfe6a4ac87..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h +++ /dev/null @@ -1,1047 +0,0 @@ -uint32_t nvc0_grhub_data[] = { -/* 0x0000: hub_mmio_list_head */ - 0x00000300, -/* 0x0004: hub_mmio_list_tail */ - 0x00000304, -/* 0x0008: gpc_count */ - 0x00000000, -/* 0x000c: rop_count */ - 0x00000000, -/* 0x0010: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: ctx_current */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: chan_data */ -/* 0x0100: chan_mmio_count */ - 0x00000000, -/* 0x0104: chan_mmio_address */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0200: xfer_data */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0300: hub_mmio_list_base */ - 0x0417e91c, -}; - -uint32_t nvc0_grhub_code[] = { - 0x039b0ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0x07f100f8, - 0x03f00500, - 0x000fd002, - 0xf7f004bd, - 0x0007f101, - 0x0303f007, - 0xbd000fd0, -/* 0x039b: init */ - 0xbd00f804, - 0x0007fe04, - 0x420017f1, - 0xcf0013f0, - 0x11e70011, - 0x14b60109, - 0x0014fe08, - 0xf10227f0, - 0xf0120007, - 0x02d00003, - 0xf104bd00, - 0xfe06c817, - 0x24bd0010, - 0x070007f1, - 0xd00003f0, - 0x04bd0002, - 0x200327f1, - 0x010007f1, - 0xd00103f0, - 0x04bd0002, - 0x200427f1, - 0x010407f1, - 0xd00103f0, - 0x04bd0002, - 0x200b27f1, - 0x010807f1, - 0xd00103f0, - 0x04bd0002, - 0x200c27f1, - 0x011c07f1, - 0xd00103f0, - 0x04bd0002, - 0xf1010392, - 0xf0090007, - 0x03d00303, - 0xf104bd00, - 0xf0870427, - 0x07f10023, - 0x03f00400, - 0x0002d000, - 0x27f004bd, - 0x0007f104, - 0x0003f003, - 0xbd0002d0, - 0x1031f404, - 0x9604e7f1, - 0xf440e3f0, - 0xfeb96821, - 0x90f1c702, - 0xf0030180, - 0x0f801ff4, - 0x0117f002, - 0xb6041fbb, - 0x07f10112, - 0x03f00300, - 0x0001d001, - 0x07f104bd, - 0x03f00400, - 0x0001d001, - 0x17f104bd, - 0xf7f00100, - 0x0d21f502, - 0x1f21f508, - 0x10f7f008, - 0x086c21f5, - 0x98000e98, - 0x21f5010f, - 0x14950150, - 0x0007f108, - 0x0103f0c0, - 0xbd0004d0, - 0x0007f104, - 0x0103f0c1, - 0xbd0004d0, - 0x0030b704, - 0x001fbb13, - 0xf102f5b6, - 0xf0d30007, - 0x0fd00103, - 0xb604bd00, - 0x10b60815, - 0x0814b601, - 0xf5021fb9, - 0xbb02d321, - 0x0398001f, - 0x0047f102, - 0x5043f020, -/* 0x04f4: init_gpc */ - 0x08044ea0, - 0xf4021fb9, - 0x4ea09d21, - 0xf4bd010c, - 0xa09d21f4, - 0xf401044e, - 0x4ea09d21, - 0xf7f00100, - 0x9d21f402, - 0x08004ea0, -/* 0x051c: init_gpc_wait */ - 0xc86821f4, - 0x0bf41fff, - 0x044ea0fa, - 0x6821f408, - 0xb7001fbb, - 0xb6800040, - 0x1bf40132, - 0x00f7f0be, - 0x086c21f5, - 0xf500f7f0, - 0xf1080d21, - 0xf0010007, - 0x01d00203, - 0xbd04bd00, - 0x1f19f014, - 0x080007f1, - 0xd00203f0, - 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, - 0x3921f410, - 0xb1f401f4, - 0xf54001e4, - 0xbd00e91b, - 0x0499f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xc00017f1, - 0xcf0213f0, - 0x27f10011, - 0x23f0c100, - 0x0022cf02, - 0xf51f13c8, - 0xc800890b, - 0x0bf41f23, - 0xb920f962, - 0x94bd0212, - 0xf10799f0, - 0xf00f0007, - 0x09d00203, - 0xf404bd00, - 0x31f40132, - 0x4021f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x20fc04bd, - 0x99f094bd, - 0x0007f106, - 0x0203f00f, - 0xbd0009d0, - 0x0131f404, - 0x0a4021f5, - 0x99f094bd, - 0x0007f106, - 0x0203f017, - 0xbd0009d0, - 0x330ef404, -/* 0x060c: chsw_prev_no_next */ - 0x12b920f9, - 0x0132f402, - 0xf50232f4, - 0xfc0a4021, - 0x0007f120, - 0x0203f0c0, - 0xbd0002d0, - 0x130ef404, -/* 0x062c: chsw_no_prev */ - 0xf41f23c8, - 0x31f40d0b, - 0x0232f401, - 0x0a4021f5, -/* 0x063c: chsw_done */ - 0xf10127f0, - 0xf0c30007, - 0x02d00203, - 0xbd04bd00, - 0x0499f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, - 0xff080ef5, -/* 0x0660: main_not_ctx_switch */ - 0xf401e4b0, - 0xf2b90d1b, - 0xd021f502, - 0x460ef409, -/* 0x0670: main_not_ctx_chan */ - 0xf402e4b0, - 0x94bd321b, - 0xf10799f0, - 0xf00f0007, - 0x09d00203, - 0xf404bd00, - 0x32f40132, - 0x4021f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x0ef404bd, -/* 0x06a5: main_not_ctx_save */ - 0x10ef9411, - 0xf501f5f0, - 0xf5037e21, -/* 0x06b3: main_done */ - 0xbdfeb50e, - 0x1f29f024, - 0x080007f1, - 0xd00203f0, - 0x04bd0002, - 0xfea00ef5, -/* 0x06c8: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x10d7f030, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xb70421f4, - 0xf00400b0, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x071a: ih_no_fifo */ - 0xabe404bd, - 0x0bf40100, - 0x10d7f00d, - 0x4001e7f1, -/* 0x072b: ih_no_ctxsw */ - 0xe40421f4, - 0xf40400ab, - 0xe7f16c0b, - 0xe3f00708, - 0x6821f440, - 0xf102ffb9, - 0xf0040007, - 0x0fd00203, - 0xf104bd00, - 0xf00704e7, - 0x21f440e3, - 0x02ffb968, - 0x030007f1, - 0xd00203f0, - 0x04bd000f, - 0x9450fec7, - 0xf7f102ee, - 0xf3f00700, - 0x00efbb40, - 0xf16821f4, - 0xf0020007, - 0x0fd00203, - 0xf004bd00, - 0x21f503f7, - 0xb7f1037e, - 0xbfb90100, - 0x44e7f102, - 0x40e3f001, -/* 0x079b: ih_no_fwmthd */ - 0xf19d21f4, - 0xbd0504b7, - 0xb4abffb0, - 0xf10f0bf4, - 0xf0070007, - 0x0bd00303, -/* 0x07b3: ih_no_other */ - 0xf104bd00, - 0xf0010007, - 0x0ad00003, - 0xfc04bd00, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x07d7: ctx_4160s */ - 0xf001f800, - 0xffb901f7, - 0x60e7f102, - 0x40e3f041, -/* 0x07e7: ctx_4160s_wait */ - 0xf19d21f4, - 0xf04160e7, - 0x21f440e3, - 0x02ffb968, - 0xf404ffc8, - 0x00f8f00b, -/* 0x07fc: ctx_4160c */ - 0xffb9f4bd, - 0x60e7f102, - 0x40e3f041, - 0xf89d21f4, -/* 0x080d: ctx_4170s */ - 0x10f5f000, - 0xf102ffb9, - 0xf04170e7, - 0x21f440e3, -/* 0x081f: ctx_4170w */ - 0xf100f89d, - 0xf04170e7, - 0x21f440e3, - 0x02ffb968, - 0xf410f4f0, - 0x00f8f01b, -/* 0x0834: ctx_redswitch */ - 0x0200e7f1, - 0xf040e5f0, - 0xe5f020e5, - 0x0007f110, - 0x0103f085, - 0xbd000ed0, - 0x08f7f004, -/* 0x0850: ctx_redswitch_delay */ - 0xf401f2b6, - 0xe5f1fd1b, - 0xe5f10400, - 0x07f10100, - 0x03f08500, - 0x000ed001, - 0x00f804bd, -/* 0x086c: ctx_86c */ - 0x1b0007f1, - 0xd00203f0, - 0x04bd000f, - 0xf102ffb9, - 0xf08a14e7, - 0x21f440e3, - 0x02ffb99d, - 0xa86ce7f1, - 0xf441e3f0, - 0x00f89d21, -/* 0x0894: ctx_mem */ - 0x840007f1, - 0xd00203f0, - 0x04bd000f, -/* 0x08a0: ctx_mem_wait */ - 0x8400f7f1, - 0xcf02f3f0, - 0xfffd00ff, - 0xf31bf405, -/* 0x08b2: ctx_load */ - 0x94bd00f8, - 0xf10599f0, - 0xf00f0007, - 0x09d00203, - 0xf004bd00, - 0x21f40ca7, - 0xf1f4bdd0, - 0xf0890007, - 0x0fd00203, - 0xf104bd00, - 0xf0c10007, - 0x02d00203, - 0xf104bd00, - 0xf0830007, - 0x02d00203, - 0xf004bd00, - 0x21f507f7, - 0x07f10894, - 0x03f0c000, - 0x0002d002, - 0x0bfe04bd, - 0x1f2af000, - 0xb60424b6, - 0x94bd0220, - 0xf10899f0, - 0xf00f0007, - 0x09d00203, - 0xf104bd00, - 0xf0810007, - 0x02d00203, - 0xf104bd00, - 0xf1000027, - 0xf0800023, - 0x07f10225, - 0x03f08800, - 0x0002d002, - 0x17f004bd, - 0x0027f110, - 0x0223f002, - 0xf80512fa, - 0xf094bd03, - 0x07f10899, - 0x03f01700, - 0x0009d002, - 0x019804bd, - 0x1814b681, - 0xb6800298, - 0x12fd0825, - 0x16018005, - 0x99f094bd, - 0x0007f109, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f081, - 0xbd0001d0, - 0x0127f004, - 0x880007f1, - 0xd00203f0, - 0x04bd0002, - 0x010017f1, - 0xfa0613f0, - 0x03f80501, - 0x99f094bd, - 0x0007f109, - 0x0203f017, - 0xbd0009d0, - 0xf094bd04, - 0x07f10599, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x09d0: ctx_chan */ - 0x07d721f5, - 0x08b221f5, - 0xf40ca7f0, - 0xf7f0d021, - 0x9421f505, - 0xfc21f508, -/* 0x09eb: ctx_mmio_exec */ - 0x9800f807, - 0x07f14103, - 0x03f08100, - 0x0003d002, - 0x34bd04bd, -/* 0x09fc: ctx_mmio_loop */ - 0xf4ff34c4, - 0x57f10f1b, - 0x53f00200, - 0x0535fa06, -/* 0x0a0e: ctx_mmio_pull */ - 0x4e9803f8, - 0x814f9880, - 0xb69d21f4, - 0x12b60830, - 0xdf1bf401, -/* 0x0a20: ctx_mmio_done */ - 0xf1160398, - 0xf0810007, - 0x03d00203, - 0x8004bd00, - 0x17f14000, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x0a40: ctx_xfer */ - 0xf104e7f0, - 0xf0020007, - 0x0ed00303, -/* 0x0a4f: ctx_xfer_idle */ - 0xf104bd00, - 0xf00000e7, - 0xeecf03e3, - 0x00e4f100, - 0xf21bf420, - 0xf40611f4, -/* 0x0a66: ctx_xfer_pre */ - 0xf7f01102, - 0x6c21f510, - 0xd721f508, - 0x1c11f407, -/* 0x0a74: ctx_xfer_pre_load */ - 0xf502f7f0, - 0xf5080d21, - 0xf5081f21, - 0xbd083421, - 0x0d21f5f4, - 0xb221f508, -/* 0x0a8d: ctx_xfer_exec */ - 0x16019808, - 0x07f124bd, - 0x03f00500, - 0x0002d001, - 0x1fb904bd, - 0x00e7f102, - 0x41e3f0a5, - 0xf09d21f4, - 0x2cf001fc, - 0x0124b602, - 0xb905f2fd, - 0xe7f102ff, - 0xe3f0a504, - 0x9d21f441, - 0x026a21f5, - 0x07f124bd, - 0x03f047fc, - 0x0002d002, - 0x2cf004bd, - 0x0320b601, - 0x4afc07f1, - 0xd00203f0, - 0x04bd0002, - 0xf001acf0, - 0xb7f006a5, - 0x000c9800, - 0xf0010d98, - 0x21f500e7, - 0xa7f0016f, - 0x1021f508, - 0x5e21f501, - 0x1301f402, - 0xf40ca7f0, - 0xf7f0d021, - 0x9421f505, - 0x3202f408, -/* 0x0b1c: ctx_xfer_post */ - 0xf502f7f0, - 0xbd080d21, - 0x6c21f5f4, - 0x7f21f508, - 0x1f21f502, - 0xf5f4bd08, - 0xf4080d21, - 0x01981011, - 0x0511fd40, - 0xf5070bf4, -/* 0x0b47: ctx_xfer_no_post_mmio */ - 0xf509eb21, -/* 0x0b4b: ctx_xfer_done */ - 0xf807fc21, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3 deleted file mode 100644 index afbe03ac9077..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3 +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define CHIPSET GF117 -#include "macros.fuc" - -.section #nvd7_grhub_data -#define INCLUDE_DATA -#include "com.fuc" -#include "hub.fuc" -#undef INCLUDE_DATA - -.section #nvd7_grhub_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "hub.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h deleted file mode 100644 index 62b0c7601d8b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h +++ /dev/null @@ -1,1047 +0,0 @@ -uint32_t nvd7_grhub_data[] = { -/* 0x0000: hub_mmio_list_head */ - 0x00000300, -/* 0x0004: hub_mmio_list_tail */ - 0x00000304, -/* 0x0008: gpc_count */ - 0x00000000, -/* 0x000c: rop_count */ - 0x00000000, -/* 0x0010: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: ctx_current */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: chan_data */ -/* 0x0100: chan_mmio_count */ - 0x00000000, -/* 0x0104: chan_mmio_address */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0200: xfer_data */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0300: hub_mmio_list_base */ - 0x0417e91c, -}; - -uint32_t nvd7_grhub_code[] = { - 0x039b0ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0x07f100f8, - 0x03f00500, - 0x000fd002, - 0xf7f004bd, - 0x0007f101, - 0x0303f007, - 0xbd000fd0, -/* 0x039b: init */ - 0xbd00f804, - 0x0007fe04, - 0x420017f1, - 0xcf0013f0, - 0x11e70011, - 0x14b60109, - 0x0014fe08, - 0xf10227f0, - 0xf0120007, - 0x02d00003, - 0xf104bd00, - 0xfe06c817, - 0x24bd0010, - 0x070007f1, - 0xd00003f0, - 0x04bd0002, - 0x200327f1, - 0x010007f1, - 0xd00103f0, - 0x04bd0002, - 0x200427f1, - 0x010407f1, - 0xd00103f0, - 0x04bd0002, - 0x200b27f1, - 0x010807f1, - 0xd00103f0, - 0x04bd0002, - 0x200c27f1, - 0x011c07f1, - 0xd00103f0, - 0x04bd0002, - 0xf1010392, - 0xf0090007, - 0x03d00303, - 0xf104bd00, - 0xf0870427, - 0x07f10023, - 0x03f00400, - 0x0002d000, - 0x27f004bd, - 0x0007f104, - 0x0003f003, - 0xbd0002d0, - 0x1031f404, - 0x9604e7f1, - 0xf440e3f0, - 0xfeb96821, - 0x90f1c702, - 0xf0030180, - 0x0f801ff4, - 0x0117f002, - 0xb6041fbb, - 0x07f10112, - 0x03f00300, - 0x0001d001, - 0x07f104bd, - 0x03f00400, - 0x0001d001, - 0x17f104bd, - 0xf7f00100, - 0x0d21f502, - 0x1f21f508, - 0x10f7f008, - 0x086c21f5, - 0x98000e98, - 0x21f5010f, - 0x14950150, - 0x0007f108, - 0x0103f0c0, - 0xbd0004d0, - 0x0007f104, - 0x0103f0c1, - 0xbd0004d0, - 0x0030b704, - 0x001fbb13, - 0xf102f5b6, - 0xf0d30007, - 0x0fd00103, - 0xb604bd00, - 0x10b60815, - 0x0814b601, - 0xf5021fb9, - 0xbb02d321, - 0x0398001f, - 0x0047f102, - 0x5043f020, -/* 0x04f4: init_gpc */ - 0x08044ea0, - 0xf4021fb9, - 0x4ea09d21, - 0xf4bd010c, - 0xa09d21f4, - 0xf401044e, - 0x4ea09d21, - 0xf7f00100, - 0x9d21f402, - 0x08004ea0, -/* 0x051c: init_gpc_wait */ - 0xc86821f4, - 0x0bf41fff, - 0x044ea0fa, - 0x6821f408, - 0xb7001fbb, - 0xb6800040, - 0x1bf40132, - 0x00f7f0be, - 0x086c21f5, - 0xf500f7f0, - 0xf1080d21, - 0xf0010007, - 0x01d00203, - 0xbd04bd00, - 0x1f19f014, - 0x080007f1, - 0xd00203f0, - 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, - 0x3921f410, - 0xb1f401f4, - 0xf54001e4, - 0xbd00e91b, - 0x0499f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xc00017f1, - 0xcf0213f0, - 0x27f10011, - 0x23f0c100, - 0x0022cf02, - 0xf51f13c8, - 0xc800890b, - 0x0bf41f23, - 0xb920f962, - 0x94bd0212, - 0xf10799f0, - 0xf00f0007, - 0x09d00203, - 0xf404bd00, - 0x31f40132, - 0x4021f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x20fc04bd, - 0x99f094bd, - 0x0007f106, - 0x0203f00f, - 0xbd0009d0, - 0x0131f404, - 0x0a4021f5, - 0x99f094bd, - 0x0007f106, - 0x0203f017, - 0xbd0009d0, - 0x330ef404, -/* 0x060c: chsw_prev_no_next */ - 0x12b920f9, - 0x0132f402, - 0xf50232f4, - 0xfc0a4021, - 0x0007f120, - 0x0203f0c0, - 0xbd0002d0, - 0x130ef404, -/* 0x062c: chsw_no_prev */ - 0xf41f23c8, - 0x31f40d0b, - 0x0232f401, - 0x0a4021f5, -/* 0x063c: chsw_done */ - 0xf10127f0, - 0xf0c30007, - 0x02d00203, - 0xbd04bd00, - 0x0499f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, - 0xff080ef5, -/* 0x0660: main_not_ctx_switch */ - 0xf401e4b0, - 0xf2b90d1b, - 0xd021f502, - 0x460ef409, -/* 0x0670: main_not_ctx_chan */ - 0xf402e4b0, - 0x94bd321b, - 0xf10799f0, - 0xf00f0007, - 0x09d00203, - 0xf404bd00, - 0x32f40132, - 0x4021f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x0ef404bd, -/* 0x06a5: main_not_ctx_save */ - 0x10ef9411, - 0xf501f5f0, - 0xf5037e21, -/* 0x06b3: main_done */ - 0xbdfeb50e, - 0x1f29f024, - 0x080007f1, - 0xd00203f0, - 0x04bd0002, - 0xfea00ef5, -/* 0x06c8: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x10d7f030, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xb70421f4, - 0xf00400b0, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x071a: ih_no_fifo */ - 0xabe404bd, - 0x0bf40100, - 0x10d7f00d, - 0x4001e7f1, -/* 0x072b: ih_no_ctxsw */ - 0xe40421f4, - 0xf40400ab, - 0xe7f16c0b, - 0xe3f00708, - 0x6821f440, - 0xf102ffb9, - 0xf0040007, - 0x0fd00203, - 0xf104bd00, - 0xf00704e7, - 0x21f440e3, - 0x02ffb968, - 0x030007f1, - 0xd00203f0, - 0x04bd000f, - 0x9450fec7, - 0xf7f102ee, - 0xf3f00700, - 0x00efbb40, - 0xf16821f4, - 0xf0020007, - 0x0fd00203, - 0xf004bd00, - 0x21f503f7, - 0xb7f1037e, - 0xbfb90100, - 0x44e7f102, - 0x40e3f001, -/* 0x079b: ih_no_fwmthd */ - 0xf19d21f4, - 0xbd0504b7, - 0xb4abffb0, - 0xf10f0bf4, - 0xf0070007, - 0x0bd00303, -/* 0x07b3: ih_no_other */ - 0xf104bd00, - 0xf0010007, - 0x0ad00003, - 0xfc04bd00, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x07d7: ctx_4160s */ - 0xf001f800, - 0xffb901f7, - 0x60e7f102, - 0x40e3f041, -/* 0x07e7: ctx_4160s_wait */ - 0xf19d21f4, - 0xf04160e7, - 0x21f440e3, - 0x02ffb968, - 0xf404ffc8, - 0x00f8f00b, -/* 0x07fc: ctx_4160c */ - 0xffb9f4bd, - 0x60e7f102, - 0x40e3f041, - 0xf89d21f4, -/* 0x080d: ctx_4170s */ - 0x10f5f000, - 0xf102ffb9, - 0xf04170e7, - 0x21f440e3, -/* 0x081f: ctx_4170w */ - 0xf100f89d, - 0xf04170e7, - 0x21f440e3, - 0x02ffb968, - 0xf410f4f0, - 0x00f8f01b, -/* 0x0834: ctx_redswitch */ - 0x0200e7f1, - 0xf040e5f0, - 0xe5f020e5, - 0x0007f110, - 0x0103f085, - 0xbd000ed0, - 0x08f7f004, -/* 0x0850: ctx_redswitch_delay */ - 0xf401f2b6, - 0xe5f1fd1b, - 0xe5f10400, - 0x07f10100, - 0x03f08500, - 0x000ed001, - 0x00f804bd, -/* 0x086c: ctx_86c */ - 0x1b0007f1, - 0xd00203f0, - 0x04bd000f, - 0xf102ffb9, - 0xf08a14e7, - 0x21f440e3, - 0x02ffb99d, - 0xa86ce7f1, - 0xf441e3f0, - 0x00f89d21, -/* 0x0894: ctx_mem */ - 0x840007f1, - 0xd00203f0, - 0x04bd000f, -/* 0x08a0: ctx_mem_wait */ - 0x8400f7f1, - 0xcf02f3f0, - 0xfffd00ff, - 0xf31bf405, -/* 0x08b2: ctx_load */ - 0x94bd00f8, - 0xf10599f0, - 0xf00f0007, - 0x09d00203, - 0xf004bd00, - 0x21f40ca7, - 0xf1f4bdd0, - 0xf0890007, - 0x0fd00203, - 0xf104bd00, - 0xf0c10007, - 0x02d00203, - 0xf104bd00, - 0xf0830007, - 0x02d00203, - 0xf004bd00, - 0x21f507f7, - 0x07f10894, - 0x03f0c000, - 0x0002d002, - 0x0bfe04bd, - 0x1f2af000, - 0xb60424b6, - 0x94bd0220, - 0xf10899f0, - 0xf00f0007, - 0x09d00203, - 0xf104bd00, - 0xf0810007, - 0x02d00203, - 0xf104bd00, - 0xf1000027, - 0xf0800023, - 0x07f10225, - 0x03f08800, - 0x0002d002, - 0x17f004bd, - 0x0027f110, - 0x0223f002, - 0xf80512fa, - 0xf094bd03, - 0x07f10899, - 0x03f01700, - 0x0009d002, - 0x019804bd, - 0x1814b681, - 0xb6800298, - 0x12fd0825, - 0x16018005, - 0x99f094bd, - 0x0007f109, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f081, - 0xbd0001d0, - 0x0127f004, - 0x880007f1, - 0xd00203f0, - 0x04bd0002, - 0x010017f1, - 0xfa0613f0, - 0x03f80501, - 0x99f094bd, - 0x0007f109, - 0x0203f017, - 0xbd0009d0, - 0xf094bd04, - 0x07f10599, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x09d0: ctx_chan */ - 0x07d721f5, - 0x08b221f5, - 0xf40ca7f0, - 0xf7f0d021, - 0x9421f505, - 0xfc21f508, -/* 0x09eb: ctx_mmio_exec */ - 0x9800f807, - 0x07f14103, - 0x03f08100, - 0x0003d002, - 0x34bd04bd, -/* 0x09fc: ctx_mmio_loop */ - 0xf4ff34c4, - 0x57f10f1b, - 0x53f00200, - 0x0535fa06, -/* 0x0a0e: ctx_mmio_pull */ - 0x4e9803f8, - 0x814f9880, - 0xb69d21f4, - 0x12b60830, - 0xdf1bf401, -/* 0x0a20: ctx_mmio_done */ - 0xf1160398, - 0xf0810007, - 0x03d00203, - 0x8004bd00, - 0x17f14000, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x0a40: ctx_xfer */ - 0xf104e7f0, - 0xf0020007, - 0x0ed00303, -/* 0x0a4f: ctx_xfer_idle */ - 0xf104bd00, - 0xf00000e7, - 0xeecf03e3, - 0x00e4f100, - 0xf21bf420, - 0xf40611f4, -/* 0x0a66: ctx_xfer_pre */ - 0xf7f01102, - 0x6c21f510, - 0xd721f508, - 0x1c11f407, -/* 0x0a74: ctx_xfer_pre_load */ - 0xf502f7f0, - 0xf5080d21, - 0xf5081f21, - 0xbd083421, - 0x0d21f5f4, - 0xb221f508, -/* 0x0a8d: ctx_xfer_exec */ - 0x16019808, - 0x07f124bd, - 0x03f00500, - 0x0002d001, - 0x1fb904bd, - 0x00e7f102, - 0x41e3f0a5, - 0xf09d21f4, - 0x2cf001fc, - 0x0124b602, - 0xb905f2fd, - 0xe7f102ff, - 0xe3f0a504, - 0x9d21f441, - 0x026a21f5, - 0x07f124bd, - 0x03f047fc, - 0x0002d002, - 0x2cf004bd, - 0x0320b601, - 0x4afc07f1, - 0xd00203f0, - 0x04bd0002, - 0xf001acf0, - 0xb7f006a5, - 0x000c9800, - 0xf0010d98, - 0x21f500e7, - 0xa7f0016f, - 0x1021f508, - 0x5e21f501, - 0x1301f402, - 0xf40ca7f0, - 0xf7f0d021, - 0x9421f505, - 0x3202f408, -/* 0x0b1c: ctx_xfer_post */ - 0xf502f7f0, - 0xbd080d21, - 0x6c21f5f4, - 0x7f21f508, - 0x1f21f502, - 0xf5f4bd08, - 0xf4080d21, - 0x01981011, - 0x0511fd40, - 0xf5070bf4, -/* 0x0b47: ctx_xfer_no_post_mmio */ - 0xf509eb21, -/* 0x0b4b: ctx_xfer_done */ - 0xf807fc21, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3 deleted file mode 100644 index d4840f1879fd..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3 +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define CHIPSET GK100 -#include "macros.fuc" - -.section #nve0_grhub_data -#define INCLUDE_DATA -#include "com.fuc" -#include "hub.fuc" -#undef INCLUDE_DATA - -.section #nve0_grhub_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "hub.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h deleted file mode 100644 index 51c3797d8537..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h +++ /dev/null @@ -1,1044 +0,0 @@ -uint32_t nve0_grhub_data[] = { -/* 0x0000: hub_mmio_list_head */ - 0x00000300, -/* 0x0004: hub_mmio_list_tail */ - 0x00000304, -/* 0x0008: gpc_count */ - 0x00000000, -/* 0x000c: rop_count */ - 0x00000000, -/* 0x0010: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: ctx_current */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: chan_data */ -/* 0x0100: chan_mmio_count */ - 0x00000000, -/* 0x0104: chan_mmio_address */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0200: xfer_data */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0300: hub_mmio_list_base */ - 0x0417e91c, -}; - -uint32_t nve0_grhub_code[] = { - 0x039b0ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0x07f100f8, - 0x03f00500, - 0x000fd002, - 0xf7f004bd, - 0x0007f101, - 0x0303f007, - 0xbd000fd0, -/* 0x039b: init */ - 0xbd00f804, - 0x0007fe04, - 0x420017f1, - 0xcf0013f0, - 0x11e70011, - 0x14b60109, - 0x0014fe08, - 0xf10227f0, - 0xf0120007, - 0x02d00003, - 0xf104bd00, - 0xfe06c817, - 0x24bd0010, - 0x070007f1, - 0xd00003f0, - 0x04bd0002, - 0x200327f1, - 0x010007f1, - 0xd00103f0, - 0x04bd0002, - 0x200427f1, - 0x010407f1, - 0xd00103f0, - 0x04bd0002, - 0x200b27f1, - 0x010807f1, - 0xd00103f0, - 0x04bd0002, - 0x200c27f1, - 0x011c07f1, - 0xd00103f0, - 0x04bd0002, - 0xf1010392, - 0xf0090007, - 0x03d00303, - 0xf104bd00, - 0xf0870427, - 0x07f10023, - 0x03f00400, - 0x0002d000, - 0x27f004bd, - 0x0007f104, - 0x0003f003, - 0xbd0002d0, - 0x1031f404, - 0x9604e7f1, - 0xf440e3f0, - 0xfeb96821, - 0x90f1c702, - 0xf0030180, - 0x0f801ff4, - 0x0117f002, - 0xb6041fbb, - 0x07f10112, - 0x03f00300, - 0x0001d001, - 0x07f104bd, - 0x03f00400, - 0x0001d001, - 0x17f104bd, - 0xf7f00100, - 0xd721f502, - 0xe921f507, - 0x10f7f007, - 0x083621f5, - 0x98000e98, - 0x21f5010f, - 0x14950150, - 0x0007f108, - 0x0103f0c0, - 0xbd0004d0, - 0x0007f104, - 0x0103f0c1, - 0xbd0004d0, - 0x0030b704, - 0x001fbb13, - 0xf102f5b6, - 0xf0d30007, - 0x0fd00103, - 0xb604bd00, - 0x10b60815, - 0x0814b601, - 0xf5021fb9, - 0xbb02d321, - 0x0398001f, - 0x0047f102, - 0x5043f020, -/* 0x04f4: init_gpc */ - 0x08044ea0, - 0xf4021fb9, - 0x4ea09d21, - 0xf4bd010c, - 0xa09d21f4, - 0xf401044e, - 0x4ea09d21, - 0xf7f00100, - 0x9d21f402, - 0x08004ea0, -/* 0x051c: init_gpc_wait */ - 0xc86821f4, - 0x0bf41fff, - 0x044ea0fa, - 0x6821f408, - 0xb7001fbb, - 0xb6800040, - 0x1bf40132, - 0x00f7f0be, - 0x083621f5, - 0xf500f7f0, - 0xf107d721, - 0xf0010007, - 0x01d00203, - 0xbd04bd00, - 0x1f19f014, - 0x080007f1, - 0xd00203f0, - 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, - 0x3921f410, - 0xb1f401f4, - 0xf54001e4, - 0xbd00e91b, - 0x0499f094, - 0x0f0007f1, - 0xd00203f0, - 0x04bd0009, - 0xc00017f1, - 0xcf0213f0, - 0x27f10011, - 0x23f0c100, - 0x0022cf02, - 0xf51f13c8, - 0xc800890b, - 0x0bf41f23, - 0xb920f962, - 0x94bd0212, - 0xf10799f0, - 0xf00f0007, - 0x09d00203, - 0xf404bd00, - 0x31f40132, - 0x0221f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x20fc04bd, - 0x99f094bd, - 0x0007f106, - 0x0203f00f, - 0xbd0009d0, - 0x0131f404, - 0x0a0221f5, - 0x99f094bd, - 0x0007f106, - 0x0203f017, - 0xbd0009d0, - 0x330ef404, -/* 0x060c: chsw_prev_no_next */ - 0x12b920f9, - 0x0132f402, - 0xf50232f4, - 0xfc0a0221, - 0x0007f120, - 0x0203f0c0, - 0xbd0002d0, - 0x130ef404, -/* 0x062c: chsw_no_prev */ - 0xf41f23c8, - 0x31f40d0b, - 0x0232f401, - 0x0a0221f5, -/* 0x063c: chsw_done */ - 0xf10127f0, - 0xf0c30007, - 0x02d00203, - 0xbd04bd00, - 0x0499f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, - 0xff080ef5, -/* 0x0660: main_not_ctx_switch */ - 0xf401e4b0, - 0xf2b90d1b, - 0x9a21f502, - 0x460ef409, -/* 0x0670: main_not_ctx_chan */ - 0xf402e4b0, - 0x94bd321b, - 0xf10799f0, - 0xf00f0007, - 0x09d00203, - 0xf404bd00, - 0x32f40132, - 0x0221f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x0ef404bd, -/* 0x06a5: main_not_ctx_save */ - 0x10ef9411, - 0xf501f5f0, - 0xf5037e21, -/* 0x06b3: main_done */ - 0xbdfeb50e, - 0x1f29f024, - 0x080007f1, - 0xd00203f0, - 0x04bd0002, - 0xfea00ef5, -/* 0x06c8: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x10d7f030, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xb70421f4, - 0xf00400b0, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x071a: ih_no_fifo */ - 0xabe404bd, - 0x0bf40100, - 0x10d7f00d, - 0x4001e7f1, -/* 0x072b: ih_no_ctxsw */ - 0xe40421f4, - 0xf40400ab, - 0xe7f16c0b, - 0xe3f00708, - 0x6821f440, - 0xf102ffb9, - 0xf0040007, - 0x0fd00203, - 0xf104bd00, - 0xf00704e7, - 0x21f440e3, - 0x02ffb968, - 0x030007f1, - 0xd00203f0, - 0x04bd000f, - 0x9450fec7, - 0xf7f102ee, - 0xf3f00700, - 0x00efbb40, - 0xf16821f4, - 0xf0020007, - 0x0fd00203, - 0xf004bd00, - 0x21f503f7, - 0xb7f1037e, - 0xbfb90100, - 0x44e7f102, - 0x40e3f001, -/* 0x079b: ih_no_fwmthd */ - 0xf19d21f4, - 0xbd0504b7, - 0xb4abffb0, - 0xf10f0bf4, - 0xf0070007, - 0x0bd00303, -/* 0x07b3: ih_no_other */ - 0xf104bd00, - 0xf0010007, - 0x0ad00003, - 0xfc04bd00, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x07d7: ctx_4170s */ - 0xf001f800, - 0xffb910f5, - 0x70e7f102, - 0x40e3f041, - 0xf89d21f4, -/* 0x07e9: ctx_4170w */ - 0x70e7f100, - 0x40e3f041, - 0xb96821f4, - 0xf4f002ff, - 0xf01bf410, -/* 0x07fe: ctx_redswitch */ - 0xe7f100f8, - 0xe5f00200, - 0x20e5f040, - 0xf110e5f0, - 0xf0850007, - 0x0ed00103, - 0xf004bd00, -/* 0x081a: ctx_redswitch_delay */ - 0xf2b608f7, - 0xfd1bf401, - 0x0400e5f1, - 0x0100e5f1, - 0x850007f1, - 0xd00103f0, - 0x04bd000e, -/* 0x0836: ctx_86c */ - 0x07f100f8, - 0x03f01b00, - 0x000fd002, - 0xffb904bd, - 0x14e7f102, - 0x40e3f08a, - 0xb99d21f4, - 0xe7f102ff, - 0xe3f0a86c, - 0x9d21f441, -/* 0x085e: ctx_mem */ - 0x07f100f8, - 0x03f08400, - 0x000fd002, -/* 0x086a: ctx_mem_wait */ - 0xf7f104bd, - 0xf3f08400, - 0x00ffcf02, - 0xf405fffd, - 0x00f8f31b, -/* 0x087c: ctx_load */ - 0x99f094bd, - 0x0007f105, - 0x0203f00f, - 0xbd0009d0, - 0x0ca7f004, - 0xbdd021f4, - 0x0007f1f4, - 0x0203f089, - 0xbd000fd0, - 0x0007f104, - 0x0203f0c1, - 0xbd0002d0, - 0x0007f104, - 0x0203f083, - 0xbd0002d0, - 0x07f7f004, - 0x085e21f5, - 0xc00007f1, - 0xd00203f0, - 0x04bd0002, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x99f094bd, - 0x0007f108, - 0x0203f00f, - 0xbd0009d0, - 0x0007f104, - 0x0203f081, - 0xbd0002d0, - 0x0027f104, - 0x0023f100, - 0x0225f080, - 0x880007f1, - 0xd00203f0, - 0x04bd0002, - 0xf11017f0, - 0xf0020027, - 0x12fa0223, - 0xbd03f805, - 0x0899f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, - 0xb6810198, - 0x02981814, - 0x0825b680, - 0x800512fd, - 0x94bd1601, - 0xf10999f0, - 0xf00f0007, - 0x09d00203, - 0xf104bd00, - 0xf0810007, - 0x01d00203, - 0xf004bd00, - 0x07f10127, - 0x03f08800, - 0x0002d002, - 0x17f104bd, - 0x13f00100, - 0x0501fa06, - 0x94bd03f8, - 0xf10999f0, - 0xf0170007, - 0x09d00203, - 0xbd04bd00, - 0x0599f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x099a: ctx_chan */ - 0x21f500f8, - 0xa7f0087c, - 0xd021f40c, - 0xf505f7f0, - 0xf8085e21, -/* 0x09ad: ctx_mmio_exec */ - 0x41039800, - 0x810007f1, - 0xd00203f0, - 0x04bd0003, -/* 0x09be: ctx_mmio_loop */ - 0x34c434bd, - 0x0f1bf4ff, - 0x020057f1, - 0xfa0653f0, - 0x03f80535, -/* 0x09d0: ctx_mmio_pull */ - 0x98804e98, - 0x21f4814f, - 0x0830b69d, - 0xf40112b6, -/* 0x09e2: ctx_mmio_done */ - 0x0398df1b, - 0x0007f116, - 0x0203f081, - 0xbd0003d0, - 0x40008004, - 0x010017f1, - 0xfa0613f0, - 0x03f80601, -/* 0x0a02: ctx_xfer */ - 0xe7f000f8, - 0x0007f104, - 0x0303f002, - 0xbd000ed0, -/* 0x0a11: ctx_xfer_idle */ - 0x00e7f104, - 0x03e3f000, - 0xf100eecf, - 0xf42000e4, - 0x11f4f21b, - 0x0d02f406, -/* 0x0a28: ctx_xfer_pre */ - 0xf510f7f0, - 0xf4083621, -/* 0x0a32: ctx_xfer_pre_load */ - 0xf7f01c11, - 0xd721f502, - 0xe921f507, - 0xfe21f507, - 0xf5f4bd07, - 0xf507d721, -/* 0x0a4b: ctx_xfer_exec */ - 0x98087c21, - 0x24bd1601, - 0x050007f1, - 0xd00103f0, - 0x04bd0002, - 0xf1021fb9, - 0xf0a500e7, - 0x21f441e3, - 0x01fcf09d, - 0xb6022cf0, - 0xf2fd0124, - 0x02ffb905, - 0xa504e7f1, - 0xf441e3f0, - 0x21f59d21, - 0x24bd026a, - 0x47fc07f1, - 0xd00203f0, - 0x04bd0002, - 0xb6012cf0, - 0x07f10320, - 0x03f04afc, - 0x0002d002, - 0xacf004bd, - 0x06a5f001, - 0x9800b7f0, - 0x0d98000c, - 0x00e7f001, - 0x016f21f5, - 0xf508a7f0, - 0xf5011021, - 0xf4025e21, - 0xa7f01301, - 0xd021f40c, - 0xf505f7f0, - 0xf4085e21, -/* 0x0ada: ctx_xfer_post */ - 0xf7f02e02, - 0xd721f502, - 0xf5f4bd07, - 0xf5083621, - 0xf5027f21, - 0xbd07e921, - 0xd721f5f4, - 0x1011f407, - 0xfd400198, - 0x0bf40511, - 0xad21f507, -/* 0x0b05: ctx_xfer_no_post_mmio */ -/* 0x0b05: ctx_xfer_done */ - 0x0000f809, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3 deleted file mode 100644 index ec42ed29b50d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3 +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define CHIPSET GK110 -#include "macros.fuc" - -.section #nvf0_grhub_data -#define INCLUDE_DATA -#include "com.fuc" -#include "hub.fuc" -#undef INCLUDE_DATA - -.section #nvf0_grhub_code -#define INCLUDE_CODE -bra #init -#include "com.fuc" -#include "hub.fuc" -.align 256 -#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h deleted file mode 100644 index a0af4b703a8e..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h +++ /dev/null @@ -1,1044 +0,0 @@ -uint32_t nvf0_grhub_data[] = { -/* 0x0000: hub_mmio_list_head */ - 0x00000300, -/* 0x0004: hub_mmio_list_tail */ - 0x00000304, -/* 0x0008: gpc_count */ - 0x00000000, -/* 0x000c: rop_count */ - 0x00000000, -/* 0x0010: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: ctx_current */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0100: chan_data */ -/* 0x0100: chan_mmio_count */ - 0x00000000, -/* 0x0104: chan_mmio_address */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0200: xfer_data */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0300: hub_mmio_list_base */ - 0x0417e91c, -}; - -uint32_t nvf0_grhub_code[] = { - 0x039b0ef5, -/* 0x0004: queue_put */ - 0x9800d898, - 0x86f001d9, - 0x0489b808, - 0xf00c1bf4, - 0x21f502f7, - 0x00f8037e, -/* 0x001c: queue_put_next */ - 0xb60798c4, - 0x8dbb0384, - 0x0880b600, - 0x80008e80, - 0x90b6018f, - 0x0f94f001, - 0xf801d980, -/* 0x0039: queue_get */ - 0x0131f400, - 0x9800d898, - 0x89b801d9, - 0x210bf404, - 0xb60789c4, - 0x9dbb0394, - 0x0890b600, - 0x98009e98, - 0x80b6019f, - 0x0f84f001, - 0xf400d880, -/* 0x0066: queue_get_done */ - 0x00f80132, -/* 0x0068: nv_rd32 */ - 0xf002ecb9, - 0x07f11fc9, - 0x03f0ca00, - 0x000cd001, -/* 0x007a: nv_rd32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0xa7f0f31b, - 0x1021f506, - 0x00f7f101, - 0x01f3f0cb, - 0xf800ffcf, -/* 0x009d: nv_wr32 */ - 0x0007f100, - 0x0103f0cc, - 0xbd000fd0, - 0x02ecb904, - 0xf01fc9f0, - 0x07f11ec9, - 0x03f0ca00, - 0x000cd001, -/* 0x00be: nv_wr32_wait */ - 0xc7f104bd, - 0xc3f0ca00, - 0x00cccf01, - 0xf41fccc8, - 0x00f8f31b, -/* 0x00d0: wait_donez */ - 0x99f094bd, - 0x0007f100, - 0x0203f037, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x00ed: wait_donez_ne */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x1bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0110: wait_doneo */ - 0x99f094bd, - 0x0007f100, - 0x0203f037, - 0xbd0009d0, - 0x0007f104, - 0x0203f006, - 0xbd000ad0, -/* 0x012d: wait_doneo_e */ - 0x0087f104, - 0x0183f000, - 0xff0088cf, - 0x0bf4888a, - 0xf094bdf3, - 0x07f10099, - 0x03f01700, - 0x0009d002, - 0x00f804bd, -/* 0x0150: mmctx_size */ -/* 0x0152: nv_mmctx_size_loop */ - 0xe89894bd, - 0x1a85b600, - 0xb60180b6, - 0x98bb0284, - 0x04e0b600, - 0xf404efb8, - 0x9fb9eb1b, -/* 0x016f: mmctx_xfer */ - 0xbd00f802, - 0x0199f094, - 0x370007f1, - 0xd00203f0, - 0x04bd0009, - 0xbbfd94bd, - 0x120bf405, - 0xc40007f1, - 0xd00103f0, - 0x04bd000b, -/* 0x0197: mmctx_base_disabled */ - 0xfd0099f0, - 0x0bf405ee, - 0x0007f11e, - 0x0103f0c6, - 0xbd000ed0, - 0x0007f104, - 0x0103f0c7, - 0xbd000fd0, - 0x0199f004, -/* 0x01b8: mmctx_multi_disabled */ - 0xb600abc8, - 0xb9f010b4, - 0x01aec80c, - 0xfd11e4b6, - 0x07f105be, - 0x03f0c500, - 0x000bd001, -/* 0x01d6: mmctx_exec_loop */ -/* 0x01d6: mmctx_wait_free */ - 0xe7f104bd, - 0xe3f0c500, - 0x00eecf01, - 0xf41fe4f0, - 0xce98f30b, - 0x05e9fd00, - 0xc80007f1, - 0xd00103f0, - 0x04bd000e, - 0xb804c0b6, - 0x1bf404cd, - 0x02abc8d8, -/* 0x0207: mmctx_fini_wait */ - 0xf11f1bf4, - 0xf0c500b7, - 0xbbcf01b3, - 0x1fb4f000, - 0xf410b4b0, - 0xa7f0f01b, - 0xd021f405, -/* 0x0223: mmctx_stop */ - 0xc82b0ef4, - 0xb4b600ab, - 0x0cb9f010, - 0xf112b9f0, - 0xf0c50007, - 0x0bd00103, -/* 0x023b: mmctx_stop_wait */ - 0xf104bd00, - 0xf0c500b7, - 0xbbcf01b3, - 0x12bbc800, -/* 0x024b: mmctx_done */ - 0xbdf31bf4, - 0x0199f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x025e: strand_wait */ - 0xa0f900f8, - 0xf402a7f0, - 0xa0fcd021, -/* 0x026a: strand_pre */ - 0x97f000f8, - 0xfc07f10c, - 0x0203f04a, - 0xbd0009d0, - 0x5e21f504, -/* 0x027f: strand_post */ - 0xf000f802, - 0x07f10d97, - 0x03f04afc, - 0x0009d002, - 0x21f504bd, - 0x00f8025e, -/* 0x0294: strand_set */ - 0xf10fc7f0, - 0xf04ffc07, - 0x0cd00203, - 0xf004bd00, - 0x07f10bc7, - 0x03f04afc, - 0x000cd002, - 0x07f104bd, - 0x03f04ffc, - 0x000ed002, - 0xc7f004bd, - 0xfc07f10a, - 0x0203f04a, - 0xbd000cd0, - 0x5e21f504, -/* 0x02d3: strand_ctx_init */ - 0xbd00f802, - 0x0399f094, - 0x370007f1, - 0xd00203f0, - 0x04bd0009, - 0x026a21f5, - 0xf503e7f0, - 0xbd029421, - 0xfc07f1c4, - 0x0203f047, - 0xbd000cd0, - 0x01c7f004, - 0x4afc07f1, - 0xd00203f0, - 0x04bd000c, - 0x025e21f5, - 0xf1010c92, - 0xf046fc07, - 0x0cd00203, - 0xf004bd00, - 0x07f102c7, - 0x03f04afc, - 0x000cd002, - 0x21f504bd, - 0x21f5025e, - 0x87f1027f, - 0x83f04200, - 0x0097f102, - 0x0293f020, - 0x950099cf, -/* 0x034a: ctx_init_strand_loop */ - 0x8ed008fe, - 0x408ed000, - 0xb6808acf, - 0xa0b606a5, - 0x00eabb01, - 0xb60480b6, - 0x1bf40192, - 0x08e4b6e8, - 0xbdf2efbc, - 0x0399f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x037e: error */ - 0x07f100f8, - 0x03f00500, - 0x000fd002, - 0xf7f004bd, - 0x0007f101, - 0x0303f007, - 0xbd000fd0, -/* 0x039b: init */ - 0xbd00f804, - 0x0007fe04, - 0x420017f1, - 0xcf0013f0, - 0x11e70011, - 0x14b60109, - 0x0014fe08, - 0xf10227f0, - 0xf0120007, - 0x02d00003, - 0xf104bd00, - 0xfe06c817, - 0x24bd0010, - 0x070007f1, - 0xd00003f0, - 0x04bd0002, - 0x200327f1, - 0x010007f1, - 0xd00103f0, - 0x04bd0002, - 0x200427f1, - 0x010407f1, - 0xd00103f0, - 0x04bd0002, - 0x200b27f1, - 0x010807f1, - 0xd00103f0, - 0x04bd0002, - 0x200c27f1, - 0x011c07f1, - 0xd00103f0, - 0x04bd0002, - 0xf1010392, - 0xf0090007, - 0x03d00303, - 0xf104bd00, - 0xf0870427, - 0x07f10023, - 0x03f00400, - 0x0002d000, - 0x27f004bd, - 0x0007f104, - 0x0003f003, - 0xbd0002d0, - 0x1031f404, - 0x9604e7f1, - 0xf440e3f0, - 0xfeb96821, - 0x90f1c702, - 0xf0030180, - 0x0f801ff4, - 0x0117f002, - 0xb6041fbb, - 0x07f10112, - 0x03f00300, - 0x0001d001, - 0x07f104bd, - 0x03f00400, - 0x0001d001, - 0x17f104bd, - 0xf7f00100, - 0xd721f502, - 0xe921f507, - 0x10f7f007, - 0x083621f5, - 0x98000e98, - 0x21f5010f, - 0x14950150, - 0x0007f108, - 0x0103f0c0, - 0xbd0004d0, - 0x0007f104, - 0x0103f0c1, - 0xbd0004d0, - 0x0030b704, - 0x001fbb13, - 0xf102f5b6, - 0xf0d30007, - 0x0fd00103, - 0xb604bd00, - 0x10b60815, - 0x0814b601, - 0xf5021fb9, - 0xbb02d321, - 0x0398001f, - 0x0047f102, - 0x5043f020, -/* 0x04f4: init_gpc */ - 0x08044ea0, - 0xf4021fb9, - 0x4ea09d21, - 0xf4bd010c, - 0xa09d21f4, - 0xf401044e, - 0x4ea09d21, - 0xf7f00100, - 0x9d21f402, - 0x08004ea0, -/* 0x051c: init_gpc_wait */ - 0xc86821f4, - 0x0bf41fff, - 0x044ea0fa, - 0x6821f408, - 0xb7001fbb, - 0xb6800040, - 0x1bf40132, - 0x00f7f0be, - 0x083621f5, - 0xf500f7f0, - 0xf107d721, - 0xf0010007, - 0x01d00203, - 0xbd04bd00, - 0x1f19f014, - 0x300007f1, - 0xd00203f0, - 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, - 0x3921f410, - 0xb1f401f4, - 0xf54001e4, - 0xbd00e91b, - 0x0499f094, - 0x370007f1, - 0xd00203f0, - 0x04bd0009, - 0xc00017f1, - 0xcf0213f0, - 0x27f10011, - 0x23f0c100, - 0x0022cf02, - 0xf51f13c8, - 0xc800890b, - 0x0bf41f23, - 0xb920f962, - 0x94bd0212, - 0xf10799f0, - 0xf0370007, - 0x09d00203, - 0xf404bd00, - 0x31f40132, - 0x0221f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x20fc04bd, - 0x99f094bd, - 0x0007f106, - 0x0203f037, - 0xbd0009d0, - 0x0131f404, - 0x0a0221f5, - 0x99f094bd, - 0x0007f106, - 0x0203f017, - 0xbd0009d0, - 0x330ef404, -/* 0x060c: chsw_prev_no_next */ - 0x12b920f9, - 0x0132f402, - 0xf50232f4, - 0xfc0a0221, - 0x0007f120, - 0x0203f0c0, - 0xbd0002d0, - 0x130ef404, -/* 0x062c: chsw_no_prev */ - 0xf41f23c8, - 0x31f40d0b, - 0x0232f401, - 0x0a0221f5, -/* 0x063c: chsw_done */ - 0xf10127f0, - 0xf0c30007, - 0x02d00203, - 0xbd04bd00, - 0x0499f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, - 0xff080ef5, -/* 0x0660: main_not_ctx_switch */ - 0xf401e4b0, - 0xf2b90d1b, - 0x9a21f502, - 0x460ef409, -/* 0x0670: main_not_ctx_chan */ - 0xf402e4b0, - 0x94bd321b, - 0xf10799f0, - 0xf0370007, - 0x09d00203, - 0xf404bd00, - 0x32f40132, - 0x0221f502, - 0xf094bd0a, - 0x07f10799, - 0x03f01700, - 0x0009d002, - 0x0ef404bd, -/* 0x06a5: main_not_ctx_save */ - 0x10ef9411, - 0xf501f5f0, - 0xf5037e21, -/* 0x06b3: main_done */ - 0xbdfeb50e, - 0x1f29f024, - 0x300007f1, - 0xd00203f0, - 0x04bd0002, - 0xfea00ef5, -/* 0x06c8: ih */ - 0x88fe80f9, - 0xf980f901, - 0xf9a0f990, - 0xf9d0f9b0, - 0xbdf0f9e0, - 0x00a7f104, - 0x00a3f002, - 0xc400aacf, - 0x0bf404ab, - 0x10d7f030, - 0x1a00e7f1, - 0xcf00e3f0, - 0xf7f100ee, - 0xf3f01900, - 0x00ffcf00, - 0xb70421f4, - 0xf00400b0, - 0x07f101e7, - 0x03f01d00, - 0x000ed000, -/* 0x071a: ih_no_fifo */ - 0xabe404bd, - 0x0bf40100, - 0x10d7f00d, - 0x4001e7f1, -/* 0x072b: ih_no_ctxsw */ - 0xe40421f4, - 0xf40400ab, - 0xe7f16c0b, - 0xe3f00708, - 0x6821f440, - 0xf102ffb9, - 0xf0040007, - 0x0fd00203, - 0xf104bd00, - 0xf00704e7, - 0x21f440e3, - 0x02ffb968, - 0x030007f1, - 0xd00203f0, - 0x04bd000f, - 0x9450fec7, - 0xf7f102ee, - 0xf3f00700, - 0x00efbb40, - 0xf16821f4, - 0xf0020007, - 0x0fd00203, - 0xf004bd00, - 0x21f503f7, - 0xb7f1037e, - 0xbfb90100, - 0x44e7f102, - 0x40e3f001, -/* 0x079b: ih_no_fwmthd */ - 0xf19d21f4, - 0xbd0504b7, - 0xb4abffb0, - 0xf10f0bf4, - 0xf0070007, - 0x0bd00303, -/* 0x07b3: ih_no_other */ - 0xf104bd00, - 0xf0010007, - 0x0ad00003, - 0xfc04bd00, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x07d7: ctx_4170s */ - 0xf001f800, - 0xffb910f5, - 0x70e7f102, - 0x40e3f041, - 0xf89d21f4, -/* 0x07e9: ctx_4170w */ - 0x70e7f100, - 0x40e3f041, - 0xb96821f4, - 0xf4f002ff, - 0xf01bf410, -/* 0x07fe: ctx_redswitch */ - 0xe7f100f8, - 0xe5f00200, - 0x20e5f040, - 0xf110e5f0, - 0xf0850007, - 0x0ed00103, - 0xf004bd00, -/* 0x081a: ctx_redswitch_delay */ - 0xf2b608f7, - 0xfd1bf401, - 0x0400e5f1, - 0x0100e5f1, - 0x850007f1, - 0xd00103f0, - 0x04bd000e, -/* 0x0836: ctx_86c */ - 0x07f100f8, - 0x03f02300, - 0x000fd002, - 0xffb904bd, - 0x14e7f102, - 0x40e3f08a, - 0xb99d21f4, - 0xe7f102ff, - 0xe3f0a88c, - 0x9d21f441, -/* 0x085e: ctx_mem */ - 0x07f100f8, - 0x03f08400, - 0x000fd002, -/* 0x086a: ctx_mem_wait */ - 0xf7f104bd, - 0xf3f08400, - 0x00ffcf02, - 0xf405fffd, - 0x00f8f31b, -/* 0x087c: ctx_load */ - 0x99f094bd, - 0x0007f105, - 0x0203f037, - 0xbd0009d0, - 0x0ca7f004, - 0xbdd021f4, - 0x0007f1f4, - 0x0203f089, - 0xbd000fd0, - 0x0007f104, - 0x0203f0c1, - 0xbd0002d0, - 0x0007f104, - 0x0203f083, - 0xbd0002d0, - 0x07f7f004, - 0x085e21f5, - 0xc00007f1, - 0xd00203f0, - 0x04bd0002, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x99f094bd, - 0x0007f108, - 0x0203f037, - 0xbd0009d0, - 0x0007f104, - 0x0203f081, - 0xbd0002d0, - 0x0027f104, - 0x0023f100, - 0x0225f080, - 0x880007f1, - 0xd00203f0, - 0x04bd0002, - 0xf11017f0, - 0xf0020027, - 0x12fa0223, - 0xbd03f805, - 0x0899f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, - 0xb6810198, - 0x02981814, - 0x0825b680, - 0x800512fd, - 0x94bd1601, - 0xf10999f0, - 0xf0370007, - 0x09d00203, - 0xf104bd00, - 0xf0810007, - 0x01d00203, - 0xf004bd00, - 0x07f10127, - 0x03f08800, - 0x0002d002, - 0x17f104bd, - 0x13f00100, - 0x0501fa06, - 0x94bd03f8, - 0xf10999f0, - 0xf0170007, - 0x09d00203, - 0xbd04bd00, - 0x0599f094, - 0x170007f1, - 0xd00203f0, - 0x04bd0009, -/* 0x099a: ctx_chan */ - 0x21f500f8, - 0xa7f0087c, - 0xd021f40c, - 0xf505f7f0, - 0xf8085e21, -/* 0x09ad: ctx_mmio_exec */ - 0x41039800, - 0x810007f1, - 0xd00203f0, - 0x04bd0003, -/* 0x09be: ctx_mmio_loop */ - 0x34c434bd, - 0x0f1bf4ff, - 0x020057f1, - 0xfa0653f0, - 0x03f80535, -/* 0x09d0: ctx_mmio_pull */ - 0x98804e98, - 0x21f4814f, - 0x0830b69d, - 0xf40112b6, -/* 0x09e2: ctx_mmio_done */ - 0x0398df1b, - 0x0007f116, - 0x0203f081, - 0xbd0003d0, - 0x40008004, - 0x010017f1, - 0xfa0613f0, - 0x03f80601, -/* 0x0a02: ctx_xfer */ - 0xe7f000f8, - 0x0007f104, - 0x0303f002, - 0xbd000ed0, -/* 0x0a11: ctx_xfer_idle */ - 0x00e7f104, - 0x03e3f000, - 0xf100eecf, - 0xf42000e4, - 0x11f4f21b, - 0x0d02f406, -/* 0x0a28: ctx_xfer_pre */ - 0xf510f7f0, - 0xf4083621, -/* 0x0a32: ctx_xfer_pre_load */ - 0xf7f01c11, - 0xd721f502, - 0xe921f507, - 0xfe21f507, - 0xf5f4bd07, - 0xf507d721, -/* 0x0a4b: ctx_xfer_exec */ - 0x98087c21, - 0x24bd1601, - 0x050007f1, - 0xd00103f0, - 0x04bd0002, - 0xf1021fb9, - 0xf0a500e7, - 0x21f441e3, - 0x01fcf09d, - 0xb6022cf0, - 0xf2fd0124, - 0x02ffb905, - 0xa504e7f1, - 0xf441e3f0, - 0x21f59d21, - 0x24bd026a, - 0x47fc07f1, - 0xd00203f0, - 0x04bd0002, - 0xb6012cf0, - 0x07f10320, - 0x03f04afc, - 0x0002d002, - 0xacf004bd, - 0x06a5f001, - 0x9800b7f0, - 0x0d98000c, - 0x00e7f001, - 0x016f21f5, - 0xf508a7f0, - 0xf5011021, - 0xf4025e21, - 0xa7f01301, - 0xd021f40c, - 0xf505f7f0, - 0xf4085e21, -/* 0x0ada: ctx_xfer_post */ - 0xf7f02e02, - 0xd721f502, - 0xf5f4bd07, - 0xf5083621, - 0xf5027f21, - 0xbd07e921, - 0xd721f5f4, - 0x1011f407, - 0xfd400198, - 0x0bf40511, - 0xad21f507, -/* 0x0b05: ctx_xfer_no_post_mmio */ -/* 0x0b05: ctx_xfer_done */ - 0x0000f809, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc deleted file mode 100644 index 2a0b0f844299..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "os.h" - -#define GF100 0xc0 -#define GF117 0xd7 -#define GK100 0xe0 -#define GK110 0xf0 -#define GK208 0x108 - -#define NV_PGRAPH_TRAPPED_ADDR 0x400704 -#define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 -#define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c - -#define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700) - -#define NV_PGRAPH_FECS_INTR_ACK 0x409004 -#define NV_PGRAPH_FECS_INTR 0x409008 -#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 -#define NV_PGRAPH_FECS_INTR_CHSW 0x00000100 -#define NV_PGRAPH_FECS_INTR_FIFO 0x00000004 -#define NV_PGRAPH_FECS_INTR_MODE 0x40900c -#define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004 -#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004 -#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000 -#define NV_PGRAPH_FECS_INTR_EN_SET 0x409010 -#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004 -#define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c -#define NV_PGRAPH_FECS_ACCESS 0x409048 -#define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002 -#define NV_PGRAPH_FECS_FIFO_DATA 0x409064 -#define NV_PGRAPH_FECS_FIFO_CMD 0x409068 -#define NV_PGRAPH_FECS_FIFO_ACK 0x409074 -#define NV_PGRAPH_FECS_CAPS 0x409108 -#define NV_PGRAPH_FECS_SIGNAL 0x409400 -#define NV_PGRAPH_FECS_IROUTE 0x409404 -#define NV_PGRAPH_FECS_BAR_MASK0 0x40940c -#define NV_PGRAPH_FECS_BAR_MASK1 0x409410 -#define NV_PGRAPH_FECS_BAR 0x409414 -#define NV_PGRAPH_FECS_BAR_SET 0x409418 -#define NV_PGRAPH_FECS_RED_SWITCH 0x409614 -#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400 -#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200 -#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100 -#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040 -#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020 -#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010 -#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002 -#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001 -#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 -#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 -#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c -#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 -#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 -#define NV_PGRAPH_FECS_MMCTX_BASE 0x409710 -#define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714 -#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718 -#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c -#define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720 -#define NV_PGRAPH_FECS_MMIO_CTRL 0x409728 -#define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c -#define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730 -#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c -#if CHIPSET < GK110 -#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) -#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) -#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) -#define NV_PGRAPH_FECS_UNK86C 0x40986c -#else -#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) -#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) -#define NV_PGRAPH_FECS_UNK86C 0x40988c -#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) -#endif -#define NV_PGRAPH_FECS_STRANDS_CNT 0x409880 -#define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908 -#define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c -#define NV_PGRAPH_FECS_STRAND_WORDS 0x409910 -#define NV_PGRAPH_FECS_STRAND_DATA 0x409918 -#define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c -#define NV_PGRAPH_FECS_STRAND_CMD 0x409928 -#define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001 -#define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002 -#define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003 -#define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004 -#define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a -#define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b -#define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c -#define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d -#define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c -#define NV_PGRAPH_FECS_MEM_BASE 0x409a04 -#define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c -#define NV_PGRAPH_FECS_MEM_CMD 0x409a10 -#define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007 -#define NV_PGRAPH_FECS_MEM_TARGET 0x409a20 -#define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000 -#define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f -#define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001 -#define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002 -#define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00 -#define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04 -#define NV_PGRAPH_FECS_CHSW 0x409b0c -#define NV_PGRAPH_FECS_CHSW_ACK 0x00000001 -#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c -#define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24 - -#define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004 -#define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008 -#define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004 -#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010 -#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004 -#define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c -#define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048 -#define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002 -#define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064 -#define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068 -#define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074 -#define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608 -#define NV_PGRAPH_GPCX_GPCCS_CAPS 0x41a108 -#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614 -#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800 -#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200 -#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020 -#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002 -#define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618 -#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700 -#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704 -#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c -#if CHIPSET < GK110 -#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) -#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) -#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) -#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c -#else -#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) -#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) -#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c -#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) -#endif -#define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c -#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928 -#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003 -#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004 -#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04 - -#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) -#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) - -#define T_WAIT 0 -#define T_MMCTX 1 -#define T_STRWAIT 2 -#define T_STRINIT 3 -#define T_AUTO 4 -#define T_CHAN 5 -#define T_LOAD 6 -#define T_SAVE 7 -#define T_LCHAN 8 -#define T_LCTXH 9 - -#if CHIPSET < GK208 -#define imm32(reg,val) /* -*/ movw reg ((val) & 0x0000ffff) /* -*/ sethi reg ((val) & 0xffff0000) -#else -#define imm32(reg,val) /* -*/ mov reg (val) -#endif - -#define nv_mkio(rv,r,i) /* -*/ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2)) - -#define hash # -#define fn(a) a -#if CHIPSET < GK208 -#define call(a) call fn(hash)a -#else -#define call(a) lcall fn(hash)a -#endif - -#define nv_iord(rv,r,i) /* -*/ nv_mkio(rv,r,i) /* -*/ iord rv I[rv] - -#define nv_iowr(r,i,rv) /* -*/ nv_mkio($r0,r,i) /* -*/ iowr I[$r0] rv /* -*/ clear b32 $r0 - -#define nv_rd32(reg,addr) /* -*/ imm32($r14, addr) /* -*/ call(nv_rd32) /* -*/ mov b32 reg $r15 - -#define nv_wr32(addr,reg) /* -*/ mov b32 $r15 reg /* -*/ imm32($r14, addr) /* -*/ call(nv_wr32) - -#define trace_set(bit) /* -*/ clear b32 $r9 /* -*/ bset $r9 bit /* -*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) - -#define trace_clr(bit) /* -*/ clear b32 $r9 /* -*/ bset $r9 bit /* -*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h deleted file mode 100644 index 1718ae4e8224..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __NVKM_GRAPH_OS_H__ -#define __NVKM_GRAPH_OS_H__ - -#define E_BAD_COMMAND 0x00000001 -#define E_CMD_OVERFLOW 0x00000002 -#define E_BAD_FWMTHD 0x00000003 - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c deleted file mode 100644 index d07b19dc168d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -gk110b_graph_init_l1c_0[] = { - { 0x419c98, 1, 0x04, 0x00000000 }, - { 0x419ca8, 1, 0x04, 0x00000000 }, - { 0x419cb0, 1, 0x04, 0x09000000 }, - { 0x419cb4, 1, 0x04, 0x00000000 }, - { 0x419cb8, 1, 0x04, 0x00b08bea }, - { 0x419c84, 1, 0x04, 0x00010384 }, - { 0x419cbc, 1, 0x04, 0x281b3646 }, - { 0x419cc0, 2, 0x04, 0x00000000 }, - { 0x419c80, 1, 0x04, 0x00020230 }, - { 0x419ccc, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gk110b_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000080 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ee4, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x00000000 }, - { 0x419eb4, 1, 0x04, 0x00000000 }, - { 0x419ebc, 2, 0x04, 0x00000000 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419ed0, 1, 0x04, 0x00002616 }, - { 0x419f74, 1, 0x04, 0x00015555 }, - { 0x419f80, 4, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -gk110b_graph_pack_mmio[] = { - { nve4_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvf0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvf0_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvf0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nvf0_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { gk110b_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { gk110b_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -struct nouveau_oclass * -gk110b_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xf1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = nvf0_graph_fini, - }, - .cclass = &gk110b_grctx_oclass, - .sclass = nvf0_graph_sclass, - .mmio = gk110b_graph_pack_mmio, - .fecs.ucode = &nvf0_graph_fecs_ucode, - .gpccs.ucode = &nvf0_graph_gpccs_ucode, - .ppc_nr = 2, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c deleted file mode 100644 index 7d0abe9f3fe7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -static struct nouveau_oclass -gk20a_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa040, &nouveau_object_ofuncs }, - { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -struct nouveau_oclass * -gk20a_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &gk20a_grctx_oclass, - .sclass = gk20a_graph_sclass, - .mmio = nve4_graph_pack_mmio, - .ppc_nr = 1, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c deleted file mode 100644 index 4bdbdab2fd9a..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -gm107_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa140, &nouveau_object_ofuncs }, - { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -gm107_graph_init_main_0[] = { - { 0x400080, 1, 0x04, 0x003003c2 }, - { 0x400088, 1, 0x04, 0x0001bfe7 }, - { 0x40008c, 1, 0x04, 0x00060000 }, - { 0x400090, 1, 0x04, 0x00000030 }, - { 0x40013c, 1, 0x04, 0x003901f3 }, - { 0x400140, 1, 0x04, 0x00000100 }, - { 0x400144, 1, 0x04, 0x00000000 }, - { 0x400148, 1, 0x04, 0x00000110 }, - { 0x400138, 1, 0x04, 0x00000000 }, - { 0x400130, 2, 0x04, 0x00000000 }, - { 0x400124, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405900, 1, 0x04, 0x00000000 }, - { 0x405908, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_scc_0[] = { - { 0x40803c, 1, 0x04, 0x00000010 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_sked_0[] = { - { 0x407010, 1, 0x04, 0x00000000 }, - { 0x407040, 1, 0x04, 0x40440424 }, - { 0x407048, 1, 0x04, 0x0000000a }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_prop_0[] = { - { 0x418408, 1, 0x04, 0x00000000 }, - { 0x4184a0, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_setup_1[] = { - { 0x4188c8, 2, 0x04, 0x00000000 }, - { 0x4188d0, 1, 0x04, 0x00010000 }, - { 0x4188d4, 1, 0x04, 0x00010201 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_zcull_0[] = { - { 0x418910, 1, 0x04, 0x00010001 }, - { 0x418914, 1, 0x04, 0x00000301 }, - { 0x418918, 1, 0x04, 0x00800000 }, - { 0x418930, 2, 0x04, 0x00000000 }, - { 0x418980, 1, 0x04, 0x77777770 }, - { 0x418984, 3, 0x04, 0x77777777 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_gpc_unk_1[] = { - { 0x418d00, 1, 0x04, 0x00000000 }, - { 0x418f00, 1, 0x04, 0x00000400 }, - { 0x418f08, 1, 0x04, 0x00000000 }, - { 0x418e08, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_tpccs_0[] = { - { 0x419dc4, 1, 0x04, 0x00000000 }, - { 0x419dc8, 1, 0x04, 0x00000501 }, - { 0x419dd0, 1, 0x04, 0x00000000 }, - { 0x419dd4, 1, 0x04, 0x00000100 }, - { 0x419dd8, 1, 0x04, 0x00000001 }, - { 0x419ddc, 1, 0x04, 0x00000002 }, - { 0x419de0, 1, 0x04, 0x00000001 }, - { 0x419d0c, 1, 0x04, 0x00000000 }, - { 0x419d10, 1, 0x04, 0x00000014 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_tex_0[] = { - { 0x419ab0, 1, 0x04, 0x00000000 }, - { 0x419ab8, 1, 0x04, 0x000000e7 }, - { 0x419abc, 1, 0x04, 0x00000000 }, - { 0x419acc, 1, 0x04, 0x000000ff }, - { 0x419ac0, 1, 0x04, 0x00000000 }, - { 0x419aa8, 2, 0x04, 0x00000000 }, - { 0x419ad0, 2, 0x04, 0x00000000 }, - { 0x419ae0, 2, 0x04, 0x00000000 }, - { 0x419af0, 4, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_pe_0[] = { - { 0x419900, 1, 0x04, 0x000000ff }, - { 0x41980c, 1, 0x04, 0x00000010 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x419838, 1, 0x04, 0x000000ff }, - { 0x419850, 1, 0x04, 0x00000004 }, - { 0x419854, 2, 0x04, 0x00000000 }, - { 0x419894, 3, 0x04, 0x00100401 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_l1c_0[] = { - { 0x419c98, 1, 0x04, 0x00000000 }, - { 0x419cc0, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_sm_0[] = { - { 0x419e30, 1, 0x04, 0x000000ff }, - { 0x419e00, 1, 0x04, 0x00000000 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ee4, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x01000000 }, - { 0x419ee8, 1, 0x04, 0x00000091 }, - { 0x419eb4, 1, 0x04, 0x00000000 }, - { 0x419ebc, 2, 0x04, 0x00000000 }, - { 0x419edc, 1, 0x04, 0x000c1810 }, - { 0x419ed8, 1, 0x04, 0x00000000 }, - { 0x419ee0, 1, 0x04, 0x00000000 }, - { 0x419f74, 1, 0x04, 0x00005155 }, - { 0x419f80, 4, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_l1c_1[] = { - { 0x419ccc, 2, 0x04, 0x00000000 }, - { 0x419c80, 1, 0x04, 0x3f006022 }, - { 0x419c88, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_pes_0[] = { - { 0x41be50, 1, 0x04, 0x000000ff }, - { 0x41be04, 1, 0x04, 0x00000000 }, - { 0x41be08, 1, 0x04, 0x00000004 }, - { 0x41be0c, 1, 0x04, 0x00000008 }, - { 0x41be10, 1, 0x04, 0x0e3b8bc7 }, - { 0x41be14, 2, 0x04, 0x00000000 }, - { 0x41be3c, 5, 0x04, 0x00100401 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_wwdx_0[] = { - { 0x41bfd4, 1, 0x04, 0x00800000 }, - { 0x41bfdc, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_cbm_0[] = { - { 0x41becc, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_be_0[] = { - { 0x408890, 1, 0x04, 0x000000ff }, - { 0x40880c, 1, 0x04, 0x00000000 }, - { 0x408850, 1, 0x04, 0x00000004 }, - { 0x408878, 1, 0x04, 0x00c81603 }, - { 0x40887c, 1, 0x04, 0x80543432 }, - { 0x408880, 1, 0x04, 0x0010581e }, - { 0x408884, 1, 0x04, 0x00001205 }, - { 0x408974, 1, 0x04, 0x000000ff }, - { 0x408910, 9, 0x04, 0x00000000 }, - { 0x408950, 1, 0x04, 0x00000000 }, - { 0x408954, 1, 0x04, 0x0000ffff }, - { 0x408958, 1, 0x04, 0x00000034 }, - { 0x40895c, 1, 0x04, 0x8531a003 }, - { 0x408960, 1, 0x04, 0x0561985a }, - { 0x408964, 1, 0x04, 0x04e15c4f }, - { 0x408968, 1, 0x04, 0x02808833 }, - { 0x40896c, 1, 0x04, 0x01f02438 }, - { 0x408970, 1, 0x04, 0x00012c00 }, - { 0x408984, 1, 0x04, 0x00000000 }, - { 0x408988, 1, 0x04, 0x08040201 }, - { 0x40898c, 1, 0x04, 0x80402010 }, - {} -}; - -static const struct nvc0_graph_init -gm107_graph_init_sm_1[] = { - { 0x419e5c, 1, 0x04, 0x00000000 }, - { 0x419e58, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -gm107_graph_pack_mmio[] = { - { gm107_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { gm107_graph_init_ds_0 }, - { gm107_graph_init_scc_0 }, - { gm107_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { gm107_graph_init_prop_0 }, - { nv108_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { gm107_graph_init_setup_1 }, - { gm107_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { gm107_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { gm107_graph_init_tpccs_0 }, - { gm107_graph_init_tex_0 }, - { gm107_graph_init_pe_0 }, - { gm107_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { gm107_graph_init_sm_0 }, - { gm107_graph_init_l1c_1 }, - { gm107_graph_init_pes_0 }, - { gm107_graph_init_wwdx_0 }, - { gm107_graph_init_cbm_0 }, - { gm107_graph_init_be_0 }, - { gm107_graph_init_sm_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static void -gm107_graph_init_bios(struct nvc0_graph_priv *priv) -{ - static const struct { - u32 ctrl; - u32 data; - } regs[] = { - { 0x419ed8, 0x419ee0 }, - { 0x419ad0, 0x419ad4 }, - { 0x419ae0, 0x419ae4 }, - { 0x419af0, 0x419af4 }, - { 0x419af8, 0x419afc }, - }; - struct nouveau_bios *bios = nouveau_bios(priv); - struct nvbios_P0260E infoE; - struct nvbios_P0260X infoX; - int E = -1, X; - u8 ver, hdr; - - while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { - if (X = -1, E < ARRAY_SIZE(regs)) { - nv_wr32(priv, regs[E].ctrl, infoE.data); - while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) - nv_wr32(priv, regs[E].data, infoX.data); - } - } -} - -int -gm107_graph_init(struct nouveau_object *object) -{ - struct nvc0_graph_oclass *oclass = (void *)object->oclass; - struct nvc0_graph_priv *priv = (void *)object; - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); - u32 data[TPC_MAX / 8] = {}; - u8 tpcnr[GPC_MAX]; - int gpc, tpc, ppc, rop; - int ret, i; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); - - nvc0_graph_mmio(priv, oclass->mmio); - - gm107_graph_init_bios(priv); - - nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); - - memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - data[i / 8] |= tpc << ((i % 8) * 4); - } - - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); - } - - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - - nv_wr32(priv, 0x400500, 0x00010001); - - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - nv_wr32(priv, 0x400124, 0x00000002); - nv_wr32(priv, 0x409c24, 0x000e0000); - - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++) - nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); - } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); - } - - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); - } - - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); - - nv_wr32(priv, 0x400054, 0x2c350f63); - - nvc0_graph_zbc_init(priv); - - return nvc0_graph_init_ctxctl(priv); -} - -#include "fuc/hubgm107.fuc5.h" - -static struct nvc0_graph_ucode -gm107_graph_fecs_ucode = { - .code.data = gm107_grhub_code, - .code.size = sizeof(gm107_grhub_code), - .data.data = gm107_grhub_data, - .data.size = sizeof(gm107_grhub_data), -}; - -#include "fuc/gpcgm107.fuc5.h" - -static struct nvc0_graph_ucode -gm107_graph_gpccs_ucode = { - .code.data = gm107_grgpc_code, - .code.size = sizeof(gm107_grgpc_code), - .data.data = gm107_grgpc_data, - .data.size = sizeof(gm107_grgpc_data), -}; - -struct nouveau_oclass * -gm107_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0x07), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = gm107_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &gm107_grctx_oclass, - .sclass = gm107_graph_sclass, - .mmio = gm107_graph_pack_mmio, - .fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL, - .gpccs.ucode = &gm107_graph_gpccs_ucode, - .ppc_nr = 2, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c deleted file mode 100644 index f70e2f67a4dd..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c +++ /dev/null @@ -1,1388 +0,0 @@ -/* - * Copyright 2007 Stephane Marchesin - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "regs.h" - -static u32 -nv04_graph_ctx_regs[] = { - 0x0040053c, - 0x00400544, - 0x00400540, - 0x00400548, - NV04_PGRAPH_CTX_SWITCH1, - NV04_PGRAPH_CTX_SWITCH2, - NV04_PGRAPH_CTX_SWITCH3, - NV04_PGRAPH_CTX_SWITCH4, - NV04_PGRAPH_CTX_CACHE1, - NV04_PGRAPH_CTX_CACHE2, - NV04_PGRAPH_CTX_CACHE3, - NV04_PGRAPH_CTX_CACHE4, - 0x00400184, - 0x004001a4, - 0x004001c4, - 0x004001e4, - 0x00400188, - 0x004001a8, - 0x004001c8, - 0x004001e8, - 0x0040018c, - 0x004001ac, - 0x004001cc, - 0x004001ec, - 0x00400190, - 0x004001b0, - 0x004001d0, - 0x004001f0, - 0x00400194, - 0x004001b4, - 0x004001d4, - 0x004001f4, - 0x00400198, - 0x004001b8, - 0x004001d8, - 0x004001f8, - 0x0040019c, - 0x004001bc, - 0x004001dc, - 0x004001fc, - 0x00400174, - NV04_PGRAPH_DMA_START_0, - NV04_PGRAPH_DMA_START_1, - NV04_PGRAPH_DMA_LENGTH, - NV04_PGRAPH_DMA_MISC, - NV04_PGRAPH_DMA_PITCH, - NV04_PGRAPH_BOFFSET0, - NV04_PGRAPH_BBASE0, - NV04_PGRAPH_BLIMIT0, - NV04_PGRAPH_BOFFSET1, - NV04_PGRAPH_BBASE1, - NV04_PGRAPH_BLIMIT1, - NV04_PGRAPH_BOFFSET2, - NV04_PGRAPH_BBASE2, - NV04_PGRAPH_BLIMIT2, - NV04_PGRAPH_BOFFSET3, - NV04_PGRAPH_BBASE3, - NV04_PGRAPH_BLIMIT3, - NV04_PGRAPH_BOFFSET4, - NV04_PGRAPH_BBASE4, - NV04_PGRAPH_BLIMIT4, - NV04_PGRAPH_BOFFSET5, - NV04_PGRAPH_BBASE5, - NV04_PGRAPH_BLIMIT5, - NV04_PGRAPH_BPITCH0, - NV04_PGRAPH_BPITCH1, - NV04_PGRAPH_BPITCH2, - NV04_PGRAPH_BPITCH3, - NV04_PGRAPH_BPITCH4, - NV04_PGRAPH_SURFACE, - NV04_PGRAPH_STATE, - NV04_PGRAPH_BSWIZZLE2, - NV04_PGRAPH_BSWIZZLE5, - NV04_PGRAPH_BPIXEL, - NV04_PGRAPH_NOTIFY, - NV04_PGRAPH_PATT_COLOR0, - NV04_PGRAPH_PATT_COLOR1, - NV04_PGRAPH_PATT_COLORRAM+0x00, - NV04_PGRAPH_PATT_COLORRAM+0x04, - NV04_PGRAPH_PATT_COLORRAM+0x08, - NV04_PGRAPH_PATT_COLORRAM+0x0c, - NV04_PGRAPH_PATT_COLORRAM+0x10, - NV04_PGRAPH_PATT_COLORRAM+0x14, - NV04_PGRAPH_PATT_COLORRAM+0x18, - NV04_PGRAPH_PATT_COLORRAM+0x1c, - NV04_PGRAPH_PATT_COLORRAM+0x20, - NV04_PGRAPH_PATT_COLORRAM+0x24, - NV04_PGRAPH_PATT_COLORRAM+0x28, - NV04_PGRAPH_PATT_COLORRAM+0x2c, - NV04_PGRAPH_PATT_COLORRAM+0x30, - NV04_PGRAPH_PATT_COLORRAM+0x34, - NV04_PGRAPH_PATT_COLORRAM+0x38, - NV04_PGRAPH_PATT_COLORRAM+0x3c, - NV04_PGRAPH_PATT_COLORRAM+0x40, - NV04_PGRAPH_PATT_COLORRAM+0x44, - NV04_PGRAPH_PATT_COLORRAM+0x48, - NV04_PGRAPH_PATT_COLORRAM+0x4c, - NV04_PGRAPH_PATT_COLORRAM+0x50, - NV04_PGRAPH_PATT_COLORRAM+0x54, - NV04_PGRAPH_PATT_COLORRAM+0x58, - NV04_PGRAPH_PATT_COLORRAM+0x5c, - NV04_PGRAPH_PATT_COLORRAM+0x60, - NV04_PGRAPH_PATT_COLORRAM+0x64, - NV04_PGRAPH_PATT_COLORRAM+0x68, - NV04_PGRAPH_PATT_COLORRAM+0x6c, - NV04_PGRAPH_PATT_COLORRAM+0x70, - NV04_PGRAPH_PATT_COLORRAM+0x74, - NV04_PGRAPH_PATT_COLORRAM+0x78, - NV04_PGRAPH_PATT_COLORRAM+0x7c, - NV04_PGRAPH_PATT_COLORRAM+0x80, - NV04_PGRAPH_PATT_COLORRAM+0x84, - NV04_PGRAPH_PATT_COLORRAM+0x88, - NV04_PGRAPH_PATT_COLORRAM+0x8c, - NV04_PGRAPH_PATT_COLORRAM+0x90, - NV04_PGRAPH_PATT_COLORRAM+0x94, - NV04_PGRAPH_PATT_COLORRAM+0x98, - NV04_PGRAPH_PATT_COLORRAM+0x9c, - NV04_PGRAPH_PATT_COLORRAM+0xa0, - NV04_PGRAPH_PATT_COLORRAM+0xa4, - NV04_PGRAPH_PATT_COLORRAM+0xa8, - NV04_PGRAPH_PATT_COLORRAM+0xac, - NV04_PGRAPH_PATT_COLORRAM+0xb0, - NV04_PGRAPH_PATT_COLORRAM+0xb4, - NV04_PGRAPH_PATT_COLORRAM+0xb8, - NV04_PGRAPH_PATT_COLORRAM+0xbc, - NV04_PGRAPH_PATT_COLORRAM+0xc0, - NV04_PGRAPH_PATT_COLORRAM+0xc4, - NV04_PGRAPH_PATT_COLORRAM+0xc8, - NV04_PGRAPH_PATT_COLORRAM+0xcc, - NV04_PGRAPH_PATT_COLORRAM+0xd0, - NV04_PGRAPH_PATT_COLORRAM+0xd4, - NV04_PGRAPH_PATT_COLORRAM+0xd8, - NV04_PGRAPH_PATT_COLORRAM+0xdc, - NV04_PGRAPH_PATT_COLORRAM+0xe0, - NV04_PGRAPH_PATT_COLORRAM+0xe4, - NV04_PGRAPH_PATT_COLORRAM+0xe8, - NV04_PGRAPH_PATT_COLORRAM+0xec, - NV04_PGRAPH_PATT_COLORRAM+0xf0, - NV04_PGRAPH_PATT_COLORRAM+0xf4, - NV04_PGRAPH_PATT_COLORRAM+0xf8, - NV04_PGRAPH_PATT_COLORRAM+0xfc, - NV04_PGRAPH_PATTERN, - 0x0040080c, - NV04_PGRAPH_PATTERN_SHAPE, - 0x00400600, - NV04_PGRAPH_ROP3, - NV04_PGRAPH_CHROMA, - NV04_PGRAPH_BETA_AND, - NV04_PGRAPH_BETA_PREMULT, - NV04_PGRAPH_CONTROL0, - NV04_PGRAPH_CONTROL1, - NV04_PGRAPH_CONTROL2, - NV04_PGRAPH_BLEND, - NV04_PGRAPH_STORED_FMT, - NV04_PGRAPH_SOURCE_COLOR, - 0x00400560, - 0x00400568, - 0x00400564, - 0x0040056c, - 0x00400400, - 0x00400480, - 0x00400404, - 0x00400484, - 0x00400408, - 0x00400488, - 0x0040040c, - 0x0040048c, - 0x00400410, - 0x00400490, - 0x00400414, - 0x00400494, - 0x00400418, - 0x00400498, - 0x0040041c, - 0x0040049c, - 0x00400420, - 0x004004a0, - 0x00400424, - 0x004004a4, - 0x00400428, - 0x004004a8, - 0x0040042c, - 0x004004ac, - 0x00400430, - 0x004004b0, - 0x00400434, - 0x004004b4, - 0x00400438, - 0x004004b8, - 0x0040043c, - 0x004004bc, - 0x00400440, - 0x004004c0, - 0x00400444, - 0x004004c4, - 0x00400448, - 0x004004c8, - 0x0040044c, - 0x004004cc, - 0x00400450, - 0x004004d0, - 0x00400454, - 0x004004d4, - 0x00400458, - 0x004004d8, - 0x0040045c, - 0x004004dc, - 0x00400460, - 0x004004e0, - 0x00400464, - 0x004004e4, - 0x00400468, - 0x004004e8, - 0x0040046c, - 0x004004ec, - 0x00400470, - 0x004004f0, - 0x00400474, - 0x004004f4, - 0x00400478, - 0x004004f8, - 0x0040047c, - 0x004004fc, - 0x00400534, - 0x00400538, - 0x00400514, - 0x00400518, - 0x0040051c, - 0x00400520, - 0x00400524, - 0x00400528, - 0x0040052c, - 0x00400530, - 0x00400d00, - 0x00400d40, - 0x00400d80, - 0x00400d04, - 0x00400d44, - 0x00400d84, - 0x00400d08, - 0x00400d48, - 0x00400d88, - 0x00400d0c, - 0x00400d4c, - 0x00400d8c, - 0x00400d10, - 0x00400d50, - 0x00400d90, - 0x00400d14, - 0x00400d54, - 0x00400d94, - 0x00400d18, - 0x00400d58, - 0x00400d98, - 0x00400d1c, - 0x00400d5c, - 0x00400d9c, - 0x00400d20, - 0x00400d60, - 0x00400da0, - 0x00400d24, - 0x00400d64, - 0x00400da4, - 0x00400d28, - 0x00400d68, - 0x00400da8, - 0x00400d2c, - 0x00400d6c, - 0x00400dac, - 0x00400d30, - 0x00400d70, - 0x00400db0, - 0x00400d34, - 0x00400d74, - 0x00400db4, - 0x00400d38, - 0x00400d78, - 0x00400db8, - 0x00400d3c, - 0x00400d7c, - 0x00400dbc, - 0x00400590, - 0x00400594, - 0x00400598, - 0x0040059c, - 0x004005a8, - 0x004005ac, - 0x004005b0, - 0x004005b4, - 0x004005c0, - 0x004005c4, - 0x004005c8, - 0x004005cc, - 0x004005d0, - 0x004005d4, - 0x004005d8, - 0x004005dc, - 0x004005e0, - NV04_PGRAPH_PASSTHRU_0, - NV04_PGRAPH_PASSTHRU_1, - NV04_PGRAPH_PASSTHRU_2, - NV04_PGRAPH_DVD_COLORFMT, - NV04_PGRAPH_SCALED_FORMAT, - NV04_PGRAPH_MISC24_0, - NV04_PGRAPH_MISC24_1, - NV04_PGRAPH_MISC24_2, - 0x00400500, - 0x00400504, - NV04_PGRAPH_VALID1, - NV04_PGRAPH_VALID2, - NV04_PGRAPH_DEBUG_3 -}; - -struct nv04_graph_priv { - struct nouveau_graph base; - struct nv04_graph_chan *chan[16]; - spinlock_t lock; -}; - -struct nv04_graph_chan { - struct nouveau_object base; - int chid; - u32 nv04[ARRAY_SIZE(nv04_graph_ctx_regs)]; -}; - - -static inline struct nv04_graph_priv * -nv04_graph_priv(struct nv04_graph_chan *chan) -{ - return (void *)nv_object(chan)->engine; -} - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -/* - * Software methods, why they are needed, and how they all work: - * - * NV04 and NV05 keep most of the state in PGRAPH context itself, but some - * 2d engine settings are kept inside the grobjs themselves. The grobjs are - * 3 words long on both. grobj format on NV04 is: - * - * word 0: - * - bits 0-7: class - * - bit 12: color key active - * - bit 13: clip rect active - * - bit 14: if set, destination surface is swizzled and taken from buffer 5 - * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken - * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or - * NV03_CONTEXT_SURFACE_DST]. - * - bits 15-17: 2d operation [aka patch config] - * - bit 24: patch valid [enables rendering using this object] - * - bit 25: surf3d valid [for tex_tri and multitex_tri only] - * word 1: - * - bits 0-1: mono format - * - bits 8-13: color format - * - bits 16-31: DMA_NOTIFY instance - * word 2: - * - bits 0-15: DMA_A instance - * - bits 16-31: DMA_B instance - * - * On NV05 it's: - * - * word 0: - * - bits 0-7: class - * - bit 12: color key active - * - bit 13: clip rect active - * - bit 14: if set, destination surface is swizzled and taken from buffer 5 - * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken - * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or - * NV03_CONTEXT_SURFACE_DST]. - * - bits 15-17: 2d operation [aka patch config] - * - bits 20-22: dither mode - * - bit 24: patch valid [enables rendering using this object] - * - bit 25: surface_dst/surface_color/surf2d/surf3d valid - * - bit 26: surface_src/surface_zeta valid - * - bit 27: pattern valid - * - bit 28: rop valid - * - bit 29: beta1 valid - * - bit 30: beta4 valid - * word 1: - * - bits 0-1: mono format - * - bits 8-13: color format - * - bits 16-31: DMA_NOTIFY instance - * word 2: - * - bits 0-15: DMA_A instance - * - bits 16-31: DMA_B instance - * - * NV05 will set/unset the relevant valid bits when you poke the relevant - * object-binding methods with object of the proper type, or with the NULL - * type. It'll only allow rendering using the grobj if all needed objects - * are bound. The needed set of objects depends on selected operation: for - * example rop object is needed by ROP_AND, but not by SRCCOPY_AND. - * - * NV04 doesn't have these methods implemented at all, and doesn't have the - * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24 - * is set. So we have to emulate them in software, internally keeping the - * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04, - * but the last word isn't actually used for anything, we abuse it for this - * purpose. - * - * Actually, NV05 can optionally check bit 24 too, but we disable this since - * there's no use for it. - * - * For unknown reasons, NV04 implements surf3d binding in hardware as an - * exception. Also for unknown reasons, NV04 doesn't implement the clipping - * methods on the surf3d object, so we have to emulate them too. - */ - -static void -nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value) -{ - struct nv04_graph_priv *priv = (void *)object->engine; - int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; - u32 tmp; - - tmp = nv_ro32(object, 0x00); - tmp &= ~mask; - tmp |= value; - nv_wo32(object, 0x00, tmp); - - nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp); - nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); -} - -static void -nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value) -{ - int class, op, valid = 1; - u32 tmp, ctx1; - - ctx1 = nv_ro32(object, 0x00); - class = ctx1 & 0xff; - op = (ctx1 >> 15) & 7; - - tmp = nv_ro32(object, 0x0c); - tmp &= ~mask; - tmp |= value; - nv_wo32(object, 0x0c, tmp); - - /* check for valid surf2d/surf_dst/surf_color */ - if (!(tmp & 0x02000000)) - valid = 0; - /* check for valid surf_src/surf_zeta */ - if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000)) - valid = 0; - - switch (op) { - /* SRCCOPY_AND, SRCCOPY: no extra objects required */ - case 0: - case 3: - break; - /* ROP_AND: requires pattern and rop */ - case 1: - if (!(tmp & 0x18000000)) - valid = 0; - break; - /* BLEND_AND: requires beta1 */ - case 2: - if (!(tmp & 0x20000000)) - valid = 0; - break; - /* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */ - case 4: - case 5: - if (!(tmp & 0x40000000)) - valid = 0; - break; - } - - nv04_graph_set_ctx1(object, 0x01000000, valid << 24); -} - -static int -nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - u32 class = nv_ro32(object, 0) & 0xff; - u32 data = *(u32 *)args; - if (data > 5) - return 1; - /* Old versions of the objects only accept first three operations. */ - if (data > 2 && class < 0x40) - return 1; - nv04_graph_set_ctx1(object, 0x00038000, data << 15); - /* changing operation changes set of objects needed for validation */ - nv04_graph_set_ctx_val(object, 0, 0); - return 0; -} - -static int -nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv04_graph_priv *priv = (void *)object->engine; - u32 data = *(u32 *)args; - u32 min = data & 0xffff, max; - u32 w = data >> 16; - if (min & 0x8000) - /* too large */ - return 1; - if (w & 0x8000) - /* yes, it accepts negative for some reason. */ - w |= 0xffff0000; - max = min + w; - max &= 0x3ffff; - nv_wr32(priv, 0x40053c, min); - nv_wr32(priv, 0x400544, max); - return 0; -} - -static int -nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv04_graph_priv *priv = (void *)object->engine; - u32 data = *(u32 *)args; - u32 min = data & 0xffff, max; - u32 w = data >> 16; - if (min & 0x8000) - /* too large */ - return 1; - if (w & 0x8000) - /* yes, it accepts negative for some reason. */ - w |= 0xffff0000; - max = min + w; - max &= 0x3ffff; - nv_wr32(priv, 0x400540, min); - nv_wr32(priv, 0x400548, max); - return 0; -} - -static u16 -nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size) -{ - struct nouveau_instmem *imem = nouveau_instmem(object); - u32 inst = *(u32 *)args << 4; - return nv_ro32(imem, inst); -} - -static int -nv04_graph_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0); - return 0; - case 0x42: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0); - return 0; - case 0x42: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; - case 0x52: - nv04_graph_set_ctx1(object, 0x00004000, 0x00004000); - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; - } - return 1; -} - -static int -nv01_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x08000000, 0); - return 0; - case 0x18: - nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x08000000, 0); - return 0; - case 0x44: - nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_rop(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x10000000, 0); - return 0; - case 0x43: - nv04_graph_set_ctx_val(object, 0x10000000, 0x10000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_beta1(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x20000000, 0); - return 0; - case 0x12: - nv04_graph_set_ctx_val(object, 0x20000000, 0x20000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_beta4(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x40000000, 0); - return 0; - case 0x72: - nv04_graph_set_ctx_val(object, 0x40000000, 0x40000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x02000000, 0); - return 0; - case 0x58: - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x04000000, 0); - return 0; - case 0x59: - nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x02000000, 0); - return 0; - case 0x5a: - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; - } - return 1; -} - -static int -nv04_graph_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx_val(object, 0x04000000, 0); - return 0; - case 0x5b: - nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000); - return 0; - } - return 1; -} - -static int -nv01_graph_mthd_bind_clip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx1(object, 0x2000, 0); - return 0; - case 0x19: - nv04_graph_set_ctx1(object, 0x2000, 0x2000); - return 0; - } - return 1; -} - -static int -nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - switch (nv04_graph_mthd_bind_class(object, args, size)) { - case 0x30: - nv04_graph_set_ctx1(object, 0x1000, 0); - return 0; - /* Yes, for some reason even the old versions of objects - * accept 0x57 and not 0x17. Consistency be damned. - */ - case 0x57: - nv04_graph_set_ctx1(object, 0x1000, 0x1000); - return 0; - } - return 1; -} - -static struct nouveau_omthds -nv03_graph_gdi_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_patt }, - { 0x0188, 0x0188, nv04_graph_mthd_bind_rop }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_gdi_omthds[] = { - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv01_graph_blit_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_blit_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_iifc_omthds[] = { - { 0x0188, 0x0188, nv01_graph_mthd_bind_chroma }, - { 0x018c, 0x018c, nv01_graph_mthd_bind_clip }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_patt }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_rop }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 }, - { 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, - { 0x03e4, 0x03e4, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv01_graph_ifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_ifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv03_graph_sifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_sifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv03_graph_sifm_omthds[] = { - { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, - { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_sifm_omthds[] = { - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_surf3d_omthds[] = { - { 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h }, - { 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v }, - {} -}; - -static struct nouveau_omthds -nv03_graph_ttri_omthds[] = { - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta }, - {} -}; - -static struct nouveau_omthds -nv01_graph_prim_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static struct nouveau_omthds -nv04_graph_prim_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, - {} -}; - -static int -nv04_graph_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_gpuobj *obj; - int ret; - - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); - *pobject = nv_object(obj); - if (ret) - return ret; - - nv_wo32(obj, 0x00, nv_mclass(obj)); -#ifdef __BIG_ENDIAN - nv_mo32(obj, 0x00, 0x00080000, 0x00080000); -#endif - nv_wo32(obj, 0x04, 0x00000000); - nv_wo32(obj, 0x08, 0x00000000); - nv_wo32(obj, 0x0c, 0x00000000); - return 0; -} - -struct nouveau_ofuncs -nv04_graph_ofuncs = { - .ctor = nv04_graph_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, -}; - -static struct nouveau_oclass -nv04_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0017, &nv04_graph_ofuncs }, /* chroma */ - { 0x0018, &nv04_graph_ofuncs }, /* pattern (nv01) */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x001c, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* line */ - { 0x001d, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* tri */ - { 0x001e, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* rect */ - { 0x001f, &nv04_graph_ofuncs, nv01_graph_blit_omthds }, - { 0x0021, &nv04_graph_ofuncs, nv01_graph_ifc_omthds }, - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0036, &nv04_graph_ofuncs, nv03_graph_sifc_omthds }, - { 0x0037, &nv04_graph_ofuncs, nv03_graph_sifm_omthds }, - { 0x0038, &nv04_graph_ofuncs }, /* dvd subpicture */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0042, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x0048, &nv04_graph_ofuncs, nv03_graph_ttri_omthds }, - { 0x004a, &nv04_graph_ofuncs, nv04_graph_gdi_omthds }, - { 0x004b, &nv04_graph_ofuncs, nv03_graph_gdi_omthds }, - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x0053, &nv04_graph_ofuncs, nv04_graph_surf3d_omthds }, - { 0x0054, &nv04_graph_ofuncs }, /* ttri */ - { 0x0055, &nv04_graph_ofuncs }, /* mtri */ - { 0x0057, &nv04_graph_ofuncs }, /* chroma */ - { 0x0058, &nv04_graph_ofuncs }, /* surf_dst */ - { 0x0059, &nv04_graph_ofuncs }, /* surf_src */ - { 0x005a, &nv04_graph_ofuncs }, /* surf_color */ - { 0x005b, &nv04_graph_ofuncs }, /* surf_zeta */ - { 0x005c, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* line */ - { 0x005d, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* tri */ - { 0x005e, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* rect */ - { 0x005f, &nv04_graph_ofuncs, nv04_graph_blit_omthds }, - { 0x0060, &nv04_graph_ofuncs, nv04_graph_iifc_omthds }, - { 0x0061, &nv04_graph_ofuncs, nv04_graph_ifc_omthds }, - { 0x0064, &nv04_graph_ofuncs }, /* iifc (nv05) */ - { 0x0065, &nv04_graph_ofuncs }, /* ifc (nv05) */ - { 0x0066, &nv04_graph_ofuncs }, /* sifc (nv05) */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0076, &nv04_graph_ofuncs, nv04_graph_sifc_omthds }, - { 0x0077, &nv04_graph_ofuncs, nv04_graph_sifm_omthds }, - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static struct nv04_graph_chan * -nv04_graph_channel(struct nv04_graph_priv *priv) -{ - struct nv04_graph_chan *chan = NULL; - if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { - int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; - if (chid < ARRAY_SIZE(priv->chan)) - chan = priv->chan[chid]; - } - return chan; -} - -static int -nv04_graph_load_context(struct nv04_graph_chan *chan, int chid) -{ - struct nv04_graph_priv *priv = nv04_graph_priv(chan); - int i; - - for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) - nv_wr32(priv, nv04_graph_ctx_regs[i], chan->nv04[i]); - - nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100); - nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); - nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); - return 0; -} - -static int -nv04_graph_unload_context(struct nv04_graph_chan *chan) -{ - struct nv04_graph_priv *priv = nv04_graph_priv(chan); - int i; - - for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) - chan->nv04[i] = nv_rd32(priv, nv04_graph_ctx_regs[i]); - - nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000); - nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); - return 0; -} - -static void -nv04_graph_context_switch(struct nv04_graph_priv *priv) -{ - struct nv04_graph_chan *prev = NULL; - struct nv04_graph_chan *next = NULL; - unsigned long flags; - int chid; - - spin_lock_irqsave(&priv->lock, flags); - nv04_graph_idle(priv); - - /* If previous context is valid, we need to save it */ - prev = nv04_graph_channel(priv); - if (prev) - nv04_graph_unload_context(prev); - - /* load context for next channel */ - chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; - next = priv->chan[chid]; - if (next) - nv04_graph_load_context(next, chid); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) { - if (nv04_graph_ctx_regs[i] == reg) - return &chan->nv04[i]; - } - - return NULL; -} - -static int -nv04_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_fifo_chan *fifo = (void *)parent; - struct nv04_graph_priv *priv = (void *)engine; - struct nv04_graph_chan *chan; - unsigned long flags; - int ret; - - ret = nouveau_object_create(parent, engine, oclass, 0, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - spin_lock_irqsave(&priv->lock, flags); - if (priv->chan[fifo->chid]) { - *pobject = nv_object(priv->chan[fifo->chid]); - atomic_inc(&(*pobject)->refcount); - spin_unlock_irqrestore(&priv->lock, flags); - nouveau_object_destroy(&chan->base); - return 1; - } - - *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; - - priv->chan[fifo->chid] = chan; - chan->chid = fifo->chid; - spin_unlock_irqrestore(&priv->lock, flags); - return 0; -} - -static void -nv04_graph_context_dtor(struct nouveau_object *object) -{ - struct nv04_graph_priv *priv = (void *)object->engine; - struct nv04_graph_chan *chan = (void *)object; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - priv->chan[chan->chid] = NULL; - spin_unlock_irqrestore(&priv->lock, flags); - - nouveau_object_destroy(&chan->base); -} - -static int -nv04_graph_context_fini(struct nouveau_object *object, bool suspend) -{ - struct nv04_graph_priv *priv = (void *)object->engine; - struct nv04_graph_chan *chan = (void *)object; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv04_graph_channel(priv) == chan) - nv04_graph_unload_context(chan); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->lock, flags); - - return nouveau_object_fini(&chan->base, suspend); -} - -static struct nouveau_oclass -nv04_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_graph_context_ctor, - .dtor = nv04_graph_context_dtor, - .init = nouveau_object_init, - .fini = nv04_graph_context_fini, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -bool -nv04_graph_idle(void *obj) -{ - struct nouveau_graph *graph = nouveau_graph(obj); - u32 mask = 0xffffffff; - - if (nv_device(obj)->card_type == NV_40) - mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; - - if (!nv_wait(graph, NV04_PGRAPH_STATUS, mask, 0)) { - nv_error(graph, "idle timed out with status 0x%08x\n", - nv_rd32(graph, NV04_PGRAPH_STATUS)); - return false; - } - - return true; -} - -static const struct nouveau_bitfield -nv04_graph_intr_name[] = { - { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, - {} -}; - -static const struct nouveau_bitfield -nv04_graph_nstatus[] = { - { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, - { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, - { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, - { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }, - {} -}; - -const struct nouveau_bitfield -nv04_graph_nsource[] = { - { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, - { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, - { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, - { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" }, - { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" }, - { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" }, - { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" }, - { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" }, - { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" }, - { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" }, - { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" }, - { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" }, - { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" }, - { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" }, - { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" }, - { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" }, - { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" }, - { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" }, - { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" }, - {} -}; - -static void -nv04_graph_intr(struct nouveau_subdev *subdev) -{ - struct nv04_graph_priv *priv = (void *)subdev; - struct nv04_graph_chan *chan = NULL; - struct nouveau_namedb *namedb = NULL; - struct nouveau_handle *handle = NULL; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); - u32 chid = (addr & 0x0f000000) >> 24; - u32 subc = (addr & 0x0000e000) >> 13; - u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff; - u32 inst = (nv_rd32(priv, 0x40016c) & 0xffff) << 4; - u32 show = stat; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - chan = priv->chan[chid]; - if (chan) - namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); - spin_unlock_irqrestore(&priv->lock, flags); - - if (stat & NV_PGRAPH_INTR_NOTIFY) { - if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { - handle = nouveau_namedb_get_vinst(namedb, inst); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~NV_PGRAPH_INTR_NOTIFY; - } - } - - if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); - stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - nv04_graph_context_switch(priv); - } - - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); - - if (show) { - nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv04_graph_intr_name, show); - pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); - pr_cont(" nstatus:"); - nouveau_bitfield_print(nv04_graph_nstatus, nstatus); - pr_cont("\n"); - nv_error(priv, - "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nouveau_client_name(chan), subc, class, mthd, - data); - } - - nouveau_namedb_put(handle); -} - -static int -nv04_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv04_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv04_graph_intr; - nv_engine(priv)->cclass = &nv04_graph_cclass; - nv_engine(priv)->sclass = nv04_graph_sclass; - spin_lock_init(&priv->lock); - return 0; -} - -static int -nv04_graph_init(struct nouveau_object *object) -{ - struct nouveau_engine *engine = nv_engine(object); - struct nv04_graph_priv *priv = (void *)engine; - int ret; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - /* Enable PGRAPH interrupts */ - nv_wr32(priv, NV03_PGRAPH_INTR, 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_VALID1, 0); - nv_wr32(priv, NV04_PGRAPH_VALID2, 0); - /*nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x000001FF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x1231c000); - /*1231C000 blob, 001 haiku*/ - /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x72111100); - /*0x72111100 blob , 01 haiku*/ - /*nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f071); - /*haiku same*/ - - /*nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); - /*haiku and blob 10d4*/ - - nv_wr32(priv, NV04_PGRAPH_STATE , 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL , 0x10000100); - nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); - - /* These don't belong here, they're part of a per-channel context */ - nv_wr32(priv, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); - return 0; -} - -struct nouveau_oclass -nv04_graph_oclass = { - .handle = NV_ENGINE(GR, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_graph_ctor, - .dtor = _nouveau_graph_dtor, - .init = nv04_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c deleted file mode 100644 index 2b12b09683c8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c +++ /dev/null @@ -1,1319 +0,0 @@ -/* - * Copyright 2007 Matthieu CASTET - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include - -#include -#include - -#include "regs.h" - -struct pipe_state { - u32 pipe_0x0000[0x040/4]; - u32 pipe_0x0040[0x010/4]; - u32 pipe_0x0200[0x0c0/4]; - u32 pipe_0x4400[0x080/4]; - u32 pipe_0x6400[0x3b0/4]; - u32 pipe_0x6800[0x2f0/4]; - u32 pipe_0x6c00[0x030/4]; - u32 pipe_0x7000[0x130/4]; - u32 pipe_0x7400[0x0c0/4]; - u32 pipe_0x7800[0x0c0/4]; -}; - -static int nv10_graph_ctx_regs[] = { - NV10_PGRAPH_CTX_SWITCH(0), - NV10_PGRAPH_CTX_SWITCH(1), - NV10_PGRAPH_CTX_SWITCH(2), - NV10_PGRAPH_CTX_SWITCH(3), - NV10_PGRAPH_CTX_SWITCH(4), - NV10_PGRAPH_CTX_CACHE(0, 0), - NV10_PGRAPH_CTX_CACHE(0, 1), - NV10_PGRAPH_CTX_CACHE(0, 2), - NV10_PGRAPH_CTX_CACHE(0, 3), - NV10_PGRAPH_CTX_CACHE(0, 4), - NV10_PGRAPH_CTX_CACHE(1, 0), - NV10_PGRAPH_CTX_CACHE(1, 1), - NV10_PGRAPH_CTX_CACHE(1, 2), - NV10_PGRAPH_CTX_CACHE(1, 3), - NV10_PGRAPH_CTX_CACHE(1, 4), - NV10_PGRAPH_CTX_CACHE(2, 0), - NV10_PGRAPH_CTX_CACHE(2, 1), - NV10_PGRAPH_CTX_CACHE(2, 2), - NV10_PGRAPH_CTX_CACHE(2, 3), - NV10_PGRAPH_CTX_CACHE(2, 4), - NV10_PGRAPH_CTX_CACHE(3, 0), - NV10_PGRAPH_CTX_CACHE(3, 1), - NV10_PGRAPH_CTX_CACHE(3, 2), - NV10_PGRAPH_CTX_CACHE(3, 3), - NV10_PGRAPH_CTX_CACHE(3, 4), - NV10_PGRAPH_CTX_CACHE(4, 0), - NV10_PGRAPH_CTX_CACHE(4, 1), - NV10_PGRAPH_CTX_CACHE(4, 2), - NV10_PGRAPH_CTX_CACHE(4, 3), - NV10_PGRAPH_CTX_CACHE(4, 4), - NV10_PGRAPH_CTX_CACHE(5, 0), - NV10_PGRAPH_CTX_CACHE(5, 1), - NV10_PGRAPH_CTX_CACHE(5, 2), - NV10_PGRAPH_CTX_CACHE(5, 3), - NV10_PGRAPH_CTX_CACHE(5, 4), - NV10_PGRAPH_CTX_CACHE(6, 0), - NV10_PGRAPH_CTX_CACHE(6, 1), - NV10_PGRAPH_CTX_CACHE(6, 2), - NV10_PGRAPH_CTX_CACHE(6, 3), - NV10_PGRAPH_CTX_CACHE(6, 4), - NV10_PGRAPH_CTX_CACHE(7, 0), - NV10_PGRAPH_CTX_CACHE(7, 1), - NV10_PGRAPH_CTX_CACHE(7, 2), - NV10_PGRAPH_CTX_CACHE(7, 3), - NV10_PGRAPH_CTX_CACHE(7, 4), - NV10_PGRAPH_CTX_USER, - NV04_PGRAPH_DMA_START_0, - NV04_PGRAPH_DMA_START_1, - NV04_PGRAPH_DMA_LENGTH, - NV04_PGRAPH_DMA_MISC, - NV10_PGRAPH_DMA_PITCH, - NV04_PGRAPH_BOFFSET0, - NV04_PGRAPH_BBASE0, - NV04_PGRAPH_BLIMIT0, - NV04_PGRAPH_BOFFSET1, - NV04_PGRAPH_BBASE1, - NV04_PGRAPH_BLIMIT1, - NV04_PGRAPH_BOFFSET2, - NV04_PGRAPH_BBASE2, - NV04_PGRAPH_BLIMIT2, - NV04_PGRAPH_BOFFSET3, - NV04_PGRAPH_BBASE3, - NV04_PGRAPH_BLIMIT3, - NV04_PGRAPH_BOFFSET4, - NV04_PGRAPH_BBASE4, - NV04_PGRAPH_BLIMIT4, - NV04_PGRAPH_BOFFSET5, - NV04_PGRAPH_BBASE5, - NV04_PGRAPH_BLIMIT5, - NV04_PGRAPH_BPITCH0, - NV04_PGRAPH_BPITCH1, - NV04_PGRAPH_BPITCH2, - NV04_PGRAPH_BPITCH3, - NV04_PGRAPH_BPITCH4, - NV10_PGRAPH_SURFACE, - NV10_PGRAPH_STATE, - NV04_PGRAPH_BSWIZZLE2, - NV04_PGRAPH_BSWIZZLE5, - NV04_PGRAPH_BPIXEL, - NV10_PGRAPH_NOTIFY, - NV04_PGRAPH_PATT_COLOR0, - NV04_PGRAPH_PATT_COLOR1, - NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ - 0x00400904, - 0x00400908, - 0x0040090c, - 0x00400910, - 0x00400914, - 0x00400918, - 0x0040091c, - 0x00400920, - 0x00400924, - 0x00400928, - 0x0040092c, - 0x00400930, - 0x00400934, - 0x00400938, - 0x0040093c, - 0x00400940, - 0x00400944, - 0x00400948, - 0x0040094c, - 0x00400950, - 0x00400954, - 0x00400958, - 0x0040095c, - 0x00400960, - 0x00400964, - 0x00400968, - 0x0040096c, - 0x00400970, - 0x00400974, - 0x00400978, - 0x0040097c, - 0x00400980, - 0x00400984, - 0x00400988, - 0x0040098c, - 0x00400990, - 0x00400994, - 0x00400998, - 0x0040099c, - 0x004009a0, - 0x004009a4, - 0x004009a8, - 0x004009ac, - 0x004009b0, - 0x004009b4, - 0x004009b8, - 0x004009bc, - 0x004009c0, - 0x004009c4, - 0x004009c8, - 0x004009cc, - 0x004009d0, - 0x004009d4, - 0x004009d8, - 0x004009dc, - 0x004009e0, - 0x004009e4, - 0x004009e8, - 0x004009ec, - 0x004009f0, - 0x004009f4, - 0x004009f8, - 0x004009fc, - NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ - 0x0040080c, - NV04_PGRAPH_PATTERN_SHAPE, - NV03_PGRAPH_MONO_COLOR0, - NV04_PGRAPH_ROP3, - NV04_PGRAPH_CHROMA, - NV04_PGRAPH_BETA_AND, - NV04_PGRAPH_BETA_PREMULT, - 0x00400e70, - 0x00400e74, - 0x00400e78, - 0x00400e7c, - 0x00400e80, - 0x00400e84, - 0x00400e88, - 0x00400e8c, - 0x00400ea0, - 0x00400ea4, - 0x00400ea8, - 0x00400e90, - 0x00400e94, - 0x00400e98, - 0x00400e9c, - NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */ - NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */ - 0x00400f04, - 0x00400f24, - 0x00400f08, - 0x00400f28, - 0x00400f0c, - 0x00400f2c, - 0x00400f10, - 0x00400f30, - 0x00400f14, - 0x00400f34, - 0x00400f18, - 0x00400f38, - 0x00400f1c, - 0x00400f3c, - NV10_PGRAPH_XFMODE0, - NV10_PGRAPH_XFMODE1, - NV10_PGRAPH_GLOBALSTATE0, - NV10_PGRAPH_GLOBALSTATE1, - NV04_PGRAPH_STORED_FMT, - NV04_PGRAPH_SOURCE_COLOR, - NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ - NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ - 0x00400404, - 0x00400484, - 0x00400408, - 0x00400488, - 0x0040040c, - 0x0040048c, - 0x00400410, - 0x00400490, - 0x00400414, - 0x00400494, - 0x00400418, - 0x00400498, - 0x0040041c, - 0x0040049c, - 0x00400420, - 0x004004a0, - 0x00400424, - 0x004004a4, - 0x00400428, - 0x004004a8, - 0x0040042c, - 0x004004ac, - 0x00400430, - 0x004004b0, - 0x00400434, - 0x004004b4, - 0x00400438, - 0x004004b8, - 0x0040043c, - 0x004004bc, - 0x00400440, - 0x004004c0, - 0x00400444, - 0x004004c4, - 0x00400448, - 0x004004c8, - 0x0040044c, - 0x004004cc, - 0x00400450, - 0x004004d0, - 0x00400454, - 0x004004d4, - 0x00400458, - 0x004004d8, - 0x0040045c, - 0x004004dc, - 0x00400460, - 0x004004e0, - 0x00400464, - 0x004004e4, - 0x00400468, - 0x004004e8, - 0x0040046c, - 0x004004ec, - 0x00400470, - 0x004004f0, - 0x00400474, - 0x004004f4, - 0x00400478, - 0x004004f8, - 0x0040047c, - 0x004004fc, - NV03_PGRAPH_ABS_UCLIP_XMIN, - NV03_PGRAPH_ABS_UCLIP_XMAX, - NV03_PGRAPH_ABS_UCLIP_YMIN, - NV03_PGRAPH_ABS_UCLIP_YMAX, - 0x00400550, - 0x00400558, - 0x00400554, - 0x0040055c, - NV03_PGRAPH_ABS_UCLIPA_XMIN, - NV03_PGRAPH_ABS_UCLIPA_XMAX, - NV03_PGRAPH_ABS_UCLIPA_YMIN, - NV03_PGRAPH_ABS_UCLIPA_YMAX, - NV03_PGRAPH_ABS_ICLIP_XMAX, - NV03_PGRAPH_ABS_ICLIP_YMAX, - NV03_PGRAPH_XY_LOGIC_MISC0, - NV03_PGRAPH_XY_LOGIC_MISC1, - NV03_PGRAPH_XY_LOGIC_MISC2, - NV03_PGRAPH_XY_LOGIC_MISC3, - NV03_PGRAPH_CLIPX_0, - NV03_PGRAPH_CLIPX_1, - NV03_PGRAPH_CLIPY_0, - NV03_PGRAPH_CLIPY_1, - NV10_PGRAPH_COMBINER0_IN_ALPHA, - NV10_PGRAPH_COMBINER1_IN_ALPHA, - NV10_PGRAPH_COMBINER0_IN_RGB, - NV10_PGRAPH_COMBINER1_IN_RGB, - NV10_PGRAPH_COMBINER_COLOR0, - NV10_PGRAPH_COMBINER_COLOR1, - NV10_PGRAPH_COMBINER0_OUT_ALPHA, - NV10_PGRAPH_COMBINER1_OUT_ALPHA, - NV10_PGRAPH_COMBINER0_OUT_RGB, - NV10_PGRAPH_COMBINER1_OUT_RGB, - NV10_PGRAPH_COMBINER_FINAL0, - NV10_PGRAPH_COMBINER_FINAL1, - 0x00400e00, - 0x00400e04, - 0x00400e08, - 0x00400e0c, - 0x00400e10, - 0x00400e14, - 0x00400e18, - 0x00400e1c, - 0x00400e20, - 0x00400e24, - 0x00400e28, - 0x00400e2c, - 0x00400e30, - 0x00400e34, - 0x00400e38, - 0x00400e3c, - NV04_PGRAPH_PASSTHRU_0, - NV04_PGRAPH_PASSTHRU_1, - NV04_PGRAPH_PASSTHRU_2, - NV10_PGRAPH_DIMX_TEXTURE, - NV10_PGRAPH_WDIMX_TEXTURE, - NV10_PGRAPH_DVD_COLORFMT, - NV10_PGRAPH_SCALED_FORMAT, - NV04_PGRAPH_MISC24_0, - NV04_PGRAPH_MISC24_1, - NV04_PGRAPH_MISC24_2, - NV03_PGRAPH_X_MISC, - NV03_PGRAPH_Y_MISC, - NV04_PGRAPH_VALID1, - NV04_PGRAPH_VALID2, -}; - -static int nv17_graph_ctx_regs[] = { - NV10_PGRAPH_DEBUG_4, - 0x004006b0, - 0x00400eac, - 0x00400eb0, - 0x00400eb4, - 0x00400eb8, - 0x00400ebc, - 0x00400ec0, - 0x00400ec4, - 0x00400ec8, - 0x00400ecc, - 0x00400ed0, - 0x00400ed4, - 0x00400ed8, - 0x00400edc, - 0x00400ee0, - 0x00400a00, - 0x00400a04, -}; - -struct nv10_graph_priv { - struct nouveau_graph base; - struct nv10_graph_chan *chan[32]; - spinlock_t lock; -}; - -struct nv10_graph_chan { - struct nouveau_object base; - int chid; - int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)]; - int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)]; - struct pipe_state pipe_state; - u32 lma_window[4]; -}; - - -static inline struct nv10_graph_priv * -nv10_graph_priv(struct nv10_graph_chan *chan) -{ - return (void *)nv_object(chan)->engine; -} - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -#define PIPE_SAVE(priv, state, addr) \ - do { \ - int __i; \ - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ - for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ - state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \ - } while (0) - -#define PIPE_RESTORE(priv, state, addr) \ - do { \ - int __i; \ - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ - for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \ - } while (0) - -static struct nouveau_oclass -nv10_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x004a, &nv04_graph_ofuncs }, /* gdi */ - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_graph_ofuncs }, /* blit */ - { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs }, /* blit */ - { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ - { 0x0094, &nv04_graph_ofuncs }, /* ttri */ - { 0x0095, &nv04_graph_ofuncs }, /* mtri */ - { 0x0056, &nv04_graph_ofuncs }, /* celcius */ - {}, -}; - -static struct nouveau_oclass -nv15_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x004a, &nv04_graph_ofuncs }, /* gdi */ - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_graph_ofuncs }, /* blit */ - { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs }, /* blit */ - { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ - { 0x0094, &nv04_graph_ofuncs }, /* ttri */ - { 0x0095, &nv04_graph_ofuncs }, /* mtri */ - { 0x0096, &nv04_graph_ofuncs }, /* celcius */ - {}, -}; - -static int -nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv10_graph_chan *chan = (void *)object->parent; - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - struct pipe_state *pipe = &chan->pipe_state; - u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; - u32 xfmode0, xfmode1; - u32 data = *(u32 *)args; - int i; - - chan->lma_window[(mthd - 0x1638) / 4] = data; - - if (mthd != 0x1644) - return 0; - - nv04_graph_idle(priv); - - PIPE_SAVE(priv, pipe_0x0040, 0x0040); - PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); - - PIPE_RESTORE(priv, chan->lma_window, 0x6790); - - nv04_graph_idle(priv); - - xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); - xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); - - PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); - PIPE_SAVE(priv, pipe_0x64c0, 0x64c0); - PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0); - PIPE_SAVE(priv, pipe_0x6a80, 0x6a80); - - nv04_graph_idle(priv); - - nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); - for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); - for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); - for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); - - PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); - - nv04_graph_idle(priv); - - PIPE_RESTORE(priv, pipe_0x0040, 0x0040); - - nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); - - PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0); - PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0); - PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80); - PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); - - nv04_graph_idle(priv); - - return 0; -} - -static int -nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv10_graph_chan *chan = (void *)object->parent; - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - - nv04_graph_idle(priv); - - nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); - nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000); - return 0; -} - -static struct nouveau_omthds -nv17_celcius_omthds[] = { - { 0x1638, 0x1638, nv17_graph_mthd_lma_window }, - { 0x163c, 0x163c, nv17_graph_mthd_lma_window }, - { 0x1640, 0x1640, nv17_graph_mthd_lma_window }, - { 0x1644, 0x1644, nv17_graph_mthd_lma_window }, - { 0x1658, 0x1658, nv17_graph_mthd_lma_enable }, - {} -}; - -static struct nouveau_oclass -nv17_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x004a, &nv04_graph_ofuncs }, /* gdi */ - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_graph_ofuncs }, /* blit */ - { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs }, /* blit */ - { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ - { 0x0094, &nv04_graph_ofuncs }, /* ttri */ - { 0x0095, &nv04_graph_ofuncs }, /* mtri */ - { 0x0099, &nv04_graph_ofuncs, nv17_celcius_omthds }, - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static struct nv10_graph_chan * -nv10_graph_channel(struct nv10_graph_priv *priv) -{ - struct nv10_graph_chan *chan = NULL; - if (nv_rd32(priv, 0x400144) & 0x00010000) { - int chid = nv_rd32(priv, 0x400148) >> 24; - if (chid < ARRAY_SIZE(priv->chan)) - chan = priv->chan[chid]; - } - return chan; -} - -static void -nv10_graph_save_pipe(struct nv10_graph_chan *chan) -{ - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - struct pipe_state *pipe = &chan->pipe_state; - - PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); - PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); - PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400); - PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800); - PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00); - PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000); - PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400); - PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800); - PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040); - PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000); -} - -static void -nv10_graph_load_pipe(struct nv10_graph_chan *chan) -{ - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - struct pipe_state *pipe = &chan->pipe_state; - u32 xfmode0, xfmode1; - int i; - - nv04_graph_idle(priv); - /* XXX check haiku comments */ - xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); - xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); - nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); - for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); - for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); - for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); - - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); - - - PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); - nv04_graph_idle(priv); - - /* restore XFMODE */ - nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); - PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400); - PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800); - PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00); - PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000); - PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400); - PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800); - PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); - PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000); - PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040); - nv04_graph_idle(priv); -} - -static void -nv10_graph_create_pipe(struct nv10_graph_chan *chan) -{ - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - struct pipe_state *pipe_state = &chan->pipe_state; - u32 *pipe_state_addr; - int i; -#define PIPE_INIT(addr) \ - do { \ - pipe_state_addr = pipe_state->pipe_##addr; \ - } while (0) -#define PIPE_INIT_END(addr) \ - do { \ - u32 *__end_addr = pipe_state->pipe_##addr + \ - ARRAY_SIZE(pipe_state->pipe_##addr); \ - if (pipe_state_addr != __end_addr) \ - nv_error(priv, "incomplete pipe init for 0x%x : %p/%p\n", \ - addr, pipe_state_addr, __end_addr); \ - } while (0) -#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value - - PIPE_INIT(0x0200); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0200); - - PIPE_INIT(0x6400); - for (i = 0; i < 211; i++) - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f000000); - NV_WRITE_PIPE_INIT(0x3f000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - PIPE_INIT_END(0x6400); - - PIPE_INIT(0x6800); - for (i = 0; i < 162; i++) - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - for (i = 0; i < 25; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x6800); - - PIPE_INIT(0x6c00); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0xbf800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x6c00); - - PIPE_INIT(0x7000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - for (i = 0; i < 35; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7000); - - PIPE_INIT(0x7400); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7400); - - PIPE_INIT(0x7800); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7800); - - PIPE_INIT(0x4400); - for (i = 0; i < 32; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x4400); - - PIPE_INIT(0x0000); - for (i = 0; i < 16; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0000); - - PIPE_INIT(0x0040); - for (i = 0; i < 4; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0040); - -#undef PIPE_INIT -#undef PIPE_INIT_END -#undef NV_WRITE_PIPE_INIT -} - -static int -nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) -{ - int i; - for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) { - if (nv10_graph_ctx_regs[i] == reg) - return i; - } - nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg); - return -1; -} - -static int -nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) -{ - int i; - for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) { - if (nv17_graph_ctx_regs[i] == reg) - return i; - } - nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg); - return -1; -} - -static void -nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst) -{ - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; - u32 ctx_user, ctx_switch[5]; - int i, subchan = -1; - - /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state - * that cannot be restored via MMIO. Do it through the FIFO - * instead. - */ - - /* Look for a celsius object */ - for (i = 0; i < 8; i++) { - int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; - - if (class == 0x56 || class == 0x96 || class == 0x99) { - subchan = i; - break; - } - } - - if (subchan < 0 || !inst) - return; - - /* Save the current ctx object */ - ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER); - for (i = 0; i < 5; i++) - ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i)); - - /* Save the FIFO state */ - st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2); - st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL); - st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH); - fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR); - - for (i = 0; i < ARRAY_SIZE(fifo); i++) - fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i); - - /* Switch to the celsius subchannel */ - for (i = 0; i < 5; i++) - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), - nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i))); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); - - /* Inject NV10TCL_DMA_VTXBUF */ - nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, - 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst); - nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - - /* Restore the FIFO state */ - for (i = 0; i < ARRAY_SIZE(fifo); i++) - nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]); - - nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); - - /* Restore the current ctx object */ - for (i = 0; i < 5; i++) - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); - nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user); -} - -static int -nv10_graph_load_context(struct nv10_graph_chan *chan, int chid) -{ - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - u32 inst; - int i; - - for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) - nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]); - - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { - for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) - nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]); - } - - nv10_graph_load_pipe(chan); - - inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; - nv10_graph_load_dma_vtxbuf(chan, chid, inst); - - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); - nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); - return 0; -} - -static int -nv10_graph_unload_context(struct nv10_graph_chan *chan) -{ - struct nv10_graph_priv *priv = nv10_graph_priv(chan); - int i; - - for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) - chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]); - - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { - for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) - chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]); - } - - nv10_graph_save_pipe(chan); - - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); - return 0; -} - -static void -nv10_graph_context_switch(struct nv10_graph_priv *priv) -{ - struct nv10_graph_chan *prev = NULL; - struct nv10_graph_chan *next = NULL; - unsigned long flags; - int chid; - - spin_lock_irqsave(&priv->lock, flags); - nv04_graph_idle(priv); - - /* If previous context is valid, we need to save it */ - prev = nv10_graph_channel(priv); - if (prev) - nv10_graph_unload_context(prev); - - /* load context for next channel */ - chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; - next = priv->chan[chid]; - if (next) - nv10_graph_load_context(next, chid); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -#define NV_WRITE_CTX(reg, val) do { \ - int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \ - if (offset > 0) \ - chan->nv10[offset] = val; \ - } while (0) - -#define NV17_WRITE_CTX(reg, val) do { \ - int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \ - if (offset > 0) \ - chan->nv17[offset] = val; \ - } while (0) - -static int -nv10_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_fifo_chan *fifo = (void *)parent; - struct nv10_graph_priv *priv = (void *)engine; - struct nv10_graph_chan *chan; - unsigned long flags; - int ret; - - ret = nouveau_object_create(parent, engine, oclass, 0, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - spin_lock_irqsave(&priv->lock, flags); - if (priv->chan[fifo->chid]) { - *pobject = nv_object(priv->chan[fifo->chid]); - atomic_inc(&(*pobject)->refcount); - spin_unlock_irqrestore(&priv->lock, flags); - nouveau_object_destroy(&chan->base); - return 1; - } - - NV_WRITE_CTX(0x00400e88, 0x08000000); - NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); - NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); - NV_WRITE_CTX(0x00400e10, 0x00001000); - NV_WRITE_CTX(0x00400e14, 0x00001000); - NV_WRITE_CTX(0x00400e30, 0x00080008); - NV_WRITE_CTX(0x00400e34, 0x00080008); - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { - /* is it really needed ??? */ - NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, - nv_rd32(priv, NV10_PGRAPH_DEBUG_4)); - NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0)); - NV17_WRITE_CTX(0x00400eac, 0x0fff0000); - NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); - NV17_WRITE_CTX(0x00400ec0, 0x00000080); - NV17_WRITE_CTX(0x00400ed0, 0x00000080); - } - NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24); - - nv10_graph_create_pipe(chan); - - priv->chan[fifo->chid] = chan; - chan->chid = fifo->chid; - spin_unlock_irqrestore(&priv->lock, flags); - return 0; -} - -static void -nv10_graph_context_dtor(struct nouveau_object *object) -{ - struct nv10_graph_priv *priv = (void *)object->engine; - struct nv10_graph_chan *chan = (void *)object; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - priv->chan[chan->chid] = NULL; - spin_unlock_irqrestore(&priv->lock, flags); - - nouveau_object_destroy(&chan->base); -} - -static int -nv10_graph_context_fini(struct nouveau_object *object, bool suspend) -{ - struct nv10_graph_priv *priv = (void *)object->engine; - struct nv10_graph_chan *chan = (void *)object; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv10_graph_channel(priv) == chan) - nv10_graph_unload_context(chan); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->lock, flags); - - return nouveau_object_fini(&chan->base, suspend); -} - -static struct nouveau_oclass -nv10_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_graph_context_ctor, - .dtor = nv10_graph_context_dtor, - .init = nouveau_object_init, - .fini = nv10_graph_context_fini, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static void -nv10_graph_tile_prog(struct nouveau_engine *engine, int i) -{ - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; - struct nouveau_fifo *pfifo = nouveau_fifo(engine); - struct nv10_graph_priv *priv = (void *)engine; - unsigned long flags; - - pfifo->pause(pfifo, &flags); - nv04_graph_idle(priv); - - nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr); - - pfifo->start(pfifo, &flags); -} - -const struct nouveau_bitfield nv10_graph_intr_name[] = { - { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, - { NV_PGRAPH_INTR_ERROR, "ERROR" }, - {} -}; - -const struct nouveau_bitfield nv10_graph_nstatus[] = { - { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, - { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, - { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, - { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }, - {} -}; - -static void -nv10_graph_intr(struct nouveau_subdev *subdev) -{ - struct nv10_graph_priv *priv = (void *)subdev; - struct nv10_graph_chan *chan = NULL; - struct nouveau_namedb *namedb = NULL; - struct nouveau_handle *handle = NULL; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); - u32 chid = (addr & 0x01f00000) >> 20; - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; - u32 show = stat; - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - chan = priv->chan[chid]; - if (chan) - namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); - spin_unlock_irqrestore(&priv->lock, flags); - - if (stat & NV_PGRAPH_INTR_ERROR) { - if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { - handle = nouveau_namedb_get_class(namedb, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~NV_PGRAPH_INTR_ERROR; - } - } - - if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); - stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - nv10_graph_context_switch(priv); - } - - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); - - if (show) { - nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv10_graph_intr_name, show); - pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); - pr_cont(" nstatus:"); - nouveau_bitfield_print(nv10_graph_nstatus, nstatus); - pr_cont("\n"); - nv_error(priv, - "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nouveau_client_name(chan), subc, class, mthd, - data); - } - - nouveau_namedb_put(handle); -} - -static int -nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv10_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv10_graph_intr; - nv_engine(priv)->cclass = &nv10_graph_cclass; - - if (nv_device(priv)->chipset <= 0x10) - nv_engine(priv)->sclass = nv10_graph_sclass; - else - if (nv_device(priv)->chipset < 0x17 || - nv_device(priv)->card_type < NV_11) - nv_engine(priv)->sclass = nv15_graph_sclass; - else - nv_engine(priv)->sclass = nv17_graph_sclass; - - nv_engine(priv)->tile_prog = nv10_graph_tile_prog; - spin_lock_init(&priv->lock); - return 0; -} - -static void -nv10_graph_dtor(struct nouveau_object *object) -{ - struct nv10_graph_priv *priv = (void *)object; - nouveau_graph_destroy(&priv->base); -} - -static int -nv10_graph_init(struct nouveau_object *object) -{ - struct nouveau_engine *engine = nv_engine(object); - struct nouveau_fb *pfb = nouveau_fb(object); - struct nv10_graph_priv *priv = (void *)engine; - int ret, i; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); - /* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ - nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); - - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000); - nv_wr32(priv, 0x400a10, 0x03ff3fb6); - nv_wr32(priv, 0x400838, 0x002f8684); - nv_wr32(priv, 0x40083c, 0x00115f3f); - nv_wr32(priv, 0x4006b0, 0x40000020); - } else { - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); - } - - /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) - engine->tile_prog(engine, i); - - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF); - - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); - return 0; -} - -static int -nv10_graph_fini(struct nouveau_object *object, bool suspend) -{ - struct nv10_graph_priv *priv = (void *)object; - return nouveau_graph_fini(&priv->base, suspend); -} - -struct nouveau_oclass -nv10_graph_oclass = { - .handle = NV_ENGINE(GR, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_graph_ctor, - .dtor = nv10_graph_dtor, - .init = nv10_graph_init, - .fini = nv10_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c deleted file mode 100644 index 2b0e8f48c029..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nv108_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa140, &nouveau_object_ofuncs }, - { KEPLER_B, &nvc0_fermi_ofuncs }, - { 0xa1c0, &nouveau_object_ofuncs }, - {} -}; - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nv108_graph_init_main_0[] = { - { 0x400080, 1, 0x04, 0x003083c2 }, - { 0x400088, 1, 0x04, 0x0001bfe7 }, - { 0x40008c, 1, 0x04, 0x00000000 }, - { 0x400090, 1, 0x04, 0x00000030 }, - { 0x40013c, 1, 0x04, 0x003901f7 }, - { 0x400140, 1, 0x04, 0x00000100 }, - { 0x400144, 1, 0x04, 0x00000000 }, - { 0x400148, 1, 0x04, 0x00000110 }, - { 0x400138, 1, 0x04, 0x00000000 }, - { 0x400130, 2, 0x04, 0x00000000 }, - { 0x400124, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_init -nv108_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405900, 1, 0x04, 0x00000000 }, - { 0x405908, 1, 0x04, 0x00000000 }, - { 0x405928, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nv108_graph_init_gpc_unk_0[] = { - { 0x418604, 1, 0x04, 0x00000000 }, - { 0x418680, 1, 0x04, 0x00000000 }, - { 0x418714, 1, 0x04, 0x00000000 }, - { 0x418384, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nv108_graph_init_setup_1[] = { - { 0x4188c8, 2, 0x04, 0x00000000 }, - { 0x4188d0, 1, 0x04, 0x00010000 }, - { 0x4188d4, 1, 0x04, 0x00000201 }, - {} -}; - -static const struct nvc0_graph_init -nv108_graph_init_tex_0[] = { - { 0x419ab0, 1, 0x04, 0x00000000 }, - { 0x419ac8, 1, 0x04, 0x00000000 }, - { 0x419ab8, 1, 0x04, 0x000000e7 }, - { 0x419abc, 2, 0x04, 0x00000000 }, - { 0x419ab4, 1, 0x04, 0x00000000 }, - { 0x419aa8, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nv108_graph_init_l1c_0[] = { - { 0x419c98, 1, 0x04, 0x00000000 }, - { 0x419ca8, 1, 0x04, 0x00000000 }, - { 0x419cb0, 1, 0x04, 0x01000000 }, - { 0x419cb4, 1, 0x04, 0x00000000 }, - { 0x419cb8, 1, 0x04, 0x00b08bea }, - { 0x419c84, 1, 0x04, 0x00010384 }, - { 0x419cbc, 1, 0x04, 0x281b3646 }, - { 0x419cc0, 2, 0x04, 0x00000000 }, - { 0x419c80, 1, 0x04, 0x00000230 }, - { 0x419ccc, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nv108_graph_pack_mmio[] = { - { nv108_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nv108_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvf0_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nv108_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nv108_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvf0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nv108_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { nv108_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nvf0_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static int -nv108_graph_fini(struct nouveau_object *object, bool suspend) -{ - struct nvc0_graph_priv *priv = (void *)object; - static const struct { - u32 addr; - u32 data; - } magic[] = { - { 0x020520, 0xfffffffc }, - { 0x020524, 0xfffffffe }, - { 0x020524, 0xfffffffc }, - { 0x020524, 0xfffffff8 }, - { 0x020524, 0xffffffe0 }, - { 0x020530, 0xfffffffe }, - { 0x02052c, 0xfffffffa }, - { 0x02052c, 0xfffffff0 }, - { 0x02052c, 0xffffffc0 }, - { 0x02052c, 0xffffff00 }, - { 0x02052c, 0xfffffc00 }, - { 0x02052c, 0xfffcfc00 }, - { 0x02052c, 0xfff0fc00 }, - { 0x02052c, 0xff80fc00 }, - { 0x020528, 0xfffffffe }, - { 0x020528, 0xfffffffc }, - }; - int i; - - nv_mask(priv, 0x000200, 0x08001000, 0x00000000); - nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); - for (i = 0; i < ARRAY_SIZE(magic); i++) { - nv_wr32(priv, magic[i].addr, magic[i].data); - nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); - } - - return nouveau_graph_fini(&priv->base, suspend); -} - -#include "fuc/hubnv108.fuc5.h" - -static struct nvc0_graph_ucode -nv108_graph_fecs_ucode = { - .code.data = nv108_grhub_code, - .code.size = sizeof(nv108_grhub_code), - .data.data = nv108_grhub_data, - .data.size = sizeof(nv108_grhub_data), -}; - -#include "fuc/gpcnv108.fuc5.h" - -static struct nvc0_graph_ucode -nv108_graph_gpccs_ucode = { - .code.data = nv108_grgpc_code, - .code.size = sizeof(nv108_grgpc_code), - .data.data = nv108_grgpc_data, - .data.size = sizeof(nv108_grgpc_data), -}; - -struct nouveau_oclass * -nv108_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = nv108_graph_fini, - }, - .cclass = &nv108_grctx_oclass, - .sclass = nv108_graph_sclass, - .mmio = nv108_graph_pack_mmio, - .fecs.ucode = &nv108_graph_fecs_ucode, - .gpccs.ucode = &nv108_graph_gpccs_ucode, - .ppc_nr = 1, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c deleted file mode 100644 index ceb9c746d94e..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c +++ /dev/null @@ -1,383 +0,0 @@ -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "nv20.h" -#include "regs.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nv20_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */ - { 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */ - { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv20_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_chan *chan; - int ret, i; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC, - &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nouveau_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x033c, 0xffff0000); - nv_wo32(chan, 0x03a0, 0x0fff0000); - nv_wo32(chan, 0x03a4, 0x0fff0000); - nv_wo32(chan, 0x047c, 0x00000101); - nv_wo32(chan, 0x0490, 0x00000111); - nv_wo32(chan, 0x04a8, 0x44400000); - for (i = 0x04d4; i <= 0x04e0; i += 4) - nv_wo32(chan, i, 0x00030303); - for (i = 0x04f4; i <= 0x0500; i += 4) - nv_wo32(chan, i, 0x00080000); - for (i = 0x050c; i <= 0x0518; i += 4) - nv_wo32(chan, i, 0x01012000); - for (i = 0x051c; i <= 0x0528; i += 4) - nv_wo32(chan, i, 0x000105b8); - for (i = 0x052c; i <= 0x0538; i += 4) - nv_wo32(chan, i, 0x00080008); - for (i = 0x055c; i <= 0x0598; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x05a4, 0x4b7fffff); - nv_wo32(chan, 0x05fc, 0x00000001); - nv_wo32(chan, 0x0604, 0x00004000); - nv_wo32(chan, 0x0610, 0x00000001); - nv_wo32(chan, 0x0618, 0x00040000); - nv_wo32(chan, 0x061c, 0x00010000); - for (i = 0x1c1c; i <= 0x248c; i += 16) { - nv_wo32(chan, (i + 0), 0x10700ff9); - nv_wo32(chan, (i + 4), 0x0436086c); - nv_wo32(chan, (i + 8), 0x000c001b); - } - nv_wo32(chan, 0x281c, 0x3f800000); - nv_wo32(chan, 0x2830, 0x3f800000); - nv_wo32(chan, 0x285c, 0x40000000); - nv_wo32(chan, 0x2860, 0x3f800000); - nv_wo32(chan, 0x2864, 0x3f000000); - nv_wo32(chan, 0x286c, 0x40000000); - nv_wo32(chan, 0x2870, 0x3f800000); - nv_wo32(chan, 0x2878, 0xbf800000); - nv_wo32(chan, 0x2880, 0xbf800000); - nv_wo32(chan, 0x34a4, 0x000fe000); - nv_wo32(chan, 0x3530, 0x000003f8); - nv_wo32(chan, 0x3540, 0x002fe000); - for (i = 0x355c; i <= 0x3578; i += 4) - nv_wo32(chan, i, 0x001c527c); - return 0; -} - -int -nv20_graph_context_init(struct nouveau_object *object) -{ - struct nv20_graph_priv *priv = (void *)object->engine; - struct nv20_graph_chan *chan = (void *)object; - int ret; - - ret = nouveau_graph_context_init(&chan->base); - if (ret) - return ret; - - nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); - return 0; -} - -int -nv20_graph_context_fini(struct nouveau_object *object, bool suspend) -{ - struct nv20_graph_priv *priv = (void *)object->engine; - struct nv20_graph_chan *chan = (void *)object; - int chid = -1; - - nv_mask(priv, 0x400720, 0x00000001, 0x00000000); - if (nv_rd32(priv, 0x400144) & 0x00010000) - chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; - if (chan->chid == chid) { - nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); - nv_wr32(priv, 0x400788, 0x00000002); - nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); - nv_wr32(priv, 0x400144, 0x10000000); - nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); - } - nv_mask(priv, 0x400720, 0x00000001, 0x00000001); - - nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); - return nouveau_graph_context_fini(&chan->base, suspend); -} - -static struct nouveau_oclass -nv20_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x20), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv20_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -void -nv20_graph_tile_prog(struct nouveau_engine *engine, int i) -{ - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; - struct nouveau_fifo *pfifo = nouveau_fifo(engine); - struct nv20_graph_priv *priv = (void *)engine; - unsigned long flags; - - pfifo->pause(pfifo, &flags); - nv04_graph_idle(priv); - - nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); - - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); - - if (nv_device(engine)->chipset != 0x34) { - nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); - } - - pfifo->start(pfifo, &flags); -} - -void -nv20_graph_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle; - struct nv20_graph_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); - u32 chid = (addr & 0x01f00000) >> 20; - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; - u32 show = stat; - - engctx = nouveau_engctx_get(engine, chid); - if (stat & NV_PGRAPH_INTR_ERROR) { - if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - handle = nouveau_handle_get_class(engctx, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~NV_PGRAPH_INTR_ERROR; - nouveau_handle_put(handle); - } - } - - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); - - if (show) { - nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv10_graph_intr_name, show); - pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); - pr_cont(" nstatus:"); - nouveau_bitfield_print(nv10_graph_nstatus, nstatus); - pr_cont("\n"); - nv_error(priv, - "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nouveau_client_name(engctx), subc, class, mthd, - data); - } - - nouveau_engctx_put(engctx); -} - -static int -nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv20_graph_cclass; - nv_engine(priv)->sclass = nv20_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; - return 0; -} - -void -nv20_graph_dtor(struct nouveau_object *object) -{ - struct nv20_graph_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->ctxtab); - nouveau_graph_destroy(&priv->base); -} - -int -nv20_graph_init(struct nouveau_object *object) -{ - struct nouveau_engine *engine = nv_engine(object); - struct nv20_graph_priv *priv = (void *)engine; - struct nouveau_fb *pfb = nouveau_fb(object); - u32 tmp, vramsz; - int ret, i; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); - - if (nv_device(priv)->chipset == 0x20) { - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000); - for (i = 0; i < 15; i++) - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); - nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); - } else { - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000); - for (i = 0; i < 32; i++) - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); - nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); - } - - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); - nv_wr32(priv, 0x40009C , 0x00000040); - - if (nv_device(priv)->chipset >= 0x25) { - nv_wr32(priv, 0x400890, 0x00a8cfff); - nv_wr32(priv, 0x400610, 0x304B1FB6); - nv_wr32(priv, 0x400B80, 0x1cbd3883); - nv_wr32(priv, 0x400B84, 0x44000000); - nv_wr32(priv, 0x400098, 0x40000080); - nv_wr32(priv, 0x400B88, 0x000000ff); - - } else { - nv_wr32(priv, 0x400880, 0x0008c7df); - nv_wr32(priv, 0x400094, 0x00000005); - nv_wr32(priv, 0x400B80, 0x45eae20e); - nv_wr32(priv, 0x400B84, 0x24000000); - nv_wr32(priv, 0x400098, 0x00000040); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); - } - - /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) - engine->tile_prog(engine, i); - - nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); - - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); - - tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00; - nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); - tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100; - nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); - - /* begin RAM config */ - vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; - nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200)); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x400820, 0); - nv_wr32(priv, 0x400824, 0); - nv_wr32(priv, 0x400864, vramsz - 1); - nv_wr32(priv, 0x400868, vramsz - 1); - - /* interesting.. the below overwrites some of the tile setup above.. */ - nv_wr32(priv, 0x400B20, 0x00000000); - nv_wr32(priv, 0x400B04, 0xFFFFFFFF); - - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); - return 0; -} - -struct nouveau_oclass -nv20_graph_oclass = { - .handle = NV_ENGINE(GR, 0x20), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv20_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv20_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h deleted file mode 100644 index 2bea7313e03f..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NV20_GRAPH_H__ -#define __NV20_GRAPH_H__ - -#include - -#include -#include - -struct nv20_graph_priv { - struct nouveau_graph base; - struct nouveau_gpuobj *ctxtab; -}; - -struct nv20_graph_chan { - struct nouveau_graph_chan base; - int chid; -}; - -extern struct nouveau_oclass nv25_graph_sclass[]; -int nv20_graph_context_init(struct nouveau_object *); -int nv20_graph_context_fini(struct nouveau_object *, bool); - -void nv20_graph_tile_prog(struct nouveau_engine *, int); -void nv20_graph_intr(struct nouveau_subdev *); - -void nv20_graph_dtor(struct nouveau_object *); -int nv20_graph_init(struct nouveau_object *); - -int nv30_graph_init(struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c deleted file mode 100644 index f8a6fdd7d5e8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c +++ /dev/null @@ -1,166 +0,0 @@ -#include -#include -#include - -#include -#include - -#include - -#include "nv20.h" -#include "regs.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -struct nouveau_oclass -nv25_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */ - { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0597, &nv04_graph_ofuncs, NULL }, /* kelvin */ - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv25_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_chan *chan; - int ret, i; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x3724, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nouveau_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x035c, 0xffff0000); - nv_wo32(chan, 0x03c0, 0x0fff0000); - nv_wo32(chan, 0x03c4, 0x0fff0000); - nv_wo32(chan, 0x049c, 0x00000101); - nv_wo32(chan, 0x04b0, 0x00000111); - nv_wo32(chan, 0x04c8, 0x00000080); - nv_wo32(chan, 0x04cc, 0xffff0000); - nv_wo32(chan, 0x04d0, 0x00000001); - nv_wo32(chan, 0x04e4, 0x44400000); - nv_wo32(chan, 0x04fc, 0x4b800000); - for (i = 0x0510; i <= 0x051c; i += 4) - nv_wo32(chan, i, 0x00030303); - for (i = 0x0530; i <= 0x053c; i += 4) - nv_wo32(chan, i, 0x00080000); - for (i = 0x0548; i <= 0x0554; i += 4) - nv_wo32(chan, i, 0x01012000); - for (i = 0x0558; i <= 0x0564; i += 4) - nv_wo32(chan, i, 0x000105b8); - for (i = 0x0568; i <= 0x0574; i += 4) - nv_wo32(chan, i, 0x00080008); - for (i = 0x0598; i <= 0x05d4; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x05e0, 0x4b7fffff); - nv_wo32(chan, 0x0620, 0x00000080); - nv_wo32(chan, 0x0624, 0x30201000); - nv_wo32(chan, 0x0628, 0x70605040); - nv_wo32(chan, 0x062c, 0xb0a09080); - nv_wo32(chan, 0x0630, 0xf0e0d0c0); - nv_wo32(chan, 0x0664, 0x00000001); - nv_wo32(chan, 0x066c, 0x00004000); - nv_wo32(chan, 0x0678, 0x00000001); - nv_wo32(chan, 0x0680, 0x00040000); - nv_wo32(chan, 0x0684, 0x00010000); - for (i = 0x1b04; i <= 0x2374; i += 16) { - nv_wo32(chan, (i + 0), 0x10700ff9); - nv_wo32(chan, (i + 4), 0x0436086c); - nv_wo32(chan, (i + 8), 0x000c001b); - } - nv_wo32(chan, 0x2704, 0x3f800000); - nv_wo32(chan, 0x2718, 0x3f800000); - nv_wo32(chan, 0x2744, 0x40000000); - nv_wo32(chan, 0x2748, 0x3f800000); - nv_wo32(chan, 0x274c, 0x3f000000); - nv_wo32(chan, 0x2754, 0x40000000); - nv_wo32(chan, 0x2758, 0x3f800000); - nv_wo32(chan, 0x2760, 0xbf800000); - nv_wo32(chan, 0x2768, 0xbf800000); - nv_wo32(chan, 0x308c, 0x000fe000); - nv_wo32(chan, 0x3108, 0x000003f8); - nv_wo32(chan, 0x3468, 0x002fe000); - for (i = 0x3484; i <= 0x34a0; i += 4) - nv_wo32(chan, i, 0x001c527c); - return 0; -} - -static struct nouveau_oclass -nv25_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x25), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv25_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static int -nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv25_graph_cclass; - nv_engine(priv)->sclass = nv25_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; - return 0; -} - -struct nouveau_oclass -nv25_graph_oclass = { - .handle = NV_ENGINE(GR, 0x25), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv25_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv20_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c deleted file mode 100644 index 5de9caa2ef67..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c +++ /dev/null @@ -1,133 +0,0 @@ -#include -#include -#include - -#include -#include - -#include - -#include "nv20.h" -#include "regs.h" - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv2a_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_chan *chan; - int ret, i; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x36b0, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nouveau_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x033c, 0xffff0000); - nv_wo32(chan, 0x03a0, 0x0fff0000); - nv_wo32(chan, 0x03a4, 0x0fff0000); - nv_wo32(chan, 0x047c, 0x00000101); - nv_wo32(chan, 0x0490, 0x00000111); - nv_wo32(chan, 0x04a8, 0x44400000); - for (i = 0x04d4; i <= 0x04e0; i += 4) - nv_wo32(chan, i, 0x00030303); - for (i = 0x04f4; i <= 0x0500; i += 4) - nv_wo32(chan, i, 0x00080000); - for (i = 0x050c; i <= 0x0518; i += 4) - nv_wo32(chan, i, 0x01012000); - for (i = 0x051c; i <= 0x0528; i += 4) - nv_wo32(chan, i, 0x000105b8); - for (i = 0x052c; i <= 0x0538; i += 4) - nv_wo32(chan, i, 0x00080008); - for (i = 0x055c; i <= 0x0598; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x05a4, 0x4b7fffff); - nv_wo32(chan, 0x05fc, 0x00000001); - nv_wo32(chan, 0x0604, 0x00004000); - nv_wo32(chan, 0x0610, 0x00000001); - nv_wo32(chan, 0x0618, 0x00040000); - nv_wo32(chan, 0x061c, 0x00010000); - for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ - nv_wo32(chan, (i + 0), 0x10700ff9); - nv_wo32(chan, (i + 4), 0x0436086c); - nv_wo32(chan, (i + 8), 0x000c001b); - } - nv_wo32(chan, 0x269c, 0x3f800000); - nv_wo32(chan, 0x26b0, 0x3f800000); - nv_wo32(chan, 0x26dc, 0x40000000); - nv_wo32(chan, 0x26e0, 0x3f800000); - nv_wo32(chan, 0x26e4, 0x3f000000); - nv_wo32(chan, 0x26ec, 0x40000000); - nv_wo32(chan, 0x26f0, 0x3f800000); - nv_wo32(chan, 0x26f8, 0xbf800000); - nv_wo32(chan, 0x2700, 0xbf800000); - nv_wo32(chan, 0x3024, 0x000fe000); - nv_wo32(chan, 0x30a0, 0x000003f8); - nv_wo32(chan, 0x33fc, 0x002fe000); - for (i = 0x341c; i <= 0x3438; i += 4) - nv_wo32(chan, i, 0x001c527c); - return 0; -} - -static struct nouveau_oclass -nv2a_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x2a), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv2a_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static int -nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv2a_graph_cclass; - nv_engine(priv)->sclass = nv25_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; - return 0; -} - -struct nouveau_oclass -nv2a_graph_oclass = { - .handle = NV_ENGINE(GR, 0x2a), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv2a_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv20_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c deleted file mode 100644 index 2f9dbc709389..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c +++ /dev/null @@ -1,237 +0,0 @@ -#include -#include -#include - -#include -#include - -#include - -#include "nv20.h" -#include "regs.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nv30_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */ - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv30_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_chan *chan; - int ret, i; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nouveau_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x0410, 0x00000101); - nv_wo32(chan, 0x0424, 0x00000111); - nv_wo32(chan, 0x0428, 0x00000060); - nv_wo32(chan, 0x0444, 0x00000080); - nv_wo32(chan, 0x0448, 0xffff0000); - nv_wo32(chan, 0x044c, 0x00000001); - nv_wo32(chan, 0x0460, 0x44400000); - nv_wo32(chan, 0x048c, 0xffff0000); - for (i = 0x04e0; i < 0x04e8; i += 4) - nv_wo32(chan, i, 0x0fff0000); - nv_wo32(chan, 0x04ec, 0x00011100); - for (i = 0x0508; i < 0x0548; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x0550, 0x4b7fffff); - nv_wo32(chan, 0x058c, 0x00000080); - nv_wo32(chan, 0x0590, 0x30201000); - nv_wo32(chan, 0x0594, 0x70605040); - nv_wo32(chan, 0x0598, 0xb8a89888); - nv_wo32(chan, 0x059c, 0xf8e8d8c8); - nv_wo32(chan, 0x05b0, 0xb0000000); - for (i = 0x0600; i < 0x0640; i += 4) - nv_wo32(chan, i, 0x00010588); - for (i = 0x0640; i < 0x0680; i += 4) - nv_wo32(chan, i, 0x00030303); - for (i = 0x06c0; i < 0x0700; i += 4) - nv_wo32(chan, i, 0x0008aae4); - for (i = 0x0700; i < 0x0740; i += 4) - nv_wo32(chan, i, 0x01012000); - for (i = 0x0740; i < 0x0780; i += 4) - nv_wo32(chan, i, 0x00080008); - nv_wo32(chan, 0x085c, 0x00040000); - nv_wo32(chan, 0x0860, 0x00010000); - for (i = 0x0864; i < 0x0874; i += 4) - nv_wo32(chan, i, 0x00040004); - for (i = 0x1f18; i <= 0x3088 ; i += 16) { - nv_wo32(chan, i + 0, 0x10700ff9); - nv_wo32(chan, i + 1, 0x0436086c); - nv_wo32(chan, i + 2, 0x000c001b); - } - for (i = 0x30b8; i < 0x30c8; i += 4) - nv_wo32(chan, i, 0x0000ffff); - nv_wo32(chan, 0x344c, 0x3f800000); - nv_wo32(chan, 0x3808, 0x3f800000); - nv_wo32(chan, 0x381c, 0x3f800000); - nv_wo32(chan, 0x3848, 0x40000000); - nv_wo32(chan, 0x384c, 0x3f800000); - nv_wo32(chan, 0x3850, 0x3f000000); - nv_wo32(chan, 0x3858, 0x40000000); - nv_wo32(chan, 0x385c, 0x3f800000); - nv_wo32(chan, 0x3864, 0xbf800000); - nv_wo32(chan, 0x386c, 0xbf800000); - return 0; -} - -static struct nouveau_oclass -nv30_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x30), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv30_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static int -nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv30_graph_cclass; - nv_engine(priv)->sclass = nv30_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; - return 0; -} - -int -nv30_graph_init(struct nouveau_object *object) -{ - struct nouveau_engine *engine = nv_engine(object); - struct nv20_graph_priv *priv = (void *)engine; - struct nouveau_fb *pfb = nouveau_fb(object); - int ret, i; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); - - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); - nv_wr32(priv, 0x400890, 0x01b463ff); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475); - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); - nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); - nv_wr32(priv, 0x400B80, 0x1003d888); - nv_wr32(priv, 0x400B84, 0x0c000000); - nv_wr32(priv, 0x400098, 0x00000000); - nv_wr32(priv, 0x40009C, 0x0005ad00); - nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ - nv_wr32(priv, 0x4000a0, 0x00000000); - nv_wr32(priv, 0x4000a4, 0x00000008); - nv_wr32(priv, 0x4008a8, 0xb784a400); - nv_wr32(priv, 0x400ba0, 0x002f8685); - nv_wr32(priv, 0x400ba4, 0x00231f3f); - nv_wr32(priv, 0x4008a4, 0x40000020); - - if (nv_device(priv)->chipset == 0x34) { - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002); - } - - nv_wr32(priv, 0x4000c0, 0x00000016); - - /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) - engine->tile_prog(engine, i); - - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); - nv_wr32(priv, 0x0040075c , 0x00000001); - - /* begin RAM config */ - /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */ - nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); - if (nv_device(priv)->chipset != 0x34) { - nv_wr32(priv, 0x400750, 0x00EA0000); - nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x400750, 0x00EA0004); - nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); - } - return 0; -} - -struct nouveau_oclass -nv30_graph_oclass = { - .handle = NV_ENGINE(GR, 0x30), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv30_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv30_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c deleted file mode 100644 index 34dd26c70b64..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c +++ /dev/null @@ -1,167 +0,0 @@ -#include -#include -#include - -#include -#include - -#include - -#include "nv20.h" -#include "regs.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nv34_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0697, &nv04_graph_ofuncs, NULL }, /* rankine */ - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv34_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_chan *chan; - int ret, i; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x46dc, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nouveau_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x040c, 0x01000101); - nv_wo32(chan, 0x0420, 0x00000111); - nv_wo32(chan, 0x0424, 0x00000060); - nv_wo32(chan, 0x0440, 0x00000080); - nv_wo32(chan, 0x0444, 0xffff0000); - nv_wo32(chan, 0x0448, 0x00000001); - nv_wo32(chan, 0x045c, 0x44400000); - nv_wo32(chan, 0x0480, 0xffff0000); - for (i = 0x04d4; i < 0x04dc; i += 4) - nv_wo32(chan, i, 0x0fff0000); - nv_wo32(chan, 0x04e0, 0x00011100); - for (i = 0x04fc; i < 0x053c; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x0544, 0x4b7fffff); - nv_wo32(chan, 0x057c, 0x00000080); - nv_wo32(chan, 0x0580, 0x30201000); - nv_wo32(chan, 0x0584, 0x70605040); - nv_wo32(chan, 0x0588, 0xb8a89888); - nv_wo32(chan, 0x058c, 0xf8e8d8c8); - nv_wo32(chan, 0x05a0, 0xb0000000); - for (i = 0x05f0; i < 0x0630; i += 4) - nv_wo32(chan, i, 0x00010588); - for (i = 0x0630; i < 0x0670; i += 4) - nv_wo32(chan, i, 0x00030303); - for (i = 0x06b0; i < 0x06f0; i += 4) - nv_wo32(chan, i, 0x0008aae4); - for (i = 0x06f0; i < 0x0730; i += 4) - nv_wo32(chan, i, 0x01012000); - for (i = 0x0730; i < 0x0770; i += 4) - nv_wo32(chan, i, 0x00080008); - nv_wo32(chan, 0x0850, 0x00040000); - nv_wo32(chan, 0x0854, 0x00010000); - for (i = 0x0858; i < 0x0868; i += 4) - nv_wo32(chan, i, 0x00040004); - for (i = 0x15ac; i <= 0x271c ; i += 16) { - nv_wo32(chan, i + 0, 0x10700ff9); - nv_wo32(chan, i + 1, 0x0436086c); - nv_wo32(chan, i + 2, 0x000c001b); - } - for (i = 0x274c; i < 0x275c; i += 4) - nv_wo32(chan, i, 0x0000ffff); - nv_wo32(chan, 0x2ae0, 0x3f800000); - nv_wo32(chan, 0x2e9c, 0x3f800000); - nv_wo32(chan, 0x2eb0, 0x3f800000); - nv_wo32(chan, 0x2edc, 0x40000000); - nv_wo32(chan, 0x2ee0, 0x3f800000); - nv_wo32(chan, 0x2ee4, 0x3f000000); - nv_wo32(chan, 0x2eec, 0x40000000); - nv_wo32(chan, 0x2ef0, 0x3f800000); - nv_wo32(chan, 0x2ef8, 0xbf800000); - nv_wo32(chan, 0x2f00, 0xbf800000); - return 0; -} - -static struct nouveau_oclass -nv34_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x34), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv34_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static int -nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv34_graph_cclass; - nv_engine(priv)->sclass = nv34_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; - return 0; -} - -struct nouveau_oclass -nv34_graph_oclass = { - .handle = NV_ENGINE(GR, 0x34), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv34_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv30_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c deleted file mode 100644 index 2fb5756d9f66..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c +++ /dev/null @@ -1,165 +0,0 @@ -#include -#include -#include - -#include -#include - -#include "nv20.h" -#include "regs.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nv35_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0497, &nv04_graph_ofuncs, NULL }, /* rankine */ - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv35_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_chan *chan; - int ret, i; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x577c, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nouveau_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x040c, 0x00000101); - nv_wo32(chan, 0x0420, 0x00000111); - nv_wo32(chan, 0x0424, 0x00000060); - nv_wo32(chan, 0x0440, 0x00000080); - nv_wo32(chan, 0x0444, 0xffff0000); - nv_wo32(chan, 0x0448, 0x00000001); - nv_wo32(chan, 0x045c, 0x44400000); - nv_wo32(chan, 0x0488, 0xffff0000); - for (i = 0x04dc; i < 0x04e4; i += 4) - nv_wo32(chan, i, 0x0fff0000); - nv_wo32(chan, 0x04e8, 0x00011100); - for (i = 0x0504; i < 0x0544; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x054c, 0x4b7fffff); - nv_wo32(chan, 0x0588, 0x00000080); - nv_wo32(chan, 0x058c, 0x30201000); - nv_wo32(chan, 0x0590, 0x70605040); - nv_wo32(chan, 0x0594, 0xb8a89888); - nv_wo32(chan, 0x0598, 0xf8e8d8c8); - nv_wo32(chan, 0x05ac, 0xb0000000); - for (i = 0x0604; i < 0x0644; i += 4) - nv_wo32(chan, i, 0x00010588); - for (i = 0x0644; i < 0x0684; i += 4) - nv_wo32(chan, i, 0x00030303); - for (i = 0x06c4; i < 0x0704; i += 4) - nv_wo32(chan, i, 0x0008aae4); - for (i = 0x0704; i < 0x0744; i += 4) - nv_wo32(chan, i, 0x01012000); - for (i = 0x0744; i < 0x0784; i += 4) - nv_wo32(chan, i, 0x00080008); - nv_wo32(chan, 0x0860, 0x00040000); - nv_wo32(chan, 0x0864, 0x00010000); - for (i = 0x0868; i < 0x0878; i += 4) - nv_wo32(chan, i, 0x00040004); - for (i = 0x1f1c; i <= 0x308c ; i += 16) { - nv_wo32(chan, i + 0, 0x10700ff9); - nv_wo32(chan, i + 4, 0x0436086c); - nv_wo32(chan, i + 8, 0x000c001b); - } - for (i = 0x30bc; i < 0x30cc; i += 4) - nv_wo32(chan, i, 0x0000ffff); - nv_wo32(chan, 0x3450, 0x3f800000); - nv_wo32(chan, 0x380c, 0x3f800000); - nv_wo32(chan, 0x3820, 0x3f800000); - nv_wo32(chan, 0x384c, 0x40000000); - nv_wo32(chan, 0x3850, 0x3f800000); - nv_wo32(chan, 0x3854, 0x3f000000); - nv_wo32(chan, 0x385c, 0x40000000); - nv_wo32(chan, 0x3860, 0x3f800000); - nv_wo32(chan, 0x3868, 0xbf800000); - nv_wo32(chan, 0x3870, 0xbf800000); - return 0; -} - -static struct nouveau_oclass -nv35_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x35), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv35_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static int -nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv20_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv35_graph_cclass; - nv_engine(priv)->sclass = nv35_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; - return 0; -} - -struct nouveau_oclass -nv35_graph_oclass = { - .handle = NV_ENGINE(GR, 0x35), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv35_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv30_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c deleted file mode 100644 index 4f401174868d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "nv40.h" -#include "regs.h" - -struct nv40_graph_priv { - struct nouveau_graph base; - u32 size; -}; - -struct nv40_graph_chan { - struct nouveau_graph_chan base; -}; - -static u64 -nv40_graph_units(struct nouveau_graph *graph) -{ - struct nv40_graph_priv *priv = (void *)graph; - - return nv_rd32(priv, 0x1540); -} - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static int -nv40_graph_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_gpuobj *obj; - int ret; - - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 20, 16, 0, &obj); - *pobject = nv_object(obj); - if (ret) - return ret; - - nv_wo32(obj, 0x00, nv_mclass(obj)); - nv_wo32(obj, 0x04, 0x00000000); - nv_wo32(obj, 0x08, 0x00000000); -#ifdef __BIG_ENDIAN - nv_mo32(obj, 0x08, 0x01000000, 0x01000000); -#endif - nv_wo32(obj, 0x0c, 0x00000000); - nv_wo32(obj, 0x10, 0x00000000); - return 0; -} - -static struct nouveau_ofuncs -nv40_graph_ofuncs = { - .ctor = nv40_graph_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, -}; - -static struct nouveau_oclass -nv40_graph_sclass[] = { - { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */ - { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */ - { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */ - { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */ - { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */ - {}, -}; - -static struct nouveau_oclass -nv44_graph_sclass[] = { - { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */ - { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */ - { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */ - { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */ - { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */ - {}, -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv40_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv40_graph_priv *priv = (void *)engine; - struct nv40_graph_chan *chan; - int ret; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - priv->size, 16, - NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan)); - nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4); - return 0; -} - -static int -nv40_graph_context_fini(struct nouveau_object *object, bool suspend) -{ - struct nv40_graph_priv *priv = (void *)object->engine; - struct nv40_graph_chan *chan = (void *)object; - u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; - int ret = 0; - - nv_mask(priv, 0x400720, 0x00000001, 0x00000000); - - if (nv_rd32(priv, 0x40032c) == inst) { - if (suspend) { - nv_wr32(priv, 0x400720, 0x00000000); - nv_wr32(priv, 0x400784, inst); - nv_mask(priv, 0x400310, 0x00000020, 0x00000020); - nv_mask(priv, 0x400304, 0x00000001, 0x00000001); - if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) { - u32 insn = nv_rd32(priv, 0x400308); - nv_warn(priv, "ctxprog timeout 0x%08x\n", insn); - ret = -EBUSY; - } - } - - nv_mask(priv, 0x40032c, 0x01000000, 0x00000000); - } - - if (nv_rd32(priv, 0x400330) == inst) - nv_mask(priv, 0x400330, 0x01000000, 0x00000000); - - nv_mask(priv, 0x400720, 0x00000001, 0x00000001); - return ret; -} - -static struct nouveau_oclass -nv40_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = nv40_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static void -nv40_graph_tile_prog(struct nouveau_engine *engine, int i) -{ - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; - struct nouveau_fifo *pfifo = nouveau_fifo(engine); - struct nv40_graph_priv *priv = (void *)engine; - unsigned long flags; - - pfifo->pause(pfifo, &flags); - nv04_graph_idle(priv); - - switch (nv_device(priv)->chipset) { - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x45: - case 0x4e: - nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); - nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); - nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); - nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); - switch (nv_device(priv)->chipset) { - case 0x40: - case 0x45: - nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); - nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); - break; - case 0x41: - case 0x42: - case 0x43: - nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); - nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); - break; - default: - break; - } - break; - case 0x44: - case 0x4a: - nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); - break; - case 0x46: - case 0x4c: - case 0x47: - case 0x49: - case 0x4b: - case 0x63: - case 0x67: - case 0x68: - nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr); - nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); - nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); - nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); - switch (nv_device(priv)->chipset) { - case 0x47: - case 0x49: - case 0x4b: - nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); - nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); - break; - default: - break; - } - break; - default: - break; - } - - pfifo->start(pfifo, &flags); -} - -static void -nv40_graph_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle = NULL; - struct nv40_graph_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff; - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff; - u32 show = stat; - int chid; - - engctx = nouveau_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); - - if (stat & NV_PGRAPH_INTR_ERROR) { - if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - handle = nouveau_handle_get_class(engctx, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~NV_PGRAPH_INTR_ERROR; - nouveau_handle_put(handle); - } - - if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { - nv_mask(priv, 0x402000, 0, 0); - } - } - - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); - - if (show) { - nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv10_graph_intr_name, show); - pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); - pr_cont(" nstatus:"); - nouveau_bitfield_print(nv10_graph_nstatus, nstatus); - pr_cont("\n"); - nv_error(priv, - "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 4, nouveau_client_name(engctx), subc, - class, mthd, data); - } - - nouveau_engctx_put(engctx); -} - -static int -nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv40_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv40_graph_intr; - nv_engine(priv)->cclass = &nv40_graph_cclass; - if (nv44_graph_class(priv)) - nv_engine(priv)->sclass = nv44_graph_sclass; - else - nv_engine(priv)->sclass = nv40_graph_sclass; - nv_engine(priv)->tile_prog = nv40_graph_tile_prog; - - priv->base.units = nv40_graph_units; - return 0; -} - -static int -nv40_graph_init(struct nouveau_object *object) -{ - struct nouveau_engine *engine = nv_engine(object); - struct nouveau_fb *pfb = nouveau_fb(object); - struct nv40_graph_priv *priv = (void *)engine; - int ret, i, j; - u32 vramsz; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - /* generate and upload context program */ - ret = nv40_grctx_init(nv_device(priv), &priv->size); - if (ret) - return ret; - - /* No context present currently */ - nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); - - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055); - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); - nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); - - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); - nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); - - j = nv_rd32(priv, 0x1540) & 0xff; - if (j) { - for (i = 0; !(j & 1); j >>= 1, i++) - ; - nv_wr32(priv, 0x405000, i); - } - - if (nv_device(priv)->chipset == 0x40) { - nv_wr32(priv, 0x4009b0, 0x83280fff); - nv_wr32(priv, 0x4009b4, 0x000000a0); - } else { - nv_wr32(priv, 0x400820, 0x83280eff); - nv_wr32(priv, 0x400824, 0x000000a0); - } - - switch (nv_device(priv)->chipset) { - case 0x40: - case 0x45: - nv_wr32(priv, 0x4009b8, 0x0078e366); - nv_wr32(priv, 0x4009bc, 0x0000014c); - break; - case 0x41: - case 0x42: /* pciid also 0x00Cx */ - /* case 0x0120: XXX (pciid) */ - nv_wr32(priv, 0x400828, 0x007596ff); - nv_wr32(priv, 0x40082c, 0x00000108); - break; - case 0x43: - nv_wr32(priv, 0x400828, 0x0072cb77); - nv_wr32(priv, 0x40082c, 0x00000108); - break; - case 0x44: - case 0x46: /* G72 */ - case 0x4a: - case 0x4c: /* G7x-based C51 */ - case 0x4e: - nv_wr32(priv, 0x400860, 0); - nv_wr32(priv, 0x400864, 0); - break; - case 0x47: /* G70 */ - case 0x49: /* G71 */ - case 0x4b: /* G73 */ - nv_wr32(priv, 0x400828, 0x07830610); - nv_wr32(priv, 0x40082c, 0x0000016A); - break; - default: - break; - } - - nv_wr32(priv, 0x400b38, 0x2ffff800); - nv_wr32(priv, 0x400b3c, 0x00006000); - - /* Tiling related stuff. */ - switch (nv_device(priv)->chipset) { - case 0x44: - case 0x4a: - nv_wr32(priv, 0x400bc4, 0x1003d888); - nv_wr32(priv, 0x400bbc, 0xb7a7b500); - break; - case 0x46: - nv_wr32(priv, 0x400bc4, 0x0000e024); - nv_wr32(priv, 0x400bbc, 0xb7a7b520); - break; - case 0x4c: - case 0x4e: - case 0x67: - nv_wr32(priv, 0x400bc4, 0x1003d888); - nv_wr32(priv, 0x400bbc, 0xb7a7b540); - break; - default: - break; - } - - /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) - engine->tile_prog(engine, i); - - /* begin RAM config */ - vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; - switch (nv_device(priv)->chipset) { - case 0x40: - nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x400820, 0); - nv_wr32(priv, 0x400824, 0); - nv_wr32(priv, 0x400864, vramsz); - nv_wr32(priv, 0x400868, vramsz); - break; - default: - switch (nv_device(priv)->chipset) { - case 0x41: - case 0x42: - case 0x43: - case 0x45: - case 0x4e: - case 0x44: - case 0x4a: - nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204)); - break; - default: - nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204)); - break; - } - nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x400840, 0); - nv_wr32(priv, 0x400844, 0); - nv_wr32(priv, 0x4008A0, vramsz); - nv_wr32(priv, 0x4008A4, vramsz); - break; - } - - return 0; -} - -struct nouveau_oclass -nv40_graph_oclass = { - .handle = NV_ENGINE(GR, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_graph_ctor, - .dtor = _nouveau_graph_dtor, - .init = nv40_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h deleted file mode 100644 index ad8209377529..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __NV40_GRAPH_H__ -#define __NV40_GRAPH_H__ - -#include -#include - -/* returns 1 if device is one of the nv4x using the 0x4497 object class, - * helpful to determine a number of other hardware features - */ -static inline int -nv44_graph_class(void *priv) -{ - struct nouveau_device *device = nv_device(priv); - - if ((device->chipset & 0xf0) == 0x60) - return 1; - - return !(0x0baf & (1 << (device->chipset & 0x0f))); -} - -int nv40_grctx_init(struct nouveau_device *, u32 *size); -void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c deleted file mode 100644 index 896e17b56f45..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "nv50.h" - -struct nv50_graph_priv { - struct nouveau_graph base; - spinlock_t lock; - u32 size; -}; - -struct nv50_graph_chan { - struct nouveau_graph_chan base; -}; - -static u64 -nv50_graph_units(struct nouveau_graph *graph) -{ - struct nv50_graph_priv *priv = (void *)graph; - - return nv_rd32(priv, 0x1540); -} - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static int -nv50_graph_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_gpuobj *obj; - int ret; - - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); - *pobject = nv_object(obj); - if (ret) - return ret; - - nv_wo32(obj, 0x00, nv_mclass(obj)); - nv_wo32(obj, 0x04, 0x00000000); - nv_wo32(obj, 0x08, 0x00000000); - nv_wo32(obj, 0x0c, 0x00000000); - return 0; -} - -static struct nouveau_ofuncs -nv50_graph_ofuncs = { - .ctor = nv50_graph_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, -}; - -static struct nouveau_oclass -nv50_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x5097, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - {} -}; - -static struct nouveau_oclass -nv84_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x8297, &nv50_graph_ofuncs }, - {} -}; - -static struct nouveau_oclass -nva0_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x8397, &nv50_graph_ofuncs }, - {} -}; - -static struct nouveau_oclass -nva3_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x8597, &nv50_graph_ofuncs }, - { 0x85c0, &nv50_graph_ofuncs }, - {} -}; - -static struct nouveau_oclass -nvaf_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x85c0, &nv50_graph_ofuncs }, - { 0x8697, &nv50_graph_ofuncs }, - {} -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static int -nv50_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv50_graph_priv *priv = (void *)engine; - struct nv50_graph_chan *chan; - int ret; - - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - priv->size, 0, - NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); - return 0; -} - -static struct nouveau_oclass -nv50_graph_cclass = { - .handle = NV_ENGCTX(GR, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_bitfield nv50_pgraph_status[] = { - { 0x00000001, "BUSY" }, /* set when any bit is set */ - { 0x00000002, "DISPATCH" }, - { 0x00000004, "UNK2" }, - { 0x00000008, "UNK3" }, - { 0x00000010, "UNK4" }, - { 0x00000020, "UNK5" }, - { 0x00000040, "M2MF" }, - { 0x00000080, "UNK7" }, - { 0x00000100, "CTXPROG" }, - { 0x00000200, "VFETCH" }, - { 0x00000400, "CCACHE_PREGEOM" }, - { 0x00000800, "STRMOUT_VATTR_POSTGEOM" }, - { 0x00001000, "VCLIP" }, - { 0x00002000, "RATTR_APLANE" }, - { 0x00004000, "TRAST" }, - { 0x00008000, "CLIPID" }, - { 0x00010000, "ZCULL" }, - { 0x00020000, "ENG2D" }, - { 0x00040000, "RMASK" }, - { 0x00080000, "TPC_RAST" }, - { 0x00100000, "TPC_PROP" }, - { 0x00200000, "TPC_TEX" }, - { 0x00400000, "TPC_GEOM" }, - { 0x00800000, "TPC_MP" }, - { 0x01000000, "ROP" }, - {} -}; - -static const char *const nv50_pgraph_vstatus_0[] = { - "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP", - NULL -}; - -static const char *const nv50_pgraph_vstatus_1[] = { - "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL -}; - -static const char *const nv50_pgraph_vstatus_2[] = { - "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK", - "ROP", NULL -}; - -static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, - const char *const units[], u32 status) -{ - int i; - - nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); - - for (i = 0; units[i] && status; i++) { - if ((status & 7) == 1) - pr_cont(" %s", units[i]); - status >>= 3; - } - if (status) - pr_cont(" (invalid: 0x%x)", status); - pr_cont("\n"); -} - -static int -nv84_graph_tlb_flush(struct nouveau_engine *engine) -{ - struct nouveau_timer *ptimer = nouveau_timer(engine); - struct nv50_graph_priv *priv = (void *)engine; - bool idle, timeout = false; - unsigned long flags; - u64 start; - u32 tmp; - - spin_lock_irqsave(&priv->lock, flags); - nv_mask(priv, 0x400500, 0x00000001, 0x00000000); - - start = ptimer->read(ptimer); - do { - idle = true; - - for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { - if ((tmp & 7) == 1) - idle = false; - } - - for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { - if ((tmp & 7) == 1) - idle = false; - } - - for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { - if ((tmp & 7) == 1) - idle = false; - } - } while (!idle && - !(timeout = ptimer->read(ptimer) - start > 2000000000)); - - if (timeout) { - nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); - - tmp = nv_rd32(priv, 0x400700); - nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); - nouveau_bitfield_print(nv50_pgraph_status, tmp); - pr_cont("\n"); - - nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, - nv_rd32(priv, 0x400380)); - nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, - nv_rd32(priv, 0x400384)); - nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, - nv_rd32(priv, 0x400388)); - } - - - nv_wr32(priv, 0x100c80, 0x00000001); - if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) - nv_error(priv, "vm flush timeout\n"); - nv_mask(priv, 0x400500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->lock, flags); - return timeout ? -EBUSY : 0; -} - -static const struct nouveau_bitfield nv50_mp_exec_errors[] = { - { 0x01, "STACK_UNDERFLOW" }, - { 0x02, "STACK_MISMATCH" }, - { 0x04, "QUADON_ACTIVE" }, - { 0x08, "TIMEOUT" }, - { 0x10, "INVALID_OPCODE" }, - { 0x20, "PM_OVERFLOW" }, - { 0x40, "BREAKPOINT" }, - {} -}; - -static const struct nouveau_bitfield nv50_mpc_traps[] = { - { 0x0000001, "LOCAL_LIMIT_READ" }, - { 0x0000010, "LOCAL_LIMIT_WRITE" }, - { 0x0000040, "STACK_LIMIT" }, - { 0x0000100, "GLOBAL_LIMIT_READ" }, - { 0x0001000, "GLOBAL_LIMIT_WRITE" }, - { 0x0010000, "MP0" }, - { 0x0020000, "MP1" }, - { 0x0040000, "GLOBAL_LIMIT_RED" }, - { 0x0400000, "GLOBAL_LIMIT_ATOM" }, - { 0x4000000, "MP2" }, - {} -}; - -static const struct nouveau_bitfield nv50_tex_traps[] = { - { 0x00000001, "" }, /* any bit set? */ - { 0x00000002, "FAULT" }, - { 0x00000004, "STORAGE_TYPE_MISMATCH" }, - { 0x00000008, "LINEAR_MISMATCH" }, - { 0x00000020, "WRONG_MEMTYPE" }, - {} -}; - -static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = { - { 0x00000001, "NOTIFY" }, - { 0x00000002, "IN" }, - { 0x00000004, "OUT" }, - {} -}; - -static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = { - { 0x00000001, "FAULT" }, - {} -}; - -static const struct nouveau_bitfield nv50_graph_trap_strmout[] = { - { 0x00000001, "FAULT" }, - {} -}; - -static const struct nouveau_bitfield nv50_graph_trap_ccache[] = { - { 0x00000001, "FAULT" }, - {} -}; - -/* There must be a *lot* of these. Will take some time to gather them up. */ -const struct nouveau_enum nv50_data_error_names[] = { - { 0x00000003, "INVALID_OPERATION", NULL }, - { 0x00000004, "INVALID_VALUE", NULL }, - { 0x00000005, "INVALID_ENUM", NULL }, - { 0x00000008, "INVALID_OBJECT", NULL }, - { 0x00000009, "READ_ONLY_OBJECT", NULL }, - { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, - { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, - { 0x0000000c, "INVALID_BITFIELD", NULL }, - { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, - { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, - { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, - { 0x00000010, "RT_DOUBLE_BIND", NULL }, - { 0x00000011, "RT_TYPES_MISMATCH", NULL }, - { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, - { 0x00000015, "FP_TOO_FEW_REGS", NULL }, - { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, - { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, - { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, - { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, - { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, - { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, - { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, - { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, - { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, - { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, - { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, - { 0x00000024, "VP_ZERO_INPUTS", NULL }, - { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, - { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, - { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, - { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, - { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, - { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, - { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, - { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, - { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, - { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, - { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, - { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, - { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, - { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, - { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, - {} -}; - -static const struct nouveau_bitfield nv50_graph_intr_name[] = { - { 0x00000001, "NOTIFY" }, - { 0x00000002, "COMPUTE_QUERY" }, - { 0x00000010, "ILLEGAL_MTHD" }, - { 0x00000020, "ILLEGAL_CLASS" }, - { 0x00000040, "DOUBLE_NOTIFY" }, - { 0x00001000, "CONTEXT_SWITCH" }, - { 0x00010000, "BUFFER_NOTIFY" }, - { 0x00100000, "DATA_ERROR" }, - { 0x00200000, "TRAP" }, - { 0x01000000, "SINGLE_STEP" }, - {} -}; - -static const struct nouveau_bitfield nv50_graph_trap_prop[] = { - { 0x00000004, "SURF_WIDTH_OVERRUN" }, - { 0x00000008, "SURF_HEIGHT_OVERRUN" }, - { 0x00000010, "DST2D_FAULT" }, - { 0x00000020, "ZETA_FAULT" }, - { 0x00000040, "RT_FAULT" }, - { 0x00000080, "CUDA_FAULT" }, - { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" }, - { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" }, - { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" }, - { 0x00000800, "DST2D_LINEAR_MISMATCH" }, - { 0x00001000, "RT_LINEAR_MISMATCH" }, - {} -}; - -static void -nv50_priv_prop_trap(struct nv50_graph_priv *priv, - u32 ustatus_addr, u32 ustatus, u32 tp) -{ - u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); - u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); - u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); - u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); - u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); - u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); - u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); - - /* CUDA memory: l[], g[] or stack. */ - if (ustatus & 0x00000080) { - if (e18 & 0x80000000) { - /* g[] read fault? */ - nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", - tp, e14, e10 | ((e18 >> 24) & 0x1f)); - e18 &= ~0x1f000000; - } else if (e18 & 0xc) { - /* g[] write fault? */ - nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", - tp, e14, e10 | ((e18 >> 7) & 0x1f)); - e18 &= ~0x00000f80; - } else { - nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", - tp, e14, e10); - } - ustatus &= ~0x00000080; - } - if (ustatus) { - nv_error(priv, "TRAP_PROP - TP %d -", tp); - nouveau_bitfield_print(nv50_graph_trap_prop, ustatus); - pr_cont(" - Address %02x%08x\n", e14, e10); - } - nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", - tp, e0c, e18, e1c, e20, e24); -} - -static void -nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) -{ - u32 units = nv_rd32(priv, 0x1540); - u32 addr, mp10, status, pc, oplow, ophigh; - int i; - int mps = 0; - for (i = 0; i < 4; i++) { - if (!(units & 1 << (i+24))) - continue; - if (nv_device(priv)->chipset < 0xa0) - addr = 0x408200 + (tpid << 12) + (i << 7); - else - addr = 0x408100 + (tpid << 11) + (i << 7); - mp10 = nv_rd32(priv, addr + 0x10); - status = nv_rd32(priv, addr + 0x14); - if (!status) - continue; - if (display) { - nv_rd32(priv, addr + 0x20); - pc = nv_rd32(priv, addr + 0x24); - oplow = nv_rd32(priv, addr + 0x70); - ophigh = nv_rd32(priv, addr + 0x74); - nv_error(priv, "TRAP_MP_EXEC - " - "TP %d MP %d:", tpid, i); - nouveau_bitfield_print(nv50_mp_exec_errors, status); - pr_cont(" at %06x warp %d, opcode %08x %08x\n", - pc&0xffffff, pc >> 24, - oplow, ophigh); - } - nv_wr32(priv, addr + 0x10, mp10); - nv_wr32(priv, addr + 0x14, 0); - mps++; - } - if (!mps && display) - nv_error(priv, "TRAP_MP_EXEC - TP %d: " - "No MPs claiming errors?\n", tpid); -} - -static void -nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, - u32 ustatus_new, int display, const char *name) -{ - int tps = 0; - u32 units = nv_rd32(priv, 0x1540); - int i, r; - u32 ustatus_addr, ustatus; - for (i = 0; i < 16; i++) { - if (!(units & (1 << i))) - continue; - if (nv_device(priv)->chipset < 0xa0) - ustatus_addr = ustatus_old + (i << 12); - else - ustatus_addr = ustatus_new + (i << 11); - ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; - if (!ustatus) - continue; - tps++; - switch (type) { - case 6: /* texture error... unknown for now */ - if (display) { - nv_error(priv, "magic set %d:\n", i); - for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) - nv_error(priv, "\t0x%08x: 0x%08x\n", r, - nv_rd32(priv, r)); - if (ustatus) { - nv_error(priv, "%s - TP%d:", name, i); - nouveau_bitfield_print(nv50_tex_traps, - ustatus); - pr_cont("\n"); - ustatus = 0; - } - } - break; - case 7: /* MP error */ - if (ustatus & 0x04030000) { - nv50_priv_mp_trap(priv, i, display); - ustatus &= ~0x04030000; - } - if (ustatus && display) { - nv_error(priv, "%s - TP%d:", name, i); - nouveau_bitfield_print(nv50_mpc_traps, ustatus); - pr_cont("\n"); - ustatus = 0; - } - break; - case 8: /* PROP error */ - if (display) - nv50_priv_prop_trap( - priv, ustatus_addr, ustatus, i); - ustatus = 0; - break; - } - if (ustatus) { - if (display) - nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); - } - nv_wr32(priv, ustatus_addr, 0xc0000000); - } - - if (!tps && display) - nv_warn(priv, "%s - No TPs claiming errors?\n", name); -} - -static int -nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, - int chid, u64 inst, struct nouveau_object *engctx) -{ - u32 status = nv_rd32(priv, 0x400108); - u32 ustatus; - - if (!status && display) { - nv_error(priv, "TRAP: no units reporting traps?\n"); - return 1; - } - - /* DISPATCH: Relays commands to other units and handles NOTIFY, - * COND, QUERY. If you get a trap from it, the command is still stuck - * in DISPATCH and you need to do something about it. */ - if (status & 0x001) { - ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; - if (!ustatus && display) { - nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); - } - - nv_wr32(priv, 0x400500, 0x00000000); - - /* Known to be triggered by screwed up NOTIFY and COND... */ - if (ustatus & 0x00000001) { - u32 addr = nv_rd32(priv, 0x400808); - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00001ffc); - u32 datal = nv_rd32(priv, 0x40080c); - u32 datah = nv_rd32(priv, 0x400810); - u32 class = nv_rd32(priv, 0x400814); - u32 r848 = nv_rd32(priv, 0x400848); - - nv_error(priv, "TRAP DISPATCH_FAULT\n"); - if (display && (addr & 0x80000000)) { - nv_error(priv, - "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", - chid, inst, - nouveau_client_name(engctx), subc, - class, mthd, datah, datal, addr, r848); - } else - if (display) { - nv_error(priv, "no stuck command?\n"); - } - - nv_wr32(priv, 0x400808, 0); - nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); - nv_wr32(priv, 0x400848, 0); - ustatus &= ~0x00000001; - } - - if (ustatus & 0x00000002) { - u32 addr = nv_rd32(priv, 0x40084c); - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, 0x40085c); - u32 class = nv_rd32(priv, 0x400814); - - nv_error(priv, "TRAP DISPATCH_QUERY\n"); - if (display && (addr & 0x80000000)) { - nv_error(priv, - "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", - chid, inst, - nouveau_client_name(engctx), subc, - class, mthd, data, addr); - } else - if (display) { - nv_error(priv, "no stuck command?\n"); - } - - nv_wr32(priv, 0x40084c, 0); - ustatus &= ~0x00000002; - } - - if (ustatus && display) { - nv_error(priv, "TRAP_DISPATCH (unknown " - "0x%08x)\n", ustatus); - } - - nv_wr32(priv, 0x400804, 0xc0000000); - nv_wr32(priv, 0x400108, 0x001); - status &= ~0x001; - if (!status) - return 0; - } - - /* M2MF: Memory to memory copy engine. */ - if (status & 0x002) { - u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; - if (display) { - nv_error(priv, "TRAP_M2MF"); - nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); - pr_cont("\n"); - nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", - nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), - nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); - - } - - /* No sane way found yet -- just reset the bugger. */ - nv_wr32(priv, 0x400040, 2); - nv_wr32(priv, 0x400040, 0); - nv_wr32(priv, 0x406800, 0xc0000000); - nv_wr32(priv, 0x400108, 0x002); - status &= ~0x002; - } - - /* VFETCH: Fetches data from vertex buffers. */ - if (status & 0x004) { - u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; - if (display) { - nv_error(priv, "TRAP_VFETCH"); - nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); - pr_cont("\n"); - nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", - nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), - nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); - } - - nv_wr32(priv, 0x400c04, 0xc0000000); - nv_wr32(priv, 0x400108, 0x004); - status &= ~0x004; - } - - /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ - if (status & 0x008) { - ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; - if (display) { - nv_error(priv, "TRAP_STRMOUT"); - nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); - pr_cont("\n"); - nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", - nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), - nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); - - } - - /* No sane way found yet -- just reset the bugger. */ - nv_wr32(priv, 0x400040, 0x80); - nv_wr32(priv, 0x400040, 0); - nv_wr32(priv, 0x401800, 0xc0000000); - nv_wr32(priv, 0x400108, 0x008); - status &= ~0x008; - } - - /* CCACHE: Handles code and c[] caches and fills them. */ - if (status & 0x010) { - ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; - if (display) { - nv_error(priv, "TRAP_CCACHE"); - nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); - pr_cont("\n"); - nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" - " %08x %08x %08x\n", - nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), - nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), - nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), - nv_rd32(priv, 0x40501c)); - - } - - nv_wr32(priv, 0x405018, 0xc0000000); - nv_wr32(priv, 0x400108, 0x010); - status &= ~0x010; - } - - /* Unknown, not seen yet... 0x402000 is the only trap status reg - * remaining, so try to handle it anyway. Perhaps related to that - * unknown DMA slot on tesla? */ - if (status & 0x20) { - ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; - if (display) - nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); - nv_wr32(priv, 0x402000, 0xc0000000); - /* no status modifiction on purpose */ - } - - /* TEXTURE: CUDA texturing units */ - if (status & 0x040) { - nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, - "TRAP_TEXTURE"); - nv_wr32(priv, 0x400108, 0x040); - status &= ~0x040; - } - - /* MP: CUDA execution engines. */ - if (status & 0x080) { - nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, - "TRAP_MP"); - nv_wr32(priv, 0x400108, 0x080); - status &= ~0x080; - } - - /* PROP: Handles TP-initiated uncached memory accesses: - * l[], g[], stack, 2d surfaces, render targets. */ - if (status & 0x100) { - nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, - "TRAP_PROP"); - nv_wr32(priv, 0x400108, 0x100); - status &= ~0x100; - } - - if (status) { - if (display) - nv_error(priv, "TRAP: unknown 0x%08x\n", status); - nv_wr32(priv, 0x400108, status); - } - - return 1; -} - -static void -nv50_graph_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle = NULL; - struct nv50_graph_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, 0x400100); - u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; - u32 addr = nv_rd32(priv, 0x400704); - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, 0x400708); - u32 class = nv_rd32(priv, 0x400814); - u32 show = stat, show_bitfield = stat; - int chid; - - engctx = nouveau_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); - - if (stat & 0x00000010) { - handle = nouveau_handle_get_class(engctx, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~0x00000010; - nouveau_handle_put(handle); - } - - if (show & 0x00100000) { - u32 ecode = nv_rd32(priv, 0x400110); - nv_error(priv, "DATA_ERROR "); - nouveau_enum_print(nv50_data_error_names, ecode); - pr_cont("\n"); - show_bitfield &= ~0x00100000; - } - - if (stat & 0x00200000) { - if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, - engctx)) - show &= ~0x00200000; - show_bitfield &= ~0x00200000; - } - - nv_wr32(priv, 0x400100, stat); - nv_wr32(priv, 0x400500, 0x00010001); - - if (show) { - show &= show_bitfield; - if (show) { - nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv50_graph_intr_name, show); - pr_cont("\n"); - } - nv_error(priv, - "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, (u64)inst << 12, nouveau_client_name(engctx), - subc, class, mthd, data); - } - - if (nv_rd32(priv, 0x400824) & (1 << 31)) - nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); - - nouveau_engctx_put(engctx); -} - -static int -nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv50_graph_priv *priv; - int ret; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00201000; - nv_subdev(priv)->intr = nv50_graph_intr; - nv_engine(priv)->cclass = &nv50_graph_cclass; - - priv->base.units = nv50_graph_units; - - switch (nv_device(priv)->chipset) { - case 0x50: - nv_engine(priv)->sclass = nv50_graph_sclass; - break; - case 0x84: - case 0x86: - case 0x92: - case 0x94: - case 0x96: - case 0x98: - nv_engine(priv)->sclass = nv84_graph_sclass; - break; - case 0xa0: - case 0xaa: - case 0xac: - nv_engine(priv)->sclass = nva0_graph_sclass; - break; - case 0xa3: - case 0xa5: - case 0xa8: - nv_engine(priv)->sclass = nva3_graph_sclass; - break; - case 0xaf: - nv_engine(priv)->sclass = nvaf_graph_sclass; - break; - - } - - /* unfortunate hw bug workaround... */ - if (nv_device(priv)->chipset != 0x50 && - nv_device(priv)->chipset != 0xac) - nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush; - - spin_lock_init(&priv->lock); - return 0; -} - -static int -nv50_graph_init(struct nouveau_object *object) -{ - struct nv50_graph_priv *priv = (void *)object; - int ret, units, i; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ - nv_wr32(priv, 0x40008c, 0x00000004); - - /* reset/enable traps and interrupts */ - nv_wr32(priv, 0x400804, 0xc0000000); - nv_wr32(priv, 0x406800, 0xc0000000); - nv_wr32(priv, 0x400c04, 0xc0000000); - nv_wr32(priv, 0x401800, 0xc0000000); - nv_wr32(priv, 0x405018, 0xc0000000); - nv_wr32(priv, 0x402000, 0xc0000000); - - units = nv_rd32(priv, 0x001540); - for (i = 0; i < 16; i++) { - if (!(units & (1 << i))) - continue; - - if (nv_device(priv)->chipset < 0xa0) { - nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); - nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); - nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); - } else { - nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); - nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); - nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); - } - } - - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - nv_wr32(priv, 0x400500, 0x00010001); - - /* upload context program, initialise ctxctl defaults */ - ret = nv50_grctx_init(nv_device(priv), &priv->size); - if (ret) - return ret; - - nv_wr32(priv, 0x400824, 0x00000000); - nv_wr32(priv, 0x400828, 0x00000000); - nv_wr32(priv, 0x40082c, 0x00000000); - nv_wr32(priv, 0x400830, 0x00000000); - nv_wr32(priv, 0x40032c, 0x00000000); - nv_wr32(priv, 0x400330, 0x00000000); - - /* some unknown zcull magic */ - switch (nv_device(priv)->chipset & 0xf0) { - case 0x50: - case 0x80: - case 0x90: - nv_wr32(priv, 0x402ca8, 0x00000800); - break; - case 0xa0: - default: - if (nv_device(priv)->chipset == 0xa0 || - nv_device(priv)->chipset == 0xaa || - nv_device(priv)->chipset == 0xac) { - nv_wr32(priv, 0x402ca8, 0x00000802); - } else { - nv_wr32(priv, 0x402cc0, 0x00000000); - nv_wr32(priv, 0x402ca8, 0x00000002); - } - - break; - } - - /* zero out zcull regions */ - for (i = 0; i < 8; i++) { - nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); - nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); - nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); - nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); - } - return 0; -} - -struct nouveau_oclass -nv50_graph_oclass = { - .handle = NV_ENGINE(GR, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_graph_ctor, - .dtor = _nouveau_graph_dtor, - .init = nv50_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h deleted file mode 100644 index 0505fb419bde..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __NV50_GRAPH_H__ -#define __NV50_GRAPH_H__ - -int nv50_grctx_init(struct nouveau_device *, u32 *size); -void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c deleted file mode 100644 index 3e90e437dbbe..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c +++ /dev/null @@ -1,1667 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Zero Bandwidth Clear - ******************************************************************************/ - -static void -nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc) -{ - if (priv->zbc_color[zbc].format) { - nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); - nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); - nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); - nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); - } - nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); - nv_wr32(priv, 0x405820, zbc); - nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ -} - -static int -nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format, - const u32 ds[4], const u32 l2[4]) -{ - struct nouveau_ltc *ltc = nouveau_ltc(priv); - int zbc = -ENOSPC, i; - - for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { - if (priv->zbc_color[i].format) { - if (priv->zbc_color[i].format != format) - continue; - if (memcmp(priv->zbc_color[i].ds, ds, sizeof( - priv->zbc_color[i].ds))) - continue; - if (memcmp(priv->zbc_color[i].l2, l2, sizeof( - priv->zbc_color[i].l2))) { - WARN_ON(1); - return -EINVAL; - } - return i; - } else { - zbc = (zbc < 0) ? i : zbc; - } - } - - if (zbc < 0) - return zbc; - - memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); - memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); - priv->zbc_color[zbc].format = format; - ltc->zbc_color_get(ltc, zbc, l2); - nvc0_graph_zbc_clear_color(priv, zbc); - return zbc; -} - -static void -nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc) -{ - if (priv->zbc_depth[zbc].format) - nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); - nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); - nv_wr32(priv, 0x405820, zbc); - nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ -} - -static int -nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format, - const u32 ds, const u32 l2) -{ - struct nouveau_ltc *ltc = nouveau_ltc(priv); - int zbc = -ENOSPC, i; - - for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { - if (priv->zbc_depth[i].format) { - if (priv->zbc_depth[i].format != format) - continue; - if (priv->zbc_depth[i].ds != ds) - continue; - if (priv->zbc_depth[i].l2 != l2) { - WARN_ON(1); - return -EINVAL; - } - return i; - } else { - zbc = (zbc < 0) ? i : zbc; - } - } - - if (zbc < 0) - return zbc; - - priv->zbc_depth[zbc].format = format; - priv->zbc_depth[zbc].ds = ds; - priv->zbc_depth[zbc].l2 = l2; - ltc->zbc_depth_get(ltc, zbc, l2); - nvc0_graph_zbc_clear_depth(priv, zbc); - return zbc; -} - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static int -nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size) -{ - struct nvc0_graph_priv *priv = (void *)object->engine; - union { - struct fermi_a_zbc_color_v0 v0; - } *args = data; - int ret; - - if (nvif_unpack(args->v0, 0, 0, false)) { - switch (args->v0.format) { - case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: - case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: - case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: - case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: - case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: - case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: - case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: - case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: - case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: - case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: - case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: - case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: - case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: - case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: - case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: - case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: - case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: - case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: - case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: - ret = nvc0_graph_zbc_color_get(priv, args->v0.format, - args->v0.ds, - args->v0.l2); - if (ret >= 0) { - args->v0.index = ret; - return 0; - } - break; - default: - return -EINVAL; - } - } - - return ret; -} - -static int -nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size) -{ - struct nvc0_graph_priv *priv = (void *)object->engine; - union { - struct fermi_a_zbc_depth_v0 v0; - } *args = data; - int ret; - - if (nvif_unpack(args->v0, 0, 0, false)) { - switch (args->v0.format) { - case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: - ret = nvc0_graph_zbc_depth_get(priv, args->v0.format, - args->v0.ds, - args->v0.l2); - return (ret >= 0) ? 0 : -ENOSPC; - default: - return -EINVAL; - } - } - - return ret; -} - -static int -nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) -{ - switch (mthd) { - case FERMI_A_ZBC_COLOR: - return nvc0_fermi_mthd_zbc_color(object, data, size); - case FERMI_A_ZBC_DEPTH: - return nvc0_fermi_mthd_zbc_depth(object, data, size); - default: - break; - } - return -EINVAL; -} - -struct nouveau_ofuncs -nvc0_fermi_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nvc0_fermi_mthd, -}; - -static int -nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd, - void *pdata, u32 size) -{ - struct nvc0_graph_priv *priv = (void *)nv_engine(object); - if (size >= sizeof(u32)) { - u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; - nv_wr32(priv, 0x419e44, data); - nv_wr32(priv, 0x419e4c, data); - return 0; - } - return -EINVAL; -} - -struct nouveau_omthds -nvc0_graph_9097_omthds[] = { - { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions }, - {} -}; - -struct nouveau_omthds -nvc0_graph_90c0_omthds[] = { - { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions }, - {} -}; - -struct nouveau_oclass -nvc0_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -int -nvc0_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *args, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_vm *vm = nouveau_client(parent)->vm; - struct nvc0_graph_priv *priv = (void *)engine; - struct nvc0_graph_data *data = priv->mmio_data; - struct nvc0_graph_mmio *mmio = priv->mmio_list; - struct nvc0_graph_chan *chan; - int ret, i; - - /* allocate memory for context, and fill with default values */ - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - priv->size, 0x100, - NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - /* allocate memory for a "mmio list" buffer that's used by the HUB - * fuc to modify some per-context register settings on first load - * of the context. - */ - ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, - &chan->mmio); - if (ret) - return ret; - - ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, - NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, - &chan->mmio_vma); - if (ret) - return ret; - - /* allocate buffers referenced by mmio list */ - for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { - ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size, - data->align, 0, &chan->data[i].mem); - if (ret) - return ret; - - ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access, - &chan->data[i].vma); - if (ret) - return ret; - - data++; - } - - /* finally, fill in the mmio list and point the context at it */ - for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { - u32 addr = mmio->addr; - u32 data = mmio->data; - - if (mmio->buffer >= 0) { - u64 info = chan->data[mmio->buffer].vma.offset; - data |= info >> mmio->shift; - } - - nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); - nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); - mmio++; - } - - for (i = 0; i < priv->size; i += 4) - nv_wo32(chan, i, priv->data[i / 4]); - - if (!priv->firmware) { - nv_wo32(chan, 0x00, chan->mmio_nr / 2); - nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); - } else { - nv_wo32(chan, 0xf4, 0); - nv_wo32(chan, 0xf8, 0); - nv_wo32(chan, 0x10, chan->mmio_nr / 2); - nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); - nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); - nv_wo32(chan, 0x1c, 1); - nv_wo32(chan, 0x20, 0); - nv_wo32(chan, 0x28, 0); - nv_wo32(chan, 0x2c, 0); - } - - return 0; -} - -void -nvc0_graph_context_dtor(struct nouveau_object *object) -{ - struct nvc0_graph_chan *chan = (void *)object; - int i; - - for (i = 0; i < ARRAY_SIZE(chan->data); i++) { - nouveau_gpuobj_unmap(&chan->data[i].vma); - nouveau_gpuobj_ref(NULL, &chan->data[i].mem); - } - - nouveau_gpuobj_unmap(&chan->mmio_vma); - nouveau_gpuobj_ref(NULL, &chan->mmio); - - nouveau_graph_context_destroy(&chan->base); -} - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nvc0_graph_init_main_0[] = { - { 0x400080, 1, 0x04, 0x003083c2 }, - { 0x400088, 1, 0x04, 0x00006fe7 }, - { 0x40008c, 1, 0x04, 0x00000000 }, - { 0x400090, 1, 0x04, 0x00000030 }, - { 0x40013c, 1, 0x04, 0x013901f7 }, - { 0x400140, 1, 0x04, 0x00000100 }, - { 0x400144, 1, 0x04, 0x00000000 }, - { 0x400148, 1, 0x04, 0x00000110 }, - { 0x400138, 1, 0x04, 0x00000000 }, - { 0x400130, 2, 0x04, 0x00000000 }, - { 0x400124, 1, 0x04, 0x00000002 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_fe_0[] = { - { 0x40415c, 1, 0x04, 0x00000000 }, - { 0x404170, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_pri_0[] = { - { 0x404488, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_rstr2d_0[] = { - { 0x407808, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_pd_0[] = { - { 0x406024, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405908, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_scc_0[] = { - { 0x40803c, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_prop_0[] = { - { 0x4184a0, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_gpc_unk_0[] = { - { 0x418604, 1, 0x04, 0x00000000 }, - { 0x418680, 1, 0x04, 0x00000000 }, - { 0x418714, 1, 0x04, 0x80000000 }, - { 0x418384, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_setup_0[] = { - { 0x418814, 3, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_crstr_0[] = { - { 0x418b04, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_setup_1[] = { - { 0x4188c8, 1, 0x04, 0x80000000 }, - { 0x4188cc, 1, 0x04, 0x00000000 }, - { 0x4188d0, 1, 0x04, 0x00010000 }, - { 0x4188d4, 1, 0x04, 0x00000001 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_zcull_0[] = { - { 0x418910, 1, 0x04, 0x00010001 }, - { 0x418914, 1, 0x04, 0x00000301 }, - { 0x418918, 1, 0x04, 0x00800000 }, - { 0x418980, 1, 0x04, 0x77777770 }, - { 0x418984, 3, 0x04, 0x77777777 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_gpm_0[] = { - { 0x418c04, 1, 0x04, 0x00000000 }, - { 0x418c88, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_gpc_unk_1[] = { - { 0x418d00, 1, 0x04, 0x00000000 }, - { 0x418f08, 1, 0x04, 0x00000000 }, - { 0x418e00, 1, 0x04, 0x00000050 }, - { 0x418e08, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_gcc_0[] = { - { 0x41900c, 1, 0x04, 0x00000000 }, - { 0x419018, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_tpccs_0[] = { - { 0x419d08, 2, 0x04, 0x00000000 }, - { 0x419d10, 1, 0x04, 0x00000014 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_tex_0[] = { - { 0x419ab0, 1, 0x04, 0x00000000 }, - { 0x419ab8, 1, 0x04, 0x000000e7 }, - { 0x419abc, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_pe_0[] = { - { 0x41980c, 3, 0x04, 0x00000000 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x41984c, 1, 0x04, 0x00005bc5 }, - { 0x419850, 4, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_l1c_0[] = { - { 0x419c98, 1, 0x04, 0x00000000 }, - { 0x419ca8, 1, 0x04, 0x80000000 }, - { 0x419cb4, 1, 0x04, 0x00000000 }, - { 0x419cb8, 1, 0x04, 0x00008bf4 }, - { 0x419cbc, 1, 0x04, 0x28137606 }, - { 0x419cc0, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_wwdx_0[] = { - { 0x419bd4, 1, 0x04, 0x00800000 }, - { 0x419bdc, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_tpccs_1[] = { - { 0x419d2c, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_mpc_0[] = { - { 0x419c0c, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc0_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000000 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x00001100 }, - { 0x419eac, 1, 0x04, 0x11100702 }, - { 0x419eb0, 1, 0x04, 0x00000003 }, - { 0x419eb4, 4, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x06060618 }, - { 0x419ed0, 1, 0x04, 0x0eff0e38 }, - { 0x419ed4, 1, 0x04, 0x011104f1 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419f2c, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_be_0[] = { - { 0x40880c, 1, 0x04, 0x00000000 }, - { 0x408910, 9, 0x04, 0x00000000 }, - { 0x408950, 1, 0x04, 0x00000000 }, - { 0x408954, 1, 0x04, 0x0000ffff }, - { 0x408984, 1, 0x04, 0x00000000 }, - { 0x408988, 1, 0x04, 0x08040201 }, - { 0x40898c, 1, 0x04, 0x80402010 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_fe_1[] = { - { 0x4040f0, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc0_graph_init_pe_1[] = { - { 0x419880, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_pack -nvc0_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc0_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc0_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc0_graph_init_tex_0 }, - { nvc0_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc0_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - { nvc0_graph_init_pe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -void -nvc0_graph_zbc_init(struct nvc0_graph_priv *priv) -{ - const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; - const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; - const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; - const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; - struct nouveau_ltc *ltc = nouveau_ltc(priv); - int index; - - if (!priv->zbc_color[0].format) { - nvc0_graph_zbc_color_get(priv, 1, & zero[0], &zero[4]); - nvc0_graph_zbc_color_get(priv, 2, & one[0], &one[4]); - nvc0_graph_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); - nvc0_graph_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); - nvc0_graph_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); - nvc0_graph_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); - } - - for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) - nvc0_graph_zbc_clear_color(priv, index); - for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) - nvc0_graph_zbc_clear_depth(priv, index); -} - -void -nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) -{ - const struct nvc0_graph_pack *pack; - const struct nvc0_graph_init *init; - - pack_for_each_init(init, pack, p) { - u32 next = init->addr + init->count * init->pitch; - u32 addr = init->addr; - while (addr < next) { - nv_wr32(priv, addr, init->data); - addr += init->pitch; - } - } -} - -void -nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) -{ - const struct nvc0_graph_pack *pack; - const struct nvc0_graph_init *init; - u32 data = 0; - - nv_wr32(priv, 0x400208, 0x80000000); - - pack_for_each_init(init, pack, p) { - u32 next = init->addr + init->count * init->pitch; - u32 addr = init->addr; - - if ((pack == p && init == p->init) || data != init->data) { - nv_wr32(priv, 0x400204, init->data); - data = init->data; - } - - while (addr < next) { - nv_wr32(priv, 0x400200, addr); - nv_wait(priv, 0x400700, 0x00000002, 0x00000000); - addr += init->pitch; - } - } - - nv_wr32(priv, 0x400208, 0x00000000); -} - -void -nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) -{ - const struct nvc0_graph_pack *pack; - const struct nvc0_graph_init *init; - u32 data = 0; - - pack_for_each_init(init, pack, p) { - u32 ctrl = 0x80000000 | pack->type; - u32 next = init->addr + init->count * init->pitch; - u32 addr = init->addr; - - if ((pack == p && init == p->init) || data != init->data) { - nv_wr32(priv, 0x40448c, init->data); - data = init->data; - } - - while (addr < next) { - nv_wr32(priv, 0x404488, ctrl | (addr << 14)); - addr += init->pitch; - } - } -} - -u64 -nvc0_graph_units(struct nouveau_graph *graph) -{ - struct nvc0_graph_priv *priv = (void *)graph; - u64 cfg; - - cfg = (u32)priv->gpc_nr; - cfg |= (u32)priv->tpc_total << 8; - cfg |= (u64)priv->rop_nr << 32; - - return cfg; -} - -static const struct nouveau_enum nve0_sked_error[] = { - { 7, "CONSTANT_BUFFER_SIZE" }, - { 9, "LOCAL_MEMORY_SIZE_POS" }, - { 10, "LOCAL_MEMORY_SIZE_NEG" }, - { 11, "WARP_CSTACK_SIZE" }, - { 12, "TOTAL_TEMP_SIZE" }, - { 13, "REGISTER_COUNT" }, - { 18, "TOTAL_THREADS" }, - { 20, "PROGRAM_OFFSET" }, - { 21, "SHARED_MEMORY_SIZE" }, - { 25, "SHARED_CONFIG_TOO_SMALL" }, - { 26, "TOTAL_REGISTER_COUNT" }, - {} -}; - -static const struct nouveau_enum nvc0_gpc_rop_error[] = { - { 1, "RT_PITCH_OVERRUN" }, - { 4, "RT_WIDTH_OVERRUN" }, - { 5, "RT_HEIGHT_OVERRUN" }, - { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, - { 8, "RT_STORAGE_TYPE_MISMATCH" }, - { 10, "RT_LINEAR_MISMATCH" }, - {} -}; - -static void -nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc) -{ - u32 trap[4]; - int i; - - trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); - trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); - trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); - trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); - - nv_error(priv, "GPC%d/PROP trap:", gpc); - for (i = 0; i <= 29; ++i) { - if (!(trap[0] & (1 << i))) - continue; - pr_cont(" "); - nouveau_enum_print(nvc0_gpc_rop_error, i); - } - pr_cont("\n"); - - nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", - trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, - trap[3] & 0xff); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); -} - -static const struct nouveau_enum nvc0_mp_warp_error[] = { - { 0x00, "NO_ERROR" }, - { 0x01, "STACK_MISMATCH" }, - { 0x05, "MISALIGNED_PC" }, - { 0x08, "MISALIGNED_GPR" }, - { 0x09, "INVALID_OPCODE" }, - { 0x0d, "GPR_OUT_OF_BOUNDS" }, - { 0x0e, "MEM_OUT_OF_BOUNDS" }, - { 0x0f, "UNALIGNED_MEM_ACCESS" }, - { 0x11, "INVALID_PARAM" }, - {} -}; - -static const struct nouveau_bitfield nvc0_mp_global_error[] = { - { 0x00000004, "MULTIPLE_WARP_ERRORS" }, - { 0x00000008, "OUT_OF_STACK_SPACE" }, - {} -}; - -static void -nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc) -{ - u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); - u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); - - nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); - nouveau_bitfield_print(nvc0_mp_global_error, gerr); - if (werr) { - pr_cont(" "); - nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff); - } - pr_cont("\n"); - - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); -} - -static void -nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) -{ - u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); - - if (stat & 0x00000001) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); - nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); - stat &= ~0x00000001; - } - - if (stat & 0x00000002) { - nvc0_graph_trap_mp(priv, gpc, tpc); - stat &= ~0x00000002; - } - - if (stat & 0x00000004) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); - nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); - stat &= ~0x00000004; - } - - if (stat & 0x00000008) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); - nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); - stat &= ~0x00000008; - } - - if (stat) { - nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); - } -} - -static void -nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) -{ - u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); - int tpc; - - if (stat & 0x00000001) { - nvc0_graph_trap_gpc_rop(priv, gpc); - stat &= ~0x00000001; - } - - if (stat & 0x00000002) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); - nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - stat &= ~0x00000002; - } - - if (stat & 0x00000004) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); - nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - stat &= ~0x00000004; - } - - if (stat & 0x00000008) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); - nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - stat &= ~0x00000009; - } - - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - u32 mask = 0x00010000 << tpc; - if (stat & mask) { - nvc0_graph_trap_tpc(priv, gpc, tpc); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); - stat &= ~mask; - } - } - - if (stat) { - nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); - } -} - -static void -nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) -{ - u32 trap = nv_rd32(priv, 0x400108); - int rop, gpc, i; - - if (trap & 0x00000001) { - u32 stat = nv_rd32(priv, 0x404000); - nv_error(priv, "DISPATCH 0x%08x\n", stat); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000001); - trap &= ~0x00000001; - } - - if (trap & 0x00000002) { - u32 stat = nv_rd32(priv, 0x404600); - nv_error(priv, "M2MF 0x%08x\n", stat); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000002); - trap &= ~0x00000002; - } - - if (trap & 0x00000008) { - u32 stat = nv_rd32(priv, 0x408030); - nv_error(priv, "CCACHE 0x%08x\n", stat); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000008); - trap &= ~0x00000008; - } - - if (trap & 0x00000010) { - u32 stat = nv_rd32(priv, 0x405840); - nv_error(priv, "SHADER 0x%08x\n", stat); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000010); - trap &= ~0x00000010; - } - - if (trap & 0x00000040) { - u32 stat = nv_rd32(priv, 0x40601c); - nv_error(priv, "UNK6 0x%08x\n", stat); - nv_wr32(priv, 0x40601c, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000040); - trap &= ~0x00000040; - } - - if (trap & 0x00000080) { - u32 stat = nv_rd32(priv, 0x404490); - nv_error(priv, "MACRO 0x%08x\n", stat); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000080); - trap &= ~0x00000080; - } - - if (trap & 0x00000100) { - u32 stat = nv_rd32(priv, 0x407020); - - nv_error(priv, "SKED:"); - for (i = 0; i <= 29; ++i) { - if (!(stat & (1 << i))) - continue; - pr_cont(" "); - nouveau_enum_print(nve0_sked_error, i); - } - pr_cont("\n"); - - if (stat & 0x3fffffff) - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x400108, 0x00000100); - trap &= ~0x00000100; - } - - if (trap & 0x01000000) { - u32 stat = nv_rd32(priv, 0x400118); - for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { - u32 mask = 0x00000001 << gpc; - if (stat & mask) { - nvc0_graph_trap_gpc(priv, gpc); - nv_wr32(priv, 0x400118, mask); - stat &= ~mask; - } - } - nv_wr32(priv, 0x400108, 0x01000000); - trap &= ~0x01000000; - } - - if (trap & 0x02000000) { - for (rop = 0; rop < priv->rop_nr; rop++) { - u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); - u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); - nv_error(priv, "ROP%d 0x%08x 0x%08x\n", - rop, statz, statc); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - } - nv_wr32(priv, 0x400108, 0x02000000); - trap &= ~0x02000000; - } - - if (trap) { - nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); - nv_wr32(priv, 0x400108, trap); - } -} - -static void -nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) -{ - nv_error(priv, "%06x - done 0x%08x\n", base, - nv_rd32(priv, base + 0x400)); - nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), - nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); - nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), - nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); -} - -void -nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) -{ - u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; - u32 gpc; - - nvc0_graph_ctxctl_debug_unit(priv, 0x409000); - for (gpc = 0; gpc < gpcnr; gpc++) - nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); -} - -static void -nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) -{ - u32 stat = nv_rd32(priv, 0x409c18); - - if (stat & 0x00000001) { - u32 code = nv_rd32(priv, 0x409814); - if (code == E_BAD_FWMTHD) { - u32 class = nv_rd32(priv, 0x409808); - u32 addr = nv_rd32(priv, 0x40980c); - u32 subc = (addr & 0x00070000) >> 16; - u32 mthd = (addr & 0x00003ffc); - u32 data = nv_rd32(priv, 0x409810); - - nv_error(priv, "FECS MTHD subc %d class 0x%04x " - "mthd 0x%04x data 0x%08x\n", - subc, class, mthd, data); - - nv_wr32(priv, 0x409c20, 0x00000001); - stat &= ~0x00000001; - } else { - nv_error(priv, "FECS ucode error %d\n", code); - } - } - - if (stat & 0x00080000) { - nv_error(priv, "FECS watchdog timeout\n"); - nvc0_graph_ctxctl_debug(priv); - nv_wr32(priv, 0x409c20, 0x00080000); - stat &= ~0x00080000; - } - - if (stat) { - nv_error(priv, "FECS 0x%08x\n", stat); - nvc0_graph_ctxctl_debug(priv); - nv_wr32(priv, 0x409c20, stat); - } -} - -static void -nvc0_graph_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle; - struct nvc0_graph_priv *priv = (void *)subdev; - u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; - u32 stat = nv_rd32(priv, 0x400100); - u32 addr = nv_rd32(priv, 0x400704); - u32 mthd = (addr & 0x00003ffc); - u32 subc = (addr & 0x00070000) >> 16; - u32 data = nv_rd32(priv, 0x400708); - u32 code = nv_rd32(priv, 0x400110); - u32 class = nv_rd32(priv, 0x404200 + (subc * 4)); - int chid; - - engctx = nouveau_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); - - if (stat & 0x00000010) { - handle = nouveau_handle_get_class(engctx, class); - if (!handle || nv_call(handle->object, mthd, data)) { - nv_error(priv, - "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), - subc, class, mthd, data); - } - nouveau_handle_put(handle); - nv_wr32(priv, 0x400100, 0x00000010); - stat &= ~0x00000010; - } - - if (stat & 0x00000020) { - nv_error(priv, - "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, - class, mthd, data); - nv_wr32(priv, 0x400100, 0x00000020); - stat &= ~0x00000020; - } - - if (stat & 0x00100000) { - nv_error(priv, "DATA_ERROR ["); - nouveau_enum_print(nv50_data_error_names, code); - pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, - class, mthd, data); - nv_wr32(priv, 0x400100, 0x00100000); - stat &= ~0x00100000; - } - - if (stat & 0x00200000) { - nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, - nouveau_client_name(engctx)); - nvc0_graph_trap_intr(priv); - nv_wr32(priv, 0x400100, 0x00200000); - stat &= ~0x00200000; - } - - if (stat & 0x00080000) { - nvc0_graph_ctxctl_isr(priv); - nv_wr32(priv, 0x400100, 0x00080000); - stat &= ~0x00080000; - } - - if (stat) { - nv_error(priv, "unknown stat 0x%08x\n", stat); - nv_wr32(priv, 0x400100, stat); - } - - nv_wr32(priv, 0x400500, 0x00010001); - nouveau_engctx_put(engctx); -} - -void -nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, - struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) -{ - int i; - - nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); - for (i = 0; i < data->size / 4; i++) - nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); - - nv_wr32(priv, fuc_base + 0x0180, 0x01000000); - for (i = 0; i < code->size / 4; i++) { - if ((i & 0x3f) == 0) - nv_wr32(priv, fuc_base + 0x0188, i >> 6); - nv_wr32(priv, fuc_base + 0x0184, code->data[i]); - } - - /* code must be padded to 0x40 words */ - for (; i & 0x3f; i++) - nv_wr32(priv, fuc_base + 0x0184, 0); -} - -static void -nvc0_graph_init_csdata(struct nvc0_graph_priv *priv, - const struct nvc0_graph_pack *pack, - u32 falcon, u32 starstar, u32 base) -{ - const struct nvc0_graph_pack *iter; - const struct nvc0_graph_init *init; - u32 addr = ~0, prev = ~0, xfer = 0; - u32 star, temp; - - nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); - star = nv_rd32(priv, falcon + 0x01c4); - temp = nv_rd32(priv, falcon + 0x01c4); - if (temp > star) - star = temp; - nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); - - pack_for_each_init(init, iter, pack) { - u32 head = init->addr - base; - u32 tail = head + init->count * init->pitch; - while (head < tail) { - if (head != prev + 4 || xfer >= 32) { - if (xfer) { - u32 data = ((--xfer << 26) | addr); - nv_wr32(priv, falcon + 0x01c4, data); - star += 4; - } - addr = head; - xfer = 0; - } - prev = head; - xfer = xfer + 1; - head = head + init->pitch; - } - } - - nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); - nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); - nv_wr32(priv, falcon + 0x01c4, star + 4); -} - -int -nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) -{ - struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass; - struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; - int i; - - if (priv->firmware) { - /* load fuc microcode */ - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); - nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, - &priv->fuc409d); - nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, - &priv->fuc41ad); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); - - /* start both of them running */ - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x41a10c, 0x00000000); - nv_wr32(priv, 0x40910c, 0x00000000); - nv_wr32(priv, 0x41a100, 0x00000002); - nv_wr32(priv, 0x409100, 0x00000002); - if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) - nv_warn(priv, "0x409800 wait failed\n"); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x7fffffff); - nv_wr32(priv, 0x409504, 0x00000021); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000010); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x10 timeout\n"); - return -EBUSY; - } - priv->size = nv_rd32(priv, 0x409800); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000016); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x16 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000025); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x25 timeout\n"); - return -EBUSY; - } - - if (nv_device(priv)->chipset >= 0xe0) { - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000030); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x30 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409810, 0xb00095c8); - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000031); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x31 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409810, 0x00080420); - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000032); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x32 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409614, 0x00000070); - nv_wr32(priv, 0x409614, 0x00000770); - nv_wr32(priv, 0x40802c, 0x00000001); - } - - if (priv->data == NULL) { - int ret = nvc0_grctx_generate(priv); - if (ret) { - nv_error(priv, "failed to construct context\n"); - return ret; - } - } - - return 0; - } else - if (!oclass->fecs.ucode) { - return -ENOSYS; - } - - /* load HUB microcode */ - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); - nv_wr32(priv, 0x4091c0, 0x01000000); - for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) - nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); - - nv_wr32(priv, 0x409180, 0x01000000); - for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { - if ((i & 0x3f) == 0) - nv_wr32(priv, 0x409188, i >> 6); - nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); - } - - /* load GPC microcode */ - nv_wr32(priv, 0x41a1c0, 0x01000000); - for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) - nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); - - nv_wr32(priv, 0x41a180, 0x01000000); - for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { - if ((i & 0x3f) == 0) - nv_wr32(priv, 0x41a188, i >> 6); - nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); - } - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); - - /* load register lists */ - nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); - nvc0_graph_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); - nvc0_graph_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); - nvc0_graph_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); - - /* start HUB ucode running, it'll init the GPCs */ - nv_wr32(priv, 0x40910c, 0x00000000); - nv_wr32(priv, 0x409100, 0x00000002); - if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { - nv_error(priv, "HUB_INIT timed out\n"); - nvc0_graph_ctxctl_debug(priv); - return -EBUSY; - } - - priv->size = nv_rd32(priv, 0x409804); - if (priv->data == NULL) { - int ret = nvc0_grctx_generate(priv); - if (ret) { - nv_error(priv, "failed to construct context\n"); - return ret; - } - } - - return 0; -} - -int -nvc0_graph_init(struct nouveau_object *object) -{ - struct nvc0_graph_oclass *oclass = (void *)object->oclass; - struct nvc0_graph_priv *priv = (void *)object; - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); - u32 data[TPC_MAX / 8] = {}; - u8 tpcnr[GPC_MAX]; - int gpc, tpc, rop; - int ret, i; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); - - nvc0_graph_mmio(priv, oclass->mmio); - - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - data[i / 8] |= tpc << ((i % 8) * 4); - } - - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); - } - - if (nv_device(priv)->chipset != 0xd7) - nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); - else - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - - nv_wr32(priv, 0x400500, 0x00010001); - - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - - nv_wr32(priv, 0x409c24, 0x000f0000); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x40601c, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); - } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); - } - - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); - } - - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); - - nv_wr32(priv, 0x400054, 0x34ce3464); - - nvc0_graph_zbc_init(priv); - - return nvc0_graph_init_ctxctl(priv); -} - -static void -nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc) -{ - kfree(fuc->data); - fuc->data = NULL; -} - -int -nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname, - struct nvc0_graph_fuc *fuc) -{ - struct nouveau_device *device = nv_device(priv); - const struct firmware *fw; - char f[32]; - int ret; - - snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); - ret = request_firmware(&fw, f, nv_device_base(device)); - if (ret) { - snprintf(f, sizeof(f), "nouveau/%s", fwname); - ret = request_firmware(&fw, f, nv_device_base(device)); - if (ret) { - nv_error(priv, "failed to load %s\n", fwname); - return ret; - } - } - - fuc->size = fw->size; - fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); - release_firmware(fw); - return (fuc->data != NULL) ? 0 : -ENOMEM; -} - -void -nvc0_graph_dtor(struct nouveau_object *object) -{ - struct nvc0_graph_priv *priv = (void *)object; - - kfree(priv->data); - - nvc0_graph_dtor_fw(&priv->fuc409c); - nvc0_graph_dtor_fw(&priv->fuc409d); - nvc0_graph_dtor_fw(&priv->fuc41ac); - nvc0_graph_dtor_fw(&priv->fuc41ad); - - nouveau_gpuobj_ref(NULL, &priv->unk4188b8); - nouveau_gpuobj_ref(NULL, &priv->unk4188b4); - - nouveau_graph_destroy(&priv->base); -} - -int -nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *bclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_graph_oclass *oclass = (void *)bclass; - struct nouveau_device *device = nv_device(parent); - struct nvc0_graph_priv *priv; - bool use_ext_fw, enable; - int ret, i, j; - - use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW", - oclass->fecs.ucode == NULL); - enable = use_ext_fw || oclass->fecs.ucode != NULL; - - ret = nouveau_graph_create(parent, engine, bclass, enable, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x08001000; - nv_subdev(priv)->intr = nvc0_graph_intr; - - priv->base.units = nvc0_graph_units; - - if (use_ext_fw) { - nv_info(priv, "using external firmware\n"); - if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) || - nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) || - nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || - nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) - return -ENODEV; - priv->firmware = true; - } - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b4); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b8); - if (ret) - return ret; - - for (i = 0; i < 0x1000; i += 4) { - nv_wo32(priv->unk4188b4, i, 0x00000010); - nv_wo32(priv->unk4188b8, i, 0x00000010); - } - - priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; - priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; - for (i = 0; i < priv->gpc_nr; i++) { - priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); - priv->tpc_total += priv->tpc_nr[i]; - priv->ppc_nr[i] = oclass->ppc_nr; - for (j = 0; j < priv->ppc_nr[i]; j++) { - u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); - priv->ppc_tpc_nr[i][j] = hweight8(mask); - } - } - - /*XXX: these need figuring out... though it might not even matter */ - switch (nv_device(priv)->chipset) { - case 0xc0: - if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ - priv->magic_not_rop_nr = 0x07; - } else - if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ - priv->magic_not_rop_nr = 0x05; - } else - if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ - priv->magic_not_rop_nr = 0x06; - } - break; - case 0xc3: /* 450, 4/0/0/0, 2 */ - priv->magic_not_rop_nr = 0x03; - break; - case 0xc4: /* 460, 3/4/0/0, 4 */ - priv->magic_not_rop_nr = 0x01; - break; - case 0xc1: /* 2/0/0/0, 1 */ - priv->magic_not_rop_nr = 0x01; - break; - case 0xc8: /* 4/4/3/4, 5 */ - priv->magic_not_rop_nr = 0x06; - break; - case 0xce: /* 4/4/0/0, 4 */ - priv->magic_not_rop_nr = 0x03; - break; - case 0xcf: /* 4/0/0/0, 3 */ - priv->magic_not_rop_nr = 0x03; - break; - case 0xd7: - case 0xd9: /* 1/0/0/0, 1 */ - priv->magic_not_rop_nr = 0x01; - break; - } - - nv_engine(priv)->cclass = *oclass->cclass; - nv_engine(priv)->sclass = oclass->sclass; - return 0; -} - -#include "fuc/hubnvc0.fuc3.h" - -struct nvc0_graph_ucode -nvc0_graph_fecs_ucode = { - .code.data = nvc0_grhub_code, - .code.size = sizeof(nvc0_grhub_code), - .data.data = nvc0_grhub_data, - .data.size = sizeof(nvc0_grhub_data), -}; - -#include "fuc/gpcnvc0.fuc3.h" - -struct nvc0_graph_ucode -nvc0_graph_gpccs_ucode = { - .code.data = nvc0_grgpc_code, - .code.size = sizeof(nvc0_grgpc_code), - .data.data = nvc0_grgpc_data, - .data.size = sizeof(nvc0_grgpc_data), -}; - -struct nouveau_oclass * -nvc0_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nvc0_grctx_oclass, - .sclass = nvc0_graph_sclass, - .mmio = nvc0_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h deleted file mode 100644 index 86b7735242e1..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifndef __NVC0_GRAPH_H__ -#define __NVC0_GRAPH_H__ - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "fuc/os.h" - -#define GPC_MAX 32 -#define TPC_MAX (GPC_MAX * 8) - -#define ROP_BCAST(r) (0x408800 + (r)) -#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) -#define GPC_BCAST(r) (0x418000 + (r)) -#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r)) -#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r)) -#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) - -struct nvc0_graph_data { - u32 size; - u32 align; - u32 access; -}; - -struct nvc0_graph_mmio { - u32 addr; - u32 data; - u32 shift; - int buffer; -}; - -struct nvc0_graph_fuc { - u32 *data; - u32 size; -}; - -struct nvc0_graph_zbc_color { - u32 format; - u32 ds[4]; - u32 l2[4]; -}; - -struct nvc0_graph_zbc_depth { - u32 format; - u32 ds; - u32 l2; -}; - -struct nvc0_graph_priv { - struct nouveau_graph base; - - struct nvc0_graph_fuc fuc409c; - struct nvc0_graph_fuc fuc409d; - struct nvc0_graph_fuc fuc41ac; - struct nvc0_graph_fuc fuc41ad; - bool firmware; - - struct nvc0_graph_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT]; - struct nvc0_graph_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; - - u8 rop_nr; - u8 gpc_nr; - u8 tpc_nr[GPC_MAX]; - u8 tpc_total; - u8 ppc_nr[GPC_MAX]; - u8 ppc_tpc_nr[GPC_MAX][4]; - - struct nouveau_gpuobj *unk4188b4; - struct nouveau_gpuobj *unk4188b8; - - struct nvc0_graph_data mmio_data[4]; - struct nvc0_graph_mmio mmio_list[4096/8]; - u32 size; - u32 *data; - - u8 magic_not_rop_nr; -}; - -struct nvc0_graph_chan { - struct nouveau_graph_chan base; - - struct nouveau_gpuobj *mmio; - struct nouveau_vma mmio_vma; - int mmio_nr; - struct { - struct nouveau_gpuobj *mem; - struct nouveau_vma vma; - } data[4]; -}; - -int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_graph_context_dtor(struct nouveau_object *); - -void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *); - -u64 nvc0_graph_units(struct nouveau_graph *); -int nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *data, u32 size, - struct nouveau_object **); -void nvc0_graph_dtor(struct nouveau_object *); -int nvc0_graph_init(struct nouveau_object *); -void nvc0_graph_zbc_init(struct nvc0_graph_priv *); - -int nve4_graph_fini(struct nouveau_object *, bool); -int nve4_graph_init(struct nouveau_object *); - -int nvf0_graph_fini(struct nouveau_object *, bool); - -extern struct nouveau_ofuncs nvc0_fermi_ofuncs; - -extern struct nouveau_oclass nvc0_graph_sclass[]; -extern struct nouveau_omthds nvc0_graph_9097_omthds[]; -extern struct nouveau_omthds nvc0_graph_90c0_omthds[]; -extern struct nouveau_oclass nvc8_graph_sclass[]; -extern struct nouveau_oclass nvf0_graph_sclass[]; - -struct nvc0_graph_init { - u32 addr; - u8 count; - u8 pitch; - u32 data; -}; - -struct nvc0_graph_pack { - const struct nvc0_graph_init *init; - u32 type; -}; - -#define pack_for_each_init(init, pack, head) \ - for (pack = head; pack && pack->init; pack++) \ - for (init = pack->init; init && init->count; init++) - -struct nvc0_graph_ucode { - struct nvc0_graph_fuc code; - struct nvc0_graph_fuc data; -}; - -extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode; -extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode; - -extern struct nvc0_graph_ucode nvf0_graph_fecs_ucode; -extern struct nvc0_graph_ucode nvf0_graph_gpccs_ucode; - -struct nvc0_graph_oclass { - struct nouveau_oclass base; - struct nouveau_oclass **cclass; - struct nouveau_oclass *sclass; - const struct nvc0_graph_pack *mmio; - struct { - struct nvc0_graph_ucode *ucode; - } fecs; - struct { - struct nvc0_graph_ucode *ucode; - } gpccs; - int ppc_nr; -}; - -void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); -void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); -void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); -int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *); - -/* register init value lists */ - -extern const struct nvc0_graph_init nvc0_graph_init_main_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_fe_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_pri_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_pd_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_scc_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_prop_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_setup_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_crstr_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_setup_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_pe_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_be_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_fe_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_pe_1[]; - -extern const struct nvc0_graph_init nvc4_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvc4_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvc4_graph_init_sm_0[]; - -extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[]; -extern const struct nvc0_graph_init nvc1_graph_init_setup_1[]; - -extern const struct nvc0_graph_init nvd9_graph_init_pd_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_prop_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvd9_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_sm_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_fe_1[]; - -extern const struct nvc0_graph_init nvd7_graph_init_pes_0[]; -extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[]; -extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[]; - -extern const struct nvc0_graph_init nve4_graph_init_main_0[]; -extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[]; -extern const struct nvc0_graph_init nve4_graph_init_pe_0[]; -extern const struct nvc0_graph_init nve4_graph_init_be_0[]; -extern const struct nvc0_graph_pack nve4_graph_pack_mmio[]; - -extern const struct nvc0_graph_init nvf0_graph_init_fe_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_sked_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvf0_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_sm_0[]; - -extern const struct nvc0_graph_init nv108_graph_init_gpc_unk_0[]; - - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c deleted file mode 100644 index 93d58e5b82c2..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nvc1_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nvc1_graph_init_gpc_unk_0[] = { - { 0x418604, 1, 0x04, 0x00000000 }, - { 0x418680, 1, 0x04, 0x00000000 }, - { 0x418714, 1, 0x04, 0x00000000 }, - { 0x418384, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc1_graph_init_setup_1[] = { - { 0x4188c8, 2, 0x04, 0x00000000 }, - { 0x4188d0, 1, 0x04, 0x00010000 }, - { 0x4188d4, 1, 0x04, 0x00000001 }, - {} -}; - -static const struct nvc0_graph_init -nvc1_graph_init_gpc_unk_1[] = { - { 0x418d00, 1, 0x04, 0x00000000 }, - { 0x418f08, 1, 0x04, 0x00000000 }, - { 0x418e00, 1, 0x04, 0x00000003 }, - { 0x418e08, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc1_graph_init_pe_0[] = { - { 0x41980c, 1, 0x04, 0x00000010 }, - { 0x419810, 1, 0x04, 0x00000000 }, - { 0x419814, 1, 0x04, 0x00000004 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x41984c, 1, 0x04, 0x00005bc5 }, - { 0x419850, 4, 0x04, 0x00000000 }, - { 0x419880, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_pack -nvc1_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc4_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc1_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc4_graph_init_tex_0 }, - { nvc1_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc4_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -struct nouveau_oclass * -nvc1_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xc1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nvc1_grctx_oclass, - .sclass = nvc1_graph_sclass, - .mmio = nvc1_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c deleted file mode 100644 index e82e70c53132..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nvc4_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405900, 1, 0x04, 0x00002834 }, - { 0x405908, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvc4_graph_init_tex_0[] = { - { 0x419ab0, 1, 0x04, 0x00000000 }, - { 0x419ac8, 1, 0x04, 0x00000000 }, - { 0x419ab8, 1, 0x04, 0x000000e7 }, - { 0x419abc, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvc4_graph_init_pe_0[] = { - { 0x41980c, 3, 0x04, 0x00000000 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x41984c, 1, 0x04, 0x00005bc5 }, - { 0x419850, 4, 0x04, 0x00000000 }, - { 0x419880, 1, 0x04, 0x00000002 }, - {} -}; - -const struct nvc0_graph_init -nvc4_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000000 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x00001100 }, - { 0x419eac, 1, 0x04, 0x11100702 }, - { 0x419eb0, 1, 0x04, 0x00000003 }, - { 0x419eb4, 4, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x0e063818 }, - { 0x419ecc, 1, 0x04, 0x0e060e06 }, - { 0x419ed0, 1, 0x04, 0x00003818 }, - { 0x419ed4, 1, 0x04, 0x011104f1 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419f2c, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvc4_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc4_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc0_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc0_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc4_graph_init_tex_0 }, - { nvc4_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc4_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -struct nouveau_oclass * -nvc4_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xc3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nvc4_grctx_oclass, - .sclass = nvc0_graph_sclass, - .mmio = nvc4_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c deleted file mode 100644 index 692e1eda0eb4..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -struct nouveau_oclass -nvc8_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvc8_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000000 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x00001100 }, - { 0x419eac, 1, 0x04, 0x11100f02 }, - { 0x419eb0, 1, 0x04, 0x00000003 }, - { 0x419eb4, 4, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x06060618 }, - { 0x419ed0, 1, 0x04, 0x0eff0e38 }, - { 0x419ed4, 1, 0x04, 0x011104f1 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419f2c, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvc8_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc0_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc0_graph_init_tex_0 }, - { nvc0_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc8_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - { nvc0_graph_init_pe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -struct nouveau_oclass * -nvc8_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xc8), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nvc8_grctx_oclass, - .sclass = nvc8_graph_sclass, - .mmio = nvc8_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c deleted file mode 100644 index 6f9f5ede5588..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -static const struct nvc0_graph_init -nvd7_graph_init_pe_0[] = { - { 0x41980c, 1, 0x04, 0x00000010 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x41984c, 1, 0x04, 0x00005bc8 }, - { 0x419850, 3, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd7_graph_init_pes_0[] = { - { 0x41be04, 1, 0x04, 0x00000000 }, - { 0x41be08, 1, 0x04, 0x00000004 }, - { 0x41be0c, 1, 0x04, 0x00000000 }, - { 0x41be10, 1, 0x04, 0x003b8bc7 }, - { 0x41be14, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd7_graph_init_wwdx_0[] = { - { 0x41bfd4, 1, 0x04, 0x00800000 }, - { 0x41bfdc, 1, 0x04, 0x00000000 }, - { 0x41bff8, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd7_graph_init_cbm_0[] = { - { 0x41becc, 1, 0x04, 0x00000000 }, - { 0x41bee8, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvd7_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvd9_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvd9_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvd9_graph_init_tex_0 }, - { nvd7_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nvd9_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nvc0_graph_init_be_0 }, - { nvd9_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -#include "fuc/hubnvd7.fuc3.h" - -struct nvc0_graph_ucode -nvd7_graph_fecs_ucode = { - .code.data = nvd7_grhub_code, - .code.size = sizeof(nvd7_grhub_code), - .data.data = nvd7_grhub_data, - .data.size = sizeof(nvd7_grhub_data), -}; - -#include "fuc/gpcnvd7.fuc3.h" - -struct nvc0_graph_ucode -nvd7_graph_gpccs_ucode = { - .code.data = nvd7_grgpc_code, - .code.size = sizeof(nvd7_grgpc_code), - .data.data = nvd7_grgpc_data, - .data.size = sizeof(nvd7_grgpc_data), -}; - -struct nouveau_oclass * -nvd7_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xd7), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nvd7_grctx_oclass, - .sclass = nvc8_graph_sclass, - .mmio = nvd7_graph_pack_mmio, - .fecs.ucode = &nvd7_graph_fecs_ucode, - .gpccs.ucode = &nvd7_graph_gpccs_ucode, - .ppc_nr = 1, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c deleted file mode 100644 index 00fdf202fb92..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nvd9_graph_init_pd_0[] = { - { 0x406024, 1, 0x04, 0x00000000 }, - { 0x4064f0, 3, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405900, 1, 0x04, 0x00002834 }, - { 0x405908, 1, 0x04, 0x00000000 }, - { 0x405928, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_prop_0[] = { - { 0x418408, 1, 0x04, 0x00000000 }, - { 0x4184a0, 3, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_gpm_0[] = { - { 0x418c04, 1, 0x04, 0x00000000 }, - { 0x418c64, 2, 0x04, 0x00000000 }, - { 0x418c88, 1, 0x04, 0x00000000 }, - { 0x418cb4, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_gpc_unk_1[] = { - { 0x418d00, 1, 0x04, 0x00000000 }, - { 0x418d28, 2, 0x04, 0x00000000 }, - { 0x418f00, 1, 0x04, 0x00000000 }, - { 0x418f08, 1, 0x04, 0x00000000 }, - { 0x418f20, 2, 0x04, 0x00000000 }, - { 0x418e00, 1, 0x04, 0x00000003 }, - { 0x418e08, 1, 0x04, 0x00000000 }, - { 0x418e1c, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_tex_0[] = { - { 0x419ab0, 1, 0x04, 0x00000000 }, - { 0x419ac8, 1, 0x04, 0x00000000 }, - { 0x419ab8, 1, 0x04, 0x000000e7 }, - { 0x419abc, 2, 0x04, 0x00000000 }, - { 0x419ab4, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_graph_init_pe_0[] = { - { 0x41980c, 1, 0x04, 0x00000010 }, - { 0x419810, 1, 0x04, 0x00000000 }, - { 0x419814, 1, 0x04, 0x00000004 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x41984c, 1, 0x04, 0x0000a918 }, - { 0x419850, 4, 0x04, 0x00000000 }, - { 0x419880, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_graph_init_wwdx_0[] = { - { 0x419bd4, 1, 0x04, 0x00800000 }, - { 0x419bdc, 1, 0x04, 0x00000000 }, - { 0x419bf8, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvd9_graph_init_tpccs_1[] = { - { 0x419d2c, 1, 0x04, 0x00000000 }, - { 0x419d48, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000000 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x02001100 }, - { 0x419eac, 1, 0x04, 0x11100702 }, - { 0x419eb0, 1, 0x04, 0x00000003 }, - { 0x419eb4, 4, 0x04, 0x00000000 }, - { 0x419ec8, 1, 0x04, 0x0e063818 }, - { 0x419ecc, 1, 0x04, 0x0e060e06 }, - { 0x419ed0, 1, 0x04, 0x00003818 }, - { 0x419ed4, 1, 0x04, 0x011104f1 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419f2c, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvd9_graph_init_fe_1[] = { - { 0x40402c, 1, 0x04, 0x00000000 }, - { 0x4040f0, 1, 0x04, 0x00000000 }, - { 0x404174, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvd9_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvd9_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvd9_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvd9_graph_init_tex_0 }, - { nvd9_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvd9_graph_init_wwdx_0 }, - { nvd9_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvd9_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvd9_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -struct nouveau_oclass * -nvd9_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xd9), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nvd9_grctx_oclass, - .sclass = nvc8_graph_sclass, - .mmio = nvd9_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c deleted file mode 100644 index 8e6b62c4706c..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nve4_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa040, &nouveau_object_ofuncs }, - { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nve4_graph_init_main_0[] = { - { 0x400080, 1, 0x04, 0x003083c2 }, - { 0x400088, 1, 0x04, 0x0001ffe7 }, - { 0x40008c, 1, 0x04, 0x00000000 }, - { 0x400090, 1, 0x04, 0x00000030 }, - { 0x40013c, 1, 0x04, 0x003901f7 }, - { 0x400140, 1, 0x04, 0x00000100 }, - { 0x400144, 1, 0x04, 0x00000000 }, - { 0x400148, 1, 0x04, 0x00000110 }, - { 0x400138, 1, 0x04, 0x00000000 }, - { 0x400130, 2, 0x04, 0x00000000 }, - { 0x400124, 1, 0x04, 0x00000002 }, - {} -}; - -static const struct nvc0_graph_init -nve4_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405900, 1, 0x04, 0x0000ff34 }, - { 0x405908, 1, 0x04, 0x00000000 }, - { 0x405928, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_graph_init_sked_0[] = { - { 0x407010, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_graph_init_cwd_0[] = { - { 0x405b50, 1, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_graph_init_gpc_unk_1[] = { - { 0x418d00, 1, 0x04, 0x00000000 }, - { 0x418d28, 2, 0x04, 0x00000000 }, - { 0x418f00, 1, 0x04, 0x00000000 }, - { 0x418f08, 1, 0x04, 0x00000000 }, - { 0x418f20, 2, 0x04, 0x00000000 }, - { 0x418e00, 1, 0x04, 0x00000060 }, - { 0x418e08, 1, 0x04, 0x00000000 }, - { 0x418e1c, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nve4_graph_init_tpccs_0[] = { - { 0x419d0c, 1, 0x04, 0x00000000 }, - { 0x419d10, 1, 0x04, 0x00000014 }, - {} -}; - -const struct nvc0_graph_init -nve4_graph_init_pe_0[] = { - { 0x41980c, 1, 0x04, 0x00000010 }, - { 0x419844, 1, 0x04, 0x00000000 }, - { 0x419850, 1, 0x04, 0x00000004 }, - { 0x419854, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nve4_graph_init_l1c_0[] = { - { 0x419c98, 1, 0x04, 0x00000000 }, - { 0x419ca8, 1, 0x04, 0x00000000 }, - { 0x419cb0, 1, 0x04, 0x01000000 }, - { 0x419cb4, 1, 0x04, 0x00000000 }, - { 0x419cb8, 1, 0x04, 0x00b08bea }, - { 0x419c84, 1, 0x04, 0x00010384 }, - { 0x419cbc, 1, 0x04, 0x28137646 }, - { 0x419cc0, 2, 0x04, 0x00000000 }, - { 0x419c80, 1, 0x04, 0x00020232 }, - {} -}; - -static const struct nvc0_graph_init -nve4_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000000 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ee4, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x00000000 }, - { 0x419eb4, 4, 0x04, 0x00000000 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419f74, 1, 0x04, 0x00000555 }, - {} -}; - -const struct nvc0_graph_init -nve4_graph_init_be_0[] = { - { 0x40880c, 1, 0x04, 0x00000000 }, - { 0x408850, 1, 0x04, 0x00000004 }, - { 0x408910, 9, 0x04, 0x00000000 }, - { 0x408950, 1, 0x04, 0x00000000 }, - { 0x408954, 1, 0x04, 0x0000ffff }, - { 0x408958, 1, 0x04, 0x00000034 }, - { 0x408984, 1, 0x04, 0x00000000 }, - { 0x408988, 1, 0x04, 0x08040201 }, - { 0x40898c, 1, 0x04, 0x80402010 }, - {} -}; - -const struct nvc0_graph_pack -nve4_graph_pack_mmio[] = { - { nve4_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nve4_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nve4_graph_init_sked_0 }, - { nve4_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nve4_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nvd9_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { nve4_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nve4_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -int -nve4_graph_init(struct nouveau_object *object) -{ - struct nvc0_graph_oclass *oclass = (void *)object->oclass; - struct nvc0_graph_priv *priv = (void *)object; - struct nouveau_pmu *pmu = nouveau_pmu(priv); - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); - u32 data[TPC_MAX / 8] = {}; - u8 tpcnr[GPC_MAX]; - int gpc, tpc, rop; - int ret, i; - - if (pmu) - pmu->pgob(pmu, false); - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); - - nvc0_graph_mmio(priv, oclass->mmio); - - nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); - - memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - data[i / 8] |= tpc << ((i % 8) * 4); - } - - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); - } - - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - - nv_wr32(priv, 0x400500, 0x00010001); - - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - - nv_wr32(priv, 0x409ffc, 0x00000000); - nv_wr32(priv, 0x409c14, 0x00003e3e); - nv_wr32(priv, 0x409c24, 0x000f0001); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); - } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); - } - - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); - } - - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); - - nv_wr32(priv, 0x400054, 0x34ce3464); - - nvc0_graph_zbc_init(priv); - - return nvc0_graph_init_ctxctl(priv); -} - -#include "fuc/hubnve0.fuc3.h" - -static struct nvc0_graph_ucode -nve4_graph_fecs_ucode = { - .code.data = nve0_grhub_code, - .code.size = sizeof(nve0_grhub_code), - .data.data = nve0_grhub_data, - .data.size = sizeof(nve0_grhub_data), -}; - -#include "fuc/gpcnve0.fuc3.h" - -static struct nvc0_graph_ucode -nve4_graph_gpccs_ucode = { - .code.data = nve0_grgpc_code, - .code.size = sizeof(nve0_grgpc_code), - .data.data = nve0_grgpc_data, - .data.size = sizeof(nve0_grgpc_data), -}; - -struct nouveau_oclass * -nve4_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xe4), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = _nouveau_graph_fini, - }, - .cclass = &nve4_grctx_oclass, - .sclass = nve4_graph_sclass, - .mmio = nve4_graph_pack_mmio, - .fecs.ucode = &nve4_graph_fecs_ucode, - .gpccs.ucode = &nve4_graph_gpccs_ucode, - .ppc_nr = 1, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c deleted file mode 100644 index 73f77fa04a62..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "ctxnvc0.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -struct nouveau_oclass -nvf0_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa140, &nouveau_object_ofuncs }, - { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, - {} -}; - -/******************************************************************************* - * PGRAPH register lists - ******************************************************************************/ - -const struct nvc0_graph_init -nvf0_graph_init_fe_0[] = { - { 0x40415c, 1, 0x04, 0x00000000 }, - { 0x404170, 1, 0x04, 0x00000000 }, - { 0x4041b4, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvf0_graph_init_ds_0[] = { - { 0x405844, 1, 0x04, 0x00ffffff }, - { 0x405850, 1, 0x04, 0x00000000 }, - { 0x405900, 1, 0x04, 0x0000ff00 }, - { 0x405908, 1, 0x04, 0x00000000 }, - { 0x405928, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvf0_graph_init_sked_0[] = { - { 0x407010, 1, 0x04, 0x00000000 }, - { 0x407040, 1, 0x04, 0x80440424 }, - { 0x407048, 1, 0x04, 0x0000000a }, - {} -}; - -const struct nvc0_graph_init -nvf0_graph_init_cwd_0[] = { - { 0x405b44, 1, 0x04, 0x00000000 }, - { 0x405b50, 1, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvf0_graph_init_gpc_unk_1[] = { - { 0x418d00, 1, 0x04, 0x00000000 }, - { 0x418d28, 2, 0x04, 0x00000000 }, - { 0x418f00, 1, 0x04, 0x00000400 }, - { 0x418f08, 1, 0x04, 0x00000000 }, - { 0x418f20, 2, 0x04, 0x00000000 }, - { 0x418e00, 1, 0x04, 0x00000000 }, - { 0x418e08, 1, 0x04, 0x00000000 }, - { 0x418e1c, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvf0_graph_init_tex_0[] = { - { 0x419ab0, 1, 0x04, 0x00000000 }, - { 0x419ac8, 1, 0x04, 0x00000000 }, - { 0x419ab8, 1, 0x04, 0x000000e7 }, - { 0x419aec, 1, 0x04, 0x00000000 }, - { 0x419abc, 2, 0x04, 0x00000000 }, - { 0x419ab4, 1, 0x04, 0x00000000 }, - { 0x419aa8, 2, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_init -nvf0_graph_init_l1c_0[] = { - { 0x419c98, 1, 0x04, 0x00000000 }, - { 0x419ca8, 1, 0x04, 0x00000000 }, - { 0x419cb0, 1, 0x04, 0x01000000 }, - { 0x419cb4, 1, 0x04, 0x00000000 }, - { 0x419cb8, 1, 0x04, 0x00b08bea }, - { 0x419c84, 1, 0x04, 0x00010384 }, - { 0x419cbc, 1, 0x04, 0x281b3646 }, - { 0x419cc0, 2, 0x04, 0x00000000 }, - { 0x419c80, 1, 0x04, 0x00020230 }, - { 0x419ccc, 2, 0x04, 0x00000000 }, - {} -}; - -const struct nvc0_graph_init -nvf0_graph_init_sm_0[] = { - { 0x419e00, 1, 0x04, 0x00000080 }, - { 0x419ea0, 1, 0x04, 0x00000000 }, - { 0x419ee4, 1, 0x04, 0x00000000 }, - { 0x419ea4, 1, 0x04, 0x00000100 }, - { 0x419ea8, 1, 0x04, 0x00000000 }, - { 0x419eb4, 1, 0x04, 0x00000000 }, - { 0x419ebc, 2, 0x04, 0x00000000 }, - { 0x419edc, 1, 0x04, 0x00000000 }, - { 0x419f00, 1, 0x04, 0x00000000 }, - { 0x419ed0, 1, 0x04, 0x00003234 }, - { 0x419f74, 1, 0x04, 0x00015555 }, - { 0x419f80, 4, 0x04, 0x00000000 }, - {} -}; - -static const struct nvc0_graph_pack -nvf0_graph_pack_mmio[] = { - { nve4_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvf0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvf0_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvf0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nvf0_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { nvf0_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nvf0_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - {} -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -int -nvf0_graph_fini(struct nouveau_object *object, bool suspend) -{ - struct nvc0_graph_priv *priv = (void *)object; - static const struct { - u32 addr; - u32 data; - } magic[] = { - { 0x020520, 0xfffffffc }, - { 0x020524, 0xfffffffe }, - { 0x020524, 0xfffffffc }, - { 0x020524, 0xfffffff8 }, - { 0x020524, 0xffffffe0 }, - { 0x020530, 0xfffffffe }, - { 0x02052c, 0xfffffffa }, - { 0x02052c, 0xfffffff0 }, - { 0x02052c, 0xffffffc0 }, - { 0x02052c, 0xffffff00 }, - { 0x02052c, 0xfffffc00 }, - { 0x02052c, 0xfffcfc00 }, - { 0x02052c, 0xfff0fc00 }, - { 0x02052c, 0xff80fc00 }, - { 0x020528, 0xfffffffe }, - { 0x020528, 0xfffffffc }, - }; - int i; - - nv_mask(priv, 0x000200, 0x08001000, 0x00000000); - nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); - for (i = 0; i < ARRAY_SIZE(magic); i++) { - nv_wr32(priv, magic[i].addr, magic[i].data); - nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); - } - - return nouveau_graph_fini(&priv->base, suspend); -} - -#include "fuc/hubnvf0.fuc3.h" - -struct nvc0_graph_ucode -nvf0_graph_fecs_ucode = { - .code.data = nvf0_grhub_code, - .code.size = sizeof(nvf0_grhub_code), - .data.data = nvf0_grhub_data, - .data.size = sizeof(nvf0_grhub_data), -}; - -#include "fuc/gpcnvf0.fuc3.h" - -struct nvc0_graph_ucode -nvf0_graph_gpccs_ucode = { - .code.data = nvf0_grgpc_code, - .code.size = sizeof(nvf0_grgpc_code), - .data.data = nvf0_grgpc_data, - .data.size = sizeof(nvf0_grgpc_data), -}; - -struct nouveau_oclass * -nvf0_graph_oclass = &(struct nvc0_graph_oclass) { - .base.handle = NV_ENGINE(GR, 0xf0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = nvf0_graph_fini, - }, - .cclass = &nvf0_grctx_oclass, - .sclass = nvf0_graph_sclass, - .mmio = nvf0_graph_pack_mmio, - .fecs.ucode = &nvf0_graph_fecs_ucode, - .gpccs.ucode = &nvf0_graph_gpccs_ucode, - .ppc_nr = 2, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h deleted file mode 100644 index fde8e24415e4..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h +++ /dev/null @@ -1,274 +0,0 @@ -#ifndef __NOUVEAU_GRAPH_REGS_H__ -#define __NOUVEAU_GRAPH_REGS_H__ - -#define NV04_PGRAPH_DEBUG_0 0x00400080 -#define NV04_PGRAPH_DEBUG_1 0x00400084 -#define NV04_PGRAPH_DEBUG_2 0x00400088 -#define NV04_PGRAPH_DEBUG_3 0x0040008c -#define NV10_PGRAPH_DEBUG_4 0x00400090 -#define NV03_PGRAPH_INTR 0x00400100 -#define NV03_PGRAPH_NSTATUS 0x00400104 -# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) -# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) -# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) -# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) -# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) -# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) -# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) -# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) -#define NV03_PGRAPH_NSOURCE 0x00400108 -# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0) -# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1) -# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2) -# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3) -# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4) -# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5) -# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6) -# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7) -# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8) -# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9) -# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) -# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) -# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) -# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) -# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) -# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) -# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) -# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) -# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) -#define NV03_PGRAPH_INTR_EN 0x00400140 -#define NV40_PGRAPH_INTR_EN 0x0040013C -# define NV_PGRAPH_INTR_NOTIFY (1<<0) -# define NV_PGRAPH_INTR_MISSING_HW (1<<4) -# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) -# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) -# define NV_PGRAPH_INTR_ERROR (1<<20) -#define NV10_PGRAPH_CTX_CONTROL 0x00400144 -#define NV10_PGRAPH_CTX_USER 0x00400148 -#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i)) -#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 -#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \ - + 0x4*(i) + 0x20*(j)) -#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 -#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 -#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C -#define NV04_PGRAPH_CTX_CONTROL 0x00400170 -#define NV04_PGRAPH_CTX_USER 0x00400174 -#define NV04_PGRAPH_CTX_CACHE1 0x00400180 -#define NV03_PGRAPH_CTX_CONTROL 0x00400190 -#define NV03_PGRAPH_CTX_USER 0x00400194 -#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 -#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 -#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 -#define NV40_PGRAPH_CTXCTL_0304 0x00400304 -#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff -#define NV40_PGRAPH_CTXCTL_0310 0x00400310 -#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 -#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 -#define NV40_PGRAPH_CTXCTL_030C 0x0040030c -#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 -#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 -#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c -#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 -#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF -#define NV40_PGRAPH_CTXCTL_NEXT 0x00400330 -#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff -#define NV50_PGRAPH_CTXCTL_CUR 0x0040032c -#define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000 -#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff -#define NV50_PGRAPH_CTXCTL_NEXT 0x00400330 -#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff -#define NV03_PGRAPH_ABS_X_RAM 0x00400400 -#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 -#define NV03_PGRAPH_X_MISC 0x00400500 -#define NV03_PGRAPH_Y_MISC 0x00400504 -#define NV04_PGRAPH_VALID1 0x00400508 -#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C -#define NV04_PGRAPH_MISC24_0 0x00400510 -#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 -#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 -#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C -#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 -#define NV03_PGRAPH_CLIPX_0 0x00400524 -#define NV03_PGRAPH_CLIPX_1 0x00400528 -#define NV03_PGRAPH_CLIPY_0 0x0040052C -#define NV03_PGRAPH_CLIPY_1 0x00400530 -#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 -#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 -#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C -#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 -#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 -#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 -#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 -#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 -#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 -#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C -#define NV04_PGRAPH_MISC24_1 0x00400570 -#define NV04_PGRAPH_MISC24_2 0x00400574 -#define NV04_PGRAPH_VALID2 0x00400578 -#define NV04_PGRAPH_PASSTHRU_0 0x0040057C -#define NV04_PGRAPH_PASSTHRU_1 0x00400580 -#define NV04_PGRAPH_PASSTHRU_2 0x00400584 -#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 -#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C -#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 -#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 -#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 -#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C -#define NV04_PGRAPH_FORMAT_0 0x004005A8 -#define NV04_PGRAPH_FORMAT_1 0x004005AC -#define NV04_PGRAPH_FILTER_0 0x004005B0 -#define NV04_PGRAPH_FILTER_1 0x004005B4 -#define NV03_PGRAPH_MONO_COLOR0 0x00400600 -#define NV04_PGRAPH_ROP3 0x00400604 -#define NV04_PGRAPH_BETA_AND 0x00400608 -#define NV04_PGRAPH_BETA_PREMULT 0x0040060C -#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 -#define NV04_PGRAPH_FORMATS 0x00400618 -#define NV10_PGRAPH_DEBUG_2 0x00400620 -#define NV04_PGRAPH_BOFFSET0 0x00400640 -#define NV04_PGRAPH_BOFFSET1 0x00400644 -#define NV04_PGRAPH_BOFFSET2 0x00400648 -#define NV04_PGRAPH_BOFFSET3 0x0040064C -#define NV04_PGRAPH_BOFFSET4 0x00400650 -#define NV04_PGRAPH_BOFFSET5 0x00400654 -#define NV04_PGRAPH_BBASE0 0x00400658 -#define NV04_PGRAPH_BBASE1 0x0040065C -#define NV04_PGRAPH_BBASE2 0x00400660 -#define NV04_PGRAPH_BBASE3 0x00400664 -#define NV04_PGRAPH_BBASE4 0x00400668 -#define NV04_PGRAPH_BBASE5 0x0040066C -#define NV04_PGRAPH_BPITCH0 0x00400670 -#define NV04_PGRAPH_BPITCH1 0x00400674 -#define NV04_PGRAPH_BPITCH2 0x00400678 -#define NV04_PGRAPH_BPITCH3 0x0040067C -#define NV04_PGRAPH_BPITCH4 0x00400680 -#define NV04_PGRAPH_BLIMIT0 0x00400684 -#define NV04_PGRAPH_BLIMIT1 0x00400688 -#define NV04_PGRAPH_BLIMIT2 0x0040068C -#define NV04_PGRAPH_BLIMIT3 0x00400690 -#define NV04_PGRAPH_BLIMIT4 0x00400694 -#define NV04_PGRAPH_BLIMIT5 0x00400698 -#define NV04_PGRAPH_BSWIZZLE2 0x0040069C -#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 -#define NV03_PGRAPH_STATUS 0x004006B0 -#define NV04_PGRAPH_STATUS 0x00400700 -# define NV40_PGRAPH_STATUS_SYNC_STALL 0x00004000 -#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 -#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 -#define NV04_PGRAPH_SURFACE 0x0040070C -#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C -#define NV04_PGRAPH_STATE 0x00400710 -#define NV10_PGRAPH_SURFACE 0x00400710 -#define NV04_PGRAPH_NOTIFY 0x00400714 -#define NV10_PGRAPH_STATE 0x00400714 -#define NV10_PGRAPH_NOTIFY 0x00400718 - -#define NV04_PGRAPH_FIFO 0x00400720 - -#define NV04_PGRAPH_BPIXEL 0x00400724 -#define NV10_PGRAPH_RDI_INDEX 0x00400750 -#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 -#define NV10_PGRAPH_RDI_DATA 0x00400754 -#define NV04_PGRAPH_DMA_PITCH 0x00400760 -#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760 -#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 -#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 -#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 -#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768 -#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c -#define NV10_PGRAPH_DMA_PITCH 0x00400770 -#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 -#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 -#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 -#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 -#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 -#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 -#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 -#define NV04_PGRAPH_PATT_COLOR0 0x00400800 -#define NV04_PGRAPH_PATT_COLOR1 0x00400804 -#define NV04_PGRAPH_PATTERN 0x00400808 -#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 -#define NV04_PGRAPH_CHROMA 0x00400814 -#define NV04_PGRAPH_CONTROL0 0x00400818 -#define NV04_PGRAPH_CONTROL1 0x0040081C -#define NV04_PGRAPH_CONTROL2 0x00400820 -#define NV04_PGRAPH_BLEND 0x00400824 -#define NV04_PGRAPH_STORED_FMT 0x00400830 -#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 -#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16)) -#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16)) -#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16)) -#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16)) -#define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i)) -#define NV41_PGRAPH_ZCOMP0(i) (0x004009c0 + 4*(i)) -#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) -#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) -#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) -#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) -#define NV04_PGRAPH_U_RAM 0x00400D00 -#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16)) -#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16)) -#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16)) -#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16)) -#define NV04_PGRAPH_V_RAM 0x00400D40 -#define NV04_PGRAPH_W_RAM 0x00400D80 -#define NV47_PGRAPH_ZCOMP0(i) (0x00400e00 + 4*(i)) -#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 -#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 -#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 -#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C -#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 -#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 -#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 -#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C -#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 -#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 -#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 -#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C -#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 -#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 -#define NV10_PGRAPH_XFMODE0 0x00400F40 -#define NV10_PGRAPH_XFMODE1 0x00400F44 -#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 -#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C -#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 -#define NV10_PGRAPH_PIPE_DATA 0x00400F54 -#define NV04_PGRAPH_DMA_START_0 0x00401000 -#define NV04_PGRAPH_DMA_START_1 0x00401004 -#define NV04_PGRAPH_DMA_LENGTH 0x00401008 -#define NV04_PGRAPH_DMA_MISC 0x0040100C -#define NV04_PGRAPH_DMA_DATA_0 0x00401020 -#define NV04_PGRAPH_DMA_DATA_1 0x00401024 -#define NV04_PGRAPH_DMA_RM 0x00401030 -#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 -#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 -#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 -#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C -#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 -#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 -#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 -#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C -#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 -#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 -#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 -#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 -#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C -#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 -#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 -#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 -#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C -#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 -#define NV47_PGRAPH_ZCOMP1(i) (0x004068c0 + 4*(i)) -#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) -#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) -#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) -#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) -#define NV40_PGRAPH_ZCOMP1(i) (0x00406980 + 4*(i)) -#define NV41_PGRAPH_ZCOMP1(i) (0x004069c0 + 4*(i)) - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index 8803809f9fc5..f65bc796bcde 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include "nv04.h" @@ -73,12 +73,12 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, /* PRAMIN aperture maps over the end of vram, reserve enough space * to fit graphics contexts for every channel, the magics come - * from engine/graph/nv40.c + * from engine/gr/nv40.c */ vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8); if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs; else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs; - else if (nv44_graph_class(priv)) priv->base.reserved = 0x4980 * vs; + else if (nv44_gr_class(priv)) priv->base.reserved = 0x4980 * vs; else priv->base.reserved = 0x4a40 * vs; priv->base.reserved += 16 * 1024; priv->base.reserved *= 32; /* per-channel */ -- cgit v1.2.3-59-g8ed1b From 8700287be2b12d091d477fe0568c3858bdedf4e7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 12:34:00 +1000 Subject: drm/nouveau/sw: rename from software (no binary change) Shorter device name, make consistent with our engine enums. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +- .../gpu/drm/nouveau/include/nvkm/engine/software.h | 51 ----- drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h | 51 +++++ drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +- drivers/gpu/drm/nouveau/nouveau_reg.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 16 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 +-- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +-- drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/software/Kbuild | 4 - .../gpu/drm/nouveau/nvkm/engine/software/nv04.c | 146 ------------- .../gpu/drm/nouveau/nvkm/engine/software/nv10.c | 128 ----------- .../gpu/drm/nouveau/nvkm/engine/software/nv50.c | 241 --------------------- .../gpu/drm/nouveau/nvkm/engine/software/nv50.h | 46 ---- .../gpu/drm/nouveau/nvkm/engine/software/nvc0.c | 149 ------------- drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild | 4 + drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c | 146 +++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c | 128 +++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 241 +++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 46 ++++ drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c | 149 +++++++++++++ 36 files changed, 854 insertions(+), 854 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/software.h create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 7f1770beff21..90e2d9706f23 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -53,7 +53,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); #include #include #include -#include +#include #define nvkm_fifo(a) nouveau_fifo(nvkm_device(a)) #define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a)) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h deleted file mode 100644 index 23a462b50d03..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __NOUVEAU_SOFTWARE_H__ -#define __NOUVEAU_SOFTWARE_H__ - -#include -#include - -struct nouveau_software_chan { - struct nouveau_engctx base; - - int (*flip)(void *); - void *flip_data; -}; - -#define nouveau_software_context_create(p,e,c,d) \ - nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d)) -#define nouveau_software_context_destroy(d) \ - nouveau_engctx_destroy(&(d)->base) -#define nouveau_software_context_init(d) \ - nouveau_engctx_init(&(d)->base) -#define nouveau_software_context_fini(d,s) \ - nouveau_engctx_fini(&(d)->base, (s)) - -#define _nouveau_software_context_dtor _nouveau_engctx_dtor -#define _nouveau_software_context_init _nouveau_engctx_init -#define _nouveau_software_context_fini _nouveau_engctx_fini - -struct nouveau_software { - struct nouveau_engine base; -}; - -#define nouveau_software_create(p,e,c,d) \ - nouveau_engine_create((p), (e), (c), true, "SW", "software", (d)) -#define nouveau_software_destroy(d) \ - nouveau_engine_destroy(&(d)->base) -#define nouveau_software_init(d) \ - nouveau_engine_init(&(d)->base) -#define nouveau_software_fini(d,s) \ - nouveau_engine_fini(&(d)->base, (s)) - -#define _nouveau_software_dtor _nouveau_engine_dtor -#define _nouveau_software_init _nouveau_engine_init -#define _nouveau_software_fini _nouveau_engine_fini - -extern struct nouveau_oclass *nv04_software_oclass; -extern struct nouveau_oclass *nv10_software_oclass; -extern struct nouveau_oclass *nv50_software_oclass; -extern struct nouveau_oclass *nvc0_software_oclass; - -void nv04_software_intr(struct nouveau_subdev *); - -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h new file mode 100644 index 000000000000..4c61a39222bb --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h @@ -0,0 +1,51 @@ +#ifndef __NOUVEAU_SW_H__ +#define __NOUVEAU_SW_H__ + +#include +#include + +struct nouveau_sw_chan { + struct nouveau_engctx base; + + int (*flip)(void *); + void *flip_data; +}; + +#define nouveau_sw_context_create(p,e,c,d) \ + nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d)) +#define nouveau_sw_context_destroy(d) \ + nouveau_engctx_destroy(&(d)->base) +#define nouveau_sw_context_init(d) \ + nouveau_engctx_init(&(d)->base) +#define nouveau_sw_context_fini(d,s) \ + nouveau_engctx_fini(&(d)->base, (s)) + +#define _nouveau_sw_context_dtor _nouveau_engctx_dtor +#define _nouveau_sw_context_init _nouveau_engctx_init +#define _nouveau_sw_context_fini _nouveau_engctx_fini + +struct nouveau_sw { + struct nouveau_engine base; +}; + +#define nouveau_sw_create(p,e,c,d) \ + nouveau_engine_create((p), (e), (c), true, "SW", "software", (d)) +#define nouveau_sw_destroy(d) \ + nouveau_engine_destroy(&(d)->base) +#define nouveau_sw_init(d) \ + nouveau_engine_init(&(d)->base) +#define nouveau_sw_fini(d,s) \ + nouveau_engine_fini(&(d)->base, (s)) + +#define _nouveau_sw_dtor _nouveau_engine_dtor +#define _nouveau_sw_init _nouveau_engine_init +#define _nouveau_sw_fini _nouveau_engine_fini + +extern struct nouveau_oclass *nv04_sw_oclass; +extern struct nouveau_oclass *nv10_sw_oclass; +extern struct nouveau_oclass *nv50_sw_oclass; +extern struct nouveau_oclass *nvc0_sw_oclass; + +void nv04_sw_intr(struct nouveau_subdev *); + +#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 80302530ead7..58b8b6423026 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -282,7 +282,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) struct nvif_device *device = chan->device; struct nouveau_cli *cli = (void *)nvif_client(&device->base); struct nouveau_mmu *mmu = nvkm_mmu(device); - struct nouveau_software_chan *swch; + struct nouveau_sw_chan *swch; struct nv_dma_v0 args = {}; int ret, i; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 1118efa56817..e684040ccf11 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -231,7 +231,7 @@ nouveau_accel_init(struct nouveau_drm *drm) ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW, nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw); if (ret == 0) { - struct nouveau_software_chan *swch; + struct nouveau_sw_chan *swch; ret = RING_SPACE(drm->channel, 2); if (ret == 0) { if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 43a96b99e180..7226f1f60901 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h @@ -72,7 +72,7 @@ # define NV_RAMHT_CONTEXT_VALID (1<<31) # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 -# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 +# define NV_RAMHT_CONTEXT_ENGINE_SW 0 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index 0607d595f6e7..bc51b0581ba5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -14,5 +14,5 @@ include $(src)/nvkm/engine/msvld/Kbuild include $(src)/nvkm/engine/pm/Kbuild include $(src)/nvkm/engine/msppp/Kbuild include $(src)/nvkm/engine/sec/Kbuild -include $(src)/nvkm/engine/software/Kbuild +include $(src)/nvkm/engine/sw/Kbuild include $(src)/nvkm/engine/vp/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 690250503332..55e463396c8c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -45,7 +45,7 @@ #include #include #include -#include +#include #include #include #include @@ -85,7 +85,7 @@ gm100_identify(struct nouveau_device *device) #endif device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -129,7 +129,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; #if 0 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #endif device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index dcb53917b5e0..1d409af560da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include @@ -58,7 +58,7 @@ nv04_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -76,7 +76,7 @@ nv04_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index f292e7b88628..66d8c338ae98 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include @@ -77,7 +77,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -96,7 +96,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -115,7 +115,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -134,7 +134,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -153,7 +153,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -172,7 +172,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -191,7 +191,7 @@ nv10_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index a03420ca82b1..59cefdd46897 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include #include @@ -61,7 +61,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -80,7 +80,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -99,7 +99,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -118,7 +118,7 @@ nv20_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 59b6baa64b4c..dfb610f837b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -61,7 +61,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -80,7 +80,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; @@ -99,7 +99,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -119,7 +119,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -139,7 +139,7 @@ nv30_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index cd859b081db4..7bdb7d6729b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -40,7 +40,7 @@ #include #include #include -#include +#include #include #include #include @@ -67,7 +67,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -90,7 +90,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -113,7 +113,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -136,7 +136,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -159,7 +159,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -182,7 +182,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -205,7 +205,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -228,7 +228,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -251,7 +251,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -274,7 +274,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -297,7 +297,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -320,7 +320,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -343,7 +343,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -366,7 +366,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -389,7 +389,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; @@ -412,7 +412,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 3f3d2ea1a930..13203f53c80d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -43,7 +43,7 @@ #include #include #include -#include +#include #include #include #include @@ -80,7 +80,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; @@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; @@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; @@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; @@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; @@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; @@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; @@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; @@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; @@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; @@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; @@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; @@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; @@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index b241421e76a2..ae856f8bcc75 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -45,7 +45,7 @@ #include #include #include -#include +#include #include #include #include @@ -82,7 +82,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -115,7 +115,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -148,7 +148,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -180,7 +180,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -245,7 +245,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -277,7 +277,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -310,7 +310,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; @@ -340,7 +340,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index df975987b9ca..13934f2b9cbd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -45,7 +45,7 @@ #include #include #include -#include +#include #include #include #include @@ -82,7 +82,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -116,7 +116,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -150,7 +150,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -176,7 +176,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; @@ -206,7 +206,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -240,7 +240,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -274,7 +274,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; @@ -307,7 +307,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c index e2ad0543fb31..26aaa2a201e5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c index 672ded79b2a9..40b44f990990 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c index 13eff5e4ee51..547926678710 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c index 2bb7ac5cd0e6..c009be4fb11c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c index b32456c9494f..317fd1a22076 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c index 951d79f9b781..af9441338239 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c index 55debec7e68f..063cb4ad304c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c index 3e7e2d28744c..3fd9b462d51f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild deleted file mode 100644 index e1332a15dc1b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild +++ /dev/null @@ -1,4 +0,0 @@ -nvkm-y += nvkm/engine/software/nv04.o -nvkm-y += nvkm/engine/software/nv10.o -nvkm-y += nvkm/engine/software/nv50.o -nvkm-y += nvkm/engine/software/nvc0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c deleted file mode 100644 index 64df15c7f051..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include -#include - -struct nv04_software_priv { - struct nouveau_software base; -}; - -struct nv04_software_chan { - struct nouveau_software_chan base; -}; - -/******************************************************************************* - * software object classes - ******************************************************************************/ - -static int -nv04_software_set_ref(struct nouveau_object *object, u32 mthd, - void *data, u32 size) -{ - struct nouveau_object *channel = (void *)nv_engctx(object->parent); - struct nouveau_fifo_chan *fifo = (void *)channel->parent; - atomic_set(&fifo->refcnt, *(u32*)data); - return 0; -} - -static int -nv04_software_flip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv04_software_chan *chan = (void *)nv_engctx(object->parent); - if (chan->base.flip) - return chan->base.flip(chan->base.flip_data); - return -EINVAL; -} - -static struct nouveau_omthds -nv04_software_omthds[] = { - { 0x0150, 0x0150, nv04_software_set_ref }, - { 0x0500, 0x0500, nv04_software_flip }, - {} -}; - -static struct nouveau_oclass -nv04_software_sclass[] = { - { 0x006e, &nouveau_object_ofuncs, nv04_software_omthds }, - {} -}; - -/******************************************************************************* - * software context - ******************************************************************************/ - -static int -nv04_software_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv04_software_chan *chan; - int ret; - - ret = nouveau_software_context_create(parent, engine, oclass, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - return 0; -} - -static struct nouveau_oclass -nv04_software_cclass = { - .handle = NV_ENGCTX(SW, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_software_context_ctor, - .dtor = _nouveau_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, - }, -}; - -/******************************************************************************* - * software engine/subdev functions - ******************************************************************************/ - -void -nv04_software_intr(struct nouveau_subdev *subdev) -{ - nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); -} - -static int -nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv04_software_priv *priv; - int ret; - - ret = nouveau_software_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nv04_software_cclass; - nv_engine(priv)->sclass = nv04_software_sclass; - nv_subdev(priv)->intr = nv04_software_intr; - return 0; -} - -struct nouveau_oclass * -nv04_software_oclass = &(struct nouveau_oclass) { - .handle = NV_ENGINE(SW, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c deleted file mode 100644 index f54a2253deca..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include - -#include - -struct nv10_software_priv { - struct nouveau_software base; -}; - -struct nv10_software_chan { - struct nouveau_software_chan base; -}; - -/******************************************************************************* - * software object classes - ******************************************************************************/ - -static int -nv10_software_flip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv10_software_chan *chan = (void *)nv_engctx(object->parent); - if (chan->base.flip) - return chan->base.flip(chan->base.flip_data); - return -EINVAL; -} - -static struct nouveau_omthds -nv10_software_omthds[] = { - { 0x0500, 0x0500, nv10_software_flip }, - {} -}; - -static struct nouveau_oclass -nv10_software_sclass[] = { - { 0x016e, &nouveau_object_ofuncs, nv10_software_omthds }, - {} -}; - -/******************************************************************************* - * software context - ******************************************************************************/ - -static int -nv10_software_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv10_software_chan *chan; - int ret; - - ret = nouveau_software_context_create(parent, engine, oclass, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - return 0; -} - -static struct nouveau_oclass -nv10_software_cclass = { - .handle = NV_ENGCTX(SW, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_software_context_ctor, - .dtor = _nouveau_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, - }, -}; - -/******************************************************************************* - * software engine/subdev functions - ******************************************************************************/ - -static int -nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv10_software_priv *priv; - int ret; - - ret = nouveau_software_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nv10_software_cclass; - nv_engine(priv)->sclass = nv10_software_sclass; - nv_subdev(priv)->intr = nv04_software_intr; - return 0; -} - -struct nouveau_oclass * -nv10_software_oclass = &(struct nouveau_oclass) { - .handle = NV_ENGINE(SW, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c deleted file mode 100644 index a0fec205f9db..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include "nv50.h" - -/******************************************************************************* - * software object classes - ******************************************************************************/ - -static int -nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent; - struct nouveau_handle *handle; - int ret = -EINVAL; - - handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args); - if (!handle) - return -ENOENT; - - if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { - struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object); - chan->vblank.ctxdma = gpuobj->node->offset >> 4; - ret = 0; - } - nouveau_namedb_put(handle); - return ret; -} - -static int -nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - chan->vblank.offset = *(u32 *)args; - return 0; -} - -int -nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - chan->vblank.value = *(u32 *)args; - return 0; -} - -int -nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - u32 head = *(u32 *)args; - if (head >= nouveau_disp(chan)->vblank.index_nr) - return -EINVAL; - - nvkm_notify_get(&chan->vblank.notify[head]); - return 0; -} - -int -nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - if (chan->base.flip) - return chan->base.flip(chan->base.flip_data); - return -EINVAL; -} - -static struct nouveau_omthds -nv50_software_omthds[] = { - { 0x018c, 0x018c, nv50_software_mthd_dma_vblsem }, - { 0x0400, 0x0400, nv50_software_mthd_vblsem_offset }, - { 0x0404, 0x0404, nv50_software_mthd_vblsem_value }, - { 0x0408, 0x0408, nv50_software_mthd_vblsem_release }, - { 0x0500, 0x0500, nv50_software_mthd_flip }, - {} -}; - -static struct nouveau_oclass -nv50_software_sclass[] = { - { 0x506e, &nouveau_object_ofuncs, nv50_software_omthds }, - {} -}; - -/******************************************************************************* - * software context - ******************************************************************************/ - -static int -nv50_software_vblsem_release(struct nvkm_notify *notify) -{ - struct nv50_software_chan *chan = - container_of(notify, typeof(*chan), vblank.notify[notify->index]); - struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; - struct nouveau_bar *bar = nouveau_bar(priv); - - nv_wr32(priv, 0x001704, chan->vblank.channel); - nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); - bar->flush(bar); - - if (nv_device(priv)->chipset == 0x50) { - nv_wr32(priv, 0x001570, chan->vblank.offset); - nv_wr32(priv, 0x001574, chan->vblank.value); - } else { - nv_wr32(priv, 0x060010, chan->vblank.offset); - nv_wr32(priv, 0x060014, chan->vblank.value); - } - - return NVKM_NOTIFY_DROP; -} - -void -nv50_software_context_dtor(struct nouveau_object *object) -{ - struct nv50_software_chan *chan = (void *)object; - int i; - - for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) - nvkm_notify_fini(&chan->vblank.notify[i]); - - nouveau_software_context_destroy(&chan->base); -} - -int -nv50_software_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_disp *pdisp = nouveau_disp(parent); - struct nv50_software_cclass *pclass = (void *)oclass; - struct nv50_software_chan *chan; - int ret, i; - - ret = nouveau_software_context_create(parent, engine, oclass, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) { - ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank, - false, - &(struct nvif_notify_head_req_v0) { - .head = i, - }, - sizeof(struct nvif_notify_head_req_v0), - sizeof(struct nvif_notify_head_rep_v0), - &chan->vblank.notify[i]); - if (ret) - return ret; - } - - chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; - return 0; -} - -static struct nv50_software_cclass -nv50_software_cclass = { - .base.handle = NV_ENGCTX(SW, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_context_ctor, - .dtor = nv50_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, - }, - .vblank = nv50_software_vblsem_release, -}; - -/******************************************************************************* - * software engine/subdev functions - ******************************************************************************/ - -int -nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv50_software_oclass *pclass = (void *)oclass; - struct nv50_software_priv *priv; - int ret; - - ret = nouveau_software_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_engine(priv)->cclass = pclass->cclass; - nv_engine(priv)->sclass = pclass->sclass; - nv_subdev(priv)->intr = nv04_software_intr; - return 0; -} - -struct nouveau_oclass * -nv50_software_oclass = &(struct nv50_software_oclass) { - .base.handle = NV_ENGINE(SW, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, - }, - .cclass = &nv50_software_cclass.base, - .sclass = nv50_software_sclass, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h deleted file mode 100644 index 41542e725b4b..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __NVKM_SW_NV50_H__ -#define __NVKM_SW_NV50_H__ - -#include - -struct nv50_software_oclass { - struct nouveau_oclass base; - struct nouveau_oclass *cclass; - struct nouveau_oclass *sclass; -}; - -struct nv50_software_priv { - struct nouveau_software base; -}; - -int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -struct nv50_software_cclass { - struct nouveau_oclass base; - int (*vblank)(struct nvkm_notify *); -}; - -struct nv50_software_chan { - struct nouveau_software_chan base; - struct { - struct nvkm_notify notify[4]; - u32 channel; - u32 ctxdma; - u64 offset; - u32 value; - } vblank; -}; - -int nv50_software_context_ctor(struct nouveau_object *, - struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv50_software_context_dtor(struct nouveau_object *); - -int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32); -int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32); -int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c deleted file mode 100644 index 6af370d3a06d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include - -#include -#include - -#include "nv50.h" - -/******************************************************************************* - * software object classes - ******************************************************************************/ - -static int -nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - u64 data = *(u32 *)args; - if (mthd == 0x0400) { - chan->vblank.offset &= 0x00ffffffffULL; - chan->vblank.offset |= data << 32; - } else { - chan->vblank.offset &= 0xff00000000ULL; - chan->vblank.offset |= data; - } - return 0; -} - -static int -nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd, - void *args, u32 size) -{ - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; - u32 data = *(u32 *)args; - - switch (mthd) { - case 0x600: - nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */ - break; - case 0x644: - if (data & ~0x1ffffe) - return -EINVAL; - nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ - break; - case 0x6ac: - nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */ - break; - default: - return -EINVAL; - } - return 0; -} - -static struct nouveau_omthds -nvc0_software_omthds[] = { - { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset }, - { 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset }, - { 0x0408, 0x0408, nv50_software_mthd_vblsem_value }, - { 0x040c, 0x040c, nv50_software_mthd_vblsem_release }, - { 0x0500, 0x0500, nv50_software_mthd_flip }, - { 0x0600, 0x0600, nvc0_software_mthd_mp_control }, - { 0x0644, 0x0644, nvc0_software_mthd_mp_control }, - { 0x06ac, 0x06ac, nvc0_software_mthd_mp_control }, - {} -}; - -static struct nouveau_oclass -nvc0_software_sclass[] = { - { 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds }, - {} -}; - -/******************************************************************************* - * software context - ******************************************************************************/ - -static int -nvc0_software_vblsem_release(struct nvkm_notify *notify) -{ - struct nv50_software_chan *chan = - container_of(notify, typeof(*chan), vblank.notify[notify->index]); - struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; - struct nouveau_bar *bar = nouveau_bar(priv); - - nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); - bar->flush(bar); - nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset)); - nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset)); - nv_wr32(priv, 0x060014, chan->vblank.value); - - return NVKM_NOTIFY_DROP; -} - -static struct nv50_software_cclass -nvc0_software_cclass = { - .base.handle = NV_ENGCTX(SW, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_context_ctor, - .dtor = nv50_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, - }, - .vblank = nvc0_software_vblsem_release, -}; - -/******************************************************************************* - * software engine/subdev functions - ******************************************************************************/ - -struct nouveau_oclass * -nvc0_software_oclass = &(struct nv50_software_oclass) { - .base.handle = NV_ENGINE(SW, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, - }, - .cclass = &nvc0_software_cclass.base, - .sclass = nvc0_software_sclass, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild new file mode 100644 index 000000000000..b8d215900fce --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/engine/sw/nv04.o +nvkm-y += nvkm/engine/sw/nv10.o +nvkm-y += nvkm/engine/sw/nv50.o +nvkm-y += nvkm/engine/sw/nvc0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c new file mode 100644 index 000000000000..3d0e4bc76389 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -0,0 +1,146 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include +#include + +struct nv04_sw_priv { + struct nouveau_sw base; +}; + +struct nv04_sw_chan { + struct nouveau_sw_chan base; +}; + +/******************************************************************************* + * software object classes + ******************************************************************************/ + +static int +nv04_sw_set_ref(struct nouveau_object *object, u32 mthd, + void *data, u32 size) +{ + struct nouveau_object *channel = (void *)nv_engctx(object->parent); + struct nouveau_fifo_chan *fifo = (void *)channel->parent; + atomic_set(&fifo->refcnt, *(u32*)data); + return 0; +} + +static int +nv04_sw_flip(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent); + if (chan->base.flip) + return chan->base.flip(chan->base.flip_data); + return -EINVAL; +} + +static struct nouveau_omthds +nv04_sw_omthds[] = { + { 0x0150, 0x0150, nv04_sw_set_ref }, + { 0x0500, 0x0500, nv04_sw_flip }, + {} +}; + +static struct nouveau_oclass +nv04_sw_sclass[] = { + { 0x006e, &nouveau_object_ofuncs, nv04_sw_omthds }, + {} +}; + +/******************************************************************************* + * software context + ******************************************************************************/ + +static int +nv04_sw_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv04_sw_chan *chan; + int ret; + + ret = nouveau_sw_context_create(parent, engine, oclass, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + return 0; +} + +static struct nouveau_oclass +nv04_sw_cclass = { + .handle = NV_ENGCTX(SW, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_sw_context_ctor, + .dtor = _nouveau_sw_context_dtor, + .init = _nouveau_sw_context_init, + .fini = _nouveau_sw_context_fini, + }, +}; + +/******************************************************************************* + * software engine/subdev functions + ******************************************************************************/ + +void +nv04_sw_intr(struct nouveau_subdev *subdev) +{ + nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); +} + +static int +nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv04_sw_priv *priv; + int ret; + + ret = nouveau_sw_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nv04_sw_cclass; + nv_engine(priv)->sclass = nv04_sw_sclass; + nv_subdev(priv)->intr = nv04_sw_intr; + return 0; +} + +struct nouveau_oclass * +nv04_sw_oclass = &(struct nouveau_oclass) { + .handle = NV_ENGINE(SW, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv04_sw_ctor, + .dtor = _nouveau_sw_dtor, + .init = _nouveau_sw_init, + .fini = _nouveau_sw_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c new file mode 100644 index 000000000000..12775cdbde70 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -0,0 +1,128 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include + +struct nv10_sw_priv { + struct nouveau_sw base; +}; + +struct nv10_sw_chan { + struct nouveau_sw_chan base; +}; + +/******************************************************************************* + * software object classes + ******************************************************************************/ + +static int +nv10_sw_flip(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent); + if (chan->base.flip) + return chan->base.flip(chan->base.flip_data); + return -EINVAL; +} + +static struct nouveau_omthds +nv10_sw_omthds[] = { + { 0x0500, 0x0500, nv10_sw_flip }, + {} +}; + +static struct nouveau_oclass +nv10_sw_sclass[] = { + { 0x016e, &nouveau_object_ofuncs, nv10_sw_omthds }, + {} +}; + +/******************************************************************************* + * software context + ******************************************************************************/ + +static int +nv10_sw_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv10_sw_chan *chan; + int ret; + + ret = nouveau_sw_context_create(parent, engine, oclass, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + return 0; +} + +static struct nouveau_oclass +nv10_sw_cclass = { + .handle = NV_ENGCTX(SW, 0x04), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv10_sw_context_ctor, + .dtor = _nouveau_sw_context_dtor, + .init = _nouveau_sw_context_init, + .fini = _nouveau_sw_context_fini, + }, +}; + +/******************************************************************************* + * software engine/subdev functions + ******************************************************************************/ + +static int +nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv10_sw_priv *priv; + int ret; + + ret = nouveau_sw_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nv10_sw_cclass; + nv_engine(priv)->sclass = nv10_sw_sclass; + nv_subdev(priv)->intr = nv04_sw_intr; + return 0; +} + +struct nouveau_oclass * +nv10_sw_oclass = &(struct nouveau_oclass) { + .handle = NV_ENGINE(SW, 0x10), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv10_sw_ctor, + .dtor = _nouveau_sw_dtor, + .init = _nouveau_sw_init, + .fini = _nouveau_sw_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c new file mode 100644 index 000000000000..a214a4debcc4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -0,0 +1,241 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "nv50.h" + +/******************************************************************************* + * software object classes + ******************************************************************************/ + +static int +nv50_sw_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent; + struct nouveau_handle *handle; + int ret = -EINVAL; + + handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args); + if (!handle) + return -ENOENT; + + if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { + struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object); + chan->vblank.ctxdma = gpuobj->node->offset >> 4; + ret = 0; + } + nouveau_namedb_put(handle); + return ret; +} + +static int +nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + chan->vblank.offset = *(u32 *)args; + return 0; +} + +int +nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + chan->vblank.value = *(u32 *)args; + return 0; +} + +int +nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + u32 head = *(u32 *)args; + if (head >= nouveau_disp(chan)->vblank.index_nr) + return -EINVAL; + + nvkm_notify_get(&chan->vblank.notify[head]); + return 0; +} + +int +nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + if (chan->base.flip) + return chan->base.flip(chan->base.flip_data); + return -EINVAL; +} + +static struct nouveau_omthds +nv50_sw_omthds[] = { + { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem }, + { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset }, + { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value }, + { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release }, + { 0x0500, 0x0500, nv50_sw_mthd_flip }, + {} +}; + +static struct nouveau_oclass +nv50_sw_sclass[] = { + { 0x506e, &nouveau_object_ofuncs, nv50_sw_omthds }, + {} +}; + +/******************************************************************************* + * software context + ******************************************************************************/ + +static int +nv50_sw_vblsem_release(struct nvkm_notify *notify) +{ + struct nv50_sw_chan *chan = + container_of(notify, typeof(*chan), vblank.notify[notify->index]); + struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; + struct nouveau_bar *bar = nouveau_bar(priv); + + nv_wr32(priv, 0x001704, chan->vblank.channel); + nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); + bar->flush(bar); + + if (nv_device(priv)->chipset == 0x50) { + nv_wr32(priv, 0x001570, chan->vblank.offset); + nv_wr32(priv, 0x001574, chan->vblank.value); + } else { + nv_wr32(priv, 0x060010, chan->vblank.offset); + nv_wr32(priv, 0x060014, chan->vblank.value); + } + + return NVKM_NOTIFY_DROP; +} + +void +nv50_sw_context_dtor(struct nouveau_object *object) +{ + struct nv50_sw_chan *chan = (void *)object; + int i; + + for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) + nvkm_notify_fini(&chan->vblank.notify[i]); + + nouveau_sw_context_destroy(&chan->base); +} + +int +nv50_sw_context_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_disp *pdisp = nouveau_disp(parent); + struct nv50_sw_cclass *pclass = (void *)oclass; + struct nv50_sw_chan *chan; + int ret, i; + + ret = nouveau_sw_context_create(parent, engine, oclass, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) { + ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank, + false, + &(struct nvif_notify_head_req_v0) { + .head = i, + }, + sizeof(struct nvif_notify_head_req_v0), + sizeof(struct nvif_notify_head_rep_v0), + &chan->vblank.notify[i]); + if (ret) + return ret; + } + + chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; + return 0; +} + +static struct nv50_sw_cclass +nv50_sw_cclass = { + .base.handle = NV_ENGCTX(SW, 0x50), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_sw_context_ctor, + .dtor = nv50_sw_context_dtor, + .init = _nouveau_sw_context_init, + .fini = _nouveau_sw_context_fini, + }, + .vblank = nv50_sw_vblsem_release, +}; + +/******************************************************************************* + * software engine/subdev functions + ******************************************************************************/ + +int +nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_sw_oclass *pclass = (void *)oclass; + struct nv50_sw_priv *priv; + int ret; + + ret = nouveau_sw_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->cclass = pclass->cclass; + nv_engine(priv)->sclass = pclass->sclass; + nv_subdev(priv)->intr = nv04_sw_intr; + return 0; +} + +struct nouveau_oclass * +nv50_sw_oclass = &(struct nv50_sw_oclass) { + .base.handle = NV_ENGINE(SW, 0x50), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_sw_ctor, + .dtor = _nouveau_sw_dtor, + .init = _nouveau_sw_init, + .fini = _nouveau_sw_fini, + }, + .cclass = &nv50_sw_cclass.base, + .sclass = nv50_sw_sclass, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h new file mode 100644 index 000000000000..618e41fa36d0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h @@ -0,0 +1,46 @@ +#ifndef __NVKM_SW_NV50_H__ +#define __NVKM_SW_NV50_H__ + +#include + +struct nv50_sw_oclass { + struct nouveau_oclass base; + struct nouveau_oclass *cclass; + struct nouveau_oclass *sclass; +}; + +struct nv50_sw_priv { + struct nouveau_sw base; +}; + +int nv50_sw_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); + +struct nv50_sw_cclass { + struct nouveau_oclass base; + int (*vblank)(struct nvkm_notify *); +}; + +struct nv50_sw_chan { + struct nouveau_sw_chan base; + struct { + struct nvkm_notify notify[4]; + u32 channel; + u32 ctxdma; + u64 offset; + u32 value; + } vblank; +}; + +int nv50_sw_context_ctor(struct nouveau_object *, + struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); +void nv50_sw_context_dtor(struct nouveau_object *); + +int nv50_sw_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32); +int nv50_sw_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32); +int nv50_sw_mthd_flip(struct nouveau_object *, u32, void *, u32); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c new file mode 100644 index 000000000000..dcb056eae471 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c @@ -0,0 +1,149 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include + +#include + +#include +#include + +#include "nv50.h" + +/******************************************************************************* + * software object classes + ******************************************************************************/ + +static int +nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + u64 data = *(u32 *)args; + if (mthd == 0x0400) { + chan->vblank.offset &= 0x00ffffffffULL; + chan->vblank.offset |= data << 32; + } else { + chan->vblank.offset &= 0xff00000000ULL; + chan->vblank.offset |= data; + } + return 0; +} + +static int +nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd, + void *args, u32 size) +{ + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; + u32 data = *(u32 *)args; + + switch (mthd) { + case 0x600: + nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */ + break; + case 0x644: + if (data & ~0x1ffffe) + return -EINVAL; + nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ + break; + case 0x6ac: + nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */ + break; + default: + return -EINVAL; + } + return 0; +} + +static struct nouveau_omthds +nvc0_sw_omthds[] = { + { 0x0400, 0x0400, nvc0_sw_mthd_vblsem_offset }, + { 0x0404, 0x0404, nvc0_sw_mthd_vblsem_offset }, + { 0x0408, 0x0408, nv50_sw_mthd_vblsem_value }, + { 0x040c, 0x040c, nv50_sw_mthd_vblsem_release }, + { 0x0500, 0x0500, nv50_sw_mthd_flip }, + { 0x0600, 0x0600, nvc0_sw_mthd_mp_control }, + { 0x0644, 0x0644, nvc0_sw_mthd_mp_control }, + { 0x06ac, 0x06ac, nvc0_sw_mthd_mp_control }, + {} +}; + +static struct nouveau_oclass +nvc0_sw_sclass[] = { + { 0x906e, &nouveau_object_ofuncs, nvc0_sw_omthds }, + {} +}; + +/******************************************************************************* + * software context + ******************************************************************************/ + +static int +nvc0_sw_vblsem_release(struct nvkm_notify *notify) +{ + struct nv50_sw_chan *chan = + container_of(notify, typeof(*chan), vblank.notify[notify->index]); + struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; + struct nouveau_bar *bar = nouveau_bar(priv); + + nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); + bar->flush(bar); + nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset)); + nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset)); + nv_wr32(priv, 0x060014, chan->vblank.value); + + return NVKM_NOTIFY_DROP; +} + +static struct nv50_sw_cclass +nvc0_sw_cclass = { + .base.handle = NV_ENGCTX(SW, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_sw_context_ctor, + .dtor = nv50_sw_context_dtor, + .init = _nouveau_sw_context_init, + .fini = _nouveau_sw_context_fini, + }, + .vblank = nvc0_sw_vblsem_release, +}; + +/******************************************************************************* + * software engine/subdev functions + ******************************************************************************/ + +struct nouveau_oclass * +nvc0_sw_oclass = &(struct nv50_sw_oclass) { + .base.handle = NV_ENGINE(SW, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_sw_ctor, + .dtor = _nouveau_sw_dtor, + .init = _nouveau_sw_init, + .fini = _nouveau_sw_fini, + }, + .cclass = &nvc0_sw_cclass.base, + .sclass = nvc0_sw_sclass, +}.base; -- cgit v1.2.3-59-g8ed1b From 9719047b4d985ca7a46819956047cca04213d63e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 15:35:00 +1000 Subject: drm/nouveau/device: namespace + nvidia gpu names (no binary change) The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 14 + drivers/gpu/drm/nouveau/include/nvkm/core/os.h | 2 + drivers/gpu/drm/nouveau/nouveau_drm.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c | 9 +- drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h | 9 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 249 +++++++------- drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c | 66 ++-- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 358 +++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 326 +++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 12 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 14 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 36 +-- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 32 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 358 --------------------- drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 326 ------------------- drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h | 14 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 3 +- 22 files changed, 943 insertions(+), 931 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 1d186e21d123..1fafcac299d3 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -50,7 +50,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **); #define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c)) #define nvxx_therm(a) nouveau_therm(nvxx_device(a)) -#include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 9c2f13694a57..333db33a162c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -84,4 +84,18 @@ nv_device_resource_len(struct nvkm_device *device, unsigned int bar); int nv_device_get_irq(struct nvkm_device *device, bool stall); + +struct platform_device; + +enum nv_bus_type { + NVKM_BUS_PCI, + NVKM_BUS_PLATFORM, +}; + +#define nvkm_device_create(p,t,n,s,c,d,u) \ + nvkm_device_create_((void *)(p), (t), (n), (s), (c), (d), \ + sizeof(**u), (void **)u) +int nvkm_device_create_(void *, enum nv_bus_type type, u64 name, + const char *sname, const char *cfg, const char *dbg, + int, void **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index 0b35ba672265..537db3a512c8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -253,5 +253,7 @@ #define nouveau_gr nvkm_gr #define nouveau_sw nvkm_sw #define nouveau_sw_chan nvkm_sw_chan +#define nouveau_device_create nvkm_device_create +#define nouveau_device_create_ nvkm_device_create_ #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 1de82ec6c276..f4ac7b5af85e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -318,7 +318,7 @@ static int nouveau_drm_probe(struct pci_dev *pdev, remove_conflicting_framebuffers(aper, "nouveaufb", boot); kfree(aper); - ret = nouveau_device_create(pdev, NOUVEAU_BUS_PCI, + ret = nouveau_device_create(pdev, NVKM_BUS_PCI, nouveau_pci_name(pdev), pci_name(pdev), nouveau_config, nouveau_debug, &device); if (ret) @@ -1056,7 +1056,7 @@ nouveau_platform_device_create_(struct platform_device *pdev, int size, struct drm_device *drm; int err; - err = nouveau_device_create_(pdev, NOUVEAU_BUS_PLATFORM, + err = nouveau_device_create_(pdev, NVKM_BUS_PLATFORM, nouveau_platform_name(pdev), dev_name(&pdev->dev), nouveau_config, nouveau_debug, size, pobject); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild index 77d06d46eff4..de1bf092b2b2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild @@ -7,6 +7,6 @@ nvkm-y += nvkm/engine/device/nv20.o nvkm-y += nvkm/engine/device/nv30.o nvkm-y += nvkm/engine/device/nv40.o nvkm-y += nvkm/engine/device/nv50.o -nvkm-y += nvkm/engine/device/nvc0.o -nvkm-y += nvkm/engine/device/nve0.o +nvkm-y += nvkm/engine/device/gf100.o +nvkm-y += nvkm/engine/device/gk104.o nvkm-y += nvkm/engine/device/gm100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c index 4dbf0ba89e5c..f42706e1d5db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c @@ -21,14 +21,15 @@ * * Authors: Ben Skeggs */ - #include "acpi.h" +#include + #ifdef CONFIG_ACPI static int nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) { - struct nouveau_device *device = + struct nvkm_device *device = container_of(nb, typeof(*device), acpi.nb); struct acpi_bus_event *info = data; @@ -40,7 +41,7 @@ nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) #endif int -nvkm_acpi_fini(struct nouveau_device *device, bool suspend) +nvkm_acpi_fini(struct nvkm_device *device, bool suspend) { #ifdef CONFIG_ACPI unregister_acpi_notifier(&device->acpi.nb); @@ -49,7 +50,7 @@ nvkm_acpi_fini(struct nouveau_device *device, bool suspend) } int -nvkm_acpi_init(struct nouveau_device *device) +nvkm_acpi_init(struct nvkm_device *device) { #ifdef CONFIG_ACPI device->acpi.nb.notifier_call = nvkm_acpi_ntfy; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h index cc49f4f568cd..82dd359ddfa4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h @@ -1,9 +1,8 @@ #ifndef __NVKM_DEVICE_ACPI_H__ #define __NVKM_DEVICE_ACPI_H__ +#include +struct nvkm_device; -#include - -int nvkm_acpi_init(struct nouveau_device *); -int nvkm_acpi_fini(struct nouveau_device *, bool); - +int nvkm_acpi_init(struct nvkm_device *); +int nvkm_acpi_fini(struct nvkm_device *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index ae2ad8b4e5df..29bd539af183 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -21,29 +21,27 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include "acpi.h" -#include -#include -#include #include #include -#include -#include - +#include +#include #include #include #include -#include "priv.h" -#include "acpi.h" +#include +#include static DEFINE_MUTEX(nv_devices_mutex); static LIST_HEAD(nv_devices); -struct nouveau_device * -nouveau_device_find(u64 name) +struct nvkm_device * +nvkm_device_find(u64 name) { - struct nouveau_device *device, *match = NULL; + struct nvkm_device *device, *match = NULL; mutex_lock(&nv_devices_mutex); list_for_each_entry(device, &nv_devices, head) { if (device->handle == name) { @@ -56,9 +54,9 @@ nouveau_device_find(u64 name) } int -nouveau_device_list(u64 *name, int size) +nvkm_device_list(u64 *name, int size) { - struct nouveau_device *device; + struct nvkm_device *device; int nr = 0; mutex_lock(&nv_devices_mutex); list_for_each_entry(device, &nv_devices, head) { @@ -70,20 +68,20 @@ nouveau_device_list(u64 *name, int size) } /****************************************************************************** - * nouveau_devobj (0x0080): class implementation + * nvkm_devobj (0x0080): class implementation *****************************************************************************/ -struct nouveau_devobj { - struct nouveau_parent base; - struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; +struct nvkm_devobj { + struct nvkm_parent base; + struct nvkm_object *subdev[NVDEV_SUBDEV_NR]; }; static int -nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size) +nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) { - struct nouveau_device *device = nv_device(object); - struct nouveau_fb *pfb = nouveau_fb(device); - struct nouveau_instmem *imem = nouveau_instmem(device); + struct nvkm_device *device = nv_device(object); + struct nvkm_fb *pfb = nvkm_fb(device); + struct nvkm_instmem *imem = nvkm_instmem(device); union { struct nv_device_info_v0 v0; } *args = data; @@ -148,12 +146,11 @@ nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size) } static int -nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nvkm_devobj_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case NV_DEVICE_V0_INFO: - return nouveau_devobj_info(object, data, size); + return nvkm_devobj_info(object, data, size); default: break; } @@ -161,45 +158,45 @@ nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd, } static u8 -nouveau_devobj_rd08(struct nouveau_object *object, u64 addr) +nvkm_devobj_rd08(struct nvkm_object *object, u64 addr) { return nv_rd08(object->engine, addr); } static u16 -nouveau_devobj_rd16(struct nouveau_object *object, u64 addr) +nvkm_devobj_rd16(struct nvkm_object *object, u64 addr) { return nv_rd16(object->engine, addr); } static u32 -nouveau_devobj_rd32(struct nouveau_object *object, u64 addr) +nvkm_devobj_rd32(struct nvkm_object *object, u64 addr) { return nv_rd32(object->engine, addr); } static void -nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data) +nvkm_devobj_wr08(struct nvkm_object *object, u64 addr, u8 data) { nv_wr08(object->engine, addr, data); } static void -nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data) +nvkm_devobj_wr16(struct nvkm_object *object, u64 addr, u16 data) { nv_wr16(object->engine, addr, data); } static void -nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +nvkm_devobj_wr32(struct nvkm_object *object, u64 addr, u32 data) { nv_wr32(object->engine, addr, data); } static int -nouveau_devobj_map(struct nouveau_object *object, u64 *addr, u32 *size) +nvkm_devobj_map(struct nvkm_object *object, u64 *addr, u32 *size) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); *addr = nv_device_resource_start(device, 0); *size = nv_device_resource_len(device, 0); return 0; @@ -248,47 +245,46 @@ static const u64 disable_map[] = { }; static void -nouveau_devobj_dtor(struct nouveau_object *object) +nvkm_devobj_dtor(struct nvkm_object *object) { - struct nouveau_devobj *devobj = (void *)object; + struct nvkm_devobj *devobj = (void *)object; int i; for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) - nouveau_object_ref(NULL, &devobj->subdev[i]); + nvkm_object_ref(NULL, &devobj->subdev[i]); - nouveau_parent_destroy(&devobj->base); + nvkm_parent_destroy(&devobj->base); } -static struct nouveau_oclass -nouveau_devobj_oclass_super = { +static struct nvkm_oclass +nvkm_devobj_oclass_super = { .handle = NV_DEVICE, - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_devobj_dtor, - .init = _nouveau_parent_init, - .fini = _nouveau_parent_fini, - .mthd = nouveau_devobj_mthd, - .map = nouveau_devobj_map, - .rd08 = nouveau_devobj_rd08, - .rd16 = nouveau_devobj_rd16, - .rd32 = nouveau_devobj_rd32, - .wr08 = nouveau_devobj_wr08, - .wr16 = nouveau_devobj_wr16, - .wr32 = nouveau_devobj_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .dtor = nvkm_devobj_dtor, + .init = _nvkm_parent_init, + .fini = _nvkm_parent_fini, + .mthd = nvkm_devobj_mthd, + .map = nvkm_devobj_map, + .rd08 = nvkm_devobj_rd08, + .rd16 = nvkm_devobj_rd16, + .rd32 = nvkm_devobj_rd32, + .wr08 = nvkm_devobj_wr08, + .wr16 = nvkm_devobj_wr16, + .wr32 = nvkm_devobj_wr32, } }; static int -nouveau_devobj_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv_device_v0 v0; } *args = data; - struct nouveau_client *client = nv_client(parent); - struct nouveau_device *device; - struct nouveau_devobj *devobj; + struct nvkm_client *client = nv_client(parent); + struct nvkm_device *device; + struct nvkm_devobj *devobj; u32 boot0, strap; u64 disable, mmio_base, mmio_size; void __iomem *map; @@ -305,22 +301,22 @@ nouveau_devobj_ctor(struct nouveau_object *parent, /* give priviledged clients register access */ if (client->super) - oclass = &nouveau_devobj_oclass_super; + oclass = &nvkm_devobj_oclass_super; /* find the device subdev that matches what the client requested */ device = nv_device(client->device); if (args->v0.device != ~0) { - device = nouveau_device_find(args->v0.device); + device = nvkm_device_find(args->v0.device); if (!device) return -ENODEV; } - ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, - nouveau_control_oclass, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_FIFO) | - (1ULL << NVDEV_ENGINE_DISP) | - (1ULL << NVDEV_ENGINE_PM ), &devobj); + ret = nvkm_parent_create(parent, nv_object(device), oclass, 0, + nvkm_control_oclass, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_FIFO) | + (1ULL << NVDEV_ENGINE_DISP) | + (1ULL << NVDEV_ENGINE_PM), &devobj); *pobject = nv_object(devobj); if (ret) return ret; @@ -403,8 +399,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent, case NV_30: ret = nv30_identify(device); break; case NV_40: ret = nv40_identify(device); break; case NV_50: ret = nv50_identify(device); break; - case NV_C0: ret = nvc0_identify(device); break; - case NV_E0: ret = nve0_identify(device); break; + case NV_C0: ret = gf100_identify(device); break; + case NV_E0: ret = gk104_identify(device); break; case GM100: ret = gm100_identify(device); break; default: ret = -EINVAL; @@ -439,7 +435,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent, } else if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) { device->cname = "NULL"; - device->oclass[NVDEV_SUBDEV_VBIOS] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass; } if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && @@ -457,14 +453,12 @@ nouveau_devobj_ctor(struct nouveau_object *parent, continue; if (device->subdev[i]) { - nouveau_object_ref(device->subdev[i], - &devobj->subdev[i]); + nvkm_object_ref(device->subdev[i], &devobj->subdev[i]); continue; } - ret = nouveau_object_ctor(nv_object(device), NULL, - oclass, NULL, i, - &devobj->subdev[i]); + ret = nvkm_object_ctor(nv_object(device), NULL, oclass, + NULL, i, &devobj->subdev[i]); if (ret == -ENODEV) continue; if (ret) @@ -482,15 +476,15 @@ nouveau_devobj_ctor(struct nouveau_object *parent, * subdev in turn as they're created. */ while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { - struct nouveau_object *subdev = devobj->subdev[c++]; + struct nvkm_object *subdev = devobj->subdev[c++]; if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); + ret = nvkm_object_inc(subdev); if (ret) return ret; atomic_dec(&nv_object(device)->usecount); } else if (subdev) { - nouveau_subdev_reset(subdev); + nvkm_subdev_reset(subdev); } } } @@ -498,23 +492,23 @@ nouveau_devobj_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs -nouveau_devobj_ofuncs = { - .ctor = nouveau_devobj_ctor, - .dtor = nouveau_devobj_dtor, - .init = _nouveau_parent_init, - .fini = _nouveau_parent_fini, - .mthd = nouveau_devobj_mthd, +static struct nvkm_ofuncs +nvkm_devobj_ofuncs = { + .ctor = nvkm_devobj_ctor, + .dtor = nvkm_devobj_dtor, + .init = _nvkm_parent_init, + .fini = _nvkm_parent_fini, + .mthd = nvkm_devobj_mthd, }; /****************************************************************************** - * nouveau_device: engine functions + * nvkm_device: engine functions *****************************************************************************/ -struct nouveau_device * +struct nvkm_device * nv_device(void *obj) { - struct nouveau_object *device = nv_object(obj); + struct nvkm_object *device = nv_object(obj); if (device->engine == NULL) { while (device && device->parent) device = device->parent; @@ -530,15 +524,15 @@ nv_device(void *obj) return (void *)device; } -static struct nouveau_oclass -nouveau_device_sclass[] = { - { 0x0080, &nouveau_devobj_ofuncs }, +static struct nvkm_oclass +nvkm_device_sclass[] = { + { 0x0080, &nvkm_devobj_ofuncs }, {} }; static int -nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { if (!WARN_ON(size != 0)) { notify->size = 0; @@ -550,21 +544,21 @@ nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size, } static const struct nvkm_event_func -nouveau_device_event_func = { - .ctor = nouveau_device_event_ctor, +nvkm_device_event_func = { + .ctor = nvkm_device_event_ctor, }; static int -nouveau_device_fini(struct nouveau_object *object, bool suspend) +nvkm_device_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_device *device = (void *)object; - struct nouveau_object *subdev; + struct nvkm_device *device = (void *)object; + struct nvkm_object *subdev; int ret, i; for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_dec(subdev, suspend); + ret = nvkm_object_dec(subdev, suspend); if (ret && suspend) goto fail; } @@ -576,7 +570,7 @@ fail: for (; ret && i < NVDEV_SUBDEV_NR; i++) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); + ret = nvkm_object_inc(subdev); if (ret) { /* XXX */ } @@ -588,10 +582,10 @@ fail: } static int -nouveau_device_init(struct nouveau_object *object) +nvkm_device_init(struct nvkm_object *object) { - struct nouveau_device *device = (void *)object; - struct nouveau_object *subdev; + struct nvkm_device *device = (void *)object; + struct nvkm_object *subdev; int ret, i = 0; ret = nvkm_acpi_init(device); @@ -601,11 +595,11 @@ nouveau_device_init(struct nouveau_object *object) for (i = 0; i < NVDEV_SUBDEV_NR; i++) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); + ret = nvkm_object_inc(subdev); if (ret) goto fail; } else { - nouveau_subdev_reset(subdev); + nvkm_subdev_reset(subdev); } } } @@ -615,7 +609,7 @@ fail: for (--i; ret && i >= 0; i--) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) - nouveau_object_dec(subdev, false); + nvkm_object_dec(subdev, false); } } @@ -625,9 +619,9 @@ fail: } static void -nouveau_device_dtor(struct nouveau_object *object) +nvkm_device_dtor(struct nvkm_object *object) { - struct nouveau_device *device = (void *)object; + struct nvkm_device *device = (void *)object; nvkm_event_fini(&device->event); @@ -638,11 +632,11 @@ nouveau_device_dtor(struct nouveau_object *object) if (nv_subdev(device)->mmio) iounmap(nv_subdev(device)->mmio); - nouveau_engine_destroy(&device->engine); + nvkm_engine_destroy(&device->engine); } resource_size_t -nv_device_resource_start(struct nouveau_device *device, unsigned int bar) +nv_device_resource_start(struct nvkm_device *device, unsigned int bar) { if (nv_device_is_pci(device)) { return pci_resource_start(device->pdev, bar); @@ -657,7 +651,7 @@ nv_device_resource_start(struct nouveau_device *device, unsigned int bar) } resource_size_t -nv_device_resource_len(struct nouveau_device *device, unsigned int bar) +nv_device_resource_len(struct nvkm_device *device, unsigned int bar) { if (nv_device_is_pci(device)) { return pci_resource_len(device->pdev, bar); @@ -672,7 +666,7 @@ nv_device_resource_len(struct nouveau_device *device, unsigned int bar) } int -nv_device_get_irq(struct nouveau_device *device, bool stall) +nv_device_get_irq(struct nvkm_device *device, bool stall) { if (nv_device_is_pci(device)) { return device->pdev->irq; @@ -682,22 +676,22 @@ nv_device_get_irq(struct nouveau_device *device, bool stall) } } -static struct nouveau_oclass -nouveau_device_oclass = { +static struct nvkm_oclass +nvkm_device_oclass = { .handle = NV_ENGINE(DEVICE, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_device_dtor, - .init = nouveau_device_init, - .fini = nouveau_device_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .dtor = nvkm_device_dtor, + .init = nvkm_device_init, + .fini = nvkm_device_fini, }, }; int -nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, - const char *sname, const char *cfg, const char *dbg, - int length, void **pobject) +nvkm_device_create_(void *dev, enum nv_bus_type type, u64 name, + const char *sname, const char *cfg, const char *dbg, + int length, void **pobject) { - struct nouveau_device *device; + struct nvkm_device *device; int ret = -EEXIST; mutex_lock(&nv_devices_mutex); @@ -706,17 +700,17 @@ nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, goto done; } - ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true, - "DEVICE", "device", length, pobject); + ret = nvkm_engine_create_(NULL, NULL, &nvkm_device_oclass, true, + "DEVICE", "device", length, pobject); device = *pobject; if (ret) goto done; switch (type) { - case NOUVEAU_BUS_PCI: + case NVKM_BUS_PCI: device->pdev = dev; break; - case NOUVEAU_BUS_PLATFORM: + case NVKM_BUS_PLATFORM: device->platformdev = dev; break; } @@ -725,12 +719,11 @@ nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, device->dbgopt = dbg; device->name = sname; - nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); - nv_engine(device)->sclass = nouveau_device_sclass; + nv_subdev(device)->debug = nvkm_dbgopt(device->dbgopt, "DEVICE"); + nv_engine(device)->sclass = nvkm_device_sclass; list_add(&device->head, &nv_devices); - ret = nvkm_event_init(&nouveau_device_event_func, 1, 1, - &device->event); + ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); done: mutex_unlock(&nv_devices_mutex); return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c index 7a7632e65c77..0b794b13cec3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c @@ -21,25 +21,22 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include -#include -#include -#include -#include - #include -#include "priv.h" +#include +#include +#include static int -nouveau_control_mthd_pstate_info(struct nouveau_object *object, - void *data, u32 size) +nvkm_control_mthd_pstate_info(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_control_pstate_info_v0 v0; } *args = data; - struct nouveau_clk *clk = nouveau_clk(object); + struct nvkm_clk *clk = nvkm_clk(object); int ret; nv_ioctl(object, "control pstate info size %d\n", size); @@ -67,16 +64,15 @@ nouveau_control_mthd_pstate_info(struct nouveau_object *object, } static int -nouveau_control_mthd_pstate_attr(struct nouveau_object *object, - void *data, u32 size) +nvkm_control_mthd_pstate_attr(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_control_pstate_attr_v0 v0; } *args = data; - struct nouveau_clk *clk = nouveau_clk(object); - struct nouveau_domain *domain; - struct nouveau_pstate *pstate; - struct nouveau_cstate *cstate; + struct nvkm_clk *clk = nvkm_clk(object); + struct nvkm_domain *domain; + struct nvkm_pstate *pstate; + struct nvkm_cstate *cstate; int i = 0, j = -1; u32 lo, hi; int ret; @@ -141,13 +137,12 @@ nouveau_control_mthd_pstate_attr(struct nouveau_object *object, } static int -nouveau_control_mthd_pstate_user(struct nouveau_object *object, - void *data, u32 size) +nvkm_control_mthd_pstate_user(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_control_pstate_user_v0 v0; } *args = data; - struct nouveau_clk *clk = nouveau_clk(object); + struct nvkm_clk *clk = nvkm_clk(object); int ret; nv_ioctl(object, "control pstate user size %d\n", size); @@ -161,45 +156,44 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object, return ret; if (args->v0.pwrsrc >= 0) { - ret |= nouveau_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc); + ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc); } else { - ret |= nouveau_clk_ustate(clk, args->v0.ustate, 0); - ret |= nouveau_clk_ustate(clk, args->v0.ustate, 1); + ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0); + ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1); } return ret; } static int -nouveau_control_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nvkm_control_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case NVIF_CONTROL_PSTATE_INFO: - return nouveau_control_mthd_pstate_info(object, data, size); + return nvkm_control_mthd_pstate_info(object, data, size); case NVIF_CONTROL_PSTATE_ATTR: - return nouveau_control_mthd_pstate_attr(object, data, size); + return nvkm_control_mthd_pstate_attr(object, data, size); case NVIF_CONTROL_PSTATE_USER: - return nouveau_control_mthd_pstate_user(object, data, size); + return nvkm_control_mthd_pstate_user(object, data, size); default: break; } return -EINVAL; } -static struct nouveau_ofuncs -nouveau_control_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nouveau_control_mthd, +static struct nvkm_ofuncs +nvkm_control_ofuncs = { + .ctor = _nvkm_object_ctor, + .dtor = nvkm_object_destroy, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .mthd = nvkm_control_mthd, }; -struct nouveau_oclass -nouveau_control_oclass[] = { +struct nvkm_oclass +nvkm_control_oclass[] = { { .handle = NVIF_IOCTL_NEW_V0_CONTROL, - .ofuncs = &nouveau_control_ofuncs + .ofuncs = &nvkm_control_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c new file mode 100644 index 000000000000..82b38d7e9730 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -0,0 +1,358 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +gf100_identify(struct nvkm_device *device) +{ + switch (device->chipset) { + case 0xc0: + device->cname = "GF100"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc4: + device->cname = "GF104"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc3: + device->cname = "GF106"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xce: + device->cname = "GF114"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xcf: + device->cname = "GF116"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc1: + device->cname = "GF108"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc8: + device->cname = "GF110"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xd9: + device->cname = "GF119"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xd7: + device->cname = "GF117"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + default: + nv_fatal(device, "unknown Fermi chipset\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c new file mode 100644 index 000000000000..bf5893458a47 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -0,0 +1,326 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +gk104_identify(struct nvkm_device *device) +{ + switch (device->chipset) { + case 0xe4: + device->cname = "GK104"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + break; + case 0xe7: + device->cname = "GK107"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + break; + case 0xe6: + device->cname = "GK106"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + break; + case 0xea: + device->cname = "GK20A"; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; + break; + case 0xf0: + device->cname = "GK110"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; + break; + case 0xf1: + device->cname = "GK110B"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; + break; + case 0x106: + device->cname = "GK208B"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + break; + case 0x108: + device->cname = "GK208"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + break; + default: + nv_fatal(device, "unknown Kepler chipset\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index ffa2da42f397..539561ed3281 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -42,7 +43,6 @@ #include #include -#include #include #include #include @@ -56,12 +56,12 @@ #include int -gm100_identify(struct nouveau_device *device) +gm100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x117: device->cname = "GM107"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; @@ -101,7 +101,7 @@ gm100_identify(struct nouveau_device *device) break; case 0x124: device->cname = "GM204"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 1d409af560da..5a2ae043b478 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -33,7 +34,6 @@ #include #include -#include #include #include #include @@ -41,12 +41,12 @@ #include int -nv04_identify(struct nouveau_device *device) +nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: device->cname = "NV04"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; @@ -64,7 +64,7 @@ nv04_identify(struct nouveau_device *device) break; case 0x05: device->cname = "NV05"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 66d8c338ae98..94a1ca45e94a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -34,7 +35,6 @@ #include #include -#include #include #include #include @@ -42,12 +42,12 @@ #include int -nv10_identify(struct nouveau_device *device) +nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: device->cname = "NV10"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -64,7 +64,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x15: device->cname = "NV15"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -83,7 +83,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x16: device->cname = "NV16"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -102,7 +102,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x1a: device->cname = "nForce"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -121,7 +121,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x11: device->cname = "NV11"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -140,7 +140,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x17: device->cname = "NV17"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -159,7 +159,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x1f: device->cname = "nForce2"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -178,7 +178,7 @@ nv10_identify(struct nouveau_device *device) break; case 0x18: device->cname = "NV18"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index 59cefdd46897..d5ec8937df68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -35,7 +36,6 @@ #include #include -#include #include #include #include @@ -43,12 +43,12 @@ #include int -nv20_identify(struct nouveau_device *device) +nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: device->cname = "NV20"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -67,7 +67,7 @@ nv20_identify(struct nouveau_device *device) break; case 0x25: device->cname = "NV25"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -86,7 +86,7 @@ nv20_identify(struct nouveau_device *device) break; case 0x28: device->cname = "NV28"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -105,7 +105,7 @@ nv20_identify(struct nouveau_device *device) break; case 0x2a: device->cname = "NV2A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index dfb610f837b0..dda09621e898 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -34,7 +35,6 @@ #include #include -#include #include #include #include @@ -43,12 +43,12 @@ #include int -nv30_identify(struct nouveau_device *device) +nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: device->cname = "NV30"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -67,7 +67,7 @@ nv30_identify(struct nouveau_device *device) break; case 0x35: device->cname = "NV35"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -86,7 +86,7 @@ nv30_identify(struct nouveau_device *device) break; case 0x31: device->cname = "NV31"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -106,7 +106,7 @@ nv30_identify(struct nouveau_device *device) break; case 0x36: device->cname = "NV36"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -126,7 +126,7 @@ nv30_identify(struct nouveau_device *device) break; case 0x34: device->cname = "NV34"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 7bdb7d6729b7..c6301361d14f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -37,7 +38,6 @@ #include #include -#include #include #include #include @@ -47,12 +47,12 @@ #include int -nv40_identify(struct nouveau_device *device) +nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: device->cname = "NV40"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -75,7 +75,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x41: device->cname = "NV41"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -98,7 +98,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x42: device->cname = "NV42"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -121,7 +121,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x43: device->cname = "NV43"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -144,7 +144,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x45: device->cname = "NV45"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -167,7 +167,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x47: device->cname = "G70"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -190,7 +190,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x49: device->cname = "G71"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -213,7 +213,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x4b: device->cname = "G73"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -236,7 +236,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x44: device->cname = "NV44"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -259,7 +259,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x46: device->cname = "G72"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -282,7 +282,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x4a: device->cname = "NV44A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -305,7 +305,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x4c: device->cname = "C61"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -328,7 +328,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x4e: device->cname = "C51"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -351,7 +351,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x63: device->cname = "C73"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -374,7 +374,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x67: device->cname = "C67"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; @@ -397,7 +397,7 @@ nv40_identify(struct nouveau_device *device) break; case 0x68: device->cname = "C68"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 36944babbb53..249b84454612 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -21,6 +21,7 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include #include @@ -40,7 +41,6 @@ #include #include -#include #include #include #include @@ -58,12 +58,12 @@ #include int -nv50_identify(struct nouveau_device *device) +nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: device->cname = "G80"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -89,7 +89,7 @@ nv50_identify(struct nouveau_device *device) break; case 0x84: device->cname = "G84"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -118,7 +118,7 @@ nv50_identify(struct nouveau_device *device) break; case 0x86: device->cname = "G86"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -147,7 +147,7 @@ nv50_identify(struct nouveau_device *device) break; case 0x92: device->cname = "G92"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -176,7 +176,7 @@ nv50_identify(struct nouveau_device *device) break; case 0x94: device->cname = "G94"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -205,7 +205,7 @@ nv50_identify(struct nouveau_device *device) break; case 0x96: device->cname = "G96"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -234,7 +234,7 @@ nv50_identify(struct nouveau_device *device) break; case 0x98: device->cname = "G98"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -263,7 +263,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xa0: device->cname = "G200"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -292,7 +292,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xaa: device->cname = "MCP77/MCP78"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -321,7 +321,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xac: device->cname = "MCP79/MCP7A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -350,7 +350,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xa3: device->cname = "GT215"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -381,7 +381,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xa5: device->cname = "GT216"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -411,7 +411,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xa8: device->cname = "GT218"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; @@ -441,7 +441,7 @@ nv50_identify(struct nouveau_device *device) break; case 0xaf: device->cname = "MCP89"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c deleted file mode 100644 index 887ec05d0c3c..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int -nvc0_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0xc0: - device->cname = "GF100"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xc4: - device->cname = "GF104"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xc3: - device->cname = "GF106"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xce: - device->cname = "GF114"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xcf: - device->cname = "GF116"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xc1: - device->cname = "GF108"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xc8: - device->cname = "GF110"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xd9: - device->cname = "GF119"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - case 0xd7: - device->cname = "GF117"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; - break; - default: - nv_fatal(device, "unknown Fermi chipset\n"); - return -EINVAL; - } - - return 0; - } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c deleted file mode 100644 index faaf87b462a6..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int -nve0_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0xe4: - device->cname = "GK104"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; - break; - case 0xe7: - device->cname = "GK107"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; - break; - case 0xe6: - device->cname = "GK106"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; - break; - case 0xea: - device->cname = "GK20A"; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; - break; - case 0xf0: - device->cname = "GK110"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; - break; - case 0xf1: - device->cname = "GK110B"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; - break; - case 0x106: - device->cname = "GK208B"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - break; - case 0x108: - device->cname = "GK208"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - break; - default: - nv_fatal(device, "unknown Kepler chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index 035fd5b9cfc3..8d3590e7bd87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -1,8 +1,16 @@ #ifndef __NVKM_DEVICE_PRIV_H__ #define __NVKM_DEVICE_PRIV_H__ +#include -#include - -extern struct nouveau_oclass nouveau_control_oclass[]; +extern struct nvkm_oclass nvkm_control_oclass[]; +int nv04_identify(struct nvkm_device *); +int nv10_identify(struct nvkm_device *); +int nv20_identify(struct nvkm_device *); +int nv30_identify(struct nvkm_device *); +int nv40_identify(struct nvkm_device *); +int nv50_identify(struct nvkm_device *); +int gf100_identify(struct nvkm_device *); +int gk104_identify(struct nvkm_device *); +int gm100_identify(struct nvkm_device *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index 131619bda22f..d852bd6de571 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -1,7 +1,8 @@ #ifndef __NV40_GR_H__ #define __NV40_GR_H__ #include -#include + +#include struct nvkm_gpuobj; /* returns 1 if device is one of the nv4x using the 0x4497 object class, -- cgit v1.2.3-59-g8ed1b