From 4e484e7dc5856ff5086b6329d82e36d4adaf1f02 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 16 Jun 2009 17:29:06 +0200 Subject: radeon: Fix CP byte order on big endian architectures with KMS. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_reg.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/radeon/radeon_reg.h') diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 6d3d90406a24..e1b618574461 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -3184,6 +3184,7 @@ # define RADEON_RB_BUFSZ_MASK (0x3f << 0) # define RADEON_RB_BLKSZ_SHIFT 8 # define RADEON_RB_BLKSZ_MASK (0x3f << 8) +# define RADEON_BUF_SWAP_32BIT (1 << 17) # define RADEON_MAX_FETCH_SHIFT 18 # define RADEON_MAX_FETCH_MASK (0x3 << 18) # define RADEON_RB_NO_UPDATE (1 << 27) -- cgit v1.2.3-59-g8ed1b