From 6475a7cce61967fca4dd793b60acf5a7dc70bc9a Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 17 Feb 2017 13:57:30 +1100 Subject: drm/ast: Fix calculation of MCLK Some braces were missing causing an incorrect calculation. Y.C. Chen from Aspeed provided me with the right formula which I tested on AST2400 and 2500. The MCLK isn't currently used by the driver (it will eventually to filter modes) so the issue isn't catastrophic. Also make the printed value a bit more meaningful Signed-off-by: Benjamin Herrenschmidt Acked-by: Joel Stanley Tested-by: Y.C. Chen Signed-off-by: Dave Airlie --- drivers/gpu/drm/ast/ast_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 29ab2c11db41..fd167008be31 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -354,7 +354,7 @@ static int ast_get_dram_info(struct drm_device *dev) div = 0x1; break; } - ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000); + ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); return 0; } @@ -498,7 +498,9 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) if (ret) goto out_free; ast->vram_size = ast_get_vram_info(dev); - DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); + DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", + ast->mclk, ast->dram_type, + ast->dram_bus_width, ast->vram_size); } if (need_post) -- cgit v1.2.3-59-g8ed1b