From cc5454490b514a87ccf99fce7ee224cc95980d99 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Apr 2015 09:25:36 -0600 Subject: coresight: etb10: Print size of buffer we fail to allocate When we initialise the ETB driver we attempt to allocate a buffer suitable for storing the data buffered in the hardware based on sizing information reported by the hardware. Unfortunately if the hardware is not properly configured (for example if power domains are not set up correctly) then we may read back a nonsensically large value and therefore the allocation will be too big to succeed. Print an error message showing the amount of memory we tried to allocate if the buffer allocation fails to help users diagnose such problems. Normally it is bad practice to print an error message on memory allocation failures since there are verbose core messages reported for this but in this case where the allocation size might be incorrect it is a useful hint. Signed-off-by: Mark Brown Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-etb10.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/hwtracing/coresight/coresight-etb10.c') diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 40049869aecd..46eb9f88a29f 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -462,8 +462,11 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) drvdata->buf = devm_kzalloc(dev, drvdata->buffer_depth * 4, GFP_KERNEL); - if (!drvdata->buf) + if (!drvdata->buf) { + dev_err(dev, "Failed to allocate %u bytes for buffer data\n", + drvdata->buffer_depth * 4); return -ENOMEM; + } desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); if (!desc) -- cgit v1.2.3-59-g8ed1b From f5da7cb24b78f2398c80a3ba25438602a68fc3e4 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Apr 2015 09:25:37 -0600 Subject: coresight: etb10: Fix check for bogus buffer depth We attempt to sanity check the buffer depth reported by the hardware by making sure it is not less than zero however this check will never be true since the buffer depth is stored in an unsigned integer. Instead change the check to look for the top bit being set which was the intention. Signed-off-by: Mark Brown Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-etb10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/hwtracing/coresight/coresight-etb10.c') diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 46eb9f88a29f..2a77d83130e6 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -457,7 +457,7 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) drvdata->buffer_depth = etb_get_buffer_depth(drvdata); clk_disable_unprepare(drvdata->clk); - if (drvdata->buffer_depth < 0) + if (drvdata->buffer_depth & 0x80000000) return -EINVAL; drvdata->buf = devm_kzalloc(dev, -- cgit v1.2.3-59-g8ed1b From 1b19f59dca70d802cee8a7d324c2340fdf0bd258 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 May 2015 10:55:11 -0600 Subject: coresight: etb: let runtime PM handle core clock This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-etb10.c | 35 +++++++-------------------- 1 file changed, 9 insertions(+), 26 deletions(-) (limited to 'drivers/hwtracing/coresight/coresight-etb10.c') diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 2a77d83130e6..df306aef4360 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -68,7 +68,6 @@ * @dev: the device entity associated to this component. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.etb" entry. - * @clk: the clock this component is associated to. * @spinlock: only one at a time pls. * @in_use: synchronise user space access to etb buffer. * @buf: area of memory where ETB buffer content gets sent. @@ -81,7 +80,6 @@ struct etb_drvdata { struct device *dev; struct coresight_device *csdev; struct miscdevice miscdev; - struct clk *clk; spinlock_t spinlock; atomic_t in_use; u8 *buf; @@ -92,17 +90,14 @@ struct etb_drvdata { static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { - int ret; u32 depth = 0; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(drvdata->dev); /* RO registers don't need locking */ depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); return depth; } @@ -137,12 +132,9 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - int ret; unsigned long flags; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); etb_enable_hw(drvdata); @@ -252,7 +244,7 @@ static void etb_disable(struct coresight_device *csdev) drvdata->enable = false; spin_unlock_irqrestore(&drvdata->spinlock, flags); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); dev_info(drvdata->dev, "ETB disabled\n"); } @@ -339,16 +331,12 @@ static const struct file_operations etb_fops = { static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { - int ret; unsigned long flags; u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = clk_prepare_enable(drvdata->clk); - if (ret) - goto out; - + pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); @@ -364,7 +352,7 @@ static ssize_t status_show(struct device *dev, CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); return sprintf(buf, "Depth:\t\t0x%x\n" @@ -377,7 +365,7 @@ static ssize_t status_show(struct device *dev, "Flush ctrl:\t0x%x\n", etb_rdr, etb_sr, etb_rrp, etb_rwp, etb_trg, etb_cr, etb_ffsr, etb_ffcr); -out: + return -EINVAL; } static DEVICE_ATTR_RO(status); @@ -449,13 +437,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); - drvdata->clk = adev->pclk; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; - drvdata->buffer_depth = etb_get_buffer_depth(drvdata); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(&adev->dev); if (drvdata->buffer_depth & 0x80000000) return -EINVAL; -- cgit v1.2.3-59-g8ed1b From 267b2c2358255ab7e709079fbe46f518d73df3a2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 May 2015 10:55:16 -0600 Subject: coresight: etb: retrieve and handle atclk As can be seen from the datasheet of the CoreSight Components, DDI0314 table A-8 the ETB has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks. The ATCLK is enabled and disabled using the runtime PM callbacks. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-etb10.c | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers/hwtracing/coresight/coresight-etb10.c') diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index df306aef4360..77d0f9c1118d 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "coresight-priv.h" @@ -66,6 +67,7 @@ * struct etb_drvdata - specifics associated to an ETB component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. + * @atclk: optional clock for the core parts of the ETB. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @spinlock: only one at a time pls. @@ -78,6 +80,7 @@ struct etb_drvdata { void __iomem *base; struct device *dev; + struct clk *atclk; struct coresight_device *csdev; struct miscdevice miscdev; spinlock_t spinlock; @@ -426,6 +429,12 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return -ENOMEM; drvdata->dev = &adev->dev; + drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ + if (!IS_ERR(drvdata->atclk)) { + ret = clk_prepare_enable(drvdata->atclk); + if (ret) + return ret; + } dev_set_drvdata(dev, drvdata); /* validity for the resource is already checked by the AMBA core */ @@ -489,6 +498,32 @@ static int etb_remove(struct amba_device *adev) return 0; } +#ifdef CONFIG_PM +static int etb_runtime_suspend(struct device *dev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_disable_unprepare(drvdata->atclk); + + return 0; +} + +static int etb_runtime_resume(struct device *dev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_prepare_enable(drvdata->atclk); + + return 0; +} +#endif + +static const struct dev_pm_ops etb_dev_pm_ops = { + SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) +}; + static struct amba_id etb_ids[] = { { .id = 0x0003b907, @@ -501,6 +536,8 @@ static struct amba_driver etb_driver = { .drv = { .name = "coresight-etb10", .owner = THIS_MODULE, + .pm = &etb_dev_pm_ops, + }, .probe = etb_probe, .remove = etb_remove, -- cgit v1.2.3-59-g8ed1b