From e9c091b47409255cefa1672041479d850b7b991a Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 4 Jan 2006 16:24:05 +0000 Subject: [MMC] mmci: add data cache coherency Since MMCI currently uses PIO to read data, we have to take steps to ensure data cache coherency on aliasing CPU caches. Add the necessary flush_dcache_page() calls. Signed-off-by: Russell King --- drivers/mmc/mmci.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/mmc') diff --git a/drivers/mmc/mmci.c b/drivers/mmc/mmci.c index 166c9b0ad04e..6d161c70014a 100644 --- a/drivers/mmc/mmci.c +++ b/drivers/mmc/mmci.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -157,6 +158,13 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) data->error = MMC_ERR_FIFO; status |= MCI_DATAEND; + + /* + * We hit an error condition. Ensure that any data + * partially written to a page is properly coherent. + */ + if (host->sg_len && data->flags & MMC_DATA_READ) + flush_dcache_page(host->sg_ptr->page); } if (status & MCI_DATAEND) { mmci_stop_data(host); @@ -301,6 +309,13 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs) if (remain) break; + /* + * If we were reading, and we have completed this + * page, ensure that the data cache is coherent. + */ + if (status & MCI_RXACTIVE) + flush_dcache_page(host->sg_ptr->page); + if (!mmci_next_sg(host)) break; -- cgit v1.2.3-59-g8ed1b