From ebe22ed960024385d935620910c1dd9d2c36bf23 Mon Sep 17 00:00:00 2001 From: "Huang, Xiong" Date: Wed, 18 Apr 2012 22:01:29 +0000 Subject: atl1c: refine atl1c_pcie_patch bit PCIE_PHYMISC_FORCE_RCV_DET is only for l1c&l2c to fix WoL issue, other chips set bit5 of REG_MASTER_CTRL --- this way could save more power than the former, and the bit should be kept all time. l2cb 1.x has special setting for L0S/L1 l2cb 1.x & l1d 1.x should clear Vendor Message on some platforms, otherwise it will cause the root complex hang. Signed-off-by: xiong Tested-by: Liu David Signed-off-by: David S. Miller --- drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'drivers/net/ethernet/atheros/atl1c/atl1c_hw.h') diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h index 5e49ea28d33b..59051e71068f 100644 --- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h @@ -96,17 +96,24 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw); #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 #define REG_PCIE_PHYMISC 0x1000 -#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 +#define PCIE_PHYMISC_FORCE_RCV_DET BIT(2) +#define PCIE_PHYMISC_NFTS_MASK 0xFFUL +#define PCIE_PHYMISC_NFTS_SHIFT 16 #define REG_PCIE_PHYMISC2 0x1004 -#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x3 -#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 -#define PCIE_PHYMISC2_SERDES_TH_MASK 0x3 -#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 +#define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL +#define PCIE_PHYMISC2_L0S_TH_SHIFT 18 +#define L2CB1_PCIE_PHYMISC2_L0S_TH 3 +#define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL +#define PCIE_PHYMISC2_CDR_BW_SHIFT 16 +#define L2CB1_PCIE_PHYMISC2_CDR_BW 3 #define REG_TWSI_DEBUG 0x1108 #define TWSI_DEBUG_DEV_EXIST 0x20000000 +#define REG_DMA_DBG 0x1114 +#define DMA_DBG_VENDOR_MSG BIT(0) + #define REG_EEPROM_CTRL 0x12C0 #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF #define EEPROM_CTRL_DATA_HI_SHIFT 0 -- cgit v1.2.3-59-g8ed1b