From 43b3cf6634a4ae2eac3b6f08019db8f19a114811 Mon Sep 17 00:00:00 2001 From: Iyappan Subramanian Date: Mon, 25 Jul 2016 17:12:40 -0700 Subject: drivers: net: phy: xgene: Add MDIO driver Currently, SGMII based 1G rely on the hardware registers for link state and sometimes it's not reliable. To get most accurate link state, this interface has to use the MDIO bus to poll the PHY. In X-Gene SoC, MDIO bus is shared across RGMII and SGMII based 1G interfaces, so adding this driver to manage MDIO bus. This driver registers the mdio bus and registers the PHYs connected to it. Signed-off-by: Iyappan Subramanian Tested-by: Fushen Chen Tested-by: Toan Le Signed-off-by: David S. Miller --- drivers/net/phy/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/net/phy/Kconfig') diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 1d7b208b1629..47a64342cc16 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -301,6 +301,12 @@ config MDIO_HISI_FEMAC This module provides a driver for the MDIO busses found in the Hisilicon SoC that have an Fast Ethernet MAC. +config MDIO_XGENE + tristate "APM X-Gene SoC MDIO bus controller" + help + This module provides a driver for the MDIO busses found in the + APM X-Gene SoC's. + endif # PHYLIB config MICREL_KS8995MA -- cgit v1.2.3-59-g8ed1b