From 2d649d972bae50199a498f46b945ef8fd78cad5a Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 9 Nov 2018 00:32:43 +0530 Subject: platform/x86: intel_pmc_core: Fix LTR IGNORE Max offset Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint PCH so make the LTR ignore platform specific. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/platform/x86/intel_pmc_core.h') diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index fcb13ca1f2bd..e57b26cdb442 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -35,7 +35,7 @@ #define SPT_PMC_READ_DISABLE_BIT 0x16 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 #define NUM_RETRIES 100 -#define NUM_IP_IGN_ALLOWED 17 +#define SPT_NUM_IP_IGN_ALLOWED 17 #define SPT_PMC_LTR_CUR_PLT 0x350 #define SPT_PMC_LTR_CUR_ASLT 0x354 @@ -146,6 +146,7 @@ enum ppfear_regs { #define CNP_PMC_MMIO_REG_LEN 0x2000 #define CNP_PPFEAR_NUM_ENTRIES 8 #define CNP_PMC_READ_DISABLE_BIT 22 +#define CNP_NUM_IP_IGN_ALLOWED 19 #define CNP_PMC_LTR_CUR_PLT 0x1B50 #define CNP_PMC_LTR_CUR_ASLT 0x1B54 #define CNP_PMC_LTR_SPA 0x1B60 @@ -208,6 +209,7 @@ struct pmc_reg_map { const u32 pm_cfg_offset; const int pm_read_disable_bit; const u32 slps0_dbg_offset; + const u32 ltr_ignore_max; }; /** -- cgit v1.2.3-59-g8ed1b