From 1a2f25d5e73f4f1ae985801a05ed37bbe0ea11f3 Mon Sep 17 00:00:00 2001 From: Qipeng Zha Date: Thu, 18 Feb 2016 02:03:37 +0800 Subject: intel_pmc_ipc: Fix GCR register base address and length GCR register (pmc_cfg register) is at offset 0x1008, and remapping of 0x4 bytes is enough. Signed-off-by: Francois-Nicolas Muller Signed-off-by: Qipeng Zha Acked-by: Andy Shevchenko Signed-off-by: Darren Hart --- drivers/platform/x86/intel_pmc_ipc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_ipc.c') diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index 092519e37de6..3b0182c189d6 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -67,7 +67,8 @@ /* exported resources from IFWI */ #define PLAT_RESOURCE_IPC_INDEX 0 #define PLAT_RESOURCE_IPC_SIZE 0x1000 -#define PLAT_RESOURCE_GCR_SIZE 0x1000 +#define PLAT_RESOURCE_GCR_OFFSET 0x1008 +#define PLAT_RESOURCE_GCR_SIZE 0x4 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3 @@ -766,7 +767,7 @@ static int ipc_plat_get_res(struct platform_device *pdev) } ipcdev.ipc_base = addr; - ipcdev.gcr_base = res->start + size; + ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET; ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; dev_info(&pdev->dev, "ipc res: %pR\n", res); -- cgit v1.2.3-59-g8ed1b