From bea307c16a3a297f87c7ab9a54de686da2afbad5 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Mar 2016 23:33:34 +0100 Subject: pwm: img: Test clock rate to avoid division by 0 The clk API may return 0 on clk_get_rate(), so we should check the result before using it as a divisor. Signed-off-by: Wolfram Sang Signed-off-by: Thierry Reding --- drivers/pwm/pwm-img.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-img.c b/drivers/pwm/pwm-img.c index 8a029f9bc18c..2fb30deee345 100644 --- a/drivers/pwm/pwm-img.c +++ b/drivers/pwm/pwm-img.c @@ -237,6 +237,11 @@ static int img_pwm_probe(struct platform_device *pdev) } clk_rate = clk_get_rate(pwm->pwm_clk); + if (!clk_rate) { + dev_err(&pdev->dev, "pwm clock has no frequency\n"); + ret = -EINVAL; + goto disable_pwmclk; + } /* The maximum input clock divider is 512 */ val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase; -- cgit v1.2.3-59-g8ed1b