From 302e8dcc3f78261f7f8fdd3baa452944c515a219 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 27 Feb 2018 22:44:55 +0100 Subject: serial: imx: Rename register fields to match newer reference manuals MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only the reference manual for the i.MX1 (I have MC9328MX1RM/D Rev 5 from 2004) uses TDMAEN and RDMAEN for these. All reference manuals for the newer chips use TXDMAEN and RXDMAEN. Update to the newer name with the assumption that most imx users don't use an imx1 any more. Signed-off-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/imx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/tty') diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 78bacd020221..dd763f349890 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -71,12 +71,12 @@ #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ #define UCR1_IREN (1<<7) /* Infrared interface enable */ #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ #define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ #define UCR1_DOZE (1<<1) /* Doze */ @@ -441,7 +441,7 @@ static inline void imx_transmit_buffer(struct imx_port *sport) temp = readl(sport->port.membase + UCR1); temp &= ~UCR1_TXMPTYEN; if (sport->dma_is_txing) { - temp |= UCR1_TDMAEN; + temp |= UCR1_TXDMAEN; writel(temp, sport->port.membase + UCR1); } else { writel(temp, sport->port.membase + UCR1); @@ -481,7 +481,7 @@ static void dma_tx_callback(void *data) dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); temp = readl(sport->port.membase + UCR1); - temp &= ~UCR1_TDMAEN; + temp &= ~UCR1_TXDMAEN; writel(temp, sport->port.membase + UCR1); /* update the stat */ @@ -547,7 +547,7 @@ static void imx_dma_tx(struct imx_port *sport) uart_circ_chars_pending(xmit)); temp = readl(sport->port.membase + UCR1); - temp |= UCR1_TDMAEN; + temp |= UCR1_TXDMAEN; writel(temp, sport->port.membase + UCR1); /* fire it */ @@ -591,7 +591,7 @@ static void imx_start_tx(struct uart_port *port) /* We have X-char to send, so enable TX IRQ and * disable TX DMA to let TX interrupt to send X-char */ temp = readl(sport->port.membase + UCR1); - temp &= ~UCR1_TDMAEN; + temp &= ~UCR1_TXDMAEN; temp |= UCR1_TXMPTYEN; writel(temp, sport->port.membase + UCR1); return; @@ -1177,7 +1177,7 @@ static void imx_enable_dma(struct imx_port *sport) /* set UCR1 */ temp = readl(sport->port.membase + UCR1); - temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; + temp |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; writel(temp, sport->port.membase + UCR1); imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); @@ -1191,7 +1191,7 @@ static void imx_disable_dma(struct imx_port *sport) /* clear UCR1 */ temp = readl(sport->port.membase + UCR1); - temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); + temp &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); writel(temp, sport->port.membase + UCR1); /* clear UCR2 */ @@ -1380,7 +1380,7 @@ static void imx_flush_buffer(struct uart_port *port) dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); temp = readl(sport->port.membase + UCR1); - temp &= ~UCR1_TDMAEN; + temp &= ~UCR1_TXDMAEN; writel(temp, sport->port.membase + UCR1); sport->dma_is_txing = 0; } -- cgit v1.2.3-59-g8ed1b