From 75c66b6db7baacf592268d5d5c4c9ecb6e2bcae7 Mon Sep 17 00:00:00 2001 From: Dmitry Kalinkin Date: Thu, 28 May 2015 15:07:01 +0300 Subject: vme: stop DMA transfer on interruption Signed-off-by: Dmitry Kalinkin Cc: Igor Alekseev Signed-off-by: Greg Kroah-Hartman --- drivers/vme/bridges/vme_ca91cx42.c | 17 ++++++++++++++--- drivers/vme/bridges/vme_tsi148.c | 15 +++++++++++++-- 2 files changed, 27 insertions(+), 5 deletions(-) (limited to 'drivers/vme') diff --git a/drivers/vme/bridges/vme_ca91cx42.c b/drivers/vme/bridges/vme_ca91cx42.c index 18078ecbfcc6..e9bd65723134 100644 --- a/drivers/vme/bridges/vme_ca91cx42.c +++ b/drivers/vme/bridges/vme_ca91cx42.c @@ -1192,7 +1192,7 @@ static int ca91cx42_dma_list_exec(struct vme_dma_list *list) { struct vme_dma_resource *ctrlr; struct ca91cx42_dma_entry *entry; - int retval = 0; + int retval; dma_addr_t bus_addr; u32 val; struct device *dev; @@ -1245,8 +1245,18 @@ static int ca91cx42_dma_list_exec(struct vme_dma_list *list) iowrite32(val, bridge->base + DGCS); - wait_event_interruptible(bridge->dma_queue, - ca91cx42_dma_busy(ctrlr->parent)); + retval = wait_event_interruptible(bridge->dma_queue, + ca91cx42_dma_busy(ctrlr->parent)); + + if (retval) { + val = ioread32(bridge->base + DGCS); + iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); + /* Wait for the operation to abort */ + wait_event(bridge->dma_queue, + ca91cx42_dma_busy(ctrlr->parent)); + retval = -EINTR; + goto exit; + } /* * Read status register, this register is valid until we kick off a @@ -1261,6 +1271,7 @@ static int ca91cx42_dma_list_exec(struct vme_dma_list *list) val = ioread32(bridge->base + DCTL); } +exit: /* Remove list from running list */ mutex_lock(&ctrlr->mtx); list_del(&list->list); diff --git a/drivers/vme/bridges/vme_tsi148.c b/drivers/vme/bridges/vme_tsi148.c index 65623481b84c..fb1e7ad272ec 100644 --- a/drivers/vme/bridges/vme_tsi148.c +++ b/drivers/vme/bridges/vme_tsi148.c @@ -1892,7 +1892,7 @@ static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) static int tsi148_dma_list_exec(struct vme_dma_list *list) { struct vme_dma_resource *ctrlr; - int channel, retval = 0; + int channel, retval; struct tsi148_dma_entry *entry; u32 bus_addr_high, bus_addr_low; u32 val, dctlreg = 0; @@ -1942,9 +1942,19 @@ static int tsi148_dma_list_exec(struct vme_dma_list *list) iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); - wait_event_interruptible(bridge->dma_queue[channel], + retval = wait_event_interruptible(bridge->dma_queue[channel], tsi148_dma_busy(ctrlr->parent, channel)); + if (retval) { + iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base + + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); + /* Wait for the operation to abort */ + wait_event(bridge->dma_queue[channel], + tsi148_dma_busy(ctrlr->parent, channel)); + retval = -EINTR; + goto exit; + } + /* * Read status register, this register is valid until we kick off a * new transfer. @@ -1957,6 +1967,7 @@ static int tsi148_dma_list_exec(struct vme_dma_list *list) retval = -EIO; } +exit: /* Remove list from running list */ mutex_lock(&ctrlr->mtx); list_del(&list->list); -- cgit v1.2.3-59-g8ed1b