From 1ab7ef158dfbaf6314b6660a3e3fb037cba2a1ca Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 13 Jun 2012 09:04:03 +0800 Subject: gpio/mxc: move irq_domain_add_legacy call into gpio driver Move irq_domain_add_legacy call from imx*-dt.c into gpio driver and have the gpio driver adopt irqdomain support for both DT and non-DT boot. With all imx platform code converted from static gpio irq number computation to use run-time gpio_to_irq call, we can now use irq_alloc_descs and irqdomain support to dynamically get irq_base and have the mapping between gpio and irq number available without using virtual_irq_start and MXC_GPIO_IRQ_START. Signed-off-by: Shawn Guo Cc: Grant Likely Acked-by: Sascha Hauer Acked-by: Dong Aisheng --- drivers/gpio/gpio-mxc.c | 56 ++++++++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c337143b18f8..e5db670d0002 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -33,8 +34,6 @@ #include #include -#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) - enum mxc_gpio_hwtype { IMX1_GPIO, /* runs on i.mx1 */ IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ @@ -61,7 +60,7 @@ struct mxc_gpio_port { void __iomem *base; int irq; int irq_high; - int virtual_irq_start; + struct irq_domain *domain; struct bgpio_chip bgc; u32 both_edges; }; @@ -144,14 +143,15 @@ static LIST_HEAD(mxc_gpio_ports); static int gpio_set_irq_type(struct irq_data *d, u32 type) { - u32 gpio = irq_to_gpio(d->irq); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; u32 bit, val; + u32 gpio_idx = d->hwirq; + u32 gpio = port->bgc.gc.base + gpio_idx; int edge; void __iomem *reg = port->base; - port->both_edges &= ~(1 << (gpio & 31)); + port->both_edges &= ~(1 << gpio_idx); switch (type) { case IRQ_TYPE_EDGE_RISING: edge = GPIO_INT_RISE_EDGE; @@ -168,7 +168,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) edge = GPIO_INT_HIGH_LEV; pr_debug("mxc: set GPIO %d to high trigger\n", gpio); } - port->both_edges |= 1 << (gpio & 31); + port->both_edges |= 1 << gpio_idx; break; case IRQ_TYPE_LEVEL_LOW: edge = GPIO_INT_LOW_LEV; @@ -180,11 +180,11 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) return -EINVAL; } - reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ - bit = gpio & 0xf; + reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* ICR1 or ICR2 */ + bit = gpio_idx & 0xf; val = readl(reg) & ~(0x3 << (bit << 1)); writel(val | (edge << (bit << 1)), reg); - writel(1 << (gpio & 0x1f), port->base + GPIO_ISR); + writel(1 << gpio_idx, port->base + GPIO_ISR); return 0; } @@ -217,15 +217,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) /* handle 32 interrupts in one status register */ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) { - u32 gpio_irq_no_base = port->virtual_irq_start; - while (irq_stat != 0) { int irqoffset = fls(irq_stat) - 1; if (port->both_edges & (1 << irqoffset)) mxc_flip_edge(port, irqoffset); - generic_handle_irq(gpio_irq_no_base + irqoffset); + generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); irq_stat &= ~(1 << irqoffset); } @@ -276,10 +274,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) */ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) { - u32 gpio = irq_to_gpio(d->irq); - u32 gpio_idx = gpio & 0x1F; struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; + u32 gpio_idx = d->hwirq; if (enable) { if (port->irq_high && (gpio_idx >= 16)) @@ -296,12 +293,12 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) return 0; } -static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port) +static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) { struct irq_chip_generic *gc; struct irq_chip_type *ct; - gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start, + gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base, port->base, handle_level_irq); gc->private = port; @@ -352,7 +349,7 @@ static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) struct mxc_gpio_port *port = container_of(bgc, struct mxc_gpio_port, bgc); - return port->virtual_irq_start + offset; + return irq_find_mapping(port->domain, offset); } static int __devinit mxc_gpio_probe(struct platform_device *pdev) @@ -360,6 +357,7 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct mxc_gpio_port *port; struct resource *iores; + int irq_base; int err; mxc_gpio_get_hw(pdev); @@ -430,20 +428,30 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev) if (err) goto out_bgpio_remove; - /* - * In dt case, we use gpio number range dynamically - * allocated by gpio core. - */ - port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base : - pdev->id * 32); + irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id()); + if (irq_base < 0) { + err = irq_base; + goto out_gpiochip_remove; + } + + port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, + &irq_domain_simple_ops, NULL); + if (!port->domain) { + err = -ENODEV; + goto out_irqdesc_free; + } /* gpio-mxc can be a generic irq chip */ - mxc_gpio_init_gc(port); + mxc_gpio_init_gc(port, irq_base); list_add_tail(&port->node, &mxc_gpio_ports); return 0; +out_irqdesc_free: + irq_free_descs(irq_base, 32); +out_gpiochip_remove: + WARN_ON(gpiochip_remove(&port->bgc.gc) < 0); out_bgpio_remove: bgpio_remove(&port->bgc); out_iounmap: -- cgit v1.2.3-59-g8ed1b From 88289c80d419897c03f7f43b35e3730d8fb6825b Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 13 Jun 2012 14:07:31 +0800 Subject: dma: ipu: remove the use of ipu_platform_data The struct ipu_platform_data is used by platform code to pass MXC_IPU_IRQ_START to ipu-core driver. We can save it by having ipu-core driver call irq_alloc_descs to get the irq_base. Signed-off-by: Shawn Guo Acked-by: Vinod Koul Acked-by: Sascha Hauer Acked-by: Dong Aisheng --- arch/arm/mach-imx/devices-imx31.h | 4 ++-- arch/arm/mach-imx/devices-imx35.h | 4 ++-- arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 6 +----- arch/arm/mach-imx/mach-armadillo5x0.c | 6 +----- arch/arm/mach-imx/mach-mx31_3ds.c | 6 +----- arch/arm/mach-imx/mach-mx31moboard.c | 6 +----- arch/arm/mach-imx/mach-mx35_3ds.c | 10 +--------- arch/arm/mach-imx/mach-pcm037.c | 6 +----- arch/arm/mach-imx/mach-pcm043.c | 6 +----- arch/arm/mach-imx/mach-vpr200.c | 6 +----- arch/arm/mach-imx/mx31lilly-db.c | 6 +----- arch/arm/plat-mxc/devices/platform-ipu-core.c | 5 ++--- arch/arm/plat-mxc/include/mach/devices-common.h | 4 +--- arch/arm/plat-mxc/include/mach/ipu.h | 4 ---- drivers/dma/ipu/ipu_idmac.c | 8 +++----- drivers/dma/ipu/ipu_irq.c | 14 +++++++++----- 16 files changed, 28 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index 488e241a6db6..911c2dac2452 100644 --- a/arch/arm/mach-imx/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h @@ -42,8 +42,8 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[]; #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) extern const struct imx_ipu_core_data imx31_ipu_core_data; -#define imx31_add_ipu_core(pdata) \ - imx_add_ipu_core(&imx31_ipu_core_data, pdata) +#define imx31_add_ipu_core() \ + imx_add_ipu_core(&imx31_ipu_core_data) #define imx31_alloc_mx3_camera(pdata) \ imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata) #define imx31_add_mx3_sdc_fb(pdata) \ diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h index 7b99ef0bb501..6fb907290f47 100644 --- a/arch/arm/mach-imx/devices-imx35.h +++ b/arch/arm/mach-imx/devices-imx35.h @@ -50,8 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[]; #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) extern const struct imx_ipu_core_data imx35_ipu_core_data; -#define imx35_add_ipu_core(pdata) \ - imx_add_ipu_core(&imx35_ipu_core_data, pdata) +#define imx35_add_ipu_core() \ + imx_add_ipu_core(&imx35_ipu_core_data) #define imx35_alloc_mx3_camera(pdata) \ imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata) #define imx35_add_mx3_sdc_fb(pdata) \ diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c index 557f6c486053..6e9dd12a6961 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c @@ -95,10 +95,6 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "CMO-QVGA", .mode = fb_modedb, @@ -287,7 +283,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) printk(KERN_ERR "error setting mbimxsd pads !\n"); imx35_add_imx_uart1(&uart_pdata); - imx35_add_ipu_core(&mx3_ipu_data); + imx35_add_ipu_core(); imx35_add_mx3_sdc_fb(&mx3fb_pdata); imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index f83c5c683575..2c6ab3273f9e 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -367,10 +367,6 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "CRT-VGA", .mode = fb_modedb, @@ -517,7 +513,7 @@ static void __init armadillo5x0_init(void) imx31_add_mxc_mmc(0, &sdhc_pdata); /* Register FB */ - imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_ipu_core(); imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* Register NOR Flash */ diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index ecdba0497e7e..618935e1e325 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -274,10 +274,6 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static struct ipu_platform_data mx3_ipu_data = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "Epson-VGA", .mode = fb_modedb, @@ -743,7 +739,7 @@ static void __init mx31_3ds_init(void) imx31_add_mxc_mmc(0, &sdhc1_pdata); imx31_add_spi_imx0(&spi0_pdata); - imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_ipu_core(); imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* CSI */ diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index f0d26db7719e..54d9e5d9fcec 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -473,10 +473,6 @@ static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = { .leds = mx31moboard_leds, }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct platform_device *devices[] __initdata = { &mx31moboard_flash, }; @@ -494,7 +490,7 @@ static int __init mx31moboard_init_cam(void) int dma, ret = -ENOMEM; struct platform_device *pdev; - imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_ipu_core(); pdev = imx31_alloc_mx3_camera(&camera_pdata); if (IS_ERR(pdev)) diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index fa1ea74dfdd3..ad63e6ebee6d 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c @@ -80,10 +80,6 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "Ceramate-CLAA070VC01", .mode = fb_modedb, @@ -297,10 +293,6 @@ err: return ret; } -static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct i2c_board_info mx35_3ds_i2c_camera = { I2C_BOARD_INFO("ov2640", 0x30), }; @@ -596,7 +588,7 @@ static void __init mx35_3ds_init(void) i2c_register_board_info( 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds)); - imx35_add_ipu_core(&mx35_3ds_ipu_data); + imx35_add_ipu_core(); platform_device_register(&mx35_3ds_ov2640); imx35_3ds_init_camera(); diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 551a035f0c2d..ded4ed9def9e 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -441,10 +441,6 @@ static struct platform_device *devices[] __initdata = { &pcm037_mt9v022, }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static const struct fb_videomode fb_modedb[] = { { /* 240x320 @ 60 Hz Sharp */ @@ -648,7 +644,7 @@ static void __init pcm037_init(void) imx31_add_mxc_nand(&pcm037_nand_board_info); imx31_add_mxc_mmc(0, &sdhc_pdata); - imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_ipu_core(); imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* CSI */ diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 73585f55cca0..133908f94f7e 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -76,10 +76,6 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "Sharp-LQ035Q7", .mode = fb_modedb, @@ -376,7 +372,7 @@ static void __init pcm043_init(void) imx35_add_imx_i2c0(&pcm043_i2c0_data); - imx35_add_ipu_core(&mx3_ipu_data); + imx35_add_ipu_core(); imx35_add_mx3_sdc_fb(&mx3fb_pdata); if (otg_mode_host) { diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index e36eb2c40f41..1aa562285960 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -87,10 +87,6 @@ static const struct fb_videomode fb_modedb[] = { } }; -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "PT0708048", .mode = fb_modedb, @@ -290,7 +286,7 @@ static void __init vpr200_board_init(void) imx35_add_imx_uart0(NULL); imx35_add_imx_uart2(NULL); - imx35_add_ipu_core(&mx3_ipu_data); + imx35_add_ipu_core(); imx35_add_mx3_sdc_fb(&mx3fb_pdata); imx35_add_fsl_usb2_udc(&otg_device_pdata); diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c index 2df625bdc71e..29e890f92055 100644 --- a/arch/arm/mach-imx/mx31lilly-db.c +++ b/arch/arm/mach-imx/mx31lilly-db.c @@ -162,10 +162,6 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = { }; /* Framebuffer support */ -static const struct ipu_platform_data ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - static const struct fb_videomode fb_modedb = { /* 640x480 TFT panel (IPS-056T) */ .name = "CRT-VGA", @@ -199,7 +195,7 @@ static void __init mx31lilly_init_fb(void) return; } - imx31_add_ipu_core(&ipu_data); + imx31_add_ipu_core(); imx31_add_mx3_sdc_fb(&fb_pdata); gpio_direction_output(LCD_VCC_EN_GPIO, 1); } diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c index 79d340ae0af1..d1e33cc6f12e 100644 --- a/arch/arm/plat-mxc/devices/platform-ipu-core.c +++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c @@ -30,8 +30,7 @@ const struct imx_ipu_core_data imx35_ipu_core_data __initconst = static struct platform_device *imx_ipu_coredev __initdata; struct platform_device *__init imx_add_ipu_core( - const struct imx_ipu_core_data *data, - const struct ipu_platform_data *pdata) + const struct imx_ipu_core_data *data) { /* The resource order is important! */ struct resource res[] = { @@ -55,7 +54,7 @@ struct platform_device *__init imx_add_ipu_core( }; return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); + res, ARRAY_SIZE(res), NULL, 0); } struct platform_device *__init imx_alloc_mx3_camera( diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 1b2258daa05b..a7f5bb1084d7 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -183,7 +183,6 @@ struct platform_device *__init imx_add_imx_udc( const struct imx_imx_udc_data *data, const struct imxusb_platform_data *pdata); -#include #include #include struct imx_ipu_core_data { @@ -192,8 +191,7 @@ struct imx_ipu_core_data { resource_size_t errirq; }; struct platform_device *__init imx_add_ipu_core( - const struct imx_ipu_core_data *data, - const struct ipu_platform_data *pdata); + const struct imx_ipu_core_data *data); struct platform_device *__init imx_alloc_mx3_camera( const struct imx_ipu_core_data *data, const struct mx3_camera_pdata *pdata); diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h index a9221f1cc1a0..539e559d18b2 100644 --- a/arch/arm/plat-mxc/include/mach/ipu.h +++ b/arch/arm/plat-mxc/include/mach/ipu.h @@ -110,10 +110,6 @@ enum ipu_rotate_mode { IPU_ROTATE_90_LEFT = 7, }; -struct ipu_platform_data { - unsigned int irq_base; -}; - /* * Enumeration of DI ports for ADC. */ diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c index 5ec72044ea4c..c7573e50aa14 100644 --- a/drivers/dma/ipu/ipu_idmac.c +++ b/drivers/dma/ipu/ipu_idmac.c @@ -1663,7 +1663,6 @@ static void __exit ipu_idmac_exit(struct ipu *ipu) static int __init ipu_probe(struct platform_device *pdev) { - struct ipu_platform_data *pdata = pdev->dev.platform_data; struct resource *mem_ipu, *mem_ic; int ret; @@ -1671,7 +1670,7 @@ static int __init ipu_probe(struct platform_device *pdev) mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0); mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!pdata || !mem_ipu || !mem_ic) + if (!mem_ipu || !mem_ic) return -EINVAL; ipu_data.dev = &pdev->dev; @@ -1688,10 +1687,9 @@ static int __init ipu_probe(struct platform_device *pdev) goto err_noirq; ipu_data.irq_err = ret; - ipu_data.irq_base = pdata->irq_base; - dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n", - ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base); + dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n", + ipu_data.irq_fn, ipu_data.irq_err); /* Remap IPU common registers */ ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu)); diff --git a/drivers/dma/ipu/ipu_irq.c b/drivers/dma/ipu/ipu_irq.c index a71f55e72be9..fa95bcc3de1f 100644 --- a/drivers/dma/ipu/ipu_irq.c +++ b/drivers/dma/ipu/ipu_irq.c @@ -14,6 +14,7 @@ #include #include #include +#include #include @@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = { /* Install the IRQ handler */ int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev) { - struct ipu_platform_data *pdata = dev->dev.platform_data; - unsigned int irq, irq_base, i; + unsigned int irq, i; + int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS, + numa_node_id()); - irq_base = pdata->irq_base; + if (irq_base < 0) + return irq_base; for (i = 0; i < IPU_IRQ_NR_BANKS; i++) irq_bank[i].ipu = ipu; @@ -387,15 +390,16 @@ int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev) irq_set_handler_data(ipu->irq_err, ipu); irq_set_chained_handler(ipu->irq_err, ipu_irq_err); + ipu->irq_base = irq_base; + return 0; } void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev) { - struct ipu_platform_data *pdata = dev->dev.platform_data; unsigned int irq, irq_base; - irq_base = pdata->irq_base; + irq_base = ipu->irq_base; irq_set_chained_handler(ipu->irq_fn, NULL); irq_set_handler_data(ipu->irq_fn, NULL); -- cgit v1.2.3-59-g8ed1b From 6387f8fcb6974499c3e179d3b0f369e62969300f Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 14 Jun 2012 11:21:57 +0800 Subject: i2c: imx: remove unneeded mach/irqs.h inclusion Remove unneeded mach/irq.h inclusion from i2c-imx driver. Signed-off-by: Shawn Guo Cc: linux-i2c@vger.kernel.org Acked-by: Wolfram Sang Acked-by: Sascha Hauer Acked-by: Dong Aisheng --- drivers/i2c/busses/i2c-imx.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index 8d6b504d65c4..370031ac8200 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -53,7 +53,6 @@ #include #include -#include #include #include -- cgit v1.2.3-59-g8ed1b From 1ee8f65b5689504b98dacb6641fc8b2cc5618ad4 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 14 Jun 2012 10:58:54 +0800 Subject: tty: serial: imx: remove the use of MXC_INTERNAL_IRQS As the part of the effort to enable SPARE_IRQ for imx platform, the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver has a references to it for a decision on flags of request_irq call based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching on imx platform code tells that rtsirq will never be beyond MXC_INTERNAL_IRQS. That said, the check, consequently the reference to MXC_INTERNAL_IRQS are not needed, so remove them. Signed-off-by: Shawn Guo Cc: linux-serial@vger.kernel.org Acked-by: Greg Kroah-Hartman Acked-by: Sascha Hauer Acked-by: Dong Aisheng --- drivers/tty/serial/imx.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 4ef747307ecb..d5c689d6217e 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -169,7 +169,6 @@ #define SERIAL_IMX_MAJOR 207 #define MINOR_START 16 #define DEV_NAME "ttymxc" -#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS /* * This determines how often we check the modem status signals @@ -741,10 +740,7 @@ static int imx_startup(struct uart_port *port) /* do not use RTS IRQ on IrDA */ if (!USE_IRDA(sport)) { - retval = request_irq(sport->rtsirq, imx_rtsint, - (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : - IRQF_TRIGGER_FALLING | - IRQF_TRIGGER_RISING, + retval = request_irq(sport->rtsirq, imx_rtsint, 0, DRIVER_NAME, sport); if (retval) goto error_out3; -- cgit v1.2.3-59-g8ed1b From 8842a9e2869cae14bbb8184004a42fc3070587fb Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 14 Jun 2012 11:16:14 +0800 Subject: ARM: imx: enable SPARSE_IRQ for imx platform As all irqchips on imx have been changed to allocate their irq_descs, and all unneeded mach/irqs.h inclusions on imx have been cleaned up, now it's time to select SPARSE_IRQ for imx/mxc. The SPARSE_IRQ support forces irqs allocation starting from 16. All those static irq number definition for SoCs need to shift 16 to keep non-DT boot works. With all those static IRQ number and start definitions removed from mach/irqs.h, the header becomes just a container of a couple of mach-imx specific irq/fiq calls. Since mach/irqs.h is not included by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly include mach/irqs.h themselves. Signed-off-by: Shawn Guo Acked-by: Sascha Hauer --- arch/arm/Kconfig | 1 + arch/arm/plat-mxc/include/mach/irqs.h | 44 ------- arch/arm/plat-mxc/include/mach/mx1.h | 111 ++++++++--------- arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++++--------- arch/arm/plat-mxc/include/mach/mx25.h | 72 +++++------ arch/arm/plat-mxc/include/mach/mx27.h | 127 ++++++++++---------- arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++++------- arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++++--------- arch/arm/plat-mxc/include/mach/mx35.h | 109 ++++++++--------- arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++++------ arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++++++--------------- arch/arm/plat-mxc/include/mach/mx51.h | 209 ++++++++++++++++---------------- arch/arm/plat-mxc/include/mach/mx53.h | 217 +++++++++++++++++----------------- drivers/media/video/mx1_camera.c | 1 + sound/soc/fsl/imx-pcm-fiq.c | 1 + 15 files changed, 722 insertions(+), 746 deletions(-) (limited to 'drivers') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 84449dd8f031..63f40b43b062 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -446,6 +446,7 @@ config ARCH_MXC select CLKSRC_MMIO select GENERIC_IRQ_CHIP select MULTI_IRQ_HANDLER + select SPARSE_IRQ help Support for Freescale MXC/iMX-based family of processors diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index fd9efb044656..d73f5e8ea9cb 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,50 +11,6 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ -#include - -/* - * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC - * have 128 IRQs, and those with AVIC have 64. - * - * To support single image, the biggest number should be defined on - * top of the list. - */ -#if defined CONFIG_ARM_GIC -#define MXC_INTERNAL_IRQS 160 -#elif defined CONFIG_MXC_TZIC -#define MXC_INTERNAL_IRQS 128 -#else -#define MXC_INTERNAL_IRQS 64 -#endif - -#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS - -/* - * The next 16 interrupts are for board specific purposes. Since - * the kernel can only run on one machine at a time, we can re-use - * these. If you need more, increase MXC_BOARD_IRQS, but keep it - * within sensible limits. - */ -#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -#define MXC_BOARD_IRQS 80 -#else -#define MXC_BOARD_IRQS 16 -#endif - -#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) - -#ifdef CONFIG_MX3_IPU_IRQS -#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS -#else -#define MX3_IPU_IRQS 0 -#endif -/* REVISIT: Add IPU irqs on IMX51 */ - -#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) - extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); /* all normal IRQs can be FIQs */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 2b7c08d13e89..45bd31cc34d6 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -78,61 +78,62 @@ #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ -#define MX1_INT_SOFTINT 0 -#define MX1_INT_CSI 6 -#define MX1_DSPA_MAC_INT 7 -#define MX1_DSPA_INT 8 -#define MX1_COMP_INT 9 -#define MX1_MSHC_XINT 10 -#define MX1_GPIO_INT_PORTA 11 -#define MX1_GPIO_INT_PORTB 12 -#define MX1_GPIO_INT_PORTC 13 -#define MX1_INT_LCDC 14 -#define MX1_SIM_INT 15 -#define MX1_SIM_DATA_INT 16 -#define MX1_RTC_INT 17 -#define MX1_RTC_SAMINT 18 -#define MX1_INT_UART2PFERR 19 -#define MX1_INT_UART2RTS 20 -#define MX1_INT_UART2DTR 21 -#define MX1_INT_UART2UARTC 22 -#define MX1_INT_UART2TX 23 -#define MX1_INT_UART2RX 24 -#define MX1_INT_UART1PFERR 25 -#define MX1_INT_UART1RTS 26 -#define MX1_INT_UART1DTR 27 -#define MX1_INT_UART1UARTC 28 -#define MX1_INT_UART1TX 29 -#define MX1_INT_UART1RX 30 -#define MX1_VOICE_DAC_INT 31 -#define MX1_VOICE_ADC_INT 32 -#define MX1_PEN_DATA_INT 33 -#define MX1_PWM_INT 34 -#define MX1_SDHC_INT 35 -#define MX1_INT_I2C 39 -#define MX1_INT_CSPI2 40 -#define MX1_INT_CSPI1 41 -#define MX1_SSI_TX_INT 42 -#define MX1_SSI_TX_ERR_INT 43 -#define MX1_SSI_RX_INT 44 -#define MX1_SSI_RX_ERR_INT 45 -#define MX1_TOUCH_INT 46 -#define MX1_INT_USBD0 47 -#define MX1_INT_USBD1 48 -#define MX1_INT_USBD2 49 -#define MX1_INT_USBD3 50 -#define MX1_INT_USBD4 51 -#define MX1_INT_USBD5 52 -#define MX1_INT_USBD6 53 -#define MX1_BTSYS_INT 55 -#define MX1_BTTIM_INT 56 -#define MX1_BTWUI_INT 57 -#define MX1_TIM2_INT 58 -#define MX1_TIM1_INT 59 -#define MX1_DMA_ERR 60 -#define MX1_DMA_INT 61 -#define MX1_GPIO_INT_PORTD 62 -#define MX1_WDT_INT 63 +#include +#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0) +#define MX1_INT_CSI (NR_IRQS_LEGACY + 6) +#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7) +#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8) +#define MX1_COMP_INT (NR_IRQS_LEGACY + 9) +#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10) +#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11) +#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12) +#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13) +#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14) +#define MX1_SIM_INT (NR_IRQS_LEGACY + 15) +#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16) +#define MX1_RTC_INT (NR_IRQS_LEGACY + 17) +#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18) +#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19) +#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20) +#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21) +#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22) +#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23) +#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24) +#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25) +#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26) +#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27) +#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28) +#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29) +#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30) +#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31) +#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32) +#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33) +#define MX1_PWM_INT (NR_IRQS_LEGACY + 34) +#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35) +#define MX1_INT_I2C (NR_IRQS_LEGACY + 39) +#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40) +#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41) +#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42) +#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43) +#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44) +#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45) +#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46) +#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47) +#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48) +#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49) +#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50) +#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51) +#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52) +#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53) +#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55) +#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56) +#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57) +#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58) +#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59) +#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60) +#define MX1_DMA_INT (NR_IRQS_LEGACY + 61) +#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62) +#define MX1_WDT_INT (NR_IRQS_LEGACY + 63) /* DMA */ #define MX1_DMA_REQ_UART3_T 2 diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 6cd049ebbd8d..468738aa997f 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -99,59 +99,60 @@ #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ -#define MX21_INT_CSPI3 6 -#define MX21_INT_GPIO 8 -#define MX21_INT_FIRI 9 -#define MX21_INT_SDHC2 10 -#define MX21_INT_SDHC1 11 -#define MX21_INT_I2C 12 -#define MX21_INT_SSI2 13 -#define MX21_INT_SSI1 14 -#define MX21_INT_CSPI2 15 -#define MX21_INT_CSPI1 16 -#define MX21_INT_UART4 17 -#define MX21_INT_UART3 18 -#define MX21_INT_UART2 19 -#define MX21_INT_UART1 20 -#define MX21_INT_KPP 21 -#define MX21_INT_RTC 22 -#define MX21_INT_PWM 23 -#define MX21_INT_GPT3 24 -#define MX21_INT_GPT2 25 -#define MX21_INT_GPT1 26 -#define MX21_INT_WDOG 27 -#define MX21_INT_PCMCIA 28 -#define MX21_INT_NFC 29 -#define MX21_INT_BMI 30 -#define MX21_INT_CSI 31 -#define MX21_INT_DMACH0 32 -#define MX21_INT_DMACH1 33 -#define MX21_INT_DMACH2 34 -#define MX21_INT_DMACH3 35 -#define MX21_INT_DMACH4 36 -#define MX21_INT_DMACH5 37 -#define MX21_INT_DMACH6 38 -#define MX21_INT_DMACH7 39 -#define MX21_INT_DMACH8 40 -#define MX21_INT_DMACH9 41 -#define MX21_INT_DMACH10 42 -#define MX21_INT_DMACH11 43 -#define MX21_INT_DMACH12 44 -#define MX21_INT_DMACH13 45 -#define MX21_INT_DMACH14 46 -#define MX21_INT_DMACH15 47 -#define MX21_INT_EMMAENC 49 -#define MX21_INT_EMMADEC 50 -#define MX21_INT_EMMAPRP 51 -#define MX21_INT_EMMAPP 52 -#define MX21_INT_USBWKUP 53 -#define MX21_INT_USBDMA 54 -#define MX21_INT_USBHOST 55 -#define MX21_INT_USBFUNC 56 -#define MX21_INT_USBMNP 57 -#define MX21_INT_USBCTRL 58 -#define MX21_INT_SLCDC 60 -#define MX21_INT_LCDC 61 +#include +#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) +#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) +#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) +#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) +#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) +#define MX21_INT_I2C (NR_IRQS_LEGACY + 12) +#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) +#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) +#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) +#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) +#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) +#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) +#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) +#define MX21_INT_KPP (NR_IRQS_LEGACY + 21) +#define MX21_INT_RTC (NR_IRQS_LEGACY + 22) +#define MX21_INT_PWM (NR_IRQS_LEGACY + 23) +#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) +#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) +#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) +#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) +#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) +#define MX21_INT_NFC (NR_IRQS_LEGACY + 29) +#define MX21_INT_BMI (NR_IRQS_LEGACY + 30) +#define MX21_INT_CSI (NR_IRQS_LEGACY + 31) +#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) +#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) +#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) +#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) +#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) +#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) +#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) +#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) +#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) +#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) +#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) +#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) +#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) +#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) +#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) +#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) +#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) +#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) +#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) +#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) +#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) +#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) +#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) +#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) +#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) +#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) +#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) +#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) /* fixed DMA request numbers */ #define MX21_DMA_REQ_CSPI3_RX 1 diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index ccebf5ba12f0..627d94f1b010 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -61,40 +61,44 @@ #define MX25_IO_P2V(x) IMX_IO_P2V(x) #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) -#define MX25_INT_CSPI3 0 -#define MX25_INT_I2C1 3 -#define MX25_INT_I2C2 4 -#define MX25_INT_UART4 5 -#define MX25_INT_ESDHC2 8 -#define MX25_INT_ESDHC1 9 -#define MX25_INT_I2C3 10 -#define MX25_INT_SSI2 11 -#define MX25_INT_SSI1 12 -#define MX25_INT_CSPI2 13 -#define MX25_INT_CSPI1 14 -#define MX25_INT_GPIO3 16 -#define MX25_INT_CSI 17 -#define MX25_INT_UART3 18 -#define MX25_INT_GPIO4 23 -#define MX25_INT_KPP 24 -#define MX25_INT_DRYICE 25 -#define MX25_INT_PWM1 26 -#define MX25_INT_UART2 32 -#define MX25_INT_NFC 33 -#define MX25_INT_SDMA 34 -#define MX25_INT_USB_HS 35 -#define MX25_INT_PWM2 36 -#define MX25_INT_USB_OTG 37 -#define MX25_INT_LCDC 39 -#define MX25_INT_UART5 40 -#define MX25_INT_PWM3 41 -#define MX25_INT_PWM4 42 -#define MX25_INT_CAN1 43 -#define MX25_INT_CAN2 44 -#define MX25_INT_UART1 45 -#define MX25_INT_GPIO2 51 -#define MX25_INT_GPIO1 52 -#define MX25_INT_FEC 57 +/* + * Interrupt numbers + */ +#include +#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0) +#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3) +#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5) +#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8) +#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9) +#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10) +#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11) +#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12) +#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16) +#define MX25_INT_CSI (NR_IRQS_LEGACY + 17) +#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23) +#define MX25_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25) +#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26) +#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX25_INT_NFC (NR_IRQS_LEGACY + 33) +#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35) +#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36) +#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37) +#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39) +#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40) +#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41) +#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42) +#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43) +#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44) +#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX25_INT_FEC (NR_IRQS_LEGACY + 57) #define MX25_DMA_REQ_SSI2_RX1 22 #define MX25_DMA_REQ_SSI2_TX1 23 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 6265357284d7..e074616d54ca 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -128,69 +128,70 @@ #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) /* fixed interrupt numbers */ -#define MX27_INT_I2C2 1 -#define MX27_INT_GPT6 2 -#define MX27_INT_GPT5 3 -#define MX27_INT_GPT4 4 -#define MX27_INT_RTIC 5 -#define MX27_INT_CSPI3 6 -#define MX27_INT_SDHC 7 -#define MX27_INT_GPIO 8 -#define MX27_INT_SDHC3 9 -#define MX27_INT_SDHC2 10 -#define MX27_INT_SDHC1 11 -#define MX27_INT_I2C1 12 -#define MX27_INT_SSI2 13 -#define MX27_INT_SSI1 14 -#define MX27_INT_CSPI2 15 -#define MX27_INT_CSPI1 16 -#define MX27_INT_UART4 17 -#define MX27_INT_UART3 18 -#define MX27_INT_UART2 19 -#define MX27_INT_UART1 20 -#define MX27_INT_KPP 21 -#define MX27_INT_RTC 22 -#define MX27_INT_PWM 23 -#define MX27_INT_GPT3 24 -#define MX27_INT_GPT2 25 -#define MX27_INT_GPT1 26 -#define MX27_INT_WDOG 27 -#define MX27_INT_PCMCIA 28 -#define MX27_INT_NFC 29 -#define MX27_INT_ATA 30 -#define MX27_INT_CSI 31 -#define MX27_INT_DMACH0 32 -#define MX27_INT_DMACH1 33 -#define MX27_INT_DMACH2 34 -#define MX27_INT_DMACH3 35 -#define MX27_INT_DMACH4 36 -#define MX27_INT_DMACH5 37 -#define MX27_INT_DMACH6 38 -#define MX27_INT_DMACH7 39 -#define MX27_INT_DMACH8 40 -#define MX27_INT_DMACH9 41 -#define MX27_INT_DMACH10 42 -#define MX27_INT_DMACH11 43 -#define MX27_INT_DMACH12 44 -#define MX27_INT_DMACH13 45 -#define MX27_INT_DMACH14 46 -#define MX27_INT_DMACH15 47 -#define MX27_INT_UART6 48 -#define MX27_INT_UART5 49 -#define MX27_INT_FEC 50 -#define MX27_INT_EMMAPRP 51 -#define MX27_INT_EMMAPP 52 -#define MX27_INT_VPU 53 -#define MX27_INT_USB_HS1 54 -#define MX27_INT_USB_HS2 55 -#define MX27_INT_USB_OTG 56 -#define MX27_INT_SCC_SMN 57 -#define MX27_INT_SCC_SCM 58 -#define MX27_INT_SAHARA 59 -#define MX27_INT_SLCDC 60 -#define MX27_INT_LCDC 61 -#define MX27_INT_IIM 62 -#define MX27_INT_CCM 63 +#include +#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) +#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) +#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) +#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) +#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) +#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) +#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7) +#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) +#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) +#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) +#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) +#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) +#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) +#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) +#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) +#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) +#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) +#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) +#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) +#define MX27_INT_KPP (NR_IRQS_LEGACY + 21) +#define MX27_INT_RTC (NR_IRQS_LEGACY + 22) +#define MX27_INT_PWM (NR_IRQS_LEGACY + 23) +#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) +#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) +#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) +#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) +#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) +#define MX27_INT_NFC (NR_IRQS_LEGACY + 29) +#define MX27_INT_ATA (NR_IRQS_LEGACY + 30) +#define MX27_INT_CSI (NR_IRQS_LEGACY + 31) +#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) +#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) +#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) +#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) +#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) +#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) +#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) +#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) +#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) +#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) +#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) +#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) +#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) +#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) +#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) +#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) +#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) +#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) +#define MX27_INT_FEC (NR_IRQS_LEGACY + 50) +#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) +#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) +#define MX27_INT_VPU (NR_IRQS_LEGACY + 53) +#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) +#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) +#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) +#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) +#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) +#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) +#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) +#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) +#define MX27_INT_IIM (NR_IRQS_LEGACY + 62) +#define MX27_INT_CCM (NR_IRQS_LEGACY + 63) /* fixed DMA request numbers */ #define MX27_DMA_REQ_CSPI3_RX 1 diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index 6d07839fdec2..11642f5b224c 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -68,49 +68,50 @@ #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) /* fixed interrupt numbers */ -#define MX2x_INT_CSPI3 6 -#define MX2x_INT_GPIO 8 -#define MX2x_INT_SDHC2 10 -#define MX2x_INT_SDHC1 11 -#define MX2x_INT_I2C 12 -#define MX2x_INT_SSI2 13 -#define MX2x_INT_SSI1 14 -#define MX2x_INT_CSPI2 15 -#define MX2x_INT_CSPI1 16 -#define MX2x_INT_UART4 17 -#define MX2x_INT_UART3 18 -#define MX2x_INT_UART2 19 -#define MX2x_INT_UART1 20 -#define MX2x_INT_KPP 21 -#define MX2x_INT_RTC 22 -#define MX2x_INT_PWM 23 -#define MX2x_INT_GPT3 24 -#define MX2x_INT_GPT2 25 -#define MX2x_INT_GPT1 26 -#define MX2x_INT_WDOG 27 -#define MX2x_INT_PCMCIA 28 -#define MX2x_INT_NANDFC 29 -#define MX2x_INT_CSI 31 -#define MX2x_INT_DMACH0 32 -#define MX2x_INT_DMACH1 33 -#define MX2x_INT_DMACH2 34 -#define MX2x_INT_DMACH3 35 -#define MX2x_INT_DMACH4 36 -#define MX2x_INT_DMACH5 37 -#define MX2x_INT_DMACH6 38 -#define MX2x_INT_DMACH7 39 -#define MX2x_INT_DMACH8 40 -#define MX2x_INT_DMACH9 41 -#define MX2x_INT_DMACH10 42 -#define MX2x_INT_DMACH11 43 -#define MX2x_INT_DMACH12 44 -#define MX2x_INT_DMACH13 45 -#define MX2x_INT_DMACH14 46 -#define MX2x_INT_DMACH15 47 -#define MX2x_INT_EMMAPRP 51 -#define MX2x_INT_EMMAPP 52 -#define MX2x_INT_SLCDC 60 -#define MX2x_INT_LCDC 61 +#include +#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6) +#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8) +#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10) +#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11) +#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12) +#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13) +#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14) +#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15) +#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16) +#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17) +#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19) +#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20) +#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21) +#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22) +#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23) +#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24) +#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25) +#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26) +#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27) +#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28) +#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29) +#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31) +#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32) +#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33) +#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34) +#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35) +#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36) +#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37) +#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38) +#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39) +#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40) +#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41) +#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42) +#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43) +#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44) +#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45) +#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46) +#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47) +#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51) +#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52) +#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60) +#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61) /* fixed DMA request numbers */ #define MX2x_DMA_REQ_CSPI3_RX 1 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index e27619e442c0..dbced61d9fda 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -118,63 +118,67 @@ #define MX31_IO_P2V(x) IMX_IO_P2V(x) #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) -#define MX31_INT_I2C3 3 -#define MX31_INT_I2C2 4 -#define MX31_INT_MPEG4_ENCODER 5 -#define MX31_INT_RTIC 6 -#define MX31_INT_FIRI 7 -#define MX31_INT_SDHC2 8 -#define MX31_INT_SDHC1 9 -#define MX31_INT_I2C1 10 -#define MX31_INT_SSI2 11 -#define MX31_INT_SSI1 12 -#define MX31_INT_CSPI2 13 -#define MX31_INT_CSPI1 14 -#define MX31_INT_ATA 15 -#define MX31_INT_MBX 16 -#define MX31_INT_CSPI3 17 -#define MX31_INT_UART3 18 -#define MX31_INT_IIM 19 -#define MX31_INT_SIM2 20 -#define MX31_INT_SIM1 21 -#define MX31_INT_RNGA 22 -#define MX31_INT_EVTMON 23 -#define MX31_INT_KPP 24 -#define MX31_INT_RTC 25 -#define MX31_INT_PWM 26 -#define MX31_INT_EPIT2 27 -#define MX31_INT_EPIT1 28 -#define MX31_INT_GPT 29 -#define MX31_INT_POWER_FAIL 30 -#define MX31_INT_CCM_DVFS 31 -#define MX31_INT_UART2 32 -#define MX31_INT_NFC 33 -#define MX31_INT_SDMA 34 -#define MX31_INT_USB_HS1 35 -#define MX31_INT_USB_HS2 36 -#define MX31_INT_USB_OTG 37 -#define MX31_INT_MSHC1 39 -#define MX31_INT_MSHC2 40 -#define MX31_INT_IPU_ERR 41 -#define MX31_INT_IPU_SYN 42 -#define MX31_INT_UART1 45 -#define MX31_INT_UART4 46 -#define MX31_INT_UART5 47 -#define MX31_INT_ECT 48 -#define MX31_INT_SCC_SCM 49 -#define MX31_INT_SCC_SMN 50 -#define MX31_INT_GPIO2 51 -#define MX31_INT_GPIO1 52 -#define MX31_INT_CCM 53 -#define MX31_INT_PCMCIA 54 -#define MX31_INT_WDOG 55 -#define MX31_INT_GPIO3 56 -#define MX31_INT_EXT_POWER 58 -#define MX31_INT_EXT_TEMPER 59 -#define MX31_INT_EXT_SENSOR60 60 -#define MX31_INT_EXT_SENSOR61 61 -#define MX31_INT_EXT_WDOG 62 -#define MX31_INT_EXT_TV 63 +/* + * Interrupt numbers + */ +#include +#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) +#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) +#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) +#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) +#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) +#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) +#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) +#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) +#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) +#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX31_INT_ATA (NR_IRQS_LEGACY + 15) +#define MX31_INT_MBX (NR_IRQS_LEGACY + 16) +#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) +#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX31_INT_IIM (NR_IRQS_LEGACY + 19) +#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) +#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) +#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) +#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) +#define MX31_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX31_INT_RTC (NR_IRQS_LEGACY + 25) +#define MX31_INT_PWM (NR_IRQS_LEGACY + 26) +#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) +#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) +#define MX31_INT_GPT (NR_IRQS_LEGACY + 29) +#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) +#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) +#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX31_INT_NFC (NR_IRQS_LEGACY + 33) +#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) +#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) +#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) +#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) +#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) +#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) +#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) +#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) +#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) +#define MX31_INT_ECT (NR_IRQS_LEGACY + 48) +#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) +#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) +#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX31_INT_CCM (NR_IRQS_LEGACY + 53) +#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) +#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) +#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) +#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) +#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) +#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) +#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) +#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) +#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) #define MX31_DMA_REQ_SDHC1 20 #define MX31_DMA_REQ_SDHC2 21 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 80965a99aa55..2af5d3a699c7 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -120,60 +120,61 @@ /* * Interrupt numbers */ -#define MX35_INT_OWIRE 2 -#define MX35_INT_I2C3 3 -#define MX35_INT_I2C2 4 -#define MX35_INT_RTIC 6 -#define MX35_INT_ESDHC1 7 -#define MX35_INT_ESDHC2 8 -#define MX35_INT_ESDHC3 9 -#define MX35_INT_I2C1 10 -#define MX35_INT_SSI1 11 -#define MX35_INT_SSI2 12 -#define MX35_INT_CSPI2 13 -#define MX35_INT_CSPI1 14 -#define MX35_INT_ATA 15 -#define MX35_INT_GPU2D 16 -#define MX35_INT_ASRC 17 -#define MX35_INT_UART3 18 -#define MX35_INT_IIM 19 -#define MX35_INT_RNGA 22 -#define MX35_INT_EVTMON 23 -#define MX35_INT_KPP 24 -#define MX35_INT_RTC 25 -#define MX35_INT_PWM 26 -#define MX35_INT_EPIT2 27 -#define MX35_INT_EPIT1 28 -#define MX35_INT_GPT 29 -#define MX35_INT_POWER_FAIL 30 -#define MX35_INT_UART2 32 -#define MX35_INT_NFC 33 -#define MX35_INT_SDMA 34 -#define MX35_INT_USB_HS 35 -#define MX35_INT_USB_OTG 37 -#define MX35_INT_MSHC1 39 -#define MX35_INT_ESAI 40 -#define MX35_INT_IPU_ERR 41 -#define MX35_INT_IPU_SYN 42 -#define MX35_INT_CAN1 43 -#define MX35_INT_CAN2 44 -#define MX35_INT_UART1 45 -#define MX35_INT_MLB 46 -#define MX35_INT_SPDIF 47 -#define MX35_INT_ECT 48 -#define MX35_INT_SCC_SCM 49 -#define MX35_INT_SCC_SMN 50 -#define MX35_INT_GPIO2 51 -#define MX35_INT_GPIO1 52 -#define MX35_INT_WDOG 55 -#define MX35_INT_GPIO3 56 -#define MX35_INT_FEC 57 -#define MX35_INT_EXT_POWER 58 -#define MX35_INT_EXT_TEMPER 59 -#define MX35_INT_EXT_SENSOR60 60 -#define MX35_INT_EXT_SENSOR61 61 -#define MX35_INT_EXT_WDOG 62 -#define MX35_INT_EXT_TV 63 +#include +#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) +#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) +#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) +#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) +#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) +#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) +#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) +#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) +#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) +#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX35_INT_ATA (NR_IRQS_LEGACY + 15) +#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) +#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) +#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX35_INT_IIM (NR_IRQS_LEGACY + 19) +#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) +#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) +#define MX35_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX35_INT_RTC (NR_IRQS_LEGACY + 25) +#define MX35_INT_PWM (NR_IRQS_LEGACY + 26) +#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) +#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) +#define MX35_INT_GPT (NR_IRQS_LEGACY + 29) +#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) +#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX35_INT_NFC (NR_IRQS_LEGACY + 33) +#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) +#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) +#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) +#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) +#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) +#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) +#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) +#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) +#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX35_INT_MLB (NR_IRQS_LEGACY + 46) +#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) +#define MX35_INT_ECT (NR_IRQS_LEGACY + 48) +#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) +#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) +#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) +#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) +#define MX35_INT_FEC (NR_IRQS_LEGACY + 57) +#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) +#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) +#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) +#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) +#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) +#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) #define MX35_DMA_REQ_SSI2_RX1 22 #define MX35_DMA_REQ_SSI2_TX1 23 diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 30dbf424583e..96fb4fbc8ad7 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -143,44 +143,45 @@ /* * Interrupt numbers */ -#define MX3x_INT_I2C3 3 -#define MX3x_INT_I2C2 4 -#define MX3x_INT_RTIC 6 -#define MX3x_INT_I2C 10 -#define MX3x_INT_CSPI2 13 -#define MX3x_INT_CSPI1 14 -#define MX3x_INT_ATA 15 -#define MX3x_INT_UART3 18 -#define MX3x_INT_IIM 19 -#define MX3x_INT_RNGA 22 -#define MX3x_INT_EVTMON 23 -#define MX3x_INT_KPP 24 -#define MX3x_INT_RTC 25 -#define MX3x_INT_PWM 26 -#define MX3x_INT_EPIT2 27 -#define MX3x_INT_EPIT1 28 -#define MX3x_INT_GPT 29 -#define MX3x_INT_POWER_FAIL 30 -#define MX3x_INT_UART2 32 -#define MX3x_INT_NANDFC 33 -#define MX3x_INT_SDMA 34 -#define MX3x_INT_MSHC1 39 -#define MX3x_INT_IPU_ERR 41 -#define MX3x_INT_IPU_SYN 42 -#define MX3x_INT_UART1 45 -#define MX3x_INT_ECT 48 -#define MX3x_INT_SCC_SCM 49 -#define MX3x_INT_SCC_SMN 50 -#define MX3x_INT_GPIO2 51 -#define MX3x_INT_GPIO1 52 -#define MX3x_INT_WDOG 55 -#define MX3x_INT_GPIO3 56 -#define MX3x_INT_EXT_POWER 58 -#define MX3x_INT_EXT_TEMPER 59 -#define MX3x_INT_EXT_SENSOR60 60 -#define MX3x_INT_EXT_SENSOR61 61 -#define MX3x_INT_EXT_WDOG 62 -#define MX3x_INT_EXT_TV 63 +#include +#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) +#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) +#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) +#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) +#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) +#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) +#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) +#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) +#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) +#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) +#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) +#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) +#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) +#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) +#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) +#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) +#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) +#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) +#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) +#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) +#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) +#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) +#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) +#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) +#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) +#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) +#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) +#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h index 5f2da75a47f4..09ac19c1570c 100644 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -188,99 +188,100 @@ /* * Interrupt numbers */ -#define MX50_INT_MMC_SDHC1 1 -#define MX50_INT_MMC_SDHC2 2 -#define MX50_INT_MMC_SDHC3 3 -#define MX50_INT_MMC_SDHC4 4 -#define MX50_INT_DAP 5 -#define MX50_INT_SDMA 6 -#define MX50_INT_IOMUX 7 -#define MX50_INT_UART4 13 -#define MX50_INT_USB_H1 14 -#define MX50_INT_USB_OTG 18 -#define MX50_INT_DATABAHN 19 -#define MX50_INT_ELCDIF 20 -#define MX50_INT_EPXP 21 -#define MX50_INT_SRTC_NTZ 24 -#define MX50_INT_SRTC_TZ 25 -#define MX50_INT_EPDC 27 -#define MX50_INT_NIC 28 -#define MX50_INT_SSI1 29 -#define MX50_INT_SSI2 30 -#define MX50_INT_UART1 31 -#define MX50_INT_UART2 32 -#define MX50_INT_UART3 33 -#define MX50_INT_RESV34 34 -#define MX50_INT_RESV35 35 -#define MX50_INT_CSPI1 36 -#define MX50_INT_CSPI2 37 -#define MX50_INT_CSPI 38 -#define MX50_INT_GPT 39 -#define MX50_INT_EPIT1 40 -#define MX50_INT_GPIO1_INT7 42 -#define MX50_INT_GPIO1_INT6 43 -#define MX50_INT_GPIO1_INT5 44 -#define MX50_INT_GPIO1_INT4 45 -#define MX50_INT_GPIO1_INT3 46 -#define MX50_INT_GPIO1_INT2 47 -#define MX50_INT_GPIO1_INT1 48 -#define MX50_INT_GPIO1_INT0 49 -#define MX50_INT_GPIO1_LOW 50 -#define MX50_INT_GPIO1_HIGH 51 -#define MX50_INT_GPIO2_LOW 52 -#define MX50_INT_GPIO2_HIGH 53 -#define MX50_INT_GPIO3_LOW 54 -#define MX50_INT_GPIO3_HIGH 55 -#define MX50_INT_GPIO4_LOW 56 -#define MX50_INT_GPIO4_HIGH 57 -#define MX50_INT_WDOG1 58 -#define MX50_INT_KPP 60 -#define MX50_INT_PWM1 61 -#define MX50_INT_I2C1 62 -#define MX50_INT_I2C2 63 -#define MX50_INT_I2C3 64 -#define MX50_INT_RESV65 65 -#define MX50_INT_DCDC 66 -#define MX50_INT_THERMAL_ALARM 67 -#define MX50_INT_ANA3 68 -#define MX50_INT_ANA4 69 -#define MX50_INT_CCM1 71 -#define MX50_INT_CCM2 72 -#define MX50_INT_GPC1 73 -#define MX50_INT_GPC2 74 -#define MX50_INT_SRC 75 -#define MX50_INT_NM 76 -#define MX50_INT_PMU 77 -#define MX50_INT_CTI_IRQ 78 -#define MX50_INT_CTI1_TG0 79 -#define MX50_INT_CTI1_TG1 80 -#define MX50_INT_GPU2_IRQ 84 -#define MX50_INT_GPU2_BUSY 85 -#define MX50_INT_UART5 86 -#define MX50_INT_FEC 87 -#define MX50_INT_OWIRE 88 -#define MX50_INT_CTI1_TG2 89 -#define MX50_INT_SJC 90 -#define MX50_INT_DCP_CHAN1_3 91 -#define MX50_INT_DCP_CHAN0 92 -#define MX50_INT_PWM2 94 -#define MX50_INT_RNGB 97 -#define MX50_INT_CTI1_TG3 98 -#define MX50_INT_RAWNAND_BCH 100 -#define MX50_INT_RAWNAND_GPMI 102 -#define MX50_INT_GPIO5_LOW 103 -#define MX50_INT_GPIO5_HIGH 104 -#define MX50_INT_GPIO6_LOW 105 -#define MX50_INT_GPIO6_HIGH 106 -#define MX50_INT_MSHC 109 -#define MX50_INT_APBHDMA_CHAN0 110 -#define MX50_INT_APBHDMA_CHAN1 111 -#define MX50_INT_APBHDMA_CHAN2 112 -#define MX50_INT_APBHDMA_CHAN3 113 -#define MX50_INT_APBHDMA_CHAN4 114 -#define MX50_INT_APBHDMA_CHAN5 115 -#define MX50_INT_APBHDMA_CHAN6 116 -#define MX50_INT_APBHDMA_CHAN7 117 +#include +#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1) +#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2) +#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3) +#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4) +#define MX50_INT_DAP (NR_IRQS_LEGACY + 5) +#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6) +#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7) +#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13) +#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14) +#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18) +#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19) +#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20) +#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21) +#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) +#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) +#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27) +#define MX50_INT_NIC (NR_IRQS_LEGACY + 28) +#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29) +#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30) +#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31) +#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33) +#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34) +#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35) +#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36) +#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37) +#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38) +#define MX50_INT_GPT (NR_IRQS_LEGACY + 39) +#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40) +#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) +#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) +#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) +#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) +#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) +#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) +#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) +#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) +#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) +#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) +#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) +#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) +#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) +#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) +#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) +#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) +#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58) +#define MX50_INT_KPP (NR_IRQS_LEGACY + 60) +#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61) +#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62) +#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63) +#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64) +#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65) +#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66) +#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67) +#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68) +#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69) +#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71) +#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72) +#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73) +#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74) +#define MX50_INT_SRC (NR_IRQS_LEGACY + 75) +#define MX50_INT_NM (NR_IRQS_LEGACY + 76) +#define MX50_INT_PMU (NR_IRQS_LEGACY + 77) +#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) +#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) +#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) +#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) +#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) +#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86) +#define MX50_INT_FEC (NR_IRQS_LEGACY + 87) +#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88) +#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) +#define MX50_INT_SJC (NR_IRQS_LEGACY + 90) +#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91) +#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92) +#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94) +#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97) +#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) +#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100) +#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102) +#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) +#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) +#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) +#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) +#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109) +#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110) +#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111) +#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112) +#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113) +#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114) +#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115) +#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116) +#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117) #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx50_revision(void); diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index cdf07c65ec1e..af844f76261a 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -232,110 +232,111 @@ /* * Interrupt numbers */ -#define MX51_INT_BASE 0 -#define MX51_INT_RESV0 0 -#define MX51_INT_ESDHC1 1 -#define MX51_INT_ESDHC2 2 -#define MX51_INT_ESDHC3 3 -#define MX51_INT_ESDHC4 4 -#define MX51_INT_RESV5 5 -#define MX51_INT_SDMA 6 -#define MX51_INT_IOMUX 7 -#define MX51_INT_NFC 8 -#define MX51_INT_VPU 9 -#define MX51_INT_IPU_ERR 10 -#define MX51_INT_IPU_SYN 11 -#define MX51_INT_GPU 12 -#define MX51_INT_RESV13 13 -#define MX51_INT_USB_HS1 14 -#define MX51_INT_EMI 15 -#define MX51_INT_USB_HS2 16 -#define MX51_INT_USB_HS3 17 -#define MX51_INT_USB_OTG 18 -#define MX51_INT_SAHARA_H0 19 -#define MX51_INT_SAHARA_H1 20 -#define MX51_INT_SCC_SMN 21 -#define MX51_INT_SCC_STZ 22 -#define MX51_INT_SCC_SCM 23 -#define MX51_INT_SRTC_NTZ 24 -#define MX51_INT_SRTC_TZ 25 -#define MX51_INT_RTIC 26 -#define MX51_INT_CSU 27 -#define MX51_INT_SLIM_B 28 -#define MX51_INT_SSI1 29 -#define MX51_INT_SSI2 30 -#define MX51_INT_UART1 31 -#define MX51_INT_UART2 32 -#define MX51_INT_UART3 33 -#define MX51_INT_RESV34 34 -#define MX51_INT_RESV35 35 -#define MX51_INT_ECSPI1 36 -#define MX51_INT_ECSPI2 37 -#define MX51_INT_CSPI 38 -#define MX51_INT_GPT 39 -#define MX51_INT_EPIT1 40 -#define MX51_INT_EPIT2 41 -#define MX51_INT_GPIO1_INT7 42 -#define MX51_INT_GPIO1_INT6 43 -#define MX51_INT_GPIO1_INT5 44 -#define MX51_INT_GPIO1_INT4 45 -#define MX51_INT_GPIO1_INT3 46 -#define MX51_INT_GPIO1_INT2 47 -#define MX51_INT_GPIO1_INT1 48 -#define MX51_INT_GPIO1_INT0 49 -#define MX51_INT_GPIO1_LOW 50 -#define MX51_INT_GPIO1_HIGH 51 -#define MX51_INT_GPIO2_LOW 52 -#define MX51_INT_GPIO2_HIGH 53 -#define MX51_INT_GPIO3_LOW 54 -#define MX51_INT_GPIO3_HIGH 55 -#define MX51_INT_GPIO4_LOW 56 -#define MX51_INT_GPIO4_HIGH 57 -#define MX51_INT_WDOG1 58 -#define MX51_INT_WDOG2 59 -#define MX51_INT_KPP 60 -#define MX51_INT_PWM1 61 -#define MX51_INT_I2C1 62 -#define MX51_INT_I2C2 63 -#define MX51_INT_HS_I2C 64 -#define MX51_INT_RESV65 65 -#define MX51_INT_RESV66 66 -#define MX51_INT_SIM_IPB 67 -#define MX51_INT_SIM_DAT 68 -#define MX51_INT_IIM 69 -#define MX51_INT_ATA 70 -#define MX51_INT_CCM1 71 -#define MX51_INT_CCM2 72 -#define MX51_INT_GPC1 73 -#define MX51_INT_GPC2 74 -#define MX51_INT_SRC 75 -#define MX51_INT_NM 76 -#define MX51_INT_PMU 77 -#define MX51_INT_CTI_IRQ 78 -#define MX51_INT_CTI1_TG0 79 -#define MX51_INT_CTI1_TG1 80 -#define MX51_INT_MCG_ERR 81 -#define MX51_INT_MCG_TMR 82 -#define MX51_INT_MCG_FUNC 83 -#define MX51_INT_GPU2_IRQ 84 -#define MX51_INT_GPU2_BUSY 85 -#define MX51_INT_RESV86 86 -#define MX51_INT_FEC 87 -#define MX51_INT_OWIRE 88 -#define MX51_INT_CTI1_TG2 89 -#define MX51_INT_SJC 90 -#define MX51_INT_SPDIF 91 -#define MX51_INT_TVE 92 -#define MX51_INT_FIRI 93 -#define MX51_INT_PWM2 94 -#define MX51_INT_SLIM_EXP 95 -#define MX51_INT_SSI3 96 -#define MX51_INT_EMI_BOOT 97 -#define MX51_INT_CTI1_TG3 98 -#define MX51_INT_SMC_RX 99 -#define MX51_INT_VPU_IDLE 100 -#define MX51_INT_EMI_NFC 101 -#define MX51_INT_GPU_IDLE 102 +#include +#define MX51_INT_BASE (NR_IRQS_LEGACY + 0) +#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0) +#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1) +#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2) +#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3) +#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4) +#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5) +#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6) +#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7) +#define MX51_INT_NFC (NR_IRQS_LEGACY + 8) +#define MX51_INT_VPU (NR_IRQS_LEGACY + 9) +#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10) +#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11) +#define MX51_INT_GPU (NR_IRQS_LEGACY + 12) +#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13) +#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14) +#define MX51_INT_EMI (NR_IRQS_LEGACY + 15) +#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16) +#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17) +#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18) +#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) +#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) +#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21) +#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22) +#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23) +#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) +#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) +#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26) +#define MX51_INT_CSU (NR_IRQS_LEGACY + 27) +#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28) +#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29) +#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30) +#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31) +#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33) +#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34) +#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35) +#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36) +#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37) +#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38) +#define MX51_INT_GPT (NR_IRQS_LEGACY + 39) +#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40) +#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41) +#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) +#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) +#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) +#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) +#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) +#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) +#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) +#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) +#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) +#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) +#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) +#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) +#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) +#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) +#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) +#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) +#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58) +#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59) +#define MX51_INT_KPP (NR_IRQS_LEGACY + 60) +#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61) +#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62) +#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63) +#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64) +#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65) +#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66) +#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67) +#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68) +#define MX51_INT_IIM (NR_IRQS_LEGACY + 69) +#define MX51_INT_ATA (NR_IRQS_LEGACY + 70) +#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71) +#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72) +#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73) +#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74) +#define MX51_INT_SRC (NR_IRQS_LEGACY + 75) +#define MX51_INT_NM (NR_IRQS_LEGACY + 76) +#define MX51_INT_PMU (NR_IRQS_LEGACY + 77) +#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) +#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) +#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) +#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81) +#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82) +#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83) +#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) +#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) +#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86) +#define MX51_INT_FEC (NR_IRQS_LEGACY + 87) +#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88) +#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) +#define MX51_INT_SJC (NR_IRQS_LEGACY + 90) +#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91) +#define MX51_INT_TVE (NR_IRQS_LEGACY + 92) +#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93) +#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94) +#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) +#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96) +#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) +#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) +#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99) +#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) +#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101) +#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index a37e8c353994..f829d1c22501 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -229,113 +229,114 @@ /* * Interrupt numbers */ -#define MX53_INT_RESV0 0 -#define MX53_INT_ESDHC1 1 -#define MX53_INT_ESDHC2 2 -#define MX53_INT_ESDHC3 3 -#define MX53_INT_ESDHC4 4 -#define MX53_INT_DAP 5 -#define MX53_INT_SDMA 6 -#define MX53_INT_IOMUX 7 -#define MX53_INT_NFC 8 -#define MX53_INT_VPU 9 -#define MX53_INT_IPU_ERR 10 -#define MX53_INT_IPU_SYN 11 -#define MX53_INT_GPU 12 -#define MX53_INT_UART4 13 -#define MX53_INT_USB_H1 14 -#define MX53_INT_EMI 15 -#define MX53_INT_USB_H2 16 -#define MX53_INT_USB_H3 17 -#define MX53_INT_USB_OTG 18 -#define MX53_INT_SAHARA_H0 19 -#define MX53_INT_SAHARA_H1 20 -#define MX53_INT_SCC_SMN 21 -#define MX53_INT_SCC_STZ 22 -#define MX53_INT_SCC_SCM 23 -#define MX53_INT_SRTC_NTZ 24 -#define MX53_INT_SRTC_TZ 25 -#define MX53_INT_RTIC 26 -#define MX53_INT_CSU 27 -#define MX53_INT_SATA 28 -#define MX53_INT_SSI1 29 -#define MX53_INT_SSI2 30 -#define MX53_INT_UART1 31 -#define MX53_INT_UART2 32 -#define MX53_INT_UART3 33 -#define MX53_INT_RTC 34 -#define MX53_INT_PTP 35 -#define MX53_INT_ECSPI1 36 -#define MX53_INT_ECSPI2 37 -#define MX53_INT_CSPI 38 -#define MX53_INT_GPT 39 -#define MX53_INT_EPIT1 40 -#define MX53_INT_EPIT2 41 -#define MX53_INT_GPIO1_INT7 42 -#define MX53_INT_GPIO1_INT6 43 -#define MX53_INT_GPIO1_INT5 44 -#define MX53_INT_GPIO1_INT4 45 -#define MX53_INT_GPIO1_INT3 46 -#define MX53_INT_GPIO1_INT2 47 -#define MX53_INT_GPIO1_INT1 48 -#define MX53_INT_GPIO1_INT0 49 -#define MX53_INT_GPIO1_LOW 50 -#define MX53_INT_GPIO1_HIGH 51 -#define MX53_INT_GPIO2_LOW 52 -#define MX53_INT_GPIO2_HIGH 53 -#define MX53_INT_GPIO3_LOW 54 -#define MX53_INT_GPIO3_HIGH 55 -#define MX53_INT_GPIO4_LOW 56 -#define MX53_INT_GPIO4_HIGH 57 -#define MX53_INT_WDOG1 58 -#define MX53_INT_WDOG2 59 -#define MX53_INT_KPP 60 -#define MX53_INT_PWM1 61 -#define MX53_INT_I2C1 62 -#define MX53_INT_I2C2 63 -#define MX53_INT_I2C3 64 -#define MX53_INT_MLB 65 -#define MX53_INT_ASRC 66 -#define MX53_INT_SPDIF 67 -#define MX53_INT_SIM_DAT 68 -#define MX53_INT_IIM 69 -#define MX53_INT_ATA 70 -#define MX53_INT_CCM1 71 -#define MX53_INT_CCM2 72 -#define MX53_INT_GPC1 73 -#define MX53_INT_GPC2 74 -#define MX53_INT_SRC 75 -#define MX53_INT_NM 76 -#define MX53_INT_PMU 77 -#define MX53_INT_CTI_IRQ 78 -#define MX53_INT_CTI1_TG0 79 -#define MX53_INT_CTI1_TG1 80 -#define MX53_INT_ESAI 81 -#define MX53_INT_CAN1 82 -#define MX53_INT_CAN2 83 -#define MX53_INT_GPU2_IRQ 84 -#define MX53_INT_GPU2_BUSY 85 -#define MX53_INT_UART5 86 -#define MX53_INT_FEC 87 -#define MX53_INT_OWIRE 88 -#define MX53_INT_CTI1_TG2 89 -#define MX53_INT_SJC 90 -#define MX53_INT_TVE 92 -#define MX53_INT_FIRI 93 -#define MX53_INT_PWM2 94 -#define MX53_INT_SLIM_EXP 95 -#define MX53_INT_SSI3 96 -#define MX53_INT_EMI_BOOT 97 -#define MX53_INT_CTI1_TG3 98 -#define MX53_INT_SMC_RX 99 -#define MX53_INT_VPU_IDLE 100 -#define MX53_INT_EMI_NFC 101 -#define MX53_INT_GPU_IDLE 102 -#define MX53_INT_GPIO5_LOW 103 -#define MX53_INT_GPIO5_HIGH 104 -#define MX53_INT_GPIO6_LOW 105 -#define MX53_INT_GPIO6_HIGH 106 -#define MX53_INT_GPIO7_LOW 107 -#define MX53_INT_GPIO7_HIGH 108 +#include +#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) +#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) +#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) +#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) +#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) +#define MX53_INT_DAP (NR_IRQS_LEGACY + 5) +#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) +#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) +#define MX53_INT_NFC (NR_IRQS_LEGACY + 8) +#define MX53_INT_VPU (NR_IRQS_LEGACY + 9) +#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) +#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) +#define MX53_INT_GPU (NR_IRQS_LEGACY + 12) +#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) +#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) +#define MX53_INT_EMI (NR_IRQS_LEGACY + 15) +#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) +#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) +#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) +#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) +#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) +#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) +#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) +#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) +#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) +#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) +#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) +#define MX53_INT_CSU (NR_IRQS_LEGACY + 27) +#define MX53_INT_SATA (NR_IRQS_LEGACY + 28) +#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) +#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) +#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) +#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) +#define MX53_INT_RTC (NR_IRQS_LEGACY + 34) +#define MX53_INT_PTP (NR_IRQS_LEGACY + 35) +#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) +#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) +#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) +#define MX53_INT_GPT (NR_IRQS_LEGACY + 39) +#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) +#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) +#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) +#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) +#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) +#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) +#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) +#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) +#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) +#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) +#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) +#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) +#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) +#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) +#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) +#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) +#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) +#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) +#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) +#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) +#define MX53_INT_KPP (NR_IRQS_LEGACY + 60) +#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) +#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) +#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) +#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) +#define MX53_INT_MLB (NR_IRQS_LEGACY + 65) +#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) +#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) +#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) +#define MX53_INT_IIM (NR_IRQS_LEGACY + 69) +#define MX53_INT_ATA (NR_IRQS_LEGACY + 70) +#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) +#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) +#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) +#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) +#define MX53_INT_SRC (NR_IRQS_LEGACY + 75) +#define MX53_INT_NM (NR_IRQS_LEGACY + 76) +#define MX53_INT_PMU (NR_IRQS_LEGACY + 77) +#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) +#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) +#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) +#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) +#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) +#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) +#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) +#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) +#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) +#define MX53_INT_FEC (NR_IRQS_LEGACY + 87) +#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) +#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) +#define MX53_INT_SJC (NR_IRQS_LEGACY + 90) +#define MX53_INT_TVE (NR_IRQS_LEGACY + 92) +#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) +#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) +#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) +#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) +#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) +#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) +#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) +#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) +#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) +#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) +#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) +#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) +#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) +#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) +#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) +#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) #endif /* ifndef __MACH_MX53_H__ */ diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c index 4296a8350298..d2e6f82ecfac 100644 --- a/drivers/media/video/mx1_camera.c +++ b/drivers/media/video/mx1_camera.c @@ -43,6 +43,7 @@ #include #include #include +#include #include /* diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c index 456b7d723d66..ee27ba3933bd 100644 --- a/sound/soc/fsl/imx-pcm-fiq.c +++ b/sound/soc/fsl/imx-pcm-fiq.c @@ -29,6 +29,7 @@ #include +#include #include #include "imx-ssi.h" -- cgit v1.2.3-59-g8ed1b