From a9372a5fb20597a070d89f9402241d9012c0590f Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Thu, 16 May 2019 08:19:37 +0200 Subject: ARM: mmp: add support for MMP3 SoC Similar to MMP2, which this patch is based on. Known differencies from MMP2 are: * Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes Hard to tell what else is different, because documentation is not available. Signed-off-by: Lubomir Rintel --- drivers/clk/Kconfig | 5 +++++ drivers/clk/mmp/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c44247d0b83e..0530bebfc25a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -292,6 +292,11 @@ config COMMON_CLK_STM32H7 help Support for stm32h7 SoC family clocks +config COMMON_CLK_MMP2 + def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT) + help + Support for Marvell MMP2 and MMP3 SoC clocks + config COMMON_CLK_BD718XX tristate "Clock driver for ROHM BD718x7 PMIC" depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 7bc7ac69391e..acc141adf087 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -8,7 +8,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o obj-$(CONFIG_RESET_CONTROLLER) += reset.o obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o -obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o +obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o -- cgit v1.2.3-59-g8ed1b From 91d7ff5aa7e3edd9ab99a424099476ed5667b152 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 30 Jul 2019 20:23:40 +0300 Subject: ARM: tegra: Use WFE for power-gating on Tegra30 Turned out that WFI doesn't work reliably on Tegra30 as a trigger for the power-gating, it causes CPU hang under some circumstances like having memory controller running of PLLP. The TRM doc states that WFI should be used for the Big-Little "Cluster Switch", while WFE for the power-gating. Hence let's use the WFE for CPU0 power-gating, like it is done for the power-gating of a secondary cores. This fixes CPU hang after entering LP2 with memory running off PLLP. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra30.S | 4 +++- drivers/soc/tegra/flowctrl.c | 19 +++++++++++++++++-- 2 files changed, 20 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b408fa56eb89..3341a12bbb9c 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -682,10 +682,12 @@ tegra30_enter_sleep: dsb ldr r0, [r6, r2] /* memory barrier */ + cmp r10, #TEGRA30 halted: isb dsb - wfi /* CPU should be power gated here */ + wfine /* CPU should be power gated here */ + wfeeq /* !!!FIXME!!! Implement halt failure handler */ b halted diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c index b6bdeef33db1..eb96a3086d6d 100644 --- a/drivers/soc/tegra/flowctrl.c +++ b/drivers/soc/tegra/flowctrl.c @@ -91,8 +91,23 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfi */ - reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; + + if (tegra_get_chip_id() == TEGRA30) { + /* + * The wfi doesn't work well on Tegra30 because + * CPU hangs under some odd circumstances after + * power-gating (like memory running off PLLP), + * hence use wfe that is working perfectly fine. + * Note that Tegra30 TRM doc clearly stands that + * wfi should be used for the "Cluster Switching", + * while wfe for the power-gating, just like it + * is done on Tegra20. + */ + reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; + } else { + /* pwr gating on wfi */ + reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; + } break; } reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ -- cgit v1.2.3-59-g8ed1b