From 836a8051d54525e0782f156dcfa3c13d30f22840 Mon Sep 17 00:00:00 2001
From: Stanislav Samsonov <samsonov@marvell.com>
Date: Tue, 3 Jun 2008 11:24:40 +0300
Subject: [ARM] Feroceon: L1 cache range operation support

This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
---
 include/asm-arm/cacheflush.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'include/asm-arm/cacheflush.h')

diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56eed..b85d426bb528 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
 #endif
 
 #if defined(CONFIG_CPU_FEROCEON)
-# ifdef _CACHE
-#  define MULTI_CACHE 1
-# else
-#  define _CACHE feroceon
-# endif
+# define MULTI_CACHE 1
 #endif
 
 #if defined(CONFIG_CPU_V6)
-- 
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