From f12d0d7c7786af39435ef6ae9defe47fb58f6091 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:36:37 +0900 Subject: [ARM] nommu: manage the CP15 things All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- include/asm-arm/system.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-arm/system.h') diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index c19c5b009f71..f05fbe31576c 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -46,6 +46,7 @@ #define CPUID_TCM 2 #define CPUID_TLBTYPE 3 +#ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ ({ \ unsigned int __val; \ @@ -55,6 +56,9 @@ : "cc"); \ __val; \ }) +#else +#define read_cpuid(reg) (processor_id) +#endif /* * This is used to ensure the compiler did actually allocate the register we -- cgit v1.2.3-59-g8ed1b