From 6b7d0b2fb6da3f6182f2bd162bf02ed4aed1813f Mon Sep 17 00:00:00 2001 From: bruno randolf Date: Fri, 6 Jun 2008 16:42:03 +0200 Subject: [MIPS] Alchemy: Add au1500 reserved interrupt In the conversion done in the commits 95c4eb3ef4484ca85da5c98780d358cffd546b90 9d360ab4a7568a8d177280f651a8a772ae52b9b9 [MIPS] Alchemy: Renumber interrupts so irq_cpu can work. one reserved interrupt on au1500 was missed. this broke the au1000 ethernet driver. Signed-off-by: Bruno Randolf Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1000.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-mips') diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 1b5064dac007..0d302bad4492 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -615,6 +615,7 @@ enum soc_au1500_ints { AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT, AU1500_PCI_ERR_INT, + AU1500_RESERVED_INT, AU1000_USB_DEV_REQ_INT, AU1000_USB_DEV_SUS_INT, AU1000_USB_HOST_INT, -- cgit v1.3-14-g43fede From 89052bd7b393434f7c573ce6a3b88c5f143586d2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 12 Jun 2008 17:26:02 +0100 Subject: [MIPS] Fix build for PNX platforms. Build error was caused by commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0. Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 26 ++++++++++++++++++++++++++ arch/mips/nxp/pnx8550/jbs/board_setup.c | 11 +---------- arch/mips/nxp/pnx8550/stb810/board_setup.c | 10 +--------- include/asm-mips/pgtable-bits.h | 2 -- 4 files changed, 28 insertions(+), 21 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 643c8bcffff3..c41ea2284954 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1226,6 +1226,28 @@ void au1x00_fixup_config_od(void) } } +/* CP0 hazard avoidance. */ +#define NXP_BARRIER() \ + __asm__ __volatile__( \ + ".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +static void nxp_pr4450_fixup_config(void) +{ + unsigned long config0; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7 << 25) | (7 << 28)); + config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | + ((_page_cachable_default >> _CACHE_SHIFT) << 25) | + ((_page_cachable_default >> _CACHE_SHIFT) << 28)); + write_c0_config(config0); + NXP_BARRIER(); +} + static int __cpuinitdata cca = -1; static int __init cca_setup(char *str) @@ -1271,6 +1293,10 @@ static void __cpuinit coherency_setup(void) case CPU_AU1500: /* rev. AB */ au1x00_fixup_config_od(); break; + + case PRID_IMP_PR4450: + nxp_pr4450_fixup_config(); + break; } } diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c index f92826e0096d..57dd903ca408 100644 --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c @@ -47,16 +47,7 @@ void __init board_setup(void) { - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); - BARRIER; + unsigned long configpr; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c index 1282c27cfcb7..af2a55e0b4e9 100644 --- a/arch/mips/nxp/pnx8550/stb810/board_setup.c +++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c @@ -33,15 +33,7 @@ void __init board_setup(void) { - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); + unsigned long configpr; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 60e2f9338fcd..51b34a48c84a 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -134,6 +134,4 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) - #endif /* _ASM_PGTABLE_BITS_H */ -- cgit v1.3-14-g43fede From d6c3048cad3c9eb312c070e11fdbea56498255ed Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 16 May 2008 17:29:54 -0700 Subject: [MIPS] vpe_id is required for VSMP and SMTC builds Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- include/asm-mips/cpu-info.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 0c5a358863f3..2de73dbb2e9e 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -56,7 +56,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ -#if defined(CONFIG_MIPS_MT_SMTC) +#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered * to be a "CPU" for the purposes of scheduling, but @@ -64,7 +64,7 @@ struct cpuinfo_mips { * to all TCs within the same VPE. */ int vpe_id; /* Virtual Processor number */ -#endif /* CONFIG_MIPS_MT */ +#endif #ifdef CONFIG_MIPS_MT_SMTC int tc_id; /* Thread Context number */ #endif -- cgit v1.3-14-g43fede From 0c3bd83b0974238a5808d342663c6407512564d0 Mon Sep 17 00:00:00 2001 From: Thomas Horsten Date: Sat, 14 Jun 2008 02:32:42 +0100 Subject: [MIPS] Lasat: bring back from the dead After the common MIPS CPU interrupt controller (for irq0-7) was introduced the Lasat boards didn't get their interrupts right, so nothing worked. The old routines need to be offset by the new 8 hardware interrupts common to all MIPS CPU's. Signed-off-by: Thomas Horsten Signed-off-by: Ralf Baechle --- arch/mips/lasat/interrupt.c | 2 ++ include/asm-mips/lasat/serial.h | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index cfeab669782f..a56c15026965 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -34,11 +34,13 @@ static volatile int lasat_int_mask_shift; void disable_lasat_irq(unsigned int irq_nr) { + irq_nr -= LASAT_IRQ_BASE; *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; } void enable_lasat_irq(unsigned int irq_nr) { + irq_nr -= LASAT_IRQ_BASE; *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; } diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h index bafe68b10614..1c37d70579b8 100644 --- a/include/asm-mips/lasat/serial.h +++ b/include/asm-mips/lasat/serial.h @@ -4,10 +4,10 @@ #define LASAT_BASE_BAUD_100 (7372800 / 16) #define LASAT_UART_REGS_BASE_100 0x1c8b0000 #define LASAT_UART_REGS_SHIFT_100 2 -#define LASATINT_UART_100 8 +#define LASATINT_UART_100 16 /* * LASAT 200 boards serial configuration */ #define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) #define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) #define LASAT_UART_REGS_SHIFT_200 3 -#define LASATINT_UART_200 13 +#define LASATINT_UART_200 21 -- cgit v1.3-14-g43fede From 938b2b14172bd098972df2a5157bfabf161c90e5 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Thu, 29 May 2008 22:05:07 +0200 Subject: [MIPS] Malta: Fix build errors for 64-bit kernels Fix 64-bit Malta by using CKSEG0ADDR and correct casts. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/mips-boards/generic/amon.c | 4 ++-- include/asm-mips/gic.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c index b7633fda4180..96236bf33838 100644 --- a/arch/mips/mips-boards/generic/amon.c +++ b/arch/mips/mips-boards/generic/amon.c @@ -28,7 +28,7 @@ int amon_cpu_avail(int cpu) { - struct cpulaunch *launch = (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); if (cpu < 0 || cpu >= NCPULAUNCH) { pr_debug("avail: cpu%d is out of range\n", cpu); @@ -53,7 +53,7 @@ void amon_cpu_start(int cpu, unsigned long gp, unsigned long a0) { volatile struct cpulaunch *launch = - (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); if (!amon_cpu_avail(cpu)) return; diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h index 3a492f225f00..954807d9d66a 100644 --- a/include/asm-mips/gic.h +++ b/include/asm-mips/gic.h @@ -24,8 +24,8 @@ #define MSK(n) ((1 << (n)) - 1) #define REG32(addr) (*(volatile unsigned int *) (addr)) -#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) -#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) +#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) +#define REGP(base, phys) REG32((unsigned long)(base) + (phys)) /* Accessors */ #define GIC_REG(segment, offset) \ -- cgit v1.3-14-g43fede