From e8688fe8df7d01f43586b4bb74b2fa92f56c5ee8 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 16 Oct 2019 11:57:40 +0000 Subject: clk: imx8mn: Define gates for pll1/2 fixed dividers On imx8mn there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- include/dt-bindings/clock/imx8mn-clock.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index d7b201652f4c..0f2b8423ce1d 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -211,6 +211,23 @@ #define IMX8MN_CLK_GPU_CORE_ROOT 193 #define IMX8MN_CLK_GIC 194 -#define IMX8MN_CLK_END 195 +#define IMX8MN_SYS_PLL1_40M_CG 195 +#define IMX8MN_SYS_PLL1_80M_CG 196 +#define IMX8MN_SYS_PLL1_100M_CG 197 +#define IMX8MN_SYS_PLL1_133M_CG 198 +#define IMX8MN_SYS_PLL1_160M_CG 199 +#define IMX8MN_SYS_PLL1_200M_CG 200 +#define IMX8MN_SYS_PLL1_266M_CG 201 +#define IMX8MN_SYS_PLL1_400M_CG 202 +#define IMX8MN_SYS_PLL2_50M_CG 203 +#define IMX8MN_SYS_PLL2_100M_CG 204 +#define IMX8MN_SYS_PLL2_125M_CG 205 +#define IMX8MN_SYS_PLL2_166M_CG 206 +#define IMX8MN_SYS_PLL2_200M_CG 207 +#define IMX8MN_SYS_PLL2_250M_CG 208 +#define IMX8MN_SYS_PLL2_333M_CG 209 +#define IMX8MN_SYS_PLL2_500M_CG 210 + +#define IMX8MN_CLK_END 211 #endif -- cgit v1.2.3-59-g8ed1b