From 76c9dd9dbd6459f1faf2b10351eb3d3f90255fa1 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 25 May 2018 13:11:47 -0500 Subject: clk: davinci: pll: allow dev == NULL This modifies the TI Davinci PLL clock driver to allow for the case when dev == NULL. On some (most) SoCs that use this driver, the PLL clock needs to be registered during early boot because it is used for clocksource/clkevent and there will be no platform device available. Signed-off-by: David Lechner Reviewed-by: Sekhar Nori Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com --- include/linux/clk/davinci.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/linux/clk/davinci.h (limited to 'include/linux/clk/davinci.h') diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h new file mode 100644 index 000000000000..ebdd9df1c0ef --- /dev/null +++ b/include/linux/clk/davinci.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for TI DaVinci PLL and PSC controllers + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_CLK_DAVINCI_PLL_H___ +#define __LINUX_CLK_DAVINCI_PLL_H___ + +#include +#include + +/* function for registering clocks in early boot */ + +int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); + +#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */ -- cgit v1.2.3-59-g8ed1b