From fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 10 Dec 2012 10:30:04 +0100 Subject: ALSA: ASoC: cs4271: add optional soft reset workaround The CS4271 requires its LRCLK and MCLK to be stable before its RESET line is de-asserted. That also means that clocks cannot be changed without putting the chip back into hardware reset, which also requires a complete re-initialization of all registers. One (undocumented) workaround is to assert and de-assert the PDN bit in the MODE2 register. This patch adds a new flag to both the DT bindings as well as to the platform data to enable that workaround. Signed-off-by: Daniel Mack Acked-by: Alexander Sverdlin Signed-off-by: Mark Brown --- include/sound/cs4271.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include/sound/cs4271.h') diff --git a/include/sound/cs4271.h b/include/sound/cs4271.h index dd8c48d14ed9..70f45355acaa 100644 --- a/include/sound/cs4271.h +++ b/include/sound/cs4271.h @@ -20,6 +20,21 @@ struct cs4271_platform_data { int gpio_nreset; /* GPIO driving Reset pin, if any */ bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ + + /* + * The CS4271 requires its LRCLK and MCLK to be stable before its RESET + * line is de-asserted. That also means that clocks cannot be changed + * without putting the chip back into hardware reset, which also requires + * a complete re-initialization of all registers. + * + * One (undocumented) workaround is to assert and de-assert the PDN bit + * in the MODE2 register. This workaround can be enabled with the + * following flag. + * + * Note that this is not needed in case the clocks are stable + * throughout the entire runtime of the codec. + */ + bool enable_soft_reset; }; #endif /* __CS4271_H */ -- cgit v1.2.3-59-g8ed1b