From bafe68034e3ef5e9f512bd0468001caf34981c41 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 10 Mar 2008 12:56:12 +0100 Subject: avr32: Work around byteswap bug in gcc < 4.2 gcc versions earlier than 4.2 sign-extends the result of le16_to_cpu() and friends when we implement __arch__swabX() using __builtin_bswap_X(). Disable our arch-specific optimizations when those gcc versions are being used. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/byteorder.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/asm-avr32/byteorder.h b/include/asm-avr32/byteorder.h index 402ff4125cdc..d77b48ba7338 100644 --- a/include/asm-avr32/byteorder.h +++ b/include/asm-avr32/byteorder.h @@ -12,8 +12,14 @@ extern unsigned long __builtin_bswap_32(unsigned long x); extern unsigned short __builtin_bswap_16(unsigned short x); #endif +/* + * avr32-linux-gcc versions earlier than 4.2 improperly sign-extends + * the result. + */ +#if !(__GNUC__ == 4 && __GNUC_MINOR__ < 2) #define __arch__swab32(x) __builtin_bswap_32(x) #define __arch__swab16(x) __builtin_bswap_16(x) +#endif #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ -- cgit v1.2.3-59-g8ed1b From fa86d322d89995fef1bfb5cc768b89d8c22ea0d9 Mon Sep 17 00:00:00 2001 From: Pavel Emelyanov Date: Mon, 24 Mar 2008 14:48:59 -0700 Subject: [NEIGH]: Fix race between pneigh deletion and ipv6's ndisc_recv_ns (v3). Proxy neighbors do not have any reference counting, so any caller of pneigh_lookup (unless it's a netlink triggered add/del routine) should _not_ perform any actions on the found proxy entry. There's one exception from this rule - the ipv6's ndisc_recv_ns() uses found entry to check the flags for NTF_ROUTER. This creates a race between the ndisc and pneigh_delete - after the pneigh is returned to the caller, the nd_tbl.lock is dropped and the deleting procedure may proceed. One of the fixes would be to add a reference counting, but this problem exists for ndisc only. Besides such a patch would be too big for -rc4. So I propose to introduce a __pneigh_lookup() which is supposed to be called with the lock held and use it in ndisc code to check the flags on alive pneigh entry. Changes from v2: As David noticed, Exported the __pneigh_lookup() to ipv6 module. The checkpatch generates a warning on it, since the EXPORT_SYMBOL does not follow the symbol itself, but in this file all the exports come at the end, so I decided no to break this harmony. Changes from v1: Fixed comments from YOSHIFUJI - indentation of prototype in header and the pndisc_check_router() name - and a compilation fix, pointed by Daniel - the is_routed was (falsely) considered as uninitialized by gcc. Signed-off-by: Pavel Emelyanov Signed-off-by: David S. Miller --- include/net/neighbour.h | 4 ++++ net/core/neighbour.c | 23 +++++++++++++++++++++++ net/ipv6/ndisc.c | 22 ++++++++++++++++++---- 3 files changed, 45 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/net/neighbour.h b/include/net/neighbour.h index ebbfb509822e..64a5f0120b52 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -218,6 +218,10 @@ extern unsigned long neigh_rand_reach_time(unsigned long base); extern void pneigh_enqueue(struct neigh_table *tbl, struct neigh_parms *p, struct sk_buff *skb); extern struct pneigh_entry *pneigh_lookup(struct neigh_table *tbl, struct net *net, const void *key, struct net_device *dev, int creat); +extern struct pneigh_entry *__pneigh_lookup(struct neigh_table *tbl, + struct net *net, + const void *key, + struct net_device *dev); extern int pneigh_delete(struct neigh_table *tbl, struct net *net, const void *key, struct net_device *dev); extern void neigh_app_ns(struct neighbour *n); diff --git a/net/core/neighbour.c b/net/core/neighbour.c index d9a02b2cc289..19b8e003f150 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -466,6 +466,28 @@ out_neigh_release: goto out; } +struct pneigh_entry *__pneigh_lookup(struct neigh_table *tbl, + struct net *net, const void *pkey, struct net_device *dev) +{ + struct pneigh_entry *n; + int key_len = tbl->key_len; + u32 hash_val = *(u32 *)(pkey + key_len - 4); + + hash_val ^= (hash_val >> 16); + hash_val ^= hash_val >> 8; + hash_val ^= hash_val >> 4; + hash_val &= PNEIGH_HASHMASK; + + for (n = tbl->phash_buckets[hash_val]; n; n = n->next) { + if (!memcmp(n->key, pkey, key_len) && + (n->net == net) && + (n->dev == dev || !n->dev)) + break; + } + + return n; +} + struct pneigh_entry * pneigh_lookup(struct neigh_table *tbl, struct net *net, const void *pkey, struct net_device *dev, int creat) @@ -2803,6 +2825,7 @@ EXPORT_SYMBOL(neigh_table_init_no_netlink); EXPORT_SYMBOL(neigh_update); EXPORT_SYMBOL(pneigh_enqueue); EXPORT_SYMBOL(pneigh_lookup); +EXPORT_SYMBOL_GPL(__pneigh_lookup); #ifdef CONFIG_ARPD EXPORT_SYMBOL(neigh_app_ns); diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 51557c27a0cd..452a2ac4eec8 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -676,6 +676,20 @@ static void ndisc_solicit(struct neighbour *neigh, struct sk_buff *skb) } } +static struct pneigh_entry *pndisc_check_router(struct net_device *dev, + struct in6_addr *addr, int *is_router) +{ + struct pneigh_entry *n; + + read_lock_bh(&nd_tbl.lock); + n = __pneigh_lookup(&nd_tbl, &init_net, addr, dev); + if (n != NULL) + *is_router = (n->flags & NTF_ROUTER); + read_unlock_bh(&nd_tbl.lock); + + return n; +} + static void ndisc_recv_ns(struct sk_buff *skb) { struct nd_msg *msg = (struct nd_msg *)skb_transport_header(skb); @@ -692,7 +706,7 @@ static void ndisc_recv_ns(struct sk_buff *skb) struct pneigh_entry *pneigh = NULL; int dad = ipv6_addr_any(saddr); int inc; - int is_router; + int is_router = 0; if (ipv6_addr_is_multicast(&msg->target)) { ND_PRINTK2(KERN_WARNING @@ -790,8 +804,8 @@ static void ndisc_recv_ns(struct sk_buff *skb) if (ipv6_chk_acast_addr(dev, &msg->target) || (idev->cnf.forwarding && (ipv6_devconf.proxy_ndp || idev->cnf.proxy_ndp) && - (pneigh = pneigh_lookup(&nd_tbl, &init_net, - &msg->target, dev, 0)) != NULL)) { + (pneigh = pndisc_check_router(dev, &msg->target, + &is_router)) != NULL)) { if (!(NEIGH_CB(skb)->flags & LOCALLY_ENQUEUED) && skb->pkt_type != PACKET_HOST && inc != 0 && @@ -812,7 +826,7 @@ static void ndisc_recv_ns(struct sk_buff *skb) goto out; } - is_router = !!(pneigh ? pneigh->flags & NTF_ROUTER : idev->cnf.forwarding); + is_router = !!(pneigh ? is_router : idev->cnf.forwarding); if (dad) { struct in6_addr maddr; -- cgit v1.2.3-59-g8ed1b From df9dcb4588aca9cc243cf1f3f454361a84e1cbdb Mon Sep 17 00:00:00 2001 From: Kazunori MIYAZAWA Date: Mon, 24 Mar 2008 14:51:51 -0700 Subject: [IPSEC]: Fix inter address family IPsec tunnel handling. Signed-off-by: Kazunori MIYAZAWA Signed-off-by: David S. Miller --- include/net/xfrm.h | 23 +++++++++++++++++++ net/ipv4/xfrm4_mode_tunnel.c | 2 +- net/ipv4/xfrm4_output.c | 2 +- net/ipv6/xfrm6_mode_tunnel.c | 2 +- net/ipv6/xfrm6_output.c | 2 +- net/key/af_key.c | 2 +- net/xfrm/xfrm_input.c | 22 +++++++++++++++--- net/xfrm/xfrm_output.c | 18 ++++++++++++++- net/xfrm/xfrm_state.c | 54 ++++++++++++++++++++++++++++++++++++++------ net/xfrm/xfrm_user.c | 7 ++---- 10 files changed, 113 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 619c53bc3cd2..4e6f9568cbe7 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -204,6 +204,7 @@ struct xfrm_state * transformer. */ const struct xfrm_type *type; struct xfrm_mode *inner_mode; + struct xfrm_mode *inner_mode_iaf; struct xfrm_mode *outer_mode; /* Security context */ @@ -387,6 +388,27 @@ enum { extern int xfrm_register_mode(struct xfrm_mode *mode, int family); extern int xfrm_unregister_mode(struct xfrm_mode *mode, int family); +static inline int xfrm_af2proto(unsigned int family) +{ + switch(family) { + case AF_INET: + return IPPROTO_IPIP; + case AF_INET6: + return IPPROTO_IPV6; + default: + return 0; + } +} + +static inline struct xfrm_mode *xfrm_ip2inner_mode(struct xfrm_state *x, int ipproto) +{ + if ((ipproto == IPPROTO_IPIP && x->props.family == AF_INET) || + (ipproto == IPPROTO_IPV6 && x->props.family == AF_INET6)) + return x->inner_mode; + else + return x->inner_mode_iaf; +} + struct xfrm_tmpl { /* id in template is interpreted as: @@ -1253,6 +1275,7 @@ extern int xfrm_input(struct sk_buff *skb, int nexthdr, __be32 spi, extern int xfrm_input_resume(struct sk_buff *skb, int nexthdr); extern int xfrm_output_resume(struct sk_buff *skb, int err); extern int xfrm_output(struct sk_buff *skb); +extern int xfrm_inner_extract_output(struct xfrm_state *x, struct sk_buff *skb); extern int xfrm4_extract_header(struct sk_buff *skb); extern int xfrm4_extract_input(struct xfrm_state *x, struct sk_buff *skb); extern int xfrm4_rcv_encap(struct sk_buff *skb, int nexthdr, __be32 spi, diff --git a/net/ipv4/xfrm4_mode_tunnel.c b/net/ipv4/xfrm4_mode_tunnel.c index 8dee617ee900..584e6d74e3a9 100644 --- a/net/ipv4/xfrm4_mode_tunnel.c +++ b/net/ipv4/xfrm4_mode_tunnel.c @@ -41,7 +41,7 @@ static int xfrm4_mode_tunnel_output(struct xfrm_state *x, struct sk_buff *skb) top_iph->ihl = 5; top_iph->version = 4; - top_iph->protocol = x->inner_mode->afinfo->proto; + top_iph->protocol = xfrm_af2proto(skb->dst->ops->family); /* DS disclosed */ top_iph->tos = INET_ECN_encapsulate(XFRM_MODE_SKB_CB(skb)->tos, diff --git a/net/ipv4/xfrm4_output.c b/net/ipv4/xfrm4_output.c index d5a58a818021..8c3180adddbf 100644 --- a/net/ipv4/xfrm4_output.c +++ b/net/ipv4/xfrm4_output.c @@ -56,7 +56,7 @@ int xfrm4_prepare_output(struct xfrm_state *x, struct sk_buff *skb) { int err; - err = x->inner_mode->afinfo->extract_output(x, skb); + err = xfrm_inner_extract_output(x, skb); if (err) return err; diff --git a/net/ipv6/xfrm6_mode_tunnel.c b/net/ipv6/xfrm6_mode_tunnel.c index 0c742faaa30b..e20529b4c825 100644 --- a/net/ipv6/xfrm6_mode_tunnel.c +++ b/net/ipv6/xfrm6_mode_tunnel.c @@ -45,7 +45,7 @@ static int xfrm6_mode_tunnel_output(struct xfrm_state *x, struct sk_buff *skb) memcpy(top_iph->flow_lbl, XFRM_MODE_SKB_CB(skb)->flow_lbl, sizeof(top_iph->flow_lbl)); - top_iph->nexthdr = x->inner_mode->afinfo->proto; + top_iph->nexthdr = xfrm_af2proto(skb->dst->ops->family); dsfield = XFRM_MODE_SKB_CB(skb)->tos; dsfield = INET_ECN_encapsulate(dsfield, dsfield); diff --git a/net/ipv6/xfrm6_output.c b/net/ipv6/xfrm6_output.c index 79ccfb080733..0af823cf7f1f 100644 --- a/net/ipv6/xfrm6_output.c +++ b/net/ipv6/xfrm6_output.c @@ -62,7 +62,7 @@ int xfrm6_prepare_output(struct xfrm_state *x, struct sk_buff *skb) { int err; - err = x->inner_mode->afinfo->extract_output(x, skb); + err = xfrm_inner_extract_output(x, skb); if (err) return err; diff --git a/net/key/af_key.c b/net/key/af_key.c index 8b5f486ac80f..e9ef9af4a53b 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -1219,7 +1219,7 @@ static struct xfrm_state * pfkey_msg2xfrm_state(struct sadb_msg *hdr, x->sel.prefixlen_s = addr->sadb_address_prefixlen; } - if (!x->sel.family) + if (x->props.mode == XFRM_MODE_TRANSPORT) x->sel.family = x->props.family; if (ext_hdrs[SADB_X_EXT_NAT_T_TYPE-1]) { diff --git a/net/xfrm/xfrm_input.c b/net/xfrm/xfrm_input.c index 62188c6a06dd..75279402ccf4 100644 --- a/net/xfrm/xfrm_input.c +++ b/net/xfrm/xfrm_input.c @@ -84,14 +84,21 @@ int xfrm_parse_spi(struct sk_buff *skb, u8 nexthdr, __be32 *spi, __be32 *seq) int xfrm_prepare_input(struct xfrm_state *x, struct sk_buff *skb) { + struct xfrm_mode *inner_mode = x->inner_mode; int err; err = x->outer_mode->afinfo->extract_input(x, skb); if (err) return err; - skb->protocol = x->inner_mode->afinfo->eth_proto; - return x->inner_mode->input2(x, skb); + if (x->sel.family == AF_UNSPEC) { + inner_mode = xfrm_ip2inner_mode(x, XFRM_MODE_SKB_CB(skb)->protocol); + if (inner_mode == NULL) + return -EAFNOSUPPORT; + } + + skb->protocol = inner_mode->afinfo->eth_proto; + return inner_mode->input2(x, skb); } EXPORT_SYMBOL(xfrm_prepare_input); @@ -101,6 +108,7 @@ int xfrm_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type) __be32 seq; struct xfrm_state *x; xfrm_address_t *daddr; + struct xfrm_mode *inner_mode; unsigned int family; int decaps = 0; int async = 0; @@ -207,7 +215,15 @@ resume: XFRM_MODE_SKB_CB(skb)->protocol = nexthdr; - if (x->inner_mode->input(x, skb)) { + inner_mode = x->inner_mode; + + if (x->sel.family == AF_UNSPEC) { + inner_mode = xfrm_ip2inner_mode(x, XFRM_MODE_SKB_CB(skb)->protocol); + if (inner_mode == NULL) + goto drop; + } + + if (inner_mode->input(x, skb)) { XFRM_INC_STATS(LINUX_MIB_XFRMINSTATEMODEERROR); goto drop; } diff --git a/net/xfrm/xfrm_output.c b/net/xfrm/xfrm_output.c index 569d377932c4..2519129c6d21 100644 --- a/net/xfrm/xfrm_output.c +++ b/net/xfrm/xfrm_output.c @@ -124,7 +124,7 @@ int xfrm_output_resume(struct sk_buff *skb, int err) if (!x) return dst_output(skb); - err = nf_hook(x->inner_mode->afinfo->family, + err = nf_hook(skb->dst->ops->family, NF_INET_POST_ROUTING, skb, NULL, skb->dst->dev, xfrm_output2); if (unlikely(err != 1)) @@ -193,4 +193,20 @@ int xfrm_output(struct sk_buff *skb) return xfrm_output2(skb); } + +int xfrm_inner_extract_output(struct xfrm_state *x, struct sk_buff *skb) +{ + struct xfrm_mode *inner_mode; + if (x->sel.family == AF_UNSPEC) + inner_mode = xfrm_ip2inner_mode(x, + xfrm_af2proto(skb->dst->ops->family)); + else + inner_mode = x->inner_mode; + + if (inner_mode == NULL) + return -EAFNOSUPPORT; + return inner_mode->afinfo->extract_output(x, skb); +} + EXPORT_SYMBOL_GPL(xfrm_output); +EXPORT_SYMBOL_GPL(xfrm_inner_extract_output); diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c index 7ba65e82941c..58f1f9347b54 100644 --- a/net/xfrm/xfrm_state.c +++ b/net/xfrm/xfrm_state.c @@ -388,6 +388,8 @@ static void xfrm_state_gc_destroy(struct xfrm_state *x) kfree(x->coaddr); if (x->inner_mode) xfrm_put_mode(x->inner_mode); + if (x->inner_mode_iaf) + xfrm_put_mode(x->inner_mode_iaf); if (x->outer_mode) xfrm_put_mode(x->outer_mode); if (x->type) { @@ -523,6 +525,8 @@ struct xfrm_state *xfrm_state_alloc(void) x->lft.hard_packet_limit = XFRM_INF; x->replay_maxage = 0; x->replay_maxdiff = 0; + x->inner_mode = NULL; + x->inner_mode_iaf = NULL; spin_lock_init(&x->lock); } return x; @@ -796,7 +800,7 @@ xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, selector. */ if (x->km.state == XFRM_STATE_VALID) { - if (!xfrm_selector_match(&x->sel, fl, x->sel.family) || + if ((x->sel.family && !xfrm_selector_match(&x->sel, fl, x->sel.family)) || !security_xfrm_state_pol_flow_match(x, pol, fl)) continue; if (!best || @@ -1944,6 +1948,7 @@ int xfrm_state_mtu(struct xfrm_state *x, int mtu) int xfrm_init_state(struct xfrm_state *x) { struct xfrm_state_afinfo *afinfo; + struct xfrm_mode *inner_mode; int family = x->props.family; int err; @@ -1962,13 +1967,48 @@ int xfrm_init_state(struct xfrm_state *x) goto error; err = -EPROTONOSUPPORT; - x->inner_mode = xfrm_get_mode(x->props.mode, x->sel.family); - if (x->inner_mode == NULL) - goto error; - if (!(x->inner_mode->flags & XFRM_MODE_FLAG_TUNNEL) && - family != x->sel.family) - goto error; + if (x->sel.family != AF_UNSPEC) { + inner_mode = xfrm_get_mode(x->props.mode, x->sel.family); + if (inner_mode == NULL) + goto error; + + if (!(inner_mode->flags & XFRM_MODE_FLAG_TUNNEL) && + family != x->sel.family) { + xfrm_put_mode(inner_mode); + goto error; + } + + x->inner_mode = inner_mode; + } else { + struct xfrm_mode *inner_mode_iaf; + + inner_mode = xfrm_get_mode(x->props.mode, AF_INET); + if (inner_mode == NULL) + goto error; + + if (!(inner_mode->flags & XFRM_MODE_FLAG_TUNNEL)) { + xfrm_put_mode(inner_mode); + goto error; + } + + inner_mode_iaf = xfrm_get_mode(x->props.mode, AF_INET6); + if (inner_mode_iaf == NULL) + goto error; + + if (!(inner_mode_iaf->flags & XFRM_MODE_FLAG_TUNNEL)) { + xfrm_put_mode(inner_mode_iaf); + goto error; + } + + if (x->props.family == AF_INET) { + x->inner_mode = inner_mode; + x->inner_mode_iaf = inner_mode_iaf; + } else { + x->inner_mode = inner_mode_iaf; + x->inner_mode_iaf = inner_mode; + } + } x->type = xfrm_get_type(x->id.proto, family); if (x->type == NULL) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index f971ca5645f8..5d96f2728dc6 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -288,12 +288,9 @@ static void copy_from_user_state(struct xfrm_state *x, struct xfrm_usersa_info * memcpy(&x->props.saddr, &p->saddr, sizeof(x->props.saddr)); x->props.flags = p->flags; - /* - * Set inner address family if the KM left it as zero. - * See comment in validate_tmpl. - */ - if (!x->sel.family) + if (x->props.mode == XFRM_MODE_TRANSPORT) x->sel.family = p->family; + } /* -- cgit v1.2.3-59-g8ed1b From 85a793533524f333e8d630dc22450e574b7e08d2 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 24 Mar 2008 20:06:24 -0700 Subject: [SPARC64]: Make save_stack_trace() more efficient. Doing a 'flushw' every stack trace capture creates so much overhead that it makes lockdep next to unusable. We only care about the frame pointer chain and the function caller program counters, so flush those by hand to the stack frame. This is significantly more efficient than a 'flushw' because: 1) We only save 16 bytes per active register window to the stack. 2) This doesn't push the entire register window context of the current call chain out of the cpu, forcing register window fill traps as we return back down. Note that we can't use 'restore' and 'save' instructions to move around the register windows because that wouldn't work on Niagara processors. They optimize 'save' into a new register window by simply clearing out the registers instead of pulling them in from the on-chip register window backing store. Based upon a report by Tom Callaway. Signed-off-by: David S. Miller --- arch/sparc64/kernel/entry.S | 30 ++++++++++++++++++++++++++++++ arch/sparc64/kernel/stacktrace.c | 4 +++- include/asm-sparc64/stacktrace.h | 6 ++++++ 3 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 include/asm-sparc64/stacktrace.h (limited to 'include') diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S index 6be4d2d2904e..49eca4b1cf25 100644 --- a/arch/sparc64/kernel/entry.S +++ b/arch/sparc64/kernel/entry.S @@ -1705,6 +1705,36 @@ __flushw_user: 2: retl nop + /* Flush %fp and %i7 to the stack for all register + * windows active inside of the cpu. This allows + * show_stack_trace() to avoid using an expensive + * 'flushw'. + */ + .globl stack_trace_flush + .type stack_trace_flush,#function +stack_trace_flush: + rdpr %pstate, %o0 + wrpr %o0, PSTATE_IE, %pstate + + rdpr %cwp, %g1 + rdpr %canrestore, %g2 + sub %g1, 1, %g3 + +1: brz,pn %g2, 2f + sub %g2, 1, %g2 + wrpr %g3, %cwp + stx %fp, [%sp + STACK_BIAS + RW_V9_I6] + stx %i7, [%sp + STACK_BIAS + RW_V9_I7] + ba,pt %xcc, 1b + sub %g3, 1, %g3 + +2: wrpr %g1, %cwp + wrpr %o0, %pstate + + retl + nop + .size stack_trace_flush,.-stack_trace_flush + #ifdef CONFIG_SMP .globl hard_smp_processor_id hard_smp_processor_id: diff --git a/arch/sparc64/kernel/stacktrace.c b/arch/sparc64/kernel/stacktrace.c index 47f92a59be18..84d39e873e88 100644 --- a/arch/sparc64/kernel/stacktrace.c +++ b/arch/sparc64/kernel/stacktrace.c @@ -2,13 +2,15 @@ #include #include #include +#include void save_stack_trace(struct stack_trace *trace) { unsigned long ksp, fp, thread_base; struct thread_info *tp = task_thread_info(current); - flushw_all(); + stack_trace_flush(); + __asm__ __volatile__( "mov %%fp, %0" : "=r" (ksp) diff --git a/include/asm-sparc64/stacktrace.h b/include/asm-sparc64/stacktrace.h new file mode 100644 index 000000000000..6cee39adf6d6 --- /dev/null +++ b/include/asm-sparc64/stacktrace.h @@ -0,0 +1,6 @@ +#ifndef _SPARC64_STACKTRACE_H +#define _SPARC64_STACKTRACE_H + +extern void stack_trace_flush(void); + +#endif /* _SPARC64_STACKTRACE_H */ -- cgit v1.2.3-59-g8ed1b From 606d5b19391476f71e10ccce5b376f7071d11aba Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Tue, 25 Mar 2008 21:13:22 -0700 Subject: [SPARC64]: Adjust {TLBTEMP,TSBMAP}_BASE. Move them further from the main kernel image area to facilitate larger kernel sizes. Adjust comments to match. Signed-off-by: David S. Miller --- include/asm-sparc64/pgtable.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index 3167ccff64f8..95303f5be86b 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -23,9 +23,9 @@ #include #include -/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB). - * The page copy blockops can use 0x2000000 to 0x4000000. - * The TSB is mapped in the 0x4000000 to 0x6000000 range. +/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). + * The page copy blockops can use 0x6000000 to 0x8000000. + * The TSB is mapped in the 0x8000000 to 0xa000000 range. * The PROM resides in an area spanning 0xf0000000 to 0x100000000. * The vmalloc area spans 0x100000000 to 0x200000000. * Since modules need to be in the lowest 32-bits of the address space, @@ -33,8 +33,8 @@ * There is a single static kernel PMD which maps from 0x0 to address * 0x400000000. */ -#define TLBTEMP_BASE _AC(0x0000000002000000,UL) -#define TSBMAP_BASE _AC(0x0000000004000000,UL) +#define TLBTEMP_BASE _AC(0x0000000006000000,UL) +#define TSBMAP_BASE _AC(0x0000000008000000,UL) #define MODULES_VADDR _AC(0x0000000010000000,UL) #define MODULES_LEN _AC(0x00000000e0000000,UL) #define MODULES_END _AC(0x00000000f0000000,UL) -- cgit v1.2.3-59-g8ed1b From 8b78cf602fd3bd97c0080edd22fe8fd5d0fa7832 Mon Sep 17 00:00:00 2001 From: Yi Yang Date: Mon, 25 Feb 2008 08:46:12 +0800 Subject: cpuidle: fix cpuidle time and usage overflow cpuidle C-state sysfs node time and usage are very easy to overflow because they are all of unsigned int type, time will overflow within about two hours, usage will take longer time to overflow, but they are increasing for ever. This patch will convert them to unsigned long long. Signed-off-by: Yi Yang Acked-by: Venkatesh Pallipadi Signed-off-by: Len Brown --- drivers/cpuidle/cpuidle.c | 2 +- drivers/cpuidle/sysfs.c | 10 ++++++++-- include/linux/cpuidle.h | 4 ++-- 3 files changed, 11 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index d73663a52324..d42deb310ac7 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -67,7 +67,7 @@ static void cpuidle_idle_call(void) /* enter the state and update stats */ dev->last_residency = target_state->enter(dev, target_state); dev->last_state = target_state; - target_state->time += dev->last_residency; + target_state->time += (unsigned long long)dev->last_residency; target_state->usage++; /* give the governor an opportunity to reflect on the outcome */ diff --git a/drivers/cpuidle/sysfs.c b/drivers/cpuidle/sysfs.c index 69102ca05685..e949618b9be0 100644 --- a/drivers/cpuidle/sysfs.c +++ b/drivers/cpuidle/sysfs.c @@ -218,6 +218,12 @@ static ssize_t show_state_##_name(struct cpuidle_state *state, char *buf) \ return sprintf(buf, "%u\n", state->_name);\ } +#define define_show_state_ull_function(_name) \ +static ssize_t show_state_##_name(struct cpuidle_state *state, char *buf) \ +{ \ + return sprintf(buf, "%llu\n", state->_name);\ +} + #define define_show_state_str_function(_name) \ static ssize_t show_state_##_name(struct cpuidle_state *state, char *buf) \ { \ @@ -228,8 +234,8 @@ static ssize_t show_state_##_name(struct cpuidle_state *state, char *buf) \ define_show_state_function(exit_latency) define_show_state_function(power_usage) -define_show_state_function(usage) -define_show_state_function(time) +define_show_state_ull_function(usage) +define_show_state_ull_function(time) define_show_state_str_function(name) define_show_state_str_function(desc) diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h index 6b72a4584086..51e6b1e520e6 100644 --- a/include/linux/cpuidle.h +++ b/include/linux/cpuidle.h @@ -38,8 +38,8 @@ struct cpuidle_state { unsigned int power_usage; /* in mW */ unsigned int target_residency; /* in US */ - unsigned int usage; - unsigned int time; /* in US */ + unsigned long long usage; + unsigned long long time; /* in US */ int (*enter) (struct cpuidle_device *dev, struct cpuidle_state *state); -- cgit v1.2.3-59-g8ed1b From 3d5ae6b69eacfac025021998d2ce159768edcfe1 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Tue, 25 Mar 2008 21:51:40 -0700 Subject: [SPARC64]: Fix sparse warnings in arch/sparc64/kernel/{cpu,setup}.c We create a local header file entry.h, under arch/sparc64/kernel/, that we can use to declare routines either defined in assembler or only invoked from assembler. As well as other data objects which are private to the inner sparc64 kernel arch code. Signed-off-by: David S. Miller --- arch/sparc64/kernel/cpu.c | 10 ++++++---- arch/sparc64/kernel/entry.h | 15 +++++++++++++++ arch/sparc64/kernel/setup.c | 5 ++--- arch/sparc64/mm/init.c | 1 + include/asm-sparc64/cpudata.h | 2 ++ 5 files changed, 26 insertions(+), 7 deletions(-) create mode 100644 arch/sparc64/kernel/entry.h (limited to 'include') diff --git a/arch/sparc64/kernel/cpu.c b/arch/sparc64/kernel/cpu.c index dd5d28e3d798..0097c08dc600 100644 --- a/arch/sparc64/kernel/cpu.c +++ b/arch/sparc64/kernel/cpu.c @@ -15,6 +15,8 @@ #include #include +#include "entry.h" + DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; struct cpu_iu_info { @@ -65,8 +67,6 @@ static struct cpu_iu_info linux_sparc_chips[] = { char *sparc_cpu_type; char *sparc_fpu_type; -unsigned int fsr_storage; - static void __init sun4v_cpu_probe(void) { switch (sun4v_chip_type) { @@ -94,8 +94,10 @@ void __init cpu_probe(void) unsigned long ver, fpu_vers, manuf, impl, fprs; int i; - if (tlb_type == hypervisor) - return sun4v_cpu_probe(); + if (tlb_type == hypervisor) { + sun4v_cpu_probe(); + return; + } fprs = fprs_read(); fprs_write(FPRS_FEF); diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h new file mode 100644 index 000000000000..bfcd1b8d23dc --- /dev/null +++ b/arch/sparc64/kernel/entry.h @@ -0,0 +1,15 @@ +#ifndef _ENTRY_H +#define _ENTRY_H + +#include + +extern char *sparc_cpu_type; +extern char *sparc_fpu_type; + +extern void __init per_cpu_patch(void); +extern void __init sun4v_patch(void); +extern void __init boot_cpu_id_too_large(int cpu); +extern unsigned int dcache_parity_tl1_occurred; +extern unsigned int icache_parity_tl1_occurred; + +#endif /* _ENTRY_H */ diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c index d036dbe72864..6acb4c51cfe4 100644 --- a/arch/sparc64/kernel/setup.c +++ b/arch/sparc64/kernel/setup.c @@ -51,6 +51,8 @@ #include #endif +#include "entry.h" + /* Used to synchronize accesses to NatSemi SUPER I/O chip configure * operations in asm/ns87303.h */ @@ -335,9 +337,6 @@ void __init setup_arch(char **cmdline_p) /* BUFFER is PAGE_SIZE bytes long. */ -extern char *sparc_cpu_type; -extern char *sparc_fpu_type; - extern void smp_info(struct seq_file *); extern void smp_bogo(struct seq_file *); extern void mmu_info(struct seq_file *); diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c index 466fd6cffac9..fced6dfe77a8 100644 --- a/arch/sparc64/mm/init.c +++ b/arch/sparc64/mm/init.c @@ -46,6 +46,7 @@ #include #include #include +#include #define MAX_PHYS_ADDRESS (1UL << 42UL) #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL) diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h index 542421460a12..532975ecfe10 100644 --- a/include/asm-sparc64/cpudata.h +++ b/include/asm-sparc64/cpudata.h @@ -86,6 +86,8 @@ extern struct trap_per_cpu trap_block[NR_CPUS]; extern void init_cur_cpu_trap(struct thread_info *); extern void setup_tba(void); extern int ncpus_probed; +extern void __init cpu_probe(void); +extern const struct seq_operations cpuinfo_op; extern unsigned long real_hard_smp_processor_id(void); -- cgit v1.2.3-59-g8ed1b From 99cd220133cdf2a559529d522a78b2ebc1bef2d8 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 26 Mar 2008 00:19:43 -0700 Subject: [SPARC64]: Fix sparse errors in arch/sparc64/kernel/traps.c Add 'UL' markers to DCU_* macros. Declare C functions called from assembler in entry.h Declare C functions called from within the sparc64 arch code in include/asm-sparc64/*.h headers as appropriate. Remove unused routines in traps.c Signed-off-by: David S. Miller --- arch/sparc64/kernel/entry.h | 141 ++++++++++++++++++++++++++++++++++++++++++ arch/sparc64/kernel/traps.c | 49 +-------------- arch/sparc64/mm/init.c | 4 -- include/asm-sparc64/dcu.h | 41 ++++++------ include/asm-sparc64/pgtable.h | 2 + 5 files changed, 167 insertions(+), 70 deletions(-) (limited to 'include') diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h index bfcd1b8d23dc..a5084d6821ba 100644 --- a/arch/sparc64/kernel/entry.h +++ b/arch/sparc64/kernel/entry.h @@ -2,6 +2,7 @@ #define _ENTRY_H #include +#include extern char *sparc_cpu_type; extern char *sparc_fpu_type; @@ -12,4 +13,144 @@ extern void __init boot_cpu_id_too_large(int cpu); extern unsigned int dcache_parity_tl1_occurred; extern unsigned int icache_parity_tl1_occurred; +extern void bad_trap_tl1(struct pt_regs *regs, long lvl); + +extern void do_fpe_common(struct pt_regs *regs); +extern void do_fpieee(struct pt_regs *regs); +extern void do_fpother(struct pt_regs *regs); +extern void do_tof(struct pt_regs *regs); +extern void do_div0(struct pt_regs *regs); +extern void do_illegal_instruction(struct pt_regs *regs); +extern void mem_address_unaligned(struct pt_regs *regs, + unsigned long sfar, + unsigned long sfsr); +extern void sun4v_do_mna(struct pt_regs *regs, + unsigned long addr, + unsigned long type_ctx); +extern void do_privop(struct pt_regs *regs); +extern void do_privact(struct pt_regs *regs); +extern void do_cee(struct pt_regs *regs); +extern void do_cee_tl1(struct pt_regs *regs); +extern void do_dae_tl1(struct pt_regs *regs); +extern void do_iae_tl1(struct pt_regs *regs); +extern void do_div0_tl1(struct pt_regs *regs); +extern void do_fpdis_tl1(struct pt_regs *regs); +extern void do_fpieee_tl1(struct pt_regs *regs); +extern void do_fpother_tl1(struct pt_regs *regs); +extern void do_ill_tl1(struct pt_regs *regs); +extern void do_irq_tl1(struct pt_regs *regs); +extern void do_lddfmna_tl1(struct pt_regs *regs); +extern void do_stdfmna_tl1(struct pt_regs *regs); +extern void do_paw(struct pt_regs *regs); +extern void do_paw_tl1(struct pt_regs *regs); +extern void do_vaw(struct pt_regs *regs); +extern void do_vaw_tl1(struct pt_regs *regs); +extern void do_tof_tl1(struct pt_regs *regs); +extern void do_getpsr(struct pt_regs *regs); + +extern void spitfire_insn_access_exception(struct pt_regs *regs, + unsigned long sfsr, + unsigned long sfar); +extern void spitfire_insn_access_exception_tl1(struct pt_regs *regs, + unsigned long sfsr, + unsigned long sfar); +extern void spitfire_data_access_exception(struct pt_regs *regs, + unsigned long sfsr, + unsigned long sfar); +extern void spitfire_data_access_exception_tl1(struct pt_regs *regs, + unsigned long sfsr, + unsigned long sfar); +extern void spitfire_access_error(struct pt_regs *regs, + unsigned long status_encoded, + unsigned long afar); + +extern void cheetah_fecc_handler(struct pt_regs *regs, + unsigned long afsr, + unsigned long afar); +extern void cheetah_cee_handler(struct pt_regs *regs, + unsigned long afsr, + unsigned long afar); +extern void cheetah_deferred_handler(struct pt_regs *regs, + unsigned long afsr, + unsigned long afar); +extern void cheetah_plus_parity_error(int type, struct pt_regs *regs); + +extern void sun4v_insn_access_exception(struct pt_regs *regs, + unsigned long addr, + unsigned long type_ctx); +extern void sun4v_insn_access_exception_tl1(struct pt_regs *regs, + unsigned long addr, + unsigned long type_ctx); +extern void sun4v_data_access_exception(struct pt_regs *regs, + unsigned long addr, + unsigned long type_ctx); +extern void sun4v_data_access_exception_tl1(struct pt_regs *regs, + unsigned long addr, + unsigned long type_ctx); +extern void sun4v_resum_error(struct pt_regs *regs, + unsigned long offset); +extern void sun4v_resum_overflow(struct pt_regs *regs); +extern void sun4v_nonresum_error(struct pt_regs *regs, + unsigned long offset); +extern void sun4v_nonresum_overflow(struct pt_regs *regs); + +extern unsigned long sun4v_err_itlb_vaddr; +extern unsigned long sun4v_err_itlb_ctx; +extern unsigned long sun4v_err_itlb_pte; +extern unsigned long sun4v_err_itlb_error; + +extern void sun4v_itlb_error_report(struct pt_regs *regs, int tl); + +extern unsigned long sun4v_err_dtlb_vaddr; +extern unsigned long sun4v_err_dtlb_ctx; +extern unsigned long sun4v_err_dtlb_pte; +extern unsigned long sun4v_err_dtlb_error; + +extern void sun4v_dtlb_error_report(struct pt_regs *regs, int tl); +extern void hypervisor_tlbop_error(unsigned long err, + unsigned long op); +extern void hypervisor_tlbop_error_xcall(unsigned long err, + unsigned long op); + +/* WARNING: The error trap handlers in assembly know the precise + * layout of the following structure. + * + * C-level handlers in traps.c use this information to log the + * error and then determine how to recover (if possible). + */ +struct cheetah_err_info { +/*0x00*/u64 afsr; +/*0x08*/u64 afar; + + /* D-cache state */ +/*0x10*/u64 dcache_data[4]; /* The actual data */ +/*0x30*/u64 dcache_index; /* D-cache index */ +/*0x38*/u64 dcache_tag; /* D-cache tag/valid */ +/*0x40*/u64 dcache_utag; /* D-cache microtag */ +/*0x48*/u64 dcache_stag; /* D-cache snooptag */ + + /* I-cache state */ +/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */ +/*0x90*/u64 icache_index; /* I-cache index */ +/*0x98*/u64 icache_tag; /* I-cache phys tag */ +/*0xa0*/u64 icache_utag; /* I-cache microtag */ +/*0xa8*/u64 icache_stag; /* I-cache snooptag */ +/*0xb0*/u64 icache_upper; /* I-cache upper-tag */ +/*0xb8*/u64 icache_lower; /* I-cache lower-tag */ + + /* E-cache state */ +/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */ +/*0xe0*/u64 ecache_index; /* E-cache index */ +/*0xe8*/u64 ecache_tag; /* E-cache tag/state */ + +/*0xf0*/u64 __pad[32 - 30]; +}; +#define CHAFSR_INVALID ((u64)-1L) + +/* This is allocated at boot time based upon the largest hardware + * cpu ID in the system. We allocate two entries per cpu, one for + * TL==0 logging and one for TL >= 1 logging. + */ +extern struct cheetah_err_info *cheetah_error_log; + #endif /* _ENTRY_H */ diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c index 007f5317c0de..96da847023f3 100644 --- a/arch/sparc64/kernel/traps.c +++ b/arch/sparc64/kernel/traps.c @@ -42,6 +42,7 @@ #endif #include +#include "entry.h" /* When an irrecoverable trap occurs at tl > 0, the trap entry * code logs the trap state registers at every level in the trap @@ -77,11 +78,6 @@ static void dump_tl1_traplog(struct tl1_traplog *p) } } -void do_call_debug(struct pt_regs *regs) -{ - notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT); -} - void bad_trap(struct pt_regs *regs, long lvl) { char buffer[32]; @@ -550,41 +546,6 @@ static unsigned long ecache_flush_physbase; static unsigned long ecache_flush_linesize; static unsigned long ecache_flush_size; -/* WARNING: The error trap handlers in assembly know the precise - * layout of the following structure. - * - * C-level handlers below use this information to log the error - * and then determine how to recover (if possible). - */ -struct cheetah_err_info { -/*0x00*/u64 afsr; -/*0x08*/u64 afar; - - /* D-cache state */ -/*0x10*/u64 dcache_data[4]; /* The actual data */ -/*0x30*/u64 dcache_index; /* D-cache index */ -/*0x38*/u64 dcache_tag; /* D-cache tag/valid */ -/*0x40*/u64 dcache_utag; /* D-cache microtag */ -/*0x48*/u64 dcache_stag; /* D-cache snooptag */ - - /* I-cache state */ -/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */ -/*0x90*/u64 icache_index; /* I-cache index */ -/*0x98*/u64 icache_tag; /* I-cache phys tag */ -/*0xa0*/u64 icache_utag; /* I-cache microtag */ -/*0xa8*/u64 icache_stag; /* I-cache snooptag */ -/*0xb0*/u64 icache_upper; /* I-cache upper-tag */ -/*0xb8*/u64 icache_lower; /* I-cache lower-tag */ - - /* E-cache state */ -/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */ -/*0xe0*/u64 ecache_index; /* E-cache index */ -/*0xe8*/u64 ecache_tag; /* E-cache tag/state */ - -/*0xf0*/u64 __pad[32 - 30]; -}; -#define CHAFSR_INVALID ((u64)-1L) - /* This table is ordered in priority of errors and matches the * AFAR overwrite policy as well. */ @@ -758,10 +719,6 @@ static struct afsr_error_table __jalapeno_error_table[] = { static struct afsr_error_table *cheetah_error_table; static unsigned long cheetah_afsr_errors; -/* This is allocated at boot time based upon the largest hardware - * cpu ID in the system. We allocate two entries per cpu, one for - * TL==0 logging and one for TL >= 1 logging. - */ struct cheetah_err_info *cheetah_error_log; static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr) @@ -2102,7 +2059,7 @@ void do_div0(struct pt_regs *regs) force_sig_info(SIGFPE, &info, current); } -void instruction_dump (unsigned int *pc) +static void instruction_dump(unsigned int *pc) { int i; @@ -2115,7 +2072,7 @@ void instruction_dump (unsigned int *pc) printk("\n"); } -static void user_instruction_dump (unsigned int __user *pc) +static void user_instruction_dump(unsigned int __user *pc) { int i; unsigned int buf[9]; diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c index fced6dfe77a8..f37078d96407 100644 --- a/arch/sparc64/mm/init.c +++ b/arch/sparc64/mm/init.c @@ -1274,10 +1274,6 @@ void __cpuinit sun4v_ktsb_register(void) /* paging_init() sets up the page tables */ -extern void cheetah_ecache_flush_init(void); -extern void sun4v_patch_tlb_handlers(void); - -extern void cpu_probe(void); extern void central_probe(void); static unsigned long last_valid_pfn; diff --git a/include/asm-sparc64/dcu.h b/include/asm-sparc64/dcu.h index ecbed2ae548f..0f704e106a1b 100644 --- a/include/asm-sparc64/dcu.h +++ b/include/asm-sparc64/dcu.h @@ -1,26 +1,27 @@ -/* $Id: dcu.h,v 1.2 2001/03/01 23:23:33 davem Exp $ */ #ifndef _SPARC64_DCU_H #define _SPARC64_DCU_H +#include + /* UltraSparc-III Data Cache Unit Control Register */ -#define DCU_CP 0x0002000000000000 /* Physical Cache Enable w/o mmu*/ -#define DCU_CV 0x0001000000000000 /* Virtual Cache Enable w/o mmu */ -#define DCU_ME 0x0000800000000000 /* NC-store Merging Enable */ -#define DCU_RE 0x0000400000000000 /* RAW bypass Enable */ -#define DCU_PE 0x0000200000000000 /* PCache Enable */ -#define DCU_HPE 0x0000100000000000 /* HW prefetch Enable */ -#define DCU_SPE 0x0000080000000000 /* SW prefetch Enable */ -#define DCU_SL 0x0000040000000000 /* Secondary load steering Enab */ -#define DCU_WE 0x0000020000000000 /* WCache enable */ -#define DCU_PM 0x000001fe00000000 /* PA Watchpoint Byte Mask */ -#define DCU_VM 0x00000001fe000000 /* VA Watchpoint Byte Mask */ -#define DCU_PR 0x0000000001000000 /* PA Watchpoint Read Enable */ -#define DCU_PW 0x0000000000800000 /* PA Watchpoint Write Enable */ -#define DCU_VR 0x0000000000400000 /* VA Watchpoint Read Enable */ -#define DCU_VW 0x0000000000200000 /* VA Watchpoint Write Enable */ -#define DCU_DM 0x0000000000000008 /* DMMU Enable */ -#define DCU_IM 0x0000000000000004 /* IMMU Enable */ -#define DCU_DC 0x0000000000000002 /* Data Cache Enable */ -#define DCU_IC 0x0000000000000001 /* Instruction Cache Enable */ +#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */ +#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */ +#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */ +#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */ +#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */ +#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */ +#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */ +#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/ +#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */ +#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */ +#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */ +#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */ +#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/ +#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */ +#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/ +#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */ +#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */ +#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */ +#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */ #endif /* _SPARC64_DCU_H */ diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index 95303f5be86b..549e45266b68 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -761,6 +761,8 @@ extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, extern void pgtable_cache_init(void); extern void sun4v_register_fault_status(void); extern void sun4v_ktsb_register(void); +extern void __init cheetah_ecache_flush_init(void); +extern void sun4v_patch_tlb_handlers(void); extern unsigned long cmdline_memory_size; -- cgit v1.2.3-59-g8ed1b From d91aa123b4b96e57680a39fb9dfd9722f8df3c7e Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 26 Mar 2008 00:37:51 -0700 Subject: [SPARC64]: Fix sparse warnings in arch/sparc64/kernel/irq.c Signed-off-by: David S. Miller --- arch/sparc64/kernel/entry.h | 27 +++++++++++++++++++++++++++ arch/sparc64/kernel/irq.c | 21 ++------------------- include/asm-sparc64/irq.h | 1 + 3 files changed, 30 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h index a5084d6821ba..e66d94c7caff 100644 --- a/arch/sparc64/kernel/entry.h +++ b/arch/sparc64/kernel/entry.h @@ -153,4 +153,31 @@ struct cheetah_err_info { */ extern struct cheetah_err_info *cheetah_error_log; +/* UPA nodes send interrupt packet to UltraSparc with first data reg + * value low 5 (7 on Starfire) bits holding the IRQ identifier being + * delivered. We must translate this into a non-vector IRQ so we can + * set the softint on this cpu. + * + * To make processing these packets efficient and race free we use + * an array of irq buckets below. The interrupt vector handler in + * entry.S feeds incoming packets into per-cpu pil-indexed lists. + * + * If you make changes to ino_bucket, please update hand coded assembler + * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S + */ +struct ino_bucket { +/*0x00*/unsigned long __irq_chain_pa; + + /* Virtual interrupt number assigned to this INO. */ +/*0x08*/unsigned int __virt_irq; +/*0x0c*/unsigned int __pad; +}; + +extern struct ino_bucket *ivector_table; +extern unsigned long ivector_table_pa; + +extern void handler_irq(int irq, struct pt_regs *regs); +extern void init_irqwork_curcpu(void); +extern void __cpuinit sun4v_register_mondo_queues(int this_cpu); + #endif /* _ENTRY_H */ diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c index 5ec06c8c7fea..eb88bd6e674e 100644 --- a/arch/sparc64/kernel/irq.c +++ b/arch/sparc64/kernel/irq.c @@ -44,27 +44,10 @@ #include #include -/* UPA nodes send interrupt packet to UltraSparc with first data reg - * value low 5 (7 on Starfire) bits holding the IRQ identifier being - * delivered. We must translate this into a non-vector IRQ so we can - * set the softint on this cpu. - * - * To make processing these packets efficient and race free we use - * an array of irq buckets below. The interrupt vector handler in - * entry.S feeds incoming packets into per-cpu pil-indexed lists. - * - * If you make changes to ino_bucket, please update hand coded assembler - * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S - */ -struct ino_bucket { -/*0x00*/unsigned long __irq_chain_pa; - - /* Virtual interrupt number assigned to this INO. */ -/*0x08*/unsigned int __virt_irq; -/*0x0c*/unsigned int __pad; -}; +#include "entry.h" #define NUM_IVECS (IMAP_INR + 1) + struct ino_bucket *ivector_table; unsigned long ivector_table_pa; diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index 30cb76b47be1..0bb9bf531745 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -64,6 +64,7 @@ extern unsigned char virt_irq_alloc(unsigned int dev_handle, extern void virt_irq_free(unsigned int virt_irq); #endif +extern void __init init_IRQ(void); extern void fixup_irqs(void); static inline void set_softint(unsigned long bits) -- cgit v1.2.3-59-g8ed1b From cf3d7c1ef418863376d556c48c214cb828623584 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 26 Mar 2008 01:11:55 -0700 Subject: [SPARC64]: Fix sparse warnings in arch/sparc64/kernel/time.c Signed-off-by: David S. Miller --- arch/sparc64/kernel/entry.h | 2 ++ arch/sparc64/kernel/smp.c | 3 ++- arch/sparc64/kernel/time.c | 66 +++++++++++++++++++++++++++------------------ include/asm-sparc64/timer.h | 9 ++++--- 4 files changed, 49 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h index 0d0de9c32a80..4e238a11bdfe 100644 --- a/arch/sparc64/kernel/entry.h +++ b/arch/sparc64/kernel/entry.h @@ -14,6 +14,8 @@ extern void __init boot_cpu_id_too_large(int cpu); extern unsigned int dcache_parity_tl1_occurred; extern unsigned int icache_parity_tl1_occurred; +extern void timer_interrupt(int irq, struct pt_regs *regs); + extern asmlinkage void syscall_trace(struct pt_regs *regs, int syscall_exit_p); diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c index 5a1126b363a4..59f020d69d4c 100644 --- a/arch/sparc64/kernel/smp.c +++ b/arch/sparc64/kernel/smp.c @@ -1,6 +1,6 @@ /* smp.c: Sparc64 SMP support. * - * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) + * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) */ #include @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c index d204f1ab1d4c..e5d238970c7e 100644 --- a/arch/sparc64/kernel/time.c +++ b/arch/sparc64/kernel/time.c @@ -1,7 +1,6 @@ -/* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $ - * time.c: UltraSparc timer and TOD clock support. +/* time.c: UltraSparc timer and TOD clock support. * - * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net) * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) * * Based largely on code which is: @@ -48,6 +47,8 @@ #include #include +#include "entry.h" + DEFINE_SPINLOCK(mostek_lock); DEFINE_SPINLOCK(rtc_lock); void __iomem *mstk48t02_regs = NULL; @@ -508,6 +509,37 @@ static int __init has_low_battery(void) return (data1 == data2); /* Was the write blocked? */ } +static void __init mostek_set_system_time(void __iomem *mregs) +{ + unsigned int year, mon, day, hour, min, sec; + u8 tmp; + + spin_lock_irq(&mostek_lock); + + /* Traditional Mostek chip. */ + tmp = mostek_read(mregs + MOSTEK_CREG); + tmp |= MSTK_CREG_READ; + mostek_write(mregs + MOSTEK_CREG, tmp); + + sec = MSTK_REG_SEC(mregs); + min = MSTK_REG_MIN(mregs); + hour = MSTK_REG_HOUR(mregs); + day = MSTK_REG_DOM(mregs); + mon = MSTK_REG_MONTH(mregs); + year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) ); + + xtime.tv_sec = mktime(year, mon, day, hour, min, sec); + xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); + set_normalized_timespec(&wall_to_monotonic, + -xtime.tv_sec, -xtime.tv_nsec); + + tmp = mostek_read(mregs + MOSTEK_CREG); + tmp &= ~MSTK_CREG_READ; + mostek_write(mregs + MOSTEK_CREG, tmp); + + spin_unlock_irq(&mostek_lock); +} + /* Probe for the real time clock chip. */ static void __init set_system_time(void) { @@ -520,7 +552,6 @@ static void __init set_system_time(void) unsigned long dregs = 0UL; void __iomem *bregs = 0UL; #endif - u8 tmp; if (!mregs && !dregs && !bregs) { prom_printf("Something wrong, clock regs not mapped yet.\n"); @@ -528,20 +559,11 @@ static void __init set_system_time(void) } if (mregs) { - spin_lock_irq(&mostek_lock); - - /* Traditional Mostek chip. */ - tmp = mostek_read(mregs + MOSTEK_CREG); - tmp |= MSTK_CREG_READ; - mostek_write(mregs + MOSTEK_CREG, tmp); + mostek_set_system_time(mregs); + return; + } - sec = MSTK_REG_SEC(mregs); - min = MSTK_REG_MIN(mregs); - hour = MSTK_REG_HOUR(mregs); - day = MSTK_REG_DOM(mregs); - mon = MSTK_REG_MONTH(mregs); - year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) ); - } else if (bregs) { + if (bregs) { unsigned char val = readb(bregs + 0x0e); unsigned int century; @@ -596,14 +618,6 @@ static void __init set_system_time(void) xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); - - if (mregs) { - tmp = mostek_read(mregs + MOSTEK_CREG); - tmp &= ~MSTK_CREG_READ; - mostek_write(mregs + MOSTEK_CREG, tmp); - - spin_unlock_irq(&mostek_lock); - } } /* davem suggests we keep this within the 4M locked kernel image */ @@ -1027,7 +1041,7 @@ void __init time_init(void) setup_clockevent_multiplier(clock); sparc64_clockevent.max_delta_ns = - clockevent_delta2ns(0x7fffffffffffffff, &sparc64_clockevent); + clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent); sparc64_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &sparc64_clockevent); diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h index ccbd69448866..5b779fd1f788 100644 --- a/include/asm-sparc64/timer.h +++ b/include/asm-sparc64/timer.h @@ -1,14 +1,13 @@ -/* $Id: timer.h,v 1.3 2000/05/09 17:40:15 davem Exp $ - * timer.h: System timer definitions for sun5. +/* timer.h: System timer definitions for sun5. * - * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net) */ #ifndef _SPARC64_TIMER_H #define _SPARC64_TIMER_H #include - +#include struct sparc64_tick_ops { unsigned long (*get_tick)(void); @@ -25,5 +24,7 @@ struct sparc64_tick_ops { extern struct sparc64_tick_ops *tick_ops; extern unsigned long sparc64_get_clock_tick(unsigned int cpu); +extern void __devinit setup_sparc64_timer(void); +extern void __init time_init(void); #endif /* _SPARC64_TIMER_H */ -- cgit v1.2.3-59-g8ed1b From 9bbafce2eec190ef7e44b0eb1095ba17ce6ad3af Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 26 Mar 2008 19:02:47 +0900 Subject: sh: Fix occasional FPU register corruption under preempt. Presently with preempt enabled there's the possibility to be preempted after the TIF_USEDFPU test and the register save, leading to bogus state post-__switch_to(). Use an explicit preempt_disable()/enable() pair around unlazy_fpu()/clear_fpu() to avoid this. Follows the x86 change. Reported-by: Takuo Koguchi Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh2a/fpu.c | 1 + arch/sh/kernel/cpu/sh4/fpu.c | 1 + arch/sh/kernel/cpu/sh5/fpu.c | 1 + arch/sh/kernel/dump_task.c | 1 + arch/sh/kernel/process_32.c | 1 + arch/sh/kernel/signal_32.c | 1 + include/asm-sh/fpu.h | 32 ++++++++++++++++++-------------- include/asm-sh/processor.h | 1 - include/asm-sh/processor_32.h | 1 + include/asm-sh/processor_64.h | 1 + 10 files changed, 26 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c index ff99562456fb..5627c0b3ffa8 100644 --- a/arch/sh/kernel/cpu/sh2a/fpu.c +++ b/arch/sh/kernel/cpu/sh2a/fpu.c @@ -13,6 +13,7 @@ #include #include #include +#include /* The PR (precision) bit in the FP Status Register must be clear when * an frchg instruction is executed, otherwise the instruction is undefined. diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c index 817f9939cda6..8020796139f1 100644 --- a/arch/sh/kernel/cpu/sh4/fpu.c +++ b/arch/sh/kernel/cpu/sh4/fpu.c @@ -16,6 +16,7 @@ #include #include #include +#include /* The PR (precision) bit in the FP Status Register must be clear when * an frchg instruction is executed, otherwise the instruction is undefined. diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c index 30b76a94abf2..dd4f51ffb50e 100644 --- a/arch/sh/kernel/cpu/sh5/fpu.c +++ b/arch/sh/kernel/cpu/sh5/fpu.c @@ -17,6 +17,7 @@ #include #include #include +#include /* * Initially load the FPU with signalling NANS. This bit pattern diff --git a/arch/sh/kernel/dump_task.c b/arch/sh/kernel/dump_task.c index 4a8a4083ff0b..1db7ce0f25d4 100644 --- a/arch/sh/kernel/dump_task.c +++ b/arch/sh/kernel/dump_task.c @@ -1,5 +1,6 @@ #include #include +#include /* * Capture the user space registers if the task is not running (in user space) diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index 9ab1926b9d10..b98e37a1f54c 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -25,6 +25,7 @@ #include #include #include +#include static int hlt_counter; int ubc_usercnt = 0; diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c index f6b5fbfe75c4..f311551d9a05 100644 --- a/arch/sh/kernel/signal_32.c +++ b/arch/sh/kernel/signal_32.c @@ -29,6 +29,7 @@ #include #include #include +#include #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) diff --git a/include/asm-sh/fpu.h b/include/asm-sh/fpu.h index f8429880a270..f89abf5920d8 100644 --- a/include/asm-sh/fpu.h +++ b/include/asm-sh/fpu.h @@ -1,9 +1,8 @@ #ifndef __ASM_SH_FPU_H #define __ASM_SH_FPU_H -#define SR_FD 0x00008000 - #ifndef __ASSEMBLY__ +#include #include #ifdef CONFIG_SH_FPU @@ -28,18 +27,23 @@ extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); extern int do_fpu_inst(unsigned short, struct pt_regs *); -#define unlazy_fpu(tsk, regs) do { \ - if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ - save_fpu(tsk, regs); \ - } \ -} while (0) - -#define clear_fpu(tsk, regs) do { \ - if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ - clear_tsk_thread_flag(tsk, TIF_USEDFPU); \ - release_fpu(regs); \ - } \ -} while (0) +static inline void unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs) +{ + preempt_disable(); + if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) + save_fpu(tsk, regs); + preempt_enable(); +} + +static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs) +{ + preempt_disable(); + if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { + clear_tsk_thread_flag(tsk, TIF_USEDFPU); + release_fpu(regs); + } + preempt_enable(); +} #endif /* __ASSEMBLY__ */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 19fe47c1ca17..ec707b98e5b9 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -2,7 +2,6 @@ #define __ASM_SH_PROCESSOR_H #include -#include #ifndef __ASSEMBLY__ /* diff --git a/include/asm-sh/processor_32.h b/include/asm-sh/processor_32.h index df2d5b039ef4..c09305d6a9d9 100644 --- a/include/asm-sh/processor_32.h +++ b/include/asm-sh/processor_32.h @@ -70,6 +70,7 @@ extern struct sh_cpuinfo cpu_data[]; */ #define SR_DSP 0x00001000 #define SR_IMASK 0x000000f0 +#define SR_FD 0x00008000 /* * FPU structure and data diff --git a/include/asm-sh/processor_64.h b/include/asm-sh/processor_64.h index eda4bef448e9..88a2edf8fa5d 100644 --- a/include/asm-sh/processor_64.h +++ b/include/asm-sh/processor_64.h @@ -112,6 +112,7 @@ extern struct sh_cpuinfo cpu_data[]; #endif #define SR_IMASK 0x000000f0 +#define SR_FD 0x00008000 #define SR_SSTEP 0x08000000 #ifndef __ASSEMBLY__ -- cgit v1.2.3-59-g8ed1b From 138bed154eab2205b4ef93f02f5feb1edf6d8552 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 26 Mar 2008 19:09:21 +0900 Subject: sh: Fix TIF_USEDFPU clearing under FPU emulation. The unlazy_fpu() path calls in to save_fpu() if the task has TIF_USEDFPU set. save_fpu() being the crap API that it is has the side effect of clearing the flag itself, which presently doesn't happen if we're using FPU emulation. Fix this up for now, pending an overhaul in 2.6.26. Signed-off-by: Paul Mundt --- include/asm-sh/fpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-sh/fpu.h b/include/asm-sh/fpu.h index f89abf5920d8..91462fea1507 100644 --- a/include/asm-sh/fpu.h +++ b/include/asm-sh/fpu.h @@ -20,9 +20,14 @@ struct task_struct; extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); #else + #define release_fpu(regs) do { } while (0) #define grab_fpu(regs) do { } while (0) -#define save_fpu(tsk, regs) do { } while (0) + +static inline void save_fpu(struct task_struct *tsk, struct pt_regs *regs) +{ + clear_tsk_thread_flag(tsk, TIF_USEDFPU); +} #endif extern int do_fpu_inst(unsigned short, struct pt_regs *); -- cgit v1.2.3-59-g8ed1b From d546b67a940eb42a99f56b86c5cd8d47c8348c2a Mon Sep 17 00:00:00 2001 From: Suresh Siddha Date: Tue, 25 Mar 2008 17:39:12 -0700 Subject: x86: fix performance drop for glx fix the 3D performance drop reported at: http://bugzilla.kernel.org/show_bug.cgi?id=10328 fb drivers are using ioremap()/ioremap_nocache(), followed by mtrr_add with WC attribute. Recent changes in page attribute code made both ioremap()/ioremap_nocache() mappings as UC (instead of previous UC-). This breaks the graphics performance, as the effective memory type is UC instead of expected WC. The correct way to fix this is to add ioremap_wc() (which uses UC- in the absence of PAT kernel support and WC with PAT) and change all the fb drivers to use this new ioremap_wc() API. We can take this correct and longer route for post 2.6.25. For now, revert back to the UC- behavior for ioremap/ioremap_nocache. Signed-off-by: Suresh Siddha Signed-off-by: Venkatesh Pallipadi Cc: Arjan van de Ven Signed-off-by: Ingo Molnar --- arch/x86/mm/ioremap.c | 6 +++++- arch/x86/mm/pageattr.c | 2 +- include/asm-x86/pgtable.h | 2 ++ 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 4afaba0ed722..794895c6dcc9 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -137,7 +137,11 @@ static void __iomem *__ioremap(resource_size_t phys_addr, unsigned long size, switch (mode) { case IOR_MODE_UNCACHED: default: - prot = PAGE_KERNEL_NOCACHE; + /* + * FIXME: we will use UC MINUS for now, as video fb drivers + * depend on it. Upcoming ioremap_wc() will fix this behavior. + */ + prot = PAGE_KERNEL_UC_MINUS; break; case IOR_MODE_CACHED: prot = PAGE_KERNEL; diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 14e48b5a94ba..7b79f6be4e7d 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -771,7 +771,7 @@ static inline int change_page_attr_clear(unsigned long addr, int numpages, int set_memory_uc(unsigned long addr, int numpages) { return change_page_attr_set(addr, numpages, - __pgprot(_PAGE_PCD | _PAGE_PWT)); + __pgprot(_PAGE_PCD)); } EXPORT_SYMBOL(set_memory_uc); diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h index 174b87738714..9cf472aeb9ce 100644 --- a/include/asm-x86/pgtable.h +++ b/include/asm-x86/pgtable.h @@ -85,6 +85,7 @@ extern pteval_t __PAGE_KERNEL, __PAGE_KERNEL_EXEC; #define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW) #define __PAGE_KERNEL_EXEC_NOCACHE (__PAGE_KERNEL_EXEC | _PAGE_PCD | _PAGE_PWT) #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD | _PAGE_PWT) +#define __PAGE_KERNEL_UC_MINUS (__PAGE_KERNEL | _PAGE_PCD) #define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER) #define __PAGE_KERNEL_VSYSCALL_NOCACHE (__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT) #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) @@ -101,6 +102,7 @@ extern pteval_t __PAGE_KERNEL, __PAGE_KERNEL_EXEC; #define PAGE_KERNEL_EXEC MAKE_GLOBAL(__PAGE_KERNEL_EXEC) #define PAGE_KERNEL_RX MAKE_GLOBAL(__PAGE_KERNEL_RX) #define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE) +#define PAGE_KERNEL_UC_MINUS MAKE_GLOBAL(__PAGE_KERNEL_UC_MINUS) #define PAGE_KERNEL_EXEC_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_EXEC_NOCACHE) #define PAGE_KERNEL_LARGE MAKE_GLOBAL(__PAGE_KERNEL_LARGE) #define PAGE_KERNEL_LARGE_EXEC MAKE_GLOBAL(__PAGE_KERNEL_LARGE_EXEC) -- cgit v1.2.3-59-g8ed1b From 732c8bd590625e8bc0b88313b82930e336b2bec4 Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Wed, 26 Mar 2008 16:51:09 -0700 Subject: [IPSEC]: Fix BEET output The IPv6 BEET output function is incorrectly including the inner header in the payload to be protected. This causes a crash as the packet doesn't actually have that many bytes for a second header. The IPv4 BEET output on the other hand is broken when it comes to handling an inner IPv6 header since it always assumes an inner IPv4 header. This patch fixes both by making sure that neither BEET output function touches the inner header at all. All access is now done through the protocol-independent cb structure. Two new attributes are added to make this work, the IP header length and the IPv4 option length. They're filled in by the inner mode's output function. Thanks to Joakim Koskela for finding this problem. Signed-off-by: Herbert Xu Signed-off-by: David S. Miller --- include/net/xfrm.h | 6 ++++++ net/ipv4/xfrm4_mode_beet.c | 11 +++++------ net/ipv4/xfrm4_state.c | 2 ++ net/ipv6/xfrm6_mode_beet.c | 1 + net/ipv6/xfrm6_state.c | 2 ++ 5 files changed, 16 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 4e6f9568cbe7..0d255ae008b6 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -552,6 +552,9 @@ struct xfrm_mode_skb_cb { __be16 id; __be16 frag_off; + /* IP header length (excluding options or extension headers). */ + u8 ihl; + /* TOS for IPv4, class for IPv6. */ u8 tos; @@ -561,6 +564,9 @@ struct xfrm_mode_skb_cb { /* Protocol for IPv4, NH for IPv6. */ u8 protocol; + /* Option length for IPv4, zero for IPv6. */ + u8 optlen; + /* Used by IPv6 only, zero for IPv4. */ u8 flow_lbl[3]; }; diff --git a/net/ipv4/xfrm4_mode_beet.c b/net/ipv4/xfrm4_mode_beet.c index b47030ba162b..9c798abce736 100644 --- a/net/ipv4/xfrm4_mode_beet.c +++ b/net/ipv4/xfrm4_mode_beet.c @@ -39,13 +39,11 @@ static void xfrm4_beet_make_header(struct sk_buff *skb) static int xfrm4_beet_output(struct xfrm_state *x, struct sk_buff *skb) { struct ip_beet_phdr *ph; - struct iphdr *iph, *top_iph; + struct iphdr *top_iph; int hdrlen, optlen; - iph = ip_hdr(skb); - hdrlen = 0; - optlen = iph->ihl * 4 - sizeof(*iph); + optlen = XFRM_MODE_SKB_CB(skb)->optlen; if (unlikely(optlen)) hdrlen += IPV4_BEET_PHMAXLEN - (optlen & 4); @@ -53,11 +51,12 @@ static int xfrm4_beet_output(struct xfrm_state *x, struct sk_buff *skb) hdrlen); skb->mac_header = skb->network_header + offsetof(struct iphdr, protocol); - skb->transport_header = skb->network_header + sizeof(*iph); + skb->transport_header = skb->network_header + sizeof(*top_iph); xfrm4_beet_make_header(skb); - ph = (struct ip_beet_phdr *)__skb_pull(skb, sizeof(*iph) - hdrlen); + ph = (struct ip_beet_phdr *) + __skb_pull(skb, XFRM_MODE_SKB_CB(skb)->ihl - hdrlen); top_iph = ip_hdr(skb); diff --git a/net/ipv4/xfrm4_state.c b/net/ipv4/xfrm4_state.c index fdeebe68a379..07735ed280d7 100644 --- a/net/ipv4/xfrm4_state.c +++ b/net/ipv4/xfrm4_state.c @@ -52,10 +52,12 @@ int xfrm4_extract_header(struct sk_buff *skb) { struct iphdr *iph = ip_hdr(skb); + XFRM_MODE_SKB_CB(skb)->ihl = sizeof(*iph); XFRM_MODE_SKB_CB(skb)->id = iph->id; XFRM_MODE_SKB_CB(skb)->frag_off = iph->frag_off; XFRM_MODE_SKB_CB(skb)->tos = iph->tos; XFRM_MODE_SKB_CB(skb)->ttl = iph->ttl; + XFRM_MODE_SKB_CB(skb)->optlen = iph->ihl * 4 - sizeof(*iph); memset(XFRM_MODE_SKB_CB(skb)->flow_lbl, 0, sizeof(XFRM_MODE_SKB_CB(skb)->flow_lbl)); diff --git a/net/ipv6/xfrm6_mode_beet.c b/net/ipv6/xfrm6_mode_beet.c index 0527d11c1ae3..d6ce400f585f 100644 --- a/net/ipv6/xfrm6_mode_beet.c +++ b/net/ipv6/xfrm6_mode_beet.c @@ -45,6 +45,7 @@ static int xfrm6_beet_output(struct xfrm_state *x, struct sk_buff *skb) skb->mac_header = skb->network_header + offsetof(struct ipv6hdr, nexthdr); skb->transport_header = skb->network_header + sizeof(*top_iph); + __skb_pull(skb, XFRM_MODE_SKB_CB(skb)->ihl); xfrm6_beet_make_header(skb); diff --git a/net/ipv6/xfrm6_state.c b/net/ipv6/xfrm6_state.c index dc817e035e23..ff1e1db8e236 100644 --- a/net/ipv6/xfrm6_state.c +++ b/net/ipv6/xfrm6_state.c @@ -174,10 +174,12 @@ int xfrm6_extract_header(struct sk_buff *skb) { struct ipv6hdr *iph = ipv6_hdr(skb); + XFRM_MODE_SKB_CB(skb)->ihl = sizeof(*iph); XFRM_MODE_SKB_CB(skb)->id = 0; XFRM_MODE_SKB_CB(skb)->frag_off = htons(IP_DF); XFRM_MODE_SKB_CB(skb)->tos = ipv6_get_dsfield(iph); XFRM_MODE_SKB_CB(skb)->ttl = iph->hop_limit; + XFRM_MODE_SKB_CB(skb)->optlen = 0; memcpy(XFRM_MODE_SKB_CB(skb)->flow_lbl, iph->flow_lbl, sizeof(XFRM_MODE_SKB_CB(skb)->flow_lbl)); -- cgit v1.2.3-59-g8ed1b From c101b088ba0ed16d7109b2f3c2d16798d162a535 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 26 Mar 2008 17:32:33 -0700 Subject: [SPARC64]: Define TASK_SIZE_OF() This make "cat /proc/${PID}/pagemap" more efficient for 32-bit tasks. Based upon a report by Mariusz Kozlowski. Signed-off-by: David S. Miller --- include/asm-sparc64/processor.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index 8da484c19822..885b6a1dcae4 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -37,6 +37,9 @@ #endif #define TASK_SIZE ((unsigned long)-VPTE_SIZE) +#define TASK_SIZE_OF(tsk) \ + (test_tsk_thread_flag(tsk,TIF_32BIT) ? \ + (1UL << 32UL) : TASK_SIZE) #ifdef __KERNEL__ #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) -- cgit v1.2.3-59-g8ed1b From b2ef749720a97053d60605a7456772a1752164cc Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 26 Mar 2008 22:39:15 +0100 Subject: rdc321x: GPIO routines bugfixes This patch fixes the use of GPIO routines which are in the PCI configuration space of the RDC321x, therefore reading/writing to this space without spinlock protection can be problematic. We also now request and free GPIOs and support the MGB100 board, previous code was very AR525W-centric. Signed-off-by: Volker Weiss Signed-off-by: Florian Fainelli Signed-off-by: Ingo Molnar --- arch/x86/mach-rdc321x/gpio.c | 199 +++++++++++++++++++++------- arch/x86/mach-rdc321x/platform.c | 2 + include/asm-x86/mach-rdc321x/gpio.h | 9 +- include/asm-x86/mach-rdc321x/rdc321x_defs.h | 8 +- 4 files changed, 165 insertions(+), 53 deletions(-) (limited to 'include') diff --git a/arch/x86/mach-rdc321x/gpio.c b/arch/x86/mach-rdc321x/gpio.c index 031269163bd6..247f33d3a407 100644 --- a/arch/x86/mach-rdc321x/gpio.c +++ b/arch/x86/mach-rdc321x/gpio.c @@ -1,91 +1,194 @@ /* - * Copyright (C) 2007, OpenWrt.org, Florian Fainelli - * RDC321x architecture specific GPIO support + * GPIO support for RDC SoC R3210/R8610 + * + * Copyright (C) 2007, Florian Fainelli + * Copyright (C) 2008, Volker Weiss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. */ -#include -#include + +#include #include #include #include -#include +#include #include -static inline int rdc_gpio_is_valid(unsigned gpio) + +/* spin lock to protect our private copy of GPIO data register plus + the access to PCI conf registers. */ +static DEFINE_SPINLOCK(gpio_lock); + +/* copy of GPIO data registers */ +static u32 gpio_data_reg1; +static u32 gpio_data_reg2; + +static u32 gpio_request_data[2]; + + +static inline void rdc321x_conf_write(unsigned addr, u32 value) { - return (gpio <= RDC_MAX_GPIO); + outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR); + outl(value, RDC3210_CFGREG_DATA); } -static unsigned int rdc_gpio_read(unsigned gpio) +static inline void rdc321x_conf_or(unsigned addr, u32 value) { - unsigned int val; - - val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x84:0x48)); - outl(val, RDC3210_CFGREG_ADDR); - udelay(10); - val = inl(RDC3210_CFGREG_DATA); - val |= (0x1 << (gpio & 0x1F)); - outl(val, RDC3210_CFGREG_DATA); - udelay(10); - val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x88:0x4C)); - outl(val, RDC3210_CFGREG_ADDR); - udelay(10); - val = inl(RDC3210_CFGREG_DATA); - - return val; + outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR); + value |= inl(RDC3210_CFGREG_DATA); + outl(value, RDC3210_CFGREG_DATA); } -static void rdc_gpio_write(unsigned int val) +static inline u32 rdc321x_conf_read(unsigned addr) { - if (val) { - outl(val, RDC3210_CFGREG_DATA); - udelay(10); - } + outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR); + + return inl(RDC3210_CFGREG_DATA); } -int rdc_gpio_get_value(unsigned gpio) +/* configure pin as GPIO */ +static void rdc321x_configure_gpio(unsigned gpio) +{ + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + rdc321x_conf_or(gpio < 32 + ? RDC321X_GPIO_CTRL_REG1 : RDC321X_GPIO_CTRL_REG2, + 1 << (gpio & 0x1f)); + spin_unlock_irqrestore(&gpio_lock, flags); +} + +/* initially setup the 2 copies of the gpio data registers. + This function must be called by the platform setup code. */ +void __init rdc321x_gpio_setup() +{ + /* this might not be, what others (BIOS, bootloader, etc.) + wrote to these registers before, but it's a good guess. Still + better than just using 0xffffffff. */ + + gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1); + gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2); +} + +/* determine, if gpio number is valid */ +static inline int rdc321x_is_gpio(unsigned gpio) +{ + return gpio <= RDC321X_MAX_GPIO; +} + +/* request GPIO */ +int rdc_gpio_request(unsigned gpio, const char *label) { - if (rdc_gpio_is_valid(gpio)) - return (int)rdc_gpio_read(gpio); - else + unsigned long flags; + + if (!rdc321x_is_gpio(gpio)) return -EINVAL; + + spin_lock_irqsave(&gpio_lock, flags); + if (gpio_request_data[(gpio & 0x20) ? 1 : 0] & (1 << (gpio & 0x1f))) + goto inuse; + gpio_request_data[(gpio & 0x20) ? 1 : 0] |= (1 << (gpio & 0x1f)); + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; +inuse: + spin_unlock_irqrestore(&gpio_lock, flags); + return -EINVAL; } -EXPORT_SYMBOL(rdc_gpio_get_value); +EXPORT_SYMBOL(rdc_gpio_request); -void rdc_gpio_set_value(unsigned gpio, int value) +/* release previously-claimed GPIO */ +void rdc_gpio_free(unsigned gpio) { - unsigned int val; + unsigned long flags; - if (!rdc_gpio_is_valid(gpio)) + if (!rdc321x_is_gpio(gpio)) return; - val = rdc_gpio_read(gpio); + spin_lock_irqsave(&gpio_lock, flags); + gpio_request_data[(gpio & 0x20) ? 1 : 0] &= ~(1 << (gpio & 0x1f)); + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(rdc_gpio_free); + +/* read GPIO pin */ +int rdc_gpio_get_value(unsigned gpio) +{ + u32 reg; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + reg = rdc321x_conf_read(gpio < 32 + ? RDC321X_GPIO_DATA_REG1 : RDC321X_GPIO_DATA_REG2); + spin_unlock_irqrestore(&gpio_lock, flags); - if (value) - val &= ~(0x1 << (gpio & 0x1F)); - else - val |= (0x1 << (gpio & 0x1F)); + return (1 << (gpio & 0x1f)) & reg ? 1 : 0; +} +EXPORT_SYMBOL(rdc_gpio_get_value); - rdc_gpio_write(val); +/* set GPIO pin to value */ +void rdc_gpio_set_value(unsigned gpio, int value) +{ + unsigned long flags; + u32 reg; + + reg = 1 << (gpio & 0x1f); + if (gpio < 32) { + spin_lock_irqsave(&gpio_lock, flags); + if (value) + gpio_data_reg1 |= reg; + else + gpio_data_reg1 &= ~reg; + rdc321x_conf_write(RDC321X_GPIO_DATA_REG1, gpio_data_reg1); + spin_unlock_irqrestore(&gpio_lock, flags); + } else { + spin_lock_irqsave(&gpio_lock, flags); + if (value) + gpio_data_reg2 |= reg; + else + gpio_data_reg2 &= ~reg; + rdc321x_conf_write(RDC321X_GPIO_DATA_REG2, gpio_data_reg2); + spin_unlock_irqrestore(&gpio_lock, flags); + } } EXPORT_SYMBOL(rdc_gpio_set_value); +/* configure GPIO pin as input */ int rdc_gpio_direction_input(unsigned gpio) { + if (!rdc321x_is_gpio(gpio)) + return -EINVAL; + + rdc321x_configure_gpio(gpio); + return 0; } EXPORT_SYMBOL(rdc_gpio_direction_input); +/* configure GPIO pin as output and set value */ int rdc_gpio_direction_output(unsigned gpio, int value) { + if (!rdc321x_is_gpio(gpio)) + return -EINVAL; + + gpio_set_value(gpio, value); + rdc321x_configure_gpio(gpio); + return 0; } EXPORT_SYMBOL(rdc_gpio_direction_output); - - diff --git a/arch/x86/mach-rdc321x/platform.c b/arch/x86/mach-rdc321x/platform.c index dda6024a5862..a037041817c7 100644 --- a/arch/x86/mach-rdc321x/platform.c +++ b/arch/x86/mach-rdc321x/platform.c @@ -62,6 +62,8 @@ static struct platform_device *rdc321x_devs[] = { static int __init rdc_board_setup(void) { + rdc321x_gpio_setup(); + return platform_add_devices(rdc321x_devs, ARRAY_SIZE(rdc321x_devs)); } diff --git a/include/asm-x86/mach-rdc321x/gpio.h b/include/asm-x86/mach-rdc321x/gpio.h index db31b929b990..acce0b7d397b 100644 --- a/include/asm-x86/mach-rdc321x/gpio.h +++ b/include/asm-x86/mach-rdc321x/gpio.h @@ -5,19 +5,20 @@ extern int rdc_gpio_get_value(unsigned gpio); extern void rdc_gpio_set_value(unsigned gpio, int value); extern int rdc_gpio_direction_input(unsigned gpio); extern int rdc_gpio_direction_output(unsigned gpio, int value); - +extern int rdc_gpio_request(unsigned gpio, const char *label); +extern void rdc_gpio_free(unsigned gpio); +extern void __init rdc321x_gpio_setup(void); /* Wrappers for the arch-neutral GPIO API */ static inline int gpio_request(unsigned gpio, const char *label) { - /* Not yet implemented */ - return 0; + return rdc_gpio_request(gpio, label); } static inline void gpio_free(unsigned gpio) { - /* Not yet implemented */ + rdc_gpio_free(gpio); } static inline int gpio_direction_input(unsigned gpio) diff --git a/include/asm-x86/mach-rdc321x/rdc321x_defs.h b/include/asm-x86/mach-rdc321x/rdc321x_defs.h index 838ba8f64fd3..c8e9c8bed3d0 100644 --- a/include/asm-x86/mach-rdc321x/rdc321x_defs.h +++ b/include/asm-x86/mach-rdc321x/rdc321x_defs.h @@ -3,4 +3,10 @@ /* General purpose configuration and data registers */ #define RDC3210_CFGREG_ADDR 0x0CF8 #define RDC3210_CFGREG_DATA 0x0CFC -#define RDC_MAX_GPIO 0x3A + +#define RDC321X_GPIO_CTRL_REG1 0x48 +#define RDC321X_GPIO_CTRL_REG2 0x84 +#define RDC321X_GPIO_DATA_REG1 0x4c +#define RDC321X_GPIO_DATA_REG2 0x88 + +#define RDC321X_MAX_GPIO 58 -- cgit v1.2.3-59-g8ed1b From a6bd8e13034dd7d60b6f14217096efa192d0adc1 Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Fri, 28 Mar 2008 11:05:53 -0500 Subject: lguest: comment documentation update. Took some cycles to re-read the Lguest Journey end-to-end, fix some rot and tighten some phrases. Only comments change. No new jokes, but a couple of recycled old jokes. Signed-off-by: Rusty Russell --- Documentation/lguest/lguest.c | 69 ++++++++++++---------- arch/x86/lguest/boot.c | 108 +++++++++++++++++++--------------- arch/x86/lguest/i386_head.S | 15 +++-- drivers/lguest/core.c | 18 +++--- drivers/lguest/hypercalls.c | 11 +++- drivers/lguest/interrupts_and_traps.c | 7 +-- drivers/lguest/lguest_device.c | 11 ++-- drivers/lguest/lguest_user.c | 30 +++++++--- drivers/lguest/page_tables.c | 32 +++++----- drivers/lguest/x86/core.c | 33 +++++++---- drivers/lguest/x86/switcher_32.S | 8 +-- include/asm-x86/lguest_hcall.h | 2 +- include/linux/lguest_launcher.h | 6 +- 13 files changed, 208 insertions(+), 142 deletions(-) (limited to 'include') diff --git a/Documentation/lguest/lguest.c b/Documentation/lguest/lguest.c index d45c7f682b1b..4c1fc65a8b3d 100644 --- a/Documentation/lguest/lguest.c +++ b/Documentation/lguest/lguest.c @@ -1,7 +1,7 @@ /*P:100 This is the Launcher code, a simple program which lays out the - * "physical" memory for the new Guest by mapping the kernel image and the - * virtual devices, then reads repeatedly from /dev/lguest to run the Guest. -:*/ + * "physical" memory for the new Guest by mapping the kernel image and + * the virtual devices, then opens /dev/lguest to tell the kernel + * about the Guest and control it. :*/ #define _LARGEFILE64_SOURCE #define _GNU_SOURCE #include @@ -43,7 +43,7 @@ #include "linux/virtio_console.h" #include "linux/virtio_ring.h" #include "asm-x86/bootparam.h" -/*L:110 We can ignore the 38 include files we need for this program, but I do +/*L:110 We can ignore the 39 include files we need for this program, but I do * want to draw attention to the use of kernel-style types. * * As Linus said, "C is a Spartan language, and so should your naming be." I @@ -320,7 +320,7 @@ static unsigned long map_elf(int elf_fd, const Elf32_Ehdr *ehdr) err(1, "Reading program headers"); /* Try all the headers: there are usually only three. A read-only one, - * a read-write one, and a "note" section which isn't loadable. */ + * a read-write one, and a "note" section which we don't load. */ for (i = 0; i < ehdr->e_phnum; i++) { /* If this isn't a loadable segment, we ignore it */ if (phdr[i].p_type != PT_LOAD) @@ -387,7 +387,7 @@ static unsigned long load_kernel(int fd) if (memcmp(hdr.e_ident, ELFMAG, SELFMAG) == 0) return map_elf(fd, &hdr); - /* Otherwise we assume it's a bzImage, and try to unpack it */ + /* Otherwise we assume it's a bzImage, and try to load it. */ return load_bzimage(fd); } @@ -433,12 +433,12 @@ static unsigned long load_initrd(const char *name, unsigned long mem) return len; } -/* Once we know how much memory we have, we can construct simple linear page +/* Once we know how much memory we have we can construct simple linear page * tables which set virtual == physical which will get the Guest far enough * into the boot to create its own. * * We lay them out of the way, just below the initrd (which is why we need to - * know its size). */ + * know its size here). */ static unsigned long setup_pagetables(unsigned long mem, unsigned long initrd_size) { @@ -850,7 +850,8 @@ static void handle_console_output(int fd, struct virtqueue *vq) * * Handling output for network is also simple: we get all the output buffers * and write them (ignoring the first element) to this device's file descriptor - * (stdout). */ + * (/dev/net/tun). + */ static void handle_net_output(int fd, struct virtqueue *vq) { unsigned int head, out, in; @@ -924,7 +925,7 @@ static void enable_fd(int fd, struct virtqueue *vq) write(waker_fd, &vq->dev->fd, sizeof(vq->dev->fd)); } -/* Resetting a device is fairly easy. */ +/* When the Guest asks us to reset a device, it's is fairly easy. */ static void reset_device(struct device *dev) { struct virtqueue *vq; @@ -1003,8 +1004,8 @@ static void handle_input(int fd) if (select(devices.max_infd+1, &fds, NULL, NULL, &poll) == 0) break; - /* Otherwise, call the device(s) which have readable - * file descriptors and a method of handling them. */ + /* Otherwise, call the device(s) which have readable file + * descriptors and a method of handling them. */ for (i = devices.dev; i; i = i->next) { if (i->handle_input && FD_ISSET(i->fd, &fds)) { int dev_fd; @@ -1015,8 +1016,7 @@ static void handle_input(int fd) * should no longer service it. Networking and * console do this when there's no input * buffers to deliver into. Console also uses - * it when it discovers that stdin is - * closed. */ + * it when it discovers that stdin is closed. */ FD_CLR(i->fd, &devices.infds); /* Tell waker to ignore it too, by sending a * negative fd number (-1, since 0 is a valid @@ -1033,7 +1033,8 @@ static void handle_input(int fd) * * All devices need a descriptor so the Guest knows it exists, and a "struct * device" so the Launcher can keep track of it. We have common helper - * routines to allocate and manage them. */ + * routines to allocate and manage them. + */ /* The layout of the device page is a "struct lguest_device_desc" followed by a * number of virtqueue descriptors, then two sets of feature bits, then an @@ -1078,7 +1079,7 @@ static void add_virtqueue(struct device *dev, unsigned int num_descs, struct virtqueue **i, *vq = malloc(sizeof(*vq)); void *p; - /* First we need some pages for this virtqueue. */ + /* First we need some memory for this virtqueue. */ pages = (vring_size(num_descs, getpagesize()) + getpagesize() - 1) / getpagesize(); p = get_pages(pages); @@ -1122,7 +1123,7 @@ static void add_virtqueue(struct device *dev, unsigned int num_descs, } /* The first half of the feature bitmask is for us to advertise features. The - * second half if for the Guest to accept features. */ + * second half is for the Guest to accept features. */ static void add_feature(struct device *dev, unsigned bit) { u8 *features = get_feature_bits(dev); @@ -1151,7 +1152,9 @@ static void set_config(struct device *dev, unsigned len, const void *conf) } /* This routine does all the creation and setup of a new device, including - * calling new_dev_desc() to allocate the descriptor and device memory. */ + * calling new_dev_desc() to allocate the descriptor and device memory. + * + * See what I mean about userspace being boring? */ static struct device *new_device(const char *name, u16 type, int fd, bool (*handle_input)(int, struct device *)) { @@ -1492,7 +1495,10 @@ static int io_thread(void *_dev) while (read(vblk->workpipe[0], &c, 1) == 1) { /* We acknowledge each request immediately to reduce latency, * rather than waiting until we've done them all. I haven't - * measured to see if it makes any difference. */ + * measured to see if it makes any difference. + * + * That would be an interesting test, wouldn't it? You could + * also try having more than one I/O thread. */ while (service_io(dev)) write(vblk->done_fd, &c, 1); } @@ -1500,7 +1506,7 @@ static int io_thread(void *_dev) } /* Now we've seen the I/O thread, we return to the Launcher to see what happens - * when the thread tells us it's completed some I/O. */ + * when that thread tells us it's completed some I/O. */ static bool handle_io_finish(int fd, struct device *dev) { char c; @@ -1572,11 +1578,12 @@ static void setup_block_file(const char *filename) * more work. */ pipe(vblk->workpipe); - /* Create stack for thread and run it */ + /* Create stack for thread and run it. Since stack grows upwards, we + * point the stack pointer to the end of this region. */ stack = malloc(32768); /* SIGCHLD - We dont "wait" for our cloned thread, so prevent it from * becoming a zombie. */ - if (clone(io_thread, stack + 32768, CLONE_VM | SIGCHLD, dev) == -1) + if (clone(io_thread, stack + 32768, CLONE_VM | SIGCHLD, dev) == -1) err(1, "Creating clone"); /* We don't need to keep the I/O thread's end of the pipes open. */ @@ -1586,14 +1593,14 @@ static void setup_block_file(const char *filename) verbose("device %u: virtblock %llu sectors\n", devices.device_num, le64_to_cpu(conf.capacity)); } -/* That's the end of device setup. :*/ +/* That's the end of device setup. */ -/* Reboot */ +/*L:230 Reboot is pretty easy: clean up and exec() the Launcher afresh. */ static void __attribute__((noreturn)) restart_guest(void) { unsigned int i; - /* Closing pipes causes the waker thread and io_threads to die, and + /* Closing pipes causes the Waker thread and io_threads to die, and * closing /dev/lguest cleans up the Guest. Since we don't track all * open fds, we simply close everything beyond stderr. */ for (i = 3; i < FD_SETSIZE; i++) @@ -1602,7 +1609,7 @@ static void __attribute__((noreturn)) restart_guest(void) err(1, "Could not exec %s", main_args[0]); } -/*L:220 Finally we reach the core of the Launcher, which runs the Guest, serves +/*L:220 Finally we reach the core of the Launcher which runs the Guest, serves * its input and output, and finally, lays it to rest. */ static void __attribute__((noreturn)) run_guest(int lguest_fd) { @@ -1643,7 +1650,7 @@ static void __attribute__((noreturn)) run_guest(int lguest_fd) err(1, "Resetting break"); } } -/* +/*L:240 * This is the end of the Launcher. The good news: we are over halfway * through! The bad news: the most fiendish part of the code still lies ahead * of us. @@ -1690,8 +1697,8 @@ int main(int argc, char *argv[]) * device receive input from a file descriptor, we keep an fdset * (infds) and the maximum fd number (max_infd) with the head of the * list. We also keep a pointer to the last device. Finally, we keep - * the next interrupt number to hand out (1: remember that 0 is used by - * the timer). */ + * the next interrupt number to use for devices (1: remember that 0 is + * used by the timer). */ FD_ZERO(&devices.infds); devices.max_infd = -1; devices.lastdev = NULL; @@ -1792,8 +1799,8 @@ int main(int argc, char *argv[]) lguest_fd = tell_kernel(pgdir, start); /* We fork off a child process, which wakes the Launcher whenever one - * of the input file descriptors needs attention. Otherwise we would - * run the Guest until it tries to output something. */ + * of the input file descriptors needs attention. We call this the + * Waker, and we'll cover it in a moment. */ waker_fd = setup_waker(lguest_fd); /* Finally, run the Guest. This doesn't return. */ diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index a104c532ff70..3335b4595efd 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -10,21 +10,19 @@ * (such as the example in Documentation/lguest/lguest.c) is called the * Launcher. * - * Secondly, we only run specially modified Guests, not normal kernels. When - * you set CONFIG_LGUEST to 'y' or 'm', this automatically sets - * CONFIG_LGUEST_GUEST=y, which compiles this file into the kernel so it knows - * how to be a Guest. This means that you can use the same kernel you boot - * normally (ie. as a Host) as a Guest. + * Secondly, we only run specially modified Guests, not normal kernels: setting + * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows + * how to be a Guest at boot time. This means that you can use the same kernel + * you boot normally (ie. as a Host) as a Guest. * * These Guests know that they cannot do privileged operations, such as disable * interrupts, and that they have to ask the Host to do such things explicitly. * This file consists of all the replacements for such low-level native * hardware operations: these special Guest versions call the Host. * - * So how does the kernel know it's a Guest? The Guest starts at a special - * entry point marked with a magic string, which sets up a few things then - * calls here. We replace the native functions various "paravirt" structures - * with our Guest versions, then boot like normal. :*/ + * So how does the kernel know it's a Guest? We'll see that later, but let's + * just say that we end up here where we replace the native functions various + * "paravirt" structures with our Guest versions, then boot like normal. :*/ /* * Copyright (C) 2006, Rusty Russell IBM Corporation. @@ -134,7 +132,7 @@ static void async_hcall(unsigned long call, unsigned long arg1, * lguest_leave_lazy_mode(). * * So, when we're in lazy mode, we call async_hcall() to store the call for - * future processing. */ + * future processing: */ static void lazy_hcall(unsigned long call, unsigned long arg1, unsigned long arg2, @@ -147,7 +145,7 @@ static void lazy_hcall(unsigned long call, } /* When lazy mode is turned off reset the per-cpu lazy mode variable and then - * issue a hypercall to flush any stored calls. */ + * issue the do-nothing hypercall to flush any stored calls. */ static void lguest_leave_lazy_mode(void) { paravirt_leave_lazy(paravirt_get_lazy_mode()); @@ -164,7 +162,7 @@ static void lguest_leave_lazy_mode(void) * * So instead we keep an "irq_enabled" field inside our "struct lguest_data", * which the Guest can update with a single instruction. The Host knows to - * check there when it wants to deliver an interrupt. + * check there before it tries to deliver an interrupt. */ /* save_flags() is expected to return the processor state (ie. "flags"). The @@ -196,10 +194,15 @@ static void irq_enable(void) /*M:003 Note that we don't check for outstanding interrupts when we re-enable * them (or when we unmask an interrupt). This seems to work for the moment, * since interrupts are rare and we'll just get the interrupt on the next timer - * tick, but when we turn on CONFIG_NO_HZ, we should revisit this. One way + * tick, but now we can run with CONFIG_NO_HZ, we should revisit this. One way * would be to put the "irq_enabled" field in a page by itself, and have the * Host write-protect it when an interrupt comes in when irqs are disabled. - * There will then be a page fault as soon as interrupts are re-enabled. :*/ + * There will then be a page fault as soon as interrupts are re-enabled. + * + * A better method is to implement soft interrupt disable generally for x86: + * instead of disabling interrupts, we set a flag. If an interrupt does come + * in, we then disable them for real. This is uncommon, so we could simply use + * a hypercall for interrupt control and not worry about efficiency. :*/ /*G:034 * The Interrupt Descriptor Table (IDT). @@ -212,6 +215,10 @@ static void irq_enable(void) static void lguest_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) { + /* The gate_desc structure is 8 bytes long: we hand it to the Host in + * two 32-bit chunks. The whole 32-bit kernel used to hand descriptors + * around like this; typesafety wasn't a big concern in Linux's early + * years. */ u32 *desc = (u32 *)g; /* Keep the local copy up to date. */ native_write_idt_entry(dt, entrynum, g); @@ -243,7 +250,8 @@ static void lguest_load_idt(const struct desc_ptr *desc) * * This is the opposite of the IDT code where we have a LOAD_IDT_ENTRY * hypercall and use that repeatedly to load a new IDT. I don't think it - * really matters, but wouldn't it be nice if they were the same? + * really matters, but wouldn't it be nice if they were the same? Wouldn't + * it be even better if you were the one to send the patch to fix it? */ static void lguest_load_gdt(const struct desc_ptr *desc) { @@ -298,9 +306,9 @@ static void lguest_load_tr_desc(void) /* The "cpuid" instruction is a way of querying both the CPU identity * (manufacturer, model, etc) and its features. It was introduced before the - * Pentium in 1993 and keeps getting extended by both Intel and AMD. As you - * might imagine, after a decade and a half this treatment, it is now a giant - * ball of hair. Its entry in the current Intel manual runs to 28 pages. + * Pentium in 1993 and keeps getting extended by both Intel, AMD and others. + * As you might imagine, after a decade and a half this treatment, it is now a + * giant ball of hair. Its entry in the current Intel manual runs to 28 pages. * * This instruction even it has its own Wikipedia entry. The Wikipedia entry * has been translated into 4 languages. I am not making this up! @@ -594,17 +602,17 @@ static unsigned long lguest_get_wallclock(void) return lguest_data.time.tv_sec; } -/* The TSC is a Time Stamp Counter. The Host tells us what speed it runs at, - * or 0 if it's unusable as a reliable clock source. This matches what we want - * here: if we return 0 from this function, the x86 TSC clock will not register - * itself. */ +/* The TSC is an Intel thing called the Time Stamp Counter. The Host tells us + * what speed it runs at, or 0 if it's unusable as a reliable clock source. + * This matches what we want here: if we return 0 from this function, the x86 + * TSC clock will give up and not register itself. */ static unsigned long lguest_cpu_khz(void) { return lguest_data.tsc_khz; } -/* If we can't use the TSC, the kernel falls back to our "lguest_clock", where - * we read the time value given to us by the Host. */ +/* If we can't use the TSC, the kernel falls back to our lower-priority + * "lguest_clock", where we read the time value given to us by the Host. */ static cycle_t lguest_clock_read(void) { unsigned long sec, nsec; @@ -648,12 +656,16 @@ static struct clocksource lguest_clock = { static int lguest_clockevent_set_next_event(unsigned long delta, struct clock_event_device *evt) { + /* FIXME: I don't think this can ever happen, but James tells me he had + * to put this code in. Maybe we should remove it now. Anyone? */ if (delta < LG_CLOCK_MIN_DELTA) { if (printk_ratelimit()) printk(KERN_DEBUG "%s: small delta %lu ns\n", __FUNCTION__, delta); return -ETIME; } + + /* Please wake us this far in the future. */ hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0); return 0; } @@ -738,7 +750,7 @@ static void lguest_time_init(void) * will not tolerate us trying to use that), the stack pointer, and the number * of pages in the stack. */ static void lguest_load_sp0(struct tss_struct *tss, - struct thread_struct *thread) + struct thread_struct *thread) { lazy_hcall(LHCALL_SET_STACK, __KERNEL_DS|0x1, thread->sp0, THREAD_SIZE/PAGE_SIZE); @@ -786,9 +798,8 @@ static void lguest_safe_halt(void) hcall(LHCALL_HALT, 0, 0, 0); } -/* Perhaps CRASH isn't the best name for this hypercall, but we use it to get a - * message out when we're crashing as well as elegant termination like powering - * off. +/* The SHUTDOWN hypercall takes a string to describe what's happening, and + * an argument which says whether this to restart (reboot) the Guest or not. * * Note that the Host always prefers that the Guest speak in physical addresses * rather than virtual addresses, so we use __pa() here. */ @@ -816,8 +827,9 @@ static struct notifier_block paniced = { /* Setting up memory is fairly easy. */ static __init char *lguest_memory_setup(void) { - /* We do this here and not earlier because lockcheck barfs if we do it - * before start_kernel() */ + /* We do this here and not earlier because lockcheck used to barf if we + * did it before start_kernel(). I think we fixed that, so it'd be + * nice to move it back to lguest_init. Patch welcome... */ atomic_notifier_chain_register(&panic_notifier_list, &paniced); /* The Linux bootloader header contains an "e820" memory map: the @@ -850,12 +862,19 @@ static __init int early_put_chars(u32 vtermno, const char *buf, int count) return len; } +/* Rebooting also tells the Host we're finished, but the RESTART flag tells the + * Launcher to reboot us. */ +static void lguest_restart(char *reason) +{ + hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0); +} + /*G:050 * Patching (Powerfully Placating Performance Pedants) * - * We have already seen that pv_ops structures let us replace simple - * native instructions with calls to the appropriate back end all throughout - * the kernel. This allows the same kernel to run as a Guest and as a native + * We have already seen that pv_ops structures let us replace simple native + * instructions with calls to the appropriate back end all throughout the + * kernel. This allows the same kernel to run as a Guest and as a native * kernel, but it's slow because of all the indirect branches. * * Remember that David Wheeler quote about "Any problem in computer science can @@ -908,14 +927,9 @@ static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf, return insn_len; } -static void lguest_restart(char *reason) -{ - hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0); -} - -/*G:030 Once we get to lguest_init(), we know we're a Guest. The pv_ops - * structures in the kernel provide points for (almost) every routine we have - * to override to avoid privileged instructions. */ +/*G:030 Once we get to lguest_init(), we know we're a Guest. The various + * pv_ops structures in the kernel provide points for (almost) every routine we + * have to override to avoid privileged instructions. */ __init void lguest_init(void) { /* We're under lguest, paravirt is enabled, and we're running at @@ -1003,9 +1017,9 @@ __init void lguest_init(void) * the normal data segment to get through booting. */ asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_DS) : "memory"); - /* The Host uses the top of the Guest's virtual address space for the - * Host<->Guest Switcher, and it tells us how big that is in - * lguest_data.reserve_mem, set up on the LGUEST_INIT hypercall. */ + /* The Host<->Guest Switcher lives at the top of our address space, and + * the Host told us how big it is when we made LGUEST_INIT hypercall: + * it put the answer in lguest_data.reserve_mem */ reserve_top_address(lguest_data.reserve_mem); /* If we don't initialize the lock dependency checker now, it crashes @@ -1027,6 +1041,7 @@ __init void lguest_init(void) /* Math is always hard! */ new_cpu_data.hard_math = 1; + /* We don't have features. We have puppies! Puppies! */ #ifdef CONFIG_X86_MCE mce_disabled = 1; #endif @@ -1044,10 +1059,11 @@ __init void lguest_init(void) virtio_cons_early_init(early_put_chars); /* Last of all, we set the power management poweroff hook to point to - * the Guest routine to power off. */ + * the Guest routine to power off, and the reboot hook to our restart + * routine. */ pm_power_off = lguest_power_off; - machine_ops.restart = lguest_restart; + /* Now we're set up, call start_kernel() in init/main.c and we proceed * to boot as normal. It never returns. */ start_kernel(); diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/i386_head.S index 95b6fbcded63..5c7cef34c9e7 100644 --- a/arch/x86/lguest/i386_head.S +++ b/arch/x86/lguest/i386_head.S @@ -5,13 +5,20 @@ #include #include -/*G:020 This is where we begin: head.S notes that the boot header's platform - * type field is "1" (lguest), so calls us here. +/*G:020 Our story starts with the kernel booting into startup_32 in + * arch/x86/kernel/head_32.S. It expects a boot header, which is created by + * the bootloader (the Launcher in our case). + * + * The startup_32 function does very little: it clears the uninitialized global + * C variables which we expect to be zero (ie. BSS) and then copies the boot + * header and kernel command line somewhere safe. Finally it checks the + * 'hardware_subarch' field. This was introduced in 2.6.24 for lguest and Xen: + * if it's set to '1' (lguest's assigned number), then it calls us here. * * WARNING: be very careful here! We're running at addresses equal to physical * addesses (around 0), not above PAGE_OFFSET as most code expectes * (eg. 0xC0000000). Jumps are relative, so they're OK, but we can't touch any - * data. + * data without remembering to subtract __PAGE_OFFSET! * * The .section line puts this code in .init.text so it will be discarded after * boot. */ @@ -24,7 +31,7 @@ ENTRY(lguest_entry) int $LGUEST_TRAP_ENTRY /* The Host put the toplevel pagetable in lguest_data.pgdir. The movsl - * instruction uses %esi implicitly as the source for the copy we' + * instruction uses %esi implicitly as the source for the copy we're * about to do. */ movl lguest_data - __PAGE_OFFSET + LGUEST_DATA_pgdir, %esi diff --git a/drivers/lguest/core.c b/drivers/lguest/core.c index c632c08cbbdc..5eea4356d703 100644 --- a/drivers/lguest/core.c +++ b/drivers/lguest/core.c @@ -1,8 +1,6 @@ /*P:400 This contains run_guest() which actually calls into the Host<->Guest * Switcher and analyzes the return, such as determining if the Guest wants the - * Host to do something. This file also contains useful helper routines, and a - * couple of non-obvious setup and teardown pieces which were implemented after - * days of debugging pain. :*/ + * Host to do something. This file also contains useful helper routines. :*/ #include #include #include @@ -49,8 +47,8 @@ static __init int map_switcher(void) * easy. */ - /* We allocate an array of "struct page"s. map_vm_area() wants the - * pages in this form, rather than just an array of pointers. */ + /* We allocate an array of struct page pointers. map_vm_area() wants + * this, rather than just an array of pages. */ switcher_page = kmalloc(sizeof(switcher_page[0])*TOTAL_SWITCHER_PAGES, GFP_KERNEL); if (!switcher_page) { @@ -172,7 +170,7 @@ void __lgread(struct lg_cpu *cpu, void *b, unsigned long addr, unsigned bytes) } } -/* This is the write (copy into guest) version. */ +/* This is the write (copy into Guest) version. */ void __lgwrite(struct lg_cpu *cpu, unsigned long addr, const void *b, unsigned bytes) { @@ -209,9 +207,9 @@ int run_guest(struct lg_cpu *cpu, unsigned long __user *user) if (cpu->break_out) return -EAGAIN; - /* Check if there are any interrupts which can be delivered - * now: if so, this sets up the hander to be executed when we - * next run the Guest. */ + /* Check if there are any interrupts which can be delivered now: + * if so, this sets up the hander to be executed when we next + * run the Guest. */ maybe_do_interrupt(cpu); /* All long-lived kernel loops need to check with this horrible @@ -246,8 +244,10 @@ int run_guest(struct lg_cpu *cpu, unsigned long __user *user) lguest_arch_handle_trap(cpu); } + /* Special case: Guest is 'dead' but wants a reboot. */ if (cpu->lg->dead == ERR_PTR(-ERESTART)) return -ERESTART; + /* The Guest is dead => "No such file or directory" */ return -ENOENT; } diff --git a/drivers/lguest/hypercalls.c b/drivers/lguest/hypercalls.c index 0f2cb4fd7c69..54d66f05fefa 100644 --- a/drivers/lguest/hypercalls.c +++ b/drivers/lguest/hypercalls.c @@ -29,7 +29,7 @@ #include "lg.h" /*H:120 This is the core hypercall routine: where the Guest gets what it wants. - * Or gets killed. Or, in the case of LHCALL_CRASH, both. */ + * Or gets killed. Or, in the case of LHCALL_SHUTDOWN, both. */ static void do_hcall(struct lg_cpu *cpu, struct hcall_args *args) { switch (args->arg0) { @@ -190,6 +190,13 @@ static void initialize(struct lg_cpu *cpu) * pagetable. */ guest_pagetable_clear_all(cpu); } +/*:*/ + +/*M:013 If a Guest reads from a page (so creates a mapping) that it has never + * written to, and then the Launcher writes to it (ie. the output of a virtual + * device), the Guest will still see the old page. In practice, this never + * happens: why would the Guest read a page which it has never written to? But + * a similar scenario might one day bite us, so it's worth mentioning. :*/ /*H:100 * Hypercalls @@ -227,7 +234,7 @@ void do_hypercalls(struct lg_cpu *cpu) * However, if we are signalled or the Guest sends I/O to the * Launcher, the run_guest() loop will exit without running the * Guest. When it comes back it would try to re-run the - * hypercall. */ + * hypercall. Finding that bug sucked. */ cpu->hcall = NULL; } } diff --git a/drivers/lguest/interrupts_and_traps.c b/drivers/lguest/interrupts_and_traps.c index 32e97c1858e5..0414ddf87587 100644 --- a/drivers/lguest/interrupts_and_traps.c +++ b/drivers/lguest/interrupts_and_traps.c @@ -144,7 +144,6 @@ void maybe_do_interrupt(struct lg_cpu *cpu) if (copy_from_user(&blk, cpu->lg->lguest_data->blocked_interrupts, sizeof(blk))) return; - bitmap_andnot(blk, cpu->irqs_pending, blk, LGUEST_IRQS); /* Find the first interrupt. */ @@ -237,9 +236,9 @@ void free_interrupts(void) clear_bit(syscall_vector, used_vectors); } -/*H:220 Now we've got the routines to deliver interrupts, delivering traps - * like page fault is easy. The only trick is that Intel decided that some - * traps should have error codes: */ +/*H:220 Now we've got the routines to deliver interrupts, delivering traps like + * page fault is easy. The only trick is that Intel decided that some traps + * should have error codes: */ static int has_err(unsigned int trap) { return (trap == 8 || (trap >= 10 && trap <= 14) || trap == 17); diff --git a/drivers/lguest/lguest_device.c b/drivers/lguest/lguest_device.c index 1b2ec0bf5eb1..2bc9bf7e88e5 100644 --- a/drivers/lguest/lguest_device.c +++ b/drivers/lguest/lguest_device.c @@ -1,10 +1,10 @@ /*P:050 Lguest guests use a very simple method to describe devices. It's a - * series of device descriptors contained just above the top of normal + * series of device descriptors contained just above the top of normal Guest * memory. * * We use the standard "virtio" device infrastructure, which provides us with a * console, a network and a block driver. Each one expects some configuration - * information and a "virtqueue" mechanism to send and receive data. :*/ + * information and a "virtqueue" or two to send and receive data. :*/ #include #include #include @@ -53,7 +53,7 @@ struct lguest_device { * Device configurations * * The configuration information for a device consists of one or more - * virtqueues, a feature bitmaks, and some configuration bytes. The + * virtqueues, a feature bitmap, and some configuration bytes. The * configuration bytes don't really matter to us: the Launcher sets them up, and * the driver will look at them during setup. * @@ -179,7 +179,7 @@ struct lguest_vq_info }; /* When the virtio_ring code wants to prod the Host, it calls us here and we - * make a hypercall. We hand the page number of the virtqueue so the Host + * make a hypercall. We hand the physical address of the virtqueue so the Host * knows which virtqueue we're talking about. */ static void lg_notify(struct virtqueue *vq) { @@ -199,7 +199,8 @@ static void lg_notify(struct virtqueue *vq) * allocate its own pages and tell the Host where they are, but for lguest it's * simpler for the Host to simply tell us where the pages are. * - * So we provide devices with a "find virtqueue and set it up" function. */ + * So we provide drivers with a "find the Nth virtqueue and set it up" + * function. */ static struct virtqueue *lg_find_vq(struct virtio_device *vdev, unsigned index, void (*callback)(struct virtqueue *vq)) diff --git a/drivers/lguest/lguest_user.c b/drivers/lguest/lguest_user.c index 2221485b0773..564e425d71dd 100644 --- a/drivers/lguest/lguest_user.c +++ b/drivers/lguest/lguest_user.c @@ -73,7 +73,7 @@ static ssize_t read(struct file *file, char __user *user, size_t size,loff_t*o) if (current != cpu->tsk) return -EPERM; - /* If the guest is already dead, we indicate why */ + /* If the Guest is already dead, we indicate why */ if (lg->dead) { size_t len; @@ -88,7 +88,7 @@ static ssize_t read(struct file *file, char __user *user, size_t size,loff_t*o) return len; } - /* If we returned from read() last time because the Guest notified, + /* If we returned from read() last time because the Guest sent I/O, * clear the flag. */ if (cpu->pending_notify) cpu->pending_notify = 0; @@ -97,14 +97,20 @@ static ssize_t read(struct file *file, char __user *user, size_t size,loff_t*o) return run_guest(cpu, (unsigned long __user *)user); } +/*L:025 This actually initializes a CPU. For the moment, a Guest is only + * uniprocessor, so "id" is always 0. */ static int lg_cpu_start(struct lg_cpu *cpu, unsigned id, unsigned long start_ip) { + /* We have a limited number the number of CPUs in the lguest struct. */ if (id >= NR_CPUS) return -EINVAL; + /* Set up this CPU's id, and pointer back to the lguest struct. */ cpu->id = id; cpu->lg = container_of((cpu - id), struct lguest, cpus[0]); cpu->lg->nr_cpus++; + + /* Each CPU has a timer it can set. */ init_clockdev(cpu); /* We need a complete page for the Guest registers: they are accessible @@ -120,11 +126,11 @@ static int lg_cpu_start(struct lg_cpu *cpu, unsigned id, unsigned long start_ip) * address. */ lguest_arch_setup_regs(cpu, start_ip); - /* Initialize the queue for the waker to wait on */ + /* Initialize the queue for the Waker to wait on */ init_waitqueue_head(&cpu->break_wq); /* We keep a pointer to the Launcher task (ie. current task) for when - * other Guests want to wake this one (inter-Guest I/O). */ + * other Guests want to wake this one (eg. console input). */ cpu->tsk = current; /* We need to keep a pointer to the Launcher's memory map, because if @@ -136,6 +142,7 @@ static int lg_cpu_start(struct lg_cpu *cpu, unsigned id, unsigned long start_ip) * when the same Guest runs on the same CPU twice. */ cpu->last_pages = NULL; + /* No error == success. */ return 0; } @@ -185,14 +192,13 @@ static int initialize(struct file *file, const unsigned long __user *input) lg->mem_base = (void __user *)(long)args[0]; lg->pfn_limit = args[1]; - /* This is the first cpu */ + /* This is the first cpu (cpu 0) and it will start booting at args[3] */ err = lg_cpu_start(&lg->cpus[0], 0, args[3]); if (err) goto release_guest; /* Initialize the Guest's shadow page tables, using the toplevel - * address the Launcher gave us. This allocates memory, so can - * fail. */ + * address the Launcher gave us. This allocates memory, so can fail. */ err = init_guest_pagetable(lg, args[2]); if (err) goto free_regs; @@ -218,11 +224,16 @@ unlock: /*L:010 The first operation the Launcher does must be a write. All writes * start with an unsigned long number: for the first write this must be * LHREQ_INITIALIZE to set up the Guest. After that the Launcher can use - * writes of other values to send interrupts. */ + * writes of other values to send interrupts. + * + * Note that we overload the "offset" in the /dev/lguest file to indicate what + * CPU number we're dealing with. Currently this is always 0, since we only + * support uniprocessor Guests, but you can see the beginnings of SMP support + * here. */ static ssize_t write(struct file *file, const char __user *in, size_t size, loff_t *off) { - /* Once the guest is initialized, we hold the "struct lguest" in the + /* Once the Guest is initialized, we hold the "struct lguest" in the * file private data. */ struct lguest *lg = file->private_data; const unsigned long __user *input = (const unsigned long __user *)in; @@ -230,6 +241,7 @@ static ssize_t write(struct file *file, const char __user *in, struct lg_cpu *uninitialized_var(cpu); unsigned int cpu_id = *off; + /* The first value tells us what this request is. */ if (get_user(req, input) != 0) return -EFAULT; input++; diff --git a/drivers/lguest/page_tables.c b/drivers/lguest/page_tables.c index a7f64a9d67e0..d93500f24fbb 100644 --- a/drivers/lguest/page_tables.c +++ b/drivers/lguest/page_tables.c @@ -2,8 +2,8 @@ * previous encounters. It's functional, and as neat as it can be in the * circumstances, but be wary, for these things are subtle and break easily. * The Guest provides a virtual to physical mapping, but we can neither trust - * it nor use it: we verify and convert it here to point the hardware to the - * actual Guest pages when running the Guest. :*/ + * it nor use it: we verify and convert it here then point the CPU to the + * converted Guest pages when running the Guest. :*/ /* Copyright (C) Rusty Russell IBM Corporation 2006. * GPL v2 and any later version */ @@ -106,6 +106,11 @@ static unsigned long gpte_addr(pgd_t gpgd, unsigned long vaddr) BUG_ON(!(pgd_flags(gpgd) & _PAGE_PRESENT)); return gpage + ((vaddr>>PAGE_SHIFT) % PTRS_PER_PTE) * sizeof(pte_t); } +/*:*/ + +/*M:014 get_pfn is slow; it takes the mmap sem and calls get_user_pages. We + * could probably try to grab batches of pages here as an optimization + * (ie. pre-faulting). :*/ /*H:350 This routine takes a page number given by the Guest and converts it to * an actual, physical page number. It can fail for several reasons: the @@ -113,8 +118,8 @@ static unsigned long gpte_addr(pgd_t gpgd, unsigned long vaddr) * and the page is read-only, or the write flag was set and the page was * shared so had to be copied, but we ran out of memory. * - * This holds a reference to the page, so release_pte() is careful to - * put that back. */ + * This holds a reference to the page, so release_pte() is careful to put that + * back. */ static unsigned long get_pfn(unsigned long virtpfn, int write) { struct page *page; @@ -532,13 +537,13 @@ static void do_set_pte(struct lg_cpu *cpu, int idx, * all processes. So when the page table above that address changes, we update * all the page tables, not just the current one. This is rare. * - * The benefit is that when we have to track a new page table, we can copy keep - * all the kernel mappings. This speeds up context switch immensely. */ + * The benefit is that when we have to track a new page table, we can keep all + * the kernel mappings. This speeds up context switch immensely. */ void guest_set_pte(struct lg_cpu *cpu, unsigned long gpgdir, unsigned long vaddr, pte_t gpte) { - /* Kernel mappings must be changed on all top levels. Slow, but - * doesn't happen often. */ + /* Kernel mappings must be changed on all top levels. Slow, but doesn't + * happen often. */ if (vaddr >= cpu->lg->kernel_address) { unsigned int i; for (i = 0; i < ARRAY_SIZE(cpu->lg->pgdirs); i++) @@ -704,12 +709,11 @@ static __init void populate_switcher_pte_page(unsigned int cpu, /* We've made it through the page table code. Perhaps our tired brains are * still processing the details, or perhaps we're simply glad it's over. * - * If nothing else, note that all this complexity in juggling shadow page - * tables in sync with the Guest's page tables is for one reason: for most - * Guests this page table dance determines how bad performance will be. This - * is why Xen uses exotic direct Guest pagetable manipulation, and why both - * Intel and AMD have implemented shadow page table support directly into - * hardware. + * If nothing else, note that all this complexity in juggling shadow page tables + * in sync with the Guest's page tables is for one reason: for most Guests this + * page table dance determines how bad performance will be. This is why Xen + * uses exotic direct Guest pagetable manipulation, and why both Intel and AMD + * have implemented shadow page table support directly into hardware. * * There is just one file remaining in the Host. */ diff --git a/drivers/lguest/x86/core.c b/drivers/lguest/x86/core.c index 635187812d52..5126d5d9ea0e 100644 --- a/drivers/lguest/x86/core.c +++ b/drivers/lguest/x86/core.c @@ -17,6 +17,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +/*P:450 This file contains the x86-specific lguest code. It used to be all + * mixed in with drivers/lguest/core.c but several foolhardy code slashers + * wrestled most of the dependencies out to here in preparation for porting + * lguest to other architectures (see what I mean by foolhardy?). + * + * This also contains a couple of non-obvious setup and teardown pieces which + * were implemented after days of debugging pain. :*/ #include #include #include @@ -157,6 +164,8 @@ static void run_guest_once(struct lg_cpu *cpu, struct lguest_pages *pages) * also simplify copy_in_guest_info(). Note that we'd still need to restore * things when we exit to Launcher userspace, but that's fairly easy. * + * We could also try using this hooks for PGE, but that might be too expensive. + * * The hooks were designed for KVM, but we can also put them to good use. :*/ /*H:040 This is the i386-specific code to setup and run the Guest. Interrupts @@ -182,7 +191,7 @@ void lguest_arch_run_guest(struct lg_cpu *cpu) * was doing. */ run_guest_once(cpu, lguest_pages(raw_smp_processor_id())); - /* Note that the "regs" pointer contains two extra entries which are + /* Note that the "regs" structure contains two extra entries which are * not really registers: a trap number which says what interrupt or * trap made the switcher code come back, and an error code which some * traps set. */ @@ -293,11 +302,10 @@ void lguest_arch_handle_trap(struct lg_cpu *cpu) break; case 14: /* We've intercepted a Page Fault. */ /* The Guest accessed a virtual address that wasn't mapped. - * This happens a lot: we don't actually set up most of the - * page tables for the Guest at all when we start: as it runs - * it asks for more and more, and we set them up as - * required. In this case, we don't even tell the Guest that - * the fault happened. + * This happens a lot: we don't actually set up most of the page + * tables for the Guest at all when we start: as it runs it asks + * for more and more, and we set them up as required. In this + * case, we don't even tell the Guest that the fault happened. * * The errcode tells whether this was a read or a write, and * whether kernel or userspace code. */ @@ -342,7 +350,7 @@ void lguest_arch_handle_trap(struct lg_cpu *cpu) if (!deliver_trap(cpu, cpu->regs->trapnum)) /* If the Guest doesn't have a handler (either it hasn't * registered any yet, or it's one of the faults we don't let - * it handle), it dies with a cryptic error message. */ + * it handle), it dies with this cryptic error message. */ kill_guest(cpu, "unhandled trap %li at %#lx (%#lx)", cpu->regs->trapnum, cpu->regs->eip, cpu->regs->trapnum == 14 ? cpu->arch.last_pagefault @@ -375,8 +383,8 @@ void __init lguest_arch_host_init(void) * The only exception is the interrupt handlers in switcher.S: their * addresses are placed in a table (default_idt_entries), so we need to * update the table with the new addresses. switcher_offset() is a - * convenience function which returns the distance between the builtin - * switcher code and the high-mapped copy we just made. */ + * convenience function which returns the distance between the + * compiled-in switcher code and the high-mapped copy we just made. */ for (i = 0; i < IDT_ENTRIES; i++) default_idt_entries[i] += switcher_offset(); @@ -416,7 +424,7 @@ void __init lguest_arch_host_init(void) state->guest_gdt_desc.address = (long)&state->guest_gdt; /* We know where we want the stack to be when the Guest enters - * the switcher: in pages->regs. The stack grows upwards, so + * the Switcher: in pages->regs. The stack grows upwards, so * we start it at the end of that structure. */ state->guest_tss.sp0 = (long)(&pages->regs + 1); /* And this is the GDT entry to use for the stack: we keep a @@ -513,8 +521,8 @@ int lguest_arch_init_hypercalls(struct lg_cpu *cpu) { u32 tsc_speed; - /* The pointer to the Guest's "struct lguest_data" is the only - * argument. We check that address now. */ + /* The pointer to the Guest's "struct lguest_data" is the only argument. + * We check that address now. */ if (!lguest_address_ok(cpu->lg, cpu->hcall->arg1, sizeof(*cpu->lg->lguest_data))) return -EFAULT; @@ -546,6 +554,7 @@ int lguest_arch_init_hypercalls(struct lg_cpu *cpu) return 0; } +/*:*/ /*L:030 lguest_arch_setup_regs() * diff --git a/drivers/lguest/x86/switcher_32.S b/drivers/lguest/x86/switcher_32.S index 0af8baaa0d4a..3fc15318a80f 100644 --- a/drivers/lguest/x86/switcher_32.S +++ b/drivers/lguest/x86/switcher_32.S @@ -1,6 +1,6 @@ -/*P:900 This is the Switcher: code which sits at 0xFFC00000 to do the low-level - * Guest<->Host switch. It is as simple as it can be made, but it's naturally - * very specific to x86. +/*P:900 This is the Switcher: code which sits at 0xFFC00000 astride both the + * Host and Guest to do the low-level Guest<->Host switch. It is as simple as + * it can be made, but it's naturally very specific to x86. * * You have now completed Preparation. If this has whet your appetite; if you * are feeling invigorated and refreshed then the next, more challenging stage @@ -189,7 +189,7 @@ ENTRY(switch_to_guest) // Interrupts are turned back on: we are Guest. iret -// We treat two paths to switch back to the Host +// We tread two paths to switch back to the Host // Yet both must save Guest state and restore Host // So we put the routine in a macro. #define SWITCH_TO_HOST \ diff --git a/include/asm-x86/lguest_hcall.h b/include/asm-x86/lguest_hcall.h index 758b9a5d4539..f239e7069cab 100644 --- a/include/asm-x86/lguest_hcall.h +++ b/include/asm-x86/lguest_hcall.h @@ -27,7 +27,7 @@ #ifndef __ASSEMBLY__ #include -/*G:031 First, how does our Guest contact the Host to ask for privileged +/*G:031 But first, how does our Guest contact the Host to ask for privileged * operations? There are two ways: the direct way is to make a "hypercall", * to make requests of the Host Itself. * diff --git a/include/linux/lguest_launcher.h b/include/linux/lguest_launcher.h index 589be3e1f3ac..e7217dc58f39 100644 --- a/include/linux/lguest_launcher.h +++ b/include/linux/lguest_launcher.h @@ -16,6 +16,10 @@ * a new device, we simply need to write a new virtio driver and create support * for it in the Launcher: this code won't need to change. * + * Virtio devices are also used by kvm, so we can simply reuse their optimized + * device drivers. And one day when everyone uses virtio, my plan will be + * complete. Bwahahahah! + * * Devices are described by a simplified ID, a status byte, and some "config" * bytes which describe this device's configuration. This is placed by the * Launcher just above the top of physical memory: @@ -26,7 +30,7 @@ struct lguest_device_desc { /* The number of virtqueues (first in config array) */ __u8 num_vq; /* The number of bytes of feature bits. Multiply by 2: one for host - * features and one for guest acknowledgements. */ + * features and one for Guest acknowledgements. */ __u8 feature_len; /* The number of bytes of the config array after virtqueues. */ __u8 config_len; -- cgit v1.2.3-59-g8ed1b From 50fd4407b8bfbde7c1a0bfe4f24de7df37164342 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 27 Mar 2008 17:42:50 -0700 Subject: [NET]: Use local_irq_{save,restore}() in napi_complete(). Based upon a lockdep report. Since ->poll() can be invoked from netpoll with interrupts disabled, we must not unconditionally enable interrupts in napi_complete(). Instead we must use local_irq_{save,restore}(). Noticed by Peter Zijlstra: netpoll_poll() poll_napi() spin_trylock(&napi->poll_lock) poll_one_napi() napi->poll() := sky2_poll() napi_complete() local_irq_disable() local_irq_enable() <--- *BUG* irq_exit() do_softirq() net_rx_action() spin_lock(&napi->poll_lock) <--- Deadlock! Because we still hold the lock.... Signed-off-by: David S. Miller --- include/linux/netdevice.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index a2f003239c85..fae6a7ececdb 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -383,9 +383,11 @@ static inline void __napi_complete(struct napi_struct *n) static inline void napi_complete(struct napi_struct *n) { - local_irq_disable(); + unsigned long flags; + + local_irq_save(flags); __napi_complete(n); - local_irq_enable(); + local_irq_restore(flags); } /** -- cgit v1.2.3-59-g8ed1b From 7c4b93d8269b9d35971a8239426b1f6ddc3d5ef7 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Fri, 21 Mar 2008 23:59:49 -0400 Subject: [PATCH] count ghost references to vfsmounts make propagate_mount_busy() exclude references from the vfsmounts that had been isolated by umount_tree() and are just waiting for release_mounts() to dispose of their ->mnt_parent/->mnt_mountpoint. Signed-off-by: Al Viro --- fs/namespace.c | 5 ++++- fs/pnode.c | 2 +- include/linux/mount.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/fs/namespace.c b/fs/namespace.c index 6324dfc80dc6..c175218ebae1 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -548,6 +548,7 @@ void release_mounts(struct list_head *head) m = mnt->mnt_parent; mnt->mnt_mountpoint = mnt->mnt_root; mnt->mnt_parent = mnt; + m->mnt_ghosts--; spin_unlock(&vfsmount_lock); dput(dentry); mntput(m); @@ -572,8 +573,10 @@ void umount_tree(struct vfsmount *mnt, int propagate, struct list_head *kill) __touch_mnt_namespace(p->mnt_ns); p->mnt_ns = NULL; list_del_init(&p->mnt_child); - if (p->mnt_parent != p) + if (p->mnt_parent != p) { + p->mnt_parent->mnt_ghosts++; p->mnt_mountpoint->d_mounted--; + } change_mnt_propagation(p, MS_PRIVATE); } } diff --git a/fs/pnode.c b/fs/pnode.c index 05ba692bc540..1d8f5447f3f7 100644 --- a/fs/pnode.c +++ b/fs/pnode.c @@ -225,7 +225,7 @@ out: */ static inline int do_refcount_check(struct vfsmount *mnt, int count) { - int mycount = atomic_read(&mnt->mnt_count); + int mycount = atomic_read(&mnt->mnt_count) - mnt->mnt_ghosts; return (mycount > count); } diff --git a/include/linux/mount.h b/include/linux/mount.h index 6d3047d8c91c..dac5e67ff3ee 100644 --- a/include/linux/mount.h +++ b/include/linux/mount.h @@ -61,6 +61,7 @@ struct vfsmount { atomic_t mnt_count; int mnt_expiry_mark; /* true if marked for expiry */ int mnt_pinned; + int mnt_ghosts; }; static inline struct vfsmount *mntget(struct vfsmount *mnt) -- cgit v1.2.3-59-g8ed1b From c35038becad0adb0e25261fff66d85b1a6ddd0c2 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 22 Mar 2008 00:46:23 -0400 Subject: [PATCH] do shrink_submounts() for all fs types ... and take it out of ->umount_begin() instances. Call with all locks already taken (by do_umount()) and leave calling release_mounts() to caller (it will do release_mounts() anyway, so we can just put into the same list). Signed-off-by: Al Viro --- fs/afs/internal.h | 1 - fs/afs/mntpt.c | 8 -------- fs/afs/super.c | 1 - fs/cifs/cifs_dfs_ref.c | 1 - fs/namespace.c | 23 ++++++++++------------- fs/nfs/super.c | 2 -- include/linux/mount.h | 1 - 7 files changed, 10 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/fs/afs/internal.h b/fs/afs/internal.h index 5ca3625cd39e..9ba16edc0af2 100644 --- a/fs/afs/internal.h +++ b/fs/afs/internal.h @@ -573,7 +573,6 @@ extern const struct file_operations afs_mntpt_file_operations; extern int afs_mntpt_check_symlink(struct afs_vnode *, struct key *); extern void afs_mntpt_kill_timer(void); -extern void afs_umount_begin(struct vfsmount *, int); /* * proc.c diff --git a/fs/afs/mntpt.c b/fs/afs/mntpt.c index a3510b8ba3e7..2f5503902c37 100644 --- a/fs/afs/mntpt.c +++ b/fs/afs/mntpt.c @@ -283,11 +283,3 @@ void afs_mntpt_kill_timer(void) cancel_delayed_work(&afs_mntpt_expiry_timer); flush_scheduled_work(); } - -/* - * begin unmount by attempting to remove all automounted mountpoints we added - */ -void afs_umount_begin(struct vfsmount *vfsmnt, int flags) -{ - shrink_submounts(vfsmnt, &afs_vfsmounts); -} diff --git a/fs/afs/super.c b/fs/afs/super.c index 36bbce45f44b..4b572b801d8d 100644 --- a/fs/afs/super.c +++ b/fs/afs/super.c @@ -50,7 +50,6 @@ static const struct super_operations afs_super_ops = { .write_inode = afs_write_inode, .destroy_inode = afs_destroy_inode, .clear_inode = afs_clear_inode, - .umount_begin = afs_umount_begin, .put_super = afs_put_super, .show_options = generic_show_options, }; diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c index a1a95b027136..56c924033b78 100644 --- a/fs/cifs/cifs_dfs_ref.c +++ b/fs/cifs/cifs_dfs_ref.c @@ -33,7 +33,6 @@ void dfs_shrink_umount_helper(struct vfsmount *vfsmnt) { mark_mounts_for_expiry(&cifs_dfs_automount_list); mark_mounts_for_expiry(&cifs_dfs_automount_list); - shrink_submounts(vfsmnt, &cifs_dfs_automount_list); } /** diff --git a/fs/namespace.c b/fs/namespace.c index 1c78917ec930..7bd74b25930c 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -581,6 +581,8 @@ void umount_tree(struct vfsmount *mnt, int propagate, struct list_head *kill) } } +static void shrink_submounts(struct vfsmount *mnt, struct list_head *umounts); + static int do_umount(struct vfsmount *mnt, int flags) { struct super_block *sb = mnt->mnt_sb; @@ -653,6 +655,9 @@ static int do_umount(struct vfsmount *mnt, int flags) spin_lock(&vfsmount_lock); event++; + if (!(flags & MNT_DETACH)) + shrink_submounts(mnt, &umount_list); + retval = -EBUSY; if (flags & MNT_DETACH || !propagate_mount_busy(mnt, 2)) { if (!list_empty(&mnt->mnt_list)) @@ -1302,30 +1307,22 @@ resume: * process a list of expirable mountpoints with the intent of discarding any * submounts of a specific parent mountpoint */ -void shrink_submounts(struct vfsmount *mountpoint, struct list_head *mounts) +static void shrink_submounts(struct vfsmount *mnt, struct list_head *umounts) { LIST_HEAD(graveyard); - LIST_HEAD(umounts); - struct vfsmount *mnt; + struct vfsmount *m; - down_write(&namespace_sem); - spin_lock(&vfsmount_lock); /* extract submounts of 'mountpoint' from the expiration list */ - while (select_submounts(mountpoint, &graveyard)) { + while (select_submounts(mnt, &graveyard)) { while (!list_empty(&graveyard)) { - mnt = list_first_entry(&graveyard, struct vfsmount, + m = list_first_entry(&graveyard, struct vfsmount, mnt_expire); touch_mnt_namespace(mnt->mnt_ns); - umount_tree(mnt, 1, &umounts); + umount_tree(mnt, 1, umounts); } } - spin_unlock(&vfsmount_lock); - up_write(&namespace_sem); - release_mounts(&umounts); } -EXPORT_SYMBOL_GPL(shrink_submounts); - /* * Some copy_from_user() implementations do not return the exact number of * bytes remaining to copy on a fault. But copy_mount_options() requires that. diff --git a/fs/nfs/super.c b/fs/nfs/super.c index dd4dfcd632ec..f9219024f31a 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -589,8 +589,6 @@ static void nfs_umount_begin(struct vfsmount *vfsmnt, int flags) struct nfs_server *server = NFS_SB(vfsmnt->mnt_sb); struct rpc_clnt *rpc; - shrink_submounts(vfsmnt, &nfs_automount_list); - if (!(flags & MNT_FORCE)) return; /* -EIO all pending I/O */ diff --git a/include/linux/mount.h b/include/linux/mount.h index dac5e67ff3ee..5ee2df217cdf 100644 --- a/include/linux/mount.h +++ b/include/linux/mount.h @@ -99,7 +99,6 @@ extern int do_add_mount(struct vfsmount *newmnt, struct nameidata *nd, int mnt_flags, struct list_head *fslist); extern void mark_mounts_for_expiry(struct list_head *mounts); -extern void shrink_submounts(struct vfsmount *mountpoint, struct list_head *mounts); extern spinlock_t vfsmount_lock; extern dev_t name_to_dev_t(char *name); -- cgit v1.2.3-59-g8ed1b From 8c703d35fa91911dd92a18c31a718853f483ad80 Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Fri, 28 Mar 2008 14:15:49 -0700 Subject: in_atomic(): document why it is unsuitable for general use Discourage people from inappropriately using in_atomic() Signed-off-by: Jonathan Corbet Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/hardirq.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h index 49829988bfa0..897f723bd222 100644 --- a/include/linux/hardirq.h +++ b/include/linux/hardirq.h @@ -72,6 +72,13 @@ #define in_softirq() (softirq_count()) #define in_interrupt() (irq_count()) +/* + * Are we running in atomic context? WARNING: this macro cannot + * always detect atomic context; in particular, it cannot know about + * held spinlocks in non-preemptible kernels. Thus it should not be + * used in the general case to determine whether sleeping is possible. + * Do not use in_atomic() in driver code. + */ #define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != 0) #ifdef CONFIG_PREEMPT -- cgit v1.2.3-59-g8ed1b From 3afe3925987adc3fc052abe404e44520c2072fc8 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Fri, 28 Mar 2008 14:16:01 -0700 Subject: kernel: add bit rotation helpers for 16 and 8 bit Will replace open-coded variants elsewhere. Done in the same style as the 32-bit versions. Signed-off-by: Harvey Harrison Acked-by: Randy Dunlap Cc: Johannes Berg Cc: John W. Linville Cc: Joe Perches Cc: Jiri Benc Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/bitops.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'include') diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 69c1edb9fe54..40d54731de7e 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -65,6 +65,46 @@ static inline __u32 ror32(__u32 word, unsigned int shift) return (word >> shift) | (word << (32 - shift)); } +/** + * rol16 - rotate a 16-bit value left + * @word: value to rotate + * @shift: bits to roll + */ +static inline __u16 rol16(__u16 word, unsigned int shift) +{ + return (word << shift) | (word >> (16 - shift)); +} + +/** + * ror16 - rotate a 16-bit value right + * @word: value to rotate + * @shift: bits to roll + */ +static inline __u16 ror16(__u16 word, unsigned int shift) +{ + return (word >> shift) | (word << (16 - shift)); +} + +/** + * rol8 - rotate an 8-bit value left + * @word: value to rotate + * @shift: bits to roll + */ +static inline __u8 rol8(__u8 word, unsigned int shift) +{ + return (word << shift) | (word >> (8 - shift)); +} + +/** + * ror8 - rotate an 8-bit value right + * @word: value to rotate + * @shift: bits to roll + */ +static inline __u8 ror8(__u8 word, unsigned int shift) +{ + return (word >> shift) | (word << (8 - shift)); +} + static inline unsigned fls_long(unsigned long l) { if (sizeof(l) == 4) -- cgit v1.2.3-59-g8ed1b From 5ac7ec85bcc70ef605657fb2d1106d27ab3bd131 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 28 Mar 2008 14:16:03 -0700 Subject: ext3: don't export ext3_fs.h and jbd.h Neither of the headers actually compiles when included from userpsace nor should it be made available as userspace tools should be using the libraries or at least headers from e2fsprogs. Signed-off-by: Christoph Hellwig Acked-by: "Theodore Ts'o" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/Kbuild | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/linux/Kbuild b/include/linux/Kbuild index 4108b38ebb16..4a446a19295e 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -195,7 +195,6 @@ unifdef-y += ethtool.h unifdef-y += eventpoll.h unifdef-y += signalfd.h unifdef-y += ext2_fs.h -unifdef-y += ext3_fs.h unifdef-y += fb.h unifdef-y += fcntl.h unifdef-y += filter.h @@ -248,7 +247,6 @@ unifdef-y += isdn.h unifdef-y += isdnif.h unifdef-y += isdn_divertif.h unifdef-y += isdn_ppp.h -unifdef-y += jbd.h unifdef-y += joystick.h unifdef-y += kdev_t.h unifdef-y += kd.h -- cgit v1.2.3-59-g8ed1b From a5a04819c5740cb1aa217af2cc8f5ef26f33d744 Mon Sep 17 00:00:00 2001 From: Joonwoo Park Date: Fri, 28 Mar 2008 16:28:36 -0700 Subject: [LLC]: station source mac address kill unnecessary llc_station_mac_sa. Signed-off-by: Joonwoo Park Acked-by: Arnaldo Carvalho de Melo Signed-off-by: David S. Miller --- include/net/llc.h | 1 - net/llc/llc_core.c | 8 +------- net/llc/llc_station.c | 6 +++--- 3 files changed, 4 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/net/llc.h b/include/net/llc.h index f5024583fc8b..7940da1606e7 100644 --- a/include/net/llc.h +++ b/include/net/llc.h @@ -65,7 +65,6 @@ struct llc_sap { extern struct list_head llc_sap_list; extern rwlock_t llc_sap_list_lock; -extern unsigned char llc_station_mac_sa[ETH_ALEN]; extern int llc_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt, struct net_device *orig_dev); diff --git a/net/llc/llc_core.c b/net/llc/llc_core.c index 248b5903bb13..00de27cef46b 100644 --- a/net/llc/llc_core.c +++ b/net/llc/llc_core.c @@ -25,8 +25,6 @@ LIST_HEAD(llc_sap_list); DEFINE_RWLOCK(llc_sap_list_lock); -unsigned char llc_station_mac_sa[ETH_ALEN]; - /** * llc_sap_alloc - allocates and initializes sap. * @@ -37,8 +35,8 @@ static struct llc_sap *llc_sap_alloc(void) struct llc_sap *sap = kzalloc(sizeof(*sap), GFP_ATOMIC); if (sap) { + /* sap->laddr.mac - leave as a null, it's filled by bind */ sap->state = LLC_SAP_STATE_ACTIVE; - memcpy(sap->laddr.mac, llc_station_mac_sa, ETH_ALEN); rwlock_init(&sap->sk_list.lock); atomic_set(&sap->refcnt, 1); } @@ -167,10 +165,6 @@ static int __init llc_init(void) if (dev != NULL) dev = next_net_device(dev); - if (dev != NULL) - memcpy(llc_station_mac_sa, dev->dev_addr, ETH_ALEN); - else - memset(llc_station_mac_sa, 0, ETH_ALEN); dev_add_pack(&llc_packet_type); dev_add_pack(&llc_tr_packet_type); return 0; diff --git a/net/llc/llc_station.c b/net/llc/llc_station.c index 6f2ea2090322..959e7f31833b 100644 --- a/net/llc/llc_station.c +++ b/net/llc/llc_station.c @@ -259,7 +259,7 @@ static int llc_station_ac_send_null_dsap_xid_c(struct sk_buff *skb) goto out; llc_pdu_header_init(nskb, LLC_PDU_TYPE_U, 0, 0, LLC_PDU_CMD); llc_pdu_init_as_xid_cmd(nskb, LLC_XID_NULL_CLASS_2, 127); - rc = llc_mac_hdr_init(nskb, llc_station_mac_sa, llc_station_mac_sa); + rc = llc_mac_hdr_init(nskb, skb->dev->dev_addr, skb->dev->dev_addr); if (unlikely(rc)) goto free; llc_station_send_pdu(nskb); @@ -283,7 +283,7 @@ static int llc_station_ac_send_xid_r(struct sk_buff *skb) llc_pdu_decode_ssap(skb, &dsap); llc_pdu_header_init(nskb, LLC_PDU_TYPE_U, 0, dsap, LLC_PDU_RSP); llc_pdu_init_as_xid_rsp(nskb, LLC_XID_NULL_CLASS_2, 127); - rc = llc_mac_hdr_init(nskb, llc_station_mac_sa, mac_da); + rc = llc_mac_hdr_init(nskb, skb->dev->dev_addr, mac_da); if (unlikely(rc)) goto free; llc_station_send_pdu(nskb); @@ -307,7 +307,7 @@ static int llc_station_ac_send_test_r(struct sk_buff *skb) llc_pdu_decode_ssap(skb, &dsap); llc_pdu_header_init(nskb, LLC_PDU_TYPE_U, 0, dsap, LLC_PDU_RSP); llc_pdu_init_as_test_rsp(nskb, skb); - rc = llc_mac_hdr_init(nskb, llc_station_mac_sa, mac_da); + rc = llc_mac_hdr_init(nskb, skb->dev->dev_addr, mac_da); if (unlikely(rc)) goto free; llc_station_send_pdu(nskb); -- cgit v1.2.3-59-g8ed1b From 0ef4730927c54cac5006759fa0cf50fbeff9d191 Mon Sep 17 00:00:00 2001 From: Matti Linnanvuori Date: Fri, 28 Mar 2008 16:33:00 -0700 Subject: net: Comment dev_kfree_skb_irq and dev_kfree_skb_any better Comment dev_kfree_skb_irq and dev_kfree_skb_any better. Signed-off-by: Matti Linnanvuori Signed-off-by: David S. Miller --- include/linux/netdevice.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index fae6a7ececdb..ee81906b5164 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1074,12 +1074,14 @@ static inline int netif_is_multiqueue(const struct net_device *dev) } /* Use this variant when it is known for sure that it - * is executing from interrupt context. + * is executing from hardware interrupt context or with hardware interrupts + * disabled. */ extern void dev_kfree_skb_irq(struct sk_buff *skb); /* Use this variant in places where it could be invoked - * either from interrupt or non-interrupt context. + * from either hardware interrupt or other context, with hardware interrupts + * either disabled or enabled. */ extern void dev_kfree_skb_any(struct sk_buff *skb); -- cgit v1.2.3-59-g8ed1b From 3ec25ebd69dc120d0590e64caaf1477aa88c8a93 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 27 Mar 2008 18:37:14 +0900 Subject: libata: ATA_EHI_LPM should be ATA_EH_LPM EH actions are ATA_EH_* not ATA_EHI_*. Rename ATA_EHI_LPM to ATA_EH_LPM. Signed-off-by: Tejun Heo Cc: Kristen Carlson Accardi Signed-off-by: Jeff Garzik --- drivers/ata/libata-core.c | 2 +- drivers/ata/libata-eh.c | 2 +- include/linux/libata.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index c4248b37ff64..48519887f94a 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -972,7 +972,7 @@ static void ata_dev_disable_pm(struct ata_device *dev) void ata_lpm_schedule(struct ata_port *ap, enum link_pm policy) { ap->pm_policy = policy; - ap->link.eh_info.action |= ATA_EHI_LPM; + ap->link.eh_info.action |= ATA_EH_LPM; ap->link.eh_info.flags |= ATA_EHI_NO_AUTOPSY; ata_port_schedule_eh(ap); } diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index 681252fd8143..a5830329eda4 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -2748,7 +2748,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset, ehc->i.flags &= ~ATA_EHI_SETMODE; } - if (ehc->i.action & ATA_EHI_LPM) + if (ehc->i.action & ATA_EH_LPM) ata_link_for_each_dev(dev, link) ata_dev_enable_pm(dev, ap->pm_policy); diff --git a/include/linux/libata.h b/include/linux/libata.h index 269cdba09578..b064bfeb69ee 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -295,6 +295,7 @@ enum { ATA_EH_SOFTRESET = (1 << 1), ATA_EH_HARDRESET = (1 << 2), ATA_EH_ENABLE_LINK = (1 << 3), + ATA_EH_LPM = (1 << 4), /* link power management action */ ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET, ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE, @@ -304,7 +305,6 @@ enum { ATA_EHI_RESUME_LINK = (1 << 1), /* resume link (reset modifier) */ ATA_EHI_NO_AUTOPSY = (1 << 2), /* no autopsy */ ATA_EHI_QUIET = (1 << 3), /* be quiet */ - ATA_EHI_LPM = (1 << 4), /* link power management action */ ATA_EHI_DID_SOFTRESET = (1 << 16), /* already soft-reset this port */ ATA_EHI_DID_HARDRESET = (1 << 17), /* already soft-reset this port */ -- cgit v1.2.3-59-g8ed1b From 729d4de96a5c090e40a918a41f63b7fb1b27c240 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Sat, 29 Mar 2008 19:55:17 +0100 Subject: ide: fix defining SUPPORT_VLB_SYNC We need to check for CONFIG_{CRIS,FRV} not {CRIS,FRV}. Signed-off-by: Bartlomiej Zolnierkiewicz --- include/linux/ide.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/ide.h b/include/linux/ide.h index a3b69c10d667..bc26b2f27359 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -26,7 +26,7 @@ #include #include -#if defined(CRIS) || defined(FRV) +#if defined(CONFIG_CRIS) || defined(CONFIG_FRV) # define SUPPORT_VLB_SYNC 0 #else # define SUPPORT_VLB_SYNC 1 -- cgit v1.2.3-59-g8ed1b From 7c43f2b888f9ca1fcb7b07abc4cbff4ca1b8e03b Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 29 Mar 2008 03:08:18 +0000 Subject: NULL noise: frv cmpxchg() Signed-off-by: Al Viro Acked-by: Harvey Harrison Signed-off-by: Linus Torvalds --- include/asm-frv/system.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h index b400cea81487..2c57f4734746 100644 --- a/include/asm-frv/system.h +++ b/include/asm-frv/system.h @@ -234,7 +234,7 @@ extern void free_initmem(void); break; \ \ default: \ - __xg_orig = 0; \ + __xg_orig = (__typeof__(__xg_orig))0; \ asm volatile("break"); \ break; \ } \ @@ -259,7 +259,7 @@ extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new); (__force uint32_t)__xg_test, \ (__force uint32_t)__xg_new); break; \ default: \ - __xg_orig = 0; \ + __xg_orig = (__typeof__(__xg_orig))0; \ asm volatile("break"); \ break; \ } \ -- cgit v1.2.3-59-g8ed1b From 7d61c4596d11d624efb4bbcbad01f9cf2b321162 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 29 Mar 2008 03:09:28 +0000 Subject: compat_sys_wait4() prototype misannotation Signed-off-by: Al Viro Signed-off-by: Linus Torvalds --- include/linux/compat.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/compat.h b/include/linux/compat.h index a671dbff7a1f..8fa7857e153b 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -192,8 +192,8 @@ asmlinkage long compat_sys_select(int n, compat_ulong_t __user *inp, struct compat_timeval __user *tvp); asmlinkage long compat_sys_wait4(compat_pid_t pid, - compat_uint_t *stat_addr, int options, - struct compat_rusage *ru); + compat_uint_t __user *stat_addr, int options, + struct compat_rusage __user *ru); #define BITS_PER_COMPAT_LONG (8*sizeof(compat_long_t)) -- cgit v1.2.3-59-g8ed1b From b2ddb9019ea13fb7b62d8e45adcc468376af0de7 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 29 Mar 2008 03:09:38 +0000 Subject: dma_page_list ->base_address is a userland pointer Signed-off-by: Al Viro Signed-off-by: Linus Torvalds --- include/linux/dmaengine.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 261e43a4c873..34d440698293 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -423,7 +423,7 @@ void dma_async_device_unregister(struct dma_device *device); /* --- Helper iov-locking functions --- */ struct dma_page_list { - char *base_address; + char __user *base_address; int nr_pages; struct page **pages; }; -- cgit v1.2.3-59-g8ed1b From 7d7f7c3ed2c519a462a4ae989ad3d55cc7f7f6ec Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 31 Mar 2008 01:53:43 +0300 Subject: remove include/asm-sh/floppy.h This patch removes the unused include/asm-sh/floppy.h (ARCH_MAY_HAVE_PC_FDC was not enabled). Signed-off-by: Adrian Bunk Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 3 - include/asm-sh/floppy.h | 268 ------------------------------------------------ 2 files changed, 271 deletions(-) delete mode 100644 include/asm-sh/floppy.h (limited to 'include') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 12720489e458..8d2cd1de5726 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -72,9 +72,6 @@ config SYS_SUPPORTS_NUMA config SYS_SUPPORTS_PCI bool -config ARCH_MAY_HAVE_PC_FDC - bool - config STACKTRACE_SUPPORT def_bool y diff --git a/include/asm-sh/floppy.h b/include/asm-sh/floppy.h deleted file mode 100644 index 59fbfdc90dfb..000000000000 --- a/include/asm-sh/floppy.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Architecture specific parts of the Floppy driver - * include/asm-i386/floppy.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - */ -#ifndef __ASM_SH_FLOPPY_H -#define __ASM_SH_FLOPPY_H - -#include - - -/* - * The DMA channel used by the floppy controller cannot access data at - * addresses >= 16MB - * - * Went back to the 1MB limit, as some people had problems with the floppy - * driver otherwise. It doesn't matter much for performance anyway, as most - * floppy accesses go through the track buffer. - */ -#define _CROSS_64KB(a,s,vdma) \ -(!vdma && ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)) - -#define CROSS_64KB(a,s) _CROSS_64KB(a,s,use_virtual_dma & 1) - - -#define SW fd_routine[use_virtual_dma&1] -#define CSW fd_routine[can_use_virtual_dma & 1] - - -#define fd_inb(port) inb_p(port) -#define fd_outb(value,port) outb_p(value,port) - -#define fd_request_dma() CSW._request_dma(FLOPPY_DMA,"floppy") -#define fd_free_dma() CSW._free_dma(FLOPPY_DMA) -#define fd_enable_irq() enable_irq(FLOPPY_IRQ) -#define fd_disable_irq() disable_irq(FLOPPY_IRQ) -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL) -#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA) -#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size) -#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io) - -#define FLOPPY_CAN_FALLBACK_ON_NODMA - -static int virtual_dma_count; -static int virtual_dma_residue; -static char *virtual_dma_addr; -static int virtual_dma_mode; -static int doing_pdma; - -static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs) -{ - register unsigned char st; - -#undef TRACE_FLPY_INT - -#ifdef TRACE_FLPY_INT - static int calls=0; - static int bytes=0; - static int dma_wait=0; -#endif - if(!doing_pdma) { - floppy_interrupt(irq, dev_id, regs); - return; - } - -#ifdef TRACE_FLPY_INT - if(!calls) - bytes = virtual_dma_count; -#endif - - { - register int lcount; - register char *lptr; - - st = 1; - for(lcount=virtual_dma_count, lptr=virtual_dma_addr; - lcount; lcount--, lptr++) { - st=inb(virtual_dma_port+4) & 0xa0 ; - if(st != 0xa0) - break; - if(virtual_dma_mode) - outb_p(*lptr, virtual_dma_port+5); - else - *lptr = inb_p(virtual_dma_port+5); - } - virtual_dma_count = lcount; - virtual_dma_addr = lptr; - st = inb(virtual_dma_port+4); - } - -#ifdef TRACE_FLPY_INT - calls++; -#endif - if(st == 0x20) - return; - if(!(st & 0x20)) { - virtual_dma_residue += virtual_dma_count; - virtual_dma_count=0; -#ifdef TRACE_FLPY_INT - printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", - virtual_dma_count, virtual_dma_residue, calls, bytes, - dma_wait); - calls = 0; - dma_wait=0; -#endif - doing_pdma = 0; - floppy_interrupt(irq, dev_id, regs); - return; - } -#ifdef TRACE_FLPY_INT - if(!virtual_dma_count) - dma_wait++; -#endif -} - -static void fd_disable_dma(void) -{ - if(! (can_use_virtual_dma & 1)) - disable_dma(FLOPPY_DMA); - doing_pdma = 0; - virtual_dma_residue += virtual_dma_count; - virtual_dma_count=0; -} - -static int vdma_request_dma(unsigned int dmanr, const char * device_id) -{ - return 0; -} - -static void vdma_nop(unsigned int dummy) -{ -} - - -static int vdma_get_dma_residue(unsigned int dummy) -{ - return virtual_dma_count + virtual_dma_residue; -} - - -static int fd_request_irq(void) -{ - if(can_use_virtual_dma) - return request_irq(FLOPPY_IRQ, floppy_hardint, - IRQF_DISABLED, "floppy", NULL); - else - return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); -} - -static unsigned long dma_mem_alloc(unsigned long size) -{ - return __get_dma_pages(GFP_KERNEL,get_order(size)); -} - - -static unsigned long vdma_mem_alloc(unsigned long size) -{ - return (unsigned long) vmalloc(size); - -} - -#define nodma_mem_alloc(size) vdma_mem_alloc(size) - -static void _fd_dma_mem_free(unsigned long addr, unsigned long size) -{ - if((unsigned int) addr >= (unsigned int) high_memory) - return vfree((void *)addr); - else - free_pages(addr, get_order(size)); -} - -#define fd_dma_mem_free(addr, size) _fd_dma_mem_free(addr, size) - -static void _fd_chose_dma_mode(char *addr, unsigned long size) -{ - if(can_use_virtual_dma == 2) { - if((unsigned int) addr >= (unsigned int) high_memory || - virt_to_phys(addr) >= 0x10000000) - use_virtual_dma = 1; - else - use_virtual_dma = 0; - } else { - use_virtual_dma = can_use_virtual_dma & 1; - } -} - -#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size) - - -static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) -{ - doing_pdma = 1; - virtual_dma_port = io; - virtual_dma_mode = (mode == DMA_MODE_WRITE); - virtual_dma_addr = addr; - virtual_dma_count = size; - virtual_dma_residue = 0; - return 0; -} - -static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) -{ -#ifdef FLOPPY_SANITY_CHECK - if (CROSS_64KB(addr, size)) { - printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size); - return -1; - } -#endif - - __flush_purge_region(addr, size); - - /* actual, physical DMA */ - doing_pdma = 0; - clear_dma_ff(FLOPPY_DMA); - set_dma_mode(FLOPPY_DMA,mode); - set_dma_addr(FLOPPY_DMA,virt_to_phys(addr)); - set_dma_count(FLOPPY_DMA,size); - enable_dma(FLOPPY_DMA); - return 0; -} - -static struct fd_routine_l { - int (*_request_dma)(unsigned int dmanr, const char * device_id); - void (*_free_dma)(unsigned int dmanr); - int (*_get_dma_residue)(unsigned int dummy); - unsigned long (*_dma_mem_alloc) (unsigned long size); - int (*_dma_setup)(char *addr, unsigned long size, int mode, int io); -} fd_routine[] = { - { - request_dma, - free_dma, - get_dma_residue, - dma_mem_alloc, - hard_dma_setup - }, - { - vdma_request_dma, - vdma_nop, - vdma_get_dma_residue, - vdma_mem_alloc, - vdma_dma_setup - } -}; - - -static int FDC1 = 0x3f0; -static int FDC2 = -1; - -/* - * Floppy types are stored in the rtc's CMOS RAM and so rtc_lock - * is needed to prevent corrupted CMOS RAM in case "insmod floppy" - * coincides with another rtc CMOS user. Paul G. - */ -#define FLOPPY0_TYPE (4) -#define FLOPPY1_TYPE (0) - -#define N_FDC 2 -#define N_DRIVE 8 - -#define EXTRA_FLOPPY_PARAMS - -#endif /* __ASM_SH_FLOPPY_H */ -- cgit v1.2.3-59-g8ed1b From f83f1768f833cb45bc93429fdc552252a4f55ac3 Mon Sep 17 00:00:00 2001 From: Joonwoo Park Date: Mon, 31 Mar 2008 21:02:47 -0700 Subject: [LLC]: skb allocation size for responses Allocate the skb for llc responses with the received packet size by using the size adjustable llc_frame_alloc. Don't allocate useless extra payload. Cleanup magic numbers. So, this fixes oops. Reported by Jim Westfall: kernel: skb_over_panic: text:c0541fc7 len:1000 put:997 head:c166ac00 data:c166ac2f tail:0xc166b017 end:0xc166ac80 dev:eth0 kernel: ------------[ cut here ]------------ kernel: kernel BUG at net/core/skbuff.c:95! Signed-off-by: Joonwoo Park Acked-by: Arnaldo Carvalho de Melo Signed-off-by: David S. Miller --- include/net/llc_pdu.h | 4 ++-- include/net/llc_sap.h | 7 +++++-- net/llc/llc_c_ac.c | 47 +++++++++++++++++++++++++---------------------- net/llc/llc_pdu.c | 2 +- net/llc/llc_s_ac.c | 9 +++++++-- net/llc/llc_sap.c | 27 ++++++++++++++++++++++++--- net/llc/llc_station.c | 13 ++++++++++--- 7 files changed, 74 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/include/net/llc_pdu.h b/include/net/llc_pdu.h index 4a8f58b17e43..75b8e2968c9b 100644 --- a/include/net/llc_pdu.h +++ b/include/net/llc_pdu.h @@ -381,7 +381,7 @@ static inline void llc_pdu_init_as_xid_cmd(struct sk_buff *skb, xid_info->fmt_id = LLC_XID_FMT_ID; /* 0x81 */ xid_info->type = svcs_supported; xid_info->rw = rx_window << 1; /* size of receive window */ - skb_put(skb, 3); + skb_put(skb, sizeof(struct llc_xid_info)); } /** @@ -406,7 +406,7 @@ static inline void llc_pdu_init_as_xid_rsp(struct sk_buff *skb, xid_info->fmt_id = LLC_XID_FMT_ID; xid_info->type = svcs_supported; xid_info->rw = rx_window << 1; - skb_put(skb, 3); + skb_put(skb, sizeof(struct llc_xid_info)); } /* LLC Type 2 FRMR response information field format */ diff --git a/include/net/llc_sap.h b/include/net/llc_sap.h index 2c56dbece729..ed25bec2f648 100644 --- a/include/net/llc_sap.h +++ b/include/net/llc_sap.h @@ -1,5 +1,8 @@ #ifndef LLC_SAP_H #define LLC_SAP_H + +#include + /* * Copyright (c) 1997 by Procom Technology,Inc. * 2001-2003 by Arnaldo Carvalho de Melo @@ -19,8 +22,8 @@ struct sock; extern void llc_sap_rtn_pdu(struct llc_sap *sap, struct sk_buff *skb); extern void llc_save_primitive(struct sock *sk, struct sk_buff* skb, unsigned char prim); -extern struct sk_buff *llc_alloc_frame(struct sock *sk, - struct net_device *dev); +extern struct sk_buff *llc_alloc_frame(struct sock *sk, struct net_device *dev, + u8 type, u32 data_size); extern void llc_build_and_send_test_pkt(struct llc_sap *sap, struct sk_buff *skb, diff --git a/net/llc/llc_c_ac.c b/net/llc/llc_c_ac.c index 860140caa6e0..71a00225bdb3 100644 --- a/net/llc/llc_c_ac.c +++ b/net/llc/llc_c_ac.c @@ -198,7 +198,7 @@ int llc_conn_ac_send_disc_cmd_p_set_x(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -223,7 +223,7 @@ int llc_conn_ac_send_dm_rsp_f_set_p(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -249,7 +249,7 @@ int llc_conn_ac_send_dm_rsp_f_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -282,7 +282,8 @@ int llc_conn_ac_send_frmr_rsp_f_set_x(struct sock *sk, struct sk_buff *skb) llc_pdu_decode_pf_bit(skb, &f_bit); else f_bit = 0; - nskb = llc_alloc_frame(sk, llc->dev); + nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, + sizeof(struct llc_frmr_info)); if (nskb) { struct llc_sap *sap = llc->sap; @@ -306,7 +307,8 @@ int llc_conn_ac_resend_frmr_rsp_f_set_0(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, + sizeof(struct llc_frmr_info)); if (nskb) { struct llc_sap *sap = llc->sap; @@ -336,7 +338,8 @@ int llc_conn_ac_resend_frmr_rsp_f_set_p(struct sock *sk, struct sk_buff *skb) struct llc_sock *llc = llc_sk(sk); llc_pdu_decode_pf_bit(skb, &f_bit); - nskb = llc_alloc_frame(sk, llc->dev); + nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, + sizeof(struct llc_frmr_info)); if (nskb) { struct llc_sap *sap = llc->sap; struct llc_pdu_sn *pdu = llc_pdu_sn_hdr(skb); @@ -424,7 +427,7 @@ int llc_conn_ac_resend_i_xxx_x_set_0_or_send_rr(struct sock *sk, struct llc_pdu_sn *pdu = llc_pdu_sn_hdr(skb); int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -459,7 +462,7 @@ int llc_conn_ac_send_rej_cmd_p_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -483,7 +486,7 @@ int llc_conn_ac_send_rej_rsp_f_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -507,7 +510,7 @@ int llc_conn_ac_send_rej_xxx_x_set_0(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -531,7 +534,7 @@ int llc_conn_ac_send_rnr_cmd_p_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -555,7 +558,7 @@ int llc_conn_ac_send_rnr_rsp_f_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -579,7 +582,7 @@ int llc_conn_ac_send_rnr_xxx_x_set_0(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -615,7 +618,7 @@ int llc_conn_ac_opt_send_rnr_xxx_x_set_0(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -639,7 +642,7 @@ int llc_conn_ac_send_rr_cmd_p_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -663,7 +666,7 @@ int llc_conn_ac_send_rr_rsp_f_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -688,7 +691,7 @@ int llc_conn_ac_send_ack_rsp_f_set_1(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -712,7 +715,7 @@ int llc_conn_ac_send_rr_xxx_x_set_0(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -736,7 +739,7 @@ int llc_conn_ac_send_ack_xxx_x_set_0(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -770,7 +773,7 @@ int llc_conn_ac_send_sabme_cmd_p_set_x(struct sock *sk, struct sk_buff *skb) { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, 0); if (nskb) { struct llc_sap *sap = llc->sap; @@ -799,7 +802,7 @@ int llc_conn_ac_send_ua_rsp_f_set_p(struct sock *sk, struct sk_buff *skb) u8 f_bit; int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_U, 0); llc_pdu_decode_pf_bit(skb, &f_bit); if (nskb) { @@ -956,7 +959,7 @@ static int llc_conn_ac_send_rr_rsp_f_set_ackpf(struct sock *sk, { int rc = -ENOBUFS; struct llc_sock *llc = llc_sk(sk); - struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev); + struct sk_buff *nskb = llc_alloc_frame(sk, llc->dev, LLC_PDU_TYPE_S, 0); if (nskb) { struct llc_sap *sap = llc->sap; diff --git a/net/llc/llc_pdu.c b/net/llc/llc_pdu.c index fa8324396db3..2e6cb79196bb 100644 --- a/net/llc/llc_pdu.c +++ b/net/llc/llc_pdu.c @@ -241,7 +241,7 @@ void llc_pdu_init_as_frmr_rsp(struct sk_buff *skb, struct llc_pdu_sn *prev_pdu, FRMR_INFO_SET_PDU_INFO_2LONG_IND(frmr_info, vzyxw); FRMR_INFO_SET_PDU_INVALID_Nr_IND(frmr_info, vzyxw); FRMR_INFO_SET_PDU_INVALID_Ns_IND(frmr_info, vzyxw); - skb_put(skb, 5); + skb_put(skb, sizeof(struct llc_frmr_info)); } /** diff --git a/net/llc/llc_s_ac.c b/net/llc/llc_s_ac.c index ac3d93b210d2..a94bd56bcac6 100644 --- a/net/llc/llc_s_ac.c +++ b/net/llc/llc_s_ac.c @@ -103,7 +103,8 @@ int llc_sap_action_send_xid_r(struct llc_sap *sap, struct sk_buff *skb) llc_pdu_decode_sa(skb, mac_da); llc_pdu_decode_da(skb, mac_sa); llc_pdu_decode_ssap(skb, &dsap); - nskb = llc_alloc_frame(NULL, skb->dev); + nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, + sizeof(struct llc_xid_info)); if (!nskb) goto out; llc_pdu_header_init(nskb, LLC_PDU_TYPE_U, sap->laddr.lsap, dsap, @@ -144,11 +145,15 @@ int llc_sap_action_send_test_r(struct llc_sap *sap, struct sk_buff *skb) u8 mac_da[ETH_ALEN], mac_sa[ETH_ALEN], dsap; struct sk_buff *nskb; int rc = 1; + u32 data_size; llc_pdu_decode_sa(skb, mac_da); llc_pdu_decode_da(skb, mac_sa); llc_pdu_decode_ssap(skb, &dsap); - nskb = llc_alloc_frame(NULL, skb->dev); + + /* The test request command is type U (llc_len = 3) */ + data_size = ntohs(eth_hdr(skb)->h_proto) - 3; + nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, data_size); if (!nskb) goto out; llc_pdu_header_init(nskb, LLC_PDU_TYPE_U, sap->laddr.lsap, dsap, diff --git a/net/llc/llc_sap.c b/net/llc/llc_sap.c index 2525165e2e8f..e2ddde755019 100644 --- a/net/llc/llc_sap.c +++ b/net/llc/llc_sap.c @@ -24,20 +24,41 @@ #include #include +static int llc_mac_header_len(unsigned short devtype) +{ + switch (devtype) { + case ARPHRD_ETHER: + case ARPHRD_LOOPBACK: + return sizeof(struct ethhdr); +#ifdef CONFIG_TR + case ARPHRD_IEEE802_TR: + return sizeof(struct trh_hdr); +#endif + } + return 0; +} + /** * llc_alloc_frame - allocates sk_buff for frame * @dev: network device this skb will be sent over + * @type: pdu type to allocate + * @data_size: data size to allocate * * Allocates an sk_buff for frame and initializes sk_buff fields. * Returns allocated skb or %NULL when out of memory. */ -struct sk_buff *llc_alloc_frame(struct sock *sk, struct net_device *dev) +struct sk_buff *llc_alloc_frame(struct sock *sk, struct net_device *dev, + u8 type, u32 data_size) { - struct sk_buff *skb = alloc_skb(128, GFP_ATOMIC); + int hlen = type == LLC_PDU_TYPE_U ? 3 : 4; + struct sk_buff *skb; + + hlen += llc_mac_header_len(dev->type); + skb = alloc_skb(hlen + data_size, GFP_ATOMIC); if (skb) { skb_reset_mac_header(skb); - skb_reserve(skb, 50); + skb_reserve(skb, hlen); skb_reset_network_header(skb); skb_reset_transport_header(skb); skb->protocol = htons(ETH_P_802_2); diff --git a/net/llc/llc_station.c b/net/llc/llc_station.c index 959e7f31833b..83da13339490 100644 --- a/net/llc/llc_station.c +++ b/net/llc/llc_station.c @@ -253,7 +253,8 @@ static int llc_station_ac_inc_xid_r_cnt_by_1(struct sk_buff *skb) static int llc_station_ac_send_null_dsap_xid_c(struct sk_buff *skb) { int rc = 1; - struct sk_buff *nskb = llc_alloc_frame(NULL, skb->dev); + struct sk_buff *nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, + sizeof(struct llc_xid_info)); if (!nskb) goto out; @@ -274,7 +275,8 @@ static int llc_station_ac_send_xid_r(struct sk_buff *skb) { u8 mac_da[ETH_ALEN], dsap; int rc = 1; - struct sk_buff* nskb = llc_alloc_frame(NULL, skb->dev); + struct sk_buff *nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, + sizeof(struct llc_xid_info)); if (!nskb) goto out; @@ -298,7 +300,12 @@ static int llc_station_ac_send_test_r(struct sk_buff *skb) { u8 mac_da[ETH_ALEN], dsap; int rc = 1; - struct sk_buff *nskb = llc_alloc_frame(NULL, skb->dev); + u32 data_size; + struct sk_buff *nskb; + + /* The test request command is type U (llc_len = 3) */ + data_size = ntohs(eth_hdr(skb)->h_proto) - 3; + nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, data_size); if (!nskb) goto out; -- cgit v1.2.3-59-g8ed1b From a7097ff89c3204737a07eecbc83f9ae6002cc534 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 1 Apr 2008 00:22:53 -0400 Subject: Input: make sure input interfaces pin parent input devices Recent driver core change causes references to parent devices being dropped early, at device_del() time, as opposed to when all children are freed. This causes oops in evdev with grabbed devices. Take the reference to the parent input device ourselves to ensure that it stays around long enough. Signed-off-by: Dmitry Torokhov --- drivers/input/evdev.c | 6 ++---- drivers/input/joydev.c | 3 ++- drivers/input/mousedev.c | 3 ++- include/linux/input.h | 5 +++-- 4 files changed, 9 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c index 99562cee827e..b32984bc516f 100644 --- a/drivers/input/evdev.c +++ b/drivers/input/evdev.c @@ -124,6 +124,7 @@ static void evdev_free(struct device *dev) { struct evdev *evdev = container_of(dev, struct evdev, dev); + input_put_device(evdev->handle.dev); kfree(evdev); } @@ -853,9 +854,6 @@ static void evdev_cleanup(struct evdev *evdev) evdev_hangup(evdev); evdev_remove_chrdev(evdev); - if (evdev->grab) - evdev_ungrab(evdev, evdev->grab); - /* evdev is marked dead so no one else accesses evdev->open */ if (evdev->open) { input_flush_device(handle, NULL); @@ -896,7 +894,7 @@ static int evdev_connect(struct input_handler *handler, struct input_dev *dev, evdev->exist = 1; evdev->minor = minor; - evdev->handle.dev = dev; + evdev->handle.dev = input_get_device(dev); evdev->handle.name = evdev->name; evdev->handle.handler = handler; evdev->handle.private = evdev; diff --git a/drivers/input/joydev.c b/drivers/input/joydev.c index 22b2789ef58a..65d7077a75a1 100644 --- a/drivers/input/joydev.c +++ b/drivers/input/joydev.c @@ -171,6 +171,7 @@ static void joydev_free(struct device *dev) { struct joydev *joydev = container_of(dev, struct joydev, dev); + input_put_device(joydev->handle.dev); kfree(joydev); } @@ -750,7 +751,7 @@ static int joydev_connect(struct input_handler *handler, struct input_dev *dev, joydev->minor = minor; joydev->exist = 1; - joydev->handle.dev = dev; + joydev->handle.dev = input_get_device(dev); joydev->handle.name = joydev->name; joydev->handle.handler = handler; joydev->handle.private = joydev; diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c index bbbe5e81adc1..b989748598ae 100644 --- a/drivers/input/mousedev.c +++ b/drivers/input/mousedev.c @@ -414,6 +414,7 @@ static void mousedev_free(struct device *dev) { struct mousedev *mousedev = container_of(dev, struct mousedev, dev); + input_put_device(mousedev->handle.dev); kfree(mousedev); } @@ -865,7 +866,7 @@ static struct mousedev *mousedev_create(struct input_dev *dev, mousedev->minor = minor; mousedev->exist = 1; - mousedev->handle.dev = dev; + mousedev->handle.dev = input_get_device(dev); mousedev->handle.name = mousedev->name; mousedev->handle.handler = handler; mousedev->handle.private = mousedev; diff --git a/include/linux/input.h b/include/linux/input.h index 1bdc39a8c76c..cae2c35d1206 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -1227,12 +1227,13 @@ void input_free_device(struct input_dev *dev); static inline struct input_dev *input_get_device(struct input_dev *dev) { - return to_input_dev(get_device(&dev->dev)); + return dev ? to_input_dev(get_device(&dev->dev)) : NULL; } static inline void input_put_device(struct input_dev *dev) { - put_device(&dev->dev); + if (dev) + put_device(&dev->dev); } static inline void *input_get_drvdata(struct input_dev *dev) -- cgit v1.2.3-59-g8ed1b From 758e285faca4db948ecddefb523007255b29cdb7 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 27 Mar 2008 16:09:31 +0300 Subject: [MIPS] Alchemy: work around clock misdetection on early Au1000 Work around the CPU clock miscalculation on Au1000DA/HA/HB due the sys_cpupll register being write-only, i.e. actually do what the comment before cal_r4off() function advertised for years but the code failed at. This is achieved by just giving user a chance to define the clock explicitly in the board config. via CONFIG_SOC_AU1000_FREQUENCY option, defaulting to 396 MHz if the option is not given... The patch is based on the AMD's big unpublished patch, the issue seems to be an undocumented errata (or feature :-)... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- arch/mips/au1000/common/cputable.c | 36 +++++++++++++++++------------------ arch/mips/au1000/common/setup.c | 13 ++++++++++--- arch/mips/au1000/common/time.c | 24 +++++++++++++---------- include/asm-mips/mach-au1x00/au1000.h | 1 + 4 files changed, 43 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c index d8df5fdb045f..5c0d35d6e22a 100644 --- a/arch/mips/au1000/common/cputable.c +++ b/arch/mips/au1000/common/cputable.c @@ -22,24 +22,24 @@ struct cpu_spec* cur_cpu_spec[NR_CPUS]; /* With some thought, we can probably use the mask to reduce the * size of the table. */ -struct cpu_spec cpu_specs[] = { - { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 }, - { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 }, - { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 }, - { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 }, - { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 }, - { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 }, - { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 }, - { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 }, - { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 }, - { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 }, - { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 }, - { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, - { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, - { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, - { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 }, - { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0 }, - { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, +struct cpu_spec cpu_specs[] = { + { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 }, + { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 }, + { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 }, + { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 }, + { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 }, + { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 }, + { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 }, + { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 }, + { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 }, + { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 }, + { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 }, + { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 }, + { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 }, + { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 }, + { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 }, + { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 }, + { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } }; void diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index d885e3848ec6..9e4ab80caab6 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -57,7 +57,7 @@ void __init plat_mem_setup(void) { struct cpu_spec *sp; char *argptr; - unsigned long prid, cpupll, bclk = 1; + unsigned long prid, cpufreq, bclk = 1; set_cpuspec(); sp = cur_cpu_spec[0]; @@ -65,8 +65,15 @@ void __init plat_mem_setup(void) board_setup(); /* board specific setup */ prid = read_c0_prid(); - cpupll = (au_readl(0xB1900060) & 0x3F) * 12; - printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll); + if (sp->cpu_pll_wo) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000; +#else + cpufreq = 396; +#endif + else + cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; + printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); bclk = sp->cpu_bclk; if (bclk) diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index f113b512d7b1..e122bbc6cd88 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -209,18 +209,22 @@ unsigned long cal_r4koff(void) while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); au_writel(0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); + } else + no_au1xxx_32khz = 1; - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * - AU1000_SRC_CLK; - } - else { - /* The 32KHz oscillator isn't running, so assume there - * isn't one and grab the processor speed from the PLL. - * NOTE: some old silicon doesn't allow reading the PLL. - */ + /* + * On early Au1000, sys_cpupll was write-only. Since these + * silicon versions of Au1000 are not sold by AMD, we don't bend + * over backwards trying to determine the frequency. + */ + if (cur_cpu_spec[0]->cpu_pll_wo) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; +#else + cpu_speed = 396000000; +#endif + else cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - no_au1xxx_32khz = 1; - } mips_hpt_frequency = cpu_speed; // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index cb18af989645..5bb57bf2b9d7 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1786,6 +1786,7 @@ struct cpu_spec { char *cpu_name; unsigned char cpu_od; /* Set Config[OD] */ unsigned char cpu_bclk; /* Enable BCLK switching */ + unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ }; extern struct cpu_spec cpu_specs[]; -- cgit v1.2.3-59-g8ed1b From 34e6bbf23c8f43e8713d9bd092680f1660494b4a Mon Sep 17 00:00:00 2001 From: Fabio Checconi Date: Wed, 2 Apr 2008 14:31:02 +0200 Subject: cfq-iosched: fix rcu freeing of cfq io contexts SLAB_DESTROY_BY_RCU is not a direct substitute for normal call_rcu() freeing, since it'll page freeing but NOT object freeing. So change cfq to do the freeing on its own. Signed-off-by: Fabio Checconi Acked-by: Paul E. McKenney Signed-off-by: Jens Axboe --- block/cfq-iosched.c | 57 ++++++++++++++++++++++------------------------- include/linux/iocontext.h | 3 +++ 2 files changed, 30 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/block/cfq-iosched.c b/block/cfq-iosched.c index 0f962ecae91f..f26da2bfcc15 100644 --- a/block/cfq-iosched.c +++ b/block/cfq-iosched.c @@ -1143,24 +1143,37 @@ static void cfq_put_queue(struct cfq_queue *cfqq) } /* - * Call func for each cic attached to this ioc. Returns number of cic's seen. + * Call func for each cic attached to this ioc. */ -static unsigned int +static void call_for_each_cic(struct io_context *ioc, void (*func)(struct io_context *, struct cfq_io_context *)) { struct cfq_io_context *cic; struct hlist_node *n; - int called = 0; rcu_read_lock(); - hlist_for_each_entry_rcu(cic, n, &ioc->cic_list, cic_list) { + hlist_for_each_entry_rcu(cic, n, &ioc->cic_list, cic_list) func(ioc, cic); - called++; - } rcu_read_unlock(); +} + +static void cfq_cic_free_rcu(struct rcu_head *head) +{ + struct cfq_io_context *cic; + + cic = container_of(head, struct cfq_io_context, rcu_head); + + kmem_cache_free(cfq_ioc_pool, cic); + elv_ioc_count_dec(ioc_count); + + if (ioc_gone && !elv_ioc_count_read(ioc_count)) + complete(ioc_gone); +} - return called; +static void cfq_cic_free(struct cfq_io_context *cic) +{ + call_rcu(&cic->rcu_head, cfq_cic_free_rcu); } static void cic_free_func(struct io_context *ioc, struct cfq_io_context *cic) @@ -1174,24 +1187,18 @@ static void cic_free_func(struct io_context *ioc, struct cfq_io_context *cic) hlist_del_rcu(&cic->cic_list); spin_unlock_irqrestore(&ioc->lock, flags); - kmem_cache_free(cfq_ioc_pool, cic); + cfq_cic_free(cic); } static void cfq_free_io_context(struct io_context *ioc) { - int freed; - /* - * ioc->refcount is zero here, so no more cic's are allowed to be - * linked into this ioc. So it should be ok to iterate over the known - * list, we will see all cic's since no new ones are added. + * ioc->refcount is zero here, or we are called from elv_unregister(), + * so no more cic's are allowed to be linked into this ioc. So it + * should be ok to iterate over the known list, we will see all cic's + * since no new ones are added. */ - freed = call_for_each_cic(ioc, cic_free_func); - - elv_ioc_count_mod(ioc_count, -freed); - - if (ioc_gone && !elv_ioc_count_read(ioc_count)) - complete(ioc_gone); + call_for_each_cic(ioc, cic_free_func); } static void cfq_exit_cfqq(struct cfq_data *cfqd, struct cfq_queue *cfqq) @@ -1458,15 +1465,6 @@ cfq_get_queue(struct cfq_data *cfqd, int is_sync, struct io_context *ioc, return cfqq; } -static void cfq_cic_free(struct cfq_io_context *cic) -{ - kmem_cache_free(cfq_ioc_pool, cic); - elv_ioc_count_dec(ioc_count); - - if (ioc_gone && !elv_ioc_count_read(ioc_count)) - complete(ioc_gone); -} - /* * We drop cfq io contexts lazily, so we may find a dead one. */ @@ -2138,7 +2136,7 @@ static int __init cfq_slab_setup(void) if (!cfq_pool) goto fail; - cfq_ioc_pool = KMEM_CACHE(cfq_io_context, SLAB_DESTROY_BY_RCU); + cfq_ioc_pool = KMEM_CACHE(cfq_io_context, 0); if (!cfq_ioc_pool) goto fail; @@ -2286,7 +2284,6 @@ static void __exit cfq_exit(void) smp_wmb(); if (elv_ioc_count_read(ioc_count)) wait_for_completion(ioc_gone); - synchronize_rcu(); cfq_slab_kill(); } diff --git a/include/linux/iocontext.h b/include/linux/iocontext.h index 1b4ccf25b4d2..cac4b364cd40 100644 --- a/include/linux/iocontext.h +++ b/include/linux/iocontext.h @@ -2,6 +2,7 @@ #define IOCONTEXT_H #include +#include /* * This is the per-process anticipatory I/O scheduler state. @@ -54,6 +55,8 @@ struct cfq_io_context { void (*dtor)(struct io_context *); /* destructor */ void (*exit)(struct io_context *); /* called on task exit */ + + struct rcu_head rcu_head; }; /* -- cgit v1.2.3-59-g8ed1b From dd135ebbd2a6b5e07dadb66c4dd033bb69531051 Mon Sep 17 00:00:00 2001 From: Christian Borntraeger Date: Wed, 2 Apr 2008 13:04:40 -0700 Subject: kvm: provide kvm.h for all architecture: fixes headers_install MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently include/linux/kvm.h is not considered by make headers_install, because Kbuild cannot handle " unifdef-$(CONFIG_FOO) += foo.h. This problem was introduced by commit fb56dbb31c4738a3918db81fd24da732ce3b4ae6 Author: Avi Kivity Date: Sun Dec 2 10:50:06 2007 +0200 KVM: Export include/linux/kvm.h only if $ARCH actually supports KVM Currently, make headers_check barfs due to , which includes, not existing. Rather than add a zillion s, export kvm. only if the arch actually supports it. Signed-off-by: Avi Kivity which makes this an 2.6.25 regression. One way of solving the issue is to enhance Kbuild, but Avi and David conviced me, that changing headers_install is not the way to go. This patch changes the definition for linux/kvm.h to unifdef-y. If  unifdef-y is used for linux/kvm.h "make headers_check" will fail on all architectures without asm/kvm.h. Therefore, this patch also provides asm/kvm.h on all architectures. Signed-off-by: Christian Borntraeger Acked-by: Avi Kivity Cc: Sam Ravnborg Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-alpha/kvm.h | 6 ++++++ include/asm-arm/kvm.h | 6 ++++++ include/asm-avr32/kvm.h | 6 ++++++ include/asm-blackfin/kvm.h | 6 ++++++ include/asm-cris/kvm.h | 6 ++++++ include/asm-frv/kvm.h | 6 ++++++ include/asm-generic/Kbuild.asm | 2 ++ include/asm-h8300/kvm.h | 6 ++++++ include/asm-ia64/kvm.h | 6 ++++++ include/asm-m32r/kvm.h | 6 ++++++ include/asm-m68k/kvm.h | 6 ++++++ include/asm-m68knommu/kvm.h | 6 ++++++ include/asm-mips/kvm.h | 6 ++++++ include/asm-mn10300/kvm.h | 6 ++++++ include/asm-parisc/kvm.h | 6 ++++++ include/asm-powerpc/kvm.h | 6 ++++++ include/asm-s390/kvm.h | 6 ++++++ include/asm-sh/kvm.h | 6 ++++++ include/asm-sparc/kvm.h | 6 ++++++ include/asm-sparc64/kvm.h | 6 ++++++ include/asm-um/kvm.h | 6 ++++++ include/asm-v850/kvm.h | 6 ++++++ include/asm-xtensa/kvm.h | 6 ++++++ include/linux/Kbuild | 2 +- 24 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 include/asm-alpha/kvm.h create mode 100644 include/asm-arm/kvm.h create mode 100644 include/asm-avr32/kvm.h create mode 100644 include/asm-blackfin/kvm.h create mode 100644 include/asm-cris/kvm.h create mode 100644 include/asm-frv/kvm.h create mode 100644 include/asm-h8300/kvm.h create mode 100644 include/asm-ia64/kvm.h create mode 100644 include/asm-m32r/kvm.h create mode 100644 include/asm-m68k/kvm.h create mode 100644 include/asm-m68knommu/kvm.h create mode 100644 include/asm-mips/kvm.h create mode 100644 include/asm-mn10300/kvm.h create mode 100644 include/asm-parisc/kvm.h create mode 100644 include/asm-powerpc/kvm.h create mode 100644 include/asm-s390/kvm.h create mode 100644 include/asm-sh/kvm.h create mode 100644 include/asm-sparc/kvm.h create mode 100644 include/asm-sparc64/kvm.h create mode 100644 include/asm-um/kvm.h create mode 100644 include/asm-v850/kvm.h create mode 100644 include/asm-xtensa/kvm.h (limited to 'include') diff --git a/include/asm-alpha/kvm.h b/include/asm-alpha/kvm.h new file mode 100644 index 000000000000..b9daec429689 --- /dev/null +++ b/include/asm-alpha/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_ALPHA_H +#define __LINUX_KVM_ALPHA_H + +/* alpha does not support KVM */ + +#endif diff --git a/include/asm-arm/kvm.h b/include/asm-arm/kvm.h new file mode 100644 index 000000000000..cb3c08cbcb9e --- /dev/null +++ b/include/asm-arm/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_ARM_H +#define __LINUX_KVM_ARM_H + +/* arm does not support KVM */ + +#endif diff --git a/include/asm-avr32/kvm.h b/include/asm-avr32/kvm.h new file mode 100644 index 000000000000..8c5777020e2c --- /dev/null +++ b/include/asm-avr32/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_AVR32_H +#define __LINUX_KVM_AVR32_H + +/* avr32 does not support KVM */ + +#endif diff --git a/include/asm-blackfin/kvm.h b/include/asm-blackfin/kvm.h new file mode 100644 index 000000000000..e3477d77c014 --- /dev/null +++ b/include/asm-blackfin/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_BLACKFIN_H +#define __LINUX_KVM_BLACKFIN_H + +/* blackfin does not support KVM */ + +#endif diff --git a/include/asm-cris/kvm.h b/include/asm-cris/kvm.h new file mode 100644 index 000000000000..c860f51149f0 --- /dev/null +++ b/include/asm-cris/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_CRIS_H +#define __LINUX_KVM_CRIS_H + +/* cris does not support KVM */ + +#endif diff --git a/include/asm-frv/kvm.h b/include/asm-frv/kvm.h new file mode 100644 index 000000000000..9c8a4f08d0a9 --- /dev/null +++ b/include/asm-frv/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_FRV_H +#define __LINUX_KVM_FRV_H + +/* frv does not support KVM */ + +#endif diff --git a/include/asm-generic/Kbuild.asm b/include/asm-generic/Kbuild.asm index fd9dcfd91c39..92a6d91d0c1a 100644 --- a/include/asm-generic/Kbuild.asm +++ b/include/asm-generic/Kbuild.asm @@ -1,3 +1,5 @@ +header-y += kvm.h + ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h) unifdef-y += a.out.h endif diff --git a/include/asm-h8300/kvm.h b/include/asm-h8300/kvm.h new file mode 100644 index 000000000000..bdbed7b987e1 --- /dev/null +++ b/include/asm-h8300/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_H8300_H +#define __LINUX_KVM_H8300_H + +/* h8300 does not support KVM */ + +#endif diff --git a/include/asm-ia64/kvm.h b/include/asm-ia64/kvm.h new file mode 100644 index 000000000000..030d29b4b26b --- /dev/null +++ b/include/asm-ia64/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_IA64_H +#define __LINUX_KVM_IA64_H + +/* ia64 does not support KVM */ + +#endif diff --git a/include/asm-m32r/kvm.h b/include/asm-m32r/kvm.h new file mode 100644 index 000000000000..99a40515b77e --- /dev/null +++ b/include/asm-m32r/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_M32R_H +#define __LINUX_KVM_M32R_H + +/* m32r does not support KVM */ + +#endif diff --git a/include/asm-m68k/kvm.h b/include/asm-m68k/kvm.h new file mode 100644 index 000000000000..7ed27fce5240 --- /dev/null +++ b/include/asm-m68k/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_M68K_H +#define __LINUX_KVM_M68K_H + +/* m68k does not support KVM */ + +#endif diff --git a/include/asm-m68knommu/kvm.h b/include/asm-m68knommu/kvm.h new file mode 100644 index 000000000000..b49d4258dabb --- /dev/null +++ b/include/asm-m68knommu/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_M68KNOMMU_H +#define __LINUX_KVM_M68KNOMMU_H + +/* m68knommu does not support KVM */ + +#endif diff --git a/include/asm-mips/kvm.h b/include/asm-mips/kvm.h new file mode 100644 index 000000000000..093a5b7f796b --- /dev/null +++ b/include/asm-mips/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_MIPS_H +#define __LINUX_KVM_MIPS_H + +/* mips does not support KVM */ + +#endif diff --git a/include/asm-mn10300/kvm.h b/include/asm-mn10300/kvm.h new file mode 100644 index 000000000000..f6b609ff4a57 --- /dev/null +++ b/include/asm-mn10300/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_MN10300_H +#define __LINUX_KVM_MN10300_H + +/* mn10300 does not support KVM */ + +#endif diff --git a/include/asm-parisc/kvm.h b/include/asm-parisc/kvm.h new file mode 100644 index 000000000000..00cc45812547 --- /dev/null +++ b/include/asm-parisc/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_PARISC_H +#define __LINUX_KVM_PARISC_H + +/* parisc does not support KVM */ + +#endif diff --git a/include/asm-powerpc/kvm.h b/include/asm-powerpc/kvm.h new file mode 100644 index 000000000000..d1b530fbf8dd --- /dev/null +++ b/include/asm-powerpc/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_POWERPC_H +#define __LINUX_KVM_POWERPC_H + +/* powerpc does not support KVM */ + +#endif diff --git a/include/asm-s390/kvm.h b/include/asm-s390/kvm.h new file mode 100644 index 000000000000..573f2a351386 --- /dev/null +++ b/include/asm-s390/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_S390_H +#define __LINUX_KVM_S390_H + +/* s390 does not support KVM */ + +#endif diff --git a/include/asm-sh/kvm.h b/include/asm-sh/kvm.h new file mode 100644 index 000000000000..6af51dbab2d0 --- /dev/null +++ b/include/asm-sh/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_SH_H +#define __LINUX_KVM_SH_H + +/* sh does not support KVM */ + +#endif diff --git a/include/asm-sparc/kvm.h b/include/asm-sparc/kvm.h new file mode 100644 index 000000000000..2e5478da3819 --- /dev/null +++ b/include/asm-sparc/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_SPARC_H +#define __LINUX_KVM_SPARC_H + +/* sparc does not support KVM */ + +#endif diff --git a/include/asm-sparc64/kvm.h b/include/asm-sparc64/kvm.h new file mode 100644 index 000000000000..380537a77bf9 --- /dev/null +++ b/include/asm-sparc64/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_SPARC64_H +#define __LINUX_KVM_SPARC64_H + +/* sparc64 does not support KVM */ + +#endif diff --git a/include/asm-um/kvm.h b/include/asm-um/kvm.h new file mode 100644 index 000000000000..66aa77094551 --- /dev/null +++ b/include/asm-um/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_UM_H +#define __LINUX_KVM_UM_H + +/* um does not support KVM */ + +#endif diff --git a/include/asm-v850/kvm.h b/include/asm-v850/kvm.h new file mode 100644 index 000000000000..3f729b79febc --- /dev/null +++ b/include/asm-v850/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_V850_H +#define __LINUX_KVM_V850_H + +/* v850 does not support KVM */ + +#endif diff --git a/include/asm-xtensa/kvm.h b/include/asm-xtensa/kvm.h new file mode 100644 index 000000000000..bda4e331e98c --- /dev/null +++ b/include/asm-xtensa/kvm.h @@ -0,0 +1,6 @@ +#ifndef __LINUX_KVM_XTENSA_H +#define __LINUX_KVM_XTENSA_H + +/* xtensa does not support KVM */ + +#endif diff --git a/include/linux/Kbuild b/include/linux/Kbuild index 4a446a19295e..9cdd12a9e843 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -253,7 +253,7 @@ unifdef-y += kd.h unifdef-y += kernelcapi.h unifdef-y += kernel.h unifdef-y += keyboard.h -unifdef-$(CONFIG_HAVE_KVM) += kvm.h +unifdef-y += kvm.h unifdef-y += llc.h unifdef-y += loop.h unifdef-y += lp.h -- cgit v1.2.3-59-g8ed1b From c143d43aa3149b83e4b40624a27aa2b18638afec Mon Sep 17 00:00:00 2001 From: Ivan Kokshaysky Date: Wed, 2 Apr 2008 13:04:43 -0700 Subject: alpha: fix ALSA DMA mmap crash Make dma_alloc_coherent respect gfp flags (__GFP_COMP is one that matters). Signed-off-by: Ivan Kokshaysky Tested-by: Michael Cree Cc: Richard Henderson Cc: Jaroslav Kysela Cc: Takashi Iwai Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/kernel/pci_iommu.c | 8 +++++--- include/asm-alpha/dma-mapping.h | 2 +- include/asm-alpha/pci.h | 8 +++++++- 3 files changed, 13 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c index 4e1c08636edd..dd6e334ab9e1 100644 --- a/arch/alpha/kernel/pci_iommu.c +++ b/arch/alpha/kernel/pci_iommu.c @@ -424,11 +424,13 @@ EXPORT_SYMBOL(pci_unmap_page); else DMA_ADDRP is undefined. */ void * -pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp) +__pci_alloc_consistent(struct pci_dev *pdev, size_t size, + dma_addr_t *dma_addrp, gfp_t gfp) { void *cpu_addr; long order = get_order(size); - gfp_t gfp = GFP_ATOMIC; + + gfp &= ~GFP_DMA; try_again: cpu_addr = (void *)__get_free_pages(gfp, order); @@ -458,7 +460,7 @@ try_again: return cpu_addr; } -EXPORT_SYMBOL(pci_alloc_consistent); +EXPORT_SYMBOL(__pci_alloc_consistent); /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must be values that were returned from pci_alloc_consistent. SIZE must diff --git a/include/asm-alpha/dma-mapping.h b/include/asm-alpha/dma-mapping.h index 75a1aff5b57b..db351d1296f4 100644 --- a/include/asm-alpha/dma-mapping.h +++ b/include/asm-alpha/dma-mapping.h @@ -11,7 +11,7 @@ #define dma_unmap_single(dev, addr, size, dir) \ pci_unmap_single(alpha_gendev_to_pci(dev), addr, size, dir) #define dma_alloc_coherent(dev, size, addr, gfp) \ - pci_alloc_consistent(alpha_gendev_to_pci(dev), size, addr) + __pci_alloc_consistent(alpha_gendev_to_pci(dev), size, addr, gfp) #define dma_free_coherent(dev, size, va, addr) \ pci_free_consistent(alpha_gendev_to_pci(dev), size, va, addr) #define dma_map_page(dev, page, off, size, dir) \ diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h index d5b10ef64364..d31fd49ff79a 100644 --- a/include/asm-alpha/pci.h +++ b/include/asm-alpha/pci.h @@ -76,7 +76,13 @@ extern inline void pcibios_penalize_isa_irq(int irq, int active) successful and sets *DMA_ADDRP to the pci side dma address as well, else DMA_ADDRP is undefined. */ -extern void *pci_alloc_consistent(struct pci_dev *, size_t, dma_addr_t *); +extern void *__pci_alloc_consistent(struct pci_dev *, size_t, + dma_addr_t *, gfp_t); +static inline void * +pci_alloc_consistent(struct pci_dev *dev, size_t size, dma_addr_t *dma) +{ + return __pci_alloc_consistent(dev, size, dma, GFP_ATOMIC); +} /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must be values that were returned from pci_alloc_consistent. SIZE must -- cgit v1.2.3-59-g8ed1b From 06f11f37aa84e83b48cdf36037c4414f5a83c13f Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Wed, 2 Apr 2008 13:04:52 -0700 Subject: alpha: get_current(): don't add zero to current_thread_info()->task A nasty compile error: In file included from security/keys/internal.h:16, from security/keys/sysctl.c:14: include/linux/key-ui.h: In function 'key_permission': include/linux/key-ui.h:51: error: invalid use of undefined type 'struct task_struct' apparently the compiler has decided that it needs to know sizeof(task_struct) so that it can add zero to a task_struct* (which is rather dumb of it). Getting task_struct in scope in these deeply-nested headers is scary-looking, so let's just remove the "+ 0". Cc: David Howells Cc: Richard Henderson Cc: Ivan Kokshaysky Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-alpha/current.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-alpha/current.h b/include/asm-alpha/current.h index 8d88a13c1bec..094d285a1b34 100644 --- a/include/asm-alpha/current.h +++ b/include/asm-alpha/current.h @@ -3,7 +3,7 @@ #include -#define get_current() (current_thread_info()->task + 0) +#define get_current() (current_thread_info()->task) #define current get_current() #endif /* _ALPHA_CURRENT_H */ -- cgit v1.2.3-59-g8ed1b From 436d34b36202ef724778ded1e9cb10f8c37b32bc Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Wed, 2 Apr 2008 17:28:46 +0900 Subject: libata: uninline atapi_cmd_type() Uninline atapi_cmd_type(). It doesn't really have to be inline and more case will be added which need to access unexported libata variable. Signed-off-by: Tejun Heo Signed-off-by: Jeff Garzik --- drivers/ata/libata-core.c | 34 ++++++++++++++++++++++++++++++++++ include/linux/libata.h | 22 +--------------------- 2 files changed, 35 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 2db5c9c9ca10..e9b69ba489d2 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -325,6 +325,39 @@ static void ata_force_horkage(struct ata_device *dev) } } +/** + * atapi_cmd_type - Determine ATAPI command type from SCSI opcode + * @opcode: SCSI opcode + * + * Determine ATAPI command type from @opcode. + * + * LOCKING: + * None. + * + * RETURNS: + * ATAPI_{READ|WRITE|READ_CD|PASS_THRU|MISC} + */ +int atapi_cmd_type(u8 opcode) +{ + switch (opcode) { + case GPCMD_READ_10: + case GPCMD_READ_12: + return ATAPI_READ; + + case GPCMD_WRITE_10: + case GPCMD_WRITE_12: + case GPCMD_WRITE_AND_VERIFY_10: + return ATAPI_WRITE; + + case GPCMD_READ_CD: + case GPCMD_READ_CD_MSF: + return ATAPI_READ_CD; + + default: + return ATAPI_MISC; + } +} + /** * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure * @tf: Taskfile to convert @@ -7774,6 +7807,7 @@ EXPORT_SYMBOL_GPL(ata_tf_read); EXPORT_SYMBOL_GPL(ata_noop_dev_select); EXPORT_SYMBOL_GPL(ata_std_dev_select); EXPORT_SYMBOL_GPL(sata_print_link_status); +EXPORT_SYMBOL_GPL(atapi_cmd_type); EXPORT_SYMBOL_GPL(ata_tf_to_fis); EXPORT_SYMBOL_GPL(ata_tf_from_fis); EXPORT_SYMBOL_GPL(ata_pack_xfermask); diff --git a/include/linux/libata.h b/include/linux/libata.h index b064bfeb69ee..92c64909ed25 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -849,6 +849,7 @@ extern unsigned int ata_dev_try_classify(struct ata_device *dev, int present, */ extern void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); extern void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf); +extern int atapi_cmd_type(u8 opcode); extern void ata_tf_to_fis(const struct ata_taskfile *tf, u8 pmp, int is_cmd, u8 *fis); extern void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf); @@ -1379,27 +1380,6 @@ static inline int ata_try_flush_cache(const struct ata_device *dev) ata_id_has_flush_ext(dev->id); } -static inline int atapi_cmd_type(u8 opcode) -{ - switch (opcode) { - case GPCMD_READ_10: - case GPCMD_READ_12: - return ATAPI_READ; - - case GPCMD_WRITE_10: - case GPCMD_WRITE_12: - case GPCMD_WRITE_AND_VERIFY_10: - return ATAPI_WRITE; - - case GPCMD_READ_CD: - case GPCMD_READ_CD_MSF: - return ATAPI_READ_CD; - - default: - return ATAPI_MISC; - } -} - static inline unsigned int ac_err_mask(u8 status) { if (status & (ATA_BUSY | ATA_DRQ)) -- cgit v1.2.3-59-g8ed1b From e52dcc4899cf1b7601379c31542bd91cd2997a64 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Wed, 2 Apr 2008 17:35:19 +0900 Subject: libata: ATA_12/16 doesn't fall into ATAPI_MISC SAT passthrus don't really fit into ATAPI_MISC class. SAT passthru commands always transfer multiple of 512 bytes and variable length response is not allowed. This patch creates a separate category - ATAPI_PASS_THRU - for these. This fixes HSM violation on "hdparm -I". Signed-off-by: Tejun Heo Signed-off-by: Jeff Garzik --- drivers/ata/libata-core.c | 5 +++++ include/linux/libata.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index e9b69ba489d2..be95fdb69726 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -353,6 +353,11 @@ int atapi_cmd_type(u8 opcode) case GPCMD_READ_CD_MSF: return ATAPI_READ_CD; + case ATA_16: + case ATA_12: + if (atapi_passthru16) + return ATAPI_PASS_THRU; + /* fall thru */ default: return ATAPI_MISC; } diff --git a/include/linux/libata.h b/include/linux/libata.h index 92c64909ed25..37ee881c42ac 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -350,7 +350,8 @@ enum { ATAPI_READ = 0, /* READs */ ATAPI_WRITE = 1, /* WRITEs */ ATAPI_READ_CD = 2, /* READ CD [MSF] */ - ATAPI_MISC = 3, /* the rest */ + ATAPI_PASS_THRU = 3, /* SAT pass-thru */ + ATAPI_MISC = 4, /* the rest */ }; enum ata_xfer_mask { -- cgit v1.2.3-59-g8ed1b From bae1d2507e44417455eda76d4435352fee14cf51 Mon Sep 17 00:00:00 2001 From: Ravikiran G Thirumalai Date: Fri, 4 Apr 2008 03:06:29 -0700 Subject: x86: fix breakage of vSMP irq operations 25-rc* stopped working with CONFIG_X86_VSMP on vSMP machines. Looks like the vsmp irq ops got accidentally removed during merge of x86_64 pvops in 2.6.25. -- commit 6abcd98ffafbff81f0bfd7ee1d129e634af13245 removed vsmp irq ops. Tested with both CONFIG_X86_VSMP and without CONFIG_X86_VSMP, on vSMP and non vSMP x86_64 machines. Please apply. Signed-off-by: Ravikiran Thirumalai Signed-off-by: Ingo Molnar --- include/asm-x86/irqflags.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'include') diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h index 92021c1ffa3a..0e2292483b35 100644 --- a/include/asm-x86/irqflags.h +++ b/include/asm-x86/irqflags.h @@ -70,6 +70,26 @@ static inline void raw_local_irq_restore(unsigned long flags) native_restore_fl(flags); } +#ifdef CONFIG_X86_VSMP + +/* + * Interrupt control for the VSMP architecture: + */ + +static inline void raw_local_irq_disable(void) +{ + unsigned long flags = __raw_local_save_flags(); + raw_local_irq_restore((flags & ~X86_EFLAGS_IF) | X86_EFLAGS_AC); +} + +static inline void raw_local_irq_enable(void) +{ + unsigned long flags = __raw_local_save_flags(); + raw_local_irq_restore((flags | X86_EFLAGS_IF) & (~X86_EFLAGS_AC)); +} + +#else + static inline void raw_local_irq_disable(void) { native_irq_disable(); @@ -80,6 +100,8 @@ static inline void raw_local_irq_enable(void) native_irq_enable(); } +#endif + /* * Used in the idle loop; sti takes one instruction cycle * to complete: @@ -137,10 +159,17 @@ static inline unsigned long __raw_local_irq_save(void) #define raw_local_irq_save(flags) \ do { (flags) = __raw_local_irq_save(); } while (0) +#ifdef CONFIG_X86_VSMP +static inline int raw_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & X86_EFLAGS_IF) || (flags & X86_EFLAGS_AC); +} +#else static inline int raw_irqs_disabled_flags(unsigned long flags) { return !(flags & X86_EFLAGS_IF); } +#endif static inline int raw_irqs_disabled(void) { -- cgit v1.2.3-59-g8ed1b From 5761d64b277c287a7520b868c32d656ef03374b4 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Fri, 4 Apr 2008 16:26:10 +0200 Subject: x86: revert assign IRQs to hpet timer The commits: commit 37a47db8d7f0f38dac5acf5a13abbc8f401707fa Author: Balaji Rao Date: Wed Jan 30 13:30:03 2008 +0100 x86: assign IRQs to HPET timers, fix and commit e3f37a54f690d3e64995ea7ecea08c5ab3070faf Author: Balaji Rao Date: Wed Jan 30 13:30:03 2008 +0100 x86: assign IRQs to HPET timers have been identified to cause a regression on some platforms due to the assignement of legacy IRQs which makes the legacy devices connected to those IRQs disfunctional. Revert them. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=10382 Signed-off-by: Thomas Gleixner Signed-off-by: Ingo Molnar --- arch/x86/kernel/hpet.c | 9 ++++++--- drivers/char/hpet.c | 51 +++++++------------------------------------------- include/linux/hpet.h | 2 +- 3 files changed, 14 insertions(+), 48 deletions(-) (limited to 'include') diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 235fd6c77504..36652ea1a265 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -133,13 +133,16 @@ static void hpet_reserve_platform_timers(unsigned long id) #ifdef CONFIG_HPET_EMULATE_RTC hpet_reserve_timer(&hd, 1); #endif + hd.hd_irq[0] = HPET_LEGACY_8254; hd.hd_irq[1] = HPET_LEGACY_RTC; - for (i = 2; i < nrtimers; timer++, i++) - hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> - Tn_INT_ROUTE_CNF_SHIFT; + for (i = 2; i < nrtimers; timer++, i++) + hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> + Tn_INT_ROUTE_CNF_SHIFT; + hpet_alloc(&hd); + } #else static void hpet_reserve_platform_timers(unsigned long id) { } diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c index 465ad35ed38f..1399971be689 100644 --- a/drivers/char/hpet.c +++ b/drivers/char/hpet.c @@ -731,14 +731,14 @@ static unsigned long hpet_calibrate(struct hpets *hpetp) int hpet_alloc(struct hpet_data *hdp) { - u64 cap, mcfg, hpet_config; + u64 cap, mcfg; struct hpet_dev *devp; - u32 i, ntimer, irq; + u32 i, ntimer; struct hpets *hpetp; size_t siz; struct hpet __iomem *hpet; static struct hpets *last = NULL; - unsigned long period, irq_bitmap; + unsigned long period; unsigned long long temp; /* @@ -765,47 +765,11 @@ int hpet_alloc(struct hpet_data *hdp) hpetp->hp_hpet_phys = hdp->hd_phys_address; hpetp->hp_ntimer = hdp->hd_nirqs; - hpet = hpetp->hp_hpet; - - /* Assign IRQs statically for legacy devices */ - hpetp->hp_dev[0].hd_hdwirq = hdp->hd_irq[0]; - hpetp->hp_dev[1].hd_hdwirq = hdp->hd_irq[1]; - - /* Assign IRQs dynamically for the others */ - for (i = 2, devp = &hpetp->hp_dev[2]; i < hdp->hd_nirqs; i++, devp++) { - struct hpet_timer __iomem *timer; - timer = &hpet->hpet_timers[devp - hpetp->hp_dev]; + for (i = 0; i < hdp->hd_nirqs; i++) + hpetp->hp_dev[i].hd_hdwirq = hdp->hd_irq[i]; - /* Check if there's already an IRQ assigned to the timer */ - if (hdp->hd_irq[i]) { - hpetp->hp_dev[i].hd_hdwirq = hdp->hd_irq[i]; - continue; - } - - hpet_config = readq(&timer->hpet_config); - irq_bitmap = (hpet_config & Tn_INT_ROUTE_CAP_MASK) - >> Tn_INT_ROUTE_CAP_SHIFT; - if (!irq_bitmap) - irq = 0; /* No valid IRQ Assignable */ - else { - irq = find_first_bit(&irq_bitmap, 32); - do { - hpet_config |= irq << Tn_INT_ROUTE_CNF_SHIFT; - writeq(hpet_config, &timer->hpet_config); - - /* - * Verify whether we have written a valid - * IRQ number by reading it back again - */ - hpet_config = readq(&timer->hpet_config); - if (irq == (hpet_config & Tn_INT_ROUTE_CNF_MASK) - >> Tn_INT_ROUTE_CNF_SHIFT) - break; /* Success */ - } while ((irq = (find_next_bit(&irq_bitmap, 32, irq)))); - } - hpetp->hp_dev[i].hd_hdwirq = irq; - } + hpet = hpetp->hp_hpet; cap = readq(&hpet->hpet_cap); @@ -836,8 +800,7 @@ int hpet_alloc(struct hpet_data *hdp) hpetp->hp_which, hdp->hd_phys_address, hpetp->hp_ntimer > 1 ? "s" : ""); for (i = 0; i < hpetp->hp_ntimer; i++) - printk("%s %d", i > 0 ? "," : "", - hpetp->hp_dev[i].hd_hdwirq); + printk("%s %d", i > 0 ? "," : "", hdp->hd_irq[i]); printk("\n"); printk(KERN_INFO "hpet%u: %u %d-bit timers, %Lu Hz\n", diff --git a/include/linux/hpet.h b/include/linux/hpet.h index 9cd94bfd07e5..2dc29ce6c8e4 100644 --- a/include/linux/hpet.h +++ b/include/linux/hpet.h @@ -64,7 +64,7 @@ struct hpet { */ #define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL) -#define Tn_INT_ROUTE_CAP_SHIFT (32UL) +#define Tn_INI_ROUTE_CAP_SHIFT (32UL) #define Tn_FSB_INT_DELCAP_MASK (0x8000UL) #define Tn_FSB_INT_DELCAP_SHIFT (15) #define Tn_FSB_EN_CNF_MASK (0x4000UL) -- cgit v1.2.3-59-g8ed1b From 865ab8753837b73fe1e800fc88462c5914eec549 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 2 Apr 2008 23:53:19 +0400 Subject: [MIPS] Pb1200: Fix header breakage Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-pb1x00/pb1200.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h index ed5fd7390678..72213e3d02c7 100644 --- a/include/asm-mips/mach-pb1x00/pb1200.h +++ b/include/asm-mips/mach-pb1x00/pb1200.h @@ -245,7 +245,7 @@ enum external_pb1200_ints { PB1200_SD1_INSERT_INT, PB1200_SD1_EJECT_INT, - PB1200_INT_END (PB1200_INT_BEGIN + 15) + PB1200_INT_END = PB1200_INT_BEGIN + 15 }; /* For drivers/pcmcia/au1000_db1x00.c */ -- cgit v1.2.3-59-g8ed1b From 8bab8dded67d026c39367bbd5e27d2f6c556c38e Mon Sep 17 00:00:00 2001 From: Paul Menage Date: Fri, 4 Apr 2008 14:29:57 -0700 Subject: cgroups: add cgroup support for enabling controllers at boot time The effects of cgroup_disable=foo are: - foo isn't auto-mounted if you mount all cgroups in a single hierarchy - foo isn't visible as an individually mountable subsystem As a result there will only ever be one call to foo->create(), at init time; all processes will stay in this group, and the group will never be mounted on a visible hierarchy. Any additional effects (e.g. not allocating metadata) are up to the foo subsystem. This doesn't handle early_init subsystems (their "disabled" bit isn't set be, but it could easily be extended to do so if any of the early_init systems wanted it - I think it would just involve some nastier parameter processing since it would occur before the command-line argument parser had been run. Hugh said: Ballpark figures, I'm trying to get this question out rather than processing the exact numbers: CONFIG_CGROUP_MEM_RES_CTLR adds 15% overhead to the affected paths, booting with cgroup_disable=memory cuts that back to 1% overhead (due to slightly bigger struct page). I'm no expert on distros, they may have no interest whatever in CONFIG_CGROUP_MEM_RES_CTLR=y; and the rest of us can easily build with or without it, or apply the cgroup_disable=memory patches. Unix bench's execl test result on x86_64 was == just after boot without mounting any cgroup fs.== mem_cgorup=off : Execl Throughput 43.0 3150.1 732.6 mem_cgroup=on : Execl Throughput 43.0 2932.6 682.0 == [lizf@cn.fujitsu.com: fix boot option parsing] Signed-off-by: Balbir Singh Cc: Paul Menage Cc: Balbir Singh Cc: Pavel Emelyanov Cc: KAMEZAWA Hiroyuki Cc: Hugh Dickins Cc: Sudhir Kumar Cc: YAMAMOTO Takashi Cc: David Rientjes Signed-off-by: Li Zefan Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/kernel-parameters.txt | 4 ++++ include/linux/cgroup.h | 1 + kernel/cgroup.c | 42 ++++++++++++++++++++++++++++++++----- 3 files changed, 42 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 4cd1a5da80a4..32e9297ef747 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -375,6 +375,10 @@ and is between 256 and 4096 characters. It is defined in the file ccw_timeout_log [S390] See Documentation/s390/CommonIO for details. + cgroup_disable= [KNL] Disable a particular controller + Format: {name of the controller(s) to disable} + {Currently supported controllers - "memory"} + checkreqprot [SELINUX] Set initial checkreqprot flag value. Format: { "0" | "1" } See security/selinux/Kconfig help text. diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h index 028ba3b523b1..a6a6035a4e1e 100644 --- a/include/linux/cgroup.h +++ b/include/linux/cgroup.h @@ -256,6 +256,7 @@ struct cgroup_subsys { void (*bind)(struct cgroup_subsys *ss, struct cgroup *root); int subsys_id; int active; + int disabled; int early_init; #define MAX_CGROUP_TYPE_NAMELEN 32 const char *name; diff --git a/kernel/cgroup.c b/kernel/cgroup.c index 53d86b4b0ce0..62f1a5231fe9 100644 --- a/kernel/cgroup.c +++ b/kernel/cgroup.c @@ -782,7 +782,14 @@ static int parse_cgroupfs_options(char *data, if (!*token) return -EINVAL; if (!strcmp(token, "all")) { - opts->subsys_bits = (1 << CGROUP_SUBSYS_COUNT) - 1; + /* Add all non-disabled subsystems */ + int i; + opts->subsys_bits = 0; + for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) { + struct cgroup_subsys *ss = subsys[i]; + if (!ss->disabled) + opts->subsys_bits |= 1ul << i; + } } else if (!strcmp(token, "noprefix")) { set_bit(ROOT_NOPREFIX, &opts->flags); } else if (!strncmp(token, "release_agent=", 14)) { @@ -800,7 +807,8 @@ static int parse_cgroupfs_options(char *data, for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) { ss = subsys[i]; if (!strcmp(token, ss->name)) { - set_bit(i, &opts->subsys_bits); + if (!ss->disabled) + set_bit(i, &opts->subsys_bits); break; } } @@ -2600,13 +2608,13 @@ static int proc_cgroupstats_show(struct seq_file *m, void *v) { int i; - seq_puts(m, "#subsys_name\thierarchy\tnum_cgroups\n"); + seq_puts(m, "#subsys_name\thierarchy\tnum_cgroups\tenabled\n"); mutex_lock(&cgroup_mutex); for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) { struct cgroup_subsys *ss = subsys[i]; - seq_printf(m, "%s\t%lu\t%d\n", + seq_printf(m, "%s\t%lu\t%d\t%d\n", ss->name, ss->root->subsys_bits, - ss->root->number_of_cgroups); + ss->root->number_of_cgroups, !ss->disabled); } mutex_unlock(&cgroup_mutex); return 0; @@ -3010,3 +3018,27 @@ static void cgroup_release_agent(struct work_struct *work) spin_unlock(&release_list_lock); mutex_unlock(&cgroup_mutex); } + +static int __init cgroup_disable(char *str) +{ + int i; + char *token; + + while ((token = strsep(&str, ",")) != NULL) { + if (!*token) + continue; + + for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) { + struct cgroup_subsys *ss = subsys[i]; + + if (!strcmp(token, ss->name)) { + ss->disabled = 1; + printk(KERN_INFO "Disabling %s control group" + " subsystem\n", ss->name); + break; + } + } + } + return 1; +} +__setup("cgroup_disable=", cgroup_disable); -- cgit v1.2.3-59-g8ed1b From 871de939030c903fd5ed50a7c4c88e02998e1cbc Mon Sep 17 00:00:00 2001 From: Suresh Siddha Date: Mon, 7 Apr 2008 11:56:34 -0700 Subject: x86: fix 64-bit asm NOPS for CONFIG_GENERIC_CPU ASM_NOP's for 64-bit kernel with CONFIG_GENERIC_CPU is broken with the recent x86 nops merge. They were using GENERIC_NOPS which will truncate the upper 32bits of %rsi, because of the missing 64bit rex prefix. For now, fall back ASM NOPS for generic cpu to K8 NOPS, similar to the code before the wrong x86 nop merge. This should resolve the crash seen by Ingo on a test-system: BUG: unable to handle kernel paging request at 00000000d80d8ee8 IP: [] save_i387_ia32+0x61/0xd8 PGD b8e0067 PUD 51490067 PMD 0 Oops: 0000 [1] SMP CPU 2 Modules linked in: Pid: 3871, comm: distcc Not tainted 2.6.25-rc7-sched-devel.git-x86-latest.git #359 RIP: 0010:[] [] save_i387_ia32+0x61/0xd8 RSP: 0000:ffff81003abd3cb8 EFLAGS: 00010246 RAX: ffff810082e93400 RBX: 00000000ffc37f84 RCX: ffff8100d80d8ee0 RDX: 0000000000000000 RSI: 00000000d80d8ee0 RDI: ffff810082e93400 RBP: 00000000ffc37fdc R08: 00000000ffc37f88 R09: 0000000000000008 R10: ffff81003abd2000 R11: 0000000000000000 R12: ffff810082e93400 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 FS: 0000000000000000(0000) GS:ffff81011fb12dc0(0063) knlGS:00000000f7f1a6c0 CS: 0010 DS: 002b ES: 002b CR0: 0000000080050033 CR2: 00000000d80d8ee8 CR3: 0000000076922000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process distcc (pid: 3871, threadinfo ffff81003abd2000, task ffff8100d80d8ee0) Stack: ffff8100bb670380 ffffffff8026de50 0000000000000118 0000000000000002 0000000000000002 ffff81003abd3e68 ffff81003abd3ed8 ffff81003abd3de8 ffff81003abd3d18 ffffffff80229785 ffff8100d80d8ee0 ffff810001041280 Call Trace: [] ? __generic_file_aio_write_nolock+0x343/0x377 [] ? update_curr+0x54/0x64 [] ? ia32_setup_sigcontext+0x125/0x1d2 [] ? ia32_setup_frame+0x73/0x1a5 [] ? do_notify_resume+0x1aa/0x7db [] ? getnstimeofday+0x31/0x85 [] ? ktime_get_ts+0x17/0x48 [] ? ktime_get+0xc/0x41 [] ? hrtimer_nanosleep+0x75/0xd5 [] ? hrtimer_wakeup+0x0/0x21 [] ? int_signal+0x12/0x17 [] ? dummy_file_free_security+0x0/0x1 Code: a6 08 05 00 00 f6 40 14 01 74 34 4c 89 e7 48 0f ae 07 48 8b 86 08 05 00 00 80 78 02 00 79 02 db e2 90 8d b4 26 00 00 00 00 89 f6 <48> 8b 46 08 83 60 14 fe 0f 20 c0 48 83 c8 08 0f 22 c0 eb 07 c6 Signed-off-by: Suresh Siddha Signed-off-by: Ingo Molnar --- include/asm-x86/nops.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/asm-x86/nops.h b/include/asm-x86/nops.h index e3b2bce0aff8..b3930ae539b3 100644 --- a/include/asm-x86/nops.h +++ b/include/asm-x86/nops.h @@ -73,16 +73,7 @@ #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n" #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n" -#if defined(CONFIG_MK8) -#define ASM_NOP1 K8_NOP1 -#define ASM_NOP2 K8_NOP2 -#define ASM_NOP3 K8_NOP3 -#define ASM_NOP4 K8_NOP4 -#define ASM_NOP5 K8_NOP5 -#define ASM_NOP6 K8_NOP6 -#define ASM_NOP7 K8_NOP7 -#define ASM_NOP8 K8_NOP8 -#elif defined(CONFIG_MK7) +#if defined(CONFIG_MK7) #define ASM_NOP1 K7_NOP1 #define ASM_NOP2 K7_NOP2 #define ASM_NOP3 K7_NOP3 @@ -100,6 +91,15 @@ #define ASM_NOP6 P6_NOP6 #define ASM_NOP7 P6_NOP7 #define ASM_NOP8 P6_NOP8 +#elif defined(CONFIG_X86_64) +#define ASM_NOP1 K8_NOP1 +#define ASM_NOP2 K8_NOP2 +#define ASM_NOP3 K8_NOP3 +#define ASM_NOP4 K8_NOP4 +#define ASM_NOP5 K8_NOP5 +#define ASM_NOP6 K8_NOP6 +#define ASM_NOP7 K8_NOP7 +#define ASM_NOP8 K8_NOP8 #else #define ASM_NOP1 GENERIC_NOP1 #define ASM_NOP2 GENERIC_NOP2 -- cgit v1.2.3-59-g8ed1b From 2557a933b795c1988c721ebb871cd735128bb9cb Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Mon, 7 Apr 2008 14:30:28 +1000 Subject: virtio: remove overzealous BUG_ON. The 'disable_cb' callback is designed as an optimization to tell the host we don't need callbacks now. As it is not reliable, the debug check is overzealous: it can happen on two CPUs at the same time. Document this. Even if it were reliable, the virtio_net driver doesn't disable callbacks on transmit so the START_USE/END_USE debugging reentrance protection can be easily tripped even on UP. Thanks to Balaji Rao for the bug report and testing. Signed-off-by: Rusty Russell CC: Balaji Rao Signed-off-by: Linus Torvalds --- drivers/virtio/virtio_ring.c | 3 --- include/linux/virtio.h | 5 ++++- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index aa714028641e..c2fa5c630813 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -214,10 +214,7 @@ static void vring_disable_cb(struct virtqueue *_vq) { struct vring_virtqueue *vq = to_vvq(_vq); - START_USE(vq); - BUG_ON(vq->vring.avail->flags & VRING_AVAIL_F_NO_INTERRUPT); vq->vring.avail->flags |= VRING_AVAIL_F_NO_INTERRUPT; - END_USE(vq); } static bool vring_enable_cb(struct virtqueue *_vq) diff --git a/include/linux/virtio.h b/include/linux/virtio.h index 12c18ac1b973..e7d10845b3c1 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -41,6 +41,8 @@ struct virtqueue * Returns NULL or the "data" token handed to add_buf. * @disable_cb: disable callbacks * vq: the struct virtqueue we're talking about. + * Note that this is not necessarily synchronous, hence unreliable and only + * useful as an optimization. * @enable_cb: restart callbacks after disable_cb. * vq: the struct virtqueue we're talking about. * This re-enables callbacks; it returns "false" if there are pending @@ -48,7 +50,8 @@ struct virtqueue * checking for more work, and enabling callbacks. * * Locking rules are straightforward: the driver is responsible for - * locking. No two operations may be invoked simultaneously. + * locking. No two operations may be invoked simultaneously, with the exception + * of @disable_cb. * * All operations can be called in any context. */ -- cgit v1.2.3-59-g8ed1b From 9c5a3d729cf430609d091ff610a7db363aafcd47 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 5 Apr 2008 15:13:23 +0100 Subject: [MIPS] Handle aliases in vmalloc correctly. flush_cache_vmap / flush_cache_vunmap were calling flush_cache_all which - having been deprecated - turned into a nop ... Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 14 ++++++++++++++ arch/mips/mm/c-tx39.c | 15 +++++++++++++++ arch/mips/mm/cache.c | 3 +++ include/asm-mips/cacheflush.h | 18 ++++++++++++++++-- 4 files changed, 48 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 6496925b5e29..77aefb4ebedd 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -361,6 +361,16 @@ static inline int has_valid_asid(const struct mm_struct *mm) #endif } +static void r4k__flush_cache_vmap(void) +{ + r4k_blast_dcache(); +} + +static void r4k__flush_cache_vunmap(void) +{ + r4k_blast_dcache(); +} + static inline void local_r4k_flush_cache_range(void * args) { struct vm_area_struct *vma = args; @@ -1281,6 +1291,10 @@ void __cpuinit r4k_cache_init(void) PAGE_SIZE - 1); else shm_align_mask = PAGE_SIZE-1; + + __flush_cache_vmap = r4k__flush_cache_vmap; + __flush_cache_vunmap = r4k__flush_cache_vunmap; + flush_cache_all = cache_noop; __flush_cache_all = r4k___flush_cache_all; flush_cache_mm = r4k_flush_cache_mm; diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index b09d56981d53..a9f7f1f5e9b4 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -122,6 +122,16 @@ static inline void tx39_blast_icache(void) local_irq_restore(flags); } +static void tx39__flush_cache_vmap(void) +{ + tx39_blast_dcache(); +} + +static void tx39__flush_cache_vunmap(void) +{ + tx39_blast_dcache(); +} + static inline void tx39_flush_cache_all(void) { if (!cpu_has_dc_aliases) @@ -344,6 +354,8 @@ void __cpuinit tx39_cache_init(void) switch (current_cpu_type()) { case CPU_TX3912: /* TX39/H core (writethru direct-map cache) */ + __flush_cache_vmap = tx39__flush_cache_vmap; + __flush_cache_vunmap = tx39__flush_cache_vunmap; flush_cache_all = tx39h_flush_icache_all; __flush_cache_all = tx39h_flush_icache_all; flush_cache_mm = (void *) tx39h_flush_icache_all; @@ -369,6 +381,9 @@ void __cpuinit tx39_cache_init(void) write_c0_wired(0); /* set 8 on reset... */ /* board-dependent init code may set WBON */ + __flush_cache_vmap = tx39__flush_cache_vmap; + __flush_cache_vunmap = tx39__flush_cache_vunmap; + flush_cache_all = tx39_flush_cache_all; __flush_cache_all = tx39___flush_cache_all; flush_cache_mm = tx39_flush_cache_mm; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 51ab1faa027d..f5903679ee6a 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -30,6 +30,9 @@ void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*__flush_cache_vmap)(void); +void (*__flush_cache_vunmap)(void); + /* MIPS specific cache operations */ void (*flush_cache_sigtramp)(unsigned long addr); void (*local_flush_data_cache_page)(void * addr); diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index 01e7eadc97e2..d5c0f2fda51b 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -63,8 +63,22 @@ static inline void flush_icache_page(struct vm_area_struct *vma, } extern void (*flush_icache_range)(unsigned long start, unsigned long end); -#define flush_cache_vmap(start, end) flush_cache_all() -#define flush_cache_vunmap(start, end) flush_cache_all() + +extern void (*__flush_cache_vmap)(void); + +static inline void flush_cache_vmap(unsigned long start, unsigned long end) +{ + if (cpu_has_dc_aliases) + __flush_cache_vmap(); +} + +extern void (*__flush_cache_vunmap)(void); + +static inline void flush_cache_vunmap(unsigned long start, unsigned long end) +{ + if (cpu_has_dc_aliases) + __flush_cache_vunmap(); +} extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, const void *src, -- cgit v1.2.3-59-g8ed1b From 882bebaaca4bb1484078d44ef011f918c0e1e14e Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Mon, 7 Apr 2008 22:33:07 -0700 Subject: [TCP]: tcp_simple_retransmit can cause S+L MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes Bugzilla #10384 tcp_simple_retransmit does L increment without any checking whatsoever for overflowing S+L when Reno is in use. The simplest scenario I can currently think of is rather complex in practice (there might be some more straightforward cases though). Ie., if mss is reduced during mtu probing, it may end up marking everything lost and if some duplicate ACKs arrived prior to that sacked_out will be non-zero as well, leading to S+L > packets_out, tcp_clean_rtx_queue on the next cumulative ACK or tcp_fastretrans_alert on the next duplicate ACK will fix the S counter. More straightforward (but questionable) solution would be to just call tcp_reset_reno_sack() in tcp_simple_retransmit but it would negatively impact the probe's retransmission, ie., the retransmissions would not occur if some duplicate ACKs had arrived. So I had to add reno sacked_out reseting to CA_Loss state when the first cumulative ACK arrives (this stale sacked_out might actually be the explanation for the reports of left_out overflows in kernel prior to 2.6.23 and S+L overflow reports of 2.6.24). However, this alone won't be enough to fix kernel before 2.6.24 because it is building on top of the commit 1b6d427bb7e ([TCP]: Reduce sacked_out with reno when purging write_queue) to keep the sacked_out from overflowing. Signed-off-by: Ilpo Järvinen Reported-by: Alessandro Suardi Signed-off-by: David S. Miller --- include/net/tcp.h | 2 ++ net/ipv4/tcp_input.c | 24 ++++++++++++++++++------ net/ipv4/tcp_output.c | 3 +++ 3 files changed, 23 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/net/tcp.h b/include/net/tcp.h index 7de4ea3a04d9..4fd3eb2f8ec2 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -752,6 +752,8 @@ static inline unsigned int tcp_packets_in_flight(const struct tcp_sock *tp) return tp->packets_out - tcp_left_out(tp) + tp->retrans_out; } +extern int tcp_limit_reno_sacked(struct tcp_sock *tp); + /* If cwnd > ssthresh, we may raise ssthresh to be half-way to cwnd. * The exception is rate halving phase, when cwnd is decreasing towards * ssthresh. diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 7d0958785bfb..b4812c3cbbcf 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -1625,13 +1625,11 @@ out: return flag; } -/* If we receive more dupacks than we expected counting segments - * in assumption of absent reordering, interpret this as reordering. - * The only another reason could be bug in receiver TCP. +/* Limits sacked_out so that sum with lost_out isn't ever larger than + * packets_out. Returns zero if sacked_out adjustement wasn't necessary. */ -static void tcp_check_reno_reordering(struct sock *sk, const int addend) +int tcp_limit_reno_sacked(struct tcp_sock *tp) { - struct tcp_sock *tp = tcp_sk(sk); u32 holes; holes = max(tp->lost_out, 1U); @@ -1639,8 +1637,20 @@ static void tcp_check_reno_reordering(struct sock *sk, const int addend) if ((tp->sacked_out + holes) > tp->packets_out) { tp->sacked_out = tp->packets_out - holes; - tcp_update_reordering(sk, tp->packets_out + addend, 0); + return 1; } + return 0; +} + +/* If we receive more dupacks than we expected counting segments + * in assumption of absent reordering, interpret this as reordering. + * The only another reason could be bug in receiver TCP. + */ +static void tcp_check_reno_reordering(struct sock *sk, const int addend) +{ + struct tcp_sock *tp = tcp_sk(sk); + if (tcp_limit_reno_sacked(tp)) + tcp_update_reordering(sk, tp->packets_out + addend, 0); } /* Emulate SACKs for SACKless connection: account for a new dupack. */ @@ -2600,6 +2610,8 @@ static void tcp_fastretrans_alert(struct sock *sk, int pkts_acked, int flag) case TCP_CA_Loss: if (flag & FLAG_DATA_ACKED) icsk->icsk_retransmits = 0; + if (tcp_is_reno(tp) && flag & FLAG_SND_UNA_ADVANCED) + tcp_reset_reno_sack(tp); if (!tcp_try_undo_loss(sk)) { tcp_moderate_cwnd(tp); tcp_xmit_retransmit_queue(sk); diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 72b9350006fe..d29ef79c00ca 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -1808,6 +1808,9 @@ void tcp_simple_retransmit(struct sock *sk) if (!lost) return; + if (tcp_is_reno(tp)) + tcp_limit_reno_sacked(tp); + tcp_verify_left_out(tp); /* Don't muck with the congestion window here. -- cgit v1.2.3-59-g8ed1b From a31b9dd8edc6e4e75b5299fee6093b3c54548446 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 10 Apr 2008 16:10:45 +0100 Subject: FRV: Handle update_mmu_cache() being called when current->mm is NULL [try #2] Handle update_mmu_cache() being called when current->mm is NULL. We cache static TLB mappings for the current page table in DAMPR4 and DAMPR5 on the theory that the next data lookup is likely to be in the same general region, and thus is likely to be mapped by the same page table. However, we can't get this information if we can't access the appropriate mm_struct. If current->mm is NULL, we just clear the cache in the knowledge that the TLB miss handlers will load it. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- include/asm-frv/pgtable.h | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h index 6c0682ed5fc9..4e219046fe42 100644 --- a/include/asm-frv/pgtable.h +++ b/include/asm-frv/pgtable.h @@ -507,13 +507,22 @@ static inline int pte_file(pte_t pte) */ static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) { + struct mm_struct *mm; unsigned long ampr; - pgd_t *pge = pgd_offset(current->mm, address); - pud_t *pue = pud_offset(pge, address); - pmd_t *pme = pmd_offset(pue, address); - ampr = pme->ste[0] & 0xffffff00; - ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C | xAMPRx_V; + mm = current->mm; + if (mm) { + pgd_t *pge = pgd_offset(mm, address); + pud_t *pue = pud_offset(pge, address); + pmd_t *pme = pmd_offset(pue, address); + + ampr = pme->ste[0] & 0xffffff00; + ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C | + xAMPRx_V; + } else { + address = ULONG_MAX; + ampr = 0; + } asm volatile("movgs %0,scr0\n" "movgs %0,scr1\n" -- cgit v1.2.3-59-g8ed1b From 0c93d8e4d342b1b5cda1037f2527fcf443c80fbc Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 10 Apr 2008 16:10:50 +0100 Subject: FRV: Move STACK_TOP_MAX up [try #2] Move STACK_TOP_MAX up so that we don't try moving the stack above it as that causes setup_arg_pages() to malfunction. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- include/asm-frv/mem-layout.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-frv/mem-layout.h b/include/asm-frv/mem-layout.h index 83532252b8be..734a1d0583b6 100644 --- a/include/asm-frv/mem-layout.h +++ b/include/asm-frv/mem-layout.h @@ -60,7 +60,7 @@ */ #define BRK_BASE __UL(2 * 1024 * 1024 + PAGE_SIZE) #define STACK_TOP __UL(2 * 1024 * 1024) -#define STACK_TOP_MAX STACK_TOP +#define STACK_TOP_MAX __UL(0xc0000000) /* userspace process size */ #ifdef CONFIG_MMU -- cgit v1.2.3-59-g8ed1b From e31c243f984628d02f045dc4b622f1e2827860dc Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 10 Apr 2008 16:10:55 +0100 Subject: FRV: Add support for emulation of userspace atomic ops [try #2] Use traps 120-126 to emulate atomic cmpxchg32, xchg32, and XOR-, OR-, AND-, SUB- and ADD-to-memory operations for userspace. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/frv/kernel/entry-table.S | 8 +- arch/frv/kernel/entry.S | 20 ++++ arch/frv/kernel/traps.c | 227 ++++++++++++++++++++++++++++++++++++++++++ include/asm-frv/spr-regs.h | 14 +++ 4 files changed, 268 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/frv/kernel/entry-table.S b/arch/frv/kernel/entry-table.S index d3b9253d862a..bf35f33e48c9 100644 --- a/arch/frv/kernel/entry-table.S +++ b/arch/frv/kernel/entry-table.S @@ -316,8 +316,14 @@ __trap_fixup_kernel_data_tlb_miss: .section .trap.vector .org TBR_TT_TRAP0 >> 2 .long system_call - .rept 126 + .rept 119 .long __entry_unsupported_trap .endr + + # userspace atomic op emulation, traps 120-126 + .rept 7 + .long __entry_atomic_op + .endr + .org TBR_TT_BREAK >> 2 .long __entry_debug_exception diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S index f36d7f4a7c25..b8a4b94779b1 100644 --- a/arch/frv/kernel/entry.S +++ b/arch/frv/kernel/entry.S @@ -654,6 +654,26 @@ __entry_debug_exception: movgs gr4,psr jmpl @(gr5,gr0) ; call ill_insn(esfr1,epcr0,esr0) +############################################################################### +# +# handle atomic operation emulation for userspace +# +############################################################################### + .globl __entry_atomic_op +__entry_atomic_op: + LEDS 0x6012 + sethi.p %hi(atomic_operation),gr5 + setlo %lo(atomic_operation),gr5 + movsg esfr1,gr8 + movsg epcr0,gr9 + movsg esr0,gr10 + + # now that we've accessed the exception regs, we can enable exceptions + movsg psr,gr4 + ori gr4,#PSR_ET,gr4 + movgs gr4,psr + jmpl @(gr5,gr0) ; call atomic_operation(esfr1,epcr0,esr0) + ############################################################################### # # handle media exception diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c index 2e6098c85578..2f7e66877f3b 100644 --- a/arch/frv/kernel/traps.c +++ b/arch/frv/kernel/traps.c @@ -100,6 +100,233 @@ asmlinkage void illegal_instruction(unsigned long esfr1, unsigned long epcr0, un force_sig_info(info.si_signo, &info, current); } /* end illegal_instruction() */ +/*****************************************************************************/ +/* + * handle atomic operations with errors + * - arguments in gr8, gr9, gr10 + * - original memory value placed in gr5 + * - replacement memory value placed in gr9 + */ +asmlinkage void atomic_operation(unsigned long esfr1, unsigned long epcr0, + unsigned long esr0) +{ + static DEFINE_SPINLOCK(atomic_op_lock); + unsigned long x, y, z, *p; + mm_segment_t oldfs; + siginfo_t info; + int ret; + + y = 0; + z = 0; + + oldfs = get_fs(); + if (!user_mode(__frame)) + set_fs(KERNEL_DS); + + switch (__frame->tbr & TBR_TT) { + /* TIRA gr0,#120 + * u32 __atomic_user_cmpxchg32(u32 *ptr, u32 test, u32 new) + */ + case TBR_TT_ATOMIC_CMPXCHG32: + p = (unsigned long *) __frame->gr8; + x = __frame->gr9; + y = __frame->gr10; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + if (z != x) + goto done; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + if (z != x) + goto done2; + + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + /* TIRA gr0,#121 + * u32 __atomic_kernel_xchg32(void *v, u32 new) + */ + case TBR_TT_ATOMIC_XCHG32: + p = (unsigned long *) __frame->gr8; + y = __frame->gr9; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + /* TIRA gr0,#122 + * ulong __atomic_kernel_XOR_return(ulong i, ulong *v) + */ + case TBR_TT_ATOMIC_XOR: + p = (unsigned long *) __frame->gr8; + x = __frame->gr9; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + y = x ^ z; + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + /* TIRA gr0,#123 + * ulong __atomic_kernel_OR_return(ulong i, ulong *v) + */ + case TBR_TT_ATOMIC_OR: + p = (unsigned long *) __frame->gr8; + x = __frame->gr9; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + y = x ^ z; + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + /* TIRA gr0,#124 + * ulong __atomic_kernel_AND_return(ulong i, ulong *v) + */ + case TBR_TT_ATOMIC_AND: + p = (unsigned long *) __frame->gr8; + x = __frame->gr9; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + y = x & z; + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + /* TIRA gr0,#125 + * int __atomic_user_sub_return(atomic_t *v, int i) + */ + case TBR_TT_ATOMIC_SUB: + p = (unsigned long *) __frame->gr8; + x = __frame->gr9; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + y = z - x; + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + /* TIRA gr0,#126 + * int __atomic_user_add_return(atomic_t *v, int i) + */ + case TBR_TT_ATOMIC_ADD: + p = (unsigned long *) __frame->gr8; + x = __frame->gr9; + + for (;;) { + ret = get_user(z, p); + if (ret < 0) + goto error; + + spin_lock_irq(&atomic_op_lock); + + if (__get_user(z, p) == 0) { + y = z + x; + if (__put_user(y, p) == 0) + goto done2; + goto error2; + } + + spin_unlock_irq(&atomic_op_lock); + } + + default: + BUG(); + } + +done2: + spin_unlock_irq(&atomic_op_lock); +done: + if (!user_mode(__frame)) + set_fs(oldfs); + __frame->gr5 = z; + __frame->gr9 = y; + return; + +error2: + spin_unlock_irq(&atomic_op_lock); +error: + if (!user_mode(__frame)) + set_fs(oldfs); + __frame->pc -= 4; + + die_if_kernel("-- Atomic Op Error --\n"); + + info.si_signo = SIGSEGV; + info.si_code = SEGV_ACCERR; + info.si_errno = 0; + info.si_addr = (void *) __frame->pc; + + force_sig_info(info.si_signo, &info, current); +} + /*****************************************************************************/ /* * diff --git a/include/asm-frv/spr-regs.h b/include/asm-frv/spr-regs.h index c2a541ef828d..01e6af5e99b8 100644 --- a/include/asm-frv/spr-regs.h +++ b/include/asm-frv/spr-regs.h @@ -99,9 +99,23 @@ #define TBR_TT_TRAP1 (0x81 << 4) #define TBR_TT_TRAP2 (0x82 << 4) #define TBR_TT_TRAP3 (0x83 << 4) +#define TBR_TT_TRAP120 (0xf8 << 4) +#define TBR_TT_TRAP121 (0xf9 << 4) +#define TBR_TT_TRAP122 (0xfa << 4) +#define TBR_TT_TRAP123 (0xfb << 4) +#define TBR_TT_TRAP124 (0xfc << 4) +#define TBR_TT_TRAP125 (0xfd << 4) #define TBR_TT_TRAP126 (0xfe << 4) #define TBR_TT_BREAK (0xff << 4) +#define TBR_TT_ATOMIC_CMPXCHG32 TBR_TT_TRAP120 +#define TBR_TT_ATOMIC_XCHG32 TBR_TT_TRAP121 +#define TBR_TT_ATOMIC_XOR TBR_TT_TRAP122 +#define TBR_TT_ATOMIC_OR TBR_TT_TRAP123 +#define TBR_TT_ATOMIC_AND TBR_TT_TRAP124 +#define TBR_TT_ATOMIC_SUB TBR_TT_TRAP125 +#define TBR_TT_ATOMIC_ADD TBR_TT_TRAP126 + #define __get_TBR() ({ unsigned long x; asm volatile("movsg tbr,%0" : "=r"(x)); x; }) /* -- cgit v1.2.3-59-g8ed1b From f17520e1f19172057328e50ffed01a42534921e9 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 10 Apr 2008 16:11:05 +0100 Subject: FRV: Don't make smp_{r, w, }mb() interpolate MEMBAR when CONFIG_SMP=n [try #2] Don't make smp_{r,w,}mb() interpolate a MEMBAR instruction when CONFIG_SMP=n as SMP memory barries on UP systems should interpolate a compiler barrier only. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- include/asm-frv/system.h | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h index 2c57f4734746..30a67a9da11a 100644 --- a/include/asm-frv/system.h +++ b/include/asm-frv/system.h @@ -179,14 +179,23 @@ do { \ #define mb() asm volatile ("membar" : : :"memory") #define rmb() asm volatile ("membar" : : :"memory") #define wmb() asm volatile ("membar" : : :"memory") -#define set_mb(var, value) do { var = value; mb(); } while (0) +#define read_barrier_depends() barrier() -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() - -#define read_barrier_depends() do {} while(0) +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() #define smp_read_barrier_depends() read_barrier_depends() +#define set_mb(var, value) \ + do { xchg(&var, (value)); } while (0) +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do {} while(0) +#define set_mb(var, value) \ + do { var = (value); barrier(); } while (0) +#endif #define HARD_RESET_NOW() \ do { \ -- cgit v1.2.3-59-g8ed1b From 54a015104136974262afa4b8ddd943ea70dec8a2 Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Thu, 10 Apr 2008 15:37:38 -0700 Subject: asmlinkage_protect replaces prevent_tail_call The prevent_tail_call() macro works around the problem of the compiler clobbering argument words on the stack, which for asmlinkage functions is the caller's (user's) struct pt_regs. The tail/sibling-call optimization is not the only way that the compiler can decide to use stack argument words as scratch space, which we have to prevent. Other optimizations can do it too. Until we have new compiler support to make "asmlinkage" binding on the compiler's own use of the stack argument frame, we have work around all the manifestations of this issue that crop up. More cases seem to be prevented by also keeping the incoming argument variables live at the end of the function. This makes their original stack slots attractive places to leave those variables, so the compiler tends not clobber them for something else. It's still no guarantee, but it handles some observed cases that prevent_tail_call() did not. Signed-off-by: Roland McGrath Signed-off-by: Linus Torvalds --- arch/x86/kernel/tls.c | 4 ++-- fs/open.c | 8 ++++---- include/asm-x86/linkage.h | 24 +++++++++++++++++++++++- include/linux/linkage.h | 4 ++-- kernel/exit.c | 4 ++-- kernel/uid16.c | 22 +++++++++++----------- 6 files changed, 44 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 022bcaa3b42e..ab6bf375a307 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -92,7 +92,7 @@ int do_set_thread_area(struct task_struct *p, int idx, asmlinkage int sys_set_thread_area(struct user_desc __user *u_info) { int ret = do_set_thread_area(current, -1, u_info, 1); - prevent_tail_call(ret); + asmlinkage_protect(1, ret, u_info); return ret; } @@ -142,7 +142,7 @@ int do_get_thread_area(struct task_struct *p, int idx, asmlinkage int sys_get_thread_area(struct user_desc __user *u_info) { int ret = do_get_thread_area(current, -1, u_info); - prevent_tail_call(ret); + asmlinkage_protect(1, ret, u_info); return ret; } diff --git a/fs/open.c b/fs/open.c index a4b12022edaa..3fa4e4ffce4c 100644 --- a/fs/open.c +++ b/fs/open.c @@ -335,7 +335,7 @@ asmlinkage long sys_ftruncate(unsigned int fd, unsigned long length) { long ret = do_sys_ftruncate(fd, length, 1); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(2, ret, fd, length); return ret; } @@ -350,7 +350,7 @@ asmlinkage long sys_ftruncate64(unsigned int fd, loff_t length) { long ret = do_sys_ftruncate(fd, length, 0); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(2, ret, fd, length); return ret; } #endif @@ -1067,7 +1067,7 @@ asmlinkage long sys_open(const char __user *filename, int flags, int mode) ret = do_sys_open(AT_FDCWD, filename, flags, mode); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(3, ret, filename, flags, mode); return ret; } @@ -1081,7 +1081,7 @@ asmlinkage long sys_openat(int dfd, const char __user *filename, int flags, ret = do_sys_open(dfd, filename, flags, mode); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(4, ret, dfd, filename, flags, mode); return ret; } diff --git a/include/asm-x86/linkage.h b/include/asm-x86/linkage.h index 31739c7d66a9..d605eeba0f70 100644 --- a/include/asm-x86/linkage.h +++ b/include/asm-x86/linkage.h @@ -8,12 +8,34 @@ #ifdef CONFIG_X86_32 #define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0))) -#define prevent_tail_call(ret) __asm__ ("" : "=r" (ret) : "0" (ret)) /* * For 32-bit UML - mark functions implemented in assembly that use * regparm input parameters: */ #define asmregparm __attribute__((regparm(3))) + +#define asmlinkage_protect(n, ret, args...) \ + __asmlinkage_protect##n(ret, ##args) +#define __asmlinkage_protect_n(ret, args...) \ + __asm__ __volatile__ ("" : "=r" (ret) : "0" (ret), ##args) +#define __asmlinkage_protect0(ret) \ + __asmlinkage_protect_n(ret) +#define __asmlinkage_protect1(ret, arg1) \ + __asmlinkage_protect_n(ret, "g" (arg1)) +#define __asmlinkage_protect2(ret, arg1, arg2) \ + __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2)) +#define __asmlinkage_protect3(ret, arg1, arg2, arg3) \ + __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3)) +#define __asmlinkage_protect4(ret, arg1, arg2, arg3, arg4) \ + __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \ + "g" (arg4)) +#define __asmlinkage_protect5(ret, arg1, arg2, arg3, arg4, arg5) \ + __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \ + "g" (arg4), "g" (arg5)) +#define __asmlinkage_protect6(ret, arg1, arg2, arg3, arg4, arg5, arg6) \ + __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \ + "g" (arg4), "g" (arg5), "g" (arg6)) + #endif #ifdef CONFIG_X86_ALIGNMENT_16 diff --git a/include/linux/linkage.h b/include/linux/linkage.h index 0592936344c4..fe2a39c489b6 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -17,8 +17,8 @@ # define asmregparm #endif -#ifndef prevent_tail_call -# define prevent_tail_call(ret) do { } while (0) +#ifndef asmlinkage_protect +# define asmlinkage_protect(n, ret, args...) do { } while (0) #endif #ifndef __ALIGN diff --git a/kernel/exit.c b/kernel/exit.c index 53872bf993fa..073005b1cfb2 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -1608,7 +1608,7 @@ asmlinkage long sys_waitid(int which, pid_t upid, put_pid(pid); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(5, ret, which, upid, infop, options, ru); return ret; } @@ -1640,7 +1640,7 @@ asmlinkage long sys_wait4(pid_t upid, int __user *stat_addr, put_pid(pid); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(4, ret, upid, stat_addr, options, ru); return ret; } diff --git a/kernel/uid16.c b/kernel/uid16.c index dd308ba4e03b..3e41c1673e2f 100644 --- a/kernel/uid16.c +++ b/kernel/uid16.c @@ -21,7 +21,7 @@ asmlinkage long sys_chown16(const char __user * filename, old_uid_t user, old_gi { long ret = sys_chown(filename, low2highuid(user), low2highgid(group)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(3, ret, filename, user, group); return ret; } @@ -29,7 +29,7 @@ asmlinkage long sys_lchown16(const char __user * filename, old_uid_t user, old_g { long ret = sys_lchown(filename, low2highuid(user), low2highgid(group)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(3, ret, filename, user, group); return ret; } @@ -37,7 +37,7 @@ asmlinkage long sys_fchown16(unsigned int fd, old_uid_t user, old_gid_t group) { long ret = sys_fchown(fd, low2highuid(user), low2highgid(group)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(3, ret, fd, user, group); return ret; } @@ -45,7 +45,7 @@ asmlinkage long sys_setregid16(old_gid_t rgid, old_gid_t egid) { long ret = sys_setregid(low2highgid(rgid), low2highgid(egid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(2, ret, rgid, egid); return ret; } @@ -53,7 +53,7 @@ asmlinkage long sys_setgid16(old_gid_t gid) { long ret = sys_setgid(low2highgid(gid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(1, ret, gid); return ret; } @@ -61,7 +61,7 @@ asmlinkage long sys_setreuid16(old_uid_t ruid, old_uid_t euid) { long ret = sys_setreuid(low2highuid(ruid), low2highuid(euid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(2, ret, ruid, euid); return ret; } @@ -69,7 +69,7 @@ asmlinkage long sys_setuid16(old_uid_t uid) { long ret = sys_setuid(low2highuid(uid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(1, ret, uid); return ret; } @@ -78,7 +78,7 @@ asmlinkage long sys_setresuid16(old_uid_t ruid, old_uid_t euid, old_uid_t suid) long ret = sys_setresuid(low2highuid(ruid), low2highuid(euid), low2highuid(suid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(3, ret, ruid, euid, suid); return ret; } @@ -98,7 +98,7 @@ asmlinkage long sys_setresgid16(old_gid_t rgid, old_gid_t egid, old_gid_t sgid) long ret = sys_setresgid(low2highgid(rgid), low2highgid(egid), low2highgid(sgid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(3, ret, rgid, egid, sgid); return ret; } @@ -117,7 +117,7 @@ asmlinkage long sys_setfsuid16(old_uid_t uid) { long ret = sys_setfsuid(low2highuid(uid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(1, ret, uid); return ret; } @@ -125,7 +125,7 @@ asmlinkage long sys_setfsgid16(old_gid_t gid) { long ret = sys_setfsgid(low2highgid(gid)); /* avoid REGPARM breakage on x86: */ - prevent_tail_call(ret); + asmlinkage_protect(1, ret, gid); return ret; } -- cgit v1.2.3-59-g8ed1b From d10d89ec78114f925f63c5126a2b2490f501a462 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 10 Apr 2008 17:35:23 -0700 Subject: Add commentary about the new "asmlinkage_protect()" macro It's really a pretty ugly thing to need, and some day it will hopefully be obviated by teaching gcc about the magic calling conventions for the low-level system call code, but in the meantime we can at least add big honking comments about why we need these insane and strange macros. I took my comments from my version of the macro, but I ended up deciding to just pick Roland's version of the actual code instead (with his prettier syntax that uses vararg macros). Thus the previous two commits that actually implement it. Signed-off-by: Linus Torvalds --- include/asm-x86/linkage.h | 11 +++++++++++ include/linux/linkage.h | 13 +++++++++++++ 2 files changed, 24 insertions(+) (limited to 'include') diff --git a/include/asm-x86/linkage.h b/include/asm-x86/linkage.h index d605eeba0f70..c048353f4b85 100644 --- a/include/asm-x86/linkage.h +++ b/include/asm-x86/linkage.h @@ -14,6 +14,17 @@ */ #define asmregparm __attribute__((regparm(3))) +/* + * Make sure the compiler doesn't do anything stupid with the + * arguments on the stack - they are owned by the *caller*, not + * the callee. This just fools gcc into not spilling into them, + * and keeps it from doing tailcall recursion and/or using the + * stack slots for temporaries, since they are live and "used" + * all the way to the end of the function. + * + * NOTE! On x86-64, all the arguments are in registers, so this + * only matters on a 32-bit kernel. + */ #define asmlinkage_protect(n, ret, args...) \ __asmlinkage_protect##n(ret, ##args) #define __asmlinkage_protect_n(ret, args...) \ diff --git a/include/linux/linkage.h b/include/linux/linkage.h index fe2a39c489b6..b163c5c40dbc 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -17,6 +17,19 @@ # define asmregparm #endif +/* + * This is used by architectures to keep arguments on the stack + * untouched by the compiler by keeping them live until the end. + * The argument stack may be owned by the assembly-language + * caller, not the callee, and gcc doesn't always understand + * that. + * + * We have the return value, and a maximum of six arguments. + * + * This should always be followed by a "return ret" for the + * protection to work (ie no more work that the compiler might + * end up needing stack temporaries for). + */ #ifndef asmlinkage_protect # define asmlinkage_protect(n, ret, args...) do { } while (0) #endif -- cgit v1.2.3-59-g8ed1b From 544451a1a36b06f43fc67112ede3b92e6203eb9d Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 10 Apr 2008 21:29:28 -0700 Subject: pnp: increase number of devices supported per protocol Increase the PNP "number of devices" limit. We currently use an unsigned char, which limits us to 256 devices per protocol. This patch changes that to an unsigned int. Not all backends can take advantage of this: we limit ISAPNP to 10 devices in isapnp_cfg_begin(), and PNPBIOS is limited to 256 devices because the BIOS interfaces use a one-byte device node number. But there is no limit on the number of PNPACPI devices we may have. Large HP Integrity machines have more than 256, which causes the current "unsigned char number" to wrap around. This causes errors like this: pnp: PnP ACPI init kobject_add failed for 00:00 with -EEXIST, don't try to register things with the same name in the same directory. Call Trace: [] show_stack+0x40/0xa0 [] dump_stack+0x30/0x60 [] kobject_add+0x290/0x2c0 [] device_add+0x160/0x860 [] device_register+0x30/0x60 [] __pnp_add_device+0x130/0x180 [] pnp_add_device+0xb0/0xe0 [] pnpacpi_add_device+0x510/0x5a0 [] pnpacpi_add_device_handler+0x50/0x80 This patch increases the limit to fix this PNPACPI problem. It should not have any adverse effect on ISAPNP or PNPBIOS because their limits are still enforced in the backends. Signed-off-by: Bjorn Helgaas Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/pnp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/pnp.h b/include/linux/pnp.h index 29dd55838e84..b2f05c230f4b 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -175,7 +175,7 @@ static inline void pnp_set_card_drvdata(struct pnp_card_link *pcard, void *data) struct pnp_dev { struct device dev; /* Driver Model device interface */ u64 dma_mask; - unsigned char number; /* used as an index, must be unique */ + unsigned int number; /* used as an index, must be unique */ int status; struct list_head global_list; /* node in global list of devices */ -- cgit v1.2.3-59-g8ed1b From b0fac02370cffad956ff3de5e8ed4df7e7b875d7 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Fri, 11 Apr 2008 13:46:54 +0200 Subject: Fix "$(AS) -traditional" compile breakage caused by asmlinkage_protect git commit 54a015104136974262afa4b8ddd943ea70dec8a2 ("asmlinkage_protect replaces prevent_tail_call") causes this build failure on s390: AS arch/s390/kernel/entry64.o In file included from arch/s390/kernel/entry64.S:14: include/linux/linkage.h:34: error: syntax error in macro parameter list make[1]: *** [arch/s390/kernel/entry64.o] Error 1 make: *** [arch/s390/kernel] Error 2 and some other architectures. The reason is that some architectures add the "-traditional" flag to the invocation of $(AS), which disables variadic macro argument support. So just surround the new define with an #ifndef __ASSEMBLY__ to prevent any side effects on asm code. Cc: Roland McGrath Cc: Martin Schwidefsky Signed-off-by: Heiko Carstens Signed-off-by: Linus Torvalds --- include/linux/linkage.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/linkage.h b/include/linux/linkage.h index b163c5c40dbc..2119610b24f8 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -30,9 +30,12 @@ * protection to work (ie no more work that the compiler might * end up needing stack temporaries for). */ +/* Assembly files may be compiled with -traditional .. */ +#ifndef __ASSEMBLY__ #ifndef asmlinkage_protect # define asmlinkage_protect(n, ret, args...) do { } while (0) #endif +#endif #ifndef __ALIGN #define __ALIGN .align 4,0x90 -- cgit v1.2.3-59-g8ed1b From dc07e721a26ec7e0adb66340f1763d220cfbbd0c Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Mon, 7 Apr 2008 15:59:05 -0400 Subject: Spell out behavior of atomic_dec_and_lock() in kerneldoc A little more detail here wouldn't hurt. Signed-off-by: J. Bruce Fields Signed-off-by: Jonathan Corbet --- include/linux/spinlock.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index 576a5f77d3bd..1129ee0a7180 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -341,6 +341,9 @@ static inline void double_spin_unlock(spinlock_t *l1, spinlock_t *l2, * atomic_dec_and_lock - lock on reaching reference count zero * @atomic: the atomic counter * @lock: the spinlock in question + * + * Decrements @atomic by 1. If the result is 0, returns true and locks + * @lock. Returns false for all other cases. */ extern int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock); #define atomic_dec_and_lock(atomic, lock) \ -- cgit v1.2.3-59-g8ed1b From 52e3134423c3af4431fedb34f77e31cfff91e0c3 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 3 Mar 2008 12:43:23 -0800 Subject: ARM: OMAP: Use gpiolib Update OMAP to use the new GPIO implementation framework. This is just a quick'n'dirty update ... more code could now be removed, ideally as part of cleaning up the entire OMAP GPIO infrastructure ... Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/Kconfig | 1 + arch/arm/plat-omap/gpio.c | 107 ++++++++++++++++++++++++++++++++------- include/asm-arm/arch-omap/gpio.h | 57 ++++++--------------- 3 files changed, 105 insertions(+), 60 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4039a133006e..992028f46bd1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -468,6 +468,7 @@ config ARCH_DAVINCI config ARCH_OMAP bool "TI OMAP" select GENERIC_GPIO + select HAVE_GPIO_LIB select GENERIC_TIME select GENERIC_CLOCKEVENTS help diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 8c78e4e57b5c..56889fdb0740 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -136,7 +136,6 @@ struct gpio_bank { u16 irq; u16 virtual_irq_start; int method; - u32 reserved_map; #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) u32 suspend_wakeup; u32 saved_wakeup; @@ -150,6 +149,7 @@ struct gpio_bank { u32 saved_risingdetect; #endif spinlock_t lock; + struct gpio_chip chip; }; #define METHOD_MPUIO 0 @@ -903,19 +903,17 @@ int omap_request_gpio(int gpio) { struct gpio_bank *bank; unsigned long flags; + int status; if (check_gpio(gpio) < 0) return -EINVAL; + status = gpio_request(gpio, NULL); + if (status < 0) + return status; + bank = get_gpio_bank(gpio); spin_lock_irqsave(&bank->lock, flags); - if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { - printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); - dump_stack(); - spin_unlock_irqrestore(&bank->lock, flags); - return -1; - } - bank->reserved_map |= (1 << get_gpio_index(gpio)); /* Set trigger to none. You need to enable the desired trigger with * request_irq() or set_irq_type(). @@ -945,10 +943,11 @@ void omap_free_gpio(int gpio) return; bank = get_gpio_bank(gpio); spin_lock_irqsave(&bank->lock, flags); - if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { + if (unlikely(!gpiochip_is_requested(&bank->chip, + get_gpio_index(gpio)))) { + spin_unlock_irqrestore(&bank->lock, flags); printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); dump_stack(); - spin_unlock_irqrestore(&bank->lock, flags); return; } #ifdef CONFIG_ARCH_OMAP16XX @@ -965,9 +964,9 @@ void omap_free_gpio(int gpio) __raw_writel(1 << get_gpio_index(gpio), reg); } #endif - bank->reserved_map &= ~(1 << get_gpio_index(gpio)); _reset_gpio(bank, gpio); spin_unlock_irqrestore(&bank->lock, flags); + gpio_free(gpio); } /* @@ -1266,6 +1265,53 @@ static inline void mpuio_init(void) {} /*---------------------------------------------------------------------*/ +/* REVISIT these are stupid implementations! replace by ones that + * don't switch on METHOD_* and which mostly avoid spinlocks + */ + +static int gpio_input(struct gpio_chip *chip, unsigned offset) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_direction(bank, offset, 1); + spin_unlock_irqrestore(&bank->lock, flags); + return 0; +} + +static int gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return omap_get_gpio_datain(chip->base + offset); +} + +static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_dataout(bank, offset, value); + _set_gpio_direction(bank, offset, 0); + spin_unlock_irqrestore(&bank->lock, flags); + return 0; +} + +static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_dataout(bank, offset, value); + spin_unlock_irqrestore(&bank->lock, flags); +} + +/*---------------------------------------------------------------------*/ + static int initialized; #if !defined(CONFIG_ARCH_OMAP3) static struct clk * gpio_ick; @@ -1293,6 +1339,7 @@ static struct lock_class_key gpio_lock_class; static int __init _omap_gpio_init(void) { int i; + int gpio = 0; struct gpio_bank *bank; #if defined(CONFIG_ARCH_OMAP3) char clk_name[11]; @@ -1423,7 +1470,6 @@ static int __init _omap_gpio_init(void) int j, gpio_count = 16; bank = &gpio_bank[i]; - bank->reserved_map = 0; bank->base = IO_ADDRESS(bank->base); spin_lock_init(&bank->lock); if (bank_is_mpuio(bank)) @@ -1461,6 +1507,26 @@ static int __init _omap_gpio_init(void) gpio_count = 32; } #endif + + /* REVISIT eventually switch from OMAP-specific gpio structs + * over to the generic ones + */ + bank->chip.direction_input = gpio_input; + bank->chip.get = gpio_get; + bank->chip.direction_output = gpio_output; + bank->chip.set = gpio_set; + if (bank_is_mpuio(bank)) { + bank->chip.label = "mpuio"; + bank->chip.base = OMAP_MPUIO(0); + } else { + bank->chip.label = "gpio"; + bank->chip.base = gpio; + gpio += gpio_count; + } + bank->chip.ngpio = gpio_count; + + gpiochip_add(&bank->chip); + for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + gpio_count; j++) { lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); @@ -1757,8 +1823,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { unsigned irq, value, is_in, irqstat; + const char *label; - if (!(bank->reserved_map & mask)) + label = gpiochip_is_requested(&bank->chip, j); + if (!label) continue; irq = bank->virtual_irq_start + j; @@ -1766,13 +1834,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) is_in = gpio_is_input(bank, mask); if (bank_is_mpuio(bank)) - seq_printf(s, "MPUIO %2d: ", j); + seq_printf(s, "MPUIO %2d ", j); else - seq_printf(s, "GPIO %3d: ", gpio); - seq_printf(s, "%s %s", + seq_printf(s, "GPIO %3d ", gpio); + seq_printf(s, "(%10s): %s %s", + label, is_in ? "in " : "out", value ? "hi" : "lo"); +/* FIXME for at least omap2, show pullup/pulldown state */ + irqstat = irq_desc[irq].status; if (is_in && ((bank->suspend_wakeup & mask) || irqstat & IRQ_TYPE_SENSE_MASK)) { @@ -1795,10 +1866,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) trigger = "high"; break; case IRQ_TYPE_NONE: - trigger = "(unspecified)"; + trigger = "(?)"; break; } - seq_printf(s, ", irq-%d %s%s", + seq_printf(s, ", irq-%d %-8s%s", irq, trigger, (bank->suspend_wakeup & mask) ? " wakeup" : ""); diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h index 164da09be095..86621a04cd8f 100644 --- a/include/asm-arm/arch-omap/gpio.h +++ b/include/asm-arm/arch-omap/gpio.h @@ -82,62 +82,35 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable); /*-------------------------------------------------------------------------*/ -/* wrappers for "new style" GPIO calls. the old OMAP-specfic ones should - * eventually be removed (along with this errno.h inclusion), and maybe - * gpios should put MPUIOs last too. +/* Wrappers for "new style" GPIO calls, using the new infrastructure + * which lets us plug in FPGA, I2C, and other implementations. + * * + * The original OMAP-specfic calls should eventually be removed. */ -#include - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return omap_request_gpio(gpio); -} - -static inline void gpio_free(unsigned gpio) -{ - omap_free_gpio(gpio); -} - -static inline int __gpio_set_direction(unsigned gpio, int is_input) -{ - if (cpu_class_is_omap2()) { - if (gpio > OMAP_MAX_GPIO_LINES) - return -EINVAL; - } else { - if (gpio > (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)) - return -EINVAL; - } - omap_set_gpio_direction(gpio, is_input); - return 0; -} - -static inline int gpio_direction_input(unsigned gpio) -{ - return __gpio_set_direction(gpio, 1); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - omap_set_gpio_dataout(gpio, value); - return __gpio_set_direction(gpio, 0); -} +#include +#include static inline int gpio_get_value(unsigned gpio) { - return omap_get_gpio_datain(gpio); + return __gpio_get_value(gpio); } static inline void gpio_set_value(unsigned gpio, int value) { - omap_set_gpio_dataout(gpio, value); + __gpio_set_value(gpio, value); } -#include /* cansleep wrappers */ +static inline int gpio_cansleep(unsigned gpio) +{ + return __gpio_cansleep(gpio); +} static inline int gpio_to_irq(unsigned gpio) { - return OMAP_GPIO_IRQ(gpio); + if (gpio < (OMAP_MAX_GPIO_LINES + 16)) + return OMAP_GPIO_IRQ(gpio); + return -EINVAL; } static inline int irq_to_gpio(unsigned irq) -- cgit v1.2.3-59-g8ed1b From 79966fd9b4781f9bd257312489ff511f2c01f210 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 28 Feb 2008 22:07:28 -0800 Subject: ARM: OMAP: I2C: tps65010 driver converts to gpiolib Make the tps65010 driver use gpiolib to expose its GPIOs. Note: This patch will get merged via omap tree instead of I2C as it will cause some board updates. This has been discussed at on the I2C list: http://lists.lm-sensors.org/pipermail/i2c/2008-March/003031.html Signed-off-by: David Brownell Cc: i2c@lm-sensors.org Signed-off-by: Tony Lindgren --- drivers/i2c/chips/Kconfig | 1 + drivers/i2c/chips/tps65010.c | 101 ++++++++++++++++++++++++++++++++++++++++++- include/linux/i2c/tps65010.h | 30 +++++++++++++ 3 files changed, 131 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/i2c/chips/Kconfig b/drivers/i2c/chips/Kconfig index b21593f93586..2da2edfa68ec 100644 --- a/drivers/i2c/chips/Kconfig +++ b/drivers/i2c/chips/Kconfig @@ -93,6 +93,7 @@ config ISP1301_OMAP config TPS65010 tristate "TPS6501x Power Management chips" + depends on HAVE_GPIO_LIB default y if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_OSK help If you say yes here you get support for the TPS6501x series of diff --git a/drivers/i2c/chips/tps65010.c b/drivers/i2c/chips/tps65010.c index 4154a9108859..b67f69c2e7f3 100644 --- a/drivers/i2c/chips/tps65010.c +++ b/drivers/i2c/chips/tps65010.c @@ -30,9 +30,13 @@ #include #include #include +#include #include +#include + + /*-------------------------------------------------------------------------*/ #define DRIVER_VERSION "2 May 2005" @@ -84,7 +88,9 @@ struct tps65010 { u8 chgstatus, regstatus, chgconf; u8 nmask1, nmask2; - /* not currently tracking GPIO state */ + u8 outmask; + struct gpio_chip chip; + struct platform_device *leds; }; #define POWER_POLL_DELAY msecs_to_jiffies(5000) @@ -447,6 +453,59 @@ static irqreturn_t tps65010_irq(int irq, void *_tps) return IRQ_HANDLED; } +/*-------------------------------------------------------------------------*/ + +/* offsets 0..3 == GPIO1..GPIO4 + * offsets 4..5 == LED1/nPG, LED2 (we set one of the non-BLINK modes) + */ +static void +tps65010_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (offset < 4) + tps65010_set_gpio_out_value(offset + 1, value); + else + tps65010_set_led(offset - 3, value ? ON : OFF); +} + +static int +tps65010_output(struct gpio_chip *chip, unsigned offset, int value) +{ + /* GPIOs may be input-only */ + if (offset < 4) { + struct tps65010 *tps; + + tps = container_of(chip, struct tps65010, chip); + if (!(tps->outmask & (1 << offset))) + return -EINVAL; + tps65010_set_gpio_out_value(offset + 1, value); + } else + tps65010_set_led(offset - 3, value ? ON : OFF); + + return 0; +} + +static int tps65010_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + int value; + struct tps65010 *tps; + + tps = container_of(chip, struct tps65010, chip); + + if (offset < 4) { + value = i2c_smbus_read_byte_data(tps->client, TPS_DEFGPIO); + if (value < 0) + return 0; + if (value & (1 << (offset + 4))) /* output */ + return !(value & (1 << offset)); + else /* input */ + return (value & (1 << offset)); + } + + /* REVISIT we *could* report LED1/nPG and LED2 state ... */ + return 0; +} + + /*-------------------------------------------------------------------------*/ static struct tps65010 *the_tps; @@ -454,7 +513,14 @@ static struct tps65010 *the_tps; static int __exit tps65010_remove(struct i2c_client *client) { struct tps65010 *tps = i2c_get_clientdata(client); + struct tps65010_board *board = client->dev.platform_data; + if (board && board->teardown) { + int status = board->teardown(client, board->context); + if (status < 0) + dev_dbg(&client->dev, "board %s %s err %d\n", + "teardown", client->name, status); + } if (client->irq > 0) free_irq(client->irq, tps); cancel_delayed_work(&tps->work); @@ -469,6 +535,7 @@ static int tps65010_probe(struct i2c_client *client) { struct tps65010 *tps; int status; + struct tps65010_board *board = client->dev.platform_data; if (the_tps) { dev_dbg(&client->dev, "only one tps6501x chip allowed\n"); @@ -577,6 +644,38 @@ static int tps65010_probe(struct i2c_client *client) tps->file = debugfs_create_file(DRIVER_NAME, S_IRUGO, NULL, tps, DEBUG_FOPS); + + /* optionally register GPIOs */ + if (board && board->base > 0) { + tps->outmask = board->outmask; + + tps->chip.label = client->name; + + tps->chip.set = tps65010_gpio_set; + tps->chip.direction_output = tps65010_output; + + /* NOTE: only partial support for inputs; nyet IRQs */ + tps->chip.get = tps65010_gpio_get; + + tps->chip.base = board->base; + tps->chip.ngpio = 6; + tps->chip.can_sleep = 1; + + status = gpiochip_add(&tps->chip); + if (status < 0) + dev_err(&client->dev, "can't add gpiochip, err %d\n", + status); + else if (board->setup) { + status = board->setup(client, board->context); + if (status < 0) { + dev_dbg(&client->dev, + "board %s %s err %d\n", + "setup", client->name, status); + status = 0; + } + } + } + return 0; fail1: kfree(tps); diff --git a/include/linux/i2c/tps65010.h b/include/linux/i2c/tps65010.h index 7021635ed6a0..918c5354d9b8 100644 --- a/include/linux/i2c/tps65010.h +++ b/include/linux/i2c/tps65010.h @@ -152,5 +152,35 @@ extern int tps65010_config_vregs1(unsigned value); */ extern int tps65013_set_low_pwr(unsigned mode); + +struct i2c_client; + +/** + * struct tps65010_board - packages GPIO and LED lines + * @base: the GPIO number to assign to GPIO-1 + * @outmask: bit (N-1) is set to allow GPIO-N to be used as an + * (open drain) output + * @setup: optional callback issued once the GPIOs are valid + * @teardown: optional callback issued before the GPIOs are invalidated + * @context: optional parameter passed to setup() and teardown() + * + * Board data may be used to package the GPIO (and LED) lines for use + * in by the generic GPIO and LED frameworks. The first four GPIOs + * starting at gpio_base are GPIO1..GPIO4. The next two are LED1/nPG + * and LED2 (with hardware blinking capability, not currently exposed). + * + * The @setup callback may be used with the kind of board-specific glue + * which hands the (now-valid) GPIOs to other drivers, or which puts + * devices in their initial states using these GPIOs. + */ +struct tps65010_board { + int base; + unsigned outmask; + + int (*setup)(struct i2c_client *client, void *context); + int (*teardown)(struct i2c_client *client, void *context); + void *context; +}; + #endif /* __LINUX_I2C_TPS65010_H */ -- cgit v1.2.3-59-g8ed1b From d94577d5a581fe55c46b5b82eee733b8d053db19 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 28 Feb 2008 22:09:15 -0800 Subject: ARM: OMAP: Use gpiolib with tps65010 for OSK 5912 Convert OSK board to use new tps65010 gpiolib support. This includes moving its LED support from leds-osk to gpio-leds, giving more trigger options and a net platform code shrink. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-osk.c | 108 ++++++++++++++++++++++------------ arch/arm/mach-omap1/leds-osk.c | 80 +------------------------ include/asm-arm/arch-omap/board-osk.h | 11 ++++ 3 files changed, 82 insertions(+), 117 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index dd9ece8f409f..4f9baba7d893 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -183,11 +184,80 @@ static struct platform_device *osk5912_devices[] __initdata = { &osk5912_mcbsp1_device, }; +static struct gpio_led tps_leds[] = { + /* NOTE: D9 and D2 have hardware blink support. + * Also, D9 requires non-battery power. + */ + { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", }, + { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", }, + { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1, + .default_trigger = "heartbeat", }, +}; + +static struct gpio_led_platform_data tps_leds_data = { + .num_leds = 3, + .leds = tps_leds, +}; + +static struct platform_device osk5912_tps_leds = { + .name = "leds-gpio", + .id = 0, + .dev.platform_data = &tps_leds_data, +}; + +static int osk_tps_setup(struct i2c_client *client, void *context) +{ + /* Set GPIO 1 HIGH to disable VBUS power supply; + * OHCI driver powers it up/down as needed. + */ + gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en"); + gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1); + + /* Set GPIO 2 high so LED D3 is off by default */ + tps65010_set_gpio_out_value(GPIO2, HIGH); + + /* Set GPIO 3 low to take ethernet out of reset */ + gpio_request(OSK_TPS_GPIO_LAN_RESET, "smc_reset"); + gpio_direction_output(OSK_TPS_GPIO_LAN_RESET, 0); + + /* GPIO4 is VDD_DSP */ + gpio_request(OSK_TPS_GPIO_DSP_PWR_EN, "dsp_power"); + gpio_direction_output(OSK_TPS_GPIO_DSP_PWR_EN, 1); + /* REVISIT if DSP support isn't configured, power it off ... */ + + /* Let LED1 (D9) blink; leds-gpio may override it */ + tps65010_set_led(LED1, BLINK); + + /* Set LED2 off by default */ + tps65010_set_led(LED2, OFF); + + /* Enable LOW_PWR handshake */ + tps65010_set_low_pwr(ON); + + /* Switch VLDO2 to 3.0V for AIC23 */ + tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V + | TPS_LDO1_ENABLE); + + /* register these three LEDs */ + osk5912_tps_leds.dev.parent = &client->dev; + platform_device_register(&osk5912_tps_leds); + + return 0; +} + +static struct tps65010_board tps_board = { + .base = OSK_TPS_GPIO_BASE, + .outmask = 0x0f, + .setup = osk_tps_setup, +}; + static struct i2c_board_info __initdata osk_i2c_board_info[] = { { I2C_BOARD_INFO("tps65010", 0x48), .type = "tps65010", .irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)), + .platform_data = &tps_board, + }, /* TODO when driver support is ready: * - aic23 audio chip at 0x1a @@ -488,44 +558,6 @@ static void __init osk_map_io(void) omap1_map_common_io(); } -#ifdef CONFIG_TPS65010 -static int __init osk_tps_init(void) -{ - if (!machine_is_omap_osk()) - return 0; - - /* Let LED1 (D9) blink */ - tps65010_set_led(LED1, BLINK); - - /* Disable LED 2 (D2) */ - tps65010_set_led(LED2, OFF); - - /* Set GPIO 1 HIGH to disable VBUS power supply; - * OHCI driver powers it up/down as needed. - */ - tps65010_set_gpio_out_value(GPIO1, HIGH); - - /* Set GPIO 2 low to turn on LED D3 */ - tps65010_set_gpio_out_value(GPIO2, HIGH); - - /* Set GPIO 3 low to take ethernet out of reset */ - tps65010_set_gpio_out_value(GPIO3, LOW); - - /* gpio4 for VDD_DSP */ - /* FIXME send power to DSP iff it's configured */ - - /* Enable LOW_PWR */ - tps65010_set_low_pwr(ON); - - /* Switch VLDO2 to 3.0V for AIC23 */ - tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V - | TPS_LDO1_ENABLE); - - return 0; -} -fs_initcall(osk_tps_init); -#endif - MACHINE_START(OMAP_OSK, "TI-OSK") /* Maintainer: Dirk Behme */ .phys_io = 0xfff00000, diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c index 026685ed461a..754383dde807 100644 --- a/arch/arm/mach-omap1/leds-osk.c +++ b/arch/arm/mach-omap1/leds-osk.c @@ -1,11 +1,9 @@ /* * linux/arch/arm/mach-omap1/leds-osk.c * - * LED driver for OSK, and optionally Mistral QVGA, boards + * LED driver for OSK with optional Mistral QVGA board */ #include -#include -#include #include #include @@ -20,49 +18,11 @@ #define LED_STATE_CLAIMED (1 << 1) static u8 led_state; -#define GREEN_LED (1 << 0) /* TPS65010 LED1 */ -#define AMBER_LED (1 << 1) /* TPS65010 LED2 */ -#define RED_LED (1 << 2) /* TPS65010 GPIO2 */ #define TIMER_LED (1 << 3) /* Mistral board */ #define IDLE_LED (1 << 4) /* Mistral board */ static u8 hw_led_state; -/* TPS65010 leds are changed using i2c -- from a task context. - * Using one of these for the "idle" LED would be impractical... - */ -#define TPS_LEDS (GREEN_LED | RED_LED | AMBER_LED) - -static u8 tps_leds_change; - -static void tps_work(struct work_struct *unused) -{ - for (;;) { - u8 leds; - - local_irq_disable(); - leds = tps_leds_change; - tps_leds_change = 0; - local_irq_enable(); - - if (!leds) - break; - - /* careful: the set_led() value is on/off/blink */ - if (leds & GREEN_LED) - tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED)); - if (leds & AMBER_LED) - tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED)); - - /* the gpio led doesn't have that issue */ - if (leds & RED_LED) - tps65010_set_gpio_out_value(GPIO2, - !(hw_led_state & RED_LED)); - } -} - -static DECLARE_WORK(work, tps_work); - #ifdef CONFIG_OMAP_OSK_MISTRAL /* For now, all system indicators require the Mistral board, since that @@ -112,7 +72,6 @@ void osk_leds_event(led_event_t evt) case led_stop: led_state &= ~LED_STATE_ENABLED; hw_led_state = 0; - /* NOTE: work may still be pending!! */ break; case led_claim: @@ -145,48 +104,11 @@ void osk_leds_event(led_event_t evt) #endif /* CONFIG_OMAP_OSK_MISTRAL */ - /* "green" == tps LED1 (leftmost, normally power-good) - * works only with DC adapter, not on battery power! - */ - case led_green_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= GREEN_LED; - break; - case led_green_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~GREEN_LED; - break; - - /* "amber" == tps LED2 (middle) */ - case led_amber_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= AMBER_LED; - break; - case led_amber_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~AMBER_LED; - break; - - /* "red" == LED on tps gpio3 (rightmost) */ - case led_red_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= RED_LED; - break; - case led_red_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~RED_LED; - break; - default: break; } leds ^= hw_led_state; - leds &= TPS_LEDS; - if (leds && (led_state & LED_STATE_CLAIMED)) { - tps_leds_change |= leds; - schedule_work(&work); - } done: local_irq_restore(flags); diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h index 2b1a8a4fe44e..94926090e475 100644 --- a/include/asm-arm/arch-omap/board-osk.h +++ b/include/asm-arm/arch-omap/board-osk.h @@ -32,5 +32,16 @@ /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ #define OMAP_OSK_ETHR_START 0x04800300 +/* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with + * alternate pin configurations for hardware-controlled blinking. + */ +#define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) +# define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0) +# define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1) +# define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2) +# define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3) +# define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4) +# define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5) + #endif /* __ASM_ARCH_OMAP_OSK_H */ -- cgit v1.2.3-59-g8ed1b From 7d7f665d5dac8d19f2fcb56baea09c59a3f861be Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 25 Jan 2008 00:42:48 -0800 Subject: ARM: OMAP: Allow registering pin mux function This patch changes pin multiplexing init to allow registering custom function. The omap_cfg_reg() func will be split into omap processor specific functions in later patch. This is done to make adding omap3 pin multiplexing easier. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mux.c | 21 ++++++++++++++++++--- arch/arm/mach-omap2/mux.c | 21 +++++++++++++++++++-- arch/arm/plat-omap/mux.c | 30 ++++++++++++++++-------------- include/asm-arm/arch-omap/mux.h | 8 +++++++- 4 files changed, 60 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 52c70e5fcf65..d74f6798d081 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -32,6 +32,8 @@ #ifdef CONFIG_OMAP_MUX +static struct omap_mux_cfg arch_mux_cfg; + #ifdef CONFIG_ARCH_OMAP730 struct pin_config __initdata_or_module omap730_pins[] = { MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) @@ -310,18 +312,31 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) }; #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ +int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) +{ + return 0; +} + int __init omap1_mux_init(void) { #ifdef CONFIG_ARCH_OMAP730 - omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins)); + if (cpu_is_omap730()) { + arch_mux_cfg.pins = omap730_pins; + arch_mux_cfg.size = ARRAY_SIZE(omap730_pins); + arch_mux_cfg.cfg_reg = omap1_cfg_reg; + } #endif #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) - omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins)); + if (cpu_is_omap15xx() || cpu_is_omap16xx()) { + arch_mux_cfg.pins = omap1xxx_pins; + arch_mux_cfg.size = ARRAY_SIZE(omap1xxx_pins); + arch_mux_cfg.cfg_reg = omap1_cfg_reg; + } #endif - return 0; + return omap_mux_register(&arch_mux_cfg); } #endif diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 05750975d746..351baab0503a 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -32,6 +32,8 @@ #ifdef CONFIG_OMAP_MUX +static struct omap_mux_cfg arch_mux_cfg; + /* NOTE: See mux.h for the enumeration */ struct pin_config __initdata_or_module omap24xx_pins[] = { @@ -169,10 +171,25 @@ MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) }; -int __init omap2_mux_init(void) +#ifdef CONFIG_ARCH_OMAP24XX +int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) { - omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins)); return 0; } +#endif + +int __init omap2_mux_init(void) +{ + +#ifdef CONFIG_ARCH_OMAP24XX + if (cpu_is_omap24xx()) { + arch_mux_cfg.pins = omap24xx_pins; + arch_mux_cfg.size = ARRAY_SIZE(omap24xx_pins); + arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; + } +#endif + + return omap_mux_register(&arch_mux_cfg); +} #endif diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 75211f20ccb3..d881379111e1 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c @@ -36,17 +36,17 @@ #define OMAP24XX_PULL_ENA (1 << 3) #define OMAP24XX_PULL_UP (1 << 4) -static struct pin_config * pin_table; -static unsigned long pin_table_sz; +static struct omap_mux_cfg *mux_cfg; -extern struct pin_config * omap730_pins; -extern struct pin_config * omap1xxx_pins; -extern struct pin_config * omap24xx_pins; - -int __init omap_mux_register(struct pin_config * pins, unsigned long size) +int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) { - pin_table = pins; - pin_table_sz = size; + if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0 + || !arch_mux_cfg->cfg_reg) { + printk(KERN_ERR "Invalid pin table\n"); + return -EINVAL; + } + + mux_cfg = arch_mux_cfg; return 0; } @@ -64,17 +64,19 @@ int __init_or_module omap_cfg_reg(const unsigned long index) pull_orig = 0, pull = 0; unsigned int mask, warn = 0; - if (!pin_table) - BUG(); + if (mux_cfg == NULL) { + printk(KERN_ERR "Pin mux table not initialized\n"); + return -ENODEV; + } - if (index >= pin_table_sz) { + if (index >= mux_cfg->size) { printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", - index, pin_table_sz); + index, mux_cfg->size); dump_stack(); return -ENODEV; } - cfg = (struct pin_config *)&pin_table[index]; + cfg = (struct pin_config *)&mux_cfg->pins[index]; if (cpu_is_omap24xx()) { u8 reg = 0; diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index b8fff50e6a87..0edc6ce91b33 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -559,11 +559,17 @@ enum omap24xx_index { B13_24XX_KBC6, }; +struct omap_mux_cfg { + struct pin_config *pins; + unsigned long size; + int (*cfg_reg)(const struct pin_config *cfg); +}; + #ifdef CONFIG_OMAP_MUX /* setup pin muxing in Linux */ extern int omap1_mux_init(void); extern int omap2_mux_init(void); -extern int omap_mux_register(struct pin_config * pins, unsigned long size); +extern int omap_mux_register(struct omap_mux_cfg *); extern int omap_cfg_reg(unsigned long reg_cfg); #else /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ -- cgit v1.2.3-59-g8ed1b From f7337a199acffa9f12fa9d88253d33bfb56ef14a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 20 Mar 2008 16:56:26 +0200 Subject: ARM: OMAP2: Add new pin multiplexing configurations Add new pin multiplexing configurations Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mux.c | 44 +++++++++++++++++++++++++++++++++++++--- include/asm-arm/arch-omap/mux.h | 45 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 84 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 71cff46a8b71..5cba3a2a2392 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -79,7 +79,12 @@ MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) +MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1) MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) +MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1) +MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1) +MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1) +MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1) MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) @@ -104,9 +109,6 @@ MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) -/* TSC IRQ */ -MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) - /* UART3 */ MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) @@ -169,6 +171,42 @@ MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1) MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) +/* 2430 USB */ +MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1) +MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1) +MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1) +MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1) +MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1) +MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1) +MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1) +MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1) +MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1) +MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1) +MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1) + +/* 2430 HS-USB */ +MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1) +MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1) +MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1) +MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1) +MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1) +MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1) +MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1) +MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1) +MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1) +MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1) +MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1) +MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) + +/* 2430 McBSP */ +MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) +MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) +MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) +MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1) +MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1) +MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) +MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) +MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) }; #ifdef CONFIG_ARCH_OMAP24XX diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 0edc6ce91b33..68dd93685f69 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -469,7 +469,12 @@ enum omap24xx_index { AA8_242X_GPIO58, Y20_24XX_GPIO60, W4__24XX_GPIO74, + N15_24XX_GPIO85, M15_24XX_GPIO92, + P20_24XX_GPIO93, + P18_24XX_GPIO95, + M18_24XX_GPIO96, + L14_24XX_GPIO97, J15_24XX_GPIO99, V14_24XX_GPIO117, P14_24XX_GPIO125, @@ -494,8 +499,6 @@ enum omap24xx_index { D3_242X_DMAREQ4, E3_242X_DMAREQ5, - P20_24XX_TSC_IRQ, - /* UART3 */ K15_24XX_UART3_TX, K14_24XX_UART3_RX, @@ -557,6 +560,44 @@ enum omap24xx_index { B3__24XX_KBR5, AA4_24XX_KBC2, B13_24XX_KBC6, + + /* 2430 USB */ + AD9_2430_USB0_PUEN, + Y11_2430_USB0_VP, + AD7_2430_USB0_VM, + AE7_2430_USB0_RCV, + AD4_2430_USB0_TXEN, + AF9_2430_USB0_SE0, + AE6_2430_USB0_DAT, + AD24_2430_USB1_SE0, + AB24_2430_USB1_RCV, + Y25_2430_USB1_TXEN, + AA26_2430_USB1_DAT, + + /* 2430 HS-USB */ + AD9_2430_USB0HS_DATA3, + Y11_2430_USB0HS_DATA4, + AD7_2430_USB0HS_DATA5, + AE7_2430_USB0HS_DATA6, + AD4_2430_USB0HS_DATA2, + AF9_2430_USB0HS_DATA0, + AE6_2430_USB0HS_DATA1, + AE8_2430_USB0HS_CLK, + AD8_2430_USB0HS_DIR, + AE5_2430_USB0HS_STP, + AE9_2430_USB0HS_NXT, + AC7_2430_USB0HS_DATA7, + + /* 2430 McBSP */ + AC10_2430_MCBSP2_FSX, + AD16_2430_MCBSP2_CLX, + AE13_2430_MCBSP2_DX, + AD13_2430_MCBSP2_DR, + AC10_2430_MCBSP2_FSX_OFF, + AD16_2430_MCBSP2_CLX_OFF, + AE13_2430_MCBSP2_DX_OFF, + AD13_2430_MCBSP2_DR_OFF, + }; struct omap_mux_cfg { -- cgit v1.2.3-59-g8ed1b From 9330899e0f878ff3b7a23b856de8bbb52c9c04fd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 24 Jan 2008 17:24:15 -0800 Subject: ARM: OMAP2: Clean-up mux code Misc clean-up for the mux code and remove some unnecessary ifdefs. Patch changes debug function so it can be used on both 24xx and 34xx. Changes are mostly for omap2, but patch also cleans up some omap1 and common mux code. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mux.c | 28 +++++++++-------- arch/arm/mach-omap2/mux.c | 69 +++++++++++++++++++++++++---------------- arch/arm/plat-omap/mux.c | 4 +-- include/asm-arm/arch-omap/mux.h | 13 ++------ 4 files changed, 63 insertions(+), 51 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index cf3bdc00cfdb..e207bf7cb853 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -3,9 +3,9 @@ * * OMAP1 pin multiplexing configurations * - * Copyright (C) 2003 - 2005 Nokia Corporation + * Copyright (C) 2003 - 2008 Nokia Corporation * - * Written by Tony Lindgren + * Written by Tony Lindgren * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,7 +35,7 @@ static struct omap_mux_cfg arch_mux_cfg; #ifdef CONFIG_ARCH_OMAP730 -struct pin_config __initdata_or_module omap730_pins[] = { +static struct pin_config __initdata_or_module omap730_pins[] = { MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) @@ -51,10 +51,14 @@ MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0) MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) }; -#endif +#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins) +#else +#define omap730_pins NULL +#define OMAP730_PINS_SZ 0 +#endif /* CONFIG_ARCH_OMAP730 */ #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) -struct pin_config __initdata_or_module omap1xxx_pins[] = { +static struct pin_config __initdata_or_module omap1xxx_pins[] = { /* * description mux mode mux pull pull pull pu_pd pu dbg * reg offset mode reg bit ena reg @@ -308,8 +312,11 @@ MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0) MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0) MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0) MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) - }; +#define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins) +#else +#define omap1xxx_pins NULL +#define OMAP1XXX_PINS_SZ 0 #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) @@ -422,22 +429,17 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) int __init omap1_mux_init(void) { - -#ifdef CONFIG_ARCH_OMAP730 if (cpu_is_omap730()) { arch_mux_cfg.pins = omap730_pins; - arch_mux_cfg.size = ARRAY_SIZE(omap730_pins); + arch_mux_cfg.size = OMAP730_PINS_SZ; arch_mux_cfg.cfg_reg = omap1_cfg_reg; } -#endif -#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap15xx() || cpu_is_omap16xx()) { arch_mux_cfg.pins = omap1xxx_pins; - arch_mux_cfg.size = ARRAY_SIZE(omap1xxx_pins); + arch_mux_cfg.size = OMAP1XXX_PINS_SZ; arch_mux_cfg.cfg_reg = omap1_cfg_reg; } -#endif return omap_mux_register(&arch_mux_cfg); } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 5cba3a2a2392..0cf7562ff88f 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -1,11 +1,12 @@ /* * linux/arch/arm/mach-omap2/mux.c * - * OMAP1 pin multiplexing configurations + * OMAP2 pin multiplexing configurations * - * Copyright (C) 2003 - 2005 Nokia Corporation + * Copyright (C) 2004 - 2008 Texas Instruments Inc. + * Copyright (C) 2003 - 2008 Nokia Corporation * - * Written by Tony Lindgren + * Written by Tony Lindgren * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,7 +37,8 @@ static struct omap_mux_cfg arch_mux_cfg; /* NOTE: See mux.h for the enumeration */ -struct pin_config __initdata_or_module omap24xx_pins[] = { +#ifdef CONFIG_ARCH_OMAP24XX +static struct pin_config __initdata_or_module omap24xx_pins[] = { /* * description mux mux pull pull debug * offset mode ena type @@ -209,54 +211,69 @@ MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) }; -#ifdef CONFIG_ARCH_OMAP24XX +#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) + +#else +#define omap24xx_pins NULL +#define OMAP24XX_PINS_SZ 0 +#endif /* CONFIG_ARCH_OMAP24XX */ #define OMAP24XX_L4_BASE 0x48000000 #define OMAP24XX_PULL_ENA (1 << 3) #define OMAP24XX_PULL_UP (1 << 4) /* REVISIT: Convert this code to use ctrl_{read,write}_reg */ +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) +void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) +{ + u16 orig; + u8 warn = 0, debug = 0; + + orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); + +#ifdef CONFIG_OMAP_MUX_DEBUG + debug = cfg->debug; +#endif + warn = (orig != reg); + if (debug || warn) + printk(KERN_WARNING + "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", + cfg->name, omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg)); +} +#else +#define omap2_cfg_debug(x, y) do {} while (0) +#endif + +#ifdef CONFIG_ARCH_OMAP24XX int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) { + static DEFINE_SPINLOCK(mux_spin_lock); + unsigned long flags; u8 reg = 0; - unsigned int warn = 0; + spin_lock_irqsave(&mux_spin_lock, flags); reg |= cfg->mask & 0x7; if (cfg->pull_val) reg |= OMAP24XX_PULL_ENA; - if(cfg->pu_pd_val) + if (cfg->pu_pd_val) reg |= OMAP24XX_PULL_UP; -#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) - { - u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); - u8 debug = 0; - -#ifdef CONFIG_OMAP_MUX_DEBUG - debug = cfg->debug; -#endif - warn = (orig != reg); - if (debug || warn) - printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", - cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg, - orig, reg); - } -#endif + omap2_cfg_debug(cfg, reg); omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); + spin_unlock_irqrestore(&mux_spin_lock, flags); return 0; } +#else +#define omap24xx_cfg_reg 0 #endif int __init omap2_mux_init(void) { - -#ifdef CONFIG_ARCH_OMAP24XX if (cpu_is_omap24xx()) { arch_mux_cfg.pins = omap24xx_pins; - arch_mux_cfg.size = ARRAY_SIZE(omap24xx_pins); + arch_mux_cfg.size = OMAP24XX_PINS_SZ; arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; } -#endif return omap_mux_register(&arch_mux_cfg); } diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 4de18b9ffb16..6f3f459731c8 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c @@ -3,9 +3,9 @@ * * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h * - * Copyright (C) 2003 - 2005 Nokia Corporation + * Copyright (C) 2003 - 2008 Nokia Corporation * - * Written by Tony Lindgren + * Written by Tony Lindgren * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 68dd93685f69..ff9a5b5575fd 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -4,9 +4,10 @@ * Table of the Omap register configurations for the FUNC_MUX and * PULL_DWN combinations. * - * Copyright (C) 2003 - 2005 Nokia Corporation + * Copyright (C) 2004 - 2008 Texas Instruments Inc. + * Copyright (C) 2003 - 2008 Nokia Corporation * - * Written by Tony Lindgren + * Written by Tony Lindgren * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,14 +28,6 @@ * - W8 = ball * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 * - MMC2_DAT0 = function - * - * Change log: - * Added entry for the I2C interface. (02Feb 2004) - * Copyright (C) 2004 Texas Instruments - * - * Added entry for the keypad and uwire CS1. (09Mar 2004) - * Copyright (C) 2004 Texas Instruments - * */ #ifndef __ASM_ARCH_MUX_H -- cgit v1.2.3-59-g8ed1b From 69d88a00a240fbed07fb6943c862ea3188e9097d Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 18 Mar 2008 10:02:50 +0200 Subject: ARM: OMAP2: Add common register access for 24xx and 34xx This patch adds common register access for 24xx and 34xx power and clock management in order to share code between 24xx and 34xx. Only change USB platform init code to use new register access, other access will be changed in later patches. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 4 +- arch/arm/mach-omap2/cm-regbits-24xx.h | 401 +++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cm.h | 124 ++++++++++ arch/arm/mach-omap2/control.c | 74 ++++++ arch/arm/mach-omap2/prcm-common.h | 317 ++++++++++++++++++++++++++ arch/arm/mach-omap2/prm-regbits-24xx.h | 279 +++++++++++++++++++++++ arch/arm/mach-omap2/prm.h | 316 ++++++++++++++++++++++++++ arch/arm/mach-omap2/sdrc.h | 58 +++++ arch/arm/plat-omap/usb.c | 67 ++++-- include/asm-arm/arch-omap/control.h | 191 ++++++++++++++++ include/asm-arm/arch-omap/sdrc.h | 75 ++++++ include/asm-arm/arch-omap/usb.h | 5 +- 12 files changed, 1889 insertions(+), 22 deletions(-) create mode 100644 arch/arm/mach-omap2/cm-regbits-24xx.h create mode 100644 arch/arm/mach-omap2/cm.h create mode 100644 arch/arm/mach-omap2/control.c create mode 100644 arch/arm/mach-omap2/prcm-common.h create mode 100644 arch/arm/mach-omap2/prm-regbits-24xx.h create mode 100644 arch/arm/mach-omap2/prm.h create mode 100644 arch/arm/mach-omap2/sdrc.h create mode 100644 include/asm-arm/arch-omap/control.h create mode 100644 include/asm-arm/arch-omap/sdrc.h (limited to 'include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ac343ec578c2..b9313c9c7420 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,8 +3,8 @@ # # Common support -obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \ - serial.o gpmc.o timer-gp.o +obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \ + devices.o serial.o gpmc.o timer-gp.o # Power Management obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h new file mode 100644 index 000000000000..20ac38100678 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -0,0 +1,401 @@ +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H + +/* + * OMAP24XX Clock Management register bits + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "cm.h" + +/* Bits shared between registers */ + +/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ +#define OMAP24XX_EN_CAM_SHIFT 31 +#define OMAP24XX_EN_CAM (1 << 31) +#define OMAP24XX_EN_WDT4_SHIFT 29 +#define OMAP24XX_EN_WDT4 (1 << 29) +#define OMAP2420_EN_WDT3_SHIFT 28 +#define OMAP2420_EN_WDT3 (1 << 28) +#define OMAP24XX_EN_MSPRO_SHIFT 27 +#define OMAP24XX_EN_MSPRO (1 << 27) +#define OMAP24XX_EN_FAC_SHIFT 25 +#define OMAP24XX_EN_FAC (1 << 25) +#define OMAP2420_EN_EAC_SHIFT 24 +#define OMAP2420_EN_EAC (1 << 24) +#define OMAP24XX_EN_HDQ_SHIFT 23 +#define OMAP24XX_EN_HDQ (1 << 23) +#define OMAP2420_EN_I2C2_SHIFT 20 +#define OMAP2420_EN_I2C2 (1 << 20) +#define OMAP2420_EN_I2C1_SHIFT 19 +#define OMAP2420_EN_I2C1 (1 << 19) + +/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ +#define OMAP2430_EN_MCBSP5_SHIFT 5 +#define OMAP2430_EN_MCBSP5 (1 << 5) +#define OMAP2430_EN_MCBSP4_SHIFT 4 +#define OMAP2430_EN_MCBSP4 (1 << 4) +#define OMAP2430_EN_MCBSP3_SHIFT 3 +#define OMAP2430_EN_MCBSP3 (1 << 3) +#define OMAP24XX_EN_SSI_SHIFT 1 +#define OMAP24XX_EN_SSI (1 << 1) + +/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ +#define OMAP24XX_EN_MPU_WDT_SHIFT 3 +#define OMAP24XX_EN_MPU_WDT (1 << 3) + +/* Bits specific to each register */ + +/* CM_IDLEST_MPU */ +/* 2430 only */ +#define OMAP2430_ST_MPU (1 << 0) + +/* CM_CLKSEL_MPU */ +#define OMAP24XX_CLKSEL_MPU_SHIFT 0 +#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) + +/* CM_CLKSTCTRL_MPU */ +#define OMAP24XX_AUTOSTATE_MPU (1 << 0) + +/* CM_FCLKEN1_CORE specific bits*/ +#define OMAP24XX_EN_TV_SHIFT 2 +#define OMAP24XX_EN_TV (1 << 2) +#define OMAP24XX_EN_DSS2_SHIFT 1 +#define OMAP24XX_EN_DSS2 (1 << 1) +#define OMAP24XX_EN_DSS1_SHIFT 0 +#define OMAP24XX_EN_DSS1 (1 << 0) + +/* CM_FCLKEN2_CORE specific bits */ +#define OMAP2430_EN_I2CHS2_SHIFT 20 +#define OMAP2430_EN_I2CHS2 (1 << 20) +#define OMAP2430_EN_I2CHS1_SHIFT 19 +#define OMAP2430_EN_I2CHS1 (1 << 19) +#define OMAP2430_EN_MMCHSDB2_SHIFT 17 +#define OMAP2430_EN_MMCHSDB2 (1 << 17) +#define OMAP2430_EN_MMCHSDB1_SHIFT 16 +#define OMAP2430_EN_MMCHSDB1 (1 << 16) + +/* CM_ICLKEN1_CORE specific bits */ +#define OMAP24XX_EN_MAILBOXES_SHIFT 30 +#define OMAP24XX_EN_MAILBOXES (1 << 30) +#define OMAP24XX_EN_DSS_SHIFT 0 +#define OMAP24XX_EN_DSS (1 << 0) + +/* CM_ICLKEN2_CORE specific bits */ + +/* CM_ICLKEN3_CORE */ +/* 2430 only */ +#define OMAP2430_EN_SDRC_SHIFT 2 +#define OMAP2430_EN_SDRC (1 << 2) + +/* CM_ICLKEN4_CORE */ +#define OMAP24XX_EN_PKA_SHIFT 4 +#define OMAP24XX_EN_PKA (1 << 4) +#define OMAP24XX_EN_AES_SHIFT 3 +#define OMAP24XX_EN_AES (1 << 3) +#define OMAP24XX_EN_RNG_SHIFT 2 +#define OMAP24XX_EN_RNG (1 << 2) +#define OMAP24XX_EN_SHA_SHIFT 1 +#define OMAP24XX_EN_SHA (1 << 1) +#define OMAP24XX_EN_DES_SHIFT 0 +#define OMAP24XX_EN_DES (1 << 0) + +/* CM_IDLEST1_CORE specific bits */ +#define OMAP24XX_ST_MAILBOXES (1 << 30) +#define OMAP24XX_ST_WDT4 (1 << 29) +#define OMAP2420_ST_WDT3 (1 << 28) +#define OMAP24XX_ST_MSPRO (1 << 27) +#define OMAP24XX_ST_FAC (1 << 25) +#define OMAP2420_ST_EAC (1 << 24) +#define OMAP24XX_ST_HDQ (1 << 23) +#define OMAP24XX_ST_I2C2 (1 << 20) +#define OMAP24XX_ST_I2C1 (1 << 19) +#define OMAP24XX_ST_MCBSP2 (1 << 16) +#define OMAP24XX_ST_MCBSP1 (1 << 15) +#define OMAP24XX_ST_DSS (1 << 0) + +/* CM_IDLEST2_CORE */ +#define OMAP2430_ST_MCBSP5 (1 << 5) +#define OMAP2430_ST_MCBSP4 (1 << 4) +#define OMAP2430_ST_MCBSP3 (1 << 3) +#define OMAP24XX_ST_SSI (1 << 1) + +/* CM_IDLEST3_CORE */ +/* 2430 only */ +#define OMAP2430_ST_SDRC (1 << 2) + +/* CM_IDLEST4_CORE */ +#define OMAP24XX_ST_PKA (1 << 4) +#define OMAP24XX_ST_AES (1 << 3) +#define OMAP24XX_ST_RNG (1 << 2) +#define OMAP24XX_ST_SHA (1 << 1) +#define OMAP24XX_ST_DES (1 << 0) + +/* CM_AUTOIDLE1_CORE */ +#define OMAP24XX_AUTO_CAM (1 << 31) +#define OMAP24XX_AUTO_MAILBOXES (1 << 30) +#define OMAP24XX_AUTO_WDT4 (1 << 29) +#define OMAP2420_AUTO_WDT3 (1 << 28) +#define OMAP24XX_AUTO_MSPRO (1 << 27) +#define OMAP2420_AUTO_MMC (1 << 26) +#define OMAP24XX_AUTO_FAC (1 << 25) +#define OMAP2420_AUTO_EAC (1 << 24) +#define OMAP24XX_AUTO_HDQ (1 << 23) +#define OMAP24XX_AUTO_UART2 (1 << 22) +#define OMAP24XX_AUTO_UART1 (1 << 21) +#define OMAP24XX_AUTO_I2C2 (1 << 20) +#define OMAP24XX_AUTO_I2C1 (1 << 19) +#define OMAP24XX_AUTO_MCSPI2 (1 << 18) +#define OMAP24XX_AUTO_MCSPI1 (1 << 17) +#define OMAP24XX_AUTO_MCBSP2 (1 << 16) +#define OMAP24XX_AUTO_MCBSP1 (1 << 15) +#define OMAP24XX_AUTO_GPT12 (1 << 14) +#define OMAP24XX_AUTO_GPT11 (1 << 13) +#define OMAP24XX_AUTO_GPT10 (1 << 12) +#define OMAP24XX_AUTO_GPT9 (1 << 11) +#define OMAP24XX_AUTO_GPT8 (1 << 10) +#define OMAP24XX_AUTO_GPT7 (1 << 9) +#define OMAP24XX_AUTO_GPT6 (1 << 8) +#define OMAP24XX_AUTO_GPT5 (1 << 7) +#define OMAP24XX_AUTO_GPT4 (1 << 6) +#define OMAP24XX_AUTO_GPT3 (1 << 5) +#define OMAP24XX_AUTO_GPT2 (1 << 4) +#define OMAP2420_AUTO_VLYNQ (1 << 3) +#define OMAP24XX_AUTO_DSS (1 << 0) + +/* CM_AUTOIDLE2_CORE */ +#define OMAP2430_AUTO_MDM_INTC (1 << 11) +#define OMAP2430_AUTO_GPIO5 (1 << 10) +#define OMAP2430_AUTO_MCSPI3 (1 << 9) +#define OMAP2430_AUTO_MMCHS2 (1 << 8) +#define OMAP2430_AUTO_MMCHS1 (1 << 7) +#define OMAP2430_AUTO_USBHS (1 << 6) +#define OMAP2430_AUTO_MCBSP5 (1 << 5) +#define OMAP2430_AUTO_MCBSP4 (1 << 4) +#define OMAP2430_AUTO_MCBSP3 (1 << 3) +#define OMAP24XX_AUTO_UART3 (1 << 2) +#define OMAP24XX_AUTO_SSI (1 << 1) +#define OMAP24XX_AUTO_USB (1 << 0) + +/* CM_AUTOIDLE3_CORE */ +#define OMAP24XX_AUTO_SDRC (1 << 2) +#define OMAP24XX_AUTO_GPMC (1 << 1) +#define OMAP24XX_AUTO_SDMA (1 << 0) + +/* CM_AUTOIDLE4_CORE */ +#define OMAP24XX_AUTO_PKA (1 << 4) +#define OMAP24XX_AUTO_AES (1 << 3) +#define OMAP24XX_AUTO_RNG (1 << 2) +#define OMAP24XX_AUTO_SHA (1 << 1) +#define OMAP24XX_AUTO_DES (1 << 0) + +/* CM_CLKSEL1_CORE */ +#define OMAP24XX_CLKSEL_USB_SHIFT 25 +#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) +#define OMAP24XX_CLKSEL_SSI_SHIFT 20 +#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) +#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 +#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) +#define OMAP24XX_CLKSEL_DSS2_SHIFT 13 +#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) +#define OMAP24XX_CLKSEL_DSS1_SHIFT 8 +#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) +#define OMAP24XX_CLKSEL_L4_SHIFT 5 +#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) +#define OMAP24XX_CLKSEL_L3_SHIFT 0 +#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) + +/* CM_CLKSEL2_CORE */ +#define OMAP24XX_CLKSEL_GPT12_SHIFT 22 +#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) +#define OMAP24XX_CLKSEL_GPT11_SHIFT 20 +#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) +#define OMAP24XX_CLKSEL_GPT10_SHIFT 18 +#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) +#define OMAP24XX_CLKSEL_GPT9_SHIFT 16 +#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) +#define OMAP24XX_CLKSEL_GPT8_SHIFT 14 +#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) +#define OMAP24XX_CLKSEL_GPT7_SHIFT 12 +#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) +#define OMAP24XX_CLKSEL_GPT6_SHIFT 10 +#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) +#define OMAP24XX_CLKSEL_GPT5_SHIFT 8 +#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) +#define OMAP24XX_CLKSEL_GPT4_SHIFT 6 +#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) +#define OMAP24XX_CLKSEL_GPT3_SHIFT 4 +#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) +#define OMAP24XX_CLKSEL_GPT2_SHIFT 2 +#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) + +/* CM_CLKSTCTRL_CORE */ +#define OMAP24XX_AUTOSTATE_DSS (1 << 2) +#define OMAP24XX_AUTOSTATE_L4 (1 << 1) +#define OMAP24XX_AUTOSTATE_L3 (1 << 0) + +/* CM_FCLKEN_GFX */ +#define OMAP24XX_EN_3D_SHIFT 2 +#define OMAP24XX_EN_3D (1 << 2) +#define OMAP24XX_EN_2D_SHIFT 1 +#define OMAP24XX_EN_2D (1 << 1) + +/* CM_ICLKEN_GFX specific bits */ + +/* CM_IDLEST_GFX specific bits */ + +/* CM_CLKSEL_GFX specific bits */ + +/* CM_CLKSTCTRL_GFX */ +#define OMAP24XX_AUTOSTATE_GFX (1 << 0) + +/* CM_FCLKEN_WKUP specific bits */ + +/* CM_ICLKEN_WKUP specific bits */ +#define OMAP2430_EN_ICR_SHIFT 6 +#define OMAP2430_EN_ICR (1 << 6) +#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 +#define OMAP24XX_EN_OMAPCTRL (1 << 5) +#define OMAP24XX_EN_WDT1_SHIFT 4 +#define OMAP24XX_EN_WDT1 (1 << 4) +#define OMAP24XX_EN_32KSYNC_SHIFT 1 +#define OMAP24XX_EN_32KSYNC (1 << 1) + +/* CM_IDLEST_WKUP specific bits */ +#define OMAP2430_ST_ICR (1 << 6) +#define OMAP24XX_ST_OMAPCTRL (1 << 5) +#define OMAP24XX_ST_WDT1 (1 << 4) +#define OMAP24XX_ST_MPU_WDT (1 << 3) +#define OMAP24XX_ST_32KSYNC (1 << 1) + +/* CM_AUTOIDLE_WKUP */ +#define OMAP24XX_AUTO_OMAPCTRL (1 << 5) +#define OMAP24XX_AUTO_WDT1 (1 << 4) +#define OMAP24XX_AUTO_MPU_WDT (1 << 3) +#define OMAP24XX_AUTO_GPIOS (1 << 2) +#define OMAP24XX_AUTO_32KSYNC (1 << 1) +#define OMAP24XX_AUTO_GPT1 (1 << 0) + +/* CM_CLKSEL_WKUP */ +#define OMAP24XX_CLKSEL_GPT1_SHIFT 0 +#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) + +/* CM_CLKEN_PLL */ +#define OMAP24XX_EN_54M_PLL_SHIFT 6 +#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) +#define OMAP24XX_EN_96M_PLL_SHIFT 2 +#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) +#define OMAP24XX_EN_DPLL_SHIFT 0 +#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) + +/* CM_IDLEST_CKGEN */ +#define OMAP24XX_ST_54M_APLL (1 << 9) +#define OMAP24XX_ST_96M_APLL (1 << 8) +#define OMAP24XX_ST_54M_CLK (1 << 6) +#define OMAP24XX_ST_12M_CLK (1 << 5) +#define OMAP24XX_ST_48M_CLK (1 << 4) +#define OMAP24XX_ST_96M_CLK (1 << 2) +#define OMAP24XX_ST_CORE_CLK_SHIFT 0 +#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) + +/* CM_AUTOIDLE_PLL */ +#define OMAP24XX_AUTO_54M_SHIFT 6 +#define OMAP24XX_AUTO_54M_MASK (0x3 << 6) +#define OMAP24XX_AUTO_96M_SHIFT 2 +#define OMAP24XX_AUTO_96M_MASK (0x3 << 2) +#define OMAP24XX_AUTO_DPLL_SHIFT 0 +#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) + +/* CM_CLKSEL1_PLL */ +#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 +#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) +#define OMAP24XX_APLLS_CLKIN_SHIFT 23 +#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) +#define OMAP24XX_DPLL_MULT_SHIFT 12 +#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) +#define OMAP24XX_DPLL_DIV_SHIFT 8 +#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) +#define OMAP24XX_54M_SOURCE_SHIFT 5 +#define OMAP24XX_54M_SOURCE (1 << 5) +#define OMAP2430_96M_SOURCE_SHIFT 4 +#define OMAP2430_96M_SOURCE (1 << 4) +#define OMAP24XX_48M_SOURCE_SHIFT 3 +#define OMAP24XX_48M_SOURCE (1 << 3) +#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 +#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) + +/* CM_CLKSEL2_PLL */ +#define OMAP24XX_CORE_CLK_SRC_SHIFT 0 +#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) + +/* CM_FCLKEN_DSP */ +#define OMAP2420_EN_IVA_COP_SHIFT 10 +#define OMAP2420_EN_IVA_COP (1 << 10) +#define OMAP2420_EN_IVA_MPU_SHIFT 8 +#define OMAP2420_EN_IVA_MPU (1 << 8) +#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 +#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) + +/* CM_ICLKEN_DSP */ +#define OMAP2420_EN_DSP_IPI_SHIFT 1 +#define OMAP2420_EN_DSP_IPI (1 << 1) + +/* CM_IDLEST_DSP */ +#define OMAP2420_ST_IVA (1 << 8) +#define OMAP2420_ST_IPI (1 << 1) +#define OMAP24XX_ST_DSP (1 << 0) + +/* CM_AUTOIDLE_DSP */ +#define OMAP2420_AUTO_DSP_IPI (1 << 1) + +/* CM_CLKSEL_DSP */ +#define OMAP2420_SYNC_IVA (1 << 13) +#define OMAP2420_CLKSEL_IVA_SHIFT 8 +#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) +#define OMAP24XX_SYNC_DSP (1 << 7) +#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 +#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) +#define OMAP24XX_CLKSEL_DSP_SHIFT 0 +#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) + +/* CM_CLKSTCTRL_DSP */ +#define OMAP2420_AUTOSTATE_IVA (1 << 8) +#define OMAP24XX_AUTOSTATE_DSP (1 << 0) + +/* CM_FCLKEN_MDM */ +/* 2430 only */ +#define OMAP2430_EN_OSC_SHIFT 1 +#define OMAP2430_EN_OSC (1 << 1) + +/* CM_ICLKEN_MDM */ +/* 2430 only */ +#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 +#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) + +/* CM_IDLEST_MDM specific bits */ +/* 2430 only */ + +/* CM_AUTOIDLE_MDM */ +/* 2430 only */ +#define OMAP2430_AUTO_OSC (1 << 1) +#define OMAP2430_AUTO_MDM (1 << 0) + +/* CM_CLKSEL_MDM */ +/* 2430 only */ +#define OMAP2430_SYNC_MDM (1 << 4) +#define OMAP2430_CLKSEL_MDM_SHIFT 0 +#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) + +/* CM_CLKSTCTRL_MDM */ +/* 2430 only */ +#define OMAP2430_AUTOSTATE_MDM (1 << 0) + +#endif diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h new file mode 100644 index 000000000000..8489f3029fed --- /dev/null +++ b/arch/arm/mach-omap2/cm.h @@ -0,0 +1,124 @@ +#ifndef __ARCH_ASM_MACH_OMAP2_CM_H +#define __ARCH_ASM_MACH_OMAP2_CM_H + +/* + * OMAP2/3 Clock Management (CM) register definitions + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "prcm-common.h" + +#ifndef __ASSEMBLER__ +#define OMAP_CM_REGADDR(module, reg) \ + (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) +#else +#define OMAP2420_CM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) +#define OMAP2430_CM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) +#define OMAP34XX_CM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) +#endif + +/* + * Architecture-specific global CM registers + * Use cm_{read,write}_reg() with these registers. + * These registers appear once per CM module. + */ + +#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) +#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) +#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) + +#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific CM registers from CM_BASE + domain offset + * Use cm_{read,write}_mod_reg() with these registers. + * These register offsets generally appear in more than one PRCM submodule. + */ + +/* Common between 24xx and 34xx */ + +#define CM_FCLKEN 0x0000 +#define CM_FCLKEN1 CM_FCLKEN +#define CM_CLKEN CM_FCLKEN +#define CM_ICLKEN 0x0010 +#define CM_ICLKEN1 CM_ICLKEN +#define CM_ICLKEN2 0x0014 +#define CM_ICLKEN3 0x0018 +#define CM_IDLEST 0x0020 +#define CM_IDLEST1 CM_IDLEST +#define CM_IDLEST2 0x0024 +#define CM_AUTOIDLE 0x0030 +#define CM_AUTOIDLE1 CM_AUTOIDLE +#define CM_AUTOIDLE2 0x0034 +#define CM_AUTOIDLE3 0x0038 +#define CM_CLKSEL 0x0040 +#define CM_CLKSEL1 CM_CLKSEL +#define CM_CLKSEL2 0x0044 +#define CM_CLKSTCTRL 0x0048 + + +/* Architecture-specific registers */ + +#define OMAP24XX_CM_FCLKEN2 0x0004 +#define OMAP24XX_CM_ICLKEN4 0x001c +#define OMAP24XX_CM_AUTOIDLE4 0x003c + +#define OMAP2430_CM_IDLEST3 0x0028 + +#define OMAP3430_CM_CLKEN_PLL 0x0004 +#define OMAP3430ES2_CM_CLKEN2 0x0004 +#define OMAP3430ES2_CM_FCLKEN3 0x0008 +#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 +#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 +#define OMAP3430_CM_CLKSEL1 CM_CLKSEL +#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL +#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 +#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 +#define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL +#define OMAP3430_CM_CLKSTST 0x004c +#define OMAP3430ES2_CM_CLKSEL4 0x004c +#define OMAP3430ES2_CM_CLKSEL5 0x0050 +#define OMAP3430_CM_CLKSEL2_EMU 0x0050 +#define OMAP3430_CM_CLKSEL3_EMU 0x0054 + + +/* Clock management domain register get/set */ + +#ifndef __ASSEMBLER__ +static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx) +{ + __raw_writel(val, OMAP_CM_REGADDR(module, idx)); +} + +static inline u32 cm_read_mod_reg(s16 module, s16 idx) +{ + return __raw_readl(OMAP_CM_REGADDR(module, idx)); +} +#endif + +/* CM register bits shared between 24XX and 3430 */ + +/* CM_CLKSEL_GFX */ +#define OMAP_CLKSEL_GFX_SHIFT 0 +#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) + +/* CM_ICLKEN_GFX */ +#define OMAP_EN_GFX_SHIFT 0 +#define OMAP_EN_GFX (1 << 0) + +/* CM_IDLEST_GFX */ +#define OMAP_ST_GFX (1 << 0) + + +#endif diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c new file mode 100644 index 000000000000..a5d86a49c213 --- /dev/null +++ b/arch/arm/mach-omap2/control.c @@ -0,0 +1,74 @@ +/* + * OMAP2/3 System Control Module register access + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include + +#include + +#include + +static u32 omap2_ctrl_base; + +#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \ + + (reg)) + +void omap_ctrl_base_set(u32 base) +{ + omap2_ctrl_base = base; +} + +u32 omap_ctrl_base_get(void) +{ + return omap2_ctrl_base; +} + +u8 omap_ctrl_readb(u16 offset) +{ + return __raw_readb(OMAP_CTRL_REGADDR(offset)); +} + +u16 omap_ctrl_readw(u16 offset) +{ + return __raw_readw(OMAP_CTRL_REGADDR(offset)); +} + +u32 omap_ctrl_readl(u16 offset) +{ + return __raw_readl(OMAP_CTRL_REGADDR(offset)); +} + +void omap_ctrl_writeb(u8 val, u16 offset) +{ + pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val, + (u32)OMAP_CTRL_REGADDR(offset)); + + __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); +} + +void omap_ctrl_writew(u16 val, u16 offset) +{ + pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val, + (u32)OMAP_CTRL_REGADDR(offset)); + + __raw_writew(val, OMAP_CTRL_REGADDR(offset)); +} + +void omap_ctrl_writel(u32 val, u16 offset) +{ + pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val, + (u32)OMAP_CTRL_REGADDR(offset)); + + __raw_writel(val, OMAP_CTRL_REGADDR(offset)); +} + diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h new file mode 100644 index 000000000000..cacb34086e35 --- /dev/null +++ b/arch/arm/mach-omap2/prcm-common.h @@ -0,0 +1,317 @@ +#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H +#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H + +/* + * OMAP2/3 PRCM base and module definitions + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +/* Module offsets from both CM_BASE & PRM_BASE */ + +/* + * Offsets that are the same on 24xx and 34xx + * + * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is + * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. + */ +#define OCP_MOD 0x000 +#define MPU_MOD 0x100 +#define CORE_MOD 0x200 +#define GFX_MOD 0x300 +#define WKUP_MOD 0x400 +#define PLL_MOD 0x500 + + +/* Chip-specific module offsets */ +#define OMAP24XX_DSP_MOD 0x800 + +#define OMAP2430_MDM_MOD 0xc00 + +/* IVA2 module is < base on 3430 */ +#define OMAP3430_IVA2_MOD -0x800 +#define OMAP3430ES2_SGX_MOD GFX_MOD +#define OMAP3430_CCR_MOD PLL_MOD +#define OMAP3430_DSS_MOD 0x600 +#define OMAP3430_CAM_MOD 0x700 +#define OMAP3430_PER_MOD 0x800 +#define OMAP3430_EMU_MOD 0x900 +#define OMAP3430_GR_MOD 0xa00 +#define OMAP3430_NEON_MOD 0xb00 +#define OMAP3430ES2_USBHOST_MOD 0xc00 + + +/* 24XX register bits shared between CM & PRM registers */ + +/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP2420_EN_MMC_SHIFT 26 +#define OMAP2420_EN_MMC (1 << 26) +#define OMAP24XX_EN_UART2_SHIFT 22 +#define OMAP24XX_EN_UART2 (1 << 22) +#define OMAP24XX_EN_UART1_SHIFT 21 +#define OMAP24XX_EN_UART1 (1 << 21) +#define OMAP24XX_EN_MCSPI2_SHIFT 18 +#define OMAP24XX_EN_MCSPI2 (1 << 18) +#define OMAP24XX_EN_MCSPI1_SHIFT 17 +#define OMAP24XX_EN_MCSPI1 (1 << 17) +#define OMAP24XX_EN_MCBSP2_SHIFT 16 +#define OMAP24XX_EN_MCBSP2 (1 << 16) +#define OMAP24XX_EN_MCBSP1_SHIFT 15 +#define OMAP24XX_EN_MCBSP1 (1 << 15) +#define OMAP24XX_EN_GPT12_SHIFT 14 +#define OMAP24XX_EN_GPT12 (1 << 14) +#define OMAP24XX_EN_GPT11_SHIFT 13 +#define OMAP24XX_EN_GPT11 (1 << 13) +#define OMAP24XX_EN_GPT10_SHIFT 12 +#define OMAP24XX_EN_GPT10 (1 << 12) +#define OMAP24XX_EN_GPT9_SHIFT 11 +#define OMAP24XX_EN_GPT9 (1 << 11) +#define OMAP24XX_EN_GPT8_SHIFT 10 +#define OMAP24XX_EN_GPT8 (1 << 10) +#define OMAP24XX_EN_GPT7_SHIFT 9 +#define OMAP24XX_EN_GPT7 (1 << 9) +#define OMAP24XX_EN_GPT6_SHIFT 8 +#define OMAP24XX_EN_GPT6 (1 << 8) +#define OMAP24XX_EN_GPT5_SHIFT 7 +#define OMAP24XX_EN_GPT5 (1 << 7) +#define OMAP24XX_EN_GPT4_SHIFT 6 +#define OMAP24XX_EN_GPT4 (1 << 6) +#define OMAP24XX_EN_GPT3_SHIFT 5 +#define OMAP24XX_EN_GPT3 (1 << 5) +#define OMAP24XX_EN_GPT2_SHIFT 4 +#define OMAP24XX_EN_GPT2 (1 << 4) +#define OMAP2420_EN_VLYNQ_SHIFT 3 +#define OMAP2420_EN_VLYNQ (1 << 3) + +/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ +#define OMAP2430_EN_GPIO5_SHIFT 10 +#define OMAP2430_EN_GPIO5 (1 << 10) +#define OMAP2430_EN_MCSPI3_SHIFT 9 +#define OMAP2430_EN_MCSPI3 (1 << 9) +#define OMAP2430_EN_MMCHS2_SHIFT 8 +#define OMAP2430_EN_MMCHS2 (1 << 8) +#define OMAP2430_EN_MMCHS1_SHIFT 7 +#define OMAP2430_EN_MMCHS1 (1 << 7) +#define OMAP24XX_EN_UART3_SHIFT 2 +#define OMAP24XX_EN_UART3 (1 << 2) +#define OMAP24XX_EN_USB_SHIFT 0 +#define OMAP24XX_EN_USB (1 << 0) + +/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ +#define OMAP2430_EN_MDM_INTC_SHIFT 11 +#define OMAP2430_EN_MDM_INTC (1 << 11) +#define OMAP2430_EN_USBHS_SHIFT 6 +#define OMAP2430_EN_USBHS (1 << 6) + +/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ +#define OMAP2420_ST_MMC (1 << 26) +#define OMAP24XX_ST_UART2 (1 << 22) +#define OMAP24XX_ST_UART1 (1 << 21) +#define OMAP24XX_ST_MCSPI2 (1 << 18) +#define OMAP24XX_ST_MCSPI1 (1 << 17) +#define OMAP24XX_ST_GPT12 (1 << 14) +#define OMAP24XX_ST_GPT11 (1 << 13) +#define OMAP24XX_ST_GPT10 (1 << 12) +#define OMAP24XX_ST_GPT9 (1 << 11) +#define OMAP24XX_ST_GPT8 (1 << 10) +#define OMAP24XX_ST_GPT7 (1 << 9) +#define OMAP24XX_ST_GPT6 (1 << 8) +#define OMAP24XX_ST_GPT5 (1 << 7) +#define OMAP24XX_ST_GPT4 (1 << 6) +#define OMAP24XX_ST_GPT3 (1 << 5) +#define OMAP24XX_ST_GPT2 (1 << 4) +#define OMAP2420_ST_VLYNQ (1 << 3) + +/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ +#define OMAP2430_ST_MDM_INTC (1 << 11) +#define OMAP2430_ST_GPIO5 (1 << 10) +#define OMAP2430_ST_MCSPI3 (1 << 9) +#define OMAP2430_ST_MMCHS2 (1 << 8) +#define OMAP2430_ST_MMCHS1 (1 << 7) +#define OMAP2430_ST_USBHS (1 << 6) +#define OMAP24XX_ST_UART3 (1 << 2) +#define OMAP24XX_ST_USB (1 << 0) + +/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP24XX_EN_GPIOS_SHIFT 2 +#define OMAP24XX_EN_GPIOS (1 << 2) +#define OMAP24XX_EN_GPT1_SHIFT 0 +#define OMAP24XX_EN_GPT1 (1 << 0) + +/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ +#define OMAP24XX_ST_GPIOS (1 << 2) +#define OMAP24XX_ST_GPT1 (1 << 0) + +/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ +#define OMAP2430_ST_MDM (1 << 0) + + +/* 3430 register bits shared between CM & PRM registers */ + +/* CM_REVISION, PRM_REVISION shared bits */ +#define OMAP3430_REV_SHIFT 0 +#define OMAP3430_REV_MASK (0xff << 0) + +/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ +#define OMAP3430_AUTOIDLE (1 << 0) + +/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP3430_EN_MMC2 (1 << 25) +#define OMAP3430_EN_MMC2_SHIFT 25 +#define OMAP3430_EN_MMC1 (1 << 24) +#define OMAP3430_EN_MMC1_SHIFT 24 +#define OMAP3430_EN_MCSPI4 (1 << 21) +#define OMAP3430_EN_MCSPI4_SHIFT 21 +#define OMAP3430_EN_MCSPI3 (1 << 20) +#define OMAP3430_EN_MCSPI3_SHIFT 20 +#define OMAP3430_EN_MCSPI2 (1 << 19) +#define OMAP3430_EN_MCSPI2_SHIFT 19 +#define OMAP3430_EN_MCSPI1 (1 << 18) +#define OMAP3430_EN_MCSPI1_SHIFT 18 +#define OMAP3430_EN_I2C3 (1 << 17) +#define OMAP3430_EN_I2C3_SHIFT 17 +#define OMAP3430_EN_I2C2 (1 << 16) +#define OMAP3430_EN_I2C2_SHIFT 16 +#define OMAP3430_EN_I2C1 (1 << 15) +#define OMAP3430_EN_I2C1_SHIFT 15 +#define OMAP3430_EN_UART2 (1 << 14) +#define OMAP3430_EN_UART2_SHIFT 14 +#define OMAP3430_EN_UART1 (1 << 13) +#define OMAP3430_EN_UART1_SHIFT 13 +#define OMAP3430_EN_GPT11 (1 << 12) +#define OMAP3430_EN_GPT11_SHIFT 12 +#define OMAP3430_EN_GPT10 (1 << 11) +#define OMAP3430_EN_GPT10_SHIFT 11 +#define OMAP3430_EN_MCBSP5 (1 << 10) +#define OMAP3430_EN_MCBSP5_SHIFT 10 +#define OMAP3430_EN_MCBSP1 (1 << 9) +#define OMAP3430_EN_MCBSP1_SHIFT 9 +#define OMAP3430_EN_FSHOSTUSB (1 << 5) +#define OMAP3430_EN_FSHOSTUSB_SHIFT 5 +#define OMAP3430_EN_D2D (1 << 3) +#define OMAP3430_EN_D2D_SHIFT 3 + +/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP3430_EN_HSOTGUSB (1 << 4) +#define OMAP3430_EN_HSOTGUSB_SHIFT 4 + +/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ +#define OMAP3430_ST_MMC2 (1 << 25) +#define OMAP3430_ST_MMC1 (1 << 24) +#define OMAP3430_ST_MCSPI4 (1 << 21) +#define OMAP3430_ST_MCSPI3 (1 << 20) +#define OMAP3430_ST_MCSPI2 (1 << 19) +#define OMAP3430_ST_MCSPI1 (1 << 18) +#define OMAP3430_ST_I2C3 (1 << 17) +#define OMAP3430_ST_I2C2 (1 << 16) +#define OMAP3430_ST_I2C1 (1 << 15) +#define OMAP3430_ST_UART2 (1 << 14) +#define OMAP3430_ST_UART1 (1 << 13) +#define OMAP3430_ST_GPT11 (1 << 12) +#define OMAP3430_ST_GPT10 (1 << 11) +#define OMAP3430_ST_MCBSP5 (1 << 10) +#define OMAP3430_ST_MCBSP1 (1 << 9) +#define OMAP3430_ST_FSHOSTUSB (1 << 5) +#define OMAP3430_ST_HSOTGUSB (1 << 4) +#define OMAP3430_ST_D2D (1 << 3) + +/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP3430_EN_GPIO1 (1 << 3) +#define OMAP3430_EN_GPIO1_SHIFT 3 +#define OMAP3430_EN_GPT1 (1 << 0) +#define OMAP3430_EN_GPT1_SHIFT 0 + +/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP3430_EN_SR2 (1 << 7) +#define OMAP3430_EN_SR2_SHIFT 7 +#define OMAP3430_EN_SR1 (1 << 6) +#define OMAP3430_EN_SR1_SHIFT 6 + +/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ +#define OMAP3430_EN_GPT12 (1 << 1) +#define OMAP3430_EN_GPT12_SHIFT 1 + +/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ +#define OMAP3430_ST_SR2 (1 << 7) +#define OMAP3430_ST_SR1 (1 << 6) +#define OMAP3430_ST_GPIO1 (1 << 3) +#define OMAP3430_ST_GPT12 (1 << 1) +#define OMAP3430_ST_GPT1 (1 << 0) + +/* + * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, + * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, + * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits + */ +#define OMAP3430_EN_MPU (1 << 1) +#define OMAP3430_EN_MPU_SHIFT 1 + +/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ +#define OMAP3430_EN_GPIO6 (1 << 17) +#define OMAP3430_EN_GPIO6_SHIFT 17 +#define OMAP3430_EN_GPIO5 (1 << 16) +#define OMAP3430_EN_GPIO5_SHIFT 16 +#define OMAP3430_EN_GPIO4 (1 << 15) +#define OMAP3430_EN_GPIO4_SHIFT 15 +#define OMAP3430_EN_GPIO3 (1 << 14) +#define OMAP3430_EN_GPIO3_SHIFT 14 +#define OMAP3430_EN_GPIO2 (1 << 13) +#define OMAP3430_EN_GPIO2_SHIFT 13 +#define OMAP3430_EN_UART3 (1 << 11) +#define OMAP3430_EN_UART3_SHIFT 11 +#define OMAP3430_EN_GPT9 (1 << 10) +#define OMAP3430_EN_GPT9_SHIFT 10 +#define OMAP3430_EN_GPT8 (1 << 9) +#define OMAP3430_EN_GPT8_SHIFT 9 +#define OMAP3430_EN_GPT7 (1 << 8) +#define OMAP3430_EN_GPT7_SHIFT 8 +#define OMAP3430_EN_GPT6 (1 << 7) +#define OMAP3430_EN_GPT6_SHIFT 7 +#define OMAP3430_EN_GPT5 (1 << 6) +#define OMAP3430_EN_GPT5_SHIFT 6 +#define OMAP3430_EN_GPT4 (1 << 5) +#define OMAP3430_EN_GPT4_SHIFT 5 +#define OMAP3430_EN_GPT3 (1 << 4) +#define OMAP3430_EN_GPT3_SHIFT 4 +#define OMAP3430_EN_GPT2 (1 << 3) +#define OMAP3430_EN_GPT2_SHIFT 3 + +/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ +/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits + * be ST_* bits instead? */ +#define OMAP3430_EN_MCBSP4 (1 << 2) +#define OMAP3430_EN_MCBSP4_SHIFT 2 +#define OMAP3430_EN_MCBSP3 (1 << 1) +#define OMAP3430_EN_MCBSP3_SHIFT 1 +#define OMAP3430_EN_MCBSP2 (1 << 0) +#define OMAP3430_EN_MCBSP2_SHIFT 0 + +/* CM_IDLEST_PER, PM_WKST_PER shared bits */ +#define OMAP3430_ST_GPIO6 (1 << 17) +#define OMAP3430_ST_GPIO5 (1 << 16) +#define OMAP3430_ST_GPIO4 (1 << 15) +#define OMAP3430_ST_GPIO3 (1 << 14) +#define OMAP3430_ST_GPIO2 (1 << 13) +#define OMAP3430_ST_UART3 (1 << 11) +#define OMAP3430_ST_GPT9 (1 << 10) +#define OMAP3430_ST_GPT8 (1 << 9) +#define OMAP3430_ST_GPT7 (1 << 8) +#define OMAP3430_ST_GPT6 (1 << 7) +#define OMAP3430_ST_GPT5 (1 << 6) +#define OMAP3430_ST_GPT4 (1 << 5) +#define OMAP3430_ST_GPT3 (1 << 4) +#define OMAP3430_ST_GPT2 (1 << 3) + +/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ +#define OMAP3430_EN_CORE (1 << 0) + +#endif + diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h new file mode 100644 index 000000000000..c6d17a3378ec --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -0,0 +1,279 @@ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H + +/* + * OMAP24XX Power/Reset Management register bits + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "prm.h" + +/* Bits shared between registers */ + +/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ +#define OMAP24XX_VOLTTRANS_ST (1 << 2) +#define OMAP24XX_WKUP2_ST (1 << 1) +#define OMAP24XX_WKUP1_ST (1 << 0) + +/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ +#define OMAP24XX_VOLTTRANS_EN (1 << 2) +#define OMAP24XX_WKUP2_EN (1 << 1) +#define OMAP24XX_WKUP1_EN (1 << 0) + +/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ +#define OMAP24XX_EN_MPU (1 << 1) +#define OMAP24XX_EN_CORE (1 << 0) + +/* + * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM + * shared bits + */ +#define OMAP24XX_MEMONSTATE_SHIFT 10 +#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) +#define OMAP24XX_MEMRETSTATE (1 << 3) + +/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ +#define OMAP24XX_FORCESTATE (1 << 18) + +/* + * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, + * PM_PWSTST_MDM shared bits + */ +#define OMAP24XX_CLKACTIVITY (1 << 19) + +/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ +#define OMAP24XX_LASTSTATEENTERED_SHIFT 4 +#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) + +/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ +#define OMAP2430_MEMSTATEST_SHIFT 10 +#define OMAP2430_MEMSTATEST_MASK (0x3 << 10) + +/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ +#define OMAP24XX_POWERSTATEST_SHIFT 0 +#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) + + +/* Bits specific to each register */ + +/* PRCM_REVISION */ +#define OMAP24XX_REV_SHIFT 0 +#define OMAP24XX_REV_MASK (0xff << 0) + +/* PRCM_SYSCONFIG */ +#define OMAP24XX_AUTOIDLE (1 << 0) + +/* PRCM_IRQSTATUS_MPU specific bits */ +#define OMAP2430_DPLL_RECAL_ST (1 << 6) +#define OMAP24XX_TRANSITION_ST (1 << 5) +#define OMAP24XX_EVGENOFF_ST (1 << 4) +#define OMAP24XX_EVGENON_ST (1 << 3) + +/* PRCM_IRQENABLE_MPU specific bits */ +#define OMAP2430_DPLL_RECAL_EN (1 << 6) +#define OMAP24XX_TRANSITION_EN (1 << 5) +#define OMAP24XX_EVGENOFF_EN (1 << 4) +#define OMAP24XX_EVGENON_EN (1 << 3) + +/* PRCM_VOLTCTRL */ +#define OMAP24XX_AUTO_EXTVOLT (1 << 15) +#define OMAP24XX_FORCE_EXTVOLT (1 << 14) +#define OMAP24XX_SETOFF_LEVEL_SHIFT 12 +#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) +#define OMAP24XX_MEMRETCTRL (1 << 8) +#define OMAP24XX_SETRET_LEVEL_SHIFT 6 +#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) +#define OMAP24XX_VOLT_LEVEL_SHIFT 0 +#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) + +/* PRCM_VOLTST */ +#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 +#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) + +/* PRCM_CLKSRC_CTRL specific bits */ + +/* PRCM_CLKOUT_CTRL */ +#define OMAP2420_CLKOUT2_EN_SHIFT 15 +#define OMAP2420_CLKOUT2_EN (1 << 15) +#define OMAP2420_CLKOUT2_DIV_SHIFT 11 +#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) +#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 +#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) +#define OMAP24XX_CLKOUT_EN_SHIFT 7 +#define OMAP24XX_CLKOUT_EN (1 << 7) +#define OMAP24XX_CLKOUT_DIV_SHIFT 3 +#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) +#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 +#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) + +/* PRCM_CLKEMUL_CTRL */ +#define OMAP24XX_EMULATION_EN_SHIFT 0 +#define OMAP24XX_EMULATION_EN (1 << 0) + +/* PRCM_CLKCFG_CTRL */ +#define OMAP24XX_VALID_CONFIG (1 << 0) + +/* PRCM_CLKCFG_STATUS */ +#define OMAP24XX_CONFIG_STATUS (1 << 0) + +/* PRCM_VOLTSETUP specific bits */ + +/* PRCM_CLKSSETUP specific bits */ + +/* PRCM_POLCTRL */ +#define OMAP2420_CLKOUT2_POL (1 << 10) +#define OMAP24XX_CLKOUT_POL (1 << 9) +#define OMAP24XX_CLKREQ_POL (1 << 8) +#define OMAP2430_USE_POWEROK (1 << 2) +#define OMAP2430_POWEROK_POL (1 << 1) +#define OMAP24XX_EXTVOL_POL (1 << 0) + +/* RM_RSTST_MPU specific bits */ +/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ + +/* PM_WKDEP_MPU specific bits */ +#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) +#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) + +/* PM_EVGENCTRL_MPU specific bits */ + +/* PM_EVEGENONTIM_MPU specific bits */ + +/* PM_EVEGENOFFTIM_MPU specific bits */ + +/* PM_PWSTCTRL_MPU specific bits */ +#define OMAP2430_FORCESTATE (1 << 18) + +/* PM_PWSTST_MPU specific bits */ +/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ + +/* PM_WKEN1_CORE specific bits */ + +/* PM_WKEN2_CORE specific bits */ + +/* PM_WKST1_CORE specific bits*/ + +/* PM_WKST2_CORE specific bits */ + +/* PM_WKDEP_CORE specific bits*/ +#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5) +#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3) +#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2) + +/* PM_PWSTCTRL_CORE specific bits */ +#define OMAP24XX_MEMORYCHANGE (1 << 20) +#define OMAP24XX_MEM3ONSTATE_SHIFT 14 +#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) +#define OMAP24XX_MEM2ONSTATE_SHIFT 12 +#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) +#define OMAP24XX_MEM1ONSTATE_SHIFT 10 +#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) +#define OMAP24XX_MEM3RETSTATE (1 << 5) +#define OMAP24XX_MEM2RETSTATE (1 << 4) +#define OMAP24XX_MEM1RETSTATE (1 << 3) + +/* PM_PWSTST_CORE specific bits */ +#define OMAP24XX_MEM3STATEST_SHIFT 14 +#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) +#define OMAP24XX_MEM2STATEST_SHIFT 12 +#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) +#define OMAP24XX_MEM1STATEST_SHIFT 10 +#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) + +/* RM_RSTCTRL_GFX */ +#define OMAP24XX_GFX_RST (1 << 0) + +/* RM_RSTST_GFX specific bits */ +#define OMAP24XX_GFX_SW_RST (1 << 4) + +/* PM_PWSTCTRL_GFX specific bits */ + +/* PM_WKDEP_GFX specific bits */ +/* 2430 often calls EN_WAKEUP "EN_WKUP" */ + +/* RM_RSTCTRL_WKUP specific bits */ + +/* RM_RSTTIME_WKUP specific bits */ + +/* RM_RSTST_WKUP specific bits */ +/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ +#define OMAP24XX_EXTWMPU_RST (1 << 6) +#define OMAP24XX_SECU_WD_RST (1 << 5) +#define OMAP24XX_MPU_WD_RST (1 << 4) +#define OMAP24XX_SECU_VIOL_RST (1 << 3) + +/* PM_WKEN_WKUP specific bits */ + +/* PM_WKST_WKUP specific bits */ + +/* RM_RSTCTRL_DSP */ +#define OMAP2420_RST_IVA (1 << 8) +#define OMAP24XX_RST2_DSP (1 << 1) +#define OMAP24XX_RST1_DSP (1 << 0) + +/* RM_RSTST_DSP specific bits */ +/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ +#define OMAP2420_IVA_SW_RST (1 << 8) +#define OMAP24XX_DSP_SW_RST2 (1 << 5) +#define OMAP24XX_DSP_SW_RST1 (1 << 4) + +/* PM_WKDEP_DSP specific bits */ + +/* PM_PWSTCTRL_DSP specific bits */ +/* 2430 only: MEMONSTATE, MEMRETSTATE */ +#define OMAP2420_MEMIONSTATE_SHIFT 12 +#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) +#define OMAP2420_MEMIRETSTATE (1 << 4) + +/* PM_PWSTST_DSP specific bits */ +/* MEMSTATEST is 2430 only */ +#define OMAP2420_MEMISTATEST_SHIFT 12 +#define OMAP2420_MEMISTATEST_MASK (0x3 << 12) + +/* PRCM_IRQSTATUS_DSP specific bits */ + +/* PRCM_IRQENABLE_DSP specific bits */ + +/* RM_RSTCTRL_MDM */ +/* 2430 only */ +#define OMAP2430_PWRON1_MDM (1 << 1) +#define OMAP2430_RST1_MDM (1 << 0) + +/* RM_RSTST_MDM specific bits */ +/* 2430 only */ +#define OMAP2430_MDM_SECU_VIOL (1 << 6) +#define OMAP2430_MDM_SW_PWRON1 (1 << 5) +#define OMAP2430_MDM_SW_RST1 (1 << 4) + +/* PM_WKEN_MDM */ +/* 2430 only */ +#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0) + +/* PM_WKST_MDM specific bits */ +/* 2430 only */ + +/* PM_WKDEP_MDM specific bits */ +/* 2430 only */ + +/* PM_PWSTCTRL_MDM specific bits */ +/* 2430 only */ +#define OMAP2430_KILLDOMAINWKUP (1 << 19) + +/* PM_PWSTST_MDM specific bits */ +/* 2430 only */ + +/* PRCM_IRQSTATUS_IVA */ +/* 2420 only */ + +/* PRCM_IRQENABLE_IVA */ +/* 2420 only */ + +#endif diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h new file mode 100644 index 000000000000..ab7649afd891 --- /dev/null +++ b/arch/arm/mach-omap2/prm.h @@ -0,0 +1,316 @@ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H +#define __ARCH_ARM_MACH_OMAP2_PRM_H + +/* + * OMAP2/3 Power/Reset Management (PRM) register definitions + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "prcm-common.h" + +#ifndef __ASSEMBLER__ +#define OMAP_PRM_REGADDR(module, reg) \ + (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) +#else +#define OMAP2420_PRM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) +#define OMAP2430_PRM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) +#define OMAP34XX_PRM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) +#endif + +/* + * Architecture-specific global PRM registers + * Use prm_{read,write}_reg() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the + * IRQSTATUS and IRQENABLE bits.) + * + */ + +#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific PRM registers from PRM_BASE + domain offset + * + * Use prm_{read,write}_mod_reg() with these registers. + * + * With a few exceptions, these are the register names beginning with + * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS + * and IRQENABLE bits.) + * + */ + +/* Registers appearing on both 24xx and 34xx */ + +#define RM_RSTCTRL 0x0050 +#define RM_RSTTIME 0x0054 +#define RM_RSTST 0x0058 + +#define PM_WKEN 0x00a0 +#define PM_WKEN1 PM_WKEN +#define PM_WKST 0x00b0 +#define PM_WKST1 PM_WKST +#define PM_WKDEP 0x00c8 +#define PM_EVGENCTRL 0x00d4 +#define PM_EVGENONTIM 0x00d8 +#define PM_EVGENOFFTIM 0x00dc +#define PM_PWSTCTRL 0x00e0 +#define PM_PWSTST 0x00e4 + +#define OMAP3430_PM_MPUGRPSEL 0x00a4 +#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL + +#define OMAP3430_PM_IVAGRPSEL 0x00a8 +#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL + +#define OMAP3430_PM_PREPWSTST 0x00e8 + +#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 +#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc + + +/* Architecture-specific registers */ + +#define OMAP24XX_PM_WKEN2 0x00a4 +#define OMAP24XX_PM_WKST2 0x00b4 + +#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ +#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ +#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 +#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc + +#ifndef __ASSEMBLER__ + +/* Power/reset management domain register get/set */ + +static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx) +{ + __raw_writel(val, OMAP_PRM_REGADDR(module, idx)); +} + +static inline u32 prm_read_mod_reg(s16 module, s16 idx) +{ + return __raw_readl(OMAP_PRM_REGADDR(module, idx)); +} + +#endif + +/* + * Bits common to specific registers + * + * The 3430 register and bit names are generally used, + * since they tend to make more sense + */ + +/* PM_EVGENONTIM_MPU */ +/* Named PM_EVEGENONTIM_MPU on the 24XX */ +#define OMAP_ONTIMEVAL_SHIFT 0 +#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) + +/* PM_EVGENOFFTIM_MPU */ +/* Named PM_EVEGENOFFTIM_MPU on the 24XX */ +#define OMAP_OFFTIMEVAL_SHIFT 0 +#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) + +/* PRM_CLKSETUP and PRCM_VOLTSETUP */ +/* Named PRCM_CLKSSETUP on the 24XX */ +#define OMAP_SETUP_TIME_SHIFT 0 +#define OMAP_SETUP_TIME_MASK (0xffff << 0) + +/* PRM_CLKSRC_CTRL */ +/* Named PRCM_CLKSRC_CTRL on the 24XX */ +#define OMAP_SYSCLKDIV_SHIFT 6 +#define OMAP_SYSCLKDIV_MASK (0x3 << 6) +#define OMAP_AUTOEXTCLKMODE_SHIFT 3 +#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) +#define OMAP_SYSCLKSEL_SHIFT 0 +#define OMAP_SYSCLKSEL_MASK (0x3 << 0) + +/* PM_EVGENCTRL_MPU */ +#define OMAP_OFFLOADMODE_SHIFT 3 +#define OMAP_OFFLOADMODE_MASK (0x3 << 3) +#define OMAP_ONLOADMODE_SHIFT 1 +#define OMAP_ONLOADMODE_MASK (0x3 << 1) +#define OMAP_ENABLE (1 << 0) + +/* PRM_RSTTIME */ +/* Named RM_RSTTIME_WKUP on the 24xx */ +#define OMAP_RSTTIME2_SHIFT 8 +#define OMAP_RSTTIME2_MASK (0x1f << 8) +#define OMAP_RSTTIME1_SHIFT 0 +#define OMAP_RSTTIME1_MASK (0xff << 0) + + +/* PRM_RSTCTRL */ +/* Named RM_RSTCTRL_WKUP on the 24xx */ +/* 2420 calls RST_DPLL3 'RST_DPLL' */ +#define OMAP_RST_DPLL3 (1 << 2) +#define OMAP_RST_GS (1 << 1) + + +/* + * Bits common to module-shared registers + * + * Not all registers of a particular type support all of these bits - + * check TRM if you are unsure + */ + +/* + * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP + * + * 2430: PM_PWSTST_MDM + * + * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, + * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, + * PM_PWSTST_NEON + */ +#define OMAP_INTRANSITION (1 << 20) + + +/* + * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP + * + * 2430: PM_PWSTST_MDM + * + * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, + * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, + * PM_PWSTST_NEON + */ +#define OMAP_POWERSTATEST_SHIFT 0 +#define OMAP_POWERSTATEST_MASK (0x3 << 0) + +/* + * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is + * called 'COREWKUP_RST' + * + * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, + * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON + */ +#define OMAP_COREDOMAINWKUP_RST (1 << 3) + +/* + * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP + * + * 2430: RM_RSTST_MDM + * + * 3430: RM_RSTST_CORE, RM_RSTST_EMU + */ +#define OMAP_DOMAINWKUP_RST (1 << 2) + +/* + * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP + * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. + * + * 2430: RM_RSTST_MDM + * + * 3430: RM_RSTST_CORE, RM_RSTST_EMU + */ +#define OMAP_GLOBALWARM_RST (1 << 1) +#define OMAP_GLOBALCOLD_RST (1 << 0) + +/* + * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP + * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" + * + * 2430: PM_WKDEP_MDM + * + * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, + * PM_WKDEP_PER + */ +#define OMAP_EN_WKUP (1 << 4) + +/* + * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSP + * + * 2430: PM_PWSTCTRL_MDM + * + * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, + * PM_PWSTCTRL_NEON + */ +#define OMAP_LOGICRETSTATE (1 << 2) + +/* + * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSP, PM_PWSTST_MPU + * + * 2430: PM_PWSTCTRL_MDM shared bits + * + * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, + * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, + * PM_PWSTCTRL_NEON shared bits + */ +#define OMAP_POWERSTATE_SHIFT 0 +#define OMAP_POWERSTATE_MASK (0x3 << 0) + + +#endif diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h new file mode 100644 index 000000000000..d7f23bc9550a --- /dev/null +++ b/arch/arm/mach-omap2/sdrc.h @@ -0,0 +1,58 @@ +#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H +#define __ARCH_ARM_MACH_OMAP2_SDRC_H + +/* + * OMAP2 SDRC register definitions + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include + +#ifndef __ASSEMBLER__ +extern unsigned long omap2_sdrc_base; +extern unsigned long omap2_sms_base; + +#define OMAP_SDRC_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg)) +#define OMAP_SMS_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg)) + +/* SDRC global register get/set */ + +static inline void sdrc_write_reg(u32 val, u16 reg) +{ + __raw_writel(val, OMAP_SDRC_REGADDR(reg)); +} + +static inline u32 sdrc_read_reg(u16 reg) +{ + return __raw_readl(OMAP_SDRC_REGADDR(reg)); +} + +/* SMS global register get/set */ + +static inline void sms_write_reg(u32 val, u16 reg) +{ + __raw_writel(val, OMAP_SMS_REGADDR(reg)); +} + +static inline u32 sms_read_reg(u16 reg) +{ + return __raw_readl(OMAP_SMS_REGADDR(reg)); +} +#else +#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) +#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) +#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index a5aedf964b88..a619475c4b76 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -76,7 +77,7 @@ /*-------------------------------------------------------------------------*/ -#ifdef CONFIG_ARCH_OMAP_OTG +#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG) static struct otg_transceiver *xceiv; @@ -110,12 +111,48 @@ EXPORT_SYMBOL(otg_set_transceiver); #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) +static void omap2_usb_devconf_clear(u8 port, u32 mask) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r &= ~USBTXWRMODEI(port, mask); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb_devconf_set(u8 port, u32 mask) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r |= USBTXWRMODEI(port, mask); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb2_disable_5pinbitll(void) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb2_enable_5pinunitll(void) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) { u32 syscon1 = 0; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL); + omap2_usb_devconf_clear(0, USB_BIDIR_TLL); if (nwires == 0) { if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { @@ -187,19 +224,19 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) case 3: syscon1 = 2; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR); + omap2_usb_devconf_set(0, USB_BIDIR); break; case 4: syscon1 = 1; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR); + omap2_usb_devconf_set(0, USB_BIDIR); break; case 6: syscon1 = 3; if (cpu_is_omap24xx()) { omap_cfg_reg(J19_24XX_USB0_VP); omap_cfg_reg(K20_24XX_USB0_VM); - CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR); + omap2_usb_devconf_set(0, USB_UNIDIR); } else { omap_cfg_reg(AA9_USB0_VP); omap_cfg_reg(R9_USB0_VM); @@ -220,7 +257,7 @@ static u32 __init omap_usb1_init(unsigned nwires) if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL); + omap2_usb_devconf_clear(1, USB_BIDIR_TLL); if (nwires == 0) return 0; @@ -261,17 +298,17 @@ static u32 __init omap_usb1_init(unsigned nwires) * this TLL link is not using DP/DM */ syscon1 = 1; - CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL); + omap2_usb_devconf_set(1, USB_BIDIR_TLL); break; case 3: syscon1 = 2; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR); + omap2_usb_devconf_set(1, USB_BIDIR); break; case 4: syscon1 = 1; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR); + omap2_usb_devconf_set(1, USB_BIDIR); break; case 6: if (cpu_is_omap24xx()) @@ -295,8 +332,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) u32 syscon1 = 0; if (cpu_is_omap24xx()) { - CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL) - | USBT2TLL5PI); + omap2_usb2_disable_5pinbitll(); alt_pingroup = 0; } @@ -343,17 +379,17 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) * this TLL link is not using DP/DM */ syscon1 = 1; - CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL); + omap2_usb_devconf_set(2, USB_BIDIR_TLL); break; case 3: syscon1 = 2; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR); + omap2_usb_devconf_set(2, USB_BIDIR); break; case 4: syscon1 = 1; if (cpu_is_omap24xx()) - CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR); + omap2_usb_devconf_set(2, USB_BIDIR); break; case 5: if (!cpu_is_omap24xx()) @@ -364,8 +400,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} */ syscon1 = 3; - CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL) - | USBT2TLL5PI; + omap2_usb2_enable_5pinunitll(); break; case 6: if (cpu_is_omap24xx()) diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h new file mode 100644 index 000000000000..9944bb5d5330 --- /dev/null +++ b/include/asm-arm/arch-omap/control.h @@ -0,0 +1,191 @@ +#ifndef __ASM_ARCH_CONTROL_H +#define __ASM_ARCH_CONTROL_H + +/* + * include/asm-arm/arch-omap/control.h + * + * OMAP2/3 System Control Module definitions + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + */ + +#include + +#define OMAP242X_CTRL_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) +#define OMAP243X_CTRL_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) +#define OMAP343X_CTRL_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) + +/* + * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for + * OMAP24XX and OMAP34XX. + */ + +/* Control submodule offsets */ + +#define OMAP2_CONTROL_INTERFACE 0x000 +#define OMAP2_CONTROL_PADCONFS 0x030 +#define OMAP2_CONTROL_GENERAL 0x270 +#define OMAP343X_CONTROL_MEM_WKUP 0x600 +#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 +#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 + +/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ + +#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) + +/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ +#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) +#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) +#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) +#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) +#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) +#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) +#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) +#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) +#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) +#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) +#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) +#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) + +/* 242x-only CONTROL_GENERAL register offsets */ +#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ +#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) + +/* 243x-only CONTROL_GENERAL register offsets */ +/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ +#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) +#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) +#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) +#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) +#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) + +/* 24xx-only CONTROL_GENERAL register offsets */ +#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) +#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) +#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) +#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) +#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) +#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) +#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) +#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) +#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) +#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) +#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074 +#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) +#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) +#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) +#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) +#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) +#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) +#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) +#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) +#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) +#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) +#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) +#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) +#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) +#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) +#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) +#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) +#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) +#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) +#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) +#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) + +/* 34xx-only CONTROL_GENERAL register offsets */ +#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) +#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) +#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) +#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) +#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) +#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) +#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) +#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) +#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) +#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) +#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) +#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) +#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) +#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) +#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) +#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) +#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) +#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) +#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) +#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) +#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) +#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) +#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) +#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) +#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) +#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) +#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) +#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) +#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) + +/* + * REVISIT: This list of registers is not comprehensive - there are more + * that should be added. + */ + +/* + * Control module register bit defines - these should eventually go into + * their own regbits file. Some of these will be complicated, depending + * on the device type (general-purpose, emulator, test, secure, bad, other) + * and the security mode (secure, non-secure, don't care) + */ +/* CONTROL_DEVCONF0 bits */ +#define OMAP24XX_USBSTANDBYCTRL (1 << 15) +#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) +#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) + +/* CONTROL_DEVCONF1 bits */ +#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ +#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ +#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ + +/* CONTROL_STATUS bits */ +#define OMAP2_DEVICETYPE_MASK (0x7 << 8) +#define OMAP2_SYSBOOT_5_MASK (1 << 5) +#define OMAP2_SYSBOOT_4_MASK (1 << 4) +#define OMAP2_SYSBOOT_3_MASK (1 << 3) +#define OMAP2_SYSBOOT_2_MASK (1 << 2) +#define OMAP2_SYSBOOT_1_MASK (1 << 1) +#define OMAP2_SYSBOOT_0_MASK (1 << 0) + +#ifndef __ASSEMBLY__ +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +extern void omap_ctrl_base_set(u32 base); +extern u32 omap_ctrl_base_get(void); +extern u8 omap_ctrl_readb(u16 offset); +extern u16 omap_ctrl_readw(u16 offset); +extern u32 omap_ctrl_readl(u16 offset); +extern void omap_ctrl_writeb(u8 val, u16 offset); +extern void omap_ctrl_writew(u16 val, u16 offset); +extern void omap_ctrl_writel(u32 val, u16 offset); +#else +#define omap_ctrl_base_set(x) WARN_ON(1) +#define omap_ctrl_base_get() 0 +#define omap_ctrl_readb(x) 0 +#define omap_ctrl_readw(x) 0 +#define omap_ctrl_readl(x) 0 +#define omap_ctrl_writeb(x, y) WARN_ON(1) +#define omap_ctrl_writew(x, y) WARN_ON(1) +#define omap_ctrl_writel(x, y) WARN_ON(1) +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_CONTROL_H */ + diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h new file mode 100644 index 000000000000..673b3965befc --- /dev/null +++ b/include/asm-arm/arch-omap/sdrc.h @@ -0,0 +1,75 @@ +#ifndef ____ASM_ARCH_SDRC_H +#define ____ASM_ARCH_SDRC_H + +/* + * OMAP2/3 SDRC/SMS register definitions + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ + +#define SDRC_SYSCONFIG 0x010 +#define SDRC_DLLA_CTRL 0x060 +#define SDRC_DLLA_STATUS 0x064 +#define SDRC_DLLB_CTRL 0x068 +#define SDRC_DLLB_STATUS 0x06C +#define SDRC_POWER 0x070 +#define SDRC_MR_0 0x084 +#define SDRC_RFR_CTRL_0 0x0a4 + +/* + * These values represent the number of memory clock cycles between + * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 + * rows per device, and include a subtraction of a 50 cycle window in the + * event that the autorefresh command is delayed due to other SDRC activity. + * The '| 1' sets the ARE field to send one autorefresh when the autorefresh + * counter reaches 0. + * + * These represent optimal values for common parts, it won't work for all. + * As long as you scale down, most parameters are still work, they just + * become sub-optimal. The RFR value goes in the opposite direction. If you + * don't adjust it down as your clock period increases the refresh interval + * will not be met. Setting all parameters for complete worst case may work, + * but may cut memory performance by 2x. Due to errata the DLLs need to be + * unlocked and their value needs run time calibration. A dynamic call is + * need for that as no single right value exists acorss production samples. + * + * Only the FULL speed values are given. Current code is such that rate + * changes must be made at DPLLoutx2. The actual value adjustment for low + * frequency operation will be handled by omap_set_performance() + * + * By having the boot loader boot up in the fastest L4 speed available likely + * will result in something which you can switch between. + */ +#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) +#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) +#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) +#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ +#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ + + +/* + * SMS register access + */ + + +#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) +#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) +#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) + +/* SMS register offsets - read/write with sms_{read,write}_reg() */ + +#define SMS_SYSCONFIG 0x010 +/* REVISIT: fill in other SMS registers here */ + +#endif diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h index 99ae9eabaf71..2147d18aaeae 100644 --- a/include/asm-arm/arch-omap/usb.h +++ b/include/asm-arm/arch-omap/usb.h @@ -132,14 +132,11 @@ # define CONF_USB_PWRDN_DP_R (1 << 1) /* OMAP2 */ -#define CONTROL_DEVCONF_REG __REG32(L4_24XX_BASE + 0x0274) # define USB_UNIDIR 0x0 # define USB_UNIDIR_TLL 0x1 # define USB_BIDIR 0x2 # define USB_BIDIR_TLL 0x3 -# define USBT0WRMODEI(x) ((x) << 22) -# define USBT1WRMODEI(x) ((x) << 20) -# define USBT2WRMODEI(x) ((x) << 18) +# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2))) # define USBT2TLL5PI (1 << 17) # define USB0PUENACTLOI (1 << 16) # define USBSTANDBYCTRL (1 << 15) -- cgit v1.2.3-59-g8ed1b From 445959821f82846913fe09fee0573e0238415e8c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 18 Mar 2008 10:04:51 +0200 Subject: ARM: OMAP2: Change 24xx to use new register access This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 23 ++++--- arch/arm/mach-omap2/board-apollon.c | 60 ++++++++++++++--- arch/arm/mach-omap2/board-h4.c | 111 +++++++++++++++++++++++++++++--- arch/arm/mach-omap2/gpmc.c | 12 ++-- arch/arm/mach-omap2/memory.c | 26 ++++---- arch/arm/mach-omap2/mux.c | 10 +-- arch/arm/mach-omap2/prcm-regs.h | 14 ++++ arch/arm/mach-omap2/prcm.c | 14 +++- arch/arm/mach-omap2/sleep.S | 23 ++----- arch/arm/mach-omap2/sram-fn.S | 42 +++++------- arch/arm/plat-omap/common.c | 47 +++++++++++++- include/asm-arm/arch-omap/clock.h | 5 ++ include/asm-arm/arch-omap/entry-macro.S | 2 +- include/asm-arm/arch-omap/io.h | 70 +++++++++++++++++++- include/asm-arm/arch-omap/omap24xx.h | 96 ++++++++++++++++++++++----- 15 files changed, 434 insertions(+), 121 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 64235dee5614..1c12d7c6c7fc 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -33,7 +33,6 @@ #include #include #include -#include "prcm-regs.h" #include @@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void) int eth_cs; unsigned long cs_mem_base; unsigned int rate; - struct clk *l3ck; + struct clk *gpmc_fck; eth_cs = SDP2430_SMC91X_CS; - l3ck = clk_get(NULL, "core_l3_ck"); - if (IS_ERR(l3ck)) - rate = 100000000; - else - rate = clk_get_rate(l3ck); + gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ + if (IS_ERR(gpmc_fck)) { + WARN_ON(1); + return; + } + + clk_enable(gpmc_fck); + rate = clk_get_rate(gpmc_fck); /* Make sure CS1 timings are correct, for 2430 always muxed */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); @@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void) if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); - return; + goto out; } sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; @@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void) printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", OMAP24XX_ETHR_GPIO_IRQ); gpmc_cs_free(eth_cs); - return; + goto out; } omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); +out: + clk_disable(gpmc_fck); + clk_put(gpmc_fck); } static void __init omap_2430sdp_init_irq(void) diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 7846551f0575..a1e1e6765b5b 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include @@ -39,7 +41,7 @@ #include #include #include -#include "prcm-regs.h" +#include /* LED & Switch macros */ #define LED0_GPIO13 13 @@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void) { unsigned long base; + unsigned int rate; + struct clk *gpmc_fck; + int eth_cs; + + gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ + if (IS_ERR(gpmc_fck)) { + WARN_ON(1); + return; + } + + clk_enable(gpmc_fck); + rate = clk_get_rate(gpmc_fck); + + eth_cs = APOLLON_ETH_CS; + /* Make sure CS1 timings are correct */ - GPMC_CONFIG1_1 = 0x00011203; - GPMC_CONFIG2_1 = 0x001f1f01; - GPMC_CONFIG3_1 = 0x00080803; - GPMC_CONFIG4_1 = 0x1c091c09; - GPMC_CONFIG5_1 = 0x041f1f1f; - GPMC_CONFIG6_1 = 0x000004c4; + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); + + if (rate >= 160000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else if (rate >= 130000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else {/* rate = 100000000 */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); + } if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); - return; + goto out; } apollon_smc91x_resources[0].start = base + 0x300; apollon_smc91x_resources[0].end = base + 0x30f; @@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void) printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); gpmc_cs_free(APOLLON_ETH_CS); - return; + goto out; } omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); + +out: + clk_disable(gpmc_fck); + clk_put(gpmc_fck); } static void __init omap_apollon_init_irq(void) @@ -330,6 +366,8 @@ static void __init apollon_usb_init(void) static void __init omap_apollon_init(void) { + u32 v; + apollon_led_init(); apollon_sw_init(); apollon_flash_init(); @@ -339,7 +377,9 @@ static void __init omap_apollon_init(void) omap_cfg_reg(W19_24XX_SYS_NIRQ); /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ - CONTROL_DEVCONF |= (1 << 24); + v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + v |= (1 << 24); + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); /* * Make sure the serial ports are muxed on at this point. diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index f125f432cc3e..d1915f99a5fa 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include @@ -26,6 +28,7 @@ #include #include +#include #include #include #include @@ -36,10 +39,13 @@ #include #include #include -#include "prcm-regs.h" +#include #include +#define H4_FLASH_CS 0 +#define H4_SMC91X_CS 1 + static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; @@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = { }; static struct resource h4_flash_resource = { - .start = H4_CS0_BASE, - .end = H4_CS0_BASE + SZ_64M - 1, .flags = IORESOURCE_MEM, }; @@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = { &h4_lcd_device, }; +/* 2420 Sysboot setup (2430 is different) */ +static u32 get_sysboot_value(void) +{ + return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) & + (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK | + OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK | + OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK)); +} + +/* H4-2420's always used muxed mode, H4-2422's always use non-muxed + * + * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423 + * correctly. The macro needs to look at production_id not just hawkeye. + */ +static u32 is_gpmc_muxed(void) +{ + u32 mux; + mux = get_sysboot_value(); + if ((mux & 0xF) == 0xd) + return 1; /* NAND config (could be either) */ + if (mux & 0x2) /* if mux'ed */ + return 1; + else + return 0; +} + static inline void __init h4_init_debug(void) { + int eth_cs; + unsigned long cs_mem_base; + unsigned int muxed, rate; + struct clk *gpmc_fck; + + eth_cs = H4_SMC91X_CS; + + gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ + if (IS_ERR(gpmc_fck)) { + WARN_ON(1); + return; + } + + clk_enable(gpmc_fck); + rate = clk_get_rate(gpmc_fck); + clk_disable(gpmc_fck); + clk_put(gpmc_fck); + + if (is_gpmc_muxed()) + muxed = 0x200; + else + muxed = 0; + /* Make sure CS1 timings are correct */ - GPMC_CONFIG1_1 = 0x00011200; - GPMC_CONFIG2_1 = 0x001f1f01; - GPMC_CONFIG3_1 = 0x00080803; - GPMC_CONFIG4_1 = 0x1c091c09; - GPMC_CONFIG5_1 = 0x041f1f1f; - GPMC_CONFIG6_1 = 0x000004c4; - GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, + 0x00011000 | muxed); + + if (rate >= 160000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else if (rate >= 130000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else {/* rate = 100000000 */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); + } + + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + goto out; + } + udelay(100); omap_cfg_reg(M15_24XX_GPIO92); if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) gpmc_cs_free(eth_cs); + +out: + clk_disable(gpmc_fck); + clk_put(gpmc_fck); +} + +static void __init h4_init_flash(void) +{ + unsigned long base; + + if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) { + printk("Can't request GPMC CS for flash\n"); + return; + } + h4_flash_resource.start = base; + h4_flash_resource.end = base + SZ_64M - 1; } static void __init omap_h4_init_irq(void) @@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void) omap2_init_common_hw(); omap_init_irq(); omap_gpio_init(); + h4_init_flash(); } static struct omap_uart_config h4_uart_config __initdata = { diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5a4cc2076a7d..02cede295e89 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -69,7 +69,7 @@ static void __iomem *gpmc_base = static void __iomem *gpmc_cs_base = (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; -static struct clk *gpmc_l3_clk; +static struct clk *gpmc_fck; static void gpmc_write_reg(int idx, u32 val) { @@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx) return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); } -/* TODO: Add support for gpmc_fck to clock framework and use it */ unsigned long gpmc_get_fclk_period(void) { /* In picoseconds */ - return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); + return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000); } unsigned int gpmc_ns_to_ticks(unsigned int time_ns) @@ -398,8 +397,11 @@ void __init gpmc_init(void) { u32 l; - gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); - BUG_ON(IS_ERR(gpmc_l3_clk)); + gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ + if (IS_ERR(gpmc_fck)) + WARN_ON(1); + else + clk_enable(gpmc_fck); l = gpmc_read_reg(GPMC_REVISION); printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 3e5d8cd4ea4f..b56c1a082d92 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -27,11 +27,16 @@ #include #include -#include "prcm-regs.h" +#include "prm.h" + #include "memory.h" +#include "sdrc.h" +unsigned long omap2_sdrc_base; +unsigned long omap2_sms_base; static struct memory_timings mem_timings; +static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; u32 omap2_memory_get_slow_dll_ctrl(void) { @@ -53,7 +58,7 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) unsigned long dll_cnt; u32 fast_dll = 0; - mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ + mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. * In the case of 2422, its ok to use CS1 instead of CS0. @@ -73,11 +78,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) mem_timings.dll_mode = M_LOCK; if (mem_timings.base_cs == 0) { - fast_dll = SDRC_DLLA_CTRL; - dll_cnt = SDRC_DLLA_STATUS & 0xff00; + fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL); + dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; } else { - fast_dll = SDRC_DLLB_CTRL; - dll_cnt = SDRC_DLLB_STATUS & 0xff00; + fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL); + dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00; } if (force_lock_to_unlock_mode) { fast_dll &= ~0xff00; @@ -106,14 +111,13 @@ void __init omap2_init_memory(void) { u32 l; - l = SMS_SYSCONFIG; + l = sms_read_reg(SMS_SYSCONFIG); l &= ~(0x3 << 3); l |= (0x2 << 3); - SMS_SYSCONFIG = l; + sms_write_reg(l, SMS_SYSCONFIG); - l = SDRC_SYSCONFIG; + l = sdrc_read_reg(SDRC_SYSCONFIG); l &= ~(0x3 << 3); l |= (0x2 << 3); - SDRC_SYSCONFIG = l; - + sdrc_write_reg(l, SDRC_SYSCONFIG); } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 0cf7562ff88f..930770012a75 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -29,6 +29,7 @@ #include #include +#include #include #ifdef CONFIG_OMAP_MUX @@ -218,18 +219,16 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) #define OMAP24XX_PINS_SZ 0 #endif /* CONFIG_ARCH_OMAP24XX */ -#define OMAP24XX_L4_BASE 0x48000000 #define OMAP24XX_PULL_ENA (1 << 3) #define OMAP24XX_PULL_UP (1 << 4) -/* REVISIT: Convert this code to use ctrl_{read,write}_reg */ #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) { u16 orig; u8 warn = 0, debug = 0; - orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); + orig = omap_ctrl_readb(cfg->mux_reg); #ifdef CONFIG_OMAP_MUX_DEBUG debug = cfg->debug; @@ -238,7 +237,8 @@ void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) if (debug || warn) printk(KERN_WARNING "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", - cfg->name, omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg)); + cfg->name, omap_ctrl_base_get() + cfg->mux_reg, + orig, reg); } #else #define omap2_cfg_debug(x, y) do {} while (0) @@ -258,7 +258,7 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) if (cfg->pu_pd_val) reg |= OMAP24XX_PULL_UP; omap2_cfg_debug(cfg, reg); - omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); + omap_ctrl_writeb(reg, cfg->mux_reg); spin_unlock_irqrestore(&mux_spin_lock, flags); return 0; diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h index 5e1c4b53ee9d..c7f6cfa0b485 100644 --- a/arch/arm/mach-omap2/prcm-regs.h +++ b/arch/arm/mach-omap2/prcm-regs.h @@ -23,6 +23,20 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H #define __ARCH_ARM_MACH_OMAP2_PRCM_H +#ifdef CONFIG_ARCH_OMAP2420 +#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) +#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) +#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) +#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) +#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP24XX_SDRC_BASE (0x6D000000) +#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#endif + /* SET_PERFORMANCE_LEVEL PARAMETERS */ #define PRCM_HALF_SPEED 1 #define PRCM_FULL_SPEED 2 diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 90f530540c65..b12f423b8595 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -17,19 +17,27 @@ #include #include -#include "prcm-regs.h" +#include + +#include "prm.h" +#include "prm-regbits-24xx.h" extern void omap2_clk_prepare_for_reboot(void); u32 omap_prcm_get_reset_sources(void) { - return RM_RSTST_WKUP & 0x7f; + return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; } EXPORT_SYMBOL(omap_prcm_get_reset_sources); /* Resets clock rates and reboots the system. Only called from system.h */ void omap_prcm_arch_reset(char mode) { + u32 wkup; omap2_clk_prepare_for_reboot(); - RM_RSTCTRL_WKUP |= 2; + + if (cpu_is_omap24xx()) { + wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3; + prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL); + } } diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S index 16247d557853..46ccb9b8b583 100644 --- a/arch/arm/mach-omap2/sleep.S +++ b/arch/arm/mach-omap2/sleep.S @@ -26,19 +26,10 @@ #include #include -#define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10) -#define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50) -#define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80) -#define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500) -#define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520) -#define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540) -#define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544) +#include "sdrc.h" -#define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60) -#define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70) -#define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4) +/* First address of reserved address space? apparently valid for OMAP2 & 3 */ #define A_SDRC0_V (0xC0000000) -#define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8) .text @@ -126,17 +117,11 @@ loop2: ldmfd sp!, {r0 - r12, pc} @ restore regs and return A_SDRC_POWER: - .word A_SDRC_POWER_V + .word OMAP242X_SDRC_REGADDR(SDRC_POWER) A_SDRC0: .word A_SDRC0_V -A_CM_CLKSEL2_PLL_S: - .word A_CM_CLKSEL2_PLL_V -A_CM_CLKEN_PLL: - .word A_CM_CLKEN_PLL_V A_SDRC_DLLA_CTRL_S: - .word A_SDRC_DLLA_CTRL_V -A_SDRC_MANUAL_S: - .word A_SDRC_MANUAL_V + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) ENTRY(omap24xx_cpu_suspend_sz) .word . - omap24xx_cpu_suspend diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S index b27576690f8d..4a9e49140716 100644 --- a/arch/arm/mach-omap2/sram-fn.S +++ b/arch/arm/mach-omap2/sram-fn.S @@ -27,19 +27,11 @@ #include #include -#include "prcm-regs.h" +#include "sdrc.h" +#include "prm.h" +#include "cm.h" -#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010) - -#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544) -#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050) -#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080) -#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500) -#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520) -#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540) - -#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060) -#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4) +#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) .text @@ -131,11 +123,11 @@ volt_delay: /* relative load constants */ cm_clksel2_pll: - .word CM_CLKSEL2_PLL_V + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) sdrc_dlla_ctrl: - .word SDRC_DLLA_CTRL_V + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) prcm_voltctrl: - .word PRCM_VOLTCTRL_V + .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) prcm_mask_val: .word 0xFFFF3FFC timer_32ksynct_cr: @@ -225,13 +217,13 @@ volt_delay_c: mov pc, lr @ back to caller ddr_cm_clksel2_pll: - .word CM_CLKSEL2_PLL_V + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) ddr_sdrc_dlla_ctrl: - .word SDRC_DLLA_CTRL_V + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) ddr_sdrc_rfr_ctrl: - .word SDRC_RFR_CTRL_V + .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) ddr_prcm_voltctrl: - .word PRCM_VOLTCTRL_V + .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) ddr_prcm_mask_val: .word 0xFFFF3FFC ddr_timer_32ksynct: @@ -316,17 +308,17 @@ wait_dll_lock: ldmfd sp!, {r0-r12, pc} @ restore regs and return set_config: - .word PRCM_CLKCFG_CTRL_V + .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80) pll_ctl: - .word CM_CLKEN_PLL_V + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1) pll_stat: - .word CM_IDLEST_CKGEN_V + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1) pll_div: - .word CM_CLKSEL1_PLL_V + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL) sdrc_rfr: - .word SDRC_RFR_CTRL_V + .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) dlla_ctrl: - .word SDRC_DLLA_CTRL_V + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) ENTRY(sram_set_prcm_sz) .word . - sram_set_prcm diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 7f1cae16cfad..bd1cef2c3c14 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -27,11 +27,16 @@ #include #include +#include #include #include #include +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +# include "../mach-omap2/sdrc.h" +#endif + #define NO_LENGTH_CHECK 0xffffffff unsigned char omap_bootloader_tag[512]; @@ -171,8 +176,8 @@ console_initcall(omap_add_serial_console); #if defined(CONFIG_ARCH_OMAP16XX) #define TIMER_32K_SYNCHRONIZED 0xfffbc410 -#elif defined(CONFIG_ARCH_OMAP24XX) -#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10) +#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10) #endif #ifdef TIMER_32K_SYNCHRONIZED @@ -215,7 +220,13 @@ static int __init omap_init_clocksource_32k(void) static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; - if (cpu_is_omap16xx() || cpu_is_omap24xx()) { + if (cpu_is_omap16xx() || cpu_class_is_omap2()) { + struct clk *sync_32k_ick; + + sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); + if (sync_32k_ick) + clk_enable(sync_32k_ick); + clocksource_32k.mult = clocksource_hz2mult(32768, clocksource_32k.shift); @@ -227,3 +238,33 @@ static int __init omap_init_clocksource_32k(void) arch_initcall(omap_init_clocksource_32k); #endif /* TIMER_32K_SYNCHRONIZED */ + +/* Global address base setup code */ + +#if defined(CONFIG_ARCH_OMAP2420) +void __init omap2_set_globals_242x(void) +{ + omap2_sdrc_base = OMAP2420_SDRC_BASE; + omap2_sms_base = OMAP2420_SMS_BASE; + omap_ctrl_base_set(OMAP2420_CTRL_BASE); +} +#endif + +#if defined(CONFIG_ARCH_OMAP2430) +void __init omap2_set_globals_243x(void) +{ + omap2_sdrc_base = OMAP243X_SDRC_BASE; + omap2_sms_base = OMAP243X_SMS_BASE; + omap_ctrl_base_set(OMAP243X_CTRL_BASE); +} +#endif + +#if defined(CONFIG_ARCH_OMAP3430) +void __init omap2_set_globals_343x(void) +{ + omap2_sdrc_base = OMAP343X_SDRC_BASE; + omap2_sms_base = OMAP343X_SMS_BASE; + omap_ctrl_base_set(OMAP343X_CTRL_BASE); +} +#endif + diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index fa6881049903..fc7b80643852 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -88,4 +88,9 @@ extern int clk_get_usecount(struct clk *clk); #define CLOCK_IN_OMAP242X (1 << 25) #define CLOCK_IN_OMAP243X (1 << 26) +/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ +#define CORE_CLK_SRC_32K 0 +#define CORE_CLK_SRC_DPLL 1 +#define CORE_CLK_SRC_DPLL_X2 2 + #endif diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S index f6967c8df323..74cd57221c8e 100644 --- a/include/asm-arm/arch-omap/entry-macro.S +++ b/include/asm-arm/arch-omap/entry-macro.S @@ -68,7 +68,7 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =VA_IC_BASE + ldr \base, =OMAP2_VA_IC_BASE ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ cmp \irqnr, #0x0 bne 2222f diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index 289082d07f14..160578e1f557 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -80,6 +80,13 @@ #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ #define OMAP243X_GPMC_VIRT 0xFE000000 #define OMAP243X_GPMC_SIZE SZ_1M +#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE +#define OMAP243X_SDRC_VIRT 0xFD000000 +#define OMAP243X_SDRC_SIZE SZ_1M +#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE +#define OMAP243X_SMS_VIRT 0xFC000000 +#define OMAP243X_SMS_SIZE SZ_1M + #endif #define IO_OFFSET 0x90000000 @@ -88,16 +95,73 @@ #define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ /* DSP */ -#define DSP_MEM_24XX_PHYS OMAP24XX_DSP_MEM_BASE /* 0x58000000 */ +#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ #define DSP_MEM_24XX_VIRT 0xe0000000 #define DSP_MEM_24XX_SIZE 0x28000 -#define DSP_IPI_24XX_PHYS OMAP24XX_DSP_IPI_BASE /* 0x59000000 */ +#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */ #define DSP_IPI_24XX_VIRT 0xe1000000 #define DSP_IPI_24XX_SIZE SZ_4K -#define DSP_MMU_24XX_PHYS OMAP24XX_DSP_MMU_BASE /* 0x5a000000 */ +#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */ #define DSP_MMU_24XX_VIRT 0xe2000000 #define DSP_MMU_24XX_SIZE SZ_4K +#elif defined(CONFIG_ARCH_OMAP3) + +/* We map both L3 and L4 on OMAP3 */ +#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ +#define L3_34XX_VIRT 0xf8000000 +#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ + +#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */ +#define L4_34XX_VIRT 0xd8000000 +#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ + +/* + * Need to look at the Size 4M for L4. + * VPOM3430 was not working for Int controller + */ + +#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */ +#define L4_WK_34XX_VIRT 0xd8300000 +#define L4_WK_34XX_SIZE SZ_1M + +#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */ +#define L4_PER_34XX_VIRT 0xd9000000 +#define L4_PER_34XX_SIZE SZ_1M + +#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */ +#define L4_EMU_34XX_VIRT 0xe4000000 +#define L4_EMU_34XX_SIZE SZ_64M + +#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */ +#define OMAP34XX_GPMC_VIRT 0xFE000000 +#define OMAP34XX_GPMC_SIZE SZ_1M + +#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */ +#define OMAP343X_SMS_VIRT 0xFC000000 +#define OMAP343X_SMS_SIZE SZ_1M + +#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */ +#define OMAP343X_SDRC_VIRT 0xFD000000 +#define OMAP343X_SDRC_SIZE SZ_1M + + +#define IO_OFFSET 0x90000000 +#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ + +/* DSP */ +#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */ +#define DSP_MEM_34XX_VIRT 0xe0000000 +#define DSP_MEM_34XX_SIZE 0x28000 +#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */ +#define DSP_IPI_34XX_VIRT 0xe1000000 +#define DSP_IPI_34XX_SIZE SZ_4K +#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */ +#define DSP_MMU_34XX_VIRT 0xe2000000 +#define DSP_MMU_34XX_SIZE SZ_4K + #endif #ifndef __ASSEMBLER__ diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h index 14c0f9496579..b9fcaae287c8 100644 --- a/include/asm-arm/arch-omap/omap24xx.h +++ b/include/asm-arm/arch-omap/omap24xx.h @@ -1,3 +1,28 @@ +/* + * include/asm-arm/arch-omap/omap24xx.h + * + * This file contains the processor specific definitions + * of the TI OMAP24XX. + * + * Copyright (C) 2007 Texas Instruments. + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + #ifndef __ASM_ARCH_OMAP24XX_H #define __ASM_ARCH_OMAP24XX_H @@ -13,33 +38,70 @@ /* interrupt controller */ #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) -#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) #define OMAP24XX_IVA_INTC_BASE 0x40000000 #define IRQ_SIR_IRQ 0x0040 -#ifdef CONFIG_ARCH_OMAP2420 -#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) -#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) -#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) -#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) -#endif +#define OMAP2420_CTRL_BASE L4_24XX_BASE +#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) +#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) +#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) +#define OMAP2420_PRM_BASE OMAP2420_CM_BASE +#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) +#define OMAP2420_SMS_BASE 0x68008000 -#ifdef CONFIG_ARCH_OMAP2430 -#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) -#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000) -#define OMAP24XX_SDRC_BASE (0x6D000000) -#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) +#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP2430_PRM_BASE OMAP2430_CM_BASE + +#define OMAP243X_SMS_BASE 0x6C000000 +#define OMAP243X_SDRC_BASE 0x6D000000 #define OMAP243X_GPMC_BASE 0x6E000000 -#endif +#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000) +#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE +#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000) /* DSP SS */ -#define OMAP24XX_DSP_BASE 0x58000000 -#define OMAP24XX_DSP_MEM_BASE (OMAP24XX_DSP_BASE + 0x0) -#define OMAP24XX_DSP_IPI_BASE (OMAP24XX_DSP_BASE + 0x1000000) -#define OMAP24XX_DSP_MMU_BASE (OMAP24XX_DSP_BASE + 0x2000000) +#define OMAP2420_DSP_BASE 0x58000000 +#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0) +#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000) +#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000) + +#define OMAP243X_DSP_BASE 0x5C000000 +#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0) +#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000) /* Mailbox */ #define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) +/* Camera */ +#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000) + +/* Security */ +#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000) +#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000) +#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000) +#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000) +#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) +#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) + +#if defined(CONFIG_ARCH_OMAP2420) + +#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE +#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE +#define OMAP2_CM_BASE OMAP2420_CM_BASE +#define OMAP2_PRM_BASE OMAP2420_PRM_BASE +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) + +#elif defined(CONFIG_ARCH_OMAP2430) + +#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE +#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE +#define OMAP2_CM_BASE OMAP2430_CM_BASE +#define OMAP2_PRM_BASE OMAP2430_PRM_BASE +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) + +#endif + #endif /* __ASM_ARCH_OMAP24XX_H */ -- cgit v1.2.3-59-g8ed1b From 6b8858a972a0eff1dc1ab77b0fd9fc25387c217c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 18 Mar 2008 10:35:15 +0200 Subject: ARM: OMAP2: Change 24xx to use shared clock code and new reg access This patch changes 24xx to use shared clock code and new register access. Note that patch adds some temporary OLD_CK defines to keep patch more readable. These temporary defines will be removed in the next patch. Also not all clocks are changed in this patch to limit the size. Also, the patch fixes few incorrect clock defines in clock24xx.h. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/mach-omap2/clock24xx.c | 319 +++++++++++++++++++++++-------------- arch/arm/mach-omap2/clock24xx.h | 320 +++++++++++++++++++++++++------------- arch/arm/mach-omap2/memory.c | 48 ++++++ arch/arm/mach-omap2/memory.h | 2 + arch/arm/plat-omap/clock.c | 42 +++++ include/asm-arm/arch-omap/clock.h | 65 ++++++-- 8 files changed, 562 insertions(+), 238 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index be2b671552a6..a3b2507fcc58 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o mux.o \ +obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \ devices.o serial.o gpmc.o timer-gp.o # Power Management diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a921efd43a70..b76c9fc1b8e9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -122,7 +122,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (dd->div2_reg) { dpll = __raw_readl(dd->div2_reg); dpll_div = dpll & dd->div2_mask; - dpll_div >>= __fss(dd->div2_mask); + dpll_div >>= __ffs(dd->div2_mask); do_div(dpll_clk, dpll_div + 1); } diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 5c24781f6d9b..c3ccac1b7218 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -15,6 +15,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#undef DEBUG + #include #include #include @@ -23,29 +25,64 @@ #include #include -#include +#include +#include #include #include #include +#include -#include "prcm-regs.h" #include "memory.h" +#include "clock.h" #include "clock24xx.h" +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" -#undef DEBUG +/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ +#define EN_APLL_STOPPED 0 +#define EN_APLL_LOCKED 3 -//#define DOWN_VARIABLE_DPLL 1 /* Experimental */ +/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ +#define APLLS_CLKIN_19_2MHZ 0 +#define APLLS_CLKIN_13MHZ 2 +#define APLLS_CLKIN_12MHZ 3 + +/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ static struct prcm_config *curr_prcm_set; -static u32 curr_perf_level = PRCM_FULL_SPEED; static struct clk *vclk; static struct clk *sclk; /*------------------------------------------------------------------------- - * Omap2 specific clock functions + * Omap24xx specific clock functions *-------------------------------------------------------------------------*/ +static int omap2_enable_osc_ck(struct clk *clk) +{ + u32 pcc; + + pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); + + __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_PRCM_CLKSRC_CTRL); + + return 0; +} + +static void omap2_disable_osc_ck(struct clk *clk) +{ + u32 pcc; + + pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); + + __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_PRCM_CLKSRC_CTRL); +} + +#ifdef OLD_CK /* Recalculate SYST_CLK */ static void omap2_sys_clk_recalc(struct clk * clk) { @@ -55,17 +92,18 @@ static void omap2_sys_clk_recalc(struct clk * clk) clk->rate = (clk->parent->rate / div); propagate_rate(clk); } +#endif /* OLD_CK */ -static u32 omap2_get_dpll_rate(struct clk * tclk) +/* This actually returns the rate of core_ck, not dpll_ck. */ +static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) { long long dpll_clk; - int dpll_mult, dpll_div, amult; + u8 amult; + + dpll_clk = omap2_get_dpll_rate(tclk); - dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ - dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ - dpll_clk = (long long)tclk->parent->rate * dpll_mult; - do_div(dpll_clk, dpll_div + 1); - amult = CM_CLKSEL2_PLL & 0x3; + amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + amult &= OMAP24XX_CORE_CLK_SRC_MASK; dpll_clk *= amult; return dpll_clk; @@ -84,6 +122,7 @@ static void omap2_propagate_rate(struct clk * clk) propagate_rate(clk); } +#ifdef OLD_CK static void omap2_set_osc_ck(int enable) { if (enable) @@ -91,39 +130,40 @@ static void omap2_set_osc_ck(int enable) else PRCM_CLKSRC_CTRL |= 0x3 << 3; } +#endif /* OLD_CK */ /* Enable an APLL if off */ -static void omap2_clk_fixed_enable(struct clk *clk) +static int omap2_clk_fixed_enable(struct clk *clk) { - u32 cval, i=0; + u32 cval, apll_mask; - if (clk->enable_bit == 0xff) /* Parent will do it */ - return; + apll_mask = EN_APLL_LOCKED << clk->enable_bit; - cval = CM_CLKEN_PLL; + cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); - if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit)) - return; + if ((cval & apll_mask) == apll_mask) + return 0; /* apll already enabled */ - cval &= ~(0x3 << clk->enable_bit); - cval |= (0x3 << clk->enable_bit); - CM_CLKEN_PLL = cval; + cval &= ~apll_mask; + cval |= apll_mask; + cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); if (clk == &apll96_ck) - cval = (1 << 8); + cval = OMAP24XX_ST_96M_APLL; else if (clk == &apll54_ck) - cval = (1 << 6); + cval = OMAP24XX_ST_54M_APLL; - while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */ - ++i; - udelay(1); - if (i == 100000) { - printk(KERN_ERR "Clock %s didn't lock\n", clk->name); - break; - } - } + omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, + clk->name); + + /* + * REVISIT: Should we return an error code if omap2_wait_clock_ready() + * fails? + */ + return 0; } +#ifdef OLD_CK static void omap2_clk_wait_ready(struct clk *clk) { unsigned long reg, other_reg, st_reg; @@ -199,20 +239,19 @@ static int _omap2_clk_enable(struct clk * clk) return 0; } +#endif /* OLD_CK */ /* Stop APLL */ static void omap2_clk_fixed_disable(struct clk *clk) { u32 cval; - if(clk->enable_bit == 0xff) /* let parent off do it */ - return; - - cval = CM_CLKEN_PLL; - cval &= ~(0x3 << clk->enable_bit); - CM_CLKEN_PLL = cval; + cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval &= ~(EN_APLL_LOCKED << clk->enable_bit); + cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } +#ifdef OLD_CK /* Disables clock without considering parent dependencies or use count */ static void _omap2_clk_disable(struct clk *clk) { @@ -269,6 +308,7 @@ static void omap2_clk_disable(struct clk *clk) omap2_clk_disable(clk->parent); } } +#endif /* OLD_CK */ /* * Uses the current prcm set to tell if a rate is valid. @@ -276,9 +316,12 @@ static void omap2_clk_disable(struct clk *clk) */ static u32 omap2_dpll_round_rate(unsigned long target_rate) { - u32 high, low; + u32 high, low, core_clk_src; - if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */ + core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; + + if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ high = curr_prcm_set->dpll_speed * 2; low = curr_prcm_set->dpll_speed; } else { /* DPLL clockout x 2 */ @@ -300,6 +343,7 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate) } +#ifdef OLD_CK /* * Used for clocks that are part of CLKSEL_xyz governed clocks. * REVISIT: Maybe change to use clk->enable() functions like on omap1? @@ -486,55 +530,72 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force) return prev; } +#endif /* OLD_CK */ + +static void omap2_dpll_recalc(struct clk *clk) +{ + clk->rate = omap2_get_dpll_rate_24xx(clk); + + propagate_rate(clk); +} -static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) +static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate) { - u32 flags, cur_rate, low, mult, div, valid_rate, done_rate; + u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; + const struct dpll_data *dd; + unsigned long flags; int ret = -EINVAL; local_irq_save(flags); - cur_rate = omap2_get_dpll_rate(&dpll_ck); - mult = CM_CLKSEL2_PLL & 0x3; + cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); + mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult &= OMAP24XX_CORE_CLK_SRC_MASK; if ((rate == (cur_rate / 2)) && (mult == 2)) { - omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); + omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); } else if ((rate == (cur_rate * 2)) && (mult == 1)) { - omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); + omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); } else if (rate != cur_rate) { valid_rate = omap2_dpll_round_rate(rate); if (valid_rate != rate) goto dpll_exit; - if ((CM_CLKSEL2_PLL & 0x3) == 1) + if (mult == 1) low = curr_prcm_set->dpll_speed; else low = curr_prcm_set->dpll_speed / 2; - tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL; - tmpset.cm_clksel1_pll &= ~(0x3FFF << 8); + dd = clk->dpll_data; + if (!dd) + goto dpll_exit; + + tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); + tmpset.cm_clksel1_pll &= ~(dd->mult_mask | + dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL; - tmpset.cm_clksel2_pll &= ~0x3; + tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; if (rate > low) { - tmpset.cm_clksel2_pll |= 0x2; + tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; mult = ((rate / 2) / 1000000); - done_rate = PRCM_FULL_SPEED; + done_rate = CORE_CLK_SRC_DPLL_X2; } else { - tmpset.cm_clksel2_pll |= 0x1; + tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; mult = (rate / 1000000); - done_rate = PRCM_HALF_SPEED; + done_rate = CORE_CLK_SRC_DPLL; } - tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12)); + tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); + tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); /* Worst case */ - tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS; + tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ bypass = 1; - omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */ + omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ /* Force dll lock mode */ omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, @@ -544,7 +605,7 @@ static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) omap2_init_memory_params(omap2_dll_force_needed()); omap2_reprogram_sdrc(done_rate, 0); } - omap2_clksel_recalc(&dpll_ck); + omap2_dpll_recalc(&dpll_ck); ret = 0; dpll_exit: @@ -552,8 +613,13 @@ dpll_exit: return(ret); } -/* Just return the MPU speed */ -static void omap2_mpu_recalc(struct clk * clk) +/** + * omap2_table_mpu_recalc - just return the MPU speed + * @clk: virt_prcm_set struct clk + * + * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. + */ +static void omap2_table_mpu_recalc(struct clk *clk) { clk->rate = curr_prcm_set->mpu_speed; } @@ -565,9 +631,9 @@ static void omap2_mpu_recalc(struct clk * clk) * Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ -static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) +static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) { - struct prcm_config * ptr; + struct prcm_config *ptr; long highest_rate; if (clk != &virt_prcm_set) @@ -576,6 +642,8 @@ static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) highest_rate = -EINVAL; for (ptr = rate_table; ptr->mpu_speed; ptr++) { + if (!(ptr->flags & cpu_mask)) + continue; if (ptr->xtal_speed != sys_ck.rate) continue; @@ -588,6 +656,7 @@ static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) return highest_rate; } +#ifdef OLD_CK /* * omap2_convert_field_to_div() - turn field value into integer divider */ @@ -938,24 +1007,19 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) set_parent_error: return ret; } +#endif /* OLD_CK */ /* Sets basic clocks based on the specified rate */ -static int omap2_select_table_rate(struct clk * clk, unsigned long rate) +static int omap2_select_table_rate(struct clk *clk, unsigned long rate) { - u32 flags, cur_rate, done_rate, bypass = 0; - u8 cpu_mask = 0; + u32 cur_rate, done_rate, bypass = 0, tmp; struct prcm_config *prcm; unsigned long found_speed = 0; + unsigned long flags; if (clk != &virt_prcm_set) return -EINVAL; - /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */ - if (cpu_is_omap2420()) - cpu_mask = RATE_IN_242X; - else if (cpu_is_omap2430()) - cpu_mask = RATE_IN_243X; - for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; @@ -976,38 +1040,42 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) } curr_prcm_set = prcm; - cur_rate = omap2_get_dpll_rate(&dpll_ck); + cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); if (prcm->dpll_speed == cur_rate / 2) { - omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); + omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); } else if (prcm->dpll_speed == cur_rate * 2) { - omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); + omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); } else if (prcm->dpll_speed != cur_rate) { local_irq_save(flags); if (prcm->dpll_speed == prcm->xtal_speed) bypass = 1; - if ((prcm->cm_clksel2_pll & 0x3) == 2) - done_rate = PRCM_FULL_SPEED; + if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == + CORE_CLK_SRC_DPLL_X2) + done_rate = CORE_CLK_SRC_DPLL_X2; else - done_rate = PRCM_HALF_SPEED; + done_rate = CORE_CLK_SRC_DPLL; /* MPU divider */ - CM_CLKSEL_MPU = prcm->cm_clksel_mpu; + cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); /* dsp + iva1 div(2420), iva2.1(2430) */ - CM_CLKSEL_DSP = prcm->cm_clksel_dsp; + cm_write_mod_reg(prcm->cm_clksel_dsp, + OMAP24XX_DSP_MOD, CM_CLKSEL); - CM_CLKSEL_GFX = prcm->cm_clksel_gfx; + cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); /* Major subsystem dividers */ - CM_CLKSEL1_CORE = prcm->cm_clksel1_core; + tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); if (cpu_is_omap2430()) - CM_CLKSEL_MDM = prcm->cm_clksel_mdm; + cm_write_mod_reg(prcm->cm_clksel_mdm, + OMAP2430_MDM_MOD, CM_CLKSEL); /* x2 to enter init_mem */ - omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); + omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, bypass); @@ -1017,7 +1085,7 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) local_irq_restore(flags); } - omap2_clksel_recalc(&dpll_ck); + omap2_dpll_recalc(&dpll_ck); return 0; } @@ -1051,27 +1119,45 @@ static struct clk_functions omap2_clk_functions = { .clk_disable_unused = omap2_clk_disable_unused, }; -static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) +static u32 omap2_get_apll_clkin(void) { - u32 div, aplls, sclk = 13000000; + u32 aplls, sclk = 0; - aplls = CM_CLKSEL1_PLL; - aplls &= ((1 << 23) | (1 << 24) | (1 << 25)); - aplls >>= 23; /* Isolate field, 0,2,3 */ + aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls &= OMAP24XX_APLLS_CLKIN_MASK; + aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; - if (aplls == 0) + if (aplls == APLLS_CLKIN_19_2MHZ) sclk = 19200000; - else if (aplls == 2) + else if (aplls == APLLS_CLKIN_13MHZ) sclk = 13000000; - else if (aplls == 3) + else if (aplls == APLLS_CLKIN_12MHZ) sclk = 12000000; - div = PRCM_CLKSRC_CTRL; - div &= ((1 << 7) | (1 << 6)); - div >>= sys->rate_offset; + return sclk; +} + +static u32 omap2_get_sysclkdiv(void) +{ + u32 div; + + div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); + div &= OMAP_SYSCLKDIV_MASK; + div >>= OMAP_SYSCLKDIV_SHIFT; - osc->rate = sclk * div; - sys->rate = sclk; + return div; +} + +static void omap2_osc_clk_recalc(struct clk *clk) +{ + clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); + propagate_rate(clk); +} + +static void omap2_sys_clk_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); + propagate_rate(clk); } /* @@ -1100,8 +1186,7 @@ static int __init omap2_clk_arch_init(void) if (omap2_select_table_rate(&virt_prcm_set, mpurate)) printk(KERN_ERR "Could not find matching MPU rate\n"); - propagate_rate(&osc_ck); /* update main root fast */ - propagate_rate(&func_32k_ck); /* update main root slow */ + recalculate_root_clocks(); printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " "%ld.%01ld/%ld/%ld MHz\n", @@ -1115,13 +1200,21 @@ arch_initcall(omap2_clk_arch_init); int __init omap2_clk_init(void) { struct prcm_config *prcm; - struct clk ** clkp; + struct clk **clkp; u32 clkrate; + if (cpu_is_omap242x()) + cpu_mask = RATE_IN_242X; + else if (cpu_is_omap2430()) + cpu_mask = RATE_IN_243X; + clk_init(&omap2_clk_functions); - omap2_get_crystal_rate(&osc_ck, &sys_ck); - for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); + omap2_osc_clk_recalc(&osc_ck); + omap2_sys_clk_recalc(&sys_ck); + + for (clkp = onchip_24xx_clks; + clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); clkp++) { if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { @@ -1136,8 +1229,10 @@ int __init omap2_clk_init(void) } /* Check the MPU rate set by bootloader */ - clkrate = omap2_get_dpll_rate(&dpll_ck); + clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; if (prcm->xtal_speed != sys_ck.rate) continue; if (prcm->dpll_speed <= clkrate) @@ -1145,8 +1240,7 @@ int __init omap2_clk_init(void) } curr_prcm_set = prcm; - propagate_rate(&osc_ck); /* update main root fast */ - propagate_rate(&func_32k_ck); /* update main root slow */ + recalculate_root_clocks(); printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " "%ld.%01ld/%ld/%ld MHz\n", @@ -1157,16 +1251,7 @@ int __init omap2_clk_init(void) * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ - clk_enable(&sync_32k_ick); - clk_enable(&omapctrl_ick); - - /* Force the APLLs always active. The clocks are idled - * automatically by hardware. */ - clk_enable(&apll96_ck); - clk_enable(&apll54_ck); - - if (cpu_is_omap2430()) - clk_enable(&sdrc_ick); + clk_enable_init_clocks(); /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ vclk = clk_get(NULL, "virt_prcm_set"); diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 4f791866b910..9363c207f581 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -14,24 +14,29 @@ * published by the Free Software Foundation. */ -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK_H +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H -static void omap2_sys_clk_recalc(struct clk * clk); -static void omap2_clksel_recalc(struct clk * clk); -static void omap2_followparent_recalc(struct clk * clk); -static void omap2_propagate_rate(struct clk * clk); -static void omap2_mpu_recalc(struct clk * clk); +#include "clock.h" + +#include "prm.h" +#include "cm.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" + +static void omap2_table_mpu_recalc(struct clk * clk); static int omap2_select_table_rate(struct clk * clk, unsigned long rate); static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate); -static void omap2_clk_disable(struct clk *clk); static void omap2_sys_clk_recalc(struct clk * clk); -static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val); -static u32 omap2_clksel_get_divisor(struct clk *clk); - - -#define RATE_IN_242X (1 << 0) -#define RATE_IN_243X (1 << 1) +static void omap2_osc_clk_recalc(struct clk * clk); +static void omap2_sys_clk_recalc(struct clk * clk); +static void omap2_dpll_recalc(struct clk * clk); +static int omap2_clk_fixed_enable(struct clk * clk); +static void omap2_clk_fixed_disable(struct clk * clk); +static int omap2_enable_osc_ck(struct clk * clk); +static void omap2_disable_osc_ck(struct clk * clk); +static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate); /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP @@ -52,16 +57,6 @@ struct prcm_config { unsigned char flags; }; -/* Mask for clksel which support parent settign in set_rate */ -#define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \ - CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1) - -/* Mask for clksel regs which support rate operations */ -#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \ - CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \ - CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \ - CM_SYSCLKOUT_SEL1) - /* * The OMAP2 processor can be run at several discrete 'PRCM configurations'. * These configurations are characterized by voltage and speed for clocks. @@ -174,7 +169,7 @@ struct prcm_config { #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ -#define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */ +#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ @@ -182,6 +177,27 @@ struct prcm_config { #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX +/* 2420-PRCM I 660MHz core */ +#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ +#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ +#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ +#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ + RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ + RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ + RI_CLKSEL_L4 | RI_CLKSEL_L3 +#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ +#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU +#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ +#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ +#define RI_SYNC_DSP (1 << 7) /* Activate sync */ +#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ +#define RI_SYNC_IVA (0 << 13) /* Bypass sync */ +#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ + RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ + RI_CLKSEL_DSP +#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ +#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX + /* 2420-PRCM VII (boot) */ #define RVII_CLKSEL_L3 (1 << 0) #define RVII_CLKSEL_L4 (1 << 5) @@ -224,7 +240,6 @@ struct prcm_config { /* * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed - * #2 (ratio1) baseport-target * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz */ #define M5A_DPLL_MULT_12 (133 << 12) @@ -232,13 +247,13 @@ struct prcm_config { #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ MX_APLLS_CLIKIN_12 -#define M5A_DPLL_MULT_13 (266 << 12) -#define M5A_DPLL_DIV_13 (12 << 8) +#define M5A_DPLL_MULT_13 (61 << 12) +#define M5A_DPLL_DIV_13 (2 << 8) #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ MX_APLLS_CLIKIN_13 -#define M5A_DPLL_MULT_19 (180 << 12) -#define M5A_DPLL_DIV_19 (12 << 8) +#define M5A_DPLL_MULT_19 (55 << 12) +#define M5A_DPLL_DIV_19 (3 << 8) #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ MX_APLLS_CLIKIN_19_2 @@ -260,7 +275,27 @@ struct prcm_config { M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ MX_APLLS_CLIKIN_19_2 /* - * #4 (ratio2) + * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz + */ +#define M4_DPLL_MULT_12 (133 << 12) +#define M4_DPLL_DIV_12 (3 << 8) +#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 + +#define M4_DPLL_MULT_13 (399 << 12) +#define M4_DPLL_DIV_13 (12 << 8) +#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 + +#define M4_DPLL_MULT_19 (145 << 12) +#define M4_DPLL_DIV_19 (6 << 8) +#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 + +/* * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz */ #define M3_DPLL_MULT_12 (55 << 12) @@ -268,16 +303,41 @@ struct prcm_config { #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ MX_APLLS_CLIKIN_12 -#define M3_DPLL_MULT_13 (330 << 12) -#define M3_DPLL_DIV_13 (12 << 8) +#define M3_DPLL_MULT_13 (76 << 12) +#define M3_DPLL_DIV_13 (2 << 8) #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ MX_APLLS_CLIKIN_13 -#define M3_DPLL_MULT_19 (275 << 12) -#define M3_DPLL_DIV_19 (15 << 8) +#define M3_DPLL_MULT_19 (17 << 12) +#define M3_DPLL_DIV_19 (0 << 8) #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ MX_APLLS_CLIKIN_19_2 + +/* + * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz + */ +#define M2_DPLL_MULT_12 (55 << 12) +#define M2_DPLL_DIV_12 (1 << 8) +#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 + +/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, + * relock time issue */ +/* Core frequency changed from 330/165 to 329/164 MHz*/ +#define M2_DPLL_MULT_13 (76 << 12) +#define M2_DPLL_DIV_13 (2 << 8) +#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 + +#define M2_DPLL_MULT_19 (17 << 12) +#define M2_DPLL_DIV_19 (0 << 8) +#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 + /* boot (boot) */ #define MB_DPLL_MULT (1 << 12) #define MB_DPLL_DIV (0 << 8) @@ -300,6 +360,13 @@ struct prcm_config { * boot (boot) */ +/* PRCM I target DPLL = 2*330MHz = 660MHz */ +#define MI_DPLL_MULT_12 (55 << 12) +#define MI_DPLL_DIV_12 (1 << 8) +#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 + /* * 2420 Equivalent - mode registers * PRCM II , target DPLL = 2*300MHz = 600MHz @@ -335,28 +402,6 @@ struct prcm_config { #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) -/* - * These represent optimal values for common parts, it won't work for all. - * As long as you scale down, most parameters are still work, they just - * become sub-optimal. The RFR value goes in the opposite direction. If you - * don't adjust it down as your clock period increases the refresh interval - * will not be met. Setting all parameters for complete worst case may work, - * but may cut memory performance by 2x. Due to errata the DLLs need to be - * unlocked and their value needs run time calibration. A dynamic call is - * need for that as no single right value exists acorss production samples. - * - * Only the FULL speed values are given. Current code is such that rate - * changes must be made at DPLLoutx2. The actual value adjustment for low - * frequency operation will be handled by omap_set_performance() - * - * By having the boot loader boot up in the fastest L4 speed available likely - * will result in something which you can switch between. - */ -#define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) -#define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) -#define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ -#define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ - /* MPU speed defines */ #define S12M 12000000 #define S13M 13000000 @@ -365,15 +410,21 @@ struct prcm_config { #define S100M 100000000 #define S133M 133000000 #define S150M 150000000 +#define S164M 164000000 #define S165M 165000000 +#define S199M 199000000 #define S200M 200000000 #define S266M 266000000 #define S300M 300000000 +#define S329M 329000000 #define S330M 330000000 +#define S399M 399000000 #define S400M 400000000 #define S532M 532000000 #define S600M 600000000 +#define S658M 658000000 #define S660M 660000000 +#define S798M 798000000 /*------------------------------------------------------------------------- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. @@ -394,78 +445,93 @@ struct prcm_config { * Note: This table needs to be sorted, fastest to slowest. *-------------------------------------------------------------------------*/ static struct prcm_config rate_table[] = { + /* PRCM I - FAST */ + {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ + RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, + RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, + RATE_IN_242X}, + /* PRCM II - FAST */ {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, RATE_IN_242X}, {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, RATE_IN_242X}, /* PRCM III - FAST */ {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, RATE_IN_242X}, {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, RATE_IN_242X}, /* PRCM II - SLOW */ {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, RATE_IN_242X}, {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, RATE_IN_242X}, /* PRCM III - SLOW */ {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, RATE_IN_242X}, {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, RATE_IN_242X}, /* PRCM-VII (boot-bypass) */ {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, RATE_IN_242X}, /* PRCM-VII (boot-bypass) */ {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, RATE_IN_242X}, - /* PRCM #3 - ratio2 (ES2) - FAST */ - {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ + /* PRCM #4 - ratio2 (ES2.1) - FAST */ + {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, - R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, + R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_110MHz, + SDRC_RFR_CTRL_133MHz, + RATE_IN_243X}, + + /* PRCM #2 - ratio1 (ES2) - FAST */ + {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_165MHz, RATE_IN_243X}, /* PRCM #5a - ratio1 - FAST */ @@ -473,7 +539,7 @@ static struct prcm_config rate_table[] = { R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_133MHz, + SDRC_RFR_CTRL_133MHz, RATE_IN_243X}, /* PRCM #5b - ratio1 - FAST */ @@ -481,15 +547,23 @@ static struct prcm_config rate_table[] = { R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_100MHz, + SDRC_RFR_CTRL_100MHz, RATE_IN_243X}, - /* PRCM #3 - ratio2 (ES2) - SLOW */ - {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ + /* PRCM #4 - ratio1 (ES2.1) - SLOW */ + {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, - R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, + R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_110MHz, + SDRC_RFR_CTRL_133MHz, + RATE_IN_243X}, + + /* PRCM #2 - ratio1 (ES2) - SLOW */ + {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_165MHz, RATE_IN_243X}, /* PRCM #5a - ratio1 - SLOW */ @@ -497,7 +571,7 @@ static struct prcm_config rate_table[] = { R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_133MHz, + SDRC_RFR_CTRL_133MHz, RATE_IN_243X}, /* PRCM #5b - ratio1 - SLOW*/ @@ -505,7 +579,7 @@ static struct prcm_config rate_table[] = { R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_100MHz, + SDRC_RFR_CTRL_100MHz, RATE_IN_243X}, /* PRCM-boot/bypass */ @@ -513,7 +587,7 @@ static struct prcm_config rate_table[] = { RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_BYPASS, + SDRC_RFR_CTRL_BYPASS, RATE_IN_243X}, /* PRCM-boot/bypass */ @@ -521,7 +595,7 @@ static struct prcm_config rate_table[] = { RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, - V24XX_SDRC_RFR_CTRL_BYPASS, + SDRC_RFR_CTRL_BYPASS, RATE_IN_243X}, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, @@ -547,6 +621,7 @@ static struct prcm_config rate_table[] = { * clocks. *-------------------------------------------------------------------------*/ +#ifdef OLD_CK /* Base external input clocks */ static struct clk func_32k_ck = { .name = "func_32k_ck", @@ -554,7 +629,7 @@ static struct clk func_32k_ck = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | ALWAYS_ENABLED, }; - +#endif /* OLD_CK */ /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", @@ -570,10 +645,9 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .rate = 13000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, - .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */ .recalc = &omap2_sys_clk_recalc, }; - +#ifdef OLD_CK static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", .rate = 54000000, @@ -581,29 +655,43 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, .recalc = &omap2_propagate_rate, }; - +#endif /* OLD_CK */ /* * Analog domain root source clocks */ /* dpll_ck, is broken out in to special cases through clksel */ +/* REVISIT: Rate changes on dpll_ck trigger a full set change. ... + * deal with this + */ + +static const struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, +}; + static struct clk dpll_ck = { .name = "dpll_ck", .parent = &sys_ck, /* Can be func_32k also */ + .dpll_data = &dpll_dd, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1, - .recalc = &omap2_clksel_recalc, + RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_dpll_recalc, + .set_rate = &omap2_reprogram_dpll, }; static struct clk apll96_ck = { .name = "apll96_ck", .parent = &sys_ck, .rate = 96000000, - .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X | - RATE_FIXED | RATE_PROPAGATES, - .enable_reg = (void __iomem *)&CM_CLKEN_PLL, - .enable_bit = 0x2, - .recalc = &omap2_propagate_rate, + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | + RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .enable = &omap2_clk_fixed_enable, + .disable = &omap2_clk_fixed_disable, + .recalc = &propagate_rate, }; static struct clk apll54_ck = { @@ -611,15 +699,18 @@ static struct clk apll54_ck = { .parent = &sys_ck, .rate = 54000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | RATE_PROPAGATES, - .enable_reg = (void __iomem *)&CM_CLKEN_PLL, - .enable_bit = 0x6, - .recalc = &omap2_propagate_rate, + RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .enable = &omap2_clk_fixed_enable, + .disable = &omap2_clk_fixed_disable, + .recalc = &propagate_rate, }; /* * PRCM digital base sources */ +#ifdef OLD_CK static struct clk func_54m_ck = { .name = "func_54m_ck", .parent = &apll54_ck, /* can also be alt_clk */ @@ -631,15 +722,15 @@ static struct clk func_54m_ck = { .enable_bit = 0xff, .recalc = &omap2_propagate_rate, }; - +#endif /* OLD_CK */ static struct clk core_ck = { .name = "core_ck", .parent = &dpll_ck, /* can also be 32k */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | RATE_PROPAGATES, - .recalc = &omap2_propagate_rate, + .recalc = &followparent_recalc, }; - +#ifdef OLD_CK static struct clk sleep_ck = { /* sys_clk or 32k */ .name = "sleep_ck", .parent = &func_32k_ck, @@ -726,7 +817,7 @@ static struct clk emul_ck = { .recalc = &omap2_propagate_rate, }; - +#endif /* OLD_CK */ /* * MPU clock domain * Clocks: @@ -740,13 +831,17 @@ static struct clk emul_ck = { static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", .parent = &core_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL | - ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP | + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | + ALWAYS_ENABLED | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .rate_offset = 0, /* bits 0-4 */ + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; - +#ifdef OLD_CK /* * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain * Clocks: @@ -1933,7 +2028,7 @@ static struct clk mmchsdb2_fck = { .enable_bit = 17, .recalc = &omap2_followparent_recalc, }; - +#endif /* OLD_CK */ /* * This clock is a composite clock which does entire set changes then * forces a rebalance. It keys on the MPU speed, but it really could @@ -1953,11 +2048,10 @@ static struct clk virt_prcm_set = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ - .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */ .set_rate = &omap2_select_table_rate, .round_rate = &omap2_round_to_table_rate, }; - +#ifdef OLD_CK static struct clk *onchip_clks[] = { /* external root sources */ &func_32k_ck, @@ -2107,5 +2201,17 @@ static struct clk *onchip_clks[] = { &mmchsdb1_fck, &mmchsdb2_fck, }; +#endif /* OLD_CK */ + +static struct clk *onchip_24xx_clks[] __initdata = { + /* external root sources */ + &osc_ck, + &sys_ck, + /* internal analog sources */ + &dpll_ck, + &apll96_ck, + &apll54_ck, +}; #endif + diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index b56c1a082d92..12479081881a 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -53,6 +53,54 @@ u32 omap2_memory_get_type(void) return mem_timings.m_type; } +/* + * Check the DLL lock state, and return tue if running in unlock mode. + * This is needed to compensate for the shifted DLL value in unlock mode. + */ +u32 omap2_dll_force_needed(void) +{ + /* dlla and dllb are a set */ + u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); + + if ((dll_state & (1 << 2)) == (1 << 2)) + return 1; + else + return 0; +} + +/* + * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. + * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or + * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) + */ +u32 omap2_reprogram_sdrc(u32 level, u32 force) +{ + u32 dll_ctrl, m_type; + u32 prev = curr_perf_level; + unsigned long flags; + + if ((curr_perf_level == level) && !force) + return prev; + + if (level == CORE_CLK_SRC_DPLL) { + dll_ctrl = omap2_memory_get_slow_dll_ctrl(); + } else if (level == CORE_CLK_SRC_DPLL_X2) { + dll_ctrl = omap2_memory_get_fast_dll_ctrl(); + } else { + return prev; + } + + m_type = omap2_memory_get_type(); + + local_irq_save(flags); + __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); + omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); + curr_perf_level = level; + local_irq_restore(flags); + + return prev; +} + void omap2_init_memory_params(u32 force_lock_to_unlock_mode) { unsigned long dll_cnt; diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h index d212eea83a05..9a280b50a893 100644 --- a/arch/arm/mach-omap2/memory.h +++ b/arch/arm/mach-omap2/memory.h @@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); extern u32 omap2_memory_get_slow_dll_ctrl(void); extern u32 omap2_memory_get_fast_dll_ctrl(void); extern u32 omap2_memory_get_type(void); +u32 omap2_dll_force_needed(void); +u32 omap2_reprogram_sdrc(u32 level, u32 force); diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 0a603242f367..32a533ba9ada 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -304,6 +304,23 @@ void propagate_rate(struct clk * tclk) } } +/** + * recalculate_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + * Called at init. + */ +void recalculate_root_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &clocks, node) { + if (unlikely(!clkp->parent) && likely((u32)clkp->recalc)) + clkp->recalc(clkp); + } +} + int clk_register(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) @@ -358,6 +375,30 @@ void clk_allow_idle(struct clk *clk) } EXPORT_SYMBOL(clk_allow_idle); +void clk_enable_init_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &clocks, node) { + if (clkp->flags & ENABLE_ON_INIT) + clk_enable(clkp); + } +} +EXPORT_SYMBOL(clk_enable_init_clocks); + +#ifdef CONFIG_CPU_FREQ +void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) +{ + unsigned long flags; + + spin_lock_irqsave(&clockfw_lock, flags); + if (arch_clock->clk_init_cpufreq_table) + arch_clock->clk_init_cpufreq_table(table); + spin_unlock_irqrestore(&clockfw_lock, flags); +} +EXPORT_SYMBOL(clk_init_cpufreq_table); +#endif + /*-------------------------------------------------------------------------*/ #ifdef CONFIG_OMAP_RESET_CLOCKS @@ -396,3 +437,4 @@ int __init clk_init(struct clk_functions * custom_clocks) return 0; } + diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index fc7b80643852..ff0f94de2de9 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -14,6 +14,30 @@ #define __ARCH_ARM_OMAP_CLOCK_H struct module; +struct clk; + +#if defined(CONFIG_ARCH_OMAP2) + +struct clksel_rate { + u8 div; + u32 val; + u8 flags; +}; + +struct clksel { + struct clk *parent; + const struct clksel_rate *rates; +}; + +struct dpll_data { + void __iomem *mult_div1_reg; + u32 mult_mask; + u32 div1_mask; + void __iomem *div2_reg; + u32 div2_mask; +}; + +#endif struct clk { struct list_head node; @@ -25,8 +49,6 @@ struct clk { __u32 flags; void __iomem *enable_reg; __u8 enable_bit; - __u8 rate_offset; - __u8 src_offset; __s8 usecount; void (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); @@ -34,6 +56,16 @@ struct clk { void (*init)(struct clk *); int (*enable)(struct clk *); void (*disable)(struct clk *); +#if defined(CONFIG_ARCH_OMAP2) + u8 fixed_div; + void __iomem *clksel_reg; + u32 clksel_mask; + const struct clksel *clksel; + const struct dpll_data *dpll_data; +#else + __u8 rate_offset; + __u8 src_offset; +#endif }; struct clk_functions { @@ -54,10 +86,12 @@ extern int clk_init(struct clk_functions * custom_clocks); extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); extern void propagate_rate(struct clk *clk); +extern void recalculate_root_clocks(void); extern void followparent_recalc(struct clk * clk); extern void clk_allow_idle(struct clk *clk); extern void clk_deny_idle(struct clk *clk); extern int clk_get_usecount(struct clk *clk); +extern void clk_enable_init_clocks(void); /* Clock flags */ #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ @@ -71,22 +105,29 @@ extern int clk_get_usecount(struct clk *clk); #define CLOCK_NO_IDLE_PARENT (1 << 8) #define DELAYED_APP (1 << 9) /* Delay application of clock */ #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ -#define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */ -#define CM_DSP_SEL1 (1 << 12) -#define CM_GFX_SEL1 (1 << 13) -#define CM_MODEM_SEL1 (1 << 14) -#define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */ -#define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */ -#define CM_WKUP_SEL1 (1 << 17) -#define CM_PLL_SEL1 (1 << 18) -#define CM_PLL_SEL2 (1 << 19) -#define CM_SYSCLKOUT_SEL1 (1 << 20) +#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ +/* bits 13-20 are currently free */ #define CLOCK_IN_OMAP310 (1 << 21) #define CLOCK_IN_OMAP730 (1 << 22) #define CLOCK_IN_OMAP1510 (1 << 23) #define CLOCK_IN_OMAP16XX (1 << 24) #define CLOCK_IN_OMAP242X (1 << 25) #define CLOCK_IN_OMAP243X (1 << 26) +#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ +#define PARENT_CONTROLS_CLOCK (1 << 28) +#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ +#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ + +/* Clksel_rate flags */ +#define DEFAULT_RATE (1 << 0) +#define RATE_IN_242X (1 << 1) +#define RATE_IN_243X (1 << 2) +#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ + +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) + /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ #define CORE_CLK_SRC_32K 0 -- cgit v1.2.3-59-g8ed1b From b045d0809871eae4341e60a1db2b7d31703d8175 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 18 Mar 2008 11:24:28 +0200 Subject: ARM: OMAP2: Add 34xx clocks This patch defines 34xx clocks. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock34xx.h | 2704 +++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-omap/clock.h | 11 +- 2 files changed, 2713 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/clock34xx.h (limited to 'include') diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h new file mode 100644 index 000000000000..e4d73455f4c1 --- /dev/null +++ b/arch/arm/mach-omap2/clock34xx.h @@ -0,0 +1,2704 @@ +/* + * OMAP3 clock framework + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation + * + * Written by Paul Walmsley + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H + +#include + +#include "clock.h" +#include "cm.h" +#include "cm-regbits-34xx.h" +#include "prm.h" +#include "prm-regbits-34xx.h" + +static void omap3_dpll_recalc(struct clk *clk); +static void omap3_clkoutx2_recalc(struct clk *clk); + +/* + * DPLL1 supplies clock to the MPU. + * DPLL2 supplies clock to the IVA2. + * DPLL3 supplies CORE domain clocks. + * DPLL4 supplies peripheral clocks. + * DPLL5 supplies other peripheral clocks (USBHOST, USIM). + */ + +/* PRM CLOCKS */ + +/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ +static struct clk omap_32k_fck = { + .name = "omap_32k_fck", + .rate = 32768, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static struct clk secure_32k_fck = { + .name = "secure_32k_fck", + .rate = 32768, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +/* Virtual source clocks for osc_sys_ck */ +static struct clk virt_12m_ck = { + .name = "virt_12m_ck", + .rate = 12000000, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static struct clk virt_13m_ck = { + .name = "virt_13m_ck", + .rate = 13000000, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static struct clk virt_16_8m_ck = { + .name = "virt_16_8m_ck", + .rate = 16800000, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static struct clk virt_19_2m_ck = { + .name = "virt_19_2m_ck", + .rate = 19200000, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static struct clk virt_26m_ck = { + .name = "virt_26m_ck", + .rate = 26000000, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static struct clk virt_38_4m_ck = { + .name = "virt_38_4m_ck", + .rate = 38400000, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +static const struct clksel_rate osc_sys_12m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_13m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_16_8m_rates[] = { + { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_19_2m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_26m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_38_4m_rates[] = { + { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel osc_sys_clksel[] = { + { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, + { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, + { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, + { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, + { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, + { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, + { .parent = NULL }, +}; + +/* Oscillator clock */ +/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ +static struct clk osc_sys_ck = { + .name = "osc_sys_ck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP3430_PRM_CLKSEL, + .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, + .clksel = osc_sys_clksel, + /* REVISIT: deal with autoextclkmode? */ + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate div2_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel sys_clksel[] = { + { .parent = &osc_sys_ck, .rates = div2_rates }, + { .parent = NULL } +}; + +/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ +/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ +static struct clk sys_ck = { + .name = "sys_ck", + .parent = &osc_sys_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, + .clksel_mask = OMAP_SYSCLKDIV_MASK, + .clksel = sys_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk sys_altclk = { + .name = "sys_altclk", + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +/* Optional external clock input for some McBSPs */ +static struct clk mcbsp_clks = { + .name = "mcbsp_clks", + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &propagate_rate, +}; + +/* PRM EXTERNAL CLOCK OUTPUT */ + +static struct clk sys_clkout1 = { + .name = "sys_clkout1", + .parent = &osc_sys_ck, + .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, + .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* DPLLS */ + +/* CM CLOCKS */ + +/* DPLL1 */ +/* MPU clock source */ +/* Type: DPLL */ +static const struct dpll_data dpll1_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, + .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, + .div2_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), + .div2_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, + .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), + .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, + .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, +}; + +static struct clk dpll1_ck = { + .name = "dpll1_ck", + .parent = &sys_ck, + .dpll_data = &dpll1_dd, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap3_dpll_recalc, +}; + +/* + * REVISIT: This clock is never specifically defined in the 3430 TRM, + * although it is referenced - so this is a guess + */ +static struct clk emu_mpu_alwon_ck = { + .name = "emu_mpu_alwon_ck", + .parent = &dpll1_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +/* DPLL2 */ +/* IVA2 clock source */ +/* Type: DPLL */ + +static const struct dpll_data dpll2_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, + .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, + .div2_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), + .div2_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, + .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), + .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, + .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, +}; + +static struct clk dpll2_ck = { + .name = "dpll2_ck", + .parent = &sys_ck, + .dpll_data = &dpll2_dd, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap3_dpll_recalc, +}; + +/* DPLL3 */ +/* Source clock for all interfaces and for some device fclks */ +/* Type: DPLL */ +static const struct dpll_data dpll3_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, + .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, + .div2_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .div2_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, + .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, +}; + +static struct clk dpll3_ck = { + .name = "dpll3_ck", + .parent = &sys_ck, + .dpll_data = &dpll3_dd, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap3_dpll_recalc, +}; + +static const struct clksel_rate div16_dpll_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 5, .val = 5, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 7, .val = 7, .flags = RATE_IN_343X }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 9, .val = 9, .flags = RATE_IN_343X }, + { .div = 10, .val = 10, .flags = RATE_IN_343X }, + { .div = 11, .val = 11, .flags = RATE_IN_343X }, + { .div = 12, .val = 12, .flags = RATE_IN_343X }, + { .div = 13, .val = 13, .flags = RATE_IN_343X }, + { .div = 14, .val = 14, .flags = RATE_IN_343X }, + { .div = 15, .val = 15, .flags = RATE_IN_343X }, + { .div = 16, .val = 16, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel_rate div31_dpll3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, + { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, + { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, + { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, + { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, + { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, + { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, + { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, + { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, + { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, + { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, + { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, + { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, + { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, + { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, + { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, + { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, + { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, + { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, + { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, + { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, + { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, + { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, + { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, + { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, + { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, + { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, + { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, + { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, + { .div = 0 }, +}; + +static const struct clksel div31_dpll3m2_clksel[] = { + { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, + { .parent = NULL } +}; + +/* + * REVISIT: Not sure what to do about clksel & these M2 divider clocks. + * Shouldn't they be changed in SRAM? + * This should probably remain a 'read-only' clksel clock. + */ +static struct clk dpll3_m2_ck = { + .name = "dpll3_m2_ck", + .parent = &dpll3_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, + .clksel = div31_dpll3m2_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk core_ck = { + .name = "core_ck", + .parent = &dpll3_m2_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed + */ +static struct clk dpll3_x2_ck = { + .name = "dpll3_x2_ck", + .parent = &core_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap3_clkoutx2_recalc, +}; + +static struct clk dpll3_m2x2_ck = { + .name = "dpll3_m2x2_ck", + .parent = &dpll3_x2_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll3_m3x2_ck = { + .name = "dpll3_m3x2_ck", + .parent = &dpll3_x2_ck, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &followparent_recalc, +}; + +static const struct clksel div16_dpll3_clksel[] = { + { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +static struct clk emu_core_alwon_ck = { + .name = "emu_core_alwon_ck", + .parent = &dpll3_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_DIV_DPLL3_MASK, + .clksel = div16_dpll3_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +/* DPLL4 */ +/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ +/* Type: DPLL */ +static const struct dpll_data dpll4_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), + .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, + .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, + .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, +}; + +static struct clk dpll4_ck = { + .name = "dpll4_ck", + .parent = &sys_ck, + .dpll_data = &dpll4_dd, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap3_dpll_recalc, +}; + +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed + */ +static struct clk dpll4_x2_ck = { + .name = "dpll4_x2_ck", + .parent = &dpll4_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel div16_dpll4_clksel[] = { + { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m2x2_ck = { + .name = "dpll4_m2x2_ck", + .parent = &dpll4_x2_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_96M_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), + .clksel_mask = OMAP3430_DIV_96M_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk omap_96m_alwon_fck = { + .name = "omap_96m_alwon_fck", + .parent = &dpll4_m2x2_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk omap_96m_fck = { + .name = "omap_96m_fck", + .parent = &omap_96m_alwon_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk cm_96m_fck = { + .name = "cm_96m_fck", + .parent = &dpll4_m2x2_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m3x2_ck = { + .name = "dpll4_m3x2_ck", + .parent = &dpll4_x2_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_TV_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_TV_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate omap_54m_d4m3x2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate omap_54m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_54m_clksel[] = { + { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, + { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, + { .parent = NULL } +}; + +static struct clk omap_54m_fck = { + .name = "omap_54m_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_54M, + .clksel = omap_54m_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate omap_48m_96md2_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate omap_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_48m_clksel[] = { + { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, + { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, + { .parent = NULL } +}; + +static struct clk omap_48m_fck = { + .name = "omap_48m_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_48M, + .clksel = omap_48m_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk omap_12m_fck = { + .name = "omap_12m_fck", + .parent = &omap_48m_fck, + .fixed_div = 4, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_fixed_divisor_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m4x2_ck = { + .name = "dpll4_m4x2_ck", + .parent = &dpll4_x2_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m5x2_ck = { + .name = "dpll4_m5x2_ck", + .parent = &dpll4_x2_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m6x2_ck = { + .name = "dpll4_m6x2_ck", + .parent = &dpll4_x2_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_DIV_DPLL4_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk emu_per_alwon_ck = { + .name = "emu_per_alwon_ck", + .parent = &dpll4_m6x2_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +/* DPLL5 */ +/* Supplies 120MHz clock, USIM source clock */ +/* Type: DPLL */ +/* 3430ES2 only */ +static const struct dpll_data dpll5_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), + .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, + .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), + .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, + .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, +}; + +static struct clk dpll5_ck = { + .name = "dpll5_ck", + .parent = &sys_ck, + .dpll_data = &dpll5_dd, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &omap3_dpll_recalc, +}; + +static const struct clksel div16_dpll5m2_clksel[] = { + { .parent = &dpll5_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +static struct clk dpll5_m2_ck = { + .name = "dpll5_m2_ck", + .parent = &dpll5_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), + .clksel_mask = OMAP3430ES2_DIV_120M_MASK, + .clksel = div16_dpll5m2_clksel, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk omap_120m_fck = { + .name = "omap_120m_fck", + .parent = &dpll5_m2_ck, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +/* CM EXTERNAL CLOCK OUTPUTS */ + +static const struct clksel_rate clkout2_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel clkout2_src_clksel[] = { + { .parent = &core_ck, .rates = clkout2_src_core_rates }, + { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, + { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, + { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, + { .parent = NULL } +}; + +static struct clk clkout2_src_ck = { + .name = "clkout2_src_ck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP3430_CM_CLKOUT_CTRL, + .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, + .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, + .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, + .clksel = clkout2_src_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate sys_clkout2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 1, .flags = RATE_IN_343X }, + { .div = 4, .val = 2, .flags = RATE_IN_343X }, + { .div = 8, .val = 3, .flags = RATE_IN_343X }, + { .div = 16, .val = 4, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel sys_clkout2_clksel[] = { + { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, + { .parent = NULL }, +}; + +static struct clk sys_clkout2 = { + .name = "sys_clkout2", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, + .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, + .clksel = sys_clkout2_clksel, + .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +/* CM OUTPUT CLOCKS */ + +static struct clk corex2_fck = { + .name = "corex2_fck", + .parent = &dpll3_m2x2_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +/* DPLL power domain clock controls */ + +static const struct clksel div2_core_clksel[] = { + { .parent = &core_ck, .rates = div2_rates }, + { .parent = NULL } +}; + +/* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK, + but presuming that is an error, or at least an overgeneralization */ +/* REVISIT: Are these in DPLL power domain or CM power domain? docs + may be inconsistent here? */ +static struct clk dpll1_fck = { + .name = "dpll1_fck", + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, + .clksel = div2_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk dpll2_fck = { + .name = "dpll2_fck", + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, + .clksel = div2_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +/* Common interface clocks */ + +static struct clk l3_ick = { + .name = "l3_ick", + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_L3_MASK, + .clksel = div2_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel div2_l3_clksel[] = { + { .parent = &l3_ick, .rates = div2_rates }, + { .parent = NULL } +}; + +static struct clk l4_ick = { + .name = "l4_ick", + .parent = &l3_ick, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_L4_MASK, + .clksel = div2_l3_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, + +}; + +static const struct clksel div2_l4_clksel[] = { + { .parent = &l4_ick, .rates = div2_rates }, + { .parent = NULL } +}; + +static struct clk rm_ick = { + .name = "rm_ick", + .parent = &l4_ick, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_RM_MASK, + .clksel = div2_l4_clksel, + .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +/* GFX power domain */ + +/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ + +static const struct clksel gfx_l3_clksel[] = { + { .parent = &l3_ick, .rates = gfx_l3_rates }, + { .parent = NULL } +}; + +static struct clk gfx_l3_fck = { + .name = "gfx_l3_fck", + .parent = &l3_ick, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + .clksel_mask = OMAP_CLKSEL_GFX_MASK, + .clksel = gfx_l3_clksel, + .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gfx_l3_ick = { + .name = "gfx_l3_ick", + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &followparent_recalc, +}; + +static struct clk gfx_cg1_ck = { + .name = "gfx_cg1_ck", + .parent = &gfx_l3_fck, /* REVISIT: correct? */ + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES1_EN_2D_SHIFT, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &followparent_recalc, +}; + +static struct clk gfx_cg2_ck = { + .name = "gfx_cg2_ck", + .parent = &gfx_l3_fck, /* REVISIT: correct? */ + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES1_EN_3D_SHIFT, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &followparent_recalc, +}; + +/* SGX power domain - 3430ES2 only */ + +static const struct clksel_rate sgx_core_rates[] = { + { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 4, .val = 1, .flags = RATE_IN_343X }, + { .div = 6, .val = 2, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel_rate sgx_96m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel sgx_clksel[] = { + { .parent = &core_ck, .rates = sgx_core_rates }, + { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, + { .parent = NULL }, +}; + +static struct clk sgx_fck = { + .name = "sgx_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, + .clksel = sgx_clksel, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk sgx_ick = { + .name = "sgx_ick", + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +/* CORE power domain */ + +static struct clk d2d_26m_fck = { + .name = "d2d_26m_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &followparent_recalc, +}; + +static const struct clksel omap343x_gpt_clksel[] = { + { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = NULL} +}; + +static struct clk gpt10_fck = { + .name = "gpt10_fck", + .parent = &sys_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_GPT10_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt11_fck = { + .name = "gpt11_fck", + .parent = &sys_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_GPT11_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk cpefuse_fck = { + .name = "cpefuse_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk ts_fck = { + .name = "ts_fck", + .parent = &omap_32k_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_TS_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbtll_fck = { + .name = "usbtll_fck", + .parent = &omap_120m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +/* CORE 96M FCLK-derived clocks */ + +static struct clk core_96m_fck = { + .name = "core_96m_fck", + .parent = &omap_96m_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs3_fck = { + .name = "mmchs_fck", + .id = 3, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs2_fck = { + .name = "mmchs_fck", + .id = 2, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MMC2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mspro_fck = { + .name = "mspro_fck", + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MSPRO_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs1_fck = { + .name = "mmchs_fck", + .id = 1, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MMC1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk i2c3_fck = { + .name = "i2c_fck", + .id = 3, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk i2c2_fck = { + .name = "i2c_fck", + .id = 2, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk i2c1_fck = { + .name = "i2c_fck", + .id = 1, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* + * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; + * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. + */ +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel mcbsp_15_clksel[] = { + { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + +static struct clk mcbsp5_fck = { + .name = "mcbsp5_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, + .clksel = mcbsp_15_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mcbsp1_fck = { + .name = "mcbsp1_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, + .clksel = mcbsp_15_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +/* CORE_48M_FCK-derived clocks */ + +static struct clk core_48m_fck = { + .name = "core_48m_fck", + .parent = &omap_48m_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi4_fck = { + .name = "mcspi_fck", + .id = 4, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi3_fck = { + .name = "mcspi_fck", + .id = 3, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi2_fck = { + .name = "mcspi_fck", + .id = 2, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi1_fck = { + .name = "mcspi_fck", + .id = 1, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk uart2_fck = { + .name = "uart2_fck", + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk uart1_fck = { + .name = "uart1_fck", + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk fshostusb_fck = { + .name = "fshostusb_fck", + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &followparent_recalc, +}; + +/* CORE_12M_FCK based clocks */ + +static struct clk core_12m_fck = { + .name = "core_12m_fck", + .parent = &omap_12m_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk hdq_fck = { + .name = "hdq_fck", + .parent = &core_12m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_HDQ_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* DPLL3-derived clock */ + +static const struct clksel_rate ssi_ssr_corex2_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_clksel[] = { + { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, + { .parent = NULL } +}; + +static struct clk ssi_ssr_fck = { + .name = "ssi_ssr_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, + .clksel = ssi_ssr_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk ssi_sst_fck = { + .name = "ssi_sst_fck", + .parent = &ssi_ssr_fck, + .fixed_div = 2, + .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, + .recalc = &omap2_fixed_divisor_recalc, +}; + + + +/* CORE_L3_ICK based clocks */ + +static struct clk core_l3_ick = { + .name = "core_l3_ick", + .parent = &l3_ick, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk hsotgusb_ick = { + .name = "hsotgusb_ick", + .parent = &core_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk sdrc_ick = { + .name = "sdrc_ick", + .parent = &core_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SDRC_SHIFT, + .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, + .recalc = &followparent_recalc, +}; + +static struct clk gpmc_fck = { + .name = "gpmc_fck", + .parent = &core_l3_ick, + .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | + ENABLE_ON_INIT, + .recalc = &followparent_recalc, +}; + +/* SECURITY_L3_ICK based clocks */ + +static struct clk security_l3_ick = { + .name = "security_l3_ick", + .parent = &l3_ick, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk pka_ick = { + .name = "pka_ick", + .parent = &security_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_PKA_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* CORE_L4_ICK based clocks */ + +static struct clk core_l4_ick = { + .name = "core_l4_ick", + .parent = &l4_ick, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk usbtll_ick = { + .name = "usbtll_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs3_ick = { + .name = "mmchs_ick", + .id = 3, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +/* Intersystem Communication Registers - chassis mode only */ +static struct clk icr_ick = { + .name = "icr_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_ICR_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk aes2_ick = { + .name = "aes2_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_AES2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk sha12_ick = { + .name = "sha12_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SHA12_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk des2_ick = { + .name = "des2_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_DES2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs2_ick = { + .name = "mmchs_ick", + .id = 2, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MMC2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs1_ick = { + .name = "mmchs_ick", + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MMC1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mspro_ick = { + .name = "mspro_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MSPRO_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk hdq_ick = { + .name = "hdq_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HDQ_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi4_ick = { + .name = "mcspi_ick", + .id = 4, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi3_ick = { + .name = "mcspi_ick", + .id = 3, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi2_ick = { + .name = "mcspi_ick", + .id = 2, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi1_ick = { + .name = "mcspi_ick", + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk i2c3_ick = { + .name = "i2c_ick", + .id = 3, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk i2c2_ick = { + .name = "i2c_ick", + .id = 2, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk i2c1_ick = { + .name = "i2c_ick", + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk uart2_ick = { + .name = "uart2_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_UART2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk uart1_ick = { + .name = "uart1_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_UART1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt11_ick = { + .name = "gpt11_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_GPT11_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt10_ick = { + .name = "gpt10_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_GPT10_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp5_ick = { + .name = "mcbsp5_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp1_ick = { + .name = "mcbsp1_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk fac_ick = { + .name = "fac_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &followparent_recalc, +}; + +static struct clk mailboxes_ick = { + .name = "mailboxes_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk omapctrl_ick = { + .name = "omapctrl_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, + .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, + .recalc = &followparent_recalc, +}; + +/* SSI_L4_ICK based clocks */ + +static struct clk ssi_l4_ick = { + .name = "ssi_l4_ick", + .parent = &l4_ick, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +static struct clk ssi_ick = { + .name = "ssi_ick", + .parent = &ssi_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* REVISIT: Technically the TRM claims that this is CORE_CLK based, + * but l4_ick makes more sense to me */ + +static const struct clksel usb_l4_clksel[] = { + { .parent = &l4_ick, .rates = div2_rates }, + { .parent = NULL }, +}; + +static struct clk usb_l4_ick = { + .name = "usb_l4_ick", + .parent = &l4_ick, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, + .clksel = usb_l4_clksel, + .flags = CLOCK_IN_OMAP3430ES1, + .recalc = &omap2_clksel_recalc, +}; + +/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ + +/* SECURITY_L4_ICK2 based clocks */ + +static struct clk security_l4_ick2 = { + .name = "security_l4_ick2", + .parent = &l4_ick, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk aes1_ick = { + .name = "aes1_ick", + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_AES1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk rng_ick = { + .name = "rng_ick", + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_RNG_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk sha11_ick = { + .name = "sha11_ick", + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_SHA11_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk des1_ick = { + .name = "des1_ick", + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_DES1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* DSS */ + +static struct clk dss1_alwon_fck = { + .name = "dss1_alwon_fck", + .parent = &dpll4_m4x2_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk dss_tv_fck = { + .name = "dss_tv_fck", + .parent = &omap_54m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_TV_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk dss_96m_fck = { + .name = "dss_96m_fck", + .parent = &omap_96m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_TV_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk dss2_alwon_fck = { + .name = "dss2_alwon_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk dss_ick = { + /* Handles both L3 and L4 clocks */ + .name = "dss_ick", + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* CAM */ + +static struct clk cam_mclk = { + .name = "cam_mclk", + .parent = &dpll4_m5x2_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk cam_l3_ick = { + .name = "cam_l3_ick", + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk cam_l4_ick = { + .name = "cam_l4_ick", + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* USBHOST - 3430ES2 only */ + +static struct clk usbhost_120m_fck = { + .name = "usbhost_120m_fck", + .parent = &omap_120m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_48m_fck = { + .name = "usbhost_48m_fck", + .parent = &omap_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_l3_ick = { + .name = "usbhost_l3_ick", + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_l4_ick = { + .name = "usbhost_l4_ick", + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_sar_fck = { + .name = "usbhost_sar_fck", + .parent = &osc_sys_ck, + .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), + .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +/* WKUP */ + +static const struct clksel_rate usim_96m_rates[] = { + { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 8, .val = 5, .flags = RATE_IN_343X }, + { .div = 10, .val = 6, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel_rate usim_120m_rates[] = { + { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 16, .val = 9, .flags = RATE_IN_343X }, + { .div = 20, .val = 10, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel usim_clksel[] = { + { .parent = &omap_96m_fck, .rates = usim_96m_rates }, + { .parent = &omap_120m_fck, .rates = usim_120m_rates }, + { .parent = &sys_ck, .rates = div2_rates }, + { .parent = NULL }, +}; + +/* 3430ES2 only */ +static struct clk usim_fck = { + .name = "usim_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, + .clksel = usim_clksel, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt1_fck = { + .name = "gpt1_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT1_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk wkup_32k_fck = { + .name = "wkup_32k_fck", + .parent = &omap_32k_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &followparent_recalc, +}; + +static struct clk gpio1_fck = { + .name = "gpio1_fck", + .parent = &wkup_32k_fck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk wdt2_fck = { + .name = "wdt2_fck", + .parent = &wkup_32k_fck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_WDT2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk wkup_l4_ick = { + .name = "wkup_l4_ick", + .parent = &sys_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &followparent_recalc, +}; + +/* 3430ES2 only */ +/* Never specifically named in the TRM, so we have to infer a likely name */ +static struct clk usim_ick = { + .name = "usim_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk wdt2_ick = { + .name = "wdt2_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk wdt1_ick = { + .name = "wdt1_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio1_ick = { + .name = "gpio1_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk omap_32ksync_ick = { + .name = "omap_32ksync_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt12_ick = { + .name = "gpt12_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT12_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt1_ick = { + .name = "gpt1_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT1_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + + + +/* PER clock domain */ + +static struct clk per_96m_fck = { + .name = "per_96m_fck", + .parent = &omap_96m_alwon_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk per_48m_fck = { + .name = "per_48m_fck", + .parent = &omap_48m_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk uart3_fck = { + .name = "uart3_fck", + .parent = &per_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_UART3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt2_fck = { + .name = "gpt2_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT2_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt3_fck = { + .name = "gpt3_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT3_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt4_fck = { + .name = "gpt4_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT4_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt5_fck = { + .name = "gpt5_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT5_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt6_fck = { + .name = "gpt6_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT6_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt7_fck = { + .name = "gpt7_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT7_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt8_fck = { + .name = "gpt8_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT8_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt9_fck = { + .name = "gpt9_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT9_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, + .clksel = omap343x_gpt_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk per_32k_alwon_fck = { + .name = "per_32k_alwon_fck", + .parent = &omap_32k_fck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &followparent_recalc, +}; + +static struct clk gpio6_fck = { + .name = "gpio6_fck", + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT6_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio5_fck = { + .name = "gpio5_fck", + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT5_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio4_fck = { + .name = "gpio4_fck", + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT4_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio3_fck = { + .name = "gpio3_fck", + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio2_fck = { + .name = "gpio2_fck", + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk wdt3_fck = { + .name = "wdt3_fck", + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_WDT3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk per_l4_ick = { + .name = "per_l4_ick", + .parent = &l4_ick, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + +static struct clk gpio6_ick = { + .name = "gpio6_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO6_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio5_ick = { + .name = "gpio5_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO5_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio4_ick = { + .name = "gpio4_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO4_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio3_ick = { + .name = "gpio3_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpio2_ick = { + .name = "gpio2_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk wdt3_ick = { + .name = "wdt3_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk uart3_ick = { + .name = "uart3_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_UART3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt9_ick = { + .name = "gpt9_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT9_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt8_ick = { + .name = "gpt8_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT8_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt7_ick = { + .name = "gpt7_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT7_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt6_ick = { + .name = "gpt6_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT6_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt5_ick = { + .name = "gpt5_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT5_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt4_ick = { + .name = "gpt4_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT4_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt3_ick = { + .name = "gpt3_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk gpt2_ick = { + .name = "gpt2_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp2_ick = { + .name = "mcbsp2_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp3_ick = { + .name = "mcbsp3_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp4_ick = { + .name = "mcbsp4_ick", + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +static const struct clksel mcbsp_234_clksel[] = { + { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + +static struct clk mcbsp2_fck = { + .name = "mcbsp2_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mcbsp3_fck = { + .name = "mcbsp3_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mcbsp4_fck = { + .name = "mcbsp4_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .flags = CLOCK_IN_OMAP343X, + .recalc = &omap2_clksel_recalc, +}; + +/* EMU clocks */ + +/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ + +static const struct clksel_rate emu_src_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_per_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_mpu_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel emu_src_clksel[] = { + { .parent = &sys_ck, .rates = emu_src_sys_rates }, + { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, + { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, + { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, + { .parent = NULL }, +}; + +/* + * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only + * to switch the source of some of the EMU clocks. + * XXX Are there CLKEN bits for these EMU clks? + */ +static struct clk emu_src_ck = { + .name = "emu_src_ck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_MUX_CTRL_MASK, + .clksel = emu_src_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate pclk_emu_rates[] = { + { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel pclk_emu_clksel[] = { + { .parent = &emu_src_ck, .rates = pclk_emu_rates }, + { .parent = NULL }, +}; + +static struct clk pclk_fck = { + .name = "pclk_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, + .clksel = pclk_emu_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate pclkx2_emu_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel pclkx2_emu_clksel[] = { + { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, + { .parent = NULL }, +}; + +static struct clk pclkx2_fck = { + .name = "pclkx2_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, + .clksel = pclkx2_emu_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel atclk_emu_clksel[] = { + { .parent = &emu_src_ck, .rates = div2_rates }, + { .parent = NULL }, +}; + +static struct clk atclk_fck = { + .name = "atclk_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, + .clksel = atclk_emu_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk traceclk_src_fck = { + .name = "traceclk_src_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, + .clksel = emu_src_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate traceclk_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel traceclk_clksel[] = { + { .parent = &traceclk_src_fck, .rates = traceclk_rates }, + { .parent = NULL }, +}; + +static struct clk traceclk_fck = { + .name = "traceclk_fck", + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, + .clksel = traceclk_clksel, + .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .recalc = &omap2_clksel_recalc, +}; + +/* SR clocks */ + +/* SmartReflex fclk (VDD1) */ +static struct clk sr1_fck = { + .name = "sr1_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR1_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +/* SmartReflex fclk (VDD2) */ +static struct clk sr2_fck = { + .name = "sr2_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR2_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +static struct clk sr_l4_ick = { + .name = "sr_l4_ick", + .parent = &l4_ick, + .flags = CLOCK_IN_OMAP343X, + .recalc = &followparent_recalc, +}; + +/* SECURE_32K_FCK clocks */ + +static struct clk gpt12_fck = { + .name = "gpt12_fck", + .parent = &secure_32k_fck, + .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .recalc = &followparent_recalc, +}; + +static struct clk wdt1_fck = { + .name = "wdt1_fck", + .parent = &secure_32k_fck, + .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .recalc = &followparent_recalc, +}; + + +static struct clk *onchip_34xx_clks[] __initdata = { + &omap_32k_fck, + &virt_12m_ck, + &virt_13m_ck, + &virt_16_8m_ck, + &virt_19_2m_ck, + &virt_26m_ck, + &virt_38_4m_ck, + &osc_sys_ck, + &sys_ck, + &sys_altclk, + &mcbsp_clks, + &sys_clkout1, + &dpll1_ck, + &emu_mpu_alwon_ck, + &dpll2_ck, + &dpll3_ck, + &core_ck, + &dpll3_x2_ck, + &dpll3_m2_ck, + &dpll3_m2x2_ck, + &dpll3_m3x2_ck, + &emu_core_alwon_ck, + &dpll4_ck, + &dpll4_x2_ck, + &omap_96m_alwon_fck, + &omap_96m_fck, + &cm_96m_fck, + &omap_54m_fck, + &omap_48m_fck, + &omap_12m_fck, + &dpll4_m2x2_ck, + &dpll4_m3x2_ck, + &dpll4_m4x2_ck, + &dpll4_m5x2_ck, + &dpll4_m6x2_ck, + &emu_per_alwon_ck, + &dpll5_ck, + &dpll5_m2_ck, + &omap_120m_fck, + &clkout2_src_ck, + &sys_clkout2, + &corex2_fck, + &dpll1_fck, + &dpll2_fck, + &l3_ick, + &l4_ick, + &rm_ick, + &gfx_l3_fck, + &gfx_l3_ick, + &gfx_cg1_ck, + &gfx_cg2_ck, + &sgx_fck, + &sgx_ick, + &d2d_26m_fck, + &gpt10_fck, + &gpt11_fck, + &cpefuse_fck, + &ts_fck, + &usbtll_fck, + &core_96m_fck, + &mmchs3_fck, + &mmchs2_fck, + &mspro_fck, + &mmchs1_fck, + &i2c3_fck, + &i2c2_fck, + &i2c1_fck, + &mcbsp5_fck, + &mcbsp1_fck, + &core_48m_fck, + &mcspi4_fck, + &mcspi3_fck, + &mcspi2_fck, + &mcspi1_fck, + &uart2_fck, + &uart1_fck, + &fshostusb_fck, + &core_12m_fck, + &hdq_fck, + &ssi_ssr_fck, + &ssi_sst_fck, + &core_l3_ick, + &hsotgusb_ick, + &sdrc_ick, + &gpmc_fck, + &security_l3_ick, + &pka_ick, + &core_l4_ick, + &usbtll_ick, + &mmchs3_ick, + &icr_ick, + &aes2_ick, + &sha12_ick, + &des2_ick, + &mmchs2_ick, + &mmchs1_ick, + &mspro_ick, + &hdq_ick, + &mcspi4_ick, + &mcspi3_ick, + &mcspi2_ick, + &mcspi1_ick, + &i2c3_ick, + &i2c2_ick, + &i2c1_ick, + &uart2_ick, + &uart1_ick, + &gpt11_ick, + &gpt10_ick, + &mcbsp5_ick, + &mcbsp1_ick, + &fac_ick, + &mailboxes_ick, + &omapctrl_ick, + &ssi_l4_ick, + &ssi_ick, + &usb_l4_ick, + &security_l4_ick2, + &aes1_ick, + &rng_ick, + &sha11_ick, + &des1_ick, + &dss1_alwon_fck, + &dss_tv_fck, + &dss_96m_fck, + &dss2_alwon_fck, + &dss_ick, + &cam_mclk, + &cam_l3_ick, + &cam_l4_ick, + &usbhost_120m_fck, + &usbhost_48m_fck, + &usbhost_l3_ick, + &usbhost_l4_ick, + &usbhost_sar_fck, + &usim_fck, + &gpt1_fck, + &wkup_32k_fck, + &gpio1_fck, + &wdt2_fck, + &wkup_l4_ick, + &usim_ick, + &wdt2_ick, + &wdt1_ick, + &gpio1_ick, + &omap_32ksync_ick, + &gpt12_ick, + &gpt1_ick, + &per_96m_fck, + &per_48m_fck, + &uart3_fck, + &gpt2_fck, + &gpt3_fck, + &gpt4_fck, + &gpt5_fck, + &gpt6_fck, + &gpt7_fck, + &gpt8_fck, + &gpt9_fck, + &per_32k_alwon_fck, + &gpio6_fck, + &gpio5_fck, + &gpio4_fck, + &gpio3_fck, + &gpio2_fck, + &wdt3_fck, + &per_l4_ick, + &gpio6_ick, + &gpio5_ick, + &gpio4_ick, + &gpio3_ick, + &gpio2_ick, + &wdt3_ick, + &uart3_ick, + &gpt9_ick, + &gpt8_ick, + &gpt7_ick, + &gpt6_ick, + &gpt5_ick, + &gpt4_ick, + &gpt3_ick, + &gpt2_ick, + &mcbsp2_ick, + &mcbsp3_ick, + &mcbsp4_ick, + &mcbsp2_fck, + &mcbsp3_fck, + &mcbsp4_fck, + &emu_src_ck, + &pclk_fck, + &pclkx2_fck, + &atclk_fck, + &traceclk_src_fck, + &traceclk_fck, + &sr1_fck, + &sr2_fck, + &sr_l4_ick, + &secure_32k_fck, + &gpt12_fck, + &wdt1_fck, +}; + +#endif diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index ff0f94de2de9..0baa79acc0b7 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -16,7 +16,7 @@ struct module; struct clk; -#if defined(CONFIG_ARCH_OMAP2) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) struct clksel_rate { u8 div; @@ -35,6 +35,13 @@ struct dpll_data { u32 div1_mask; void __iomem *div2_reg; u32 div2_mask; +# if defined(CONFIG_ARCH_OMAP3) + void __iomem *control_reg; + u32 enable_mask; + u8 auto_recal_bit; + u8 recal_en_bit; + u8 recal_st_bit; +# endif }; #endif @@ -56,7 +63,7 @@ struct clk { void (*init)(struct clk *); int (*enable)(struct clk *); void (*disable)(struct clk *); -#if defined(CONFIG_ARCH_OMAP2) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) u8 fixed_div; void __iomem *clksel_reg; u32 clksel_mask; -- cgit v1.2.3-59-g8ed1b From 3760d31f11bfbd0ead9eaeb8573e0602437a9d7c Mon Sep 17 00:00:00 2001 From: Roman Tereshonkov Date: Thu, 13 Mar 2008 21:35:09 +0200 Subject: ARM: OMAP2: New DPLL clock framework These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 8 - arch/arm/mach-omap2/clock34xx.c | 4 +- arch/arm/mach-omap2/clock34xx.h | 503 +++++++++++++++++++++++++++------- arch/arm/mach-omap2/cm-regbits-34xx.h | 4 + include/asm-arm/arch-omap/clock.h | 2 - 5 files changed, 410 insertions(+), 111 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a5b9564ea78e..b57ffb5a22a5 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -111,14 +111,6 @@ u32 omap2_get_dpll_rate(struct clk *clk) dpll_clk = (long long)clk->parent->rate * dpll_mult; do_div(dpll_clk, dpll_div + 1); - /* 34XX only */ - if (dd->div2_reg) { - dpll = __raw_readl(dd->div2_reg); - dpll_div = dpll & dd->div2_mask; - dpll_div >>= __ffs(dd->div2_mask); - do_div(dpll_clk, dpll_div + 1); - } - return dpll_clk; } diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index f6c82a333815..b42bdd6079a5 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -212,10 +212,10 @@ int __init omap2_clk_init(void) recalculate_root_clocks(); - printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " + printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " "%ld.%01ld/%ld/%ld MHz\n", (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, - (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ; + (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); /* * Only enable those clocks we will need, let the drivers diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index e4d73455f4c1..cf4644a94b9b 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1,6 +1,10 @@ /* * OMAP3 clock framework * + * Virtual clocks are introduced as a convenient tools. + * They are sources for other clocks and not supposed + * to be requested from drivers directly. + * * Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2008 Nokia Corporation * @@ -203,6 +207,36 @@ static struct clk sys_clkout1 = { /* CM CLOCKS */ +static const struct clksel_rate dpll_bypass_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate dpll_locked_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate div16_dpll_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 5, .val = 5, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 7, .val = 7, .flags = RATE_IN_343X }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 9, .val = 9, .flags = RATE_IN_343X }, + { .div = 10, .val = 10, .flags = RATE_IN_343X }, + { .div = 11, .val = 11, .flags = RATE_IN_343X }, + { .div = 12, .val = 12, .flags = RATE_IN_343X }, + { .div = 13, .val = 13, .flags = RATE_IN_343X }, + { .div = 14, .val = 14, .flags = RATE_IN_343X }, + { .div = 15, .val = 15, .flags = RATE_IN_343X }, + { .div = 16, .val = 16, .flags = RATE_IN_343X }, + { .div = 0 } +}; + /* DPLL1 */ /* MPU clock source */ /* Type: DPLL */ @@ -210,8 +244,6 @@ static const struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, - .div2_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), - .div2_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, @@ -228,15 +260,37 @@ static struct clk dpll1_ck = { }; /* - * REVISIT: This clock is never specifically defined in the 3430 TRM, - * although it is referenced - so this is a guess + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed. */ -static struct clk emu_mpu_alwon_ck = { - .name = "emu_mpu_alwon_ck", +static struct clk dpll1_x2_ck = { + .name = "dpll1_x2_ck", .parent = &dpll1_ck, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .recalc = &followparent_recalc, + .recalc = &omap3_clkoutx2_recalc, +}; + +/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ +static const struct clksel div16_dpll1_x2m2_clksel[] = { + { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* + * Does not exist in the TRM - needed to separate the M2 divider from + * bypass selection in mpu_ck + */ +static struct clk dpll1_x2m2_ck = { + .name = "dpll1_x2m2_ck", + .parent = &dpll1_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), + .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, + .clksel = div16_dpll1_x2m2_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, }; /* DPLL2 */ @@ -247,8 +301,6 @@ static const struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, - .div2_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), - .div2_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, @@ -264,6 +316,28 @@ static struct clk dpll2_ck = { .recalc = &omap3_dpll_recalc, }; +static const struct clksel div16_dpll2_m2x2_clksel[] = { + { .parent = &dpll2_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* + * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT + * or CLKOUTX2. CLKOUT seems most plausible. + */ +static struct clk dpll2_m2_ck = { + .name = "dpll2_m2_ck", + .parent = &dpll2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, + OMAP3430_CM_CLKSEL2_PLL), + .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, + .clksel = div16_dpll2_m2x2_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + /* DPLL3 */ /* Source clock for all interfaces and for some device fclks */ /* Type: DPLL */ @@ -271,8 +345,6 @@ static const struct dpll_data dpll3_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, - .div2_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .div2_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, @@ -288,24 +360,16 @@ static struct clk dpll3_ck = { .recalc = &omap3_dpll_recalc, }; -static const struct clksel_rate div16_dpll_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 5, .val = 5, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, - { .div = 7, .val = 7, .flags = RATE_IN_343X }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, - { .div = 9, .val = 9, .flags = RATE_IN_343X }, - { .div = 10, .val = 10, .flags = RATE_IN_343X }, - { .div = 11, .val = 11, .flags = RATE_IN_343X }, - { .div = 12, .val = 12, .flags = RATE_IN_343X }, - { .div = 13, .val = 13, .flags = RATE_IN_343X }, - { .div = 14, .val = 14, .flags = RATE_IN_343X }, - { .div = 15, .val = 15, .flags = RATE_IN_343X }, - { .div = 16, .val = 16, .flags = RATE_IN_343X }, - { .div = 0 } +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed + */ +static struct clk dpll3_x2_ck = { + .name = "dpll3_x2_ck", + .parent = &dpll3_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap3_clkoutx2_recalc, }; static const struct clksel_rate div31_dpll3_rates[] = { @@ -349,9 +413,9 @@ static const struct clksel div31_dpll3m2_clksel[] = { }; /* - * REVISIT: Not sure what to do about clksel & these M2 divider clocks. - * Shouldn't they be changed in SRAM? - * This should probably remain a 'read-only' clksel clock. + * DPLL3 output M2 + * REVISIT: This DPLL output divider must be changed in SRAM, so until + * that code is ready, this should remain a 'read-only' clksel clock. */ static struct clk dpll3_m2_ck = { .name = "dpll3_m2_ck", @@ -365,58 +429,85 @@ static struct clk dpll3_m2_ck = { .recalc = &omap2_clksel_recalc, }; +static const struct clksel core_ck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + static struct clk core_ck = { .name = "core_ck", - .parent = &dpll3_m2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_CORE_CLK, + .clksel = core_ck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed - */ -static struct clk dpll3_x2_ck = { - .name = "dpll3_x2_ck", - .parent = &core_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, - .recalc = &omap3_clkoutx2_recalc, +static const struct clksel dpll3_m2x2_ck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } }; static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", - .parent = &dpll3_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_CORE_CLK, + .clksel = dpll3_m2x2_ck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static const struct clksel div16_dpll3_clksel[] = { + { .parent = &dpll3_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* This virtual clock is the source for dpll3_m3x2_ck */ +static struct clk dpll3_m3_ck = { + .name = "dpll3_m3_ck", + .parent = &dpll3_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_DIV_DPLL3_MASK, + .clksel = div16_dpll3_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll3_m3x2_ck = { .name = "dpll3_m3x2_ck", - .parent = &dpll3_x2_ck, + .parent = &dpll3_m3_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, - .recalc = &followparent_recalc, + .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel div16_dpll3_clksel[] = { - { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates }, +static const struct clksel emu_core_alwon_ck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, { .parent = NULL } }; static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", - .parent = &dpll3_x2_ck, + .parent = &dpll3_m3x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_DIV_DPLL3_MASK, - .clksel = div16_dpll3_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &followparent_recalc, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_CORE_CLK, + .clksel = emu_core_alwon_ck_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, }; /* DPLL4 */ @@ -443,7 +534,8 @@ static struct clk dpll4_ck = { /* * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed + * DPLL isn't bypassed -- + * XXX does this serve any downstream clocks? */ static struct clk dpll4_x2_ck = { .name = "dpll4_x2_ck", @@ -454,30 +546,49 @@ static struct clk dpll4_x2_ck = { }; static const struct clksel div16_dpll4_clksel[] = { - { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates }, + { .parent = &dpll4_ck, .rates = div16_dpll_rates }, { .parent = NULL } }; +/* This virtual clock is the source for dpll4_m2x2_ck */ +static struct clk dpll4_m2_ck = { + .name = "dpll4_m2_ck", + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), + .clksel_mask = OMAP3430_DIV_96M_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m2x2_ck = { .name = "dpll4_m2x2_ck", - .parent = &dpll4_x2_ck, - .init = &omap2_init_clksel_parent, + .parent = &dpll4_m2_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), - .clksel_mask = OMAP3430_DIV_96M_MASK, - .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, - .recalc = &omap2_clksel_recalc, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel omap_96m_alwon_fck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } }; static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", .parent = &dpll4_m2x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_PERIPH_CLK, + .clksel = omap_96m_alwon_fck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; static struct clk omap_96m_fck = { @@ -488,25 +599,63 @@ static struct clk omap_96m_fck = { .recalc = &followparent_recalc, }; +static const struct clksel cm_96m_fck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + static struct clk cm_96m_fck = { .name = "cm_96m_fck", .parent = &dpll4_m2x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_PERIPH_CLK, + .clksel = cm_96m_fck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, +}; + +/* This virtual clock is the source for dpll4_m3x2_ck */ +static struct clk dpll4_m3_ck = { + .name = "dpll4_m3_ck", + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_TV_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m3x2_ck = { .name = "dpll4_m3x2_ck", - .parent = &dpll4_x2_ck, + .parent = &dpll4_m3_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_TV_MASK, - .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel virt_omap_54m_fck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + +static struct clk virt_omap_54m_fck = { + .name = "virt_omap_54m_fck", + .parent = &dpll4_m3x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_PERIPH_CLK, + .clksel = virt_omap_54m_fck_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, .recalc = &omap2_clksel_recalc, }; @@ -521,7 +670,7 @@ static const struct clksel_rate omap_54m_alt_rates[] = { }; static const struct clksel omap_54m_clksel[] = { - { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, + { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, { .parent = NULL } }; @@ -573,46 +722,74 @@ static struct clk omap_12m_fck = { .recalc = &omap2_fixed_divisor_recalc, }; +/* This virstual clock is the source for dpll4_m4x2_ck */ +static struct clk dpll4_m4_ck = { + .name = "dpll4_m4_ck", + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m4x2_ck = { .name = "dpll4_m4x2_ck", - .parent = &dpll4_x2_ck, - .init = &omap2_init_clksel_parent, + .parent = &dpll4_m4_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, - .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap3_clkoutx2_recalc, +}; + +/* This virtual clock is the source for dpll4_m5x2_ck */ +static struct clk dpll4_m5_ck = { + .name = "dpll4_m5_ck", + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m5x2_ck = { .name = "dpll4_m5x2_ck", - .parent = &dpll4_x2_ck, - .init = &omap2_init_clksel_parent, + .parent = &dpll4_m5_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, - .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .recalc = &omap3_clkoutx2_recalc, +}; + +/* This virtual clock is the source for dpll4_m6x2_ck */ +static struct clk dpll4_m6_ck = { + .name = "dpll4_m6_ck", + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_DIV_DPLL4_MASK, + .clksel = div16_dpll4_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m6x2_ck = { .name = "dpll4_m6x2_ck", - .parent = &dpll4_x2_ck, + .parent = &dpll4_m6_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_DIV_DPLL4_MASK, - .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, - .recalc = &omap2_clksel_recalc, + .recalc = &omap3_clkoutx2_recalc, }; static struct clk emu_per_alwon_ck = { @@ -647,7 +824,7 @@ static struct clk dpll5_ck = { .recalc = &omap3_dpll_recalc, }; -static const struct clksel div16_dpll5m2_clksel[] = { +static const struct clksel div16_dpll5_clksel[] = { { .parent = &dpll5_ck, .rates = div16_dpll_rates }, { .parent = NULL } }; @@ -658,16 +835,27 @@ static struct clk dpll5_m2_ck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, - .clksel = div16_dpll5m2_clksel, + .clksel = div16_dpll5_clksel, .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; +static const struct clksel omap_120m_fck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + static struct clk omap_120m_fck = { .name = "omap_120m_fck", .parent = &dpll5_m2_ck, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, - .recalc = &followparent_recalc, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), + .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, + .clksel = omap_120m_fck_clksel, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, }; /* CM EXTERNAL CLOCK OUTPUTS */ @@ -753,10 +941,10 @@ static const struct clksel div2_core_clksel[] = { { .parent = NULL } }; -/* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK, - but presuming that is an error, or at least an overgeneralization */ -/* REVISIT: Are these in DPLL power domain or CM power domain? docs - may be inconsistent here? */ +/* + * REVISIT: Are these in DPLL power domain or CM power domain? docs + * may be inconsistent here? + */ static struct clk dpll1_fck = { .name = "dpll1_fck", .parent = &core_ck, @@ -769,6 +957,66 @@ static struct clk dpll1_fck = { .recalc = &omap2_clksel_recalc, }; +/* + * MPU clksel: + * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck + * derives from the high-frequency bypass clock originating from DPLL3, + * called 'dpll1_fck' + */ +static const struct clksel mpu_clksel[] = { + { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, + { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + +static struct clk mpu_ck = { + .name = "mpu_ck", + .parent = &dpll1_x2m2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, + .clksel = mpu_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ +static const struct clksel_rate arm_fck_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 1, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel arm_fck_clksel[] = { + { .parent = &mpu_ck, .rates = arm_fck_rates }, + { .parent = NULL } +}; + +static struct clk arm_fck = { + .name = "arm_fck", + .parent = &mpu_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, + .clksel = arm_fck_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + +/* + * REVISIT: This clock is never specifically defined in the 3430 TRM, + * although it is referenced - so this is a guess + */ +static struct clk emu_mpu_alwon_ck = { + .name = "emu_mpu_alwon_ck", + .parent = &mpu_ck, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &followparent_recalc, +}; + static struct clk dpll2_fck = { .name = "dpll2_fck", .parent = &core_ck, @@ -781,6 +1029,32 @@ static struct clk dpll2_fck = { .recalc = &omap2_clksel_recalc, }; +/* + * IVA2 clksel: + * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck + * derives from the high-frequency bypass clock originating from DPLL3, + * called 'dpll2_fck' + */ + +static const struct clksel iva2_clksel[] = { + { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, + { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + +static struct clk iva2_ck = { + .name = "iva2_ck", + .parent = &dpll2_m2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, + OMAP3430_CM_IDLEST_PLL), + .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, + .clksel = iva2_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +}; + /* Common interface clocks */ static struct clk l3_ick = { @@ -831,7 +1105,7 @@ static struct clk rm_ick = { /* GFX power domain */ -/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ +/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ static const struct clksel gfx_l3_clksel[] = { { .parent = &l3_ick, .rates = gfx_l3_rates }, @@ -1645,14 +1919,23 @@ static struct clk des1_ick = { }; /* DSS */ +static const struct clksel dss1_alwon_fck_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", .parent = &dpll4_m4x2_ck, + .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_PERIPH_CLK, + .clksel = dss1_alwon_fck_clksel, .flags = CLOCK_IN_OMAP343X, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; static struct clk dss_tv_fck = { @@ -1694,13 +1977,23 @@ static struct clk dss_ick = { /* CAM */ +static const struct clksel cam_mclk_clksel[] = { + { .parent = &sys_ck, .rates = dpll_bypass_rates }, + { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, + { .parent = NULL } +}; + static struct clk cam_mclk = { .name = "cam_mclk", .parent = &dpll4_m5x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_mask = OMAP3430_ST_PERIPH_CLK, + .clksel = cam_mclk_clksel, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; static struct clk cam_l3_ick = { @@ -2497,7 +2790,6 @@ static struct clk wdt1_fck = { .recalc = &followparent_recalc, }; - static struct clk *onchip_34xx_clks[] __initdata = { &omap_32k_fck, &virt_12m_ck, @@ -2512,13 +2804,16 @@ static struct clk *onchip_34xx_clks[] __initdata = { &mcbsp_clks, &sys_clkout1, &dpll1_ck, - &emu_mpu_alwon_ck, + &dpll1_x2_ck, + &dpll1_x2m2_ck, &dpll2_ck, + &dpll2_m2_ck, &dpll3_ck, &core_ck, &dpll3_x2_ck, &dpll3_m2_ck, &dpll3_m2x2_ck, + &dpll3_m3_ck, &dpll3_m3x2_ck, &emu_core_alwon_ck, &dpll4_ck, @@ -2526,13 +2821,19 @@ static struct clk *onchip_34xx_clks[] __initdata = { &omap_96m_alwon_fck, &omap_96m_fck, &cm_96m_fck, + &virt_omap_54m_fck, &omap_54m_fck, &omap_48m_fck, &omap_12m_fck, + &dpll4_m2_ck, &dpll4_m2x2_ck, + &dpll4_m3_ck, &dpll4_m3x2_ck, + &dpll4_m4_ck, &dpll4_m4x2_ck, + &dpll4_m5_ck, &dpll4_m5x2_ck, + &dpll4_m6_ck, &dpll4_m6x2_ck, &emu_per_alwon_ck, &dpll5_ck, @@ -2542,7 +2843,11 @@ static struct clk *onchip_34xx_clks[] __initdata = { &sys_clkout2, &corex2_fck, &dpll1_fck, + &mpu_ck, + &arm_fck, + &emu_mpu_alwon_ck, &dpll2_fck, + &iva2_ck, &l3_ick, &l4_ick, &rm_ick, diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 317040887152..9249129a5f46 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -115,6 +115,10 @@ /* CM_IDLEST_PLL_MPU */ #define OMAP3430_ST_MPU_CLK (1 << 0) +#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) + +/* CM_IDLEST_PLL_MPU */ +#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) /* CM_AUTOIDLE_PLL_MPU */ #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 0baa79acc0b7..57523bdb642b 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -33,8 +33,6 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - void __iomem *div2_reg; - u32 div2_mask; # if defined(CONFIG_ARCH_OMAP3) void __iomem *control_reg; u32 enable_mask; -- cgit v1.2.3-59-g8ed1b