From e400bae98499583767da58fb0a1b9ad3e24fcb86 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 21 Jun 2005 17:15:56 -0700 Subject: [PATCH] mips: add vr41xx gpio support Add vr41xx gpio support. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-mips/vr41xx/giu.h | 69 ++++++++++++++++++++++++++++++++++++++++ include/asm-mips/vr41xx/vr41xx.h | 35 -------------------- 2 files changed, 69 insertions(+), 35 deletions(-) create mode 100644 include/asm-mips/vr41xx/giu.h (limited to 'include') diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h new file mode 100644 index 000000000000..8590885a7638 --- /dev/null +++ b/include/asm-mips/vr41xx/giu.h @@ -0,0 +1,69 @@ +/* + * Include file for NEC VR4100 series General-purpose I/O Unit. + * + * Copyright (C) 2005 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __NEC_VR41XX_GIU_H +#define __NEC_VR41XX_GIU_H + +typedef enum { + IRQ_TRIGGER_LEVEL, + IRQ_TRIGGER_EDGE, + IRQ_TRIGGER_EDGE_FALLING, + IRQ_TRIGGER_EDGE_RISING, +} irq_trigger_t; + +typedef enum { + IRQ_SIGNAL_THROUGH, + IRQ_SIGNAL_HOLD, +} irq_signal_t; + +extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal); + +typedef enum { + IRQ_LEVEL_LOW, + IRQ_LEVEL_HIGH, +} irq_level_t; + +extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level); + +typedef enum { + GPIO_DATA_LOW, + GPIO_DATA_HIGH, + GPIO_DATA_INVAL, +} gpio_data_t; + +extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin); +extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data); + +typedef enum { + GPIO_INPUT, + GPIO_OUTPUT, + GPIO_OUTPUT_DISABLE, +} gpio_direction_t; + +extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir); + +typedef enum { + GPIO_PULL_DOWN, + GPIO_PULL_UP, + GPIO_PULL_DISABLE, +} gpio_pull_t; + +extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull); + +#endif /* __NEC_VR41XX_GIU_H */ diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h index ad0d1ea144f0..7d41e44463f9 100644 --- a/include/asm-mips/vr41xx/vr41xx.h +++ b/include/asm-mips/vr41xx/vr41xx.h @@ -126,7 +126,6 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define GIU_IRQ_BASE 40 #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ #define GIU_IRQ_LAST GIU_IRQ(31) -#define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */ extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); @@ -197,38 +196,4 @@ extern void vr41xx_disable_csiint(uint16_t mask); extern void vr41xx_enable_bcuint(void); extern void vr41xx_disable_bcuint(void); -/* - * General-Purpose I/O Unit - */ -enum { - TRIGGER_LEVEL, - TRIGGER_EDGE, - TRIGGER_EDGE_FALLING, - TRIGGER_EDGE_RISING -}; - -enum { - SIGNAL_THROUGH, - SIGNAL_HOLD -}; - -extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold); - -enum { - LEVEL_LOW, - LEVEL_HIGH -}; - -extern void vr41xx_set_irq_level(int pin, int level); - -enum { - PIO_INPUT, - PIO_OUTPUT -}; - -enum { - DATA_LOW, - DATA_HIGH -}; - #endif /* __NEC_VR41XX_H */ -- cgit v1.2.3-59-g8ed1b