From 0c8ba9d28518822d612de23fc9020b2a66a0228c Mon Sep 17 00:00:00 2001 From: Jayachandran B Date: Fri, 18 Dec 2015 15:12:03 +0530 Subject: ASoC: Intel: Skylake: fix reset controller sequencing MISCBDCGE is a new register for Misc Backbone clock gate control which is useful to control while resetting the link and ensuring controller is in required state so add API to control it HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add that while doing init chip and reset sequence. Signed-off-by: Jayachandran B Signed-off-by: Vinod Koul Signed-off-by: Mark Brown --- sound/soc/intel/skylake/skl-sst-ipc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'sound/soc/intel/skylake/skl-sst-ipc.h') diff --git a/sound/soc/intel/skylake/skl-sst-ipc.h b/sound/soc/intel/skylake/skl-sst-ipc.h index 1bbcdb471cf2..d59d1ba62a43 100644 --- a/sound/soc/intel/skylake/skl-sst-ipc.h +++ b/sound/soc/intel/skylake/skl-sst-ipc.h @@ -55,6 +55,11 @@ struct skl_sst { /* IPC messaging */ struct sst_generic_ipc ipc; + + /* callback for miscbdge */ + void (*enable_miscbdcge)(struct device *dev, bool enable); + /*Is CGCTL.MISCBDCGE disabled*/ + bool miscbdcg_disabled; }; struct skl_ipc_init_instance_msg { -- cgit v1.2.3-59-g8ed1b