From 92a9f14b8b8e5ade5b49bcd6b95fc05f85a39e90 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 30 May 2012 21:16:16 +0100 Subject: Fix comment typo multipy -> multiply Signed-off-by: Ralf Baechle Signed-off-by: Jiri Kosina --- sound/oss/vwsnd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/oss/vwsnd.c b/sound/oss/vwsnd.c index 643f1113b1d8..7e814a5c3677 100644 --- a/sound/oss/vwsnd.c +++ b/sound/oss/vwsnd.c @@ -438,7 +438,7 @@ static __inline__ void li_writeb(lithium_t *lith, int off, unsigned char val) * * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)). * As long as mask is constant, we trust the compiler will change the - * multipy and divide into shifts. + * multiply and divide into shifts. */ #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask)) -- cgit v1.2.3-59-g8ed1b From 0336553e4a8c1fefc11aa5656cebf2ce80657322 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 May 2012 14:51:19 -0600 Subject: ASoC: tegra: simplify Kconfig dependencies The Tegra ASoC machine drivers only depend on Tegra architecture support to compile, not specific board support. Remove Kconfig dependencies on any particular board. This is required since Kconfig options for boards are going away given the migration to device tree. Signed-off-by: Stephen Warren Acked-by: Mark Brown --- arch/arm/mach-tegra/Kconfig | 3 --- sound/soc/tegra/Kconfig | 10 +--------- 2 files changed, 1 insertion(+), 12 deletions(-) (limited to 'sound') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 6a113a9bb87a..7c407393cd07 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -63,7 +63,6 @@ comment "Tegra board type" config MACH_HARMONY bool "Harmony board" depends on ARCH_TEGRA_2x_SOC - select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Harmony development platform @@ -71,7 +70,6 @@ config MACH_KAEN bool "Kaen board" depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD - select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for the Kaen version of Seaboard @@ -84,7 +82,6 @@ config MACH_PAZ00 config MACH_SEABOARD bool "Seaboard board" depends on ARCH_TEGRA_2x_SOC - select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Seaboard development platform. It will also be included for some of the derivative boards that diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig index c1c8e955f4d3..76dc230f2bb0 100644 --- a/sound/soc/tegra/Kconfig +++ b/sound/soc/tegra/Kconfig @@ -58,17 +58,9 @@ config SND_SOC_TEGRA_WM8753 Say Y or M here if you want to add support for SoC audio on Tegra boards using the WM8753 codec, such as Whistler. -config MACH_HAS_SND_SOC_TEGRA_WM8903 - bool - help - Machines that use the SND_SOC_TEGRA_WM8903 driver should select - this config option, in order to allow the user to enable - SND_SOC_TEGRA_WM8903. - config SND_SOC_TEGRA_WM8903 tristate "SoC Audio support for Tegra boards using a WM8903 codec" depends on SND_SOC_TEGRA && I2C - depends on MACH_HAS_SND_SOC_TEGRA_WM8903 select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC select SND_SOC_TEGRA30_I2S if ARCH_TEGRA_3x_SOC select SND_SOC_WM8903 @@ -79,7 +71,7 @@ config SND_SOC_TEGRA_WM8903 config SND_SOC_TEGRA_TRIMSLICE tristate "SoC Audio support for TrimSlice board" - depends on SND_SOC_TEGRA && MACH_TRIMSLICE && I2C + depends on SND_SOC_TEGRA && I2C select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC select SND_SOC_TLV320AIC23 help -- cgit v1.2.3-59-g8ed1b From 65d2bdd343bd07c8de7df7352186bfe57994b5e7 Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Tue, 5 Jun 2012 09:59:42 +0530 Subject: ASoC: tegra: add clk_prepare/clk_unprepare Use clk_prepare/clk_unprepare as required by the generic clk framework. Signed-off-by: Prashant Gaikwad Signed-off-by: Stephen Warren Acked-by: Mark Brown --- sound/soc/tegra/tegra20_i2s.c | 4 ++-- sound/soc/tegra/tegra20_spdif.c | 4 ++-- sound/soc/tegra/tegra30_ahub.c | 8 ++++---- sound/soc/tegra/tegra30_i2s.c | 4 ++-- sound/soc/tegra/tegra_asoc_utils.c | 12 ++++++------ 5 files changed, 16 insertions(+), 16 deletions(-) (limited to 'sound') diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c index 0c7af63d444b..1647dbfe74b5 100644 --- a/sound/soc/tegra/tegra20_i2s.c +++ b/sound/soc/tegra/tegra20_i2s.c @@ -62,7 +62,7 @@ static int tegra20_i2s_runtime_suspend(struct device *dev) { struct tegra20_i2s *i2s = dev_get_drvdata(dev); - clk_disable(i2s->clk_i2s); + clk_disable_unprepare(i2s->clk_i2s); return 0; } @@ -72,7 +72,7 @@ static int tegra20_i2s_runtime_resume(struct device *dev) struct tegra20_i2s *i2s = dev_get_drvdata(dev); int ret; - ret = clk_enable(i2s->clk_i2s); + ret = clk_prepare_enable(i2s->clk_i2s); if (ret) { dev_err(dev, "clk_enable failed: %d\n", ret); return ret; diff --git a/sound/soc/tegra/tegra20_spdif.c b/sound/soc/tegra/tegra20_spdif.c index f9b57418bd08..2262e4fdec2a 100644 --- a/sound/soc/tegra/tegra20_spdif.c +++ b/sound/soc/tegra/tegra20_spdif.c @@ -54,7 +54,7 @@ static int tegra20_spdif_runtime_suspend(struct device *dev) { struct tegra20_spdif *spdif = dev_get_drvdata(dev); - clk_disable(spdif->clk_spdif_out); + clk_disable_unprepare(spdif->clk_spdif_out); return 0; } @@ -64,7 +64,7 @@ static int tegra20_spdif_runtime_resume(struct device *dev) struct tegra20_spdif *spdif = dev_get_drvdata(dev); int ret; - ret = clk_enable(spdif->clk_spdif_out); + ret = clk_prepare_enable(spdif->clk_spdif_out); if (ret) { dev_err(dev, "clk_enable failed: %d\n", ret); return ret; diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c index 57cd419f743e..1efb822d3916 100644 --- a/sound/soc/tegra/tegra30_ahub.c +++ b/sound/soc/tegra/tegra30_ahub.c @@ -56,8 +56,8 @@ static int tegra30_ahub_runtime_suspend(struct device *dev) regcache_cache_only(ahub->regmap_apbif, true); regcache_cache_only(ahub->regmap_ahub, true); - clk_disable(ahub->clk_apbif); - clk_disable(ahub->clk_d_audio); + clk_disable_unprepare(ahub->clk_apbif); + clk_disable_unprepare(ahub->clk_d_audio); return 0; } @@ -77,12 +77,12 @@ static int tegra30_ahub_runtime_resume(struct device *dev) { int ret; - ret = clk_enable(ahub->clk_d_audio); + ret = clk_prepare_enable(ahub->clk_d_audio); if (ret) { dev_err(dev, "clk_enable d_audio failed: %d\n", ret); return ret; } - ret = clk_enable(ahub->clk_apbif); + ret = clk_prepare_enable(ahub->clk_apbif); if (ret) { dev_err(dev, "clk_enable apbif failed: %d\n", ret); clk_disable(ahub->clk_d_audio); diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c index 8596032985dc..d308faaae148 100644 --- a/sound/soc/tegra/tegra30_i2s.c +++ b/sound/soc/tegra/tegra30_i2s.c @@ -62,7 +62,7 @@ static int tegra30_i2s_runtime_suspend(struct device *dev) regcache_cache_only(i2s->regmap, true); - clk_disable(i2s->clk_i2s); + clk_disable_unprepare(i2s->clk_i2s); return 0; } @@ -72,7 +72,7 @@ static int tegra30_i2s_runtime_resume(struct device *dev) struct tegra30_i2s *i2s = dev_get_drvdata(dev); int ret; - ret = clk_enable(i2s->clk_i2s); + ret = clk_prepare_enable(i2s->clk_i2s); if (ret) { dev_err(dev, "clk_enable failed: %d\n", ret); return ret; diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c index 9515ce58ea02..6872c77a1196 100644 --- a/sound/soc/tegra/tegra_asoc_utils.c +++ b/sound/soc/tegra/tegra_asoc_utils.c @@ -69,9 +69,9 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, data->set_baseclock = 0; data->set_mclk = 0; - clk_disable(data->clk_cdev1); - clk_disable(data->clk_pll_a_out0); - clk_disable(data->clk_pll_a); + clk_disable_unprepare(data->clk_cdev1); + clk_disable_unprepare(data->clk_pll_a_out0); + clk_disable_unprepare(data->clk_pll_a); err = clk_set_rate(data->clk_pll_a, new_baseclock); if (err) { @@ -87,19 +87,19 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */ - err = clk_enable(data->clk_pll_a); + err = clk_prepare_enable(data->clk_pll_a); if (err) { dev_err(data->dev, "Can't enable pll_a: %d\n", err); return err; } - err = clk_enable(data->clk_pll_a_out0); + err = clk_prepare_enable(data->clk_pll_a_out0); if (err) { dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); return err; } - err = clk_enable(data->clk_cdev1); + err = clk_prepare_enable(data->clk_cdev1); if (err) { dev_err(data->dev, "Can't enable cdev1: %d\n", err); return err; -- cgit v1.2.3-59-g8ed1b From 54f6019b5860ec062d1149b3a97a5a63ad3e4da9 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 27 May 2012 07:25:06 -0300 Subject: [media] S_HW_FREQ_SEEK: set capability flags and return ENODATA instead of EAGAIN Set the new capability flags in G_TUNER and return ENODATA if no channels were found. Signed-off-by: Hans Verkuil Acked-by: Hans de Goede Signed-off-by: Mauro Carvalho Chehab --- drivers/media/radio/radio-mr800.c | 5 +++-- drivers/media/radio/radio-wl1273.c | 3 ++- drivers/media/radio/si470x/radio-si470x-common.c | 6 ++++-- drivers/media/radio/wl128x/fmdrv_rx.c | 2 +- drivers/media/radio/wl128x/fmdrv_v4l2.c | 4 +++- sound/i2c/other/tea575x-tuner.c | 4 +++- 6 files changed, 16 insertions(+), 8 deletions(-) (limited to 'sound') diff --git a/drivers/media/radio/radio-mr800.c b/drivers/media/radio/radio-mr800.c index 94cb6bc690f5..3182b26d6efa 100644 --- a/drivers/media/radio/radio-mr800.c +++ b/drivers/media/radio/radio-mr800.c @@ -295,7 +295,8 @@ static int vidioc_g_tuner(struct file *file, void *priv, v->type = V4L2_TUNER_RADIO; v->rangelow = FREQ_MIN * FREQ_MUL; v->rangehigh = FREQ_MAX * FREQ_MUL; - v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO; + v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO | + V4L2_TUNER_CAP_HWSEEK_WRAP; v->rxsubchans = is_stereo ? V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO; v->audmode = radio->stereo ? V4L2_TUNER_MODE_STEREO : V4L2_TUNER_MODE_MONO; @@ -372,7 +373,7 @@ static int vidioc_s_hw_freq_seek(struct file *file, void *priv, timeout = jiffies + msecs_to_jiffies(30000); for (;;) { if (time_after(jiffies, timeout)) { - retval = -EAGAIN; + retval = -ENODATA; break; } if (schedule_timeout_interruptible(msecs_to_jiffies(10))) { diff --git a/drivers/media/radio/radio-wl1273.c b/drivers/media/radio/radio-wl1273.c index f1b607099b6c..e8428f573ccd 100644 --- a/drivers/media/radio/radio-wl1273.c +++ b/drivers/media/radio/radio-wl1273.c @@ -1514,7 +1514,8 @@ static int wl1273_fm_vidioc_g_tuner(struct file *file, void *priv, tuner->rangehigh = WL1273_FREQ(WL1273_BAND_OTHER_HIGH); tuner->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_RDS | - V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS_BLOCK_IO; + V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS_BLOCK_IO | + V4L2_TUNER_CAP_HWSEEK_BOUNDED | V4L2_TUNER_CAP_HWSEEK_WRAP; if (radio->stereo) tuner->audmode = V4L2_TUNER_MODE_STEREO; diff --git a/drivers/media/radio/si470x/radio-si470x-common.c b/drivers/media/radio/si470x/radio-si470x-common.c index 969cf494d85b..d485b79222fd 100644 --- a/drivers/media/radio/si470x/radio-si470x-common.c +++ b/drivers/media/radio/si470x/radio-si470x-common.c @@ -363,7 +363,7 @@ stop: /* try again, if timed out */ if (retval == 0 && timed_out) - return -EAGAIN; + return -ENODATA; return retval; } @@ -596,7 +596,9 @@ static int si470x_vidioc_g_tuner(struct file *file, void *priv, strcpy(tuner->name, "FM"); tuner->type = V4L2_TUNER_RADIO; tuner->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO | - V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_BLOCK_IO; + V4L2_TUNER_CAP_RDS | V4L2_TUNER_CAP_RDS_BLOCK_IO | + V4L2_TUNER_CAP_HWSEEK_BOUNDED | + V4L2_TUNER_CAP_HWSEEK_WRAP; /* range limits */ switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_BAND) >> 6) { diff --git a/drivers/media/radio/wl128x/fmdrv_rx.c b/drivers/media/radio/wl128x/fmdrv_rx.c index 43fb72291bea..3dd9fc097c47 100644 --- a/drivers/media/radio/wl128x/fmdrv_rx.c +++ b/drivers/media/radio/wl128x/fmdrv_rx.c @@ -251,7 +251,7 @@ again: if (!timeleft) { fmerr("Timeout(%d sec),didn't get tune ended int\n", jiffies_to_msecs(FM_DRV_RX_SEEK_TIMEOUT) / 1000); - return -ETIMEDOUT; + return -ENODATA; } int_reason = fmdev->irq_info.flag & (FM_TUNE_COMPLETE | FM_BAND_LIMIT); diff --git a/drivers/media/radio/wl128x/fmdrv_v4l2.c b/drivers/media/radio/wl128x/fmdrv_v4l2.c index 080b96a61f1a..49a11ec1f449 100644 --- a/drivers/media/radio/wl128x/fmdrv_v4l2.c +++ b/drivers/media/radio/wl128x/fmdrv_v4l2.c @@ -285,7 +285,9 @@ static int fm_v4l2_vidioc_g_tuner(struct file *file, void *priv, tuner->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO | ((fmdev->rx.rds.flag == FM_RDS_ENABLE) ? V4L2_TUNER_SUB_RDS : 0); tuner->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS | - V4L2_TUNER_CAP_LOW; + V4L2_TUNER_CAP_LOW | + V4L2_TUNER_CAP_HWSEEK_BOUNDED | + V4L2_TUNER_CAP_HWSEEK_WRAP; tuner->audmode = (stereo_mono_mode ? V4L2_TUNER_MODE_MONO : V4L2_TUNER_MODE_STEREO); diff --git a/sound/i2c/other/tea575x-tuner.c b/sound/i2c/other/tea575x-tuner.c index 582aace20ea3..ba2bc511d777 100644 --- a/sound/i2c/other/tea575x-tuner.c +++ b/sound/i2c/other/tea575x-tuner.c @@ -191,6 +191,8 @@ static int vidioc_g_tuner(struct file *file, void *priv, strcpy(v->name, "FM"); v->type = V4L2_TUNER_RADIO; v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO; + if (!tea->cannot_read_data) + v->capability |= V4L2_TUNER_CAP_HWSEEK_BOUNDED; v->rangelow = FREQ_LO; v->rangehigh = FREQ_HI; v->rxsubchans = tea->stereo ? V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO; @@ -299,7 +301,7 @@ static int vidioc_s_hw_freq_seek(struct file *file, void *fh, } tea->val &= ~TEA575X_BIT_SEARCH; snd_tea575x_set_freq(tea); - return -EAGAIN; + return -ENODATA; } static int tea575x_s_ctrl(struct v4l2_ctrl *ctrl) -- cgit v1.2.3-59-g8ed1b From 21c4afed6acc35deed6db3989f992c17712cd00e Mon Sep 17 00:00:00 2001 From: Boojin Kim Date: Tue, 19 Jun 2012 13:27:07 +0900 Subject: ASoC: follow the updated samsung DMA common operations This patch uses config() function to configure DMA transmit options. Signed-off-by: Boojin Kim Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- sound/soc/samsung/dma.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'sound') diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c index ddc6cde14e2a..f3ebc38c10fe 100644 --- a/sound/soc/samsung/dma.c +++ b/sound/soc/samsung/dma.c @@ -74,7 +74,7 @@ static void dma_enqueue(struct snd_pcm_substream *substream) struct runtime_data *prtd = substream->runtime->private_data; dma_addr_t pos = prtd->dma_pos; unsigned int limit; - struct samsung_dma_prep_info dma_info; + struct samsung_dma_prep dma_info; pr_debug("Entered %s\n", __func__); @@ -146,7 +146,8 @@ static int dma_hw_params(struct snd_pcm_substream *substream, unsigned long totbytes = params_buffer_bytes(params); struct s3c_dma_params *dma = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); - struct samsung_dma_info dma_info; + struct samsung_dma_req req; + struct samsung_dma_config config; pr_debug("Entered %s\n", __func__); @@ -166,16 +167,17 @@ static int dma_hw_params(struct snd_pcm_substream *substream, prtd->params->ops = samsung_dma_get_ops(); - dma_info.cap = (samsung_dma_has_circular() ? + req.cap = (samsung_dma_has_circular() ? DMA_CYCLIC : DMA_SLAVE); - dma_info.client = prtd->params->client; - dma_info.direction = + req.client = prtd->params->client; + config.direction = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM); - dma_info.width = prtd->params->dma_size; - dma_info.fifo = prtd->params->dma_addr; + config.width = prtd->params->dma_size; + config.fifo = prtd->params->dma_addr; prtd->params->ch = prtd->params->ops->request( - prtd->params->channel, &dma_info); + prtd->params->channel, &req); + prtd->params->ops->config(prtd->params->ch, &config); } snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); -- cgit v1.2.3-59-g8ed1b From 8842a9e2869cae14bbb8184004a42fc3070587fb Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 14 Jun 2012 11:16:14 +0800 Subject: ARM: imx: enable SPARSE_IRQ for imx platform As all irqchips on imx have been changed to allocate their irq_descs, and all unneeded mach/irqs.h inclusions on imx have been cleaned up, now it's time to select SPARSE_IRQ for imx/mxc. The SPARSE_IRQ support forces irqs allocation starting from 16. All those static irq number definition for SoCs need to shift 16 to keep non-DT boot works. With all those static IRQ number and start definitions removed from mach/irqs.h, the header becomes just a container of a couple of mach-imx specific irq/fiq calls. Since mach/irqs.h is not included by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly include mach/irqs.h themselves. Signed-off-by: Shawn Guo Acked-by: Sascha Hauer --- arch/arm/Kconfig | 1 + arch/arm/plat-mxc/include/mach/irqs.h | 44 ------- arch/arm/plat-mxc/include/mach/mx1.h | 111 ++++++++--------- arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++++--------- arch/arm/plat-mxc/include/mach/mx25.h | 72 +++++------ arch/arm/plat-mxc/include/mach/mx27.h | 127 ++++++++++---------- arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++++------- arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++++--------- arch/arm/plat-mxc/include/mach/mx35.h | 109 ++++++++--------- arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++++------ arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++++++--------------- arch/arm/plat-mxc/include/mach/mx51.h | 209 ++++++++++++++++---------------- arch/arm/plat-mxc/include/mach/mx53.h | 217 +++++++++++++++++----------------- drivers/media/video/mx1_camera.c | 1 + sound/soc/fsl/imx-pcm-fiq.c | 1 + 15 files changed, 722 insertions(+), 746 deletions(-) (limited to 'sound') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 84449dd8f031..63f40b43b062 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -446,6 +446,7 @@ config ARCH_MXC select CLKSRC_MMIO select GENERIC_IRQ_CHIP select MULTI_IRQ_HANDLER + select SPARSE_IRQ help Support for Freescale MXC/iMX-based family of processors diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index fd9efb044656..d73f5e8ea9cb 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,50 +11,6 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ -#include - -/* - * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC - * have 128 IRQs, and those with AVIC have 64. - * - * To support single image, the biggest number should be defined on - * top of the list. - */ -#if defined CONFIG_ARM_GIC -#define MXC_INTERNAL_IRQS 160 -#elif defined CONFIG_MXC_TZIC -#define MXC_INTERNAL_IRQS 128 -#else -#define MXC_INTERNAL_IRQS 64 -#endif - -#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS - -/* - * The next 16 interrupts are for board specific purposes. Since - * the kernel can only run on one machine at a time, we can re-use - * these. If you need more, increase MXC_BOARD_IRQS, but keep it - * within sensible limits. - */ -#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -#define MXC_BOARD_IRQS 80 -#else -#define MXC_BOARD_IRQS 16 -#endif - -#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) - -#ifdef CONFIG_MX3_IPU_IRQS -#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS -#else -#define MX3_IPU_IRQS 0 -#endif -/* REVISIT: Add IPU irqs on IMX51 */ - -#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) - extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); /* all normal IRQs can be FIQs */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 2b7c08d13e89..45bd31cc34d6 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -78,61 +78,62 @@ #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ -#define MX1_INT_SOFTINT 0 -#define MX1_INT_CSI 6 -#define MX1_DSPA_MAC_INT 7 -#define MX1_DSPA_INT 8 -#define MX1_COMP_INT 9 -#define MX1_MSHC_XINT 10 -#define MX1_GPIO_INT_PORTA 11 -#define MX1_GPIO_INT_PORTB 12 -#define MX1_GPIO_INT_PORTC 13 -#define MX1_INT_LCDC 14 -#define MX1_SIM_INT 15 -#define MX1_SIM_DATA_INT 16 -#define MX1_RTC_INT 17 -#define MX1_RTC_SAMINT 18 -#define MX1_INT_UART2PFERR 19 -#define MX1_INT_UART2RTS 20 -#define MX1_INT_UART2DTR 21 -#define MX1_INT_UART2UARTC 22 -#define MX1_INT_UART2TX 23 -#define MX1_INT_UART2RX 24 -#define MX1_INT_UART1PFERR 25 -#define MX1_INT_UART1RTS 26 -#define MX1_INT_UART1DTR 27 -#define MX1_INT_UART1UARTC 28 -#define MX1_INT_UART1TX 29 -#define MX1_INT_UART1RX 30 -#define MX1_VOICE_DAC_INT 31 -#define MX1_VOICE_ADC_INT 32 -#define MX1_PEN_DATA_INT 33 -#define MX1_PWM_INT 34 -#define MX1_SDHC_INT 35 -#define MX1_INT_I2C 39 -#define MX1_INT_CSPI2 40 -#define MX1_INT_CSPI1 41 -#define MX1_SSI_TX_INT 42 -#define MX1_SSI_TX_ERR_INT 43 -#define MX1_SSI_RX_INT 44 -#define MX1_SSI_RX_ERR_INT 45 -#define MX1_TOUCH_INT 46 -#define MX1_INT_USBD0 47 -#define MX1_INT_USBD1 48 -#define MX1_INT_USBD2 49 -#define MX1_INT_USBD3 50 -#define MX1_INT_USBD4 51 -#define MX1_INT_USBD5 52 -#define MX1_INT_USBD6 53 -#define MX1_BTSYS_INT 55 -#define MX1_BTTIM_INT 56 -#define MX1_BTWUI_INT 57 -#define MX1_TIM2_INT 58 -#define MX1_TIM1_INT 59 -#define MX1_DMA_ERR 60 -#define MX1_DMA_INT 61 -#define MX1_GPIO_INT_PORTD 62 -#define MX1_WDT_INT 63 +#include +#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0) +#define MX1_INT_CSI (NR_IRQS_LEGACY + 6) +#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7) +#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8) +#define MX1_COMP_INT (NR_IRQS_LEGACY + 9) +#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10) +#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11) +#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12) +#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13) +#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14) +#define MX1_SIM_INT (NR_IRQS_LEGACY + 15) +#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16) +#define MX1_RTC_INT (NR_IRQS_LEGACY + 17) +#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18) +#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19) +#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20) +#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21) +#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22) +#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23) +#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24) +#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25) +#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26) +#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27) +#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28) +#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29) +#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30) +#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31) +#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32) +#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33) +#define MX1_PWM_INT (NR_IRQS_LEGACY + 34) +#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35) +#define MX1_INT_I2C (NR_IRQS_LEGACY + 39) +#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40) +#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41) +#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42) +#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43) +#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44) +#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45) +#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46) +#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47) +#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48) +#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49) +#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50) +#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51) +#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52) +#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53) +#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55) +#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56) +#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57) +#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58) +#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59) +#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60) +#define MX1_DMA_INT (NR_IRQS_LEGACY + 61) +#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62) +#define MX1_WDT_INT (NR_IRQS_LEGACY + 63) /* DMA */ #define MX1_DMA_REQ_UART3_T 2 diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 6cd049ebbd8d..468738aa997f 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -99,59 +99,60 @@ #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ -#define MX21_INT_CSPI3 6 -#define MX21_INT_GPIO 8 -#define MX21_INT_FIRI 9 -#define MX21_INT_SDHC2 10 -#define MX21_INT_SDHC1 11 -#define MX21_INT_I2C 12 -#define MX21_INT_SSI2 13 -#define MX21_INT_SSI1 14 -#define MX21_INT_CSPI2 15 -#define MX21_INT_CSPI1 16 -#define MX21_INT_UART4 17 -#define MX21_INT_UART3 18 -#define MX21_INT_UART2 19 -#define MX21_INT_UART1 20 -#define MX21_INT_KPP 21 -#define MX21_INT_RTC 22 -#define MX21_INT_PWM 23 -#define MX21_INT_GPT3 24 -#define MX21_INT_GPT2 25 -#define MX21_INT_GPT1 26 -#define MX21_INT_WDOG 27 -#define MX21_INT_PCMCIA 28 -#define MX21_INT_NFC 29 -#define MX21_INT_BMI 30 -#define MX21_INT_CSI 31 -#define MX21_INT_DMACH0 32 -#define MX21_INT_DMACH1 33 -#define MX21_INT_DMACH2 34 -#define MX21_INT_DMACH3 35 -#define MX21_INT_DMACH4 36 -#define MX21_INT_DMACH5 37 -#define MX21_INT_DMACH6 38 -#define MX21_INT_DMACH7 39 -#define MX21_INT_DMACH8 40 -#define MX21_INT_DMACH9 41 -#define MX21_INT_DMACH10 42 -#define MX21_INT_DMACH11 43 -#define MX21_INT_DMACH12 44 -#define MX21_INT_DMACH13 45 -#define MX21_INT_DMACH14 46 -#define MX21_INT_DMACH15 47 -#define MX21_INT_EMMAENC 49 -#define MX21_INT_EMMADEC 50 -#define MX21_INT_EMMAPRP 51 -#define MX21_INT_EMMAPP 52 -#define MX21_INT_USBWKUP 53 -#define MX21_INT_USBDMA 54 -#define MX21_INT_USBHOST 55 -#define MX21_INT_USBFUNC 56 -#define MX21_INT_USBMNP 57 -#define MX21_INT_USBCTRL 58 -#define MX21_INT_SLCDC 60 -#define MX21_INT_LCDC 61 +#include +#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) +#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) +#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) +#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) +#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) +#define MX21_INT_I2C (NR_IRQS_LEGACY + 12) +#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) +#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) +#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) +#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) +#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) +#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) +#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) +#define MX21_INT_KPP (NR_IRQS_LEGACY + 21) +#define MX21_INT_RTC (NR_IRQS_LEGACY + 22) +#define MX21_INT_PWM (NR_IRQS_LEGACY + 23) +#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) +#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) +#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) +#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) +#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) +#define MX21_INT_NFC (NR_IRQS_LEGACY + 29) +#define MX21_INT_BMI (NR_IRQS_LEGACY + 30) +#define MX21_INT_CSI (NR_IRQS_LEGACY + 31) +#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) +#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) +#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) +#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) +#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) +#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) +#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) +#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) +#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) +#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) +#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) +#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) +#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) +#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) +#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) +#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) +#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) +#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) +#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) +#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) +#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) +#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) +#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) +#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) +#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) +#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) +#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) +#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) /* fixed DMA request numbers */ #define MX21_DMA_REQ_CSPI3_RX 1 diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index ccebf5ba12f0..627d94f1b010 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -61,40 +61,44 @@ #define MX25_IO_P2V(x) IMX_IO_P2V(x) #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) -#define MX25_INT_CSPI3 0 -#define MX25_INT_I2C1 3 -#define MX25_INT_I2C2 4 -#define MX25_INT_UART4 5 -#define MX25_INT_ESDHC2 8 -#define MX25_INT_ESDHC1 9 -#define MX25_INT_I2C3 10 -#define MX25_INT_SSI2 11 -#define MX25_INT_SSI1 12 -#define MX25_INT_CSPI2 13 -#define MX25_INT_CSPI1 14 -#define MX25_INT_GPIO3 16 -#define MX25_INT_CSI 17 -#define MX25_INT_UART3 18 -#define MX25_INT_GPIO4 23 -#define MX25_INT_KPP 24 -#define MX25_INT_DRYICE 25 -#define MX25_INT_PWM1 26 -#define MX25_INT_UART2 32 -#define MX25_INT_NFC 33 -#define MX25_INT_SDMA 34 -#define MX25_INT_USB_HS 35 -#define MX25_INT_PWM2 36 -#define MX25_INT_USB_OTG 37 -#define MX25_INT_LCDC 39 -#define MX25_INT_UART5 40 -#define MX25_INT_PWM3 41 -#define MX25_INT_PWM4 42 -#define MX25_INT_CAN1 43 -#define MX25_INT_CAN2 44 -#define MX25_INT_UART1 45 -#define MX25_INT_GPIO2 51 -#define MX25_INT_GPIO1 52 -#define MX25_INT_FEC 57 +/* + * Interrupt numbers + */ +#include +#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0) +#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3) +#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5) +#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8) +#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9) +#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10) +#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11) +#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12) +#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16) +#define MX25_INT_CSI (NR_IRQS_LEGACY + 17) +#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23) +#define MX25_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25) +#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26) +#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX25_INT_NFC (NR_IRQS_LEGACY + 33) +#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35) +#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36) +#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37) +#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39) +#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40) +#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41) +#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42) +#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43) +#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44) +#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX25_INT_FEC (NR_IRQS_LEGACY + 57) #define MX25_DMA_REQ_SSI2_RX1 22 #define MX25_DMA_REQ_SSI2_TX1 23 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 6265357284d7..e074616d54ca 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -128,69 +128,70 @@ #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) /* fixed interrupt numbers */ -#define MX27_INT_I2C2 1 -#define MX27_INT_GPT6 2 -#define MX27_INT_GPT5 3 -#define MX27_INT_GPT4 4 -#define MX27_INT_RTIC 5 -#define MX27_INT_CSPI3 6 -#define MX27_INT_SDHC 7 -#define MX27_INT_GPIO 8 -#define MX27_INT_SDHC3 9 -#define MX27_INT_SDHC2 10 -#define MX27_INT_SDHC1 11 -#define MX27_INT_I2C1 12 -#define MX27_INT_SSI2 13 -#define MX27_INT_SSI1 14 -#define MX27_INT_CSPI2 15 -#define MX27_INT_CSPI1 16 -#define MX27_INT_UART4 17 -#define MX27_INT_UART3 18 -#define MX27_INT_UART2 19 -#define MX27_INT_UART1 20 -#define MX27_INT_KPP 21 -#define MX27_INT_RTC 22 -#define MX27_INT_PWM 23 -#define MX27_INT_GPT3 24 -#define MX27_INT_GPT2 25 -#define MX27_INT_GPT1 26 -#define MX27_INT_WDOG 27 -#define MX27_INT_PCMCIA 28 -#define MX27_INT_NFC 29 -#define MX27_INT_ATA 30 -#define MX27_INT_CSI 31 -#define MX27_INT_DMACH0 32 -#define MX27_INT_DMACH1 33 -#define MX27_INT_DMACH2 34 -#define MX27_INT_DMACH3 35 -#define MX27_INT_DMACH4 36 -#define MX27_INT_DMACH5 37 -#define MX27_INT_DMACH6 38 -#define MX27_INT_DMACH7 39 -#define MX27_INT_DMACH8 40 -#define MX27_INT_DMACH9 41 -#define MX27_INT_DMACH10 42 -#define MX27_INT_DMACH11 43 -#define MX27_INT_DMACH12 44 -#define MX27_INT_DMACH13 45 -#define MX27_INT_DMACH14 46 -#define MX27_INT_DMACH15 47 -#define MX27_INT_UART6 48 -#define MX27_INT_UART5 49 -#define MX27_INT_FEC 50 -#define MX27_INT_EMMAPRP 51 -#define MX27_INT_EMMAPP 52 -#define MX27_INT_VPU 53 -#define MX27_INT_USB_HS1 54 -#define MX27_INT_USB_HS2 55 -#define MX27_INT_USB_OTG 56 -#define MX27_INT_SCC_SMN 57 -#define MX27_INT_SCC_SCM 58 -#define MX27_INT_SAHARA 59 -#define MX27_INT_SLCDC 60 -#define MX27_INT_LCDC 61 -#define MX27_INT_IIM 62 -#define MX27_INT_CCM 63 +#include +#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) +#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) +#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) +#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) +#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) +#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) +#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7) +#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) +#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) +#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) +#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) +#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) +#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) +#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) +#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) +#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) +#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) +#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) +#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) +#define MX27_INT_KPP (NR_IRQS_LEGACY + 21) +#define MX27_INT_RTC (NR_IRQS_LEGACY + 22) +#define MX27_INT_PWM (NR_IRQS_LEGACY + 23) +#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) +#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) +#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) +#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) +#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) +#define MX27_INT_NFC (NR_IRQS_LEGACY + 29) +#define MX27_INT_ATA (NR_IRQS_LEGACY + 30) +#define MX27_INT_CSI (NR_IRQS_LEGACY + 31) +#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) +#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) +#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) +#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) +#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) +#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) +#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) +#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) +#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) +#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) +#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) +#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) +#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) +#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) +#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) +#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) +#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) +#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) +#define MX27_INT_FEC (NR_IRQS_LEGACY + 50) +#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) +#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) +#define MX27_INT_VPU (NR_IRQS_LEGACY + 53) +#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) +#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) +#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) +#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) +#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) +#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) +#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) +#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) +#define MX27_INT_IIM (NR_IRQS_LEGACY + 62) +#define MX27_INT_CCM (NR_IRQS_LEGACY + 63) /* fixed DMA request numbers */ #define MX27_DMA_REQ_CSPI3_RX 1 diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index 6d07839fdec2..11642f5b224c 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -68,49 +68,50 @@ #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) /* fixed interrupt numbers */ -#define MX2x_INT_CSPI3 6 -#define MX2x_INT_GPIO 8 -#define MX2x_INT_SDHC2 10 -#define MX2x_INT_SDHC1 11 -#define MX2x_INT_I2C 12 -#define MX2x_INT_SSI2 13 -#define MX2x_INT_SSI1 14 -#define MX2x_INT_CSPI2 15 -#define MX2x_INT_CSPI1 16 -#define MX2x_INT_UART4 17 -#define MX2x_INT_UART3 18 -#define MX2x_INT_UART2 19 -#define MX2x_INT_UART1 20 -#define MX2x_INT_KPP 21 -#define MX2x_INT_RTC 22 -#define MX2x_INT_PWM 23 -#define MX2x_INT_GPT3 24 -#define MX2x_INT_GPT2 25 -#define MX2x_INT_GPT1 26 -#define MX2x_INT_WDOG 27 -#define MX2x_INT_PCMCIA 28 -#define MX2x_INT_NANDFC 29 -#define MX2x_INT_CSI 31 -#define MX2x_INT_DMACH0 32 -#define MX2x_INT_DMACH1 33 -#define MX2x_INT_DMACH2 34 -#define MX2x_INT_DMACH3 35 -#define MX2x_INT_DMACH4 36 -#define MX2x_INT_DMACH5 37 -#define MX2x_INT_DMACH6 38 -#define MX2x_INT_DMACH7 39 -#define MX2x_INT_DMACH8 40 -#define MX2x_INT_DMACH9 41 -#define MX2x_INT_DMACH10 42 -#define MX2x_INT_DMACH11 43 -#define MX2x_INT_DMACH12 44 -#define MX2x_INT_DMACH13 45 -#define MX2x_INT_DMACH14 46 -#define MX2x_INT_DMACH15 47 -#define MX2x_INT_EMMAPRP 51 -#define MX2x_INT_EMMAPP 52 -#define MX2x_INT_SLCDC 60 -#define MX2x_INT_LCDC 61 +#include +#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6) +#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8) +#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10) +#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11) +#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12) +#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13) +#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14) +#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15) +#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16) +#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17) +#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19) +#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20) +#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21) +#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22) +#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23) +#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24) +#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25) +#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26) +#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27) +#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28) +#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29) +#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31) +#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32) +#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33) +#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34) +#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35) +#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36) +#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37) +#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38) +#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39) +#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40) +#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41) +#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42) +#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43) +#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44) +#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45) +#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46) +#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47) +#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51) +#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52) +#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60) +#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61) /* fixed DMA request numbers */ #define MX2x_DMA_REQ_CSPI3_RX 1 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index e27619e442c0..dbced61d9fda 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -118,63 +118,67 @@ #define MX31_IO_P2V(x) IMX_IO_P2V(x) #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) -#define MX31_INT_I2C3 3 -#define MX31_INT_I2C2 4 -#define MX31_INT_MPEG4_ENCODER 5 -#define MX31_INT_RTIC 6 -#define MX31_INT_FIRI 7 -#define MX31_INT_SDHC2 8 -#define MX31_INT_SDHC1 9 -#define MX31_INT_I2C1 10 -#define MX31_INT_SSI2 11 -#define MX31_INT_SSI1 12 -#define MX31_INT_CSPI2 13 -#define MX31_INT_CSPI1 14 -#define MX31_INT_ATA 15 -#define MX31_INT_MBX 16 -#define MX31_INT_CSPI3 17 -#define MX31_INT_UART3 18 -#define MX31_INT_IIM 19 -#define MX31_INT_SIM2 20 -#define MX31_INT_SIM1 21 -#define MX31_INT_RNGA 22 -#define MX31_INT_EVTMON 23 -#define MX31_INT_KPP 24 -#define MX31_INT_RTC 25 -#define MX31_INT_PWM 26 -#define MX31_INT_EPIT2 27 -#define MX31_INT_EPIT1 28 -#define MX31_INT_GPT 29 -#define MX31_INT_POWER_FAIL 30 -#define MX31_INT_CCM_DVFS 31 -#define MX31_INT_UART2 32 -#define MX31_INT_NFC 33 -#define MX31_INT_SDMA 34 -#define MX31_INT_USB_HS1 35 -#define MX31_INT_USB_HS2 36 -#define MX31_INT_USB_OTG 37 -#define MX31_INT_MSHC1 39 -#define MX31_INT_MSHC2 40 -#define MX31_INT_IPU_ERR 41 -#define MX31_INT_IPU_SYN 42 -#define MX31_INT_UART1 45 -#define MX31_INT_UART4 46 -#define MX31_INT_UART5 47 -#define MX31_INT_ECT 48 -#define MX31_INT_SCC_SCM 49 -#define MX31_INT_SCC_SMN 50 -#define MX31_INT_GPIO2 51 -#define MX31_INT_GPIO1 52 -#define MX31_INT_CCM 53 -#define MX31_INT_PCMCIA 54 -#define MX31_INT_WDOG 55 -#define MX31_INT_GPIO3 56 -#define MX31_INT_EXT_POWER 58 -#define MX31_INT_EXT_TEMPER 59 -#define MX31_INT_EXT_SENSOR60 60 -#define MX31_INT_EXT_SENSOR61 61 -#define MX31_INT_EXT_WDOG 62 -#define MX31_INT_EXT_TV 63 +/* + * Interrupt numbers + */ +#include +#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) +#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) +#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) +#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) +#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) +#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) +#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) +#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) +#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) +#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX31_INT_ATA (NR_IRQS_LEGACY + 15) +#define MX31_INT_MBX (NR_IRQS_LEGACY + 16) +#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) +#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX31_INT_IIM (NR_IRQS_LEGACY + 19) +#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) +#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) +#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) +#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) +#define MX31_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX31_INT_RTC (NR_IRQS_LEGACY + 25) +#define MX31_INT_PWM (NR_IRQS_LEGACY + 26) +#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) +#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) +#define MX31_INT_GPT (NR_IRQS_LEGACY + 29) +#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) +#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) +#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX31_INT_NFC (NR_IRQS_LEGACY + 33) +#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) +#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) +#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) +#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) +#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) +#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) +#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) +#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) +#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) +#define MX31_INT_ECT (NR_IRQS_LEGACY + 48) +#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) +#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) +#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX31_INT_CCM (NR_IRQS_LEGACY + 53) +#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) +#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) +#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) +#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) +#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) +#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) +#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) +#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) +#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) #define MX31_DMA_REQ_SDHC1 20 #define MX31_DMA_REQ_SDHC2 21 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 80965a99aa55..2af5d3a699c7 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -120,60 +120,61 @@ /* * Interrupt numbers */ -#define MX35_INT_OWIRE 2 -#define MX35_INT_I2C3 3 -#define MX35_INT_I2C2 4 -#define MX35_INT_RTIC 6 -#define MX35_INT_ESDHC1 7 -#define MX35_INT_ESDHC2 8 -#define MX35_INT_ESDHC3 9 -#define MX35_INT_I2C1 10 -#define MX35_INT_SSI1 11 -#define MX35_INT_SSI2 12 -#define MX35_INT_CSPI2 13 -#define MX35_INT_CSPI1 14 -#define MX35_INT_ATA 15 -#define MX35_INT_GPU2D 16 -#define MX35_INT_ASRC 17 -#define MX35_INT_UART3 18 -#define MX35_INT_IIM 19 -#define MX35_INT_RNGA 22 -#define MX35_INT_EVTMON 23 -#define MX35_INT_KPP 24 -#define MX35_INT_RTC 25 -#define MX35_INT_PWM 26 -#define MX35_INT_EPIT2 27 -#define MX35_INT_EPIT1 28 -#define MX35_INT_GPT 29 -#define MX35_INT_POWER_FAIL 30 -#define MX35_INT_UART2 32 -#define MX35_INT_NFC 33 -#define MX35_INT_SDMA 34 -#define MX35_INT_USB_HS 35 -#define MX35_INT_USB_OTG 37 -#define MX35_INT_MSHC1 39 -#define MX35_INT_ESAI 40 -#define MX35_INT_IPU_ERR 41 -#define MX35_INT_IPU_SYN 42 -#define MX35_INT_CAN1 43 -#define MX35_INT_CAN2 44 -#define MX35_INT_UART1 45 -#define MX35_INT_MLB 46 -#define MX35_INT_SPDIF 47 -#define MX35_INT_ECT 48 -#define MX35_INT_SCC_SCM 49 -#define MX35_INT_SCC_SMN 50 -#define MX35_INT_GPIO2 51 -#define MX35_INT_GPIO1 52 -#define MX35_INT_WDOG 55 -#define MX35_INT_GPIO3 56 -#define MX35_INT_FEC 57 -#define MX35_INT_EXT_POWER 58 -#define MX35_INT_EXT_TEMPER 59 -#define MX35_INT_EXT_SENSOR60 60 -#define MX35_INT_EXT_SENSOR61 61 -#define MX35_INT_EXT_WDOG 62 -#define MX35_INT_EXT_TV 63 +#include +#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) +#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) +#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) +#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) +#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) +#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) +#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) +#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) +#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) +#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX35_INT_ATA (NR_IRQS_LEGACY + 15) +#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) +#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) +#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX35_INT_IIM (NR_IRQS_LEGACY + 19) +#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) +#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) +#define MX35_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX35_INT_RTC (NR_IRQS_LEGACY + 25) +#define MX35_INT_PWM (NR_IRQS_LEGACY + 26) +#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) +#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) +#define MX35_INT_GPT (NR_IRQS_LEGACY + 29) +#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) +#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX35_INT_NFC (NR_IRQS_LEGACY + 33) +#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) +#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) +#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) +#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) +#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) +#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) +#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) +#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) +#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX35_INT_MLB (NR_IRQS_LEGACY + 46) +#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) +#define MX35_INT_ECT (NR_IRQS_LEGACY + 48) +#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) +#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) +#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) +#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) +#define MX35_INT_FEC (NR_IRQS_LEGACY + 57) +#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) +#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) +#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) +#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) +#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) +#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) #define MX35_DMA_REQ_SSI2_RX1 22 #define MX35_DMA_REQ_SSI2_TX1 23 diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 30dbf424583e..96fb4fbc8ad7 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -143,44 +143,45 @@ /* * Interrupt numbers */ -#define MX3x_INT_I2C3 3 -#define MX3x_INT_I2C2 4 -#define MX3x_INT_RTIC 6 -#define MX3x_INT_I2C 10 -#define MX3x_INT_CSPI2 13 -#define MX3x_INT_CSPI1 14 -#define MX3x_INT_ATA 15 -#define MX3x_INT_UART3 18 -#define MX3x_INT_IIM 19 -#define MX3x_INT_RNGA 22 -#define MX3x_INT_EVTMON 23 -#define MX3x_INT_KPP 24 -#define MX3x_INT_RTC 25 -#define MX3x_INT_PWM 26 -#define MX3x_INT_EPIT2 27 -#define MX3x_INT_EPIT1 28 -#define MX3x_INT_GPT 29 -#define MX3x_INT_POWER_FAIL 30 -#define MX3x_INT_UART2 32 -#define MX3x_INT_NANDFC 33 -#define MX3x_INT_SDMA 34 -#define MX3x_INT_MSHC1 39 -#define MX3x_INT_IPU_ERR 41 -#define MX3x_INT_IPU_SYN 42 -#define MX3x_INT_UART1 45 -#define MX3x_INT_ECT 48 -#define MX3x_INT_SCC_SCM 49 -#define MX3x_INT_SCC_SMN 50 -#define MX3x_INT_GPIO2 51 -#define MX3x_INT_GPIO1 52 -#define MX3x_INT_WDOG 55 -#define MX3x_INT_GPIO3 56 -#define MX3x_INT_EXT_POWER 58 -#define MX3x_INT_EXT_TEMPER 59 -#define MX3x_INT_EXT_SENSOR60 60 -#define MX3x_INT_EXT_SENSOR61 61 -#define MX3x_INT_EXT_WDOG 62 -#define MX3x_INT_EXT_TV 63 +#include +#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) +#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) +#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) +#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) +#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) +#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) +#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) +#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) +#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) +#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) +#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) +#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) +#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) +#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) +#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) +#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) +#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) +#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) +#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) +#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) +#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) +#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) +#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) +#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) +#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) +#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) +#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) +#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) +#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) +#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) +#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) +#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) +#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) +#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) +#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) +#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h index 5f2da75a47f4..09ac19c1570c 100644 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -188,99 +188,100 @@ /* * Interrupt numbers */ -#define MX50_INT_MMC_SDHC1 1 -#define MX50_INT_MMC_SDHC2 2 -#define MX50_INT_MMC_SDHC3 3 -#define MX50_INT_MMC_SDHC4 4 -#define MX50_INT_DAP 5 -#define MX50_INT_SDMA 6 -#define MX50_INT_IOMUX 7 -#define MX50_INT_UART4 13 -#define MX50_INT_USB_H1 14 -#define MX50_INT_USB_OTG 18 -#define MX50_INT_DATABAHN 19 -#define MX50_INT_ELCDIF 20 -#define MX50_INT_EPXP 21 -#define MX50_INT_SRTC_NTZ 24 -#define MX50_INT_SRTC_TZ 25 -#define MX50_INT_EPDC 27 -#define MX50_INT_NIC 28 -#define MX50_INT_SSI1 29 -#define MX50_INT_SSI2 30 -#define MX50_INT_UART1 31 -#define MX50_INT_UART2 32 -#define MX50_INT_UART3 33 -#define MX50_INT_RESV34 34 -#define MX50_INT_RESV35 35 -#define MX50_INT_CSPI1 36 -#define MX50_INT_CSPI2 37 -#define MX50_INT_CSPI 38 -#define MX50_INT_GPT 39 -#define MX50_INT_EPIT1 40 -#define MX50_INT_GPIO1_INT7 42 -#define MX50_INT_GPIO1_INT6 43 -#define MX50_INT_GPIO1_INT5 44 -#define MX50_INT_GPIO1_INT4 45 -#define MX50_INT_GPIO1_INT3 46 -#define MX50_INT_GPIO1_INT2 47 -#define MX50_INT_GPIO1_INT1 48 -#define MX50_INT_GPIO1_INT0 49 -#define MX50_INT_GPIO1_LOW 50 -#define MX50_INT_GPIO1_HIGH 51 -#define MX50_INT_GPIO2_LOW 52 -#define MX50_INT_GPIO2_HIGH 53 -#define MX50_INT_GPIO3_LOW 54 -#define MX50_INT_GPIO3_HIGH 55 -#define MX50_INT_GPIO4_LOW 56 -#define MX50_INT_GPIO4_HIGH 57 -#define MX50_INT_WDOG1 58 -#define MX50_INT_KPP 60 -#define MX50_INT_PWM1 61 -#define MX50_INT_I2C1 62 -#define MX50_INT_I2C2 63 -#define MX50_INT_I2C3 64 -#define MX50_INT_RESV65 65 -#define MX50_INT_DCDC 66 -#define MX50_INT_THERMAL_ALARM 67 -#define MX50_INT_ANA3 68 -#define MX50_INT_ANA4 69 -#define MX50_INT_CCM1 71 -#define MX50_INT_CCM2 72 -#define MX50_INT_GPC1 73 -#define MX50_INT_GPC2 74 -#define MX50_INT_SRC 75 -#define MX50_INT_NM 76 -#define MX50_INT_PMU 77 -#define MX50_INT_CTI_IRQ 78 -#define MX50_INT_CTI1_TG0 79 -#define MX50_INT_CTI1_TG1 80 -#define MX50_INT_GPU2_IRQ 84 -#define MX50_INT_GPU2_BUSY 85 -#define MX50_INT_UART5 86 -#define MX50_INT_FEC 87 -#define MX50_INT_OWIRE 88 -#define MX50_INT_CTI1_TG2 89 -#define MX50_INT_SJC 90 -#define MX50_INT_DCP_CHAN1_3 91 -#define MX50_INT_DCP_CHAN0 92 -#define MX50_INT_PWM2 94 -#define MX50_INT_RNGB 97 -#define MX50_INT_CTI1_TG3 98 -#define MX50_INT_RAWNAND_BCH 100 -#define MX50_INT_RAWNAND_GPMI 102 -#define MX50_INT_GPIO5_LOW 103 -#define MX50_INT_GPIO5_HIGH 104 -#define MX50_INT_GPIO6_LOW 105 -#define MX50_INT_GPIO6_HIGH 106 -#define MX50_INT_MSHC 109 -#define MX50_INT_APBHDMA_CHAN0 110 -#define MX50_INT_APBHDMA_CHAN1 111 -#define MX50_INT_APBHDMA_CHAN2 112 -#define MX50_INT_APBHDMA_CHAN3 113 -#define MX50_INT_APBHDMA_CHAN4 114 -#define MX50_INT_APBHDMA_CHAN5 115 -#define MX50_INT_APBHDMA_CHAN6 116 -#define MX50_INT_APBHDMA_CHAN7 117 +#include +#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1) +#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2) +#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3) +#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4) +#define MX50_INT_DAP (NR_IRQS_LEGACY + 5) +#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6) +#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7) +#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13) +#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14) +#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18) +#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19) +#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20) +#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21) +#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) +#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) +#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27) +#define MX50_INT_NIC (NR_IRQS_LEGACY + 28) +#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29) +#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30) +#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31) +#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33) +#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34) +#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35) +#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36) +#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37) +#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38) +#define MX50_INT_GPT (NR_IRQS_LEGACY + 39) +#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40) +#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) +#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) +#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) +#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) +#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) +#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) +#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) +#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) +#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) +#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) +#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) +#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) +#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) +#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) +#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) +#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) +#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58) +#define MX50_INT_KPP (NR_IRQS_LEGACY + 60) +#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61) +#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62) +#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63) +#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64) +#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65) +#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66) +#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67) +#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68) +#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69) +#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71) +#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72) +#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73) +#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74) +#define MX50_INT_SRC (NR_IRQS_LEGACY + 75) +#define MX50_INT_NM (NR_IRQS_LEGACY + 76) +#define MX50_INT_PMU (NR_IRQS_LEGACY + 77) +#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) +#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) +#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) +#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) +#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) +#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86) +#define MX50_INT_FEC (NR_IRQS_LEGACY + 87) +#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88) +#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) +#define MX50_INT_SJC (NR_IRQS_LEGACY + 90) +#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91) +#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92) +#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94) +#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97) +#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) +#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100) +#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102) +#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) +#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) +#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) +#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) +#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109) +#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110) +#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111) +#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112) +#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113) +#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114) +#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115) +#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116) +#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117) #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx50_revision(void); diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index cdf07c65ec1e..af844f76261a 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -232,110 +232,111 @@ /* * Interrupt numbers */ -#define MX51_INT_BASE 0 -#define MX51_INT_RESV0 0 -#define MX51_INT_ESDHC1 1 -#define MX51_INT_ESDHC2 2 -#define MX51_INT_ESDHC3 3 -#define MX51_INT_ESDHC4 4 -#define MX51_INT_RESV5 5 -#define MX51_INT_SDMA 6 -#define MX51_INT_IOMUX 7 -#define MX51_INT_NFC 8 -#define MX51_INT_VPU 9 -#define MX51_INT_IPU_ERR 10 -#define MX51_INT_IPU_SYN 11 -#define MX51_INT_GPU 12 -#define MX51_INT_RESV13 13 -#define MX51_INT_USB_HS1 14 -#define MX51_INT_EMI 15 -#define MX51_INT_USB_HS2 16 -#define MX51_INT_USB_HS3 17 -#define MX51_INT_USB_OTG 18 -#define MX51_INT_SAHARA_H0 19 -#define MX51_INT_SAHARA_H1 20 -#define MX51_INT_SCC_SMN 21 -#define MX51_INT_SCC_STZ 22 -#define MX51_INT_SCC_SCM 23 -#define MX51_INT_SRTC_NTZ 24 -#define MX51_INT_SRTC_TZ 25 -#define MX51_INT_RTIC 26 -#define MX51_INT_CSU 27 -#define MX51_INT_SLIM_B 28 -#define MX51_INT_SSI1 29 -#define MX51_INT_SSI2 30 -#define MX51_INT_UART1 31 -#define MX51_INT_UART2 32 -#define MX51_INT_UART3 33 -#define MX51_INT_RESV34 34 -#define MX51_INT_RESV35 35 -#define MX51_INT_ECSPI1 36 -#define MX51_INT_ECSPI2 37 -#define MX51_INT_CSPI 38 -#define MX51_INT_GPT 39 -#define MX51_INT_EPIT1 40 -#define MX51_INT_EPIT2 41 -#define MX51_INT_GPIO1_INT7 42 -#define MX51_INT_GPIO1_INT6 43 -#define MX51_INT_GPIO1_INT5 44 -#define MX51_INT_GPIO1_INT4 45 -#define MX51_INT_GPIO1_INT3 46 -#define MX51_INT_GPIO1_INT2 47 -#define MX51_INT_GPIO1_INT1 48 -#define MX51_INT_GPIO1_INT0 49 -#define MX51_INT_GPIO1_LOW 50 -#define MX51_INT_GPIO1_HIGH 51 -#define MX51_INT_GPIO2_LOW 52 -#define MX51_INT_GPIO2_HIGH 53 -#define MX51_INT_GPIO3_LOW 54 -#define MX51_INT_GPIO3_HIGH 55 -#define MX51_INT_GPIO4_LOW 56 -#define MX51_INT_GPIO4_HIGH 57 -#define MX51_INT_WDOG1 58 -#define MX51_INT_WDOG2 59 -#define MX51_INT_KPP 60 -#define MX51_INT_PWM1 61 -#define MX51_INT_I2C1 62 -#define MX51_INT_I2C2 63 -#define MX51_INT_HS_I2C 64 -#define MX51_INT_RESV65 65 -#define MX51_INT_RESV66 66 -#define MX51_INT_SIM_IPB 67 -#define MX51_INT_SIM_DAT 68 -#define MX51_INT_IIM 69 -#define MX51_INT_ATA 70 -#define MX51_INT_CCM1 71 -#define MX51_INT_CCM2 72 -#define MX51_INT_GPC1 73 -#define MX51_INT_GPC2 74 -#define MX51_INT_SRC 75 -#define MX51_INT_NM 76 -#define MX51_INT_PMU 77 -#define MX51_INT_CTI_IRQ 78 -#define MX51_INT_CTI1_TG0 79 -#define MX51_INT_CTI1_TG1 80 -#define MX51_INT_MCG_ERR 81 -#define MX51_INT_MCG_TMR 82 -#define MX51_INT_MCG_FUNC 83 -#define MX51_INT_GPU2_IRQ 84 -#define MX51_INT_GPU2_BUSY 85 -#define MX51_INT_RESV86 86 -#define MX51_INT_FEC 87 -#define MX51_INT_OWIRE 88 -#define MX51_INT_CTI1_TG2 89 -#define MX51_INT_SJC 90 -#define MX51_INT_SPDIF 91 -#define MX51_INT_TVE 92 -#define MX51_INT_FIRI 93 -#define MX51_INT_PWM2 94 -#define MX51_INT_SLIM_EXP 95 -#define MX51_INT_SSI3 96 -#define MX51_INT_EMI_BOOT 97 -#define MX51_INT_CTI1_TG3 98 -#define MX51_INT_SMC_RX 99 -#define MX51_INT_VPU_IDLE 100 -#define MX51_INT_EMI_NFC 101 -#define MX51_INT_GPU_IDLE 102 +#include +#define MX51_INT_BASE (NR_IRQS_LEGACY + 0) +#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0) +#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1) +#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2) +#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3) +#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4) +#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5) +#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6) +#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7) +#define MX51_INT_NFC (NR_IRQS_LEGACY + 8) +#define MX51_INT_VPU (NR_IRQS_LEGACY + 9) +#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10) +#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11) +#define MX51_INT_GPU (NR_IRQS_LEGACY + 12) +#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13) +#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14) +#define MX51_INT_EMI (NR_IRQS_LEGACY + 15) +#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16) +#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17) +#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18) +#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) +#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) +#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21) +#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22) +#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23) +#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) +#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) +#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26) +#define MX51_INT_CSU (NR_IRQS_LEGACY + 27) +#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28) +#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29) +#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30) +#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31) +#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33) +#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34) +#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35) +#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36) +#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37) +#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38) +#define MX51_INT_GPT (NR_IRQS_LEGACY + 39) +#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40) +#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41) +#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) +#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) +#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) +#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) +#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) +#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) +#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) +#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) +#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) +#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) +#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) +#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) +#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) +#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) +#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) +#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) +#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58) +#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59) +#define MX51_INT_KPP (NR_IRQS_LEGACY + 60) +#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61) +#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62) +#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63) +#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64) +#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65) +#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66) +#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67) +#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68) +#define MX51_INT_IIM (NR_IRQS_LEGACY + 69) +#define MX51_INT_ATA (NR_IRQS_LEGACY + 70) +#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71) +#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72) +#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73) +#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74) +#define MX51_INT_SRC (NR_IRQS_LEGACY + 75) +#define MX51_INT_NM (NR_IRQS_LEGACY + 76) +#define MX51_INT_PMU (NR_IRQS_LEGACY + 77) +#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) +#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) +#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) +#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81) +#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82) +#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83) +#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) +#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) +#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86) +#define MX51_INT_FEC (NR_IRQS_LEGACY + 87) +#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88) +#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) +#define MX51_INT_SJC (NR_IRQS_LEGACY + 90) +#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91) +#define MX51_INT_TVE (NR_IRQS_LEGACY + 92) +#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93) +#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94) +#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) +#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96) +#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) +#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) +#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99) +#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) +#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101) +#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index a37e8c353994..f829d1c22501 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -229,113 +229,114 @@ /* * Interrupt numbers */ -#define MX53_INT_RESV0 0 -#define MX53_INT_ESDHC1 1 -#define MX53_INT_ESDHC2 2 -#define MX53_INT_ESDHC3 3 -#define MX53_INT_ESDHC4 4 -#define MX53_INT_DAP 5 -#define MX53_INT_SDMA 6 -#define MX53_INT_IOMUX 7 -#define MX53_INT_NFC 8 -#define MX53_INT_VPU 9 -#define MX53_INT_IPU_ERR 10 -#define MX53_INT_IPU_SYN 11 -#define MX53_INT_GPU 12 -#define MX53_INT_UART4 13 -#define MX53_INT_USB_H1 14 -#define MX53_INT_EMI 15 -#define MX53_INT_USB_H2 16 -#define MX53_INT_USB_H3 17 -#define MX53_INT_USB_OTG 18 -#define MX53_INT_SAHARA_H0 19 -#define MX53_INT_SAHARA_H1 20 -#define MX53_INT_SCC_SMN 21 -#define MX53_INT_SCC_STZ 22 -#define MX53_INT_SCC_SCM 23 -#define MX53_INT_SRTC_NTZ 24 -#define MX53_INT_SRTC_TZ 25 -#define MX53_INT_RTIC 26 -#define MX53_INT_CSU 27 -#define MX53_INT_SATA 28 -#define MX53_INT_SSI1 29 -#define MX53_INT_SSI2 30 -#define MX53_INT_UART1 31 -#define MX53_INT_UART2 32 -#define MX53_INT_UART3 33 -#define MX53_INT_RTC 34 -#define MX53_INT_PTP 35 -#define MX53_INT_ECSPI1 36 -#define MX53_INT_ECSPI2 37 -#define MX53_INT_CSPI 38 -#define MX53_INT_GPT 39 -#define MX53_INT_EPIT1 40 -#define MX53_INT_EPIT2 41 -#define MX53_INT_GPIO1_INT7 42 -#define MX53_INT_GPIO1_INT6 43 -#define MX53_INT_GPIO1_INT5 44 -#define MX53_INT_GPIO1_INT4 45 -#define MX53_INT_GPIO1_INT3 46 -#define MX53_INT_GPIO1_INT2 47 -#define MX53_INT_GPIO1_INT1 48 -#define MX53_INT_GPIO1_INT0 49 -#define MX53_INT_GPIO1_LOW 50 -#define MX53_INT_GPIO1_HIGH 51 -#define MX53_INT_GPIO2_LOW 52 -#define MX53_INT_GPIO2_HIGH 53 -#define MX53_INT_GPIO3_LOW 54 -#define MX53_INT_GPIO3_HIGH 55 -#define MX53_INT_GPIO4_LOW 56 -#define MX53_INT_GPIO4_HIGH 57 -#define MX53_INT_WDOG1 58 -#define MX53_INT_WDOG2 59 -#define MX53_INT_KPP 60 -#define MX53_INT_PWM1 61 -#define MX53_INT_I2C1 62 -#define MX53_INT_I2C2 63 -#define MX53_INT_I2C3 64 -#define MX53_INT_MLB 65 -#define MX53_INT_ASRC 66 -#define MX53_INT_SPDIF 67 -#define MX53_INT_SIM_DAT 68 -#define MX53_INT_IIM 69 -#define MX53_INT_ATA 70 -#define MX53_INT_CCM1 71 -#define MX53_INT_CCM2 72 -#define MX53_INT_GPC1 73 -#define MX53_INT_GPC2 74 -#define MX53_INT_SRC 75 -#define MX53_INT_NM 76 -#define MX53_INT_PMU 77 -#define MX53_INT_CTI_IRQ 78 -#define MX53_INT_CTI1_TG0 79 -#define MX53_INT_CTI1_TG1 80 -#define MX53_INT_ESAI 81 -#define MX53_INT_CAN1 82 -#define MX53_INT_CAN2 83 -#define MX53_INT_GPU2_IRQ 84 -#define MX53_INT_GPU2_BUSY 85 -#define MX53_INT_UART5 86 -#define MX53_INT_FEC 87 -#define MX53_INT_OWIRE 88 -#define MX53_INT_CTI1_TG2 89 -#define MX53_INT_SJC 90 -#define MX53_INT_TVE 92 -#define MX53_INT_FIRI 93 -#define MX53_INT_PWM2 94 -#define MX53_INT_SLIM_EXP 95 -#define MX53_INT_SSI3 96 -#define MX53_INT_EMI_BOOT 97 -#define MX53_INT_CTI1_TG3 98 -#define MX53_INT_SMC_RX 99 -#define MX53_INT_VPU_IDLE 100 -#define MX53_INT_EMI_NFC 101 -#define MX53_INT_GPU_IDLE 102 -#define MX53_INT_GPIO5_LOW 103 -#define MX53_INT_GPIO5_HIGH 104 -#define MX53_INT_GPIO6_LOW 105 -#define MX53_INT_GPIO6_HIGH 106 -#define MX53_INT_GPIO7_LOW 107 -#define MX53_INT_GPIO7_HIGH 108 +#include +#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) +#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) +#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) +#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) +#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) +#define MX53_INT_DAP (NR_IRQS_LEGACY + 5) +#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) +#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) +#define MX53_INT_NFC (NR_IRQS_LEGACY + 8) +#define MX53_INT_VPU (NR_IRQS_LEGACY + 9) +#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) +#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) +#define MX53_INT_GPU (NR_IRQS_LEGACY + 12) +#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) +#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) +#define MX53_INT_EMI (NR_IRQS_LEGACY + 15) +#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) +#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) +#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) +#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) +#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) +#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) +#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) +#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) +#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) +#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) +#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) +#define MX53_INT_CSU (NR_IRQS_LEGACY + 27) +#define MX53_INT_SATA (NR_IRQS_LEGACY + 28) +#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) +#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) +#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) +#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) +#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) +#define MX53_INT_RTC (NR_IRQS_LEGACY + 34) +#define MX53_INT_PTP (NR_IRQS_LEGACY + 35) +#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) +#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) +#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) +#define MX53_INT_GPT (NR_IRQS_LEGACY + 39) +#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) +#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) +#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) +#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) +#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) +#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) +#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) +#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) +#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) +#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) +#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) +#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) +#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) +#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) +#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) +#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) +#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) +#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) +#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) +#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) +#define MX53_INT_KPP (NR_IRQS_LEGACY + 60) +#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) +#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) +#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) +#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) +#define MX53_INT_MLB (NR_IRQS_LEGACY + 65) +#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) +#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) +#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) +#define MX53_INT_IIM (NR_IRQS_LEGACY + 69) +#define MX53_INT_ATA (NR_IRQS_LEGACY + 70) +#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) +#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) +#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) +#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) +#define MX53_INT_SRC (NR_IRQS_LEGACY + 75) +#define MX53_INT_NM (NR_IRQS_LEGACY + 76) +#define MX53_INT_PMU (NR_IRQS_LEGACY + 77) +#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) +#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) +#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) +#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) +#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) +#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) +#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) +#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) +#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) +#define MX53_INT_FEC (NR_IRQS_LEGACY + 87) +#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) +#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) +#define MX53_INT_SJC (NR_IRQS_LEGACY + 90) +#define MX53_INT_TVE (NR_IRQS_LEGACY + 92) +#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) +#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) +#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) +#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) +#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) +#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) +#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) +#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) +#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) +#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) +#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) +#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) +#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) +#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) +#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) +#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) #endif /* ifndef __MACH_MX53_H__ */ diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c index 4296a8350298..d2e6f82ecfac 100644 --- a/drivers/media/video/mx1_camera.c +++ b/drivers/media/video/mx1_camera.c @@ -43,6 +43,7 @@ #include #include #include +#include #include /* diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c index 456b7d723d66..ee27ba3933bd 100644 --- a/sound/soc/fsl/imx-pcm-fiq.c +++ b/sound/soc/fsl/imx-pcm-fiq.c @@ -29,6 +29,7 @@ #include +#include #include #include "imx-ssi.h" -- cgit v1.2.3-59-g8ed1b From 26b0d14106954ae46d2f4f7eec3481828a210f7d Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Sat, 9 Jun 2012 15:58:56 +0200 Subject: sound/aoa: Adapt to new i2c probing scheme The i2c-powermac driver now creates the i2c devices properly from the device-tree, including workarounds for broken or missing device-tree bits, so let's just use the normal probe methods and get rid of the hand made device creation code. Signed-off-by: Andreas Schwab Signed-off-by: Benjamin Herrenschmidt --- sound/aoa/codecs/onyx.c | 75 ++-------------------------------------------- sound/aoa/codecs/tas.c | 80 ++----------------------------------------------- 2 files changed, 6 insertions(+), 149 deletions(-) (limited to 'sound') diff --git a/sound/aoa/codecs/onyx.c b/sound/aoa/codecs/onyx.c index 270790d384e2..4cedc6950d72 100644 --- a/sound/aoa/codecs/onyx.c +++ b/sound/aoa/codecs/onyx.c @@ -997,45 +997,10 @@ static void onyx_exit_codec(struct aoa_codec *codec) onyx->codec.soundbus_dev->detach_codec(onyx->codec.soundbus_dev, onyx); } -static int onyx_create(struct i2c_adapter *adapter, - struct device_node *node, - int addr) -{ - struct i2c_board_info info; - struct i2c_client *client; - - memset(&info, 0, sizeof(struct i2c_board_info)); - strlcpy(info.type, "aoa_codec_onyx", I2C_NAME_SIZE); - info.addr = addr; - info.platform_data = node; - client = i2c_new_device(adapter, &info); - if (!client) - return -ENODEV; - - /* - * We know the driver is already loaded, so the device should be - * already bound. If not it means binding failed, which suggests - * the device doesn't really exist and should be deleted. - * Ideally this would be replaced by better checks _before_ - * instantiating the device. - */ - if (!client->driver) { - i2c_unregister_device(client); - return -ENODEV; - } - - /* - * Let i2c-core delete that device on driver removal. - * This is safe because i2c-core holds the core_lock mutex for us. - */ - list_add_tail(&client->detected, &client->driver->clients); - return 0; -} - static int onyx_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { - struct device_node *node = client->dev.platform_data; + struct device_node *node = client->dev.of_node; struct onyx *onyx; u8 dummy; @@ -1071,40 +1036,6 @@ static int onyx_i2c_probe(struct i2c_client *client, return -ENODEV; } -static int onyx_i2c_attach(struct i2c_adapter *adapter) -{ - struct device_node *busnode, *dev = NULL; - struct pmac_i2c_bus *bus; - - bus = pmac_i2c_adapter_to_bus(adapter); - if (bus == NULL) - return -ENODEV; - busnode = pmac_i2c_get_bus_node(bus); - - while ((dev = of_get_next_child(busnode, dev)) != NULL) { - if (of_device_is_compatible(dev, "pcm3052")) { - const u32 *addr; - printk(KERN_DEBUG PFX "found pcm3052\n"); - addr = of_get_property(dev, "reg", NULL); - if (!addr) - return -ENODEV; - return onyx_create(adapter, dev, (*addr)>>1); - } - } - - /* if that didn't work, try desperate mode for older - * machines that have stuff missing from the device tree */ - - if (!of_device_is_compatible(busnode, "k2-i2c")) - return -ENODEV; - - printk(KERN_DEBUG PFX "found k2-i2c, checking if onyx chip is on it\n"); - /* probe both possible addresses for the onyx chip */ - if (onyx_create(adapter, NULL, 0x46) == 0) - return 0; - return onyx_create(adapter, NULL, 0x47); -} - static int onyx_i2c_remove(struct i2c_client *client) { struct onyx *onyx = i2c_get_clientdata(client); @@ -1117,16 +1048,16 @@ static int onyx_i2c_remove(struct i2c_client *client) } static const struct i2c_device_id onyx_i2c_id[] = { - { "aoa_codec_onyx", 0 }, + { "MAC,pcm3052", 0 }, { } }; +MODULE_DEVICE_TABLE(i2c,onyx_i2c_id); static struct i2c_driver onyx_driver = { .driver = { .name = "aoa_codec_onyx", .owner = THIS_MODULE, }, - .attach_adapter = onyx_i2c_attach, .probe = onyx_i2c_probe, .remove = onyx_i2c_remove, .id_table = onyx_i2c_id, diff --git a/sound/aoa/codecs/tas.c b/sound/aoa/codecs/tas.c index 8e63d1f35ce1..c491ae0f749c 100644 --- a/sound/aoa/codecs/tas.c +++ b/sound/aoa/codecs/tas.c @@ -883,43 +883,10 @@ static void tas_exit_codec(struct aoa_codec *codec) } -static int tas_create(struct i2c_adapter *adapter, - struct device_node *node, - int addr) -{ - struct i2c_board_info info; - struct i2c_client *client; - - memset(&info, 0, sizeof(struct i2c_board_info)); - strlcpy(info.type, "aoa_codec_tas", I2C_NAME_SIZE); - info.addr = addr; - info.platform_data = node; - - client = i2c_new_device(adapter, &info); - if (!client) - return -ENODEV; - /* - * We know the driver is already loaded, so the device should be - * already bound. If not it means binding failed, and then there - * is no point in keeping the device instantiated. - */ - if (!client->driver) { - i2c_unregister_device(client); - return -ENODEV; - } - - /* - * Let i2c-core delete that device on driver removal. - * This is safe because i2c-core holds the core_lock mutex for us. - */ - list_add_tail(&client->detected, &client->driver->clients); - return 0; -} - static int tas_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { - struct device_node *node = client->dev.platform_data; + struct device_node *node = client->dev.of_node; struct tas *tas; tas = kzalloc(sizeof(struct tas), GFP_KERNEL); @@ -953,47 +920,6 @@ static int tas_i2c_probe(struct i2c_client *client, return -EINVAL; } -static int tas_i2c_attach(struct i2c_adapter *adapter) -{ - struct device_node *busnode, *dev = NULL; - struct pmac_i2c_bus *bus; - - bus = pmac_i2c_adapter_to_bus(adapter); - if (bus == NULL) - return -ENODEV; - busnode = pmac_i2c_get_bus_node(bus); - - while ((dev = of_get_next_child(busnode, dev)) != NULL) { - if (of_device_is_compatible(dev, "tas3004")) { - const u32 *addr; - printk(KERN_DEBUG PFX "found tas3004\n"); - addr = of_get_property(dev, "reg", NULL); - if (!addr) - continue; - return tas_create(adapter, dev, ((*addr) >> 1) & 0x7f); - } - /* older machines have no 'codec' node with a 'compatible' - * property that says 'tas3004', they just have a 'deq' - * node without any such property... */ - if (strcmp(dev->name, "deq") == 0) { - const u32 *_addr; - u32 addr; - printk(KERN_DEBUG PFX "found 'deq' node\n"); - _addr = of_get_property(dev, "i2c-address", NULL); - if (!_addr) - continue; - addr = ((*_addr) >> 1) & 0x7f; - /* now, if the address doesn't match any of the two - * that a tas3004 can have, we cannot handle this. - * I doubt it ever happens but hey. */ - if (addr != 0x34 && addr != 0x35) - continue; - return tas_create(adapter, dev, addr); - } - } - return -ENODEV; -} - static int tas_i2c_remove(struct i2c_client *client) { struct tas *tas = i2c_get_clientdata(client); @@ -1011,16 +937,16 @@ static int tas_i2c_remove(struct i2c_client *client) } static const struct i2c_device_id tas_i2c_id[] = { - { "aoa_codec_tas", 0 }, + { "MAC,tas3004", 0 }, { } }; +MODULE_DEVICE_TABLE(i2c,tas_i2c_id); static struct i2c_driver tas_driver = { .driver = { .name = "aoa_codec_tas", .owner = THIS_MODULE, }, - .attach_adapter = tas_i2c_attach, .probe = tas_i2c_probe, .remove = tas_i2c_remove, .id_table = tas_i2c_id, -- cgit v1.2.3-59-g8ed1b From 6f3de8bf33902a91b83744c76fea7de3cd0328cc Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 9 May 2012 17:09:18 +0200 Subject: ASoC: siu: prepare for conversion to the shdma base library Signed-off-by: Guennadi Liakhovetski Cc: Liam Girdwood Cc: Mark Brown Acked-by: Mark Brown Signed-off-by: Vinod Koul --- sound/soc/sh/siu_pcm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound') diff --git a/sound/soc/sh/siu_pcm.c b/sound/soc/sh/siu_pcm.c index 5cfcc655e95f..3fdc801eb758 100644 --- a/sound/soc/sh/siu_pcm.c +++ b/sound/soc/sh/siu_pcm.c @@ -330,12 +330,12 @@ static bool filter(struct dma_chan *chan, void *slave) { struct sh_dmae_slave *param = slave; - pr_debug("%s: slave ID %d\n", __func__, param->slave_id); + pr_debug("%s: slave ID %d\n", __func__, param->shdma_slave.slave_id); if (unlikely(param->dma_dev != chan->device->dev)) return false; - chan->private = param; + chan->private = ¶m->shdma_slave; return true; } @@ -360,12 +360,12 @@ static int siu_pcm_open(struct snd_pcm_substream *ss) if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) { siu_stream = &port_info->playback; param = &siu_stream->param; - param->slave_id = port ? pdata->dma_slave_tx_b : + param->shdma_slave.slave_id = port ? pdata->dma_slave_tx_b : pdata->dma_slave_tx_a; } else { siu_stream = &port_info->capture; param = &siu_stream->param; - param->slave_id = port ? pdata->dma_slave_rx_b : + param->shdma_slave.slave_id = port ? pdata->dma_slave_rx_b : pdata->dma_slave_rx_a; } -- cgit v1.2.3-59-g8ed1b From b8373147ed3ca01a968d81f22688f2836a9aeb6b Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 9 May 2012 17:09:20 +0200 Subject: ASoC: fsi: prepare for conversion to the shdma base library Signed-off-by: Guennadi Liakhovetski Cc: Liam Girdwood Cc: Mark Brown Acked-by: Mark Brown Signed-off-by: Vinod Koul --- sound/soc/sh/fsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c index 2ef98536f1da..3edf3bdf536a 100644 --- a/sound/soc/sh/fsi.c +++ b/sound/soc/sh/fsi.c @@ -1631,8 +1631,8 @@ static void fsi_handler_init(struct fsi_priv *fsi) fsi->capture.priv = fsi; if (fsi->info->tx_id) { - fsi->playback.slave.slave_id = fsi->info->tx_id; - fsi->playback.handler = &fsi_dma_push_handler; + fsi->playback.slave.shdma_slave.slave_id = fsi->info->tx_id; + fsi->playback.handler = &fsi_dma_push_handler; } } -- cgit v1.2.3-59-g8ed1b From 9d051dc79f8fd1854229178476db0534359a3704 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 5 Jul 2012 12:29:38 +0200 Subject: ASoC: siu: don't use DMA device for channel filtering DMA channels are filtered based on slave IDs, no need to additionally filter on DMA device. Signed-off-by: Guennadi Liakhovetski Cc: Mark Brown Signed-off-by: Vinod Koul --- sound/soc/sh/siu_pcm.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'sound') diff --git a/sound/soc/sh/siu_pcm.c b/sound/soc/sh/siu_pcm.c index 3fdc801eb758..488f9becb44f 100644 --- a/sound/soc/sh/siu_pcm.c +++ b/sound/soc/sh/siu_pcm.c @@ -332,9 +332,6 @@ static bool filter(struct dma_chan *chan, void *slave) pr_debug("%s: slave ID %d\n", __func__, param->shdma_slave.slave_id); - if (unlikely(param->dma_dev != chan->device->dev)) - return false; - chan->private = ¶m->shdma_slave; return true; } @@ -369,7 +366,6 @@ static int siu_pcm_open(struct snd_pcm_substream *ss) pdata->dma_slave_rx_a; } - param->dma_dev = pdata->dma_dev; /* Get DMA channel */ siu_stream->chan = dma_request_channel(mask, filter, param); if (!siu_stream->chan) { -- cgit v1.2.3-59-g8ed1b From 2955b47d2c1983998a8c5915cb96884e67f7cb53 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Mon, 9 Jul 2012 19:33:25 -0700 Subject: [SCSI] async: introduce 'async_domain' type This is in preparation for teaching async_synchronize_full() to sync all pending async work, and not just on the async_running domain. This conversion is functionally equivalent, just embedding the existing list in a new async_domain type. The .registered attribute is used in a later patch to distinguish between domains that want to be flushed by async_synchronize_full() versus those that only expect async_synchronize_{full|cookie}_domain to be used for flushing. [jejb: add async.h to scsi_priv.h for struct async_domain] Signed-off-by: Dan Williams Acked-by: Arjan van de Ven Acked-by: Mark Brown Tested-by: Eldad Zack Signed-off-by: James Bottomley --- drivers/regulator/core.c | 2 +- drivers/scsi/libsas/sas_ata.c | 2 +- drivers/scsi/scsi.c | 3 ++- drivers/scsi/scsi_priv.h | 3 ++- include/linux/async.h | 35 +++++++++++++++++++++++++++++++---- kernel/async.c | 35 +++++++++++++++++------------------ sound/soc/soc-dapm.c | 2 +- 7 files changed, 55 insertions(+), 27 deletions(-) (limited to 'sound') diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 8b4b3829d9e7..6c74546fc3cd 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -2744,7 +2744,7 @@ static void regulator_bulk_enable_async(void *data, async_cookie_t cookie) int regulator_bulk_enable(int num_consumers, struct regulator_bulk_data *consumers) { - LIST_HEAD(async_domain); + ASYNC_DOMAIN_EXCLUSIVE(async_domain); int i; int ret = 0; diff --git a/drivers/scsi/libsas/sas_ata.c b/drivers/scsi/libsas/sas_ata.c index bec3bc8aab0c..a59fcdc8fd63 100644 --- a/drivers/scsi/libsas/sas_ata.c +++ b/drivers/scsi/libsas/sas_ata.c @@ -742,7 +742,7 @@ static void async_sas_ata_eh(void *data, async_cookie_t cookie) void sas_ata_strategy_handler(struct Scsi_Host *shost) { struct sas_ha_struct *sas_ha = SHOST_TO_SAS_HA(shost); - LIST_HEAD(async); + ASYNC_DOMAIN_EXCLUSIVE(async); int i; /* it's ok to defer revalidation events during ata eh, these diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index bbbc9c918d4c..4cade886a50a 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include @@ -91,7 +92,7 @@ EXPORT_SYMBOL(scsi_logging_level); #endif /* sd, scsi core and power management need to coordinate flushing async actions */ -LIST_HEAD(scsi_sd_probe_domain); +ASYNC_DOMAIN(scsi_sd_probe_domain); EXPORT_SYMBOL(scsi_sd_probe_domain); /* NB: These are exposed through /proc/scsi/scsi and form part of the ABI. diff --git a/drivers/scsi/scsi_priv.h b/drivers/scsi/scsi_priv.h index 13d74da5dfab..8f9a0cadc296 100644 --- a/drivers/scsi/scsi_priv.h +++ b/drivers/scsi/scsi_priv.h @@ -2,6 +2,7 @@ #define _SCSI_PRIV_H #include +#include #include struct request_queue; @@ -163,7 +164,7 @@ static inline int scsi_autopm_get_host(struct Scsi_Host *h) { return 0; } static inline void scsi_autopm_put_host(struct Scsi_Host *h) {} #endif /* CONFIG_PM_RUNTIME */ -extern struct list_head scsi_sd_probe_domain; +extern struct async_domain scsi_sd_probe_domain; /* * internal scsi timeout functions: for use by mid-layer and transport diff --git a/include/linux/async.h b/include/linux/async.h index 68a9530196f2..364e7ff16c08 100644 --- a/include/linux/async.h +++ b/include/linux/async.h @@ -9,19 +9,46 @@ * as published by the Free Software Foundation; version 2 * of the License. */ +#ifndef __ASYNC_H__ +#define __ASYNC_H__ #include #include typedef u64 async_cookie_t; typedef void (async_func_ptr) (void *data, async_cookie_t cookie); +struct async_domain { + struct list_head node; + struct list_head domain; + int count; + unsigned registered:1; +}; + +/* + * domain participates in global async_synchronize_full + */ +#define ASYNC_DOMAIN(_name) \ + struct async_domain _name = { .node = LIST_HEAD_INIT(_name.node), \ + .domain = LIST_HEAD_INIT(_name.domain), \ + .count = 0, \ + .registered = 1 } + +/* + * domain is free to go out of scope as soon as all pending work is + * complete, this domain does not participate in async_synchronize_full + */ +#define ASYNC_DOMAIN_EXCLUSIVE(_name) \ + struct async_domain _name = { .node = LIST_HEAD_INIT(_name.node), \ + .domain = LIST_HEAD_INIT(_name.domain), \ + .count = 0, \ + .registered = 0 } extern async_cookie_t async_schedule(async_func_ptr *ptr, void *data); extern async_cookie_t async_schedule_domain(async_func_ptr *ptr, void *data, - struct list_head *list); + struct async_domain *domain); extern void async_synchronize_full(void); -extern void async_synchronize_full_domain(struct list_head *list); +extern void async_synchronize_full_domain(struct async_domain *domain); extern void async_synchronize_cookie(async_cookie_t cookie); extern void async_synchronize_cookie_domain(async_cookie_t cookie, - struct list_head *list); - + struct async_domain *domain); +#endif diff --git a/kernel/async.c b/kernel/async.c index bd0c168a3bbe..ba5491dfa991 100644 --- a/kernel/async.c +++ b/kernel/async.c @@ -62,7 +62,7 @@ static async_cookie_t next_cookie = 1; #define MAX_WORK 32768 static LIST_HEAD(async_pending); -static LIST_HEAD(async_running); +static ASYNC_DOMAIN(async_running); static DEFINE_SPINLOCK(async_lock); struct async_entry { @@ -71,7 +71,7 @@ struct async_entry { async_cookie_t cookie; async_func_ptr *func; void *data; - struct list_head *running; + struct async_domain *running; }; static DECLARE_WAIT_QUEUE_HEAD(async_done); @@ -82,13 +82,12 @@ static atomic_t entry_count; /* * MUST be called with the lock held! */ -static async_cookie_t __lowest_in_progress(struct list_head *running) +static async_cookie_t __lowest_in_progress(struct async_domain *running) { struct async_entry *entry; - if (!list_empty(running)) { - entry = list_first_entry(running, - struct async_entry, list); + if (!list_empty(&running->domain)) { + entry = list_first_entry(&running->domain, typeof(*entry), list); return entry->cookie; } @@ -99,7 +98,7 @@ static async_cookie_t __lowest_in_progress(struct list_head *running) return next_cookie; /* "infinity" value */ } -static async_cookie_t lowest_in_progress(struct list_head *running) +static async_cookie_t lowest_in_progress(struct async_domain *running) { unsigned long flags; async_cookie_t ret; @@ -119,10 +118,11 @@ static void async_run_entry_fn(struct work_struct *work) container_of(work, struct async_entry, work); unsigned long flags; ktime_t uninitialized_var(calltime), delta, rettime; + struct async_domain *running = entry->running; /* 1) move self to the running queue */ spin_lock_irqsave(&async_lock, flags); - list_move_tail(&entry->list, entry->running); + list_move_tail(&entry->list, &running->domain); spin_unlock_irqrestore(&async_lock, flags); /* 2) run (and print duration) */ @@ -156,7 +156,7 @@ static void async_run_entry_fn(struct work_struct *work) wake_up(&async_done); } -static async_cookie_t __async_schedule(async_func_ptr *ptr, void *data, struct list_head *running) +static async_cookie_t __async_schedule(async_func_ptr *ptr, void *data, struct async_domain *running) { struct async_entry *entry; unsigned long flags; @@ -223,7 +223,7 @@ EXPORT_SYMBOL_GPL(async_schedule); * Note: This function may be called from atomic or non-atomic contexts. */ async_cookie_t async_schedule_domain(async_func_ptr *ptr, void *data, - struct list_head *running) + struct async_domain *running) { return __async_schedule(ptr, data, running); } @@ -238,20 +238,20 @@ void async_synchronize_full(void) { do { async_synchronize_cookie(next_cookie); - } while (!list_empty(&async_running) || !list_empty(&async_pending)); + } while (!list_empty(&async_running.domain) || !list_empty(&async_pending)); } EXPORT_SYMBOL_GPL(async_synchronize_full); /** * async_synchronize_full_domain - synchronize all asynchronous function within a certain domain - * @list: running list to synchronize on + * @domain: running list to synchronize on * * This function waits until all asynchronous function calls for the - * synchronization domain specified by the running list @list have been done. + * synchronization domain specified by the running list @domain have been done. */ -void async_synchronize_full_domain(struct list_head *list) +void async_synchronize_full_domain(struct async_domain *domain) { - async_synchronize_cookie_domain(next_cookie, list); + async_synchronize_cookie_domain(next_cookie, domain); } EXPORT_SYMBOL_GPL(async_synchronize_full_domain); @@ -261,11 +261,10 @@ EXPORT_SYMBOL_GPL(async_synchronize_full_domain); * @running: running list to synchronize on * * This function waits until all asynchronous function calls for the - * synchronization domain specified by the running list @list submitted + * synchronization domain specified by running list @running submitted * prior to @cookie have been done. */ -void async_synchronize_cookie_domain(async_cookie_t cookie, - struct list_head *running) +void async_synchronize_cookie_domain(async_cookie_t cookie, struct async_domain *running) { ktime_t uninitialized_var(starttime), delta, endtime; diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index 89eae93445cf..fa1e31206892 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -1545,7 +1545,7 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) struct snd_soc_dapm_context *d; LIST_HEAD(up_list); LIST_HEAD(down_list); - LIST_HEAD(async_domain); + ASYNC_DOMAIN_EXCLUSIVE(async_domain); enum snd_soc_bias_level bias; trace_snd_soc_dapm_start(card); -- cgit v1.2.3-59-g8ed1b From be4ac00ac486aa68f82a940602963c466cea1a4e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 16 Jul 2012 11:49:43 +0200 Subject: mfd: Fix twl6040 revision information twl6040 ES1.1 and ES1.2 have the same revid (0x01). ES1.3 of twl6040 REVID is 0x02. Signed-off-by: Peter Ujfalusi Signed-off-by: Samuel Ortiz --- include/linux/mfd/twl6040.h | 4 ++-- sound/soc/codecs/twl6040.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'sound') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index dcc0e12b8038..00b330e578b1 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -161,8 +161,8 @@ #define TWL6040_CELLS 2 #define TWL6040_REV_ES1_0 0x00 -#define TWL6040_REV_ES1_1 0x01 -#define TWL6040_REV_ES1_2 0x02 +#define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */ +#define TWL6040_REV_ES1_3 0x02 #define TWL6040_IRQ_TH 0 #define TWL6040_IRQ_PLUG 1 diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index a36e9fcdf184..2786de218a3c 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -653,7 +653,7 @@ int twl6040_get_hs_step_size(struct snd_soc_codec *codec) { struct twl6040 *twl6040 = codec->control_data; - if (twl6040_get_revid(twl6040) < TWL6040_REV_ES1_2) + if (twl6040_get_revid(twl6040) < TWL6040_REV_ES1_3) /* For ES under ES_1.3 HS step is 2 mV */ return 2; else -- cgit v1.2.3-59-g8ed1b From baffab28b13120694fa3ebab08d3e99667a851d2 Mon Sep 17 00:00:00 2001 From: Simon Baatz Date: Thu, 19 Jul 2012 00:04:09 +0200 Subject: ARM: Orion: fix driver probe error handling with respect to clk The clk patches added code to get and enable clocks in the respective driver probe functions. If the probe function failed for some reason after enabling the clock, the clock was not disabled again in many cases. Signed-off-by: Simon Baatz Signed-off-by: Andrew Lumm --- drivers/crypto/mv_cesa.c | 4 ++++ drivers/mmc/host/mvsdio.c | 4 ++++ drivers/mtd/nand/orion_nand.c | 4 ++++ drivers/net/ethernet/marvell/mv643xx_eth.c | 6 ++++++ drivers/usb/host/ehci-orion.c | 4 ++++ sound/soc/kirkwood/kirkwood-i2s.c | 8 +++++++- 6 files changed, 29 insertions(+), 1 deletion(-) (limited to 'sound') diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c index 1cc6b3f3e262..a4faa893199c 100644 --- a/drivers/crypto/mv_cesa.c +++ b/drivers/crypto/mv_cesa.c @@ -1098,6 +1098,10 @@ err_unreg_ecb: crypto_unregister_alg(&mv_aes_alg_ecb); err_irq: free_irq(irq, cp); + if (!IS_ERR(cp->clk)) { + clk_disable_unprepare(cp->clk); + clk_put(cp->clk); + } err_thread: kthread_stop(cp->queue_th); err_unmap_sram: diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c index 3b9136c1a475..a61cb5fca22d 100644 --- a/drivers/mmc/host/mvsdio.c +++ b/drivers/mmc/host/mvsdio.c @@ -839,6 +839,10 @@ out: if (r) release_resource(r); if (mmc) + if (!IS_ERR_OR_NULL(host->clk)) { + clk_disable_unprepare(host->clk); + clk_put(host->clk); + } mmc_free_host(mmc); return ret; diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index 513dc88a05ca..9b8fd3d77168 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -183,6 +183,10 @@ static int __init orion_nand_probe(struct platform_device *pdev) return 0; no_dev: + if (!IS_ERR(clk)) { + clk_disable_unprepare(clk); + clk_put(clk); + } platform_set_drvdata(pdev, NULL); iounmap(io_base); no_res: diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index f0f06b2bc28b..4fbba57b8ff4 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -2983,6 +2983,12 @@ static int mv643xx_eth_probe(struct platform_device *pdev) return 0; out: +#if defined(CONFIG_HAVE_CLK) + if (!IS_ERR(mp->clk)) { + clk_disable_unprepare(mp->clk); + clk_put(mp->clk); + } +#endif free_netdev(dev); return err; diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index 82de1073aa52..c6903e3af29c 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c @@ -298,6 +298,10 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) err4: usb_put_hcd(hcd); err3: + if (!IS_ERR(clk)) { + clk_disable_unprepare(clk); + clk_put(clk); + } iounmap(regs); err2: release_mem_region(res->start, resource_size(res)); diff --git a/sound/soc/kirkwood/kirkwood-i2s.c b/sound/soc/kirkwood/kirkwood-i2s.c index fa4556750451..7646dd7f30cb 100644 --- a/sound/soc/kirkwood/kirkwood-i2s.c +++ b/sound/soc/kirkwood/kirkwood-i2s.c @@ -458,7 +458,13 @@ static __devinit int kirkwood_i2s_dev_probe(struct platform_device *pdev) } clk_prepare_enable(priv->clk); - return snd_soc_register_dai(&pdev->dev, &kirkwood_i2s_dai); + err = snd_soc_register_dai(&pdev->dev, &kirkwood_i2s_dai); + if (!err) + return 0; + dev_err(&pdev->dev, "snd_soc_register_dai failed\n"); + + clk_disable_unprepare(priv->clk); + clk_put(priv->clk); err_ioremap: iounmap(priv->io); -- cgit v1.2.3-59-g8ed1b From 586093064d95618cc9ba2acd546949eea9f2a8fa Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sun, 22 Jul 2012 21:26:51 +0400 Subject: sound_firmware: don't pass crap to filp_close() Signed-off-by: Al Viro --- sound/sound_firmware.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound') diff --git a/sound/sound_firmware.c b/sound/sound_firmware.c index 7e96249536b4..37711a5d0d6b 100644 --- a/sound/sound_firmware.c +++ b/sound/sound_firmware.c @@ -23,14 +23,14 @@ static int do_mod_firmware_load(const char *fn, char **fp) if (l <= 0 || l > 131072) { printk(KERN_INFO "Invalid firmware '%s'\n", fn); - filp_close(filp, current->files); + filp_close(filp, NULL); return 0; } dp = vmalloc(l); if (dp == NULL) { printk(KERN_INFO "Out of memory loading '%s'.\n", fn); - filp_close(filp, current->files); + filp_close(filp, NULL); return 0; } pos = 0; @@ -38,10 +38,10 @@ static int do_mod_firmware_load(const char *fn, char **fp) { printk(KERN_INFO "Failed to read '%s'.\n", fn); vfree(dp); - filp_close(filp, current->files); + filp_close(filp, NULL); return 0; } - filp_close(filp, current->files); + filp_close(filp, NULL); *fp = dp; return (int) l; } -- cgit v1.2.3-59-g8ed1b From 31a62d415726d94bae5caf5f2e50232aa06babf6 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 18 May 2012 09:36:17 -0300 Subject: [media] snd_tea575x: Add write_/read_val operations Some devices which use the tea575x tuner chip don't allow bit banging the lines, instead they offer a method to directly set / get the contents of the 25 bit shift-register in the chip. Notably the Griffin radioSHARK USB radio receiver does this. Signed-off-by: Hans de Goede CC: Ondrej Zary Signed-off-by: Mauro Carvalho Chehab --- include/sound/tea575x-tuner.h | 4 ++++ sound/i2c/other/tea575x-tuner.c | 6 ++++++ 2 files changed, 10 insertions(+) (limited to 'sound') diff --git a/include/sound/tea575x-tuner.h b/include/sound/tea575x-tuner.h index 0c3c2fb0f939..7bd6f6145a38 100644 --- a/include/sound/tea575x-tuner.h +++ b/include/sound/tea575x-tuner.h @@ -37,6 +37,10 @@ struct snd_tea575x; struct snd_tea575x_ops { + /* Drivers using snd_tea575x must either define read_ and write_val */ + void (*write_val)(struct snd_tea575x *tea, u32 val); + u32 (*read_val)(struct snd_tea575x *tea); + /* Or define the 3 pin functions */ void (*set_pins)(struct snd_tea575x *tea, u8 pins); u8 (*get_pins)(struct snd_tea575x *tea); void (*set_direction)(struct snd_tea575x *tea, bool output); diff --git a/sound/i2c/other/tea575x-tuner.c b/sound/i2c/other/tea575x-tuner.c index b29b88f93c9e..080aae9d1198 100644 --- a/sound/i2c/other/tea575x-tuner.c +++ b/sound/i2c/other/tea575x-tuner.c @@ -71,6 +71,9 @@ static void snd_tea575x_write(struct snd_tea575x *tea, unsigned int val) u16 l; u8 data; + if (tea->ops->write_val) + return tea->ops->write_val(tea, val); + tea->ops->set_direction(tea, 1); udelay(16); @@ -94,6 +97,9 @@ static u32 snd_tea575x_read(struct snd_tea575x *tea) u16 l, rdata; u32 data = 0; + if (tea->ops->read_val) + return tea->ops->read_val(tea); + tea->ops->set_direction(tea, 0); tea->ops->set_pins(tea, 0); udelay(16); -- cgit v1.2.3-59-g8ed1b From 3d0fe51cfa3d07751224c034f8226136a7dd05f2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 18 May 2012 12:21:57 -0300 Subject: [media] snd_tea575x: Add a cannot_mute flag Some devices which use the tea575x tuner chip don't allow direct control over the IO pins, and thus cannot mute the audio output. Signed-off-by: Hans de Goede CC: Ondrej Zary Signed-off-by: Mauro Carvalho Chehab --- include/sound/tea575x-tuner.h | 1 + sound/i2c/other/tea575x-tuner.c | 35 +++++++++++++++++++---------------- 2 files changed, 20 insertions(+), 16 deletions(-) (limited to 'sound') diff --git a/include/sound/tea575x-tuner.h b/include/sound/tea575x-tuner.h index 7bd6f6145a38..fe8590cac5c2 100644 --- a/include/sound/tea575x-tuner.h +++ b/include/sound/tea575x-tuner.h @@ -53,6 +53,7 @@ struct snd_tea575x { int radio_nr; /* radio_nr */ bool tea5759; /* 5759 chip is present */ bool cannot_read_data; /* Device cannot read the data pin */ + bool cannot_mute; /* Device cannot mute */ bool mute; /* Device is muted? */ bool stereo; /* receiving stereo */ bool tuned; /* tuned to a station */ diff --git a/sound/i2c/other/tea575x-tuner.c b/sound/i2c/other/tea575x-tuner.c index 080aae9d1198..d14edb7d6484 100644 --- a/sound/i2c/other/tea575x-tuner.c +++ b/sound/i2c/other/tea575x-tuner.c @@ -385,7 +385,6 @@ int snd_tea575x_init(struct snd_tea575x *tea, struct module *owner) strlcpy(tea->vd.name, tea->v4l2_dev->name, sizeof(tea->vd.name)); tea->vd.lock = &tea->mutex; tea->vd.v4l2_dev = tea->v4l2_dev; - tea->vd.ctrl_handler = &tea->ctrl_handler; tea->fops = tea575x_fops; tea->fops.owner = owner; tea->vd.fops = &tea->fops; @@ -394,29 +393,33 @@ int snd_tea575x_init(struct snd_tea575x *tea, struct module *owner) if (tea->cannot_read_data) v4l2_disable_ioctl(&tea->vd, VIDIOC_S_HW_FREQ_SEEK); - v4l2_ctrl_handler_init(&tea->ctrl_handler, 1); - v4l2_ctrl_new_std(&tea->ctrl_handler, &tea575x_ctrl_ops, V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1); - retval = tea->ctrl_handler.error; - if (retval) { - v4l2_err(tea->v4l2_dev, "can't initialize controls\n"); - v4l2_ctrl_handler_free(&tea->ctrl_handler); - return retval; - } - - if (tea->ext_init) { - retval = tea->ext_init(tea); + if (!tea->cannot_mute) { + tea->vd.ctrl_handler = &tea->ctrl_handler; + v4l2_ctrl_handler_init(&tea->ctrl_handler, 1); + v4l2_ctrl_new_std(&tea->ctrl_handler, &tea575x_ctrl_ops, + V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1); + retval = tea->ctrl_handler.error; if (retval) { + v4l2_err(tea->v4l2_dev, "can't initialize controls\n"); v4l2_ctrl_handler_free(&tea->ctrl_handler); return retval; } - } - v4l2_ctrl_handler_setup(&tea->ctrl_handler); + if (tea->ext_init) { + retval = tea->ext_init(tea); + if (retval) { + v4l2_ctrl_handler_free(&tea->ctrl_handler); + return retval; + } + } + + v4l2_ctrl_handler_setup(&tea->ctrl_handler); + } retval = video_register_device(&tea->vd, VFL_TYPE_RADIO, tea->radio_nr); if (retval) { v4l2_err(tea->v4l2_dev, "can't register video device!\n"); - v4l2_ctrl_handler_free(&tea->ctrl_handler); + v4l2_ctrl_handler_free(tea->vd.ctrl_handler); return retval; } @@ -426,7 +429,7 @@ int snd_tea575x_init(struct snd_tea575x *tea, struct module *owner) void snd_tea575x_exit(struct snd_tea575x *tea) { video_unregister_device(&tea->vd); - v4l2_ctrl_handler_free(&tea->ctrl_handler); + v4l2_ctrl_handler_free(tea->vd.ctrl_handler); } static int __init alsa_tea575x_module_init(void) -- cgit v1.2.3-59-g8ed1b From b778b3f25baf46dd88f16d51f1682828be0aa2ad Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Mon, 30 Jul 2012 14:40:15 -0700 Subject: sound: use printk_get_level and printk_skip_level Make the output logging routine independent of the KERN_ style. Signed-off-by: Joe Perches Cc: Kay Sievers Cc: Takashi Iwai Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- sound/core/misc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'sound') diff --git a/sound/core/misc.c b/sound/core/misc.c index 768167925409..30e027ecf4da 100644 --- a/sound/core/misc.c +++ b/sound/core/misc.c @@ -68,6 +68,7 @@ void __snd_printk(unsigned int level, const char *path, int line, { va_list args; #ifdef CONFIG_SND_VERBOSE_PRINTK + int kern_level; struct va_format vaf; char verbose_fmt[] = KERN_DEFAULT "ALSA %s:%d %pV"; #endif @@ -81,12 +82,16 @@ void __snd_printk(unsigned int level, const char *path, int line, #ifdef CONFIG_SND_VERBOSE_PRINTK vaf.fmt = format; vaf.va = &args; - if (format[0] == '<' && format[2] == '>') { - memcpy(verbose_fmt, format, 3); - vaf.fmt = format + 3; + + kern_level = printk_get_level(format); + if (kern_level) { + const char *end_of_header = printk_skip_level(format); + memcpy(verbose_fmt, format, end_of_header - format); + vaf.fmt = end_of_header; } else if (level) - memcpy(verbose_fmt, KERN_DEBUG, 3); + memcpy(verbose_fmt, KERN_DEBUG, sizeof(KERN_DEBUG) - 1); printk(verbose_fmt, sanity_file_name(path), line, &vaf); + #else vprintk(format, args); #endif -- cgit v1.2.3-59-g8ed1b From d0db84e713eaaccea2a435e1625fb3150b335f4a Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 7 Aug 2012 15:37:47 +0300 Subject: ASoC: omap-mcbsp: Fix 6pin mux configuration The check for the mux_signal callback was wrong which prevents us to configure the 6pin port's FSR/CLKR signal mux. Reported-by: CF Adad Signed-off-by: Peter Ujfalusi Acked-by: Jarkko Nikula Signed-off-by: Mark Brown Cc: stable@vger.kernel.org (3.4+) --- sound/soc/omap/mcbsp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c index 34835e8a9160..d33c48baaf71 100644 --- a/sound/soc/omap/mcbsp.c +++ b/sound/soc/omap/mcbsp.c @@ -745,7 +745,7 @@ int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux) { const char *signal, *src; - if (mcbsp->pdata->mux_signal) + if (!mcbsp->pdata->mux_signal) return -EINVAL; switch (mux) { -- cgit v1.2.3-59-g8ed1b From 48a08bab3066a9452216f8c52e0d6f35566de04d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 8 Aug 2012 00:47:21 -0300 Subject: ASoC: mxs: Fix the name of the SoC family SND_SOC_MXS_SGTL5000 is used on MXS boards, so fix the SoC family name. Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown --- sound/soc/mxs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/mxs/Kconfig b/sound/soc/mxs/Kconfig index 99a997f19bb9..b6fa77678d97 100644 --- a/sound/soc/mxs/Kconfig +++ b/sound/soc/mxs/Kconfig @@ -10,7 +10,7 @@ menuconfig SND_MXS_SOC if SND_MXS_SOC config SND_SOC_MXS_SGTL5000 - tristate "SoC Audio support for i.MX boards with sgtl5000" + tristate "SoC Audio support for MXS boards with sgtl5000" depends on I2C select SND_SOC_SGTL5000 help -- cgit v1.2.3-59-g8ed1b From 0865a75d4166bddc533fd50831829ceefb94f9b0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 7 Aug 2012 16:51:34 -0300 Subject: ASoC: imx-ssi: Remove mono support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Playing a mono track results in incorrect playback rate, ie, the audio is played at a faster rate. Remove mono support in the driver by setting 'channes_min' to dual-channel and this allows mono tracks to be played correctly. Reported-by: Gaëtan Carlier Tested-by: Gaëtan Carlier Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown --- sound/soc/fsl/imx-ssi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c index 28dd76c7cb1c..81d7728cf67f 100644 --- a/sound/soc/fsl/imx-ssi.c +++ b/sound/soc/fsl/imx-ssi.c @@ -380,13 +380,14 @@ static int imx_ssi_dai_probe(struct snd_soc_dai *dai) static struct snd_soc_dai_driver imx_ssi_dai = { .probe = imx_ssi_dai_probe, .playback = { - .channels_min = 1, + /* The SSI does not support monaural audio. */ + .channels_min = 2, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_96000, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, .capture = { - .channels_min = 1, + .channels_min = 2, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_96000, .formats = SNDRV_PCM_FMTBIT_S16_LE, -- cgit v1.2.3-59-g8ed1b From 0d624275720a4b01217693eb80d967a0d5f1f3a3 Mon Sep 17 00:00:00 2001 From: Vaibhav Bedia Date: Wed, 8 Aug 2012 20:40:31 +0530 Subject: ASoC: Davinci: McASP: Flush the FIFO before enabling FIFO should be flushed before it is enabled for the first time. This fixes the I/O errors reported by the ASoC core on a fresh boot Signed-off-by: Vaibhav Bedia Signed-off-by: Hebbar, Gururaja Signed-off-by: Mark Brown --- sound/soc/davinci/davinci-mcasp.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index 95441bfc8190..ce5e5cd254dd 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -380,14 +380,20 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev) static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream) { if (stream == SNDRV_PCM_STREAM_PLAYBACK) { - if (dev->txnumevt) /* enable FIFO */ + if (dev->txnumevt) { /* enable FIFO */ + mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, + FIFO_ENABLE); mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); + } mcasp_start_tx(dev); } else { - if (dev->rxnumevt) /* enable FIFO */ + if (dev->rxnumevt) { /* enable FIFO */ + mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, + FIFO_ENABLE); mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); + } mcasp_start_rx(dev); } } -- cgit v1.2.3-59-g8ed1b From 8b5eae137b91cb2db15fe2c5a913cafde4629339 Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Thu, 9 Aug 2012 18:08:40 -0400 Subject: ASoC: bfin: fix memory leak in sport3 controller driver Signed-off-by: Scott Jiang Signed-off-by: Mark Brown --- sound/soc/blackfin/bf6xx-sport.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'sound') diff --git a/sound/soc/blackfin/bf6xx-sport.c b/sound/soc/blackfin/bf6xx-sport.c index 318c5ba5360f..dfb744381c42 100644 --- a/sound/soc/blackfin/bf6xx-sport.c +++ b/sound/soc/blackfin/bf6xx-sport.c @@ -413,7 +413,14 @@ EXPORT_SYMBOL(sport_create); void sport_delete(struct sport_device *sport) { + if (sport->tx_desc) + dma_free_coherent(NULL, sport->tx_desc_size, + sport->tx_desc, 0); + if (sport->rx_desc) + dma_free_coherent(NULL, sport->rx_desc_size, + sport->rx_desc, 0); sport_free_resource(sport); + kfree(sport); } EXPORT_SYMBOL(sport_delete); -- cgit v1.2.3-59-g8ed1b From 52c0eee3329b08dfd912a59e0246e21026308301 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 30 Jul 2012 18:23:35 +0100 Subject: ASoC: wm8962: Don't duplicate bias level management in resume The core will bring the bias level up for us since we use idle_bias_off, duplicating this may be harmful. Signed-off-by: Mark Brown --- sound/soc/codecs/wm8962.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index aa9ce9dd7d8a..ce6720073798 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3733,21 +3733,6 @@ static int wm8962_runtime_resume(struct device *dev) regcache_sync(wm8962->regmap); - regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, - WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA, - WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA); - - /* Bias enable at 2*50k for ramp */ - regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, - WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, - WM8962_BIAS_ENA | 0x180); - - msleep(5); - - /* VMID back to 2x250k for standby */ - regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, - WM8962_VMID_SEL_MASK, 0x100); - return 0; } -- cgit v1.2.3-59-g8ed1b From 15676937e6a7e98d37f4c1eaa0e7b3c111627fce Mon Sep 17 00:00:00 2001 From: Chris Rattray Date: Thu, 9 Aug 2012 10:10:54 +0100 Subject: ASoC: wm8994: Add missing dapm routes for WM8958 rev A Signed-off-by: Chris Rattray Signed-off-by: Mark Brown --- sound/soc/codecs/wm8994.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sound') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 04ef03175c51..6c9eeca85b95 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -4038,6 +4038,8 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) break; case WM8958: if (wm8994->revision < 1) { + snd_soc_dapm_add_routes(dapm, wm8994_intercon, + ARRAY_SIZE(wm8994_intercon)); snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, ARRAY_SIZE(wm8994_revd_intercon)); snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, -- cgit v1.2.3-59-g8ed1b From fb099cb712e878b9eb4e78dd6b268312a0b2b50f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 9 Aug 2012 18:44:37 +0100 Subject: ASoC: core: Upgrade the severity of probe deferral errors to dev_err() In the past when ASoC had a custom probe deferral mechanism people complained about the logspam it generated and didn't want to know about the fact that we were doing probe deferral so all the error messages for it were at dev_dbg(), making diagnostics hard. Now that we have probe deferral as an accepted thing and it's generating log messages anyway there's no need to worry about this so upgrade the severity of all the probe deferral sources to dev_err() so that they are displayed by default. Also add one for missing aux_devs since there wasn't one. Reported-by: Russell King Signed-off-by: Mark Brown --- sound/soc/soc-core.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'sound') diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index f81c5976b961..c501af6d8dbe 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -826,7 +826,7 @@ static int soc_bind_dai_link(struct snd_soc_card *card, int num) } if (!rtd->cpu_dai) { - dev_dbg(card->dev, "CPU DAI %s not registered\n", + dev_err(card->dev, "CPU DAI %s not registered\n", dai_link->cpu_dai_name); return -EPROBE_DEFER; } @@ -857,14 +857,14 @@ static int soc_bind_dai_link(struct snd_soc_card *card, int num) } if (!rtd->codec_dai) { - dev_dbg(card->dev, "CODEC DAI %s not registered\n", + dev_err(card->dev, "CODEC DAI %s not registered\n", dai_link->codec_dai_name); return -EPROBE_DEFER; } } if (!rtd->codec) { - dev_dbg(card->dev, "CODEC %s not registered\n", + dev_err(card->dev, "CODEC %s not registered\n", dai_link->codec_name); return -EPROBE_DEFER; } @@ -888,7 +888,7 @@ static int soc_bind_dai_link(struct snd_soc_card *card, int num) rtd->platform = platform; } if (!rtd->platform) { - dev_dbg(card->dev, "platform %s not registered\n", + dev_err(card->dev, "platform %s not registered\n", dai_link->platform_name); return -EPROBE_DEFER; } @@ -1481,6 +1481,8 @@ static int soc_check_aux_dev(struct snd_soc_card *card, int num) return 0; } + dev_err(card->dev, "%s not registered\n", aux_dev->codec_name); + return -EPROBE_DEFER; } -- cgit v1.2.3-59-g8ed1b From 61f5d61ef94d7082d96494e2a6dd79de2b4437d2 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Wed, 8 Aug 2012 11:34:43 +0530 Subject: ASoC: Samsung: Fix build error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following build error: In file included from arch/arm/mach-exynos/include/mach/dma.h:24:0, from arch/arm/plat-samsung/include/plat/dma-ops.h:17, from arch/arm/plat-samsung/include/plat/dma.h:128, from sound/soc/samsung/pcm.c:23: arch/arm/plat-samsung/include/plat/dma-pl330.h:106:8: error: redefinition of ‘struct s3c2410_dma_client’ arch/arm/plat-samsung/include/plat/dma.h:40:8: note: originally defined here make[3]: *** [sound/soc/samsung/pcm.o] Error 1 Signed-off-by: Sachin Kamat Signed-off-by: Sachin Kamat Acked-by: Kukjin Kim Signed-off-by: Mark Brown --- sound/soc/samsung/pcm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c index b7b2a1f91425..89b064650f14 100644 --- a/sound/soc/samsung/pcm.c +++ b/sound/soc/samsung/pcm.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include "dma.h" #include "pcm.h" -- cgit v1.2.3-59-g8ed1b From 14ebd8a8c15e9fed638120bdb93f1a814e13d6a9 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Aug 2012 15:40:12 +0100 Subject: ASoC: wm5102: Add missing input PGA routes Signed-off-by: Mark Brown --- sound/soc/codecs/wm5102.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'sound') diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c index 6537f16d383e..496ce9a9d8be 100644 --- a/sound/soc/codecs/wm5102.c +++ b/sound/soc/codecs/wm5102.c @@ -639,6 +639,15 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { { "AIF2 Capture", NULL, "SYSCLK" }, { "AIF3 Capture", NULL, "SYSCLK" }, + { "IN1L PGA", NULL, "IN1L" }, + { "IN1R PGA", NULL, "IN1R" }, + + { "IN2L PGA", NULL, "IN2L" }, + { "IN2R PGA", NULL, "IN2R" }, + + { "IN3L PGA", NULL, "IN3L" }, + { "IN3R PGA", NULL, "IN3R" }, + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), -- cgit v1.2.3-59-g8ed1b From 17c3f7e8f3ef796a9db3b22f3797188d0e7ac88c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Aug 2012 15:40:22 +0100 Subject: ASoC: wm5110: Add missing input PGA routes Signed-off-by: Mark Brown --- sound/soc/codecs/wm5110.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'sound') diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c index 8033f7065189..01ebbcc5c6a4 100644 --- a/sound/soc/codecs/wm5110.c +++ b/sound/soc/codecs/wm5110.c @@ -681,6 +681,18 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { { "AIF2 Capture", NULL, "SYSCLK" }, { "AIF3 Capture", NULL, "SYSCLK" }, + { "IN1L PGA", NULL, "IN1L" }, + { "IN1R PGA", NULL, "IN1R" }, + + { "IN2L PGA", NULL, "IN2L" }, + { "IN2R PGA", NULL, "IN2R" }, + + { "IN3L PGA", NULL, "IN3L" }, + { "IN3R PGA", NULL, "IN3R" }, + + { "IN4L PGA", NULL, "IN4L" }, + { "IN4R PGA", NULL, "IN4R" }, + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), -- cgit v1.2.3-59-g8ed1b From 12022a785328fdf61a3e1a4bc34db0098dabe839 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 13 Aug 2012 16:28:36 +0100 Subject: ASoC: jack: Always notify full jack status Don't just notify for the bits we've updated, notify the full state of the jack otherwise users might get confused by misleading reports. Signed-off-by: Mark Brown --- sound/soc/soc-jack.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/soc-jack.c b/sound/soc/soc-jack.c index 7f8b3b7428bb..0c172938b82a 100644 --- a/sound/soc/soc-jack.c +++ b/sound/soc/soc-jack.c @@ -103,7 +103,7 @@ void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask) } /* Report before the DAPM sync to help users updating micbias status */ - blocking_notifier_call_chain(&jack->notifier, status, jack); + blocking_notifier_call_chain(&jack->notifier, jack->status, jack); snd_soc_dapm_sync(dapm); -- cgit v1.2.3-59-g8ed1b From 939d5044b117302cabdd30833685d9f214e9bff6 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 16 Aug 2012 13:08:23 +0100 Subject: ASoC: wm5102: Remove DRC2 It will be removed from future device revisions. Signed-off-by: Mark Brown --- sound/soc/codecs/wm5102.c | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c index 496ce9a9d8be..e33d327396ad 100644 --- a/sound/soc/codecs/wm5102.c +++ b/sound/soc/codecs/wm5102.c @@ -128,13 +128,9 @@ SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), -SND_SOC_BYTES_MASK("DRC2", ARIZONA_DRC2_CTRL1, 5, - ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), @@ -236,8 +232,6 @@ ARIZONA_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); @@ -349,10 +343,6 @@ SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, NULL, 0), -SND_SOC_DAPM_PGA("DRC2L", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, - NULL, 0), -SND_SOC_DAPM_PGA("DRC2R", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, - NULL, 0), SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, NULL, 0), @@ -466,8 +456,6 @@ ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), -ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), -ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), @@ -553,8 +541,6 @@ SND_SOC_DAPM_OUTPUT("SPKDAT1R"), { name, "EQ4", "EQ4" }, \ { name, "DRC1L", "DRC1L" }, \ { name, "DRC1R", "DRC1R" }, \ - { name, "DRC2L", "DRC2L" }, \ - { name, "DRC2R", "DRC2R" }, \ { name, "LHPF1", "LHPF1" }, \ { name, "LHPF2", "LHPF2" }, \ { name, "LHPF3", "LHPF3" }, \ @@ -684,8 +670,6 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), - ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), - ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), -- cgit v1.2.3-59-g8ed1b From ccf795847a38235ee4a56a24129ce75147d6ba8f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 16 Aug 2012 22:36:04 +0100 Subject: ASoC: wm9712: Fix microphone source selection Currently the microphone input source is not selectable as while there is a DAPM widget it's not connected to anything so it won't be properly instantiated. Add something more correct for the input structure to get things going, even though it's not hooked into the rest of the routing map and so won't actually achieve anything except allowing the relevant register bits to be written. Reported-by: Christop Fritz Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- sound/soc/codecs/wm9712.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c index f16fb361a4eb..fd74b8843d34 100644 --- a/sound/soc/codecs/wm9712.c +++ b/sound/soc/codecs/wm9712.c @@ -272,7 +272,7 @@ SOC_DAPM_ENUM("Route", wm9712_enum[9]); /* Mic select */ static const struct snd_kcontrol_new wm9712_mic_src_controls = -SOC_DAPM_ENUM("Route", wm9712_enum[7]); +SOC_DAPM_ENUM("Mic Source Select", wm9712_enum[7]); /* diff select */ static const struct snd_kcontrol_new wm9712_diff_sel_controls = @@ -291,7 +291,9 @@ SND_SOC_DAPM_MUX("Left Capture Select", SND_SOC_NOPM, 0, 0, &wm9712_capture_selectl_controls), SND_SOC_DAPM_MUX("Right Capture Select", SND_SOC_NOPM, 0, 0, &wm9712_capture_selectr_controls), -SND_SOC_DAPM_MUX("Mic Select Source", SND_SOC_NOPM, 0, 0, +SND_SOC_DAPM_MUX("Left Mic Select Source", SND_SOC_NOPM, 0, 0, + &wm9712_mic_src_controls), +SND_SOC_DAPM_MUX("Right Mic Select Source", SND_SOC_NOPM, 0, 0, &wm9712_mic_src_controls), SND_SOC_DAPM_MUX("Differential Source", SND_SOC_NOPM, 0, 0, &wm9712_diff_sel_controls), @@ -319,6 +321,7 @@ SND_SOC_DAPM_PGA("Out 3 PGA", AC97_INT_PAGING, 5, 1, NULL, 0), SND_SOC_DAPM_PGA("Line PGA", AC97_INT_PAGING, 2, 1, NULL, 0), SND_SOC_DAPM_PGA("Phone PGA", AC97_INT_PAGING, 1, 1, NULL, 0), SND_SOC_DAPM_PGA("Mic PGA", AC97_INT_PAGING, 0, 1, NULL, 0), +SND_SOC_DAPM_PGA("Differential Mic", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_MICBIAS("Mic Bias", AC97_INT_PAGING, 10, 1), SND_SOC_DAPM_OUTPUT("MONOOUT"), SND_SOC_DAPM_OUTPUT("HPOUTL"), @@ -379,6 +382,18 @@ static const struct snd_soc_dapm_route wm9712_audio_map[] = { {"Mic PGA", NULL, "MIC1"}, {"Mic PGA", NULL, "MIC2"}, + /* microphones */ + {"Differential Mic", NULL, "MIC1"}, + {"Differential Mic", NULL, "MIC2"}, + {"Left Mic Select Source", "Mic 1", "MIC1"}, + {"Left Mic Select Source", "Mic 2", "MIC2"}, + {"Left Mic Select Source", "Stereo", "MIC1"}, + {"Left Mic Select Source", "Differential", "Differential Mic"}, + {"Right Mic Select Source", "Mic 1", "MIC1"}, + {"Right Mic Select Source", "Mic 2", "MIC2"}, + {"Right Mic Select Source", "Stereo", "MIC2"}, + {"Right Mic Select Source", "Differential", "Differential Mic"}, + /* left capture selector */ {"Left Capture Select", "Mic", "MIC1"}, {"Left Capture Select", "Speaker Mixer", "Speaker Mixer"}, -- cgit v1.2.3-59-g8ed1b From 28c42c28309244d0b15d1b385e33429d59997679 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 31 Jul 2012 18:37:28 +0100 Subject: ASoC: wm9712: Fix inverted capture volume The capture volume increases with the register value so it shouldn't be flagged as inverted. Reported-by: Christoph Fritz Signed-off-by: Mark Brown --- sound/soc/codecs/wm9712.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c index fd74b8843d34..c6d2076a796b 100644 --- a/sound/soc/codecs/wm9712.c +++ b/sound/soc/codecs/wm9712.c @@ -148,7 +148,7 @@ SOC_SINGLE("Treble Volume", AC97_MASTER_TONE, 0, 15, 1), SOC_SINGLE("Capture ADC Switch", AC97_REC_GAIN, 15, 1, 1), SOC_ENUM("Capture Volume Steps", wm9712_enum[6]), -SOC_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 63, 1), +SOC_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 63, 0), SOC_SINGLE("Capture ZC Switch", AC97_REC_GAIN, 7, 1, 0), SOC_SINGLE_TLV("Mic 1 Volume", AC97_MIC, 8, 31, 1, main_tlv), -- cgit v1.2.3-59-g8ed1b