From 35267cea901456d16fb3841ab44347937bf0b087 Mon Sep 17 00:00:00 2001 From: John Garry Date: Thu, 29 Jul 2021 21:56:17 +0800 Subject: perf jevents: Relocate test events to cpu folder In future to add support for sys events, relocate the core and uncore events to a cpu folder. Signed-off-by: John Garry Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jin Yao Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linuxarm@huawei.com Link: https //lore.kernel.org/r/1627566986-30605-3-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/pmu-events/arch/test/test_cpu/branch.json | 12 ---------- .../perf/pmu-events/arch/test/test_cpu/cache.json | 5 ----- .../perf/pmu-events/arch/test/test_cpu/other.json | 26 ---------------------- .../perf/pmu-events/arch/test/test_cpu/uncore.json | 21 ----------------- .../pmu-events/arch/test/test_soc/cpu/branch.json | 12 ++++++++++ .../pmu-events/arch/test/test_soc/cpu/cache.json | 5 +++++ .../pmu-events/arch/test/test_soc/cpu/other.json | 26 ++++++++++++++++++++++ .../pmu-events/arch/test/test_soc/cpu/uncore.json | 21 +++++++++++++++++ 8 files changed, 64 insertions(+), 64 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/test/test_cpu/branch.json delete mode 100644 tools/perf/pmu-events/arch/test/test_cpu/cache.json delete mode 100644 tools/perf/pmu-events/arch/test/test_cpu/other.json delete mode 100644 tools/perf/pmu-events/arch/test/test_cpu/uncore.json create mode 100644 tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json create mode 100644 tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json create mode 100644 tools/perf/pmu-events/arch/test/test_soc/cpu/other.json create mode 100644 tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json (limited to 'tools/perf/pmu-events/arch') diff --git a/tools/perf/pmu-events/arch/test/test_cpu/branch.json b/tools/perf/pmu-events/arch/test/test_cpu/branch.json deleted file mode 100644 index 93ddfd8053ca..000000000000 --- a/tools/perf/pmu-events/arch/test/test_cpu/branch.json +++ /dev/null @@ -1,12 +0,0 @@ -[ - { - "EventName": "bp_l1_btb_correct", - "EventCode": "0x8a", - "BriefDescription": "L1 BTB Correction." - }, - { - "EventName": "bp_l2_btb_correct", - "EventCode": "0x8b", - "BriefDescription": "L2 BTB Correction." - } -] diff --git a/tools/perf/pmu-events/arch/test/test_cpu/cache.json b/tools/perf/pmu-events/arch/test/test_cpu/cache.json deleted file mode 100644 index 036d0efdb2bb..000000000000 --- a/tools/perf/pmu-events/arch/test/test_cpu/cache.json +++ /dev/null @@ -1,5 +0,0 @@ -[ - { - "ArchStdEvent": "L3_CACHE_RD" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/test/test_cpu/other.json b/tools/perf/pmu-events/arch/test/test_cpu/other.json deleted file mode 100644 index 7d53d7ecd723..000000000000 --- a/tools/perf/pmu-events/arch/test/test_cpu/other.json +++ /dev/null @@ -1,26 +0,0 @@ -[ - { - "EventCode": "0x6", - "Counter": "0,1", - "UMask": "0x80", - "EventName": "SEGMENT_REG_LOADS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Number of segment register loads." - }, - { - "EventCode": "0x9", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "DISPATCH_BLOCKED.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason" - }, - { - "EventCode": "0x3A", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "EIST_TRANS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/test/test_cpu/uncore.json b/tools/perf/pmu-events/arch/test/test_cpu/uncore.json deleted file mode 100644 index d0a890cc814d..000000000000 --- a/tools/perf/pmu-events/arch/test/test_cpu/uncore.json +++ /dev/null @@ -1,21 +0,0 @@ -[ - { - "EventCode": "0x02", - "EventName": "uncore_hisi_ddrc.flux_wcmd", - "BriefDescription": "DDRC write commands", - "PublicDescription": "DDRC write commands", - "Unit": "hisi_sccl,ddrc" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x81", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json new file mode 100644 index 000000000000..93ddfd8053ca --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json @@ -0,0 +1,12 @@ +[ + { + "EventName": "bp_l1_btb_correct", + "EventCode": "0x8a", + "BriefDescription": "L1 BTB Correction." + }, + { + "EventName": "bp_l2_btb_correct", + "EventCode": "0x8b", + "BriefDescription": "L2 BTB Correction." + } +] diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json new file mode 100644 index 000000000000..036d0efdb2bb --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "L3_CACHE_RD" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json new file mode 100644 index 000000000000..7d53d7ecd723 --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0x6", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "SEGMENT_REG_LOADS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Number of segment register loads." + }, + { + "EventCode": "0x9", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "DISPATCH_BLOCKED.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason" + }, + { + "EventCode": "0x3A", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "EIST_TRANS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json new file mode 100644 index 000000000000..d0a890cc814d --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json @@ -0,0 +1,21 @@ +[ + { + "EventCode": "0x02", + "EventName": "uncore_hisi_ddrc.flux_wcmd", + "BriefDescription": "DDRC write commands", + "PublicDescription": "DDRC write commands", + "Unit": "hisi_sccl,ddrc" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x81", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + } +] -- cgit v1.2.3-59-g8ed1b