# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller Binding

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm grpahics clock control module which supports the clocks, resets and
  power domains.

properties:
  compatible:
    enum:
      - qcom,msm8998-gpucc
      - qcom,sc7180-gpucc
      - qcom,sdm845-gpucc

  clocks:
    minItems: 1
    maxItems: 3
    items:
      - description: Board XO source
      - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
      - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)

  clock-names:
    minItems: 1
    maxItems: 3
    items:
      - const: xo
      - const: gpll0_main
      - const: gpll0_div

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

examples:
  # Example of GPUCC with clock node properties for SDM845:
  - |
    clock-controller@5090000 {
      compatible = "qcom,sdm845-gpucc";
      reg = <0x5090000 0x9000>;
      clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
      clock-names = "xo", "gpll0_main", "gpll0_div";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
     };
...