/* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ /include/ "skeleton.dtsi" / { aliases { serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; }; tzic: tz-interrupt-controller@e0000000 { compatible = "fsl,imx51-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; reg = <0xe0000000 0x4000>; }; clocks { #address-cells = <1>; #size-cells = <0>; ckil { compatible = "fsl,imx-ckil", "fixed-clock"; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; clock-frequency = <22579200>; }; ckih2 { compatible = "fsl,imx-ckih2", "fixed-clock"; clock-frequency = <0>; }; osc { compatible = "fsl,imx-osc", "fixed-clock"; clock-frequency = <24000000>; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; ipu: ipu@40000000 { #crtc-cells = <1>; compatible = "fsl,imx51-ipu"; reg = <0x40000000 0x20000000>; interrupts = <11 10>; }; aips@70000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x70000000 0x10000000>; ranges; spba@70000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x70000000 0x40000>; ranges; esdhc1: esdhc@70004000 { compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; clocks = <&clks 44>, <&clks 0>, <&clks 71>; clock-names = "ipg", "ahb", "per"; status = "disabled"; }; esdhc2: esdhc@70008000 { compatible = "fsl,imx51-esdhc"; reg = <0x70008000 0x4000>; interrupts = <2>; clocks = <&clks 45>, <&clks 0>, <&clks 72>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; uart3: serial@7000c000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x7000c000 0x4000>; interrupts = <33>; clocks = <&clks 32>, <&clks 33>; clock-names = "ipg", "per"; status = "disabled"; }; ecspi1: ecspi@70010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; reg = <0x70010000 0x4000>; interrupts = <36>; clocks = <&clks 51>, <&clks 52>; clock-names = "ipg", "per"; status = "disabled"; }; ssi2: ssi@70014000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; clocks = <&clks 49>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; esdhc3: esdhc@70020000 { compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; interrupts = <3>; clocks = <&clks 46>, <&clks 0>, <&clks 73>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; esdhc4: esdhc@70024000 { compatible = "fsl,imx51-esdhc"; reg = <0x70024000 0x4000>; interrupts = <4>; clocks = <&clks 47>, <&clks 0>, <&clks 74>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; }; usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; interrupts = <18>; status = "disabled"; }; usbh1: usb@73f80200 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80200 0x0200>; interrupts = <14>; status = "disabled"; }; usbh2: usb@73f80400 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80400 0x0200>; interrupts = <16>; status = "disabled"; }; usbh3: usb@73f80600 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80600 0x0200>; interrupts = <17>; status = "disabled"; }; gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f84000 0x4000>; interrupts = <50 51>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@73f88000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f88000 0x4000>; interrupts = <52 53>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@73f8c000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f8c000 0x4000>; interrupts = <54 55>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@73f90000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f90000 0x4000>; interrupts = <56 57>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; wdog1: wdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; clocks = <&clks 0>; }; wdog2: wdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; clocks = <&clks 0>; status = "disabled"; }; iomuxc: iomuxc@73fa8000 { compatible = "fsl,imx51-iomuxc"; reg = <0x73fa8000 0x4000>; audmux { pinctrl_audmux_1: audmuxgrp-1 { fsl,pins = < 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ >; }; }; fec { pinctrl_fec_1: fecgrp-1 { fsl,pins = < 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ >; }; }; ecspi1 { pinctrl_ecspi1_1: ecspi1grp-1 { fsl,pins = < 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ >; }; }; esdhc1 { pinctrl_esdhc1_1: esdhc1grp-1 { fsl,pins = < 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ >; }; }; esdhc2 { pinctrl_esdhc2_1: esdhc2grp-1 { fsl,pins = < 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ >; }; }; i2c2 { pinctrl_i2c2_1: i2c2grp-1 { fsl,pins = < 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ >; }; }; ipu_disp1 { pinctrl_ipu_disp1_1: ipudisp1grp-1 { fsl,pins = < 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */ 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */ 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */ 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */ 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */ 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */ 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */ 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */ 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */ 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */ 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */ 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */ 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */ 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */ 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */ 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */ 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */ 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */ 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */ 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */ 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */ 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */ 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */ 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */ 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */ 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */ >; }; }; ipu_disp2 { pinctrl_ipu_disp2_1: ipudisp2grp-1 { fsl,pins = < 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */ 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */ 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */ 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */ 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */ 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */ 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */ 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */ 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */ 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */ 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */ 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */ 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */ 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */ 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */ 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */ 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */ 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */ 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */ 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */ >; }; }; uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ >; }; }; uart2 { pinctrl_uart2_1: uart2grp-1 { fsl,pins = < 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ >; }; }; uart3 { pinctrl_uart3_1: uart3grp-1 { fsl,pins = < 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ >; }; }; }; pwm1: pwm@73fb4000 { #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks 37>, <&clks 38>; clock-names = "ipg", "per"; interrupts = <61>; }; pwm2: pwm@73fb8000 { #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks 39>, <&clks 40>; clock-names = "ipg", "per"; interrupts = <94>; }; uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; clocks = <&clks 28>, <&clks 29>; clock-names = "ipg", "per"; status = "disabled"; }; uart2: serial@73fc0000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fc0000 0x4000>; interrupts = <32>; clocks = <&clks 30>, <&clks 31>; clock-names = "ipg", "per"; status = "disabled"; }; clks: ccm@73fd4000{ compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; interrupts = <0 71 0x04 0 72 0x04>; #clock-cells = <1>; }; }; aips@80000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x80000000 0x10000000>; ranges; ecspi2: ecspi@83fac000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; reg = <0x83fac000 0x4000>; interrupts = <37>; clocks = <&clks 53>, <&clks 54>; clock-names = "ipg", "per"; status = "disabled"; }; sdma: sdma@83fb0000 { compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; clocks = <&clks 56>, <&clks 56>; clock-names = "ipg", "ahb"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; cspi: cspi@83fc0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; reg = <0x83fc0000 0x4000>; interrupts = <38>; clocks = <&clks 55>, <&clks 0>; clock-names = "ipg", "per"; status = "disabled"; }; i2c2: i2c@83fc4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; reg = <0x83fc4000 0x4000>; interrupts = <63>; clocks = <&clks 35>; status = "disabled"; }; i2c1: i2c@83fc8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; reg = <0x83fc8000 0x4000>; interrupts = <62>; clocks = <&clks 34>; status = "disabled"; }; ssi1: ssi@83fcc000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; clocks = <&clks 48>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; audmux: audmux@83fd0000 { compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; reg = <0x83fd0000 0x4000>; status = "disabled"; }; nfc: nand@83fdb000 { compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; interrupts = <8>; clocks = <&clks 60>; status = "disabled"; }; ssi3: ssi@83fe8000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; clocks = <&clks 50>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; fec: ethernet@83fec000 { compatible = "fsl,imx51-fec", "fsl,imx27-fec"; reg = <0x83fec000 0x4000>; interrupts = <87>; clocks = <&clks 42>, <&clks 42>, <&clks 42>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; }; }; };