/* * linux/drivers/video/s3c2410fb.c * Copyright (c) Arnaud Patard, Ben Dooks * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive for * more details. * * S3C2410 LCD Controller Frame Buffer Driver * based on skeletonfb.c, sa1100fb.c and others * * ChangeLog * 2005-04-07: Arnaud Patard * - u32 state -> pm_message_t state * - S3C2410_{VA,SZ}_LCD -> S3C24XX * * 2005-03-15: Arnaud Patard * - Removed the ioctl * - use readl/writel instead of __raw_writel/__raw_readl * * 2004-12-04: Arnaud Patard * - Added the possibility to set on or off the * debugging mesaages * - Replaced 0 and 1 by on or off when reading the * /sys files * * 2005-03-23: Ben Dooks * - added non 16bpp modes * - updated platform information for range of x/y/bpp * - add code to ensure palette is written correctly * - add pixel clock divisor control * * 2004-11-11: Arnaud Patard * - Removed the use of currcon as it no more exist * - Added LCD power sysfs interface * * 2004-11-03: Ben Dooks * - minor cleanups * - add suspend/resume support * - s3c2410fb_setcolreg() not valid in >8bpp modes * - removed last CONFIG_FB_S3C2410_FIXED * - ensure lcd controller stopped before cleanup * - added sysfs interface for backlight power * - added mask for gpio configuration * - ensured IRQs disabled during GPIO configuration * - disable TPAL before enabling video * * 2004-09-20: Arnaud Patard * - Suppress command line options * * 2004-09-15: Arnaud Patard * - code cleanup * * 2004-09-07: Arnaud Patard * - Renamed from h1940fb.c to s3c2410fb.c * - Add support for different devices * - Backlight support * * 2004-09-05: Herbert Pötzl * - added clock (de-)allocation code * - added fixem fbmem option * * 2004-07-27: Arnaud Patard * - code cleanup * - added a forgotten return in h1940fb_init * * 2004-07-19: Herbert Pötzl * - code cleanup and extended debugging * * 2004-07-15: Arnaud Patard * - First version */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef CONFIG_PM #include #endif #include "s3c2410fb.h" static struct s3c2410fb_mach_info *mach_info; /* Debugging stuff */ #ifdef CONFIG_FB_S3C2410_DEBUG static int debug = 1; #else static int debug = 0; #endif #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); } /* useful functions */ /* s3c2410fb_set_lcdaddr * * initialise lcd controller address pointers */ static void s3c2410fb_set_lcdaddr(struct fb_info *info) { unsigned long saddr1, saddr2, saddr3; int line_length = info->var.xres * info->var.bits_per_pixel; saddr1 = info->fix.smem_start >> 1; saddr2 = info->fix.smem_start; saddr2 += (line_length * info->var.yres) / 8; saddr2 >>= 1; saddr3 = S3C2410_OFFSIZE(0) | S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff); dprintk("LCDSADDR1 = 0x%08lx\n", saddr1); dprintk("LCDSADDR2 = 0x%08lx\n", saddr2); dprintk("LCDSADDR3 = 0x%08lx\n", saddr3); writel(saddr1, S3C2410_LCDSADDR1); writel(saddr2, S3C2410_LCDSADDR2); writel(saddr3, S3C2410_LCDSADDR3); } /* s3c2410fb_calc_pixclk() * * calculate divisor for clk->pixclk */ static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi, unsigned long pixclk) { unsigned long clk = clk_get_rate(fbi->clk); unsigned long long div; /* pixclk is in picoseoncds, our clock is in Hz * * Hz -> picoseconds is / 10^-12 */ div = (unsigned long long)clk * pixclk; do_div(div, 1000000UL); do_div(div, 1000000UL); dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div); return div; } /* * s3c2410fb_check_var(): * Get the video params out of 'var'. If a value doesn't fit, round it up, * if it's too big, return -EINVAL. * */ static int s3c2410fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct s3c2410fb_info *fbi = info->par; struct s3c2410fb_mach_info *mach_info = fbi->mach_info; struct s3c2410fb_display *display = NULL; unsigned i; dprintk("check_var(var=%p, info=%p)\n", var, info); /* validate x/y resolution */ for (i = 0; i < mach_info->num_displays; i++) if (var->yres == mach_info->displays[i].yres && var->xres == mach_info->displays[i].xres && var->bits_per_pixel == mach_info->displays[i].bpp) { display = mach_info->displays + i; fbi->current_display = i; break; } if (!display) { dprintk("wrong resolution or depth %dx%d at %d bpp\n", var->xres, var->yres, var->bits_per_pixel); return -EINVAL; } var->transp.offset = 0; var->transp.length = 0; /* set r/g/b positions */ switch (var->bits_per_pixel) { case 1: case 2: case 4: var->red.offset = 0; var->red.length = var->bits_per_pixel; var->green = var->red; var->blue = var->red; break; case 8: if (display->type != S3C2410_LCDCON1_TFT) { /* 8 bpp 332 */ var->red.length = 3; var->red.offset = 5; var->green.length = 3; var->green.offset = 2; var->blue.length = 2; var->blue.offset = 0; } else { var->red.offset = 0; var->red.length = 8; var->green = var->red; var->blue = var->red; } break; case 12: /* 12 bpp 444 */ var->red.length = 4; var->red.offset = 8; var->green.length = 4; var->green.offset = 4; var->blue.length = 4; var->blue.offset = 0; break; default: case 16: if (display->regs.lcdcon5 & S3C2410_LCDCON5_FRM565) { /* 16 bpp, 565 format */ var->red.offset = 11; var->green.offset = 5; var->blue.offset = 0; var->red.length = 5; var->green.length = 6; var->blue.length = 5; } else { /* 16 bpp, 5551 format */ var->red.offset = 11; var->green.offset = 6; var->blue.offset = 1; var->red.length = 5; var->green.length = 5; var->blue.length = 5; } break; case 24: /* 24 bpp 888 */ var->red.length = 8; var->red.offset = 16; var->green.length = 8; var->green.offset = 8; var->blue.length = 8; var->blue.offset = 0; break; } return 0; } /* s3c2410fb_activate_var * * activate (set) the controller from the given framebuffer * information */ static void s3c2410fb_activate_var(struct fb_info *info, struct fb_var_screeninfo *var) { struct s3c2410fb_info *fbi = info->par; struct s3c2410fb_mach_info *mach_info = fbi->mach_info; struct s3c2410fb_display *display = mach_info->displays + fbi->current_display; int hs; fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK; fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT; dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres); dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres); dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel); fbi->regs.lcdcon1 |= display->type; if (display->type == S3C2410_LCDCON1_TFT) switch (var->bits_per_pixel) { case 1: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP; break; case 2: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP; break; case 4: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP; break; case 8: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP; break; case 16: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP; break; default: /* invalid pixel depth */ dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel); } else switch (var->bits_per_pixel) { case 1: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP; break; case 2: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY; break; case 4: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY; break; case 8: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP; break; case 12: fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP; break; default: /* invalid pixel depth */ dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel); } /* check to see if we need to update sync/borders */ if (!mach_info->fixed_syncs) { dprintk("setting vert: up=%d, low=%d, sync=%d\n", var->upper_margin, var->lower_margin, var->vsync_len); dprintk("setting horz: lft=%d, rt=%d, sync=%d\n", var->left_margin, var->right_margin, var->hsync_len); fbi->regs.lcdcon2 = S3C2410_LCDCON2_VBPD(var->upper_margin - 1) | S3C2410_LCDCON2_VFPD(var->lower_margin - 1) | S3C2410_LCDCON2_VSPW(var->vsync_len - 1); fbi->regs.lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) | S3C2410_LCDCON3_HFPD(var->left_margin - 1); fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff); fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1); } /* update X/Y info */ fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff); fbi->regs.lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1); switch (display->type) { case S3C2410_LCDCON1_DSCAN4: case S3C2410_LCDCON1_STN8: hs = var->xres / 8; break; case S3C2410_LCDCON1_STN4: hs = var->xres / 4; break; default: case S3C2410_LCDCON1_TFT: hs = var->xres; break; } /* Special cases : STN color displays */ if (((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) || ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP)) hs = hs * 3; fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff); fbi->regs.lcdcon3 |= S3C2410_LCDCON3_HOZVAL(hs - 1); if (var->pixclock > 0) { int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock); if (display->type == S3C2410_LCDCON1_TFT) { clkdiv = (clkdiv / 2) - 1; if (clkdiv < 0) clkdiv = 0; } else { clkdiv = (clkdiv / 2); if (clkdiv < 2) clkdiv = 2; } fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff); fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv); } /* write new registers */ dprintk("new register set:\n"); dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1); dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2); dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3); dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4); dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5); writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1); writel(fbi->regs.lcdcon2, S3C2410_LCDCON2); writel(fbi->regs.lcdcon3, S3C2410_LCDCON3); writel(fbi->regs.lcdcon4, S3C2410_LCDCON4); writel(fbi->regs.lcdcon5, S3C2410_LCDCON5); /* set lcd address pointers */ s3c2410fb_set_lcdaddr(info); writel(fbi->regs.lcdcon1, S3C2410_LCDCON1); } /* * s3c2410fb_set_par - Alters the hardware state. * @info: frame buffer structure that represents a single frame buffer * */ static int s3c2410fb_set_par(struct fb_info *info) { struct fb_var_screeninfo *var = &info->var; switch (var->bits_per_pixel) { case 16: info->fix.visual = FB_VISUAL_TRUECOLOR; break; case 1: info->fix.visual = FB_VISUAL_MONO01; break; default: info->fix.visual = FB_VISUAL_PSEUDOCOLOR; break; } info->fix.line_length = (var->width * var->bits_per_pixel) / 8; /* activate this new configuration */ s3c2410fb_activate_var(info, var); return 0; } static void schedule_palette_update(struct s3c2410fb_info *fbi, unsigned int regno, unsigned int val) { unsigned long flags; unsigned long irqen; void __iomem *regs = fbi->io; local_irq_save(flags); fbi->palette_buffer[regno] = val; if (!fbi->palette_ready) { fbi->palette_ready = 1; /* enable IRQ */ irqen = readl(regs + S3C2410_LCDINTMSK); irqen &= ~S3C2410_LCDINT_FRSYNC; writel(irqen, regs + S3C2410_LCDINTMSK); } local_irq_restore(flags); } /* from pxafb.c */ static inline unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf) { chan &= 0xffff; chan >>= 16 - bf->length; return chan << bf->offset; } static int s3c2410fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { struct s3c2410fb_info *fbi = info->par; unsigned int val; /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n", regno, red, green, blue); */ switch (info->fix.visual) { case FB_VISUAL_TRUECOLOR: /* true-colour, use pseudo-palette */ if (regno < 16) { u32 *pal = info->pseudo_palette; val = chan_to_field(red, &info->var.red); val |= chan_to_field(green, &info->var.green); val |= chan_to_field(blue, &info->var.blue); pal[regno] = val; } break; case FB_VISUAL_PSEUDOCOLOR: if (regno < 256) { /* currently assume RGB 5-6-5 mode */ val = ((red >> 0) & 0xf800); val |= ((green >> 5) & 0x07e0); val |= ((blue >> 11) & 0x001f); writel(val, S3C2410_TFTPAL(regno)); schedule_palette_update(fbi, regno, val); } break; default: return 1; /* unknown type */ } return 0; } /* * s3c2410fb_blank * @blank_mode: the blank mode we want. * @info: frame buffer structure that represents a single frame buffer * * Blank the screen if blank_mode != 0, else unblank. Return 0 if * blanking succeeded, != 0 if un-/blanking failed due to e.g. a * video mode which doesn't support it. Implements VESA suspend * and powerdown modes on hardware that supports disabling hsync/vsync: * blank_mode == 2: suspend vsync * blank_mode == 3: suspend hsync * blank_mode == 4: powerdown * * Returns negative errno on error, or zero on success. * */ static int s3c2410fb_blank(int blank_mode, struct fb_info *info) { dprintk("blank(mode=%d, info=%p)\n", blank_mode, info); if (mach_info == NULL) return -EINVAL; if (blank_mode == FB_BLANK_UNBLANK) writel(0x0, S3C2410_TPAL); else { dprintk("setting TPAL to output 0x000000\n"); writel(S3C2410_TPAL_EN, S3C2410_TPAL); } return 0; } static int s3c2410fb_debug_show(struct device *dev, struct device_attribute *attr, char *buf) { return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off"); } static int s3c2410fb_debug_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { if (mach_info == NULL) return -EINVAL; if (len < 1) return -EINVAL; if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0) { debug = 1; printk(KERN_DEBUG "s3c2410fb: Debug On"); } else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0) { debug = 0; printk(KERN_DEBUG "s3c2410fb: Debug Off"); } else { return -EINVAL; } return len; } static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store); static struct fb_ops s3c2410fb_ops = { .owner = THIS_MODULE, .fb_check_var = s3c2410fb_check_var, .fb_set_par = s3c2410fb_set_par, .fb_blank = s3c2410fb_blank, .fb_setcolreg = s3c2410fb_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, }; /* * s3c2410fb_map_video_memory(): * Allocates the DRAM memory for the frame buffer. This buffer is * remapped into a non-cached, non-buffered, memory region to * allow palette and pixel writes to occur without flushing the * cache. Once this area is remapped, all virtual memory * access to the video memory should occur at the new region. */ static int __init s3c2410fb_map_video_memory(struct fb_info *info) { struct s3c2410fb_info *fbi = info->par; dprintk("map_video_memory(fbi=%p)\n", fbi); fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE); fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, &fbi->map_dma, GFP_KERNEL); fbi->map_size = info->fix.smem_len; if (fbi->map_cpu) { /* prevent initial garbage on screen */ dprintk("map_video_memory: clear %p:%08x\n", fbi->map_cpu, fbi->map_size); memset(fbi->map_cpu, 0xf0, fbi->map_size); fbi->screen_dma = fbi->map_dma; info->screen_base = fbi->map_cpu; info->fix.smem_start = fbi->screen_dma; dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n", fbi->map_dma, fbi->map_cpu, info->fix.smem_len); } return fbi->map_cpu ? 0 : -ENOMEM; } static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi) { dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu, fbi->map_dma); } static inline void modify_gpio(void __iomem *reg, unsigned long set, unsigned long mask) { unsigned long tmp; tmp = readl(reg) & ~mask; writel(tmp | set, reg); } /* * s3c2410fb_init_registers - Initialise all LCD-related registers */ static int s3c2410fb_init_registers(struct fb_info *info) { struct s3c2410fb_info *fbi = info->par; unsigned long flags; void __iomem *regs = fbi->io; /* Initialise LCD with values from haret */ local_irq_save(flags); /* modify the gpio(s) with interrupts set (bjd) */ modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask); modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask); modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask); modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask); local_irq_restore(flags); writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1); writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2); writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3); writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4); writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5); s3c2410fb_set_lcdaddr(info); dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel); writel(mach_info->lpcsel, regs + S3C2410_LPCSEL); dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL)); /* ensure temporary palette disabled */ writel(0x00, regs + S3C2410_TPAL); /* Enable video by setting the ENVID bit to 1 */ fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID; writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1); return 0; } static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi) { unsigned int i; void __iomem *regs = fbi->io; fbi->palette_ready = 0; for (i = 0; i < 256; i++) { unsigned long ent = fbi->palette_buffer[i]; if (ent == PALETTE_BUFF_CLEAR) continue; writel(ent, regs + S3C2410_TFTPAL(i)); /* it seems the only way to know exactly * if the palette wrote ok, is to check * to see if the value verifies ok */ if (readw(regs + S3C2410_TFTPAL(i)) == ent) fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR; else fbi->palette_ready = 1; /* retry */ } } static irqreturn_t s3c2410fb_irq(int irq, void *dev_id) { struct s3c2410fb_info *fbi = dev_id; void __iomem *regs = fbi->io; unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND); if (lcdirq & S3C2410_LCDINT_FRSYNC) { if (fbi->palette_ready) s3c2410fb_write_palette(fbi); writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND); writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND); } return IRQ_HANDLED; } static char driver_name[] = "s3c2410fb"; static int __init s3c2410fb_probe(struct platform_device *pdev) { struct s3c2410fb_info *info; struct s3c2410fb_display *display; struct fb_info *fbinfo; struct s3c2410fb_hw *mregs; struct resource *res; int ret; int irq; int i; int size; u32 lcdcon1; mach_info = pdev->dev.platform_data; if (mach_info == NULL) { dev_err(&pdev->dev, "no platform data for lcd, cannot attach\n"); return -EINVAL; } display = mach_info->displays + mach_info->default_display; mregs = &display->regs; irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq for device\n"); return -ENOENT; } fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev); if (!fbinfo) return -ENOMEM; info = fbinfo->par; info->dev = &pdev->dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(&pdev->dev, "failed to get memory registers\n"); ret = -ENXIO; goto dealloc_fb; } size = (res->end - res->start) + 1; info->mem = request_mem_region(res->start, size, pdev->name); if (info->mem == NULL) { dev_err(&pdev->dev, "failed to get memory region\n"); ret = -ENOENT; goto dealloc_fb; } info->io = ioremap(res->start, size); if (info->io == NULL) { dev_err(&pdev->dev, "ioremap() of registers failed\n"); ret = -ENXIO; goto release_mem; } platform_set_drvdata(pdev, fbinfo); dprintk("devinit\n"); strcpy(fbinfo->fix.id, driver_name); memcpy(&info->regs, &display->regs, sizeof(info->regs)); /* Stop the video and unset ENVID if set */ info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID; lcdcon1 = readl(info->io + S3C2410_LCDCON1); writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1); info->mach_info = pdev->dev.platform_data; info->current_display = mach_info->default_display; fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; fbinfo->fix.type_aux = 0; fbinfo->fix.xpanstep = 0; fbinfo->fix.ypanstep = 0; fbinfo->fix.ywrapstep = 0; fbinfo->fix.accel = FB_ACCEL_NONE; fbinfo->var.nonstd = 0; fbinfo->var.activate = FB_ACTIVATE_NOW; fbinfo->var.height = display->height; fbinfo->var.width = display->width; fbinfo->var.accel_flags = 0; fbinfo->var.vmode = FB_VMODE_NONINTERLACED; fbinfo->fbops = &s3c2410fb_ops; fbinfo->flags = FBINFO_FLAG_DEFAULT; fbinfo->pseudo_palette = &info->pseudo_pal; fbinfo->var.xres = display->xres; fbinfo->var.xres_virtual = display->xres; fbinfo->var.yres = display->yres; fbinfo->var.yres_virtual = display->yres; fbinfo->var.bits_per_pixel = display->bpp; fbinfo->var.upper_margin = S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1; fbinfo->var.lower_margin = S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1; fbinfo->var.vsync_len = S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1; fbinfo->var.left_margin = S3C2410_LCDCON3_GET_HFPD(mregs->lcdcon3) + 1; fbinfo->var.right_margin = S3C2410_LCDCON3_GET_HBPD(mregs->lcdcon3) + 1; fbinfo->var.hsync_len = S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1; fbinfo->var.red.offset = 11; fbinfo->var.green.offset = 5; fbinfo->var.blue.offset = 0; fbinfo->var.transp.offset = 0; fbinfo->var.red.length = 5; fbinfo->var.green.length = 6; fbinfo->var.blue.length = 5; fbinfo->var.transp.length = 0; /* find maximum required memory size for display */ for (i = 0; i < mach_info->num_displays; i++) { unsigned long smem_len = mach_info->displays[i].xres; smem_len *= mach_info->displays[i].yres; smem_len *= mach_info->displays[i].bpp; smem_len >>= 3; if (fbinfo->fix.smem_len < smem_len) fbinfo->fix.smem_len = smem_len; } for (i = 0; i < 256; i++) info->palette_buffer[i] = PALETTE_BUFF_CLEAR; ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info); if (ret) { dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret); ret = -EBUSY; goto release_regs; } info->clk = clk_get(NULL, "lcd"); if (!info->clk || IS_ERR(info->clk)) { printk(KERN_ERR "failed to get lcd clock source\n"); ret = -ENOENT; goto release_irq; } clk_enable(info->clk); dprintk("got and enabled clock\n"); msleep(1); /* Initialize video memory */ ret = s3c2410fb_map_video_memory(fbinfo); if (ret) { printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret); ret = -ENOMEM; goto release_clock; } dprintk("got video memory\n"); s3c2410fb_init_registers(fbinfo); s3c2410fb_check_var(&fbinfo->var, fbinfo); ret = register_framebuffer(fbinfo); if (ret < 0) { printk(KERN_ERR "Failed to register framebuffer device: %d\n", ret); goto free_video_memory; } /* create device files */ device_create_file(&pdev->dev, &dev_attr_debug); printk(KERN_INFO "fb%d: %s frame buffer device\n", fbinfo->node, fbinfo->fix.id); return 0; free_video_memory: s3c2410fb_unmap_video_memory(info); release_clock: clk_disable(info->clk); clk_put(info->clk); release_irq: free_irq(irq, info); release_regs: iounmap(info->io); release_mem: release_resource(info->mem); kfree(info->mem); dealloc_fb: framebuffer_release(fbinfo); return ret; } /* s3c2410fb_stop_lcd * * shutdown the lcd controller */ static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi) { unsigned long flags; local_irq_save(flags); fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID; writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1); local_irq_restore(flags); } /* * Cleanup */ static int s3c2410fb_remove(struct platform_device *pdev) { struct fb_info *fbinfo = platform_get_drvdata(pdev); struct s3c2410fb_info *info = fbinfo->par; int irq; s3c2410fb_stop_lcd(info); msleep(1); s3c2410fb_unmap_video_memory(info); if (info->clk) { clk_disable(info->clk); clk_put(info->clk); info->clk = NULL; } irq = platform_get_irq(pdev, 0); free_irq(irq, info); release_resource(info->mem); kfree(info->mem); iounmap(info->io); unregister_framebuffer(fbinfo); return 0; } #ifdef CONFIG_PM /* suspend and resume support for the lcd controller */ static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state) { struct fb_info *fbinfo = platform_get_drvdata(dev); struct s3c2410fb_info *info = fbinfo->par; s3c2410fb_stop_lcd(info); /* sleep before disabling the clock, we need to ensure * the LCD DMA engine is not going to get back on the bus * before the clock goes off again (bjd) */ msleep(1); clk_disable(info->clk); return 0; } static int s3c2410fb_resume(struct platform_device *dev) { struct fb_info *fbinfo = platform_get_drvdata(dev); struct s3c2410fb_info *info = fbinfo->par; clk_enable(info->clk); msleep(1); s3c2410fb_init_registers(info); return 0; } #else #define s3c2410fb_suspend NULL #define s3c2410fb_resume NULL #endif static struct platform_driver s3c2410fb_driver = { .probe = s3c2410fb_probe, .remove = s3c2410fb_remove, .suspend = s3c2410fb_suspend, .resume = s3c2410fb_resume, .driver = { .name = "s3c2410-lcd", .owner = THIS_MODULE, }, }; int __devinit s3c2410fb_init(void) { return platform_driver_register(&s3c2410fb_driver); } static void __exit s3c2410fb_cleanup(void) { platform_driver_unregister(&s3c2410fb_driver); } module_init(s3c2410fb_init); module_exit(s3c2410fb_cleanup); MODULE_AUTHOR("Arnaud Patard , " "Ben Dooks "); MODULE_DESCRIPTION("Framebuffer driver for the s3c2410"); MODULE_LICENSE("GPL");