/* * * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp */ #ifndef _AU1000_H_ #define _AU1000_H_ #ifndef _LANGUAGE_ASSEMBLY #include #include #include /* cpu pipeline flush */ void static inline au_sync(void) { __asm__ volatile ("sync"); } void static inline au_sync_udelay(int us) { __asm__ volatile ("sync"); udelay(us); } void static inline au_sync_delay(int ms) { __asm__ volatile ("sync"); mdelay(ms); } void static inline au_writeb(u8 val, unsigned long reg) { *(volatile u8 *)(reg) = val; } void static inline au_writew(u16 val, unsigned long reg) { *(volatile u16 *)(reg) = val; } void static inline au_writel(u32 val, unsigned long reg) { *(volatile u32 *)(reg) = val; } static inline u8 au_readb(unsigned long reg) { return (*(volatile u8 *)reg); } static inline u16 au_readw(unsigned long reg) { return (*(volatile u16 *)reg); } static inline u32 au_readl(unsigned long reg) { return (*(volatile u32 *)reg); } static __inline__ int au_ffz(unsigned int x) { if ((x = ~x) == 0) return 32; return __ilog2(x & -x); } /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ static __inline__ int au_ffs(int x) { return __ilog2(x & -x) + 1; } /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); extern void set_au1x00_lcd_clock(void); extern unsigned int get_au1x00_lcd_clock(void); /* * Every board describes its IRQ mapping with this table. */ typedef struct au1xxx_irqmap { int im_irq; int im_type; int im_request; } au1xxx_irq_map_t; /* * init_IRQ looks for a table with this name. */ extern au1xxx_irq_map_t au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ #ifdef CONFIG_PM /* no CP0 timer irq */ #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) #else #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) #endif /* * SDRAM Register Offsets */ #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) #define MEM_SDMODE0 (0x0000) #define MEM_SDMODE1 (0x0004) #define MEM_SDMODE2 (0x0008) #define MEM_SDADDR0 (0x000C) #define MEM_SDADDR1 (0x0010) #define MEM_SDADDR2 (0x0014) #define MEM_SDREFCFG (0x0018) #define MEM_SDPRECMD (0x001C) #define MEM_SDAUTOREF (0x0020) #define MEM_SDWRMD0 (0x0024) #define MEM_SDWRMD1 (0x0028) #define MEM_SDWRMD2 (0x002C) #define MEM_SDSLEEP (0x0030) #define MEM_SDSMCKE (0x0034) /* * MEM_SDMODE register content definitions */ #define MEM_SDMODE_F (1<<22) #define MEM_SDMODE_SR (1<<21) #define MEM_SDMODE_BS (1<<20) #define MEM_SDMODE_RS (3<<18) #define MEM_SDMODE_CS (7<<15) #define MEM_SDMODE_TRAS (15<<11) #define MEM_SDMODE_TMRD (3<<9) #define MEM_SDMODE_TWR (3<<7) #define MEM_SDMODE_TRP (3<<5) #define MEM_SDMODE_TRCD (3<<3) #define MEM_SDMODE_TCL (7<<0) #define MEM_SDMODE_BS_2Bank (0<<20) #define MEM_SDMODE_BS_4Bank (1<<20) #define MEM_SDMODE_RS_11Row (0<<18) #define MEM_SDMODE_RS_12Row (1<<18) #define MEM_SDMODE_RS_13Row (2<<18) #define MEM_SDMODE_RS_N(N) ((N)<<18) #define MEM_SDMODE_CS_7Col (0<<15) #define MEM_SDMODE_CS_8Col (1<<15) #define MEM_SDMODE_CS_9Col (2<<15) #define MEM_SDMODE_CS_10Col (3<<15) #define MEM_SDMODE_CS_11Col (4<<15) #define MEM_SDMODE_CS_N(N) ((N)<<15) #define MEM_SDMODE_TRAS_N(N) ((N)<<11) #define MEM_SDMODE_TMRD_N(N) ((N)<<9) #define MEM_SDMODE_TWR_N(N) ((N)<<7) #define MEM_SDMODE_TRP_N(N) ((N)<<5) #define MEM_SDMODE_TRCD_N(N) ((N)<<3) #define MEM_SDMODE_TCL_N(N) ((N)<<0) /* * MEM_SDADDR register contents definitions */ #define MEM_SDADDR_E (1<<20) #define MEM_SDADDR_CSBA (0x03FF<<10) #define MEM_SDADDR_CSMASK (0x03FF<<0) #define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) /* * MEM_SDREFCFG register content definitions */ #define MEM_SDREFCFG_TRC (15<<28) #define MEM_SDREFCFG_TRPM (3<<26) #define MEM_SDREFCFG_E (1<<25) #define MEM_SDREFCFG_RE (0x1ffffff<<0) #define MEM_SDREFCFG_TRC_N(N) ((N)<>2)&0x3) #define MAC_TX_BUFF0_LEN 0x8 #define MAC_TX_BUFF1_STATUS 0x10 #define MAC_TX_BUFF1_ADDR 0x14 #define MAC_TX_BUFF1_LEN 0x18 #define MAC_TX_BUFF2_STATUS 0x20 #define MAC_TX_BUFF2_ADDR 0x24 #define MAC_TX_BUFF2_LEN 0x28 #define MAC_TX_BUFF3_STATUS 0x30 #define MAC_TX_BUFF3_ADDR 0x34 #define MAC_TX_BUFF3_LEN 0x38 #define MAC0_RX_DMA_ADDR 0xB4004100 #define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 #define RX_FRAME_LEN_MASK 0x3fff #define RX_WDOG_TIMER (1<<14) #define RX_RUNT (1<<15) #define RX_OVERLEN (1<<16) #define RX_COLL (1<<17) #define RX_ETHER (1<<18) #define RX_MII_ERROR (1<<19) #define RX_DRIBBLING (1<<20) #define RX_CRC_ERROR (1<<21) #define RX_VLAN1 (1<<22) #define RX_VLAN2 (1<<23) #define RX_LEN_ERROR (1<<24) #define RX_CNTRL_FRAME (1<<25) #define RX_U_CNTRL_FRAME (1<<26) #define RX_MCAST_FRAME (1<<27) #define RX_BCAST_FRAME (1<<28) #define RX_FILTER_FAIL (1<<29) #define RX_PACKET_FILTER (1<<30) #define RX_MISSED_FRAME (1<<31) #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 #define RX_DMA_ENABLE (1<<0) #define RX_T_DONE (1<<1) #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) #define MAC_RX_BUFF1_STATUS 0x10 #define MAC_RX_BUFF1_ADDR 0x14 #define MAC_RX_BUFF2_STATUS 0x20 #define MAC_RX_BUFF2_ADDR 0x24 #define MAC_RX_BUFF3_STATUS 0x30 #define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ #define UART_BASE UART0_ADDR #ifdef CONFIG_SOC_AU1200 #define UART_DEBUG_BASE UART1_ADDR #else #define UART_DEBUG_BASE UART3_ADDR #endif #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ #define UART_IER 8 /* Interrupt Enable Register */ #define UART_IIR 0xC /* Interrupt ID Register */ #define UART_FCR 0x10 /* FIFO Control Register */ #define UART_LCR 0x14 /* Line Control Register */ #define UART_MCR 0x18 /* Modem Control Register */ #define UART_LSR 0x1C /* Line Status Register */ #define UART_MSR 0x20 /* Modem Status Register */ #define UART_CLK 0x28 /* Baud Rate Clock Divider */ #define UART_MOD_CNTRL 0x100 /* Module Control */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ /* * These are the definitions for the Line Control Register */ #define UART_LCR_SBC 0x40 /* Set break control */ #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ #define UART_LCR_EPAR 0x10 /* Even parity select */ #define UART_LCR_PARITY 0x08 /* Parity Enable */ #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ /* * These are the definitions for the Line Status Register */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ #define UART_LSR_FE 0x08 /* Frame error indicator */ #define UART_LSR_PE 0x04 /* Parity error indicator */ #define UART_LSR_OE 0x02 /* Overrun error indicator */ #define UART_LSR_DR 0x01 /* Receiver data ready */ /* * These are the definitions for the Interrupt Identification Register */ #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ #define UART_IIR_MSI 0x00 /* Modem status interrupt */ #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ /* * These are the definitions for the Interrupt Enable Register */ #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ /* * These are the definitions for the Modem Control Register */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ #define UART_MCR_RTS 0x02 /* RTS complement */ #define UART_MCR_DTR 0x01 /* DTR complement */ /* * These are the definitions for the Modem Status Register */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ #define UART_MSR_RI 0x40 /* Ring Indicator */ #define UART_MSR_DSR 0x20 /* Data Set Ready */ #define UART_MSR_CTS 0x10 /* Clear to Send */ #define UART_MSR_DDCD 0x08 /* Delta DCD */ #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ #define UART_MSR_DDSR 0x02 /* Delta DSR */ #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ /* SSIO */ #define SSI0_STATUS 0xB1600000 #define SSI_STATUS_BF (1<<4) #define SSI_STATUS_OF (1<<3) #define SSI_STATUS_UF (1<<2) #define SSI_STATUS_D (1<<1) #define SSI_STATUS_B (1<<0) #define SSI0_INT 0xB1600004 #define SSI_INT_OI (1<<3) #define SSI_INT_UI (1<<2) #define SSI_INT_DI (1<<1) #define SSI0_INT_ENABLE 0xB1600008 #define SSI_INTE_OIE (1<<3) #define SSI_INTE_UIE (1<<2) #define SSI_INTE_DIE (1<<1) #define SSI0_CONFIG 0xB1600020 #define SSI_CONFIG_AO (1<<24) #define SSI_CONFIG_DO (1<<23) #define SSI_CONFIG_ALEN_BIT 20 #define SSI_CONFIG_ALEN_MASK (0x7<<20) #define SSI_CONFIG_DLEN_BIT 16 #define SSI_CONFIG_DLEN_MASK (0x7<<16) #define SSI_CONFIG_DD (1<<11) #define SSI_CONFIG_AD (1<<10) #define SSI_CONFIG_BM_BIT 8 #define SSI_CONFIG_BM_MASK (0x3<<8) #define SSI_CONFIG_CE (1<<7) #define SSI_CONFIG_DP (1<<6) #define SSI_CONFIG_DL (1<<5) #define SSI_CONFIG_EP (1<<4) #define SSI0_ADATA 0xB1600024 #define SSI_AD_D (1<<24) #define SSI_AD_ADDR_BIT 16 #define SSI_AD_ADDR_MASK (0xff<<16) #define SSI_AD_DATA_BIT 0 #define SSI_AD_DATA_MASK (0xfff<<0) #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 #define SSI_CONTROL_CD (1<<1) #define SSI_CONTROL_E (1<<0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 #define SSI1_INT 0xB1680004 #define SSI1_INT_ENABLE 0xB1680008 #define SSI1_CONFIG 0xB1680020 #define SSI1_ADATA 0xB1680024 #define SSI1_CLKDIV 0xB1680028 #define SSI1_ENABLE 0xB1680100 /* * Register content definitions */ #define SSI_STATUS_BF (1<<4) #define SSI_STATUS_OF (1<<3) #define SSI_STATUS_UF (1<<2) #define SSI_STATUS_D (1<<1) #define SSI_STATUS_B (1<<0) /* SSI_INT */ #define SSI_INT_OI (1<<3) #define SSI_INT_UI (1<<2) #define SSI_INT_DI (1<<1) /* SSI_INTEN */ #define SSI_INTEN_OIE (1<<3) #define SSI_INTEN_UIE (1<<2) #define SSI_INTEN_DIE (1<<1) #define SSI_CONFIG_AO (1<<24) #define SSI_CONFIG_DO (1<<23) #define SSI_CONFIG_ALEN (7<<20) #define SSI_CONFIG_DLEN (15<<16) #define SSI_CONFIG_DD (1<<11) #define SSI_CONFIG_AD (1<<10) #define SSI_CONFIG_BM (3<<8) #define SSI_CONFIG_CE (1<<7) #define SSI_CONFIG_DP (1<<6) #define SSI_CONFIG_DL (1<<5) #define SSI_CONFIG_EP (1<<4) #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) #define SSI_CONFIG_BM_HI (0<<8) #define SSI_CONFIG_BM_LO (1<<8) #define SSI_CONFIG_BM_CY (2<<8) #define SSI_ADATA_D (1<<24) #define SSI_ADATA_ADDR (0xFF<<16) #define SSI_ADATA_DATA (0x0FFF) #define SSI_ADATA_ADDR_N(N) (N<<16) #define SSI_ENABLE_CD (1<<1) #define SSI_ENABLE_E (1<<0) /* IrDA Controller */ #define IRDA_BASE 0xB0300000 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00) #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) #define IR_RING_SIZE (IRDA_BASE+0x0C) #define IR_RING_PROMPT (IRDA_BASE+0x10) #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) #define IR_INT_CLEAR (IRDA_BASE+0x18) #define IR_CONFIG_1 (IRDA_BASE+0x20) #define IR_RX_INVERT_LED (1<<0) #define IR_TX_INVERT_LED (1<<1) #define IR_ST (1<<2) #define IR_SF (1<<3) #define IR_SIR (1<<4) #define IR_MIR (1<<5) #define IR_FIR (1<<6) #define IR_16CRC (1<<7) #define IR_TD (1<<8) #define IR_RX_ALL (1<<9) #define IR_DMA_ENABLE (1<<10) #define IR_RX_ENABLE (1<<11) #define IR_TX_ENABLE (1<<12) #define IR_LOOPBACK (1<<14) #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) #define IR_SIR_FLAGS (IRDA_BASE+0x24) #define IR_ENABLE (IRDA_BASE+0x28) #define IR_RX_STATUS (1<<9) #define IR_TX_STATUS (1<<10) #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) #define IR_CONFIG_2 (IRDA_BASE+0x3C) #define IR_MODE_INV (1<<0) #define IR_ONE_PIN (1<<1) #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) /* GPIO */ #define SYS_PINFUNC 0xB190002C #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ /* Au1100 Only */ #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ /* Au1550 Only. Redefines lots of pins */ #define SYS_PF_PSC2_MASK (7 << 17) #define SYS_PF_PSC2_AC97 (0) #define SYS_PF_PSC2_SPI (0) #define SYS_PF_PSC2_I2S (1 << 17) #define SYS_PF_PSC2_SMBUS (3 << 17) #define SYS_PF_PSC2_GPIO (7 << 17) #define SYS_PF_PSC3_MASK (7 << 20) #define SYS_PF_PSC3_AC97 (0) #define SYS_PF_PSC3_SPI (0) #define SYS_PF_PSC3_I2S (1 << 20) #define SYS_PF_PSC3_SMBUS (3 << 20) #define SYS_PF_PSC3_GPIO (7 << 20) #define SYS_PF_PSC1_S1 (1 << 1) #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 Only */ #ifdef CONFIG_SOC_AU1200 #define SYS_PINFUNC_DMA (1<<31) #define SYS_PINFUNC_S0A (1<<30) #define SYS_PINFUNC_S1A (1<<29) #define SYS_PINFUNC_LP0 (1<<28) #define SYS_PINFUNC_LP1 (1<<27) #define SYS_PINFUNC_LD16 (1<<26) #define SYS_PINFUNC_LD8 (1<<25) #define SYS_PINFUNC_LD1 (1<<24) #define SYS_PINFUNC_LD0 (1<<23) #define SYS_PINFUNC_P1A (3<<21) #define SYS_PINFUNC_P1B (1<<20) #define SYS_PINFUNC_FS3 (1<<19) #define SYS_PINFUNC_P0A (3<<17) #define SYS_PINFUNC_CS (1<<16) #define SYS_PINFUNC_CIM (1<<15) #define SYS_PINFUNC_P1C (1<<14) #define SYS_PINFUNC_U1T (1<<12) #define SYS_PINFUNC_U1R (1<<11) #define SYS_PINFUNC_EX1 (1<<10) #define SYS_PINFUNC_EX0 (1<<9) #define SYS_PINFUNC_U0R (1<<8) #define SYS_PINFUNC_MC (1<<7) #define SYS_PINFUNC_S0B (1<<6) #define SYS_PINFUNC_S0C (1<<5) #define SYS_PINFUNC_P0B (1<<4) #define SYS_PINFUNC_U0T (1<<3) #define SYS_PINFUNC_S1B (1<<2) #endif #define SYS_TRIOUTRD 0xB1900100 #define SYS_TRIOUTCLR 0xB1900100 #define SYS_OUTPUTRD 0xB1900108 #define SYS_OUTPUTSET 0xB1900108 #define SYS_OUTPUTCLR 0xB190010C #define SYS_PINSTATERD 0xB1900110 #define SYS_PININPUTEN 0xB1900110 /* GPIO2, Au1500, Au1550 only */ #define GPIO2_BASE 0xB1700000 #define GPIO2_DIR (GPIO2_BASE + 0) #define GPIO2_OUTPUT (GPIO2_BASE + 8) #define GPIO2_PINSTATE (GPIO2_BASE + 0xC) #define GPIO2_INTENABLE (GPIO2_BASE + 0x10) #define GPIO2_ENABLE (GPIO2_BASE + 0x14) /* Power Management */ #define SYS_SCRATCH0 0xB1900018 #define SYS_SCRATCH1 0xB190001C #define SYS_WAKEMSK 0xB1900034 #define SYS_ENDIAN 0xB1900038 #define SYS_POWERCTRL 0xB190003C #define SYS_WAKESRC 0xB190005C #define SYS_SLPPWR 0xB1900078 #define SYS_SLEEP 0xB190007C /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 #define SYS_FC_FRDIV2_BIT 22 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) #define SYS_FC_FE2 (1<<21) #define SYS_FC_FS2 (1<<20) #define SYS_FC_FRDIV1_BIT 12 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) #define SYS_FC_FE1 (1<<11) #define SYS_FC_FS1 (1<<10) #define SYS_FC_FRDIV0_BIT 2 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) #define SYS_FC_FE0 (1<<1) #define SYS_FC_FS0 (1<<0) #define SYS_FREQCTRL1 0xB1900024 #define SYS_FC_FRDIV5_BIT 22 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) #define SYS_FC_FE5 (1<<21) #define SYS_FC_FS5 (1<<20) #define SYS_FC_FRDIV4_BIT 12 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) #define SYS_FC_FE4 (1<<11) #define SYS_FC_FS4 (1<<10) #define SYS_FC_FRDIV3_BIT 2 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) #define SYS_FC_FE3 (1<<1) #define SYS_FC_FS3 (1<<0) #define SYS_CLKSRC 0xB1900028 #define SYS_CS_ME1_BIT 27 #define SYS_CS_ME1_MASK (0x7<= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ _ctl_; }) #else /* Au1000 and Au1100 and Au1200 */ /* don't allow any legacy ports probing */ #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff #define PCI_IO_START 0 #define PCI_IO_END 0 #define PCI_MEM_START 0 #define PCI_MEM_END 0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN 0 #endif #ifndef _LANGUAGE_ASSEMBLY typedef volatile struct { /* 0x0000 */ u32 toytrim; /* 0x0004 */ u32 toywrite; /* 0x0008 */ u32 toymatch0; /* 0x000C */ u32 toymatch1; /* 0x0010 */ u32 toymatch2; /* 0x0014 */ u32 cntrctrl; /* 0x0018 */ u32 scratch0; /* 0x001C */ u32 scratch1; /* 0x0020 */ u32 freqctrl0; /* 0x0024 */ u32 freqctrl1; /* 0x0028 */ u32 clksrc; /* 0x002C */ u32 pinfunc; /* 0x0030 */ u32 reserved0; /* 0x0034 */ u32 wakemsk; /* 0x0038 */ u32 endian; /* 0x003C */ u32 powerctrl; /* 0x0040 */ u32 toyread; /* 0x0044 */ u32 rtctrim; /* 0x0048 */ u32 rtcwrite; /* 0x004C */ u32 rtcmatch0; /* 0x0050 */ u32 rtcmatch1; /* 0x0054 */ u32 rtcmatch2; /* 0x0058 */ u32 rtcread; /* 0x005C */ u32 wakesrc; /* 0x0060 */ u32 cpupll; /* 0x0064 */ u32 auxpll; /* 0x0068 */ u32 reserved1; /* 0x006C */ u32 reserved2; /* 0x0070 */ u32 reserved3; /* 0x0074 */ u32 reserved4; /* 0x0078 */ u32 slppwr; /* 0x007C */ u32 sleep; /* 0x0080 */ u32 reserved5[32]; /* 0x0100 */ u32 trioutrd; #define trioutclr trioutrd /* 0x0104 */ u32 reserved6; /* 0x0108 */ u32 outputrd; #define outputset outputrd /* 0x010C */ u32 outputclr; /* 0x0110 */ u32 pinstaterd; #define pininputen pinstaterd } AU1X00_SYS; static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; #endif /* Processor information base on prid. * Copied from PowerPC. */ #ifndef _LANGUAGE_ASSEMBLY struct cpu_spec { /* CPU is matched via (PRID & prid_mask) == prid_value */ unsigned int prid_mask; unsigned int prid_value; char *cpu_name; unsigned char cpu_od; /* Set Config[OD] */ unsigned char cpu_bclk; /* Enable BCLK switching */ }; extern struct cpu_spec cpu_specs[]; extern struct cpu_spec *cur_cpu_spec[]; #endif #endif