[
    {
        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.RD",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x3",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.WR",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0xC",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Memory controller clock ticks. Derived from unc_m_clockticks",
        "Counter": "0,1,2,3",
        "EventName": "UNC_M_CLOCKTICKS",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode. Derived from unc_m_power_channel_ppd",
        "Counter": "0,1,2,3",
        "EventCode": "0x85",
        "EventName": "UNC_M_POWER_CHANNEL_PPD",
        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles all ranks are in critical thermal throttle. Derived from unc_m_power_critical_throttle_cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x86",
        "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
        "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles Memory is in self refresh power mode. Derived from unc_m_power_self_refresh",
        "Counter": "0,1,2,3",
        "EventCode": "0x43",
        "EventName": "UNC_M_POWER_SELF_REFRESH",
        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charges due to page misses. Derived from unc_m_pre_count.page_miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charge for reads. Derived from unc_m_pre_count.rd",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_M_PRE_COUNT.RD",
        "PerPkg": "1",
        "UMask": "0x4",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charge for writes. Derived from unc_m_pre_count.wr",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_M_PRE_COUNT.WR",
        "PerPkg": "1",
        "UMask": "0x8",
        "Unit": "iMC"
    }
]