{
	"or32 reg zero extend check",
	.insns = {
	BPF_MOV64_IMM(BPF_REG_0, -1),
	BPF_MOV64_IMM(BPF_REG_2, -2),
	BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2),
	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
	BPF_EXIT_INSN(),
	},
	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
	.result = ACCEPT,
	.retval = 0,
},
{
	"and32 reg zero extend check",
	.insns = {
	BPF_MOV64_IMM(BPF_REG_0, -1),
	BPF_MOV64_IMM(BPF_REG_2, -2),
	BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2),
	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
	BPF_EXIT_INSN(),
	},
	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
	.result = ACCEPT,
	.retval = 0,
},
{
	"xor32 reg zero extend check",
	.insns = {
	BPF_MOV64_IMM(BPF_REG_0, -1),
	BPF_MOV64_IMM(BPF_REG_2, 0),
	BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2),
	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
	BPF_EXIT_INSN(),
	},
	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
	.result = ACCEPT,
	.retval = 0,
},